Mercurial > hg > truffle
annotate src/cpu/x86/vm/assembler_x86.cpp @ 7476:ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
Reviewed-by: jrose, kvn, twisti
Contributed-by: Morris Meyer <morris.meyer@oracle.com>
| author | twisti |
|---|---|
| date | Mon, 07 Jan 2013 14:08:28 -0800 |
| parents | e2e6bf86682c |
| children | 038dd2875b94 |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/assembler.hpp" |
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27 #include "asm/assembler.inline.hpp" |
| 1972 | 28 #include "gc_interface/collectedHeap.inline.hpp" |
| 29 #include "interpreter/interpreter.hpp" | |
| 30 #include "memory/cardTableModRefBS.hpp" | |
| 31 #include "memory/resourceArea.hpp" | |
| 32 #include "prims/methodHandles.hpp" | |
| 33 #include "runtime/biasedLocking.hpp" | |
| 34 #include "runtime/interfaceSupport.hpp" | |
| 35 #include "runtime/objectMonitor.hpp" | |
| 36 #include "runtime/os.hpp" | |
| 37 #include "runtime/sharedRuntime.hpp" | |
| 38 #include "runtime/stubRoutines.hpp" | |
| 39 #ifndef SERIALGC | |
| 40 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" | |
| 41 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" | |
| 42 #include "gc_implementation/g1/heapRegion.hpp" | |
| 43 #endif | |
| 0 | 44 |
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45 #ifdef PRODUCT |
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46 #define BLOCK_COMMENT(str) /* nothing */ |
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47 #define STOP(error) stop(error) |
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48 #else |
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49 #define BLOCK_COMMENT(str) block_comment(str) |
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50 #define STOP(error) block_comment(error); stop(error) |
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51 #endif |
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52 |
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53 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") |
| 0 | 54 // Implementation of AddressLiteral |
| 55 | |
| 56 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { | |
| 57 _is_lval = false; | |
| 58 _target = target; | |
| 59 switch (rtype) { | |
| 60 case relocInfo::oop_type: | |
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61 case relocInfo::metadata_type: |
| 0 | 62 // Oops are a special case. Normally they would be their own section |
| 63 // but in cases like icBuffer they are literals in the code stream that | |
| 64 // we don't have a section for. We use none so that we get a literal address | |
| 65 // which is always patchable. | |
| 66 break; | |
| 67 case relocInfo::external_word_type: | |
| 68 _rspec = external_word_Relocation::spec(target); | |
| 69 break; | |
| 70 case relocInfo::internal_word_type: | |
| 71 _rspec = internal_word_Relocation::spec(target); | |
| 72 break; | |
| 73 case relocInfo::opt_virtual_call_type: | |
| 74 _rspec = opt_virtual_call_Relocation::spec(); | |
| 75 break; | |
| 76 case relocInfo::static_call_type: | |
| 77 _rspec = static_call_Relocation::spec(); | |
| 78 break; | |
| 79 case relocInfo::runtime_call_type: | |
| 80 _rspec = runtime_call_Relocation::spec(); | |
| 81 break; | |
| 82 case relocInfo::poll_type: | |
| 83 case relocInfo::poll_return_type: | |
| 84 _rspec = Relocation::spec_simple(rtype); | |
| 85 break; | |
| 86 case relocInfo::none: | |
| 87 break; | |
| 88 default: | |
| 89 ShouldNotReachHere(); | |
| 90 break; | |
| 91 } | |
| 92 } | |
| 93 | |
| 94 // Implementation of Address | |
| 95 | |
| 304 | 96 #ifdef _LP64 |
| 97 | |
| 0 | 98 Address Address::make_array(ArrayAddress adr) { |
| 99 // Not implementable on 64bit machines | |
| 100 // Should have been handled higher up the call chain. | |
| 101 ShouldNotReachHere(); | |
| 304 | 102 return Address(); |
| 103 } | |
| 104 | |
| 105 // exceedingly dangerous constructor | |
| 106 Address::Address(int disp, address loc, relocInfo::relocType rtype) { | |
| 107 _base = noreg; | |
| 108 _index = noreg; | |
| 109 _scale = no_scale; | |
| 110 _disp = disp; | |
| 111 switch (rtype) { | |
| 112 case relocInfo::external_word_type: | |
| 113 _rspec = external_word_Relocation::spec(loc); | |
| 114 break; | |
| 115 case relocInfo::internal_word_type: | |
| 116 _rspec = internal_word_Relocation::spec(loc); | |
| 117 break; | |
| 118 case relocInfo::runtime_call_type: | |
| 119 // HMM | |
| 120 _rspec = runtime_call_Relocation::spec(); | |
| 121 break; | |
| 122 case relocInfo::poll_type: | |
| 123 case relocInfo::poll_return_type: | |
| 124 _rspec = Relocation::spec_simple(rtype); | |
| 125 break; | |
| 126 case relocInfo::none: | |
| 127 break; | |
| 128 default: | |
| 129 ShouldNotReachHere(); | |
| 130 } | |
| 131 } | |
| 132 #else // LP64 | |
| 133 | |
| 134 Address Address::make_array(ArrayAddress adr) { | |
| 0 | 135 AddressLiteral base = adr.base(); |
| 136 Address index = adr.index(); | |
| 137 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
| 138 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); | |
| 139 array._rspec = base._rspec; | |
| 140 return array; | |
| 304 | 141 } |
| 0 | 142 |
| 143 // exceedingly dangerous constructor | |
| 144 Address::Address(address loc, RelocationHolder spec) { | |
| 145 _base = noreg; | |
| 146 _index = noreg; | |
| 147 _scale = no_scale; | |
| 148 _disp = (intptr_t) loc; | |
| 149 _rspec = spec; | |
| 150 } | |
| 304 | 151 |
| 0 | 152 #endif // _LP64 |
| 153 | |
| 304 | 154 |
| 155 | |
| 0 | 156 // Convert the raw encoding form into the form expected by the constructor for |
| 157 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
| 158 // that to noreg for the Address constructor. | |
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159 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) { |
| 624 | 160 RelocationHolder rspec; |
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161 if (disp_reloc != relocInfo::none) { |
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162 rspec = Relocation::spec_simple(disp_reloc); |
| 624 | 163 } |
| 0 | 164 bool valid_index = index != rsp->encoding(); |
| 165 if (valid_index) { | |
| 166 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); | |
| 624 | 167 madr._rspec = rspec; |
| 0 | 168 return madr; |
| 169 } else { | |
| 170 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); | |
| 624 | 171 madr._rspec = rspec; |
| 0 | 172 return madr; |
| 173 } | |
| 174 } | |
| 175 | |
| 176 // Implementation of Assembler | |
| 177 | |
| 178 int AbstractAssembler::code_fill_byte() { | |
| 179 return (u_char)'\xF4'; // hlt | |
| 180 } | |
| 181 | |
| 182 // make this go away someday | |
| 183 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { | |
| 184 if (rtype == relocInfo::none) | |
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185 emit_int32(data); |
| 0 | 186 else emit_data(data, Relocation::spec_simple(rtype), format); |
| 187 } | |
| 188 | |
| 189 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { | |
| 304 | 190 assert(imm_operand == 0, "default format must be immediate in this file"); |
| 0 | 191 assert(inst_mark() != NULL, "must be inside InstructionMark"); |
| 192 if (rspec.type() != relocInfo::none) { | |
| 193 #ifdef ASSERT | |
| 194 check_relocation(rspec, format); | |
| 195 #endif | |
| 196 // Do not use AbstractAssembler::relocate, which is not intended for | |
| 197 // embedded words. Instead, relocate to the enclosing instruction. | |
| 198 | |
| 199 // hack. call32 is too wide for mask so use disp32 | |
| 200 if (format == call32_operand) | |
| 201 code_section()->relocate(inst_mark(), rspec, disp32_operand); | |
| 202 else | |
| 203 code_section()->relocate(inst_mark(), rspec, format); | |
| 204 } | |
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205 emit_int32(data); |
| 0 | 206 } |
| 207 | |
| 304 | 208 static int encode(Register r) { |
| 209 int enc = r->encoding(); | |
| 210 if (enc >= 8) { | |
| 211 enc -= 8; | |
| 212 } | |
| 213 return enc; | |
| 214 } | |
| 215 | |
| 216 static int encode(XMMRegister r) { | |
| 217 int enc = r->encoding(); | |
| 218 if (enc >= 8) { | |
| 219 enc -= 8; | |
| 220 } | |
| 221 return enc; | |
| 222 } | |
| 0 | 223 |
| 224 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { | |
| 225 assert(dst->has_byte_register(), "must have byte register"); | |
| 226 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
| 227 assert(isByte(imm8), "not a byte"); | |
| 228 assert((op1 & 0x01) == 0, "should be 8bit operation"); | |
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229 emit_int8(op1); |
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230 emit_int8(op2 | encode(dst)); |
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231 emit_int8(imm8); |
| 0 | 232 } |
| 233 | |
| 234 | |
| 304 | 235 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { |
| 0 | 236 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
| 237 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
| 238 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 239 if (is8bit(imm32)) { | |
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240 emit_int8(op1 | 0x02); // set sign bit |
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241 emit_int8(op2 | encode(dst)); |
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242 emit_int8(imm32 & 0xFF); |
| 0 | 243 } else { |
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244 emit_int8(op1); |
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245 emit_int8(op2 | encode(dst)); |
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246 emit_int32(imm32); |
| 0 | 247 } |
| 248 } | |
| 249 | |
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250 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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251 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { |
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252 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
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253 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
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254 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); |
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255 emit_int8(op1); |
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256 emit_int8(op2 | encode(dst)); |
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257 emit_int32(imm32); |
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258 } |
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259 |
| 0 | 260 // immediate-to-memory forms |
| 304 | 261 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { |
| 0 | 262 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
| 263 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 264 if (is8bit(imm32)) { | |
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265 emit_int8(op1 | 0x02); // set sign bit |
| 304 | 266 emit_operand(rm, adr, 1); |
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267 emit_int8(imm32 & 0xFF); |
| 0 | 268 } else { |
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269 emit_int8(op1); |
| 304 | 270 emit_operand(rm, adr, 4); |
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271 emit_int32(imm32); |
| 0 | 272 } |
| 273 } | |
| 274 | |
| 275 | |
| 276 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { | |
| 277 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
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278 emit_int8(op1); |
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279 emit_int8(op2 | encode(dst) << 3 | encode(src)); |
| 304 | 280 } |
| 281 | |
| 282 | |
| 283 void Assembler::emit_operand(Register reg, Register base, Register index, | |
| 284 Address::ScaleFactor scale, int disp, | |
| 285 RelocationHolder const& rspec, | |
| 286 int rip_relative_correction) { | |
| 0 | 287 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); |
| 304 | 288 |
| 289 // Encode the registers as needed in the fields they are used in | |
| 290 | |
| 291 int regenc = encode(reg) << 3; | |
| 292 int indexenc = index->is_valid() ? encode(index) << 3 : 0; | |
| 293 int baseenc = base->is_valid() ? encode(base) : 0; | |
| 294 | |
| 0 | 295 if (base->is_valid()) { |
| 296 if (index->is_valid()) { | |
| 297 assert(scale != Address::no_scale, "inconsistent address"); | |
| 298 // [base + index*scale + disp] | |
| 304 | 299 if (disp == 0 && rtype == relocInfo::none && |
| 300 base != rbp LP64_ONLY(&& base != r13)) { | |
| 0 | 301 // [base + index*scale] |
| 302 // [00 reg 100][ss index base] | |
| 303 assert(index != rsp, "illegal addressing mode"); | |
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304 emit_int8(0x04 | regenc); |
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305 emit_int8(scale << 6 | indexenc | baseenc); |
| 0 | 306 } else if (is8bit(disp) && rtype == relocInfo::none) { |
| 307 // [base + index*scale + imm8] | |
| 308 // [01 reg 100][ss index base] imm8 | |
| 309 assert(index != rsp, "illegal addressing mode"); | |
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310 emit_int8(0x44 | regenc); |
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311 emit_int8(scale << 6 | indexenc | baseenc); |
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312 emit_int8(disp & 0xFF); |
| 0 | 313 } else { |
| 304 | 314 // [base + index*scale + disp32] |
| 315 // [10 reg 100][ss index base] disp32 | |
| 0 | 316 assert(index != rsp, "illegal addressing mode"); |
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317 emit_int8(0x84 | regenc); |
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318 emit_int8(scale << 6 | indexenc | baseenc); |
| 0 | 319 emit_data(disp, rspec, disp32_operand); |
| 320 } | |
| 304 | 321 } else if (base == rsp LP64_ONLY(|| base == r12)) { |
| 322 // [rsp + disp] | |
| 0 | 323 if (disp == 0 && rtype == relocInfo::none) { |
| 304 | 324 // [rsp] |
| 0 | 325 // [00 reg 100][00 100 100] |
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326 emit_int8(0x04 | regenc); |
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327 emit_int8(0x24); |
| 0 | 328 } else if (is8bit(disp) && rtype == relocInfo::none) { |
| 304 | 329 // [rsp + imm8] |
| 330 // [01 reg 100][00 100 100] disp8 | |
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331 emit_int8(0x44 | regenc); |
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332 emit_int8(0x24); |
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333 emit_int8(disp & 0xFF); |
| 0 | 334 } else { |
| 304 | 335 // [rsp + imm32] |
| 336 // [10 reg 100][00 100 100] disp32 | |
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337 emit_int8(0x84 | regenc); |
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338 emit_int8(0x24); |
| 0 | 339 emit_data(disp, rspec, disp32_operand); |
| 340 } | |
| 341 } else { | |
| 342 // [base + disp] | |
| 304 | 343 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); |
| 344 if (disp == 0 && rtype == relocInfo::none && | |
| 345 base != rbp LP64_ONLY(&& base != r13)) { | |
| 0 | 346 // [base] |
| 347 // [00 reg base] | |
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348 emit_int8(0x00 | regenc | baseenc); |
| 0 | 349 } else if (is8bit(disp) && rtype == relocInfo::none) { |
| 304 | 350 // [base + disp8] |
| 351 // [01 reg base] disp8 | |
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352 emit_int8(0x40 | regenc | baseenc); |
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353 emit_int8(disp & 0xFF); |
| 0 | 354 } else { |
| 304 | 355 // [base + disp32] |
| 356 // [10 reg base] disp32 | |
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357 emit_int8(0x80 | regenc | baseenc); |
| 0 | 358 emit_data(disp, rspec, disp32_operand); |
| 359 } | |
| 360 } | |
| 361 } else { | |
| 362 if (index->is_valid()) { | |
| 363 assert(scale != Address::no_scale, "inconsistent address"); | |
| 364 // [index*scale + disp] | |
| 304 | 365 // [00 reg 100][ss index 101] disp32 |
| 0 | 366 assert(index != rsp, "illegal addressing mode"); |
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367 emit_int8(0x04 | regenc); |
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368 emit_int8(scale << 6 | indexenc | 0x05); |
| 0 | 369 emit_data(disp, rspec, disp32_operand); |
| 304 | 370 } else if (rtype != relocInfo::none ) { |
| 371 // [disp] (64bit) RIP-RELATIVE (32bit) abs | |
| 372 // [00 000 101] disp32 | |
| 373 | |
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374 emit_int8(0x05 | regenc); |
| 304 | 375 // Note that the RIP-rel. correction applies to the generated |
| 376 // disp field, but _not_ to the target address in the rspec. | |
| 377 | |
| 378 // disp was created by converting the target address minus the pc | |
| 379 // at the start of the instruction. That needs more correction here. | |
| 380 // intptr_t disp = target - next_ip; | |
| 381 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
| 382 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; | |
| 383 int64_t adjusted = disp; | |
| 384 // Do rip-rel adjustment for 64bit | |
| 385 LP64_ONLY(adjusted -= (next_ip - inst_mark())); | |
| 386 assert(is_simm32(adjusted), | |
| 387 "must be 32bit offset (RIP relative address)"); | |
| 388 emit_data((int32_t) adjusted, rspec, disp32_operand); | |
| 389 | |
| 0 | 390 } else { |
| 304 | 391 // 32bit never did this, did everything as the rip-rel/disp code above |
| 392 // [disp] ABSOLUTE | |
| 393 // [00 reg 100][00 100 101] disp32 | |
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394 emit_int8(0x04 | regenc); |
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395 emit_int8(0x25); |
| 0 | 396 emit_data(disp, rspec, disp32_operand); |
| 397 } | |
| 398 } | |
| 399 } | |
| 400 | |
| 304 | 401 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, |
| 402 Address::ScaleFactor scale, int disp, | |
| 403 RelocationHolder const& rspec) { | |
| 404 emit_operand((Register)reg, base, index, scale, disp, rspec); | |
| 405 } | |
| 406 | |
| 0 | 407 // Secret local extension to Assembler::WhichOperand: |
| 408 #define end_pc_operand (_WhichOperand_limit) | |
| 409 | |
| 410 address Assembler::locate_operand(address inst, WhichOperand which) { | |
| 411 // Decode the given instruction, and return the address of | |
| 412 // an embedded 32-bit operand word. | |
| 413 | |
| 414 // If "which" is disp32_operand, selects the displacement portion | |
| 415 // of an effective address specifier. | |
| 304 | 416 // If "which" is imm64_operand, selects the trailing immediate constant. |
| 0 | 417 // If "which" is call32_operand, selects the displacement of a call or jump. |
| 418 // Caller is responsible for ensuring that there is such an operand, | |
| 304 | 419 // and that it is 32/64 bits wide. |
| 0 | 420 |
| 421 // If "which" is end_pc_operand, find the end of the instruction. | |
| 422 | |
| 423 address ip = inst; | |
| 304 | 424 bool is_64bit = false; |
| 425 | |
| 426 debug_only(bool has_disp32 = false); | |
| 427 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn | |
| 428 | |
| 429 again_after_prefix: | |
| 0 | 430 switch (0xFF & *ip++) { |
| 431 | |
| 432 // These convenience macros generate groups of "case" labels for the switch. | |
| 304 | 433 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 |
| 434 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ | |
| 0 | 435 case (x)+4: case (x)+5: case (x)+6: case (x)+7 |
| 304 | 436 #define REP16(x) REP8((x)+0): \ |
| 0 | 437 case REP8((x)+8) |
| 438 | |
| 439 case CS_segment: | |
| 440 case SS_segment: | |
| 441 case DS_segment: | |
| 442 case ES_segment: | |
| 443 case FS_segment: | |
| 444 case GS_segment: | |
| 304 | 445 // Seems dubious |
| 446 LP64_ONLY(assert(false, "shouldn't have that prefix")); | |
| 0 | 447 assert(ip == inst+1, "only one prefix allowed"); |
| 448 goto again_after_prefix; | |
| 449 | |
| 304 | 450 case 0x67: |
| 451 case REX: | |
| 452 case REX_B: | |
| 453 case REX_X: | |
| 454 case REX_XB: | |
| 455 case REX_R: | |
| 456 case REX_RB: | |
| 457 case REX_RX: | |
| 458 case REX_RXB: | |
| 459 NOT_LP64(assert(false, "64bit prefixes")); | |
| 460 goto again_after_prefix; | |
| 461 | |
| 462 case REX_W: | |
| 463 case REX_WB: | |
| 464 case REX_WX: | |
| 465 case REX_WXB: | |
| 466 case REX_WR: | |
| 467 case REX_WRB: | |
| 468 case REX_WRX: | |
| 469 case REX_WRXB: | |
| 470 NOT_LP64(assert(false, "64bit prefixes")); | |
| 471 is_64bit = true; | |
| 472 goto again_after_prefix; | |
| 473 | |
| 474 case 0xFF: // pushq a; decl a; incl a; call a; jmp a | |
| 0 | 475 case 0x88: // movb a, r |
| 476 case 0x89: // movl a, r | |
| 477 case 0x8A: // movb r, a | |
| 478 case 0x8B: // movl r, a | |
| 479 case 0x8F: // popl a | |
| 304 | 480 debug_only(has_disp32 = true); |
| 0 | 481 break; |
| 482 | |
| 304 | 483 case 0x68: // pushq #32 |
| 484 if (which == end_pc_operand) { | |
| 485 return ip + 4; | |
| 486 } | |
| 487 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); | |
| 0 | 488 return ip; // not produced by emit_operand |
| 489 | |
| 490 case 0x66: // movw ... (size prefix) | |
| 304 | 491 again_after_size_prefix2: |
| 0 | 492 switch (0xFF & *ip++) { |
| 304 | 493 case REX: |
| 494 case REX_B: | |
| 495 case REX_X: | |
| 496 case REX_XB: | |
| 497 case REX_R: | |
| 498 case REX_RB: | |
| 499 case REX_RX: | |
| 500 case REX_RXB: | |
| 501 case REX_W: | |
| 502 case REX_WB: | |
| 503 case REX_WX: | |
| 504 case REX_WXB: | |
| 505 case REX_WR: | |
| 506 case REX_WRB: | |
| 507 case REX_WRX: | |
| 508 case REX_WRXB: | |
| 509 NOT_LP64(assert(false, "64bit prefix found")); | |
| 510 goto again_after_size_prefix2; | |
| 0 | 511 case 0x8B: // movw r, a |
| 512 case 0x89: // movw a, r | |
| 304 | 513 debug_only(has_disp32 = true); |
| 0 | 514 break; |
| 515 case 0xC7: // movw a, #16 | |
| 304 | 516 debug_only(has_disp32 = true); |
| 0 | 517 tail_size = 2; // the imm16 |
| 518 break; | |
| 519 case 0x0F: // several SSE/SSE2 variants | |
| 520 ip--; // reparse the 0x0F | |
| 521 goto again_after_prefix; | |
| 522 default: | |
| 523 ShouldNotReachHere(); | |
| 524 } | |
| 525 break; | |
| 526 | |
| 304 | 527 case REP8(0xB8): // movl/q r, #32/#64(oop?) |
| 528 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); | |
| 529 // these asserts are somewhat nonsensical | |
| 530 #ifndef _LP64 | |
| 5984 | 531 assert(which == imm_operand || which == disp32_operand, |
| 532 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip)); | |
| 304 | 533 #else |
| 534 assert((which == call32_operand || which == imm_operand) && is_64bit || | |
| 5984 | 535 which == narrow_oop_operand && !is_64bit, |
| 536 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip)); | |
| 304 | 537 #endif // _LP64 |
| 0 | 538 return ip; |
| 539 | |
| 540 case 0x69: // imul r, a, #32 | |
| 541 case 0xC7: // movl a, #32(oop?) | |
| 542 tail_size = 4; | |
| 304 | 543 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 544 break; |
| 545 | |
| 546 case 0x0F: // movx..., etc. | |
| 547 switch (0xFF & *ip++) { | |
| 4759 | 548 case 0x3A: // pcmpestri |
| 549 tail_size = 1; | |
| 550 case 0x38: // ptest, pmovzxbw | |
| 551 ip++; // skip opcode | |
| 552 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 553 break; | |
| 554 | |
| 555 case 0x70: // pshufd r, r/a, #8 | |
| 556 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 557 case 0x73: // psrldq r, #8 | |
| 558 tail_size = 1; | |
| 559 break; | |
| 560 | |
| 0 | 561 case 0x12: // movlps |
| 562 case 0x28: // movaps | |
| 563 case 0x2E: // ucomiss | |
| 564 case 0x2F: // comiss | |
| 565 case 0x54: // andps | |
| 566 case 0x55: // andnps | |
| 567 case 0x56: // orps | |
| 568 case 0x57: // xorps | |
| 569 case 0x6E: // movd | |
| 570 case 0x7E: // movd | |
| 4759 | 571 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush |
| 304 | 572 debug_only(has_disp32 = true); |
| 0 | 573 break; |
| 574 | |
| 575 case 0xAD: // shrd r, a, %cl | |
| 576 case 0xAF: // imul r, a | |
| 304 | 577 case 0xBE: // movsbl r, a (movsxb) |
| 578 case 0xBF: // movswl r, a (movsxw) | |
| 579 case 0xB6: // movzbl r, a (movzxb) | |
| 580 case 0xB7: // movzwl r, a (movzxw) | |
| 0 | 581 case REP16(0x40): // cmovl cc, r, a |
| 582 case 0xB0: // cmpxchgb | |
| 583 case 0xB1: // cmpxchg | |
| 584 case 0xC1: // xaddl | |
| 585 case 0xC7: // cmpxchg8 | |
| 586 case REP16(0x90): // setcc a | |
| 304 | 587 debug_only(has_disp32 = true); |
| 0 | 588 // fall out of the switch to decode the address |
| 589 break; | |
| 304 | 590 |
| 4759 | 591 case 0xC4: // pinsrw r, a, #8 |
| 592 debug_only(has_disp32 = true); | |
| 593 case 0xC5: // pextrw r, r, #8 | |
| 594 tail_size = 1; // the imm8 | |
| 595 break; | |
| 596 | |
| 0 | 597 case 0xAC: // shrd r, a, #8 |
| 304 | 598 debug_only(has_disp32 = true); |
| 0 | 599 tail_size = 1; // the imm8 |
| 600 break; | |
| 304 | 601 |
| 0 | 602 case REP16(0x80): // jcc rdisp32 |
| 603 if (which == end_pc_operand) return ip + 4; | |
| 304 | 604 assert(which == call32_operand, "jcc has no disp32 or imm"); |
| 0 | 605 return ip; |
| 606 default: | |
| 607 ShouldNotReachHere(); | |
| 608 } | |
| 609 break; | |
| 610 | |
| 611 case 0x81: // addl a, #32; addl r, #32 | |
| 612 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
| 304 | 613 // on 32bit in the case of cmpl, the imm might be an oop |
| 0 | 614 tail_size = 4; |
| 304 | 615 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 616 break; |
| 617 | |
| 618 case 0x83: // addl a, #8; addl r, #8 | |
| 619 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
| 304 | 620 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 621 tail_size = 1; |
| 622 break; | |
| 623 | |
| 624 case 0x9B: | |
| 625 switch (0xFF & *ip++) { | |
| 626 case 0xD9: // fnstcw a | |
| 304 | 627 debug_only(has_disp32 = true); |
| 0 | 628 break; |
| 629 default: | |
| 630 ShouldNotReachHere(); | |
| 631 } | |
| 632 break; | |
| 633 | |
| 634 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a | |
| 635 case REP4(0x10): // adc... | |
| 636 case REP4(0x20): // and... | |
| 637 case REP4(0x30): // xor... | |
| 638 case REP4(0x08): // or... | |
| 639 case REP4(0x18): // sbb... | |
| 640 case REP4(0x28): // sub... | |
| 304 | 641 case 0xF7: // mull a |
| 642 case 0x8D: // lea r, a | |
| 643 case 0x87: // xchg r, a | |
| 0 | 644 case REP4(0x38): // cmp... |
| 304 | 645 case 0x85: // test r, a |
| 646 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 0 | 647 break; |
| 648 | |
| 649 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 | |
| 650 case 0xC6: // movb a, #8 | |
| 651 case 0x80: // cmpb a, #8 | |
| 652 case 0x6B: // imul r, a, #8 | |
| 304 | 653 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 654 tail_size = 1; // the imm8 |
| 655 break; | |
| 656 | |
| 4759 | 657 case 0xC4: // VEX_3bytes |
| 658 case 0xC5: // VEX_2bytes | |
| 659 assert((UseAVX > 0), "shouldn't have VEX prefix"); | |
| 660 assert(ip == inst+1, "no prefixes allowed"); | |
| 661 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions | |
| 662 // but they have prefix 0x0F and processed when 0x0F processed above. | |
| 663 // | |
| 664 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES | |
| 665 // instructions (these instructions are not supported in 64-bit mode). | |
| 666 // To distinguish them bits [7:6] are set in the VEX second byte since | |
| 667 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set | |
| 668 // those VEX bits REX and vvvv bits are inverted. | |
| 669 // | |
| 670 // Fortunately C2 doesn't generate these instructions so we don't need | |
| 671 // to check for them in product version. | |
| 672 | |
| 673 // Check second byte | |
| 674 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); | |
| 675 | |
| 676 // First byte | |
| 677 if ((0xFF & *inst) == VEX_3bytes) { | |
| 678 ip++; // third byte | |
| 679 is_64bit = ((VEX_W & *ip) == VEX_W); | |
| 680 } | |
| 681 ip++; // opcode | |
| 682 // To find the end of instruction (which == end_pc_operand). | |
| 683 switch (0xFF & *ip) { | |
| 684 case 0x61: // pcmpestri r, r/a, #8 | |
| 685 case 0x70: // pshufd r, r/a, #8 | |
| 686 case 0x73: // psrldq r, #8 | |
| 687 tail_size = 1; // the imm8 | |
| 688 break; | |
| 689 default: | |
| 690 break; | |
| 691 } | |
| 692 ip++; // skip opcode | |
| 693 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 694 break; | |
| 0 | 695 |
| 696 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | |
| 697 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | |
| 698 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | |
| 699 case 0xDD: // fld_d a; fst_d a; fstp_d a | |
| 700 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a | |
| 701 case 0xDF: // fild_d a; fistp_d a | |
| 702 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | |
| 703 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | |
| 704 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | |
| 304 | 705 debug_only(has_disp32 = true); |
| 0 | 706 break; |
| 707 | |
| 4759 | 708 case 0xE8: // call rdisp32 |
| 709 case 0xE9: // jmp rdisp32 | |
| 710 if (which == end_pc_operand) return ip + 4; | |
| 711 assert(which == call32_operand, "call has no disp32 or imm"); | |
| 712 return ip; | |
| 713 | |
|
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714 case 0xF0: // Lock |
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715 assert(os::is_MP(), "only on MP"); |
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716 goto again_after_prefix; |
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717 |
| 0 | 718 case 0xF3: // For SSE |
| 719 case 0xF2: // For SSE2 | |
| 304 | 720 switch (0xFF & *ip++) { |
| 721 case REX: | |
| 722 case REX_B: | |
| 723 case REX_X: | |
| 724 case REX_XB: | |
| 725 case REX_R: | |
| 726 case REX_RB: | |
| 727 case REX_RX: | |
| 728 case REX_RXB: | |
| 729 case REX_W: | |
| 730 case REX_WB: | |
| 731 case REX_WX: | |
| 732 case REX_WXB: | |
| 733 case REX_WR: | |
| 734 case REX_WRB: | |
| 735 case REX_WRX: | |
| 736 case REX_WRXB: | |
| 737 NOT_LP64(assert(false, "found 64bit prefix")); | |
| 738 ip++; | |
| 739 default: | |
| 740 ip++; | |
| 741 } | |
| 742 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 0 | 743 break; |
| 744 | |
| 745 default: | |
| 746 ShouldNotReachHere(); | |
| 747 | |
| 304 | 748 #undef REP8 |
| 749 #undef REP16 | |
| 0 | 750 } |
| 751 | |
| 752 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); | |
| 304 | 753 #ifdef _LP64 |
| 754 assert(which != imm_operand, "instruction is not a movq reg, imm64"); | |
| 755 #else | |
| 756 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); | |
| 757 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); | |
| 758 #endif // LP64 | |
| 759 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); | |
| 0 | 760 |
| 761 // parse the output of emit_operand | |
| 762 int op2 = 0xFF & *ip++; | |
| 763 int base = op2 & 0x07; | |
| 764 int op3 = -1; | |
| 765 const int b100 = 4; | |
| 766 const int b101 = 5; | |
| 767 if (base == b100 && (op2 >> 6) != 3) { | |
| 768 op3 = 0xFF & *ip++; | |
| 769 base = op3 & 0x07; // refetch the base | |
| 770 } | |
| 771 // now ip points at the disp (if any) | |
| 772 | |
| 773 switch (op2 >> 6) { | |
| 774 case 0: | |
| 775 // [00 reg 100][ss index base] | |
| 304 | 776 // [00 reg 100][00 100 esp] |
| 0 | 777 // [00 reg base] |
| 778 // [00 reg 100][ss index 101][disp32] | |
| 779 // [00 reg 101] [disp32] | |
| 780 | |
| 781 if (base == b101) { | |
| 782 if (which == disp32_operand) | |
| 783 return ip; // caller wants the disp32 | |
| 784 ip += 4; // skip the disp32 | |
| 785 } | |
| 786 break; | |
| 787 | |
| 788 case 1: | |
| 789 // [01 reg 100][ss index base][disp8] | |
| 304 | 790 // [01 reg 100][00 100 esp][disp8] |
| 0 | 791 // [01 reg base] [disp8] |
| 792 ip += 1; // skip the disp8 | |
| 793 break; | |
| 794 | |
| 795 case 2: | |
| 796 // [10 reg 100][ss index base][disp32] | |
| 304 | 797 // [10 reg 100][00 100 esp][disp32] |
| 0 | 798 // [10 reg base] [disp32] |
| 799 if (which == disp32_operand) | |
| 800 return ip; // caller wants the disp32 | |
| 801 ip += 4; // skip the disp32 | |
| 802 break; | |
| 803 | |
| 804 case 3: | |
| 805 // [11 reg base] (not a memory addressing mode) | |
| 806 break; | |
| 807 } | |
| 808 | |
| 809 if (which == end_pc_operand) { | |
| 810 return ip + tail_size; | |
| 811 } | |
| 812 | |
| 304 | 813 #ifdef _LP64 |
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814 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); |
| 304 | 815 #else |
| 816 assert(which == imm_operand, "instruction has only an imm field"); | |
| 817 #endif // LP64 | |
| 0 | 818 return ip; |
| 819 } | |
| 820 | |
| 821 address Assembler::locate_next_instruction(address inst) { | |
| 822 // Secretly share code with locate_operand: | |
| 823 return locate_operand(inst, end_pc_operand); | |
| 824 } | |
| 825 | |
| 826 | |
| 827 #ifdef ASSERT | |
| 828 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { | |
| 829 address inst = inst_mark(); | |
| 830 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); | |
| 831 address opnd; | |
| 832 | |
| 833 Relocation* r = rspec.reloc(); | |
| 834 if (r->type() == relocInfo::none) { | |
| 835 return; | |
| 836 } else if (r->is_call() || format == call32_operand) { | |
| 837 // assert(format == imm32_operand, "cannot specify a nonzero format"); | |
| 838 opnd = locate_operand(inst, call32_operand); | |
| 839 } else if (r->is_data()) { | |
| 304 | 840 assert(format == imm_operand || format == disp32_operand |
| 841 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); | |
| 0 | 842 opnd = locate_operand(inst, (WhichOperand)format); |
| 843 } else { | |
| 304 | 844 assert(format == imm_operand, "cannot specify a format"); |
| 0 | 845 return; |
| 846 } | |
| 847 assert(opnd == pc(), "must put operand where relocs can find it"); | |
| 848 } | |
| 304 | 849 #endif // ASSERT |
| 850 | |
| 851 void Assembler::emit_operand32(Register reg, Address adr) { | |
| 852 assert(reg->encoding() < 8, "no extended registers"); | |
| 853 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 854 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 855 adr._rspec); | |
| 856 } | |
| 857 | |
| 858 void Assembler::emit_operand(Register reg, Address adr, | |
| 859 int rip_relative_correction) { | |
| 860 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 861 adr._rspec, | |
| 862 rip_relative_correction); | |
| 863 } | |
| 864 | |
| 865 void Assembler::emit_operand(XMMRegister reg, Address adr) { | |
| 866 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 867 adr._rspec); | |
| 868 } | |
| 869 | |
| 870 // MMX operations | |
| 871 void Assembler::emit_operand(MMXRegister reg, Address adr) { | |
| 872 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 873 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
| 874 } | |
| 875 | |
| 876 // work around gcc (3.2.1-7a) bug | |
| 877 void Assembler::emit_operand(Address adr, MMXRegister reg) { | |
| 878 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 879 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
| 0 | 880 } |
| 881 | |
| 882 | |
| 883 void Assembler::emit_farith(int b1, int b2, int i) { | |
| 884 assert(isByte(b1) && isByte(b2), "wrong opcode"); | |
| 885 assert(0 <= i && i < 8, "illegal stack offset"); | |
|
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886 emit_int8(b1); |
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887 emit_int8(b2 + i); |
| 0 | 888 } |
| 889 | |
| 890 | |
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891 // Now the Assembler instructions (identical for 32/64 bits) |
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892 |
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893 void Assembler::adcl(Address dst, int32_t imm32) { |
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894 InstructionMark im(this); |
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895 prefix(dst); |
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896 emit_arith_operand(0x81, rdx, dst, imm32); |
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897 } |
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898 |
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899 void Assembler::adcl(Address dst, Register src) { |
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900 InstructionMark im(this); |
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901 prefix(dst, src); |
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902 emit_int8(0x11); |
|
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903 emit_operand(src, dst); |
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904 } |
| 304 | 905 |
| 906 void Assembler::adcl(Register dst, int32_t imm32) { | |
| 907 prefix(dst); | |
| 0 | 908 emit_arith(0x81, 0xD0, dst, imm32); |
| 909 } | |
| 910 | |
| 911 void Assembler::adcl(Register dst, Address src) { | |
| 912 InstructionMark im(this); | |
| 304 | 913 prefix(src, dst); |
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914 emit_int8(0x13); |
| 0 | 915 emit_operand(dst, src); |
| 916 } | |
| 917 | |
| 918 void Assembler::adcl(Register dst, Register src) { | |
| 304 | 919 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
| 0 | 920 emit_arith(0x13, 0xC0, dst, src); |
| 921 } | |
| 922 | |
| 304 | 923 void Assembler::addl(Address dst, int32_t imm32) { |
| 924 InstructionMark im(this); | |
| 925 prefix(dst); | |
| 926 emit_arith_operand(0x81, rax, dst, imm32); | |
| 927 } | |
| 0 | 928 |
| 929 void Assembler::addl(Address dst, Register src) { | |
| 930 InstructionMark im(this); | |
| 304 | 931 prefix(dst, src); |
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932 emit_int8(0x01); |
| 0 | 933 emit_operand(src, dst); |
| 934 } | |
| 935 | |
| 304 | 936 void Assembler::addl(Register dst, int32_t imm32) { |
| 937 prefix(dst); | |
| 0 | 938 emit_arith(0x81, 0xC0, dst, imm32); |
| 939 } | |
| 940 | |
| 941 void Assembler::addl(Register dst, Address src) { | |
| 942 InstructionMark im(this); | |
| 304 | 943 prefix(src, dst); |
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944 emit_int8(0x03); |
| 0 | 945 emit_operand(dst, src); |
| 946 } | |
| 947 | |
| 948 void Assembler::addl(Register dst, Register src) { | |
| 304 | 949 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
| 0 | 950 emit_arith(0x03, 0xC0, dst, src); |
| 951 } | |
| 952 | |
| 953 void Assembler::addr_nop_4() { | |
|
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954 assert(UseAddressNop, "no CPU support"); |
| 0 | 955 // 4 bytes: NOP DWORD PTR [EAX+0] |
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956 emit_int8(0x0F); |
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957 emit_int8(0x1F); |
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958 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); |
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959 emit_int8(0); // 8-bits offset (1 byte) |
| 0 | 960 } |
| 961 | |
| 962 void Assembler::addr_nop_5() { | |
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963 assert(UseAddressNop, "no CPU support"); |
| 0 | 964 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset |
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965 emit_int8(0x0F); |
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966 emit_int8(0x1F); |
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967 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); |
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968 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); |
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969 emit_int8(0); // 8-bits offset (1 byte) |
| 0 | 970 } |
| 971 | |
| 972 void Assembler::addr_nop_7() { | |
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973 assert(UseAddressNop, "no CPU support"); |
| 0 | 974 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset |
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975 emit_int8(0x0F); |
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976 emit_int8(0x1F); |
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977 emit_int8((unsigned char)0x80); |
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978 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); |
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979 emit_int32(0); // 32-bits offset (4 bytes) |
| 0 | 980 } |
| 981 | |
| 982 void Assembler::addr_nop_8() { | |
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983 assert(UseAddressNop, "no CPU support"); |
| 0 | 984 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset |
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985 emit_int8(0x0F); |
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986 emit_int8(0x1F); |
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987 emit_int8((unsigned char)0x84); |
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988 // emit_rm(cbuf, 0x2, EAX_enc, 0x4); |
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989 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); |
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990 emit_int32(0); // 32-bits offset (4 bytes) |
| 0 | 991 } |
| 992 | |
| 304 | 993 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
| 994 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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995 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2); |
| 304 | 996 } |
| 997 | |
| 998 void Assembler::addsd(XMMRegister dst, Address src) { | |
| 999 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1000 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2); |
| 304 | 1001 } |
| 1002 | |
| 1003 void Assembler::addss(XMMRegister dst, XMMRegister src) { | |
| 1004 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1005 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3); |
| 304 | 1006 } |
| 1007 | |
| 1008 void Assembler::addss(XMMRegister dst, Address src) { | |
| 1009 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1010 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3); |
| 304 | 1011 } |
| 1012 | |
| 6894 | 1013 void Assembler::aesdec(XMMRegister dst, Address src) { |
| 1014 assert(VM_Version::supports_aes(), ""); | |
| 1015 InstructionMark im(this); | |
| 1016 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1017 emit_int8((unsigned char)0xDE); |
| 6894 | 1018 emit_operand(dst, src); |
| 1019 } | |
| 1020 | |
| 1021 void Assembler::aesdec(XMMRegister dst, XMMRegister src) { | |
| 1022 assert(VM_Version::supports_aes(), ""); | |
| 1023 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1024 emit_int8((unsigned char)0xDE); |
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1025 emit_int8(0xC0 | encode); |
| 6894 | 1026 } |
| 1027 | |
| 1028 void Assembler::aesdeclast(XMMRegister dst, Address src) { | |
| 1029 assert(VM_Version::supports_aes(), ""); | |
| 1030 InstructionMark im(this); | |
| 1031 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1032 emit_int8((unsigned char)0xDF); |
| 6894 | 1033 emit_operand(dst, src); |
| 1034 } | |
| 1035 | |
| 1036 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) { | |
| 1037 assert(VM_Version::supports_aes(), ""); | |
| 1038 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1039 emit_int8((unsigned char)0xDF); |
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1040 emit_int8((unsigned char)(0xC0 | encode)); |
| 6894 | 1041 } |
| 1042 | |
| 1043 void Assembler::aesenc(XMMRegister dst, Address src) { | |
| 1044 assert(VM_Version::supports_aes(), ""); | |
| 1045 InstructionMark im(this); | |
| 1046 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
|
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1047 emit_int8((unsigned char)0xDC); |
| 6894 | 1048 emit_operand(dst, src); |
| 1049 } | |
| 1050 | |
| 1051 void Assembler::aesenc(XMMRegister dst, XMMRegister src) { | |
| 1052 assert(VM_Version::supports_aes(), ""); | |
| 1053 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1054 emit_int8((unsigned char)0xDC); |
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1055 emit_int8(0xC0 | encode); |
| 6894 | 1056 } |
| 1057 | |
| 1058 void Assembler::aesenclast(XMMRegister dst, Address src) { | |
| 1059 assert(VM_Version::supports_aes(), ""); | |
| 1060 InstructionMark im(this); | |
| 1061 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1062 emit_int8((unsigned char)0xDD); |
| 6894 | 1063 emit_operand(dst, src); |
| 1064 } | |
| 1065 | |
| 1066 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { | |
| 1067 assert(VM_Version::supports_aes(), ""); | |
| 1068 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1069 emit_int8((unsigned char)0xDD); |
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1070 emit_int8((unsigned char)(0xC0 | encode)); |
| 6894 | 1071 } |
| 1072 | |
| 1073 | |
| 4759 | 1074 void Assembler::andl(Address dst, int32_t imm32) { |
| 1075 InstructionMark im(this); | |
| 1076 prefix(dst); | |
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1077 emit_int8((unsigned char)0x81); |
| 4759 | 1078 emit_operand(rsp, dst, 4); |
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1079 emit_int32(imm32); |
| 4759 | 1080 } |
| 1081 | |
| 304 | 1082 void Assembler::andl(Register dst, int32_t imm32) { |
| 1083 prefix(dst); | |
| 1084 emit_arith(0x81, 0xE0, dst, imm32); | |
| 1085 } | |
| 1086 | |
| 1087 void Assembler::andl(Register dst, Address src) { | |
| 1088 InstructionMark im(this); | |
| 1089 prefix(src, dst); | |
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1090 emit_int8(0x23); |
| 304 | 1091 emit_operand(dst, src); |
| 1092 } | |
| 1093 | |
| 1094 void Assembler::andl(Register dst, Register src) { | |
| 1095 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1096 emit_arith(0x23, 0xC0, dst, src); | |
| 1097 } | |
| 1098 | |
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1099 void Assembler::bsfl(Register dst, Register src) { |
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1100 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1101 emit_int8(0x0F); |
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1102 emit_int8((unsigned char)0xBC); |
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1103 emit_int8((unsigned char)(0xC0 | encode)); |
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1104 } |
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1105 |
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1106 void Assembler::bsrl(Register dst, Register src) { |
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1107 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
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1108 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1109 emit_int8(0x0F); |
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1110 emit_int8((unsigned char)0xBD); |
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1111 emit_int8((unsigned char)(0xC0 | encode)); |
|
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1112 } |
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1113 |
| 304 | 1114 void Assembler::bswapl(Register reg) { // bswap |
| 1115 int encode = prefix_and_encode(reg->encoding()); | |
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1116 emit_int8(0x0F); |
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1117 emit_int8((unsigned char)(0xC8 | encode)); |
| 304 | 1118 } |
| 1119 | |
| 1120 void Assembler::call(Label& L, relocInfo::relocType rtype) { | |
| 1121 // suspect disp32 is always good | |
| 1122 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); | |
| 1123 | |
| 1124 if (L.is_bound()) { | |
| 1125 const int long_size = 5; | |
| 1126 int offs = (int)( target(L) - pc() ); | |
| 1127 assert(offs <= 0, "assembler error"); | |
| 1128 InstructionMark im(this); | |
| 1129 // 1110 1000 #32-bit disp | |
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1130 emit_int8((unsigned char)0xE8); |
| 304 | 1131 emit_data(offs - long_size, rtype, operand); |
| 1132 } else { | |
| 1133 InstructionMark im(this); | |
| 1134 // 1110 1000 #32-bit disp | |
| 1135 L.add_patch_at(code(), locator()); | |
| 1136 | |
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1137 emit_int8((unsigned char)0xE8); |
| 304 | 1138 emit_data(int(0), rtype, operand); |
| 1139 } | |
| 1140 } | |
| 1141 | |
| 1142 void Assembler::call(Register dst) { | |
| 4759 | 1143 int encode = prefix_and_encode(dst->encoding()); |
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1144 emit_int8((unsigned char)0xFF); |
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1145 emit_int8((unsigned char)(0xD0 | encode)); |
| 304 | 1146 } |
| 1147 | |
| 1148 | |
| 1149 void Assembler::call(Address adr) { | |
| 1150 InstructionMark im(this); | |
| 1151 prefix(adr); | |
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1152 emit_int8((unsigned char)0xFF); |
| 304 | 1153 emit_operand(rdx, adr); |
| 1154 } | |
| 1155 | |
| 1156 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { | |
| 1157 assert(entry != NULL, "call most probably wrong"); | |
| 1158 InstructionMark im(this); | |
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1159 emit_int8((unsigned char)0xE8); |
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1160 intptr_t disp = entry - (pc() + sizeof(int32_t)); |
| 304 | 1161 assert(is_simm32(disp), "must be 32bit offset (call2)"); |
| 1162 // Technically, should use call32_operand, but this format is | |
| 1163 // implied by the fact that we're emitting a call instruction. | |
| 1164 | |
| 1165 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); | |
| 1166 emit_data((int) disp, rspec, operand); | |
| 1167 } | |
| 1168 | |
| 1169 void Assembler::cdql() { | |
|
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1170 emit_int8((unsigned char)0x99); |
| 304 | 1171 } |
| 1172 | |
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1173 void Assembler::cld() { |
|
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1174 emit_int8((unsigned char)0xFC); |
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1175 } |
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1176 |
| 304 | 1177 void Assembler::cmovl(Condition cc, Register dst, Register src) { |
| 1178 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
| 1179 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1180 emit_int8(0x0F); |
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1181 emit_int8(0x40 | cc); |
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1182 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 1183 } |
| 1184 | |
| 1185 | |
| 1186 void Assembler::cmovl(Condition cc, Register dst, Address src) { | |
| 1187 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
| 1188 prefix(src, dst); | |
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1189 emit_int8(0x0F); |
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1190 emit_int8(0x40 | cc); |
| 304 | 1191 emit_operand(dst, src); |
| 1192 } | |
| 1193 | |
| 1194 void Assembler::cmpb(Address dst, int imm8) { | |
| 1195 InstructionMark im(this); | |
| 1196 prefix(dst); | |
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1197 emit_int8((unsigned char)0x80); |
| 304 | 1198 emit_operand(rdi, dst, 1); |
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1199 emit_int8(imm8); |
| 304 | 1200 } |
| 1201 | |
| 1202 void Assembler::cmpl(Address dst, int32_t imm32) { | |
| 1203 InstructionMark im(this); | |
| 1204 prefix(dst); | |
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1205 emit_int8((unsigned char)0x81); |
| 304 | 1206 emit_operand(rdi, dst, 4); |
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1207 emit_int32(imm32); |
| 304 | 1208 } |
| 1209 | |
| 1210 void Assembler::cmpl(Register dst, int32_t imm32) { | |
| 1211 prefix(dst); | |
| 1212 emit_arith(0x81, 0xF8, dst, imm32); | |
| 1213 } | |
| 1214 | |
| 1215 void Assembler::cmpl(Register dst, Register src) { | |
| 1216 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1217 emit_arith(0x3B, 0xC0, dst, src); | |
| 1218 } | |
| 1219 | |
| 1220 | |
| 1221 void Assembler::cmpl(Register dst, Address src) { | |
| 1222 InstructionMark im(this); | |
| 1223 prefix(src, dst); | |
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1224 emit_int8((unsigned char)0x3B); |
| 304 | 1225 emit_operand(dst, src); |
| 1226 } | |
| 1227 | |
| 1228 void Assembler::cmpw(Address dst, int imm16) { | |
| 1229 InstructionMark im(this); | |
| 1230 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); | |
|
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1231 emit_int8(0x66); |
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1232 emit_int8((unsigned char)0x81); |
| 304 | 1233 emit_operand(rdi, dst, 2); |
|
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1234 emit_int16(imm16); |
| 304 | 1235 } |
| 1236 | |
| 1237 // The 32-bit cmpxchg compares the value at adr with the contents of rax, | |
| 1238 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | |
| 1239 // The ZF is set if the compared values were equal, and cleared otherwise. | |
| 1240 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg | |
| 6834 | 1241 InstructionMark im(this); |
| 1242 prefix(adr, reg); | |
|
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1243 emit_int8(0x0F); |
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1244 emit_int8((unsigned char)0xB1); |
| 6834 | 1245 emit_operand(reg, adr); |
| 304 | 1246 } |
| 1247 | |
| 1248 void Assembler::comisd(XMMRegister dst, Address src) { | |
| 1249 // NOTE: dbx seems to decode this as comiss even though the | |
| 1250 // 0x66 is there. Strangly ucomisd comes out correct | |
| 1251 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1252 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66); |
| 4759 | 1253 } |
| 1254 | |
| 1255 void Assembler::comisd(XMMRegister dst, XMMRegister src) { | |
| 1256 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1257 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66); |
| 304 | 1258 } |
| 1259 | |
| 1260 void Assembler::comiss(XMMRegister dst, Address src) { | |
| 1261 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1262 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE); |
| 304 | 1263 } |
| 1264 | |
| 4759 | 1265 void Assembler::comiss(XMMRegister dst, XMMRegister src) { |
| 1266 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1267 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE); |
| 4759 | 1268 } |
| 1269 | |
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1270 void Assembler::cpuid() { |
|
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1271 emit_int8(0x0F); |
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1272 emit_int8((unsigned char)0xA2); |
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1273 } |
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1274 |
| 304 | 1275 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { |
| 1276 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1277 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3); |
| 304 | 1278 } |
| 1279 | |
| 1280 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | |
| 1281 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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1282 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE); |
| 304 | 1283 } |
| 1284 | |
| 1285 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | |
| 1286 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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1287 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2); |
| 304 | 1288 } |
| 1289 | |
| 4759 | 1290 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { |
| 1291 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1292 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2); |
| 4759 | 1293 } |
| 1294 | |
| 304 | 1295 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { |
| 1296 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1297 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
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1298 emit_int8(0x2A); |
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1299 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 1300 } |
| 1301 | |
| 4759 | 1302 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { |
| 1303 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1304 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2); |
| 4759 | 1305 } |
| 1306 | |
| 304 | 1307 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { |
| 1308 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1309 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
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1310 emit_int8(0x2A); |
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1311 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 1312 } |
| 1313 | |
| 4759 | 1314 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { |
| 1315 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1316 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3); |
| 4759 | 1317 } |
| 1318 | |
| 304 | 1319 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { |
| 1320 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1321 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3); |
| 304 | 1322 } |
| 1323 | |
| 4759 | 1324 void Assembler::cvtss2sd(XMMRegister dst, Address src) { |
| 1325 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1326 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3); |
| 4759 | 1327 } |
| 1328 | |
| 1329 | |
| 304 | 1330 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { |
| 1331 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1332 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); |
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1333 emit_int8(0x2C); |
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1334 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 1335 } |
| 1336 | |
| 1337 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | |
| 1338 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1339 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
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1340 emit_int8(0x2C); |
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1341 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 1342 } |
| 1343 | |
| 1344 void Assembler::decl(Address dst) { | |
| 1345 // Don't use it directly. Use MacroAssembler::decrement() instead. | |
| 1346 InstructionMark im(this); | |
| 1347 prefix(dst); | |
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1348 emit_int8((unsigned char)0xFF); |
| 304 | 1349 emit_operand(rcx, dst); |
| 1350 } | |
| 1351 | |
| 1352 void Assembler::divsd(XMMRegister dst, Address src) { | |
| 1353 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1354 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2); |
| 304 | 1355 } |
| 1356 | |
| 1357 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | |
| 1358 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1359 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2); |
| 304 | 1360 } |
| 1361 | |
| 1362 void Assembler::divss(XMMRegister dst, Address src) { | |
| 1363 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1364 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); |
| 304 | 1365 } |
| 1366 | |
| 1367 void Assembler::divss(XMMRegister dst, XMMRegister src) { | |
| 1368 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1369 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); |
| 304 | 1370 } |
| 1371 | |
| 1372 void Assembler::emms() { | |
| 1373 NOT_LP64(assert(VM_Version::supports_mmx(), "")); | |
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1374 emit_int8(0x0F); |
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1375 emit_int8(0x77); |
| 304 | 1376 } |
| 1377 | |
| 1378 void Assembler::hlt() { | |
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1379 emit_int8((unsigned char)0xF4); |
| 304 | 1380 } |
| 1381 | |
| 1382 void Assembler::idivl(Register src) { | |
| 1383 int encode = prefix_and_encode(src->encoding()); | |
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1384 emit_int8((unsigned char)0xF7); |
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1385 emit_int8((unsigned char)(0xF8 | encode)); |
| 304 | 1386 } |
| 1387 | |
| 1920 | 1388 void Assembler::divl(Register src) { // Unsigned |
| 1389 int encode = prefix_and_encode(src->encoding()); | |
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1390 emit_int8((unsigned char)0xF7); |
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1391 emit_int8((unsigned char)(0xF0 | encode)); |
| 1920 | 1392 } |
| 1393 | |
| 304 | 1394 void Assembler::imull(Register dst, Register src) { |
| 1395 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1396 emit_int8(0x0F); |
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1397 emit_int8((unsigned char)0xAF); |
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1398 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 1399 } |
| 1400 | |
| 1401 | |
| 1402 void Assembler::imull(Register dst, Register src, int value) { | |
| 1403 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1404 if (is8bit(value)) { | |
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1405 emit_int8(0x6B); |
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1406 emit_int8((unsigned char)(0xC0 | encode)); |
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1407 emit_int8(value & 0xFF); |
| 304 | 1408 } else { |
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1409 emit_int8(0x69); |
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1410 emit_int8((unsigned char)(0xC0 | encode)); |
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1411 emit_int32(value); |
| 304 | 1412 } |
| 1413 } | |
| 1414 | |
| 1415 void Assembler::incl(Address dst) { | |
| 1416 // Don't use it directly. Use MacroAssembler::increment() instead. | |
| 1417 InstructionMark im(this); | |
| 1418 prefix(dst); | |
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1419 emit_int8((unsigned char)0xFF); |
| 304 | 1420 emit_operand(rax, dst); |
| 1421 } | |
| 1422 | |
| 3851 | 1423 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { |
| 1424 InstructionMark im(this); | |
| 304 | 1425 assert((0 <= cc) && (cc < 16), "illegal cc"); |
| 1426 if (L.is_bound()) { | |
| 1427 address dst = target(L); | |
| 1428 assert(dst != NULL, "jcc most probably wrong"); | |
| 1429 | |
| 1430 const int short_size = 2; | |
| 1431 const int long_size = 6; | |
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1432 intptr_t offs = (intptr_t)dst - (intptr_t)pc(); |
| 3851 | 1433 if (maybe_short && is8bit(offs - short_size)) { |
| 304 | 1434 // 0111 tttn #8-bit disp |
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1435 emit_int8(0x70 | cc); |
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1436 emit_int8((offs - short_size) & 0xFF); |
| 304 | 1437 } else { |
| 1438 // 0000 1111 1000 tttn #32-bit disp | |
| 1439 assert(is_simm32(offs - long_size), | |
| 1440 "must be 32bit offset (call4)"); | |
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1441 emit_int8(0x0F); |
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1442 emit_int8((unsigned char)(0x80 | cc)); |
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1443 emit_int32(offs - long_size); |
| 304 | 1444 } |
| 1445 } else { | |
| 1446 // Note: could eliminate cond. jumps to this jump if condition | |
| 1447 // is the same however, seems to be rather unlikely case. | |
| 1448 // Note: use jccb() if label to be bound is very close to get | |
| 1449 // an 8-bit displacement | |
| 1450 L.add_patch_at(code(), locator()); | |
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1451 emit_int8(0x0F); |
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1452 emit_int8((unsigned char)(0x80 | cc)); |
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1453 emit_int32(0); |
| 304 | 1454 } |
| 1455 } | |
| 1456 | |
| 1457 void Assembler::jccb(Condition cc, Label& L) { | |
| 1458 if (L.is_bound()) { | |
| 1459 const int short_size = 2; | |
| 1460 address entry = target(L); | |
|
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1461 #ifdef ASSERT |
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1462 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); |
|
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1463 intptr_t delta = short_branch_delta(); |
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1464 if (delta != 0) { |
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1465 dist += (dist < 0 ? (-delta) :delta); |
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1466 } |
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1467 assert(is8bit(dist), "Dispacement too large for a short jmp"); |
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1468 #endif |
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1469 intptr_t offs = (intptr_t)entry - (intptr_t)pc(); |
| 304 | 1470 // 0111 tttn #8-bit disp |
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1471 emit_int8(0x70 | cc); |
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1472 emit_int8((offs - short_size) & 0xFF); |
| 304 | 1473 } else { |
| 1474 InstructionMark im(this); | |
| 1475 L.add_patch_at(code(), locator()); | |
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1476 emit_int8(0x70 | cc); |
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1477 emit_int8(0); |
| 304 | 1478 } |
| 1479 } | |
| 1480 | |
| 1481 void Assembler::jmp(Address adr) { | |
| 1482 InstructionMark im(this); | |
| 1483 prefix(adr); | |
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1484 emit_int8((unsigned char)0xFF); |
| 304 | 1485 emit_operand(rsp, adr); |
| 1486 } | |
| 1487 | |
| 3851 | 1488 void Assembler::jmp(Label& L, bool maybe_short) { |
| 304 | 1489 if (L.is_bound()) { |
| 1490 address entry = target(L); | |
| 1491 assert(entry != NULL, "jmp most probably wrong"); | |
| 1492 InstructionMark im(this); | |
| 1493 const int short_size = 2; | |
| 1494 const int long_size = 5; | |
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1495 intptr_t offs = entry - pc(); |
| 3851 | 1496 if (maybe_short && is8bit(offs - short_size)) { |
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1497 emit_int8((unsigned char)0xEB); |
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1498 emit_int8((offs - short_size) & 0xFF); |
| 304 | 1499 } else { |
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1500 emit_int8((unsigned char)0xE9); |
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1501 emit_int32(offs - long_size); |
| 304 | 1502 } |
| 1503 } else { | |
| 1504 // By default, forward jumps are always 32-bit displacements, since | |
| 1505 // we can't yet know where the label will be bound. If you're sure that | |
| 1506 // the forward jump will not run beyond 256 bytes, use jmpb to | |
| 1507 // force an 8-bit displacement. | |
| 1508 InstructionMark im(this); | |
| 1509 L.add_patch_at(code(), locator()); | |
|
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1510 emit_int8((unsigned char)0xE9); |
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1511 emit_int32(0); |
| 304 | 1512 } |
| 1513 } | |
| 1514 | |
| 1515 void Assembler::jmp(Register entry) { | |
| 1516 int encode = prefix_and_encode(entry->encoding()); | |
|
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1517 emit_int8((unsigned char)0xFF); |
|
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1518 emit_int8((unsigned char)(0xE0 | encode)); |
| 304 | 1519 } |
| 1520 | |
| 1521 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { | |
| 1522 InstructionMark im(this); | |
|
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1523 emit_int8((unsigned char)0xE9); |
| 304 | 1524 assert(dest != NULL, "must have a target"); |
|
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|
1525 intptr_t disp = dest - (pc() + sizeof(int32_t)); |
| 304 | 1526 assert(is_simm32(disp), "must be 32bit offset (jmp)"); |
| 1527 emit_data(disp, rspec.reloc(), call32_operand); | |
| 1528 } | |
| 1529 | |
| 1530 void Assembler::jmpb(Label& L) { | |
| 1531 if (L.is_bound()) { | |
| 1532 const int short_size = 2; | |
| 1533 address entry = target(L); | |
| 1534 assert(entry != NULL, "jmp most probably wrong"); | |
|
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|
1535 #ifdef ASSERT |
|
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|
1536 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); |
|
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|
1537 intptr_t delta = short_branch_delta(); |
|
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|
1538 if (delta != 0) { |
|
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|
1539 dist += (dist < 0 ? (-delta) :delta); |
|
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|
1540 } |
|
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|
1541 assert(is8bit(dist), "Dispacement too large for a short jmp"); |
|
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|
1542 #endif |
|
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|
1543 intptr_t offs = entry - pc(); |
|
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|
1544 emit_int8((unsigned char)0xEB); |
|
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|
1545 emit_int8((offs - short_size) & 0xFF); |
| 304 | 1546 } else { |
| 1547 InstructionMark im(this); | |
| 1548 L.add_patch_at(code(), locator()); | |
|
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|
1549 emit_int8((unsigned char)0xEB); |
|
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|
1550 emit_int8(0); |
| 304 | 1551 } |
| 1552 } | |
| 1553 | |
| 1554 void Assembler::ldmxcsr( Address src) { | |
| 1555 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1556 InstructionMark im(this); | |
| 1557 prefix(src); | |
|
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|
1558 emit_int8(0x0F); |
|
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|
1559 emit_int8((unsigned char)0xAE); |
| 304 | 1560 emit_operand(as_Register(2), src); |
| 1561 } | |
| 1562 | |
| 1563 void Assembler::leal(Register dst, Address src) { | |
| 1564 InstructionMark im(this); | |
| 1565 #ifdef _LP64 | |
|
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|
1566 emit_int8(0x67); // addr32 |
| 304 | 1567 prefix(src, dst); |
| 1568 #endif // LP64 | |
|
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|
1569 emit_int8((unsigned char)0x8D); |
| 304 | 1570 emit_operand(dst, src); |
| 1571 } | |
| 1572 | |
|
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|
1573 void Assembler::lfence() { |
|
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|
1574 emit_int8(0x0F); |
|
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|
1575 emit_int8((unsigned char)0xAE); |
|
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|
1576 emit_int8((unsigned char)0xE8); |
|
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|
1577 } |
|
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|
1578 |
| 304 | 1579 void Assembler::lock() { |
|
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|
1580 emit_int8((unsigned char)0xF0); |
| 304 | 1581 } |
| 1582 | |
|
775
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|
1583 void Assembler::lzcntl(Register dst, Register src) { |
|
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|
1584 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
|
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|
1585 emit_int8((unsigned char)0xF3); |
|
775
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changeset
|
1586 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
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|
1587 emit_int8(0x0F); |
|
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|
1588 emit_int8((unsigned char)0xBD); |
|
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changeset
|
1589 emit_int8((unsigned char)(0xC0 | encode)); |
|
775
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|
1590 } |
|
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|
1591 |
|
671
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|
1592 // Emit mfence instruction |
| 304 | 1593 void Assembler::mfence() { |
|
671
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|
1594 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
|
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|
1595 emit_int8(0x0F); |
|
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|
1596 emit_int8((unsigned char)0xAE); |
|
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|
1597 emit_int8((unsigned char)0xF0); |
| 304 | 1598 } |
| 1599 | |
| 1600 void Assembler::mov(Register dst, Register src) { | |
| 1601 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 1602 } | |
| 1603 | |
| 1604 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | |
| 1605 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
1606 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66); |
| 304 | 1607 } |
| 1608 | |
| 1609 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | |
| 1610 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
|
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|
1611 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE); |
| 304 | 1612 } |
| 1613 | |
|
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|
1614 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { |
|
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|
1615 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
|
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|
1616 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE); |
|
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|
1617 emit_int8(0x16); |
|
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changeset
|
1618 emit_int8((unsigned char)(0xC0 | encode)); |
|
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|
1619 } |
|
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|
1620 |
| 304 | 1621 void Assembler::movb(Register dst, Address src) { |
| 1622 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
| 1623 InstructionMark im(this); | |
| 1624 prefix(src, dst, true); | |
|
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|
1625 emit_int8((unsigned char)0x8A); |
| 304 | 1626 emit_operand(dst, src); |
| 1627 } | |
| 1628 | |
| 1629 | |
| 1630 void Assembler::movb(Address dst, int imm8) { | |
| 1631 InstructionMark im(this); | |
| 1632 prefix(dst); | |
|
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changeset
|
1633 emit_int8((unsigned char)0xC6); |
| 304 | 1634 emit_operand(rax, dst, 1); |
|
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|
1635 emit_int8(imm8); |
| 304 | 1636 } |
| 1637 | |
| 1638 | |
| 1639 void Assembler::movb(Address dst, Register src) { | |
| 1640 assert(src->has_byte_register(), "must have byte register"); | |
| 1641 InstructionMark im(this); | |
| 1642 prefix(dst, src, true); | |
|
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|
1643 emit_int8((unsigned char)0x88); |
| 304 | 1644 emit_operand(src, dst); |
| 1645 } | |
| 1646 | |
| 1647 void Assembler::movdl(XMMRegister dst, Register src) { | |
| 1648 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1649 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
|
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changeset
|
1650 emit_int8(0x6E); |
|
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|
1651 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 1652 } |
| 1653 | |
| 1654 void Assembler::movdl(Register dst, XMMRegister src) { | |
| 1655 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1656 // swap src/dst to get correct prefix | |
| 4759 | 1657 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66); |
|
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|
1658 emit_int8(0x7E); |
|
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|
1659 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 1660 } |
| 1661 | |
|
2320
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|
1662 void Assembler::movdl(XMMRegister dst, Address src) { |
|
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|
1663 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
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|
1664 InstructionMark im(this); |
| 4759 | 1665 simd_prefix(dst, src, VEX_SIMD_66); |
|
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|
1666 emit_int8(0x6E); |
|
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|
1667 emit_operand(dst, src); |
|
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|
1668 } |
|
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|
1669 |
|
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|
1670 void Assembler::movdl(Address dst, XMMRegister src) { |
|
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|
1671 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
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|
1672 InstructionMark im(this); |
|
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|
1673 simd_prefix(dst, src, VEX_SIMD_66); |
|
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|
1674 emit_int8(0x7E); |
|
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changeset
|
1675 emit_operand(src, dst); |
|
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|
1676 } |
|
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|
1677 |
| 304 | 1678 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { |
| 1679 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
1680 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66); |
| 304 | 1681 } |
| 1682 | |
| 405 | 1683 void Assembler::movdqu(XMMRegister dst, Address src) { |
| 1684 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
1685 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3); |
| 405 | 1686 } |
| 1687 | |
| 1688 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |
| 1689 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
1690 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3); |
| 405 | 1691 } |
| 1692 | |
| 1693 void Assembler::movdqu(Address dst, XMMRegister src) { | |
| 1694 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1695 InstructionMark im(this); | |
| 4759 | 1696 simd_prefix(dst, src, VEX_SIMD_F3); |
|
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|
1697 emit_int8(0x7F); |
| 405 | 1698 emit_operand(src, dst); |
| 1699 } | |
| 1700 | |
|
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|
1701 // Move Unaligned 256bit Vector |
|
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|
1702 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) { |
|
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|
1703 assert(UseAVX, ""); |
|
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|
1704 bool vector256 = true; |
|
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changeset
|
1705 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256); |
|
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|
1706 emit_int8(0x6F); |
|
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1707 emit_int8((unsigned char)(0xC0 | encode)); |
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1708 } |
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1709 |
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1710 void Assembler::vmovdqu(XMMRegister dst, Address src) { |
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1711 assert(UseAVX, ""); |
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1712 InstructionMark im(this); |
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1713 bool vector256 = true; |
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1714 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256); |
|
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1715 emit_int8(0x6F); |
|
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1716 emit_operand(dst, src); |
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1717 } |
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1718 |
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1719 void Assembler::vmovdqu(Address dst, XMMRegister src) { |
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1720 assert(UseAVX, ""); |
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1721 InstructionMark im(this); |
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1722 bool vector256 = true; |
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1723 // swap src<->dst for encoding |
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1724 assert(src != xnoreg, "sanity"); |
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1725 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256); |
|
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1726 emit_int8(0x7F); |
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1727 emit_operand(src, dst); |
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1728 } |
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1729 |
| 304 | 1730 // Uses zero extension on 64bit |
| 1731 | |
| 1732 void Assembler::movl(Register dst, int32_t imm32) { | |
| 1733 int encode = prefix_and_encode(dst->encoding()); | |
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1734 emit_int8((unsigned char)(0xB8 | encode)); |
|
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1735 emit_int32(imm32); |
| 304 | 1736 } |
| 1737 | |
| 1738 void Assembler::movl(Register dst, Register src) { | |
| 1739 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1740 emit_int8((unsigned char)0x8B); |
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1741 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 1742 } |
| 1743 | |
| 1744 void Assembler::movl(Register dst, Address src) { | |
| 1745 InstructionMark im(this); | |
| 1746 prefix(src, dst); | |
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1747 emit_int8((unsigned char)0x8B); |
| 304 | 1748 emit_operand(dst, src); |
| 1749 } | |
| 1750 | |
| 1751 void Assembler::movl(Address dst, int32_t imm32) { | |
| 1752 InstructionMark im(this); | |
| 1753 prefix(dst); | |
|
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1754 emit_int8((unsigned char)0xC7); |
| 304 | 1755 emit_operand(rax, dst, 4); |
|
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1756 emit_int32(imm32); |
| 304 | 1757 } |
| 1758 | |
| 1759 void Assembler::movl(Address dst, Register src) { | |
| 1760 InstructionMark im(this); | |
| 1761 prefix(dst, src); | |
|
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1762 emit_int8((unsigned char)0x89); |
| 304 | 1763 emit_operand(src, dst); |
| 1764 } | |
| 1765 | |
| 1766 // New cpus require to use movsd and movss to avoid partial register stall | |
| 1767 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
| 1768 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
| 1769 void Assembler::movlpd(XMMRegister dst, Address src) { | |
| 1770 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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1771 emit_simd_arith(0x12, dst, src, VEX_SIMD_66); |
| 304 | 1772 } |
| 1773 | |
| 1774 void Assembler::movq( MMXRegister dst, Address src ) { | |
| 1775 assert( VM_Version::supports_mmx(), "" ); | |
|
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1776 emit_int8(0x0F); |
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1777 emit_int8(0x6F); |
| 304 | 1778 emit_operand(dst, src); |
| 1779 } | |
| 1780 | |
| 1781 void Assembler::movq( Address dst, MMXRegister src ) { | |
| 1782 assert( VM_Version::supports_mmx(), "" ); | |
|
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1783 emit_int8(0x0F); |
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1784 emit_int8(0x7F); |
| 304 | 1785 // workaround gcc (3.2.1-7a) bug |
| 1786 // In that version of gcc with only an emit_operand(MMX, Address) | |
| 1787 // gcc will tail jump and try and reverse the parameters completely | |
| 1788 // obliterating dst in the process. By having a version available | |
| 1789 // that doesn't need to swap the args at the tail jump the bug is | |
| 1790 // avoided. | |
| 1791 emit_operand(dst, src); | |
| 1792 } | |
| 1793 | |
| 1794 void Assembler::movq(XMMRegister dst, Address src) { | |
| 1795 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1796 InstructionMark im(this); | |
| 4759 | 1797 simd_prefix(dst, src, VEX_SIMD_F3); |
|
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1798 emit_int8(0x7E); |
| 304 | 1799 emit_operand(dst, src); |
| 1800 } | |
| 1801 | |
| 1802 void Assembler::movq(Address dst, XMMRegister src) { | |
| 1803 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1804 InstructionMark im(this); | |
| 4759 | 1805 simd_prefix(dst, src, VEX_SIMD_66); |
|
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1806 emit_int8((unsigned char)0xD6); |
| 304 | 1807 emit_operand(src, dst); |
| 1808 } | |
| 1809 | |
| 1810 void Assembler::movsbl(Register dst, Address src) { // movsxb | |
| 1811 InstructionMark im(this); | |
| 1812 prefix(src, dst); | |
|
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1813 emit_int8(0x0F); |
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1814 emit_int8((unsigned char)0xBE); |
| 304 | 1815 emit_operand(dst, src); |
| 1816 } | |
| 1817 | |
| 1818 void Assembler::movsbl(Register dst, Register src) { // movsxb | |
| 1819 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
| 1820 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
|
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1821 emit_int8(0x0F); |
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1822 emit_int8((unsigned char)0xBE); |
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1823 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 1824 } |
| 1825 | |
| 1826 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | |
| 1827 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1828 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2); |
| 304 | 1829 } |
| 1830 | |
| 1831 void Assembler::movsd(XMMRegister dst, Address src) { | |
| 1832 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1833 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2); |
| 304 | 1834 } |
| 1835 | |
| 1836 void Assembler::movsd(Address dst, XMMRegister src) { | |
| 1837 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1838 InstructionMark im(this); | |
| 4759 | 1839 simd_prefix(dst, src, VEX_SIMD_F2); |
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1840 emit_int8(0x11); |
| 304 | 1841 emit_operand(src, dst); |
| 1842 } | |
| 1843 | |
| 1844 void Assembler::movss(XMMRegister dst, XMMRegister src) { | |
| 1845 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1846 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3); |
| 304 | 1847 } |
| 1848 | |
| 1849 void Assembler::movss(XMMRegister dst, Address src) { | |
| 1850 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1851 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3); |
| 304 | 1852 } |
| 1853 | |
| 1854 void Assembler::movss(Address dst, XMMRegister src) { | |
| 1855 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1856 InstructionMark im(this); | |
| 4759 | 1857 simd_prefix(dst, src, VEX_SIMD_F3); |
|
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1858 emit_int8(0x11); |
| 304 | 1859 emit_operand(src, dst); |
| 1860 } | |
| 1861 | |
| 1862 void Assembler::movswl(Register dst, Address src) { // movsxw | |
| 1863 InstructionMark im(this); | |
| 1864 prefix(src, dst); | |
|
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1865 emit_int8(0x0F); |
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1866 emit_int8((unsigned char)0xBF); |
| 304 | 1867 emit_operand(dst, src); |
| 1868 } | |
| 1869 | |
| 1870 void Assembler::movswl(Register dst, Register src) { // movsxw | |
| 1871 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
|
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1872 emit_int8(0x0F); |
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1873 emit_int8((unsigned char)0xBF); |
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1874 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 1875 } |
| 1876 | |
| 1877 void Assembler::movw(Address dst, int imm16) { | |
| 1878 InstructionMark im(this); | |
| 1879 | |
|
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1880 emit_int8(0x66); // switch to 16-bit mode |
| 304 | 1881 prefix(dst); |
|
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1882 emit_int8((unsigned char)0xC7); |
| 304 | 1883 emit_operand(rax, dst, 2); |
|
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1884 emit_int16(imm16); |
| 304 | 1885 } |
| 1886 | |
| 1887 void Assembler::movw(Register dst, Address src) { | |
| 1888 InstructionMark im(this); | |
|
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1889 emit_int8(0x66); |
| 304 | 1890 prefix(src, dst); |
|
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1891 emit_int8((unsigned char)0x8B); |
| 304 | 1892 emit_operand(dst, src); |
| 1893 } | |
| 1894 | |
| 1895 void Assembler::movw(Address dst, Register src) { | |
| 1896 InstructionMark im(this); | |
|
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1897 emit_int8(0x66); |
| 304 | 1898 prefix(dst, src); |
|
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1899 emit_int8((unsigned char)0x89); |
| 304 | 1900 emit_operand(src, dst); |
| 1901 } | |
| 1902 | |
| 1903 void Assembler::movzbl(Register dst, Address src) { // movzxb | |
| 1904 InstructionMark im(this); | |
| 1905 prefix(src, dst); | |
|
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1906 emit_int8(0x0F); |
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1907 emit_int8((unsigned char)0xB6); |
| 304 | 1908 emit_operand(dst, src); |
| 1909 } | |
| 1910 | |
| 1911 void Assembler::movzbl(Register dst, Register src) { // movzxb | |
| 1912 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
| 1913 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
|
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1914 emit_int8(0x0F); |
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1915 emit_int8((unsigned char)0xB6); |
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1916 emit_int8(0xC0 | encode); |
| 304 | 1917 } |
| 1918 | |
| 1919 void Assembler::movzwl(Register dst, Address src) { // movzxw | |
| 1920 InstructionMark im(this); | |
| 1921 prefix(src, dst); | |
|
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1922 emit_int8(0x0F); |
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1923 emit_int8((unsigned char)0xB7); |
| 304 | 1924 emit_operand(dst, src); |
| 1925 } | |
| 1926 | |
| 1927 void Assembler::movzwl(Register dst, Register src) { // movzxw | |
| 1928 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
|
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1929 emit_int8(0x0F); |
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1930 emit_int8((unsigned char)0xB7); |
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1931 emit_int8(0xC0 | encode); |
| 304 | 1932 } |
| 1933 | |
| 1934 void Assembler::mull(Address src) { | |
| 1935 InstructionMark im(this); | |
| 1936 prefix(src); | |
|
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1937 emit_int8((unsigned char)0xF7); |
| 304 | 1938 emit_operand(rsp, src); |
| 1939 } | |
| 1940 | |
| 1941 void Assembler::mull(Register src) { | |
| 1942 int encode = prefix_and_encode(src->encoding()); | |
|
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1943 emit_int8((unsigned char)0xF7); |
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1944 emit_int8((unsigned char)(0xE0 | encode)); |
| 304 | 1945 } |
| 1946 | |
| 1947 void Assembler::mulsd(XMMRegister dst, Address src) { | |
| 1948 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1949 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); |
| 304 | 1950 } |
| 1951 | |
| 1952 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | |
| 1953 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1954 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); |
| 304 | 1955 } |
| 1956 | |
| 1957 void Assembler::mulss(XMMRegister dst, Address src) { | |
| 1958 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1959 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); |
| 304 | 1960 } |
| 1961 | |
| 1962 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | |
| 1963 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1964 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); |
| 304 | 1965 } |
| 1966 | |
| 1967 void Assembler::negl(Register dst) { | |
| 1968 int encode = prefix_and_encode(dst->encoding()); | |
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1969 emit_int8((unsigned char)0xF7); |
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1970 emit_int8((unsigned char)(0xD8 | encode)); |
| 304 | 1971 } |
| 1972 | |
| 0 | 1973 void Assembler::nop(int i) { |
| 304 | 1974 #ifdef ASSERT |
| 0 | 1975 assert(i > 0, " "); |
| 304 | 1976 // The fancy nops aren't currently recognized by debuggers making it a |
| 1977 // pain to disassemble code while debugging. If asserts are on clearly | |
| 1978 // speed is not an issue so simply use the single byte traditional nop | |
| 1979 // to do alignment. | |
| 1980 | |
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1981 for (; i > 0 ; i--) emit_int8((unsigned char)0x90); |
| 304 | 1982 return; |
| 1983 | |
| 1984 #endif // ASSERT | |
| 1985 | |
| 0 | 1986 if (UseAddressNop && VM_Version::is_intel()) { |
| 1987 // | |
| 1988 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel | |
| 1989 // 1: 0x90 | |
| 1990 // 2: 0x66 0x90 | |
| 1991 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
| 1992 // 4: 0x0F 0x1F 0x40 0x00 | |
| 1993 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
| 1994 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 1995 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 1996 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1997 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1998 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1999 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2000 | |
| 2001 // The rest coding is Intel specific - don't use consecutive address nops | |
| 2002 | |
| 2003 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 2004 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 2005 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 2006 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 2007 | |
| 2008 while(i >= 15) { | |
| 2009 // For Intel don't generate consecutive addess nops (mix with regular nops) | |
| 2010 i -= 15; | |
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2011 emit_int8(0x66); // size prefix |
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2012 emit_int8(0x66); // size prefix |
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2013 emit_int8(0x66); // size prefix |
| 0 | 2014 addr_nop_8(); |
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2015 emit_int8(0x66); // size prefix |
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2016 emit_int8(0x66); // size prefix |
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2017 emit_int8(0x66); // size prefix |
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2018 emit_int8((unsigned char)0x90); |
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2019 // nop |
| 0 | 2020 } |
| 2021 switch (i) { | |
| 2022 case 14: | |
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2023 emit_int8(0x66); // size prefix |
| 0 | 2024 case 13: |
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2025 emit_int8(0x66); // size prefix |
| 0 | 2026 case 12: |
| 2027 addr_nop_8(); | |
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2028 emit_int8(0x66); // size prefix |
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2029 emit_int8(0x66); // size prefix |
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2030 emit_int8(0x66); // size prefix |
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2031 emit_int8((unsigned char)0x90); |
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2032 // nop |
| 0 | 2033 break; |
| 2034 case 11: | |
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2035 emit_int8(0x66); // size prefix |
| 0 | 2036 case 10: |
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2037 emit_int8(0x66); // size prefix |
| 0 | 2038 case 9: |
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2039 emit_int8(0x66); // size prefix |
| 0 | 2040 case 8: |
| 2041 addr_nop_8(); | |
| 2042 break; | |
| 2043 case 7: | |
| 2044 addr_nop_7(); | |
| 2045 break; | |
| 2046 case 6: | |
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2047 emit_int8(0x66); // size prefix |
| 0 | 2048 case 5: |
| 2049 addr_nop_5(); | |
| 2050 break; | |
| 2051 case 4: | |
| 2052 addr_nop_4(); | |
| 2053 break; | |
| 2054 case 3: | |
| 2055 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
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2056 emit_int8(0x66); // size prefix |
| 0 | 2057 case 2: |
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2058 emit_int8(0x66); // size prefix |
| 0 | 2059 case 1: |
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2060 emit_int8((unsigned char)0x90); |
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2061 // nop |
| 0 | 2062 break; |
| 2063 default: | |
| 2064 assert(i == 0, " "); | |
| 2065 } | |
| 2066 return; | |
| 2067 } | |
| 2068 if (UseAddressNop && VM_Version::is_amd()) { | |
| 2069 // | |
| 2070 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. | |
| 2071 // 1: 0x90 | |
| 2072 // 2: 0x66 0x90 | |
| 2073 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
| 2074 // 4: 0x0F 0x1F 0x40 0x00 | |
| 2075 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
| 2076 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2077 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2078 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2079 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2080 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2081 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2082 | |
| 2083 // The rest coding is AMD specific - use consecutive address nops | |
| 2084 | |
| 2085 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2086 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2087 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2088 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2089 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2090 // Size prefixes (0x66) are added for larger sizes | |
| 2091 | |
| 2092 while(i >= 22) { | |
| 2093 i -= 11; | |
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2094 emit_int8(0x66); // size prefix |
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2095 emit_int8(0x66); // size prefix |
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2096 emit_int8(0x66); // size prefix |
| 0 | 2097 addr_nop_8(); |
| 2098 } | |
| 2099 // Generate first nop for size between 21-12 | |
| 2100 switch (i) { | |
| 2101 case 21: | |
| 2102 i -= 1; | |
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2103 emit_int8(0x66); // size prefix |
| 0 | 2104 case 20: |
| 2105 case 19: | |
| 2106 i -= 1; | |
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2107 emit_int8(0x66); // size prefix |
| 0 | 2108 case 18: |
| 2109 case 17: | |
| 2110 i -= 1; | |
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2111 emit_int8(0x66); // size prefix |
| 0 | 2112 case 16: |
| 2113 case 15: | |
| 2114 i -= 8; | |
| 2115 addr_nop_8(); | |
| 2116 break; | |
| 2117 case 14: | |
| 2118 case 13: | |
| 2119 i -= 7; | |
| 2120 addr_nop_7(); | |
| 2121 break; | |
| 2122 case 12: | |
| 2123 i -= 6; | |
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2124 emit_int8(0x66); // size prefix |
| 0 | 2125 addr_nop_5(); |
| 2126 break; | |
| 2127 default: | |
| 2128 assert(i < 12, " "); | |
| 2129 } | |
| 2130 | |
| 2131 // Generate second nop for size between 11-1 | |
| 2132 switch (i) { | |
| 2133 case 11: | |
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2134 emit_int8(0x66); // size prefix |
| 0 | 2135 case 10: |
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2136 emit_int8(0x66); // size prefix |
| 0 | 2137 case 9: |
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2138 emit_int8(0x66); // size prefix |
| 0 | 2139 case 8: |
| 2140 addr_nop_8(); | |
| 2141 break; | |
| 2142 case 7: | |
| 2143 addr_nop_7(); | |
| 2144 break; | |
| 2145 case 6: | |
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2146 emit_int8(0x66); // size prefix |
| 0 | 2147 case 5: |
| 2148 addr_nop_5(); | |
| 2149 break; | |
| 2150 case 4: | |
| 2151 addr_nop_4(); | |
| 2152 break; | |
| 2153 case 3: | |
| 2154 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
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2155 emit_int8(0x66); // size prefix |
| 0 | 2156 case 2: |
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2157 emit_int8(0x66); // size prefix |
| 0 | 2158 case 1: |
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2159 emit_int8((unsigned char)0x90); |
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2160 // nop |
| 0 | 2161 break; |
| 2162 default: | |
| 2163 assert(i == 0, " "); | |
| 2164 } | |
| 2165 return; | |
| 2166 } | |
| 2167 | |
| 2168 // Using nops with size prefixes "0x66 0x90". | |
| 2169 // From AMD Optimization Guide: | |
| 2170 // 1: 0x90 | |
| 2171 // 2: 0x66 0x90 | |
| 2172 // 3: 0x66 0x66 0x90 | |
| 2173 // 4: 0x66 0x66 0x66 0x90 | |
| 2174 // 5: 0x66 0x66 0x90 0x66 0x90 | |
| 2175 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2176 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2177 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 | |
| 2178 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2179 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2180 // | |
| 2181 while(i > 12) { | |
| 2182 i -= 4; | |
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2183 emit_int8(0x66); // size prefix |
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2184 emit_int8(0x66); |
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2185 emit_int8(0x66); |
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2186 emit_int8((unsigned char)0x90); |
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2187 // nop |
| 0 | 2188 } |
| 2189 // 1 - 12 nops | |
| 2190 if(i > 8) { | |
| 2191 if(i > 9) { | |
| 2192 i -= 1; | |
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2193 emit_int8(0x66); |
| 0 | 2194 } |
| 2195 i -= 3; | |
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2196 emit_int8(0x66); |
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2197 emit_int8(0x66); |
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2198 emit_int8((unsigned char)0x90); |
| 0 | 2199 } |
| 2200 // 1 - 8 nops | |
| 2201 if(i > 4) { | |
| 2202 if(i > 6) { | |
| 2203 i -= 1; | |
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2204 emit_int8(0x66); |
| 0 | 2205 } |
| 2206 i -= 3; | |
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2207 emit_int8(0x66); |
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2208 emit_int8(0x66); |
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2209 emit_int8((unsigned char)0x90); |
| 0 | 2210 } |
| 2211 switch (i) { | |
| 2212 case 4: | |
|
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2213 emit_int8(0x66); |
| 0 | 2214 case 3: |
|
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2215 emit_int8(0x66); |
| 0 | 2216 case 2: |
|
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2217 emit_int8(0x66); |
| 0 | 2218 case 1: |
|
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2219 emit_int8((unsigned char)0x90); |
| 0 | 2220 break; |
| 2221 default: | |
| 2222 assert(i == 0, " "); | |
| 2223 } | |
| 2224 } | |
| 2225 | |
| 304 | 2226 void Assembler::notl(Register dst) { |
| 2227 int encode = prefix_and_encode(dst->encoding()); | |
|
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2228 emit_int8((unsigned char)0xF7); |
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2229 emit_int8((unsigned char)(0xD0 | encode)); |
| 304 | 2230 } |
| 2231 | |
| 2232 void Assembler::orl(Address dst, int32_t imm32) { | |
| 2233 InstructionMark im(this); | |
| 2234 prefix(dst); | |
|
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|
2235 emit_arith_operand(0x81, rcx, dst, imm32); |
| 304 | 2236 } |
| 2237 | |
| 2238 void Assembler::orl(Register dst, int32_t imm32) { | |
| 2239 prefix(dst); | |
| 2240 emit_arith(0x81, 0xC8, dst, imm32); | |
| 2241 } | |
| 2242 | |
| 2243 void Assembler::orl(Register dst, Address src) { | |
| 2244 InstructionMark im(this); | |
| 2245 prefix(src, dst); | |
|
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|
2246 emit_int8(0x0B); |
| 304 | 2247 emit_operand(dst, src); |
| 2248 } | |
| 2249 | |
| 2250 void Assembler::orl(Register dst, Register src) { | |
| 2251 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2252 emit_arith(0x0B, 0xC0, dst, src); | |
| 2253 } | |
| 2254 | |
| 4759 | 2255 void Assembler::packuswb(XMMRegister dst, Address src) { |
| 2256 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2257 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
|
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2258 emit_simd_arith(0x67, dst, src, VEX_SIMD_66); |
| 4759 | 2259 } |
| 2260 | |
| 2261 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { | |
| 2262 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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2263 emit_simd_arith(0x67, dst, src, VEX_SIMD_66); |
| 4759 | 2264 } |
| 2265 | |
| 681 | 2266 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
| 2267 assert(VM_Version::supports_sse4_2(), ""); | |
| 4759 | 2268 InstructionMark im(this); |
| 2269 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); | |
|
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2270 emit_int8(0x61); |
| 681 | 2271 emit_operand(dst, src); |
|
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|
2272 emit_int8(imm8); |
| 681 | 2273 } |
| 2274 | |
| 2275 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | |
| 2276 assert(VM_Version::supports_sse4_2(), ""); | |
|
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2277 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); |
|
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2278 emit_int8(0x61); |
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2279 emit_int8((unsigned char)(0xC0 | encode)); |
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|
2280 emit_int8(imm8); |
| 681 | 2281 } |
| 2282 | |
| 4759 | 2283 void Assembler::pmovzxbw(XMMRegister dst, Address src) { |
| 2284 assert(VM_Version::supports_sse4_1(), ""); | |
| 2285 InstructionMark im(this); | |
| 2286 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
|
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|
2287 emit_int8(0x30); |
| 4759 | 2288 emit_operand(dst, src); |
| 2289 } | |
| 2290 | |
| 2291 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { | |
| 2292 assert(VM_Version::supports_sse4_1(), ""); | |
|
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2293 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
|
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|
2294 emit_int8(0x30); |
|
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|
2295 emit_int8((unsigned char)(0xC0 | encode)); |
| 4759 | 2296 } |
| 2297 | |
| 304 | 2298 // generic |
| 2299 void Assembler::pop(Register dst) { | |
| 2300 int encode = prefix_and_encode(dst->encoding()); | |
|
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2301 emit_int8(0x58 | encode); |
| 304 | 2302 } |
| 2303 | |
|
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2304 void Assembler::popcntl(Register dst, Address src) { |
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2305 assert(VM_Version::supports_popcnt(), "must support"); |
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2306 InstructionMark im(this); |
|
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2307 emit_int8((unsigned char)0xF3); |
|
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|
2308 prefix(src, dst); |
|
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2309 emit_int8(0x0F); |
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|
2310 emit_int8((unsigned char)0xB8); |
|
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|
2311 emit_operand(dst, src); |
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2312 } |
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2313 |
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2314 void Assembler::popcntl(Register dst, Register src) { |
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2315 assert(VM_Version::supports_popcnt(), "must support"); |
|
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|
2316 emit_int8((unsigned char)0xF3); |
|
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2317 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
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|
2318 emit_int8(0x0F); |
|
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|
2319 emit_int8((unsigned char)0xB8); |
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|
2320 emit_int8((unsigned char)(0xC0 | encode)); |
|
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2321 } |
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2322 |
| 304 | 2323 void Assembler::popf() { |
|
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|
2324 emit_int8((unsigned char)0x9D); |
| 304 | 2325 } |
| 2326 | |
| 1060 | 2327 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 2328 void Assembler::popl(Address dst) { |
| 2329 // NOTE: this will adjust stack by 8byte on 64bits | |
| 2330 InstructionMark im(this); | |
| 2331 prefix(dst); | |
|
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|
2332 emit_int8((unsigned char)0x8F); |
| 304 | 2333 emit_operand(rax, dst); |
| 2334 } | |
| 1060 | 2335 #endif |
| 304 | 2336 |
| 2337 void Assembler::prefetch_prefix(Address src) { | |
| 2338 prefix(src); | |
|
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|
2339 emit_int8(0x0F); |
| 304 | 2340 } |
| 2341 | |
| 2342 void Assembler::prefetchnta(Address src) { | |
|
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|
2343 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); |
| 304 | 2344 InstructionMark im(this); |
| 2345 prefetch_prefix(src); | |
|
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|
2346 emit_int8(0x18); |
| 304 | 2347 emit_operand(rax, src); // 0, src |
| 2348 } | |
| 2349 | |
| 2350 void Assembler::prefetchr(Address src) { | |
| 3854 | 2351 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
| 304 | 2352 InstructionMark im(this); |
| 2353 prefetch_prefix(src); | |
|
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|
2354 emit_int8(0x0D); |
| 304 | 2355 emit_operand(rax, src); // 0, src |
| 2356 } | |
| 2357 | |
| 2358 void Assembler::prefetcht0(Address src) { | |
| 2359 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2360 InstructionMark im(this); | |
| 2361 prefetch_prefix(src); | |
|
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changeset
|
2362 emit_int8(0x18); |
| 304 | 2363 emit_operand(rcx, src); // 1, src |
| 2364 } | |
| 2365 | |
| 2366 void Assembler::prefetcht1(Address src) { | |
| 2367 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2368 InstructionMark im(this); | |
| 2369 prefetch_prefix(src); | |
|
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|
2370 emit_int8(0x18); |
| 304 | 2371 emit_operand(rdx, src); // 2, src |
| 2372 } | |
| 2373 | |
| 2374 void Assembler::prefetcht2(Address src) { | |
| 2375 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2376 InstructionMark im(this); | |
| 2377 prefetch_prefix(src); | |
|
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|
2378 emit_int8(0x18); |
| 304 | 2379 emit_operand(rbx, src); // 3, src |
| 2380 } | |
| 2381 | |
| 2382 void Assembler::prefetchw(Address src) { | |
| 3854 | 2383 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
| 304 | 2384 InstructionMark im(this); |
| 2385 prefetch_prefix(src); | |
|
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|
2386 emit_int8(0x0D); |
| 304 | 2387 emit_operand(rcx, src); // 1, src |
| 2388 } | |
| 2389 | |
| 2390 void Assembler::prefix(Prefix p) { | |
|
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|
2391 emit_int8(p); |
| 304 | 2392 } |
| 2393 | |
| 6894 | 2394 void Assembler::pshufb(XMMRegister dst, XMMRegister src) { |
| 2395 assert(VM_Version::supports_ssse3(), ""); | |
| 2396 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
|
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|
2397 emit_int8(0x00); |
|
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|
2398 emit_int8((unsigned char)(0xC0 | encode)); |
| 6894 | 2399 } |
| 2400 | |
| 2401 void Assembler::pshufb(XMMRegister dst, Address src) { | |
| 2402 assert(VM_Version::supports_ssse3(), ""); | |
| 2403 InstructionMark im(this); | |
| 2404 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
|
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|
2405 emit_int8(0x00); |
| 6894 | 2406 emit_operand(dst, src); |
| 2407 } | |
| 2408 | |
| 304 | 2409 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { |
| 2410 assert(isByte(mode), "invalid value"); | |
| 2411 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2412 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66); |
|
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|
2413 emit_int8(mode & 0xFF); |
| 304 | 2414 |
| 2415 } | |
| 2416 | |
| 2417 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | |
| 2418 assert(isByte(mode), "invalid value"); | |
| 2419 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2420 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
| 2421 InstructionMark im(this); | |
| 2422 simd_prefix(dst, src, VEX_SIMD_66); | |
|
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|
2423 emit_int8(0x70); |
| 304 | 2424 emit_operand(dst, src); |
|
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|
2425 emit_int8(mode & 0xFF); |
| 304 | 2426 } |
| 2427 | |
| 2428 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | |
| 2429 assert(isByte(mode), "invalid value"); | |
| 2430 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2431 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2); |
|
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|
2432 emit_int8(mode & 0xFF); |
| 304 | 2433 } |
| 2434 | |
| 2435 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | |
| 2436 assert(isByte(mode), "invalid value"); | |
| 2437 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2438 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
| 2439 InstructionMark im(this); | |
| 2440 simd_prefix(dst, src, VEX_SIMD_F2); | |
|
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|
2441 emit_int8(0x70); |
| 304 | 2442 emit_operand(dst, src); |
|
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|
2443 emit_int8(mode & 0xFF); |
| 304 | 2444 } |
| 2445 | |
|
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2446 void Assembler::psrldq(XMMRegister dst, int shift) { |
|
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|
2447 // Shift 128 bit value in xmm register by number of bytes. |
|
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|
2448 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
| 4759 | 2449 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66); |
|
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|
2450 emit_int8(0x73); |
|
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|
2451 emit_int8((unsigned char)(0xC0 | encode)); |
|
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|
2452 emit_int8(shift); |
|
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|
2453 } |
|
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2454 |
| 681 | 2455 void Assembler::ptest(XMMRegister dst, Address src) { |
| 2456 assert(VM_Version::supports_sse4_1(), ""); | |
| 4759 | 2457 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
| 2458 InstructionMark im(this); | |
| 2459 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
|
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|
2460 emit_int8(0x17); |
| 681 | 2461 emit_operand(dst, src); |
| 2462 } | |
| 2463 | |
| 2464 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | |
| 2465 assert(VM_Version::supports_sse4_1(), ""); | |
|
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2466 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
|
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|
2467 emit_int8(0x17); |
|
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|
2468 emit_int8((unsigned char)(0xC0 | encode)); |
| 681 | 2469 } |
| 2470 | |
| 4759 | 2471 void Assembler::punpcklbw(XMMRegister dst, Address src) { |
| 2472 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2473 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
|
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|
2474 emit_simd_arith(0x60, dst, src, VEX_SIMD_66); |
| 4759 | 2475 } |
| 2476 | |
| 304 | 2477 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
| 2478 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2479 emit_simd_arith(0x60, dst, src, VEX_SIMD_66); |
| 304 | 2480 } |
| 2481 | |
| 4759 | 2482 void Assembler::punpckldq(XMMRegister dst, Address src) { |
| 2483 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2484 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
|
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|
2485 emit_simd_arith(0x62, dst, src, VEX_SIMD_66); |
| 4759 | 2486 } |
| 2487 | |
| 2488 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { | |
| 2489 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2490 emit_simd_arith(0x62, dst, src, VEX_SIMD_66); |
| 4759 | 2491 } |
| 2492 | |
| 6225 | 2493 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) { |
| 2494 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2495 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66); |
| 6225 | 2496 } |
| 2497 | |
| 304 | 2498 void Assembler::push(int32_t imm32) { |
| 2499 // in 64bits we push 64bits onto the stack but only | |
| 2500 // take a 32bit immediate | |
|
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|
2501 emit_int8(0x68); |
|
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|
2502 emit_int32(imm32); |
| 304 | 2503 } |
| 2504 | |
| 2505 void Assembler::push(Register src) { | |
| 2506 int encode = prefix_and_encode(src->encoding()); | |
| 2507 | |
|
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|
2508 emit_int8(0x50 | encode); |
| 304 | 2509 } |
| 2510 | |
| 2511 void Assembler::pushf() { | |
|
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|
2512 emit_int8((unsigned char)0x9C); |
| 304 | 2513 } |
| 2514 | |
| 1060 | 2515 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 2516 void Assembler::pushl(Address src) { |
| 2517 // Note this will push 64bit on 64bit | |
| 2518 InstructionMark im(this); | |
| 2519 prefix(src); | |
|
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|
2520 emit_int8((unsigned char)0xFF); |
| 304 | 2521 emit_operand(rsi, src); |
| 2522 } | |
| 1060 | 2523 #endif |
| 304 | 2524 |
| 2525 void Assembler::rcll(Register dst, int imm8) { | |
| 2526 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2527 int encode = prefix_and_encode(dst->encoding()); | |
| 2528 if (imm8 == 1) { | |
|
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|
2529 emit_int8((unsigned char)0xD1); |
|
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|
2530 emit_int8((unsigned char)(0xD0 | encode)); |
| 304 | 2531 } else { |
|
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|
2532 emit_int8((unsigned char)0xC1); |
|
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|
2533 emit_int8((unsigned char)0xD0 | encode); |
|
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|
2534 emit_int8(imm8); |
| 304 | 2535 } |
| 2536 } | |
| 2537 | |
| 2538 // copies data from [esi] to [edi] using rcx pointer sized words | |
| 2539 // generic | |
| 2540 void Assembler::rep_mov() { | |
|
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|
2541 emit_int8((unsigned char)0xF3); |
| 304 | 2542 // MOVSQ |
| 2543 LP64_ONLY(prefix(REX_W)); | |
|
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|
2544 emit_int8((unsigned char)0xA5); |
| 304 | 2545 } |
| 2546 | |
|
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|
2547 // sets rcx bytes with rax, value at [edi] |
|
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|
2548 void Assembler::rep_stosb() { |
|
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|
2549 emit_int8((unsigned char)0xF3); // REP |
|
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2550 LP64_ONLY(prefix(REX_W)); |
|
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|
2551 emit_int8((unsigned char)0xAA); // STOSB |
|
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|
2552 } |
|
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|
2553 |
| 304 | 2554 // sets rcx pointer sized words with rax, value at [edi] |
| 2555 // generic | |
|
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|
2556 void Assembler::rep_stos() { |
|
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|
2557 emit_int8((unsigned char)0xF3); // REP |
|
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|
2558 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD |
|
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|
2559 emit_int8((unsigned char)0xAB); |
| 304 | 2560 } |
| 2561 | |
| 2562 // scans rcx pointer sized words at [edi] for occurance of rax, | |
| 2563 // generic | |
| 2564 void Assembler::repne_scan() { // repne_scan | |
|
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|
2565 emit_int8((unsigned char)0xF2); |
| 304 | 2566 // SCASQ |
| 2567 LP64_ONLY(prefix(REX_W)); | |
|
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|
2568 emit_int8((unsigned char)0xAF); |
| 304 | 2569 } |
| 2570 | |
| 2571 #ifdef _LP64 | |
| 2572 // scans rcx 4 byte words at [edi] for occurance of rax, | |
| 2573 // generic | |
| 2574 void Assembler::repne_scanl() { // repne_scan | |
|
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|
2575 emit_int8((unsigned char)0xF2); |
| 304 | 2576 // SCASL |
|
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|
2577 emit_int8((unsigned char)0xAF); |
| 304 | 2578 } |
| 2579 #endif | |
| 2580 | |
| 0 | 2581 void Assembler::ret(int imm16) { |
| 2582 if (imm16 == 0) { | |
|
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|
2583 emit_int8((unsigned char)0xC3); |
| 0 | 2584 } else { |
|
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|
2585 emit_int8((unsigned char)0xC2); |
|
7424
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|
2586 emit_int16(imm16); |
| 0 | 2587 } |
| 2588 } | |
| 2589 | |
| 304 | 2590 void Assembler::sahf() { |
| 2591 #ifdef _LP64 | |
| 2592 // Not supported in 64bit mode | |
| 2593 ShouldNotReachHere(); | |
| 2594 #endif | |
|
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|
2595 emit_int8((unsigned char)0x9E); |
| 304 | 2596 } |
| 2597 | |
| 2598 void Assembler::sarl(Register dst, int imm8) { | |
| 2599 int encode = prefix_and_encode(dst->encoding()); | |
| 2600 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2601 if (imm8 == 1) { | |
|
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|
2602 emit_int8((unsigned char)0xD1); |
|
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|
2603 emit_int8((unsigned char)(0xF8 | encode)); |
| 304 | 2604 } else { |
|
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|
2605 emit_int8((unsigned char)0xC1); |
|
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changeset
|
2606 emit_int8((unsigned char)(0xF8 | encode)); |
|
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|
2607 emit_int8(imm8); |
| 304 | 2608 } |
| 2609 } | |
| 2610 | |
| 2611 void Assembler::sarl(Register dst) { | |
| 2612 int encode = prefix_and_encode(dst->encoding()); | |
|
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changeset
|
2613 emit_int8((unsigned char)0xD3); |
|
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|
2614 emit_int8((unsigned char)(0xF8 | encode)); |
| 304 | 2615 } |
| 2616 | |
| 2617 void Assembler::sbbl(Address dst, int32_t imm32) { | |
| 2618 InstructionMark im(this); | |
| 2619 prefix(dst); | |
| 2620 emit_arith_operand(0x81, rbx, dst, imm32); | |
| 2621 } | |
| 2622 | |
| 2623 void Assembler::sbbl(Register dst, int32_t imm32) { | |
| 2624 prefix(dst); | |
| 2625 emit_arith(0x81, 0xD8, dst, imm32); | |
| 2626 } | |
| 2627 | |
| 2628 | |
| 2629 void Assembler::sbbl(Register dst, Address src) { | |
| 2630 InstructionMark im(this); | |
| 2631 prefix(src, dst); | |
|
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changeset
|
2632 emit_int8(0x1B); |
| 304 | 2633 emit_operand(dst, src); |
| 2634 } | |
| 2635 | |
| 2636 void Assembler::sbbl(Register dst, Register src) { | |
| 2637 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2638 emit_arith(0x1B, 0xC0, dst, src); | |
| 2639 } | |
| 2640 | |
| 2641 void Assembler::setb(Condition cc, Register dst) { | |
| 2642 assert(0 <= cc && cc < 16, "illegal cc"); | |
| 2643 int encode = prefix_and_encode(dst->encoding(), true); | |
|
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|
2644 emit_int8(0x0F); |
|
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|
2645 emit_int8((unsigned char)0x90 | cc); |
|
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|
2646 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 2647 } |
| 2648 | |
| 2649 void Assembler::shll(Register dst, int imm8) { | |
| 2650 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2651 int encode = prefix_and_encode(dst->encoding()); | |
| 2652 if (imm8 == 1 ) { | |
|
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|
2653 emit_int8((unsigned char)0xD1); |
|
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|
2654 emit_int8((unsigned char)(0xE0 | encode)); |
| 304 | 2655 } else { |
|
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|
2656 emit_int8((unsigned char)0xC1); |
|
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|
2657 emit_int8((unsigned char)(0xE0 | encode)); |
|
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|
2658 emit_int8(imm8); |
| 304 | 2659 } |
| 2660 } | |
| 2661 | |
| 2662 void Assembler::shll(Register dst) { | |
| 2663 int encode = prefix_and_encode(dst->encoding()); | |
|
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|
2664 emit_int8((unsigned char)0xD3); |
|
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|
2665 emit_int8((unsigned char)(0xE0 | encode)); |
| 304 | 2666 } |
| 2667 | |
| 2668 void Assembler::shrl(Register dst, int imm8) { | |
| 2669 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2670 int encode = prefix_and_encode(dst->encoding()); | |
|
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|
2671 emit_int8((unsigned char)0xC1); |
|
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changeset
|
2672 emit_int8((unsigned char)(0xE8 | encode)); |
|
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|
2673 emit_int8(imm8); |
| 304 | 2674 } |
| 2675 | |
| 2676 void Assembler::shrl(Register dst) { | |
| 2677 int encode = prefix_and_encode(dst->encoding()); | |
|
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|
2678 emit_int8((unsigned char)0xD3); |
|
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|
2679 emit_int8((unsigned char)(0xE8 | encode)); |
| 304 | 2680 } |
| 0 | 2681 |
| 2682 // copies a single word from [esi] to [edi] | |
| 2683 void Assembler::smovl() { | |
|
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|
2684 emit_int8((unsigned char)0xA5); |
| 0 | 2685 } |
| 2686 | |
| 304 | 2687 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
| 2688 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2689 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); |
| 304 | 2690 } |
| 2691 | |
| 2008 | 2692 void Assembler::sqrtsd(XMMRegister dst, Address src) { |
| 2693 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2694 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); |
| 2008 | 2695 } |
| 2696 | |
| 2697 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { | |
| 4759 | 2698 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
|
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|
2699 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); |
| 2008 | 2700 } |
| 2701 | |
|
7199
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|
2702 void Assembler::std() { |
|
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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|
2703 emit_int8((unsigned char)0xFD); |
|
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|
2704 } |
|
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|
2705 |
| 2008 | 2706 void Assembler::sqrtss(XMMRegister dst, Address src) { |
| 4759 | 2707 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
|
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|
2708 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); |
| 2008 | 2709 } |
| 2710 | |
| 304 | 2711 void Assembler::stmxcsr( Address dst) { |
| 2712 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2713 InstructionMark im(this); | |
| 2714 prefix(dst); | |
|
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|
2715 emit_int8(0x0F); |
|
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|
2716 emit_int8((unsigned char)0xAE); |
| 304 | 2717 emit_operand(as_Register(3), dst); |
| 2718 } | |
| 2719 | |
| 2720 void Assembler::subl(Address dst, int32_t imm32) { | |
| 2721 InstructionMark im(this); | |
| 2722 prefix(dst); | |
|
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diff
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|
2723 emit_arith_operand(0x81, rbp, dst, imm32); |
| 304 | 2724 } |
| 2725 | |
| 2726 void Assembler::subl(Address dst, Register src) { | |
| 2727 InstructionMark im(this); | |
| 2728 prefix(dst, src); | |
|
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|
2729 emit_int8(0x29); |
| 304 | 2730 emit_operand(src, dst); |
| 2731 } | |
| 2732 | |
|
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|
2733 void Assembler::subl(Register dst, int32_t imm32) { |
|
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|
2734 prefix(dst); |
|
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|
2735 emit_arith(0x81, 0xE8, dst, imm32); |
|
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|
2736 } |
|
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diff
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|
2737 |
|
4947
fd8114661503
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|
2738 // Force generation of a 4 byte immediate value even if it fits into 8bit |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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changeset
|
2739 void Assembler::subl_imm32(Register dst, int32_t imm32) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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|
2740 prefix(dst); |
|
fd8114661503
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changeset
|
2741 emit_arith_imm32(0x81, 0xE8, dst, imm32); |
|
fd8114661503
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|
2742 } |
|
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|
2743 |
| 304 | 2744 void Assembler::subl(Register dst, Address src) { |
| 2745 InstructionMark im(this); | |
| 2746 prefix(src, dst); | |
|
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changeset
|
2747 emit_int8(0x2B); |
| 304 | 2748 emit_operand(dst, src); |
| 2749 } | |
| 2750 | |
| 2751 void Assembler::subl(Register dst, Register src) { | |
| 2752 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2753 emit_arith(0x2B, 0xC0, dst, src); | |
| 2754 } | |
| 2755 | |
| 2756 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | |
| 2757 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2758 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2); |
| 304 | 2759 } |
| 2760 | |
| 2761 void Assembler::subsd(XMMRegister dst, Address src) { | |
| 2762 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2763 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2); |
| 304 | 2764 } |
| 2765 | |
| 2766 void Assembler::subss(XMMRegister dst, XMMRegister src) { | |
| 2767 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
|
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|
2768 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3); |
| 304 | 2769 } |
| 2770 | |
| 2771 void Assembler::subss(XMMRegister dst, Address src) { | |
| 2772 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
|
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|
2773 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3); |
| 304 | 2774 } |
| 2775 | |
| 2776 void Assembler::testb(Register dst, int imm8) { | |
| 2777 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
| 2778 (void) prefix_and_encode(dst->encoding(), true); | |
| 2779 emit_arith_b(0xF6, 0xC0, dst, imm8); | |
| 2780 } | |
| 2781 | |
| 2782 void Assembler::testl(Register dst, int32_t imm32) { | |
| 2783 // not using emit_arith because test | |
| 2784 // doesn't support sign-extension of | |
| 2785 // 8bit operands | |
| 2786 int encode = dst->encoding(); | |
| 2787 if (encode == 0) { | |
|
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|
2788 emit_int8((unsigned char)0xA9); |
| 304 | 2789 } else { |
| 2790 encode = prefix_and_encode(encode); | |
|
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|
2791 emit_int8((unsigned char)0xF7); |
|
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|
2792 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 2793 } |
|
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
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7475
diff
changeset
|
2794 emit_int32(imm32); |
| 304 | 2795 } |
| 2796 | |
| 2797 void Assembler::testl(Register dst, Register src) { | |
| 2798 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2799 emit_arith(0x85, 0xC0, dst, src); | |
| 2800 } | |
| 2801 | |
| 2802 void Assembler::testl(Register dst, Address src) { | |
| 2803 InstructionMark im(this); | |
| 2804 prefix(src, dst); | |
|
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|
2805 emit_int8((unsigned char)0x85); |
| 304 | 2806 emit_operand(dst, src); |
| 2807 } | |
| 2808 | |
| 2809 void Assembler::ucomisd(XMMRegister dst, Address src) { | |
| 2810 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2811 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66); |
| 304 | 2812 } |
| 2813 | |
| 2814 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | |
| 2815 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
|
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|
2816 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66); |
| 304 | 2817 } |
| 2818 | |
| 2819 void Assembler::ucomiss(XMMRegister dst, Address src) { | |
| 2820 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
|
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|
2821 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE); |
| 304 | 2822 } |
| 2823 | |
| 2824 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | |
| 2825 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
|
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|
2826 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE); |
| 304 | 2827 } |
| 2828 | |
| 2829 | |
| 2830 void Assembler::xaddl(Address dst, Register src) { | |
| 2831 InstructionMark im(this); | |
| 2832 prefix(dst, src); | |
|
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|
2833 emit_int8(0x0F); |
|
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changeset
|
2834 emit_int8((unsigned char)0xC1); |
| 304 | 2835 emit_operand(src, dst); |
| 2836 } | |
| 2837 | |
| 2838 void Assembler::xchgl(Register dst, Address src) { // xchg | |
| 2839 InstructionMark im(this); | |
| 2840 prefix(src, dst); | |
|
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|
2841 emit_int8((unsigned char)0x87); |
| 304 | 2842 emit_operand(dst, src); |
| 2843 } | |
| 2844 | |
| 2845 void Assembler::xchgl(Register dst, Register src) { | |
| 2846 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
|
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|
2847 emit_int8((unsigned char)0x87); |
|
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|
2848 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 2849 } |
| 2850 | |
|
7199
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|
2851 void Assembler::xgetbv() { |
|
7430
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|
2852 emit_int8(0x0F); |
|
d02120b7a34f
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|
2853 emit_int8(0x01); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
2854 emit_int8((unsigned char)0xD0); |
|
7199
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|
2855 } |
|
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|
2856 |
| 304 | 2857 void Assembler::xorl(Register dst, int32_t imm32) { |
| 2858 prefix(dst); | |
| 2859 emit_arith(0x81, 0xF0, dst, imm32); | |
| 2860 } | |
| 2861 | |
| 2862 void Assembler::xorl(Register dst, Address src) { | |
| 2863 InstructionMark im(this); | |
| 2864 prefix(src, dst); | |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
2865 emit_int8(0x33); |
| 304 | 2866 emit_operand(dst, src); |
| 2867 } | |
| 2868 | |
| 2869 void Assembler::xorl(Register dst, Register src) { | |
| 2870 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2871 emit_arith(0x33, 0xC0, dst, src); | |
| 2872 } | |
| 2873 | |
|
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|
2874 |
|
006050192a5a
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|
2875 // AVX 3-operands scalar float-point arithmetic instructions |
|
4761
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|
2876 |
|
65149e74c706
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|
2877 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
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|
2878 assert(VM_Version::supports_avx(), ""); |
|
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|
2879 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
|
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|
2880 } |
|
65149e74c706
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|
2881 |
|
65149e74c706
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|
2882 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
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|
2883 assert(VM_Version::supports_avx(), ""); |
|
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|
2884 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
|
4761
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|
2885 } |
|
65149e74c706
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|
2886 |
|
65149e74c706
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|
2887 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
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|
2888 assert(VM_Version::supports_avx(), ""); |
|
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|
2889 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
|
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|
2890 } |
|
65149e74c706
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|
2891 |
|
65149e74c706
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|
2892 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
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|
2893 assert(VM_Version::supports_avx(), ""); |
|
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|
2894 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
|
4761
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|
2895 } |
|
65149e74c706
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|
2896 |
|
65149e74c706
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|
2897 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
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|
2898 assert(VM_Version::supports_avx(), ""); |
|
6614
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|
2899 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
|
4761
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|
2900 } |
|
65149e74c706
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|
2901 |
|
65149e74c706
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|
2902 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
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|
2903 assert(VM_Version::supports_avx(), ""); |
|
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changeset
|
2904 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2905 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2906 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2907 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2908 assert(VM_Version::supports_avx(), ""); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2909 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2910 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2911 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2912 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2913 assert(VM_Version::supports_avx(), ""); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2914 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2915 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2916 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2917 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2918 assert(VM_Version::supports_avx(), ""); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2919 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2920 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2921 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2922 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2923 assert(VM_Version::supports_avx(), ""); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2924 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2925 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2926 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2927 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2928 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2929 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2930 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2931 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2932 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2933 assert(VM_Version::supports_avx(), ""); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2934 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2935 } |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2936 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2937 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2938 assert(VM_Version::supports_avx(), ""); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2939 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2940 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2941 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2942 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2943 assert(VM_Version::supports_avx(), ""); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2944 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2945 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2946 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2947 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2948 assert(VM_Version::supports_avx(), ""); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2949 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2950 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2951 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2952 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2953 assert(VM_Version::supports_avx(), ""); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2954 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2955 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2956 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2957 //====================VECTOR ARITHMETIC===================================== |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2958 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2959 // Float-point vector arithmetic |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2960 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2961 void Assembler::addpd(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2962 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2963 emit_simd_arith(0x58, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2964 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2965 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2966 void Assembler::addps(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2967 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2968 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2969 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2970 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2971 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2972 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2973 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2974 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2975 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2976 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2977 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2978 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2979 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2980 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2981 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2982 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2983 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2984 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2985 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2986 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2987 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2988 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2989 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2990 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2991 void Assembler::subpd(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2992 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2993 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2994 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2995 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2996 void Assembler::subps(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2997 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2998 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2999 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3000 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3001 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3002 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3003 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3004 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3005 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3006 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3007 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3008 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3009 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3010 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3011 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3012 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3013 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3014 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3015 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3016 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3017 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3018 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3019 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3020 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3021 void Assembler::mulpd(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3022 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3023 emit_simd_arith(0x59, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3024 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3025 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3026 void Assembler::mulps(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3027 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3028 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3029 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3030 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3031 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3032 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3033 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3034 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3035 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3036 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3037 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3038 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3039 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3040 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3041 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3042 assert(VM_Version::supports_avx(), ""); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3043 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3044 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3045 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3046 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3047 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3048 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3049 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3050 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3051 void Assembler::divpd(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3052 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3053 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3054 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3055 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3056 void Assembler::divps(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3057 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3058 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3059 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3060 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3061 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3062 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3063 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3064 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3065 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3066 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3067 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3068 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3069 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3070 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3071 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3072 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3073 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3074 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3075 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3076 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3077 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3078 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3079 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3080 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3081 void Assembler::andpd(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3082 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3083 emit_simd_arith(0x54, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3084 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3085 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3086 void Assembler::andps(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3087 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3088 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3089 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3090 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3091 void Assembler::andps(XMMRegister dst, Address src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3092 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3093 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3094 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3095 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3096 void Assembler::andpd(XMMRegister dst, Address src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3097 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3098 emit_simd_arith(0x54, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3099 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3100 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3101 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3102 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3103 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3104 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3105 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3106 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3107 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3108 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3109 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3110 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3111 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3112 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3113 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3114 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3115 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3116 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3117 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3118 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3119 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3120 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3121 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3122 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3123 emit_simd_arith(0x57, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3124 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3125 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3126 void Assembler::xorps(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3127 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3128 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3129 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3130 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3131 void Assembler::xorpd(XMMRegister dst, Address src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3132 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3133 emit_simd_arith(0x57, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3134 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3135 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3136 void Assembler::xorps(XMMRegister dst, Address src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3137 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3138 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE); |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3139 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3140 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3141 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3142 assert(VM_Version::supports_avx(), ""); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3143 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256); |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3144 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3145 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3146 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3147 assert(VM_Version::supports_avx(), ""); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3148 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3149 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3150 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3151 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3152 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3153 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3154 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3155 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3156 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3157 assert(VM_Version::supports_avx(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3158 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3159 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3160 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3161 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3162 // Integer vector arithmetic |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3163 void Assembler::paddb(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3164 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3165 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3166 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3167 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3168 void Assembler::paddw(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3169 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3170 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3171 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3172 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3173 void Assembler::paddd(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3174 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3175 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3176 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3177 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3178 void Assembler::paddq(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3179 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3180 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3181 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3182 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3183 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3184 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3185 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3186 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3187 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3188 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3189 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3190 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3191 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3192 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3193 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3194 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3195 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3196 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3197 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3198 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3199 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3200 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3201 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3202 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3203 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3204 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3205 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3206 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3207 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3208 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3209 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3210 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3211 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3212 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3213 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3214 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3215 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3216 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3217 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3218 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3219 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3220 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3221 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3222 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3223 void Assembler::psubb(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3224 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3225 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3226 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3227 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3228 void Assembler::psubw(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3229 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3230 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3231 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3232 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3233 void Assembler::psubd(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3234 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3235 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3236 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3237 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3238 void Assembler::psubq(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3239 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3240 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3241 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3242 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3243 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3244 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3245 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3246 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3247 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3248 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3249 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3250 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3251 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3252 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3253 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3254 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3255 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3256 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3257 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3258 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3259 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3260 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3261 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3262 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3263 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3264 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3265 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3266 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3267 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3268 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3269 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3270 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3271 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3272 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3273 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3274 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3275 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3276 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3277 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3278 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3279 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3280 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3281 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3282 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3283 void Assembler::pmullw(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3284 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3285 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3286 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3287 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3288 void Assembler::pmulld(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3289 assert(VM_Version::supports_sse4_1(), ""); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3290 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3291 emit_int8(0x40); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3292 emit_int8((unsigned char)(0xC0 | encode)); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3293 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3294 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3295 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3296 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3297 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3298 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3299 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3300 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3301 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3302 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3303 emit_int8(0x40); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3304 emit_int8((unsigned char)(0xC0 | encode)); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3305 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3306 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3307 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3308 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3309 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3310 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3311 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3312 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3313 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3314 InstructionMark im(this); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3315 int dst_enc = dst->encoding(); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3316 int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3317 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3318 emit_int8(0x40); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3319 emit_operand(dst, src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3320 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3321 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3322 // Shift packed integers left by specified number of bits. |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3323 void Assembler::psllw(XMMRegister dst, int shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3324 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3325 // XMM6 is for /6 encoding: 66 0F 71 /6 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3326 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3327 emit_int8(0x71); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3328 emit_int8((unsigned char)(0xC0 | encode)); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3329 emit_int8(shift & 0xFF); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3330 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3331 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3332 void Assembler::pslld(XMMRegister dst, int shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3333 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3334 // XMM6 is for /6 encoding: 66 0F 72 /6 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3335 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3336 emit_int8(0x72); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3337 emit_int8((unsigned char)(0xC0 | encode)); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3338 emit_int8(shift & 0xFF); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3339 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3340 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3341 void Assembler::psllq(XMMRegister dst, int shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3342 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3343 // XMM6 is for /6 encoding: 66 0F 73 /6 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3344 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3345 emit_int8(0x73); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3346 emit_int8((unsigned char)(0xC0 | encode)); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3347 emit_int8(shift & 0xFF); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3348 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3349 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3350 void Assembler::psllw(XMMRegister dst, XMMRegister shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3351 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3352 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3353 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3354 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3355 void Assembler::pslld(XMMRegister dst, XMMRegister shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3356 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3357 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3358 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3359 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3360 void Assembler::psllq(XMMRegister dst, XMMRegister shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3361 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3362 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3363 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3364 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3365 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3366 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3367 // XMM6 is for /6 encoding: 66 0F 71 /6 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3368 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3369 emit_int8(shift & 0xFF); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3370 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3371 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3372 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3373 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3374 // XMM6 is for /6 encoding: 66 0F 72 /6 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3375 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3376 emit_int8(shift & 0xFF); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3377 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3378 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3379 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3380 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3381 // XMM6 is for /6 encoding: 66 0F 73 /6 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3382 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3383 emit_int8(shift & 0xFF); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3384 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3385 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3386 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3387 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3388 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3389 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3390 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3391 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3392 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3393 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3394 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3395 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3396 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3397 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3398 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3399 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3400 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3401 // Shift packed integers logically right by specified number of bits. |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3402 void Assembler::psrlw(XMMRegister dst, int shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3403 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3404 // XMM2 is for /2 encoding: 66 0F 71 /2 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3405 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3406 emit_int8(0x71); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3407 emit_int8((unsigned char)(0xC0 | encode)); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3408 emit_int8(shift & 0xFF); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3409 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3410 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3411 void Assembler::psrld(XMMRegister dst, int shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3412 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3413 // XMM2 is for /2 encoding: 66 0F 72 /2 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3414 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3415 emit_int8(0x72); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3416 emit_int8((unsigned char)(0xC0 | encode)); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3417 emit_int8(shift & 0xFF); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3418 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3419 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3420 void Assembler::psrlq(XMMRegister dst, int shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3421 // Do not confuse it with psrldq SSE2 instruction which |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3422 // shifts 128 bit value in xmm register by number of bytes. |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3423 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3424 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3425 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3426 emit_int8(0x73); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3427 emit_int8((unsigned char)(0xC0 | encode)); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3428 emit_int8(shift & 0xFF); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3429 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3430 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3431 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3432 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3433 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3434 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3435 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3436 void Assembler::psrld(XMMRegister dst, XMMRegister shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3437 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3438 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3439 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3440 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3441 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3442 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3443 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3444 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3445 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3446 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3447 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3448 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3449 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3450 emit_int8(shift & 0xFF); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3451 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3452 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3453 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3454 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3455 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3456 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3457 emit_int8(shift & 0xFF); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3458 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3459 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3460 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3461 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3462 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3463 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3464 emit_int8(shift & 0xFF); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3465 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3466 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3467 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3468 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3469 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3470 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3471 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3472 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3473 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3474 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3475 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3476 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3477 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3478 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3479 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3480 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3481 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3482 // Shift packed integers arithmetically right by specified number of bits. |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3483 void Assembler::psraw(XMMRegister dst, int shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3484 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3485 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3486 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3487 emit_int8(0x71); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3488 emit_int8((unsigned char)(0xC0 | encode)); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3489 emit_int8(shift & 0xFF); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3490 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3491 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3492 void Assembler::psrad(XMMRegister dst, int shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3493 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3494 // XMM4 is for /4 encoding: 66 0F 72 /4 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3495 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3496 emit_int8(0x72); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3497 emit_int8((unsigned char)(0xC0 | encode)); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3498 emit_int8(shift & 0xFF); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3499 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3500 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3501 void Assembler::psraw(XMMRegister dst, XMMRegister shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3502 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3503 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3504 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3505 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3506 void Assembler::psrad(XMMRegister dst, XMMRegister shift) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3507 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3508 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3509 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3510 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3511 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3512 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3513 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3514 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3515 emit_int8(shift & 0xFF); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3516 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3517 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3518 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3519 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3520 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3521 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3522 emit_int8(shift & 0xFF); |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3523 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3524 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3525 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3526 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3527 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3528 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3529 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3530 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3531 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3532 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3533 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3534 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3535 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3536 // AND packed integers |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3537 void Assembler::pand(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3538 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3539 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3540 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3541 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3542 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3543 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3544 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3545 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3546 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3547 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3548 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3549 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3550 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3551 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3552 void Assembler::por(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3553 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3554 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3555 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3556 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3557 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3558 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3559 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3560 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3561 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3562 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3563 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3564 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3565 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3566 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3567 void Assembler::pxor(XMMRegister dst, XMMRegister src) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3568 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3569 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3570 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3571 |
| 6225 | 3572 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3573 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3574 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3575 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3576 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3577 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3578 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3579 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3580 } |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3581 |
| 6225 | 3582 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3583 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3584 assert(VM_Version::supports_avx(), ""); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3585 bool vector256 = true; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3586 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3587 emit_int8(0x18); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3588 emit_int8((unsigned char)(0xC0 | encode)); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3589 // 0x00 - insert into lower 128 bits |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3590 // 0x01 - insert into upper 128 bits |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3591 emit_int8(0x01); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3592 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3593 |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3594 void Assembler::vinsertf128h(XMMRegister dst, Address src) { |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3595 assert(VM_Version::supports_avx(), ""); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3596 InstructionMark im(this); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3597 bool vector256 = true; |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3598 assert(dst != xnoreg, "sanity"); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3599 int dst_enc = dst->encoding(); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3600 // swap src<->dst for encoding |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3601 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3602 emit_int8(0x18); |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3603 emit_operand(dst, src); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3604 // 0x01 - insert into upper 128 bits |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3605 emit_int8(0x01); |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3606 } |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3607 |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3608 void Assembler::vextractf128h(Address dst, XMMRegister src) { |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3609 assert(VM_Version::supports_avx(), ""); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3610 InstructionMark im(this); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3611 bool vector256 = true; |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3612 assert(src != xnoreg, "sanity"); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3613 int src_enc = src->encoding(); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3614 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3615 emit_int8(0x19); |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3616 emit_operand(src, dst); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3617 // 0x01 - extract from upper 128 bits |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3618 emit_int8(0x01); |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3619 } |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3620 |
| 6225 | 3621 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
| 3622 assert(VM_Version::supports_avx2(), ""); | |
| 3623 bool vector256 = true; | |
| 3624 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3625 emit_int8(0x38); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3626 emit_int8((unsigned char)(0xC0 | encode)); |
| 6225 | 3627 // 0x00 - insert into lower 128 bits |
| 3628 // 0x01 - insert into upper 128 bits | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3629 emit_int8(0x01); |
| 6225 | 3630 } |
| 3631 | |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3632 void Assembler::vinserti128h(XMMRegister dst, Address src) { |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3633 assert(VM_Version::supports_avx2(), ""); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3634 InstructionMark im(this); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3635 bool vector256 = true; |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3636 assert(dst != xnoreg, "sanity"); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3637 int dst_enc = dst->encoding(); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3638 // swap src<->dst for encoding |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3639 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3640 emit_int8(0x38); |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3641 emit_operand(dst, src); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3642 // 0x01 - insert into upper 128 bits |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3643 emit_int8(0x01); |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3644 } |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3645 |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3646 void Assembler::vextracti128h(Address dst, XMMRegister src) { |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3647 assert(VM_Version::supports_avx2(), ""); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3648 InstructionMark im(this); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3649 bool vector256 = true; |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3650 assert(src != xnoreg, "sanity"); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3651 int src_enc = src->encoding(); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3652 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3653 emit_int8(0x39); |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3654 emit_operand(src, dst); |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3655 // 0x01 - extract from upper 128 bits |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3656 emit_int8(0x01); |
|
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3657 } |
|
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3658 |
|
7475
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3659 // duplicate 4-bytes integer data from src into 8 locations in dest |
|
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3660 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) { |
|
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3661 assert(VM_Version::supports_avx2(), ""); |
|
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3662 bool vector256 = true; |
|
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3663 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
|
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3664 emit_int8(0x58); |
|
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3665 emit_int8((unsigned char)(0xC0 | encode)); |
|
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3666 } |
|
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3667 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3668 void Assembler::vzeroupper() { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3669 assert(VM_Version::supports_avx(), ""); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3670 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3671 emit_int8(0x77); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3672 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3673 |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3674 |
| 304 | 3675 #ifndef _LP64 |
| 3676 // 32bit only pieces of the assembler | |
| 3677 | |
| 3678 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | |
| 3679 // NO PREFIX AS NEVER 64BIT | |
| 3680 InstructionMark im(this); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3681 emit_int8((unsigned char)0x81); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3682 emit_int8((unsigned char)(0xF8 | src1->encoding())); |
| 304 | 3683 emit_data(imm32, rspec, 0); |
| 3684 } | |
| 3685 | |
| 3686 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { | |
| 3687 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs | |
| 3688 InstructionMark im(this); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3689 emit_int8((unsigned char)0x81); |
| 304 | 3690 emit_operand(rdi, src1); |
| 3691 emit_data(imm32, rspec, 0); | |
| 3692 } | |
| 3693 | |
| 3694 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, | |
| 3695 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded | |
| 3696 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. | |
| 3697 void Assembler::cmpxchg8(Address adr) { | |
| 3698 InstructionMark im(this); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3699 emit_int8(0x0F); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3700 emit_int8((unsigned char)0xC7); |
| 304 | 3701 emit_operand(rcx, adr); |
| 3702 } | |
| 3703 | |
| 3704 void Assembler::decl(Register dst) { | |
| 3705 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3706 emit_int8(0x48 | dst->encoding()); |
| 304 | 3707 } |
| 3708 | |
| 3709 #endif // _LP64 | |
| 3710 | |
| 3711 // 64bit typically doesn't use the x87 but needs to for the trig funcs | |
| 3712 | |
| 3713 void Assembler::fabs() { | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3714 emit_int8((unsigned char)0xD9); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3715 emit_int8((unsigned char)0xE1); |
| 304 | 3716 } |
| 3717 | |
| 3718 void Assembler::fadd(int i) { | |
| 3719 emit_farith(0xD8, 0xC0, i); | |
| 3720 } | |
| 3721 | |
| 3722 void Assembler::fadd_d(Address src) { | |
| 3723 InstructionMark im(this); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3724 emit_int8((unsigned char)0xDC); |
| 304 | 3725 emit_operand32(rax, src); |
| 3726 } | |
| 3727 | |
| 3728 void Assembler::fadd_s(Address src) { | |
| 3729 InstructionMark im(this); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
3730 emit_int8((unsigned char)0xD8); |
| 304 | 3731 emit_operand32(rax, src); |
| 3732 } | |
| 3733 | |
| 3734 void Assembler::fadda(int i) { | |
| 3735 emit_farith(0xDC, 0xC0, i); | |
| 3736 } | |
| 3737 | |
| 3738 void Assembler::faddp(int i) { | |
| 3739 emit_farith(0xDE, 0xC0, i); | |
| 3740 } | |
| 3741 | |
| 3742 void Assembler::fchs() { | |
|
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changeset
|
3743 emit_int8((unsigned char)0xD9); |
|
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changeset
|
3744 emit_int8((unsigned char)0xE0); |
| 304 | 3745 } |
| 3746 | |
| 3747 void Assembler::fcom(int i) { | |
| 3748 emit_farith(0xD8, 0xD0, i); | |
| 3749 } | |
| 3750 | |
| 3751 void Assembler::fcomp(int i) { | |
| 3752 emit_farith(0xD8, 0xD8, i); | |
| 3753 } | |
| 3754 | |
| 3755 void Assembler::fcomp_d(Address src) { | |
| 3756 InstructionMark im(this); | |
|
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
3757 emit_int8((unsigned char)0xDC); |
| 304 | 3758 emit_operand32(rbx, src); |
| 3759 } | |
| 3760 | |
| 3761 void Assembler::fcomp_s(Address src) { | |
| 3762 InstructionMark im(this); | |
|
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
3763 emit_int8((unsigned char)0xD8); |
| 304 | 3764 emit_operand32(rbx, src); |
| 3765 } | |
| 3766 | |
| 3767 void Assembler::fcompp() { | |
|
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changeset
|
3768 emit_int8((unsigned char)0xDE); |
|
d02120b7a34f
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changeset
|
3769 emit_int8((unsigned char)0xD9); |
| 304 | 3770 } |
| 3771 | |
| 3772 void Assembler::fcos() { | |
|
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changeset
|
3773 emit_int8((unsigned char)0xD9); |
|
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changeset
|
3774 emit_int8((unsigned char)0xFF); |
| 304 | 3775 } |
| 3776 | |
| 3777 void Assembler::fdecstp() { | |
|
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changeset
|
3778 emit_int8((unsigned char)0xD9); |
|
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changeset
|
3779 emit_int8((unsigned char)0xF6); |
| 304 | 3780 } |
| 3781 | |
| 3782 void Assembler::fdiv(int i) { | |
| 3783 emit_farith(0xD8, 0xF0, i); | |
| 3784 } | |
| 3785 | |
| 3786 void Assembler::fdiv_d(Address src) { | |
| 3787 InstructionMark im(this); | |
|
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changeset
|
3788 emit_int8((unsigned char)0xDC); |
| 304 | 3789 emit_operand32(rsi, src); |
| 3790 } | |
| 3791 | |
| 3792 void Assembler::fdiv_s(Address src) { | |
| 3793 InstructionMark im(this); | |
|
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changeset
|
3794 emit_int8((unsigned char)0xD8); |
| 304 | 3795 emit_operand32(rsi, src); |
| 3796 } | |
| 3797 | |
| 3798 void Assembler::fdiva(int i) { | |
| 3799 emit_farith(0xDC, 0xF8, i); | |
| 3800 } | |
| 3801 | |
| 3802 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) | |
| 3803 // is erroneous for some of the floating-point instructions below. | |
| 3804 | |
| 3805 void Assembler::fdivp(int i) { | |
| 3806 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) | |
| 3807 } | |
| 3808 | |
| 3809 void Assembler::fdivr(int i) { | |
| 3810 emit_farith(0xD8, 0xF8, i); | |
| 3811 } | |
| 3812 | |
| 3813 void Assembler::fdivr_d(Address src) { | |
| 3814 InstructionMark im(this); | |
|
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changeset
|
3815 emit_int8((unsigned char)0xDC); |
| 304 | 3816 emit_operand32(rdi, src); |
| 3817 } | |
| 3818 | |
| 3819 void Assembler::fdivr_s(Address src) { | |
| 3820 InstructionMark im(this); | |
|
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
3821 emit_int8((unsigned char)0xD8); |
| 304 | 3822 emit_operand32(rdi, src); |
| 3823 } | |
| 3824 | |
| 3825 void Assembler::fdivra(int i) { | |
| 3826 emit_farith(0xDC, 0xF0, i); | |
| 3827 } | |
| 3828 | |
| 3829 void Assembler::fdivrp(int i) { | |
| 3830 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) | |
| 3831 } | |
| 3832 | |
| 3833 void Assembler::ffree(int i) { | |
| 3834 emit_farith(0xDD, 0xC0, i); | |
| 3835 } | |
| 3836 | |
| 3837 void Assembler::fild_d(Address adr) { | |
| 3838 InstructionMark im(this); | |
|
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
3839 emit_int8((unsigned char)0xDF); |
| 304 | 3840 emit_operand32(rbp, adr); |
| 3841 } | |
| 3842 | |
| 3843 void Assembler::fild_s(Address adr) { | |
| 3844 InstructionMark im(this); | |
|
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
3845 emit_int8((unsigned char)0xDB); |
| 304 | 3846 emit_operand32(rax, adr); |
| 3847 } | |
| 3848 | |
| 3849 void Assembler::fincstp() { | |
|
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changeset
|
3850 emit_int8((unsigned char)0xD9); |
|
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changeset
|
3851 emit_int8((unsigned char)0xF7); |
| 304 | 3852 } |
| 3853 | |
| 3854 void Assembler::finit() { | |
|
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changeset
|
3855 emit_int8((unsigned char)0x9B); |
|
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changeset
|
3856 emit_int8((unsigned char)0xDB); |
|
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changeset
|
3857 emit_int8((unsigned char)0xE3); |
| 304 | 3858 } |
| 3859 | |
| 3860 void Assembler::fist_s(Address adr) { | |
| 3861 InstructionMark im(this); | |
|
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
3862 emit_int8((unsigned char)0xDB); |
| 304 | 3863 emit_operand32(rdx, adr); |
| 3864 } | |
| 3865 | |
| 3866 void Assembler::fistp_d(Address adr) { | |
| 3867 InstructionMark im(this); | |
|
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changeset
|
3868 emit_int8((unsigned char)0xDF); |
| 304 | 3869 emit_operand32(rdi, adr); |
| 3870 } | |
| 3871 | |
| 3872 void Assembler::fistp_s(Address adr) { | |
| 3873 InstructionMark im(this); | |
|
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
3874 emit_int8((unsigned char)0xDB); |
| 304 | 3875 emit_operand32(rbx, adr); |
| 3876 } | |
| 0 | 3877 |
| 3878 void Assembler::fld1() { | |
|
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changeset
|
3879 emit_int8((unsigned char)0xD9); |
|
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changeset
|
3880 emit_int8((unsigned char)0xE8); |
| 0 | 3881 } |
| 3882 | |
| 304 | 3883 void Assembler::fld_d(Address adr) { |
| 3884 InstructionMark im(this); | |
|
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changeset
|
3885 emit_int8((unsigned char)0xDD); |
| 304 | 3886 emit_operand32(rax, adr); |
| 3887 } | |
| 0 | 3888 |
| 3889 void Assembler::fld_s(Address adr) { | |
| 3890 InstructionMark im(this); | |
|
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|
3891 emit_int8((unsigned char)0xD9); |
| 304 | 3892 emit_operand32(rax, adr); |
| 3893 } | |
| 3894 | |
| 3895 | |
| 3896 void Assembler::fld_s(int index) { | |
| 0 | 3897 emit_farith(0xD9, 0xC0, index); |
| 3898 } | |
| 3899 | |
| 3900 void Assembler::fld_x(Address adr) { | |
| 3901 InstructionMark im(this); | |
|
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changeset
|
3902 emit_int8((unsigned char)0xDB); |
| 304 | 3903 emit_operand32(rbp, adr); |
| 3904 } | |
| 3905 | |
| 3906 void Assembler::fldcw(Address src) { | |
| 3907 InstructionMark im(this); | |
|
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changeset
|
3908 emit_int8((unsigned char)0xD9); |
| 304 | 3909 emit_operand32(rbp, src); |
| 3910 } | |
| 3911 | |
| 3912 void Assembler::fldenv(Address src) { | |
| 0 | 3913 InstructionMark im(this); |
|
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changeset
|
3914 emit_int8((unsigned char)0xD9); |
| 304 | 3915 emit_operand32(rsp, src); |
| 3916 } | |
| 3917 | |
| 3918 void Assembler::fldlg2() { | |
|
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changeset
|
3919 emit_int8((unsigned char)0xD9); |
|
d02120b7a34f
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changeset
|
3920 emit_int8((unsigned char)0xEC); |
| 304 | 3921 } |
| 0 | 3922 |
| 3923 void Assembler::fldln2() { | |
|
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changeset
|
3924 emit_int8((unsigned char)0xD9); |
|
d02120b7a34f
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changeset
|
3925 emit_int8((unsigned char)0xED); |
| 0 | 3926 } |
| 3927 | |
| 304 | 3928 void Assembler::fldz() { |
|
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changeset
|
3929 emit_int8((unsigned char)0xD9); |
|
d02120b7a34f
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changeset
|
3930 emit_int8((unsigned char)0xEE); |
| 304 | 3931 } |
| 0 | 3932 |
| 3933 void Assembler::flog() { | |
| 3934 fldln2(); | |
| 3935 fxch(); | |
| 3936 fyl2x(); | |
| 3937 } | |
| 3938 | |
| 3939 void Assembler::flog10() { | |
| 3940 fldlg2(); | |
| 3941 fxch(); | |
| 3942 fyl2x(); | |
| 3943 } | |
| 3944 | |
| 304 | 3945 void Assembler::fmul(int i) { |
| 3946 emit_farith(0xD8, 0xC8, i); | |
| 3947 } | |
| 3948 | |
| 3949 void Assembler::fmul_d(Address src) { | |
| 3950 InstructionMark im(this); | |
|
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changeset
|
3951 emit_int8((unsigned char)0xDC); |
| 304 | 3952 emit_operand32(rcx, src); |
| 3953 } | |
| 3954 | |
| 3955 void Assembler::fmul_s(Address src) { | |
| 3956 InstructionMark im(this); | |
|
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
3957 emit_int8((unsigned char)0xD8); |
| 304 | 3958 emit_operand32(rcx, src); |
| 3959 } | |
| 3960 | |
| 3961 void Assembler::fmula(int i) { | |
| 3962 emit_farith(0xDC, 0xC8, i); | |
| 3963 } | |
| 3964 | |
| 3965 void Assembler::fmulp(int i) { | |
| 3966 emit_farith(0xDE, 0xC8, i); | |
| 3967 } | |
| 3968 | |
| 3969 void Assembler::fnsave(Address dst) { | |
| 3970 InstructionMark im(this); | |
|
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
3971 emit_int8((unsigned char)0xDD); |
| 304 | 3972 emit_operand32(rsi, dst); |
| 3973 } | |
| 3974 | |
| 3975 void Assembler::fnstcw(Address src) { | |
| 3976 InstructionMark im(this); | |
|
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
3977 emit_int8((unsigned char)0x9B); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
3978 emit_int8((unsigned char)0xD9); |
| 304 | 3979 emit_operand32(rdi, src); |
| 3980 } | |
| 3981 | |
| 3982 void Assembler::fnstsw_ax() { | |
|
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changeset
|
3983 emit_int8((unsigned char)0xDF); |
|
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changeset
|
3984 emit_int8((unsigned char)0xE0); |
| 304 | 3985 } |
| 3986 | |
| 3987 void Assembler::fprem() { | |
|
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changeset
|
3988 emit_int8((unsigned char)0xD9); |
|
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changeset
|
3989 emit_int8((unsigned char)0xF8); |
| 304 | 3990 } |
| 3991 | |
| 3992 void Assembler::fprem1() { | |
|
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changeset
|
3993 emit_int8((unsigned char)0xD9); |
|
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|
3994 emit_int8((unsigned char)0xF5); |
| 304 | 3995 } |
| 3996 | |
| 3997 void Assembler::frstor(Address src) { | |
| 3998 InstructionMark im(this); | |
|
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changeset
|
3999 emit_int8((unsigned char)0xDD); |
| 304 | 4000 emit_operand32(rsp, src); |
| 4001 } | |
| 0 | 4002 |
| 4003 void Assembler::fsin() { | |
|
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changeset
|
4004 emit_int8((unsigned char)0xD9); |
|
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|
4005 emit_int8((unsigned char)0xFE); |
| 0 | 4006 } |
| 4007 | |
| 304 | 4008 void Assembler::fsqrt() { |
|
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changeset
|
4009 emit_int8((unsigned char)0xD9); |
|
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changeset
|
4010 emit_int8((unsigned char)0xFA); |
| 304 | 4011 } |
| 4012 | |
| 4013 void Assembler::fst_d(Address adr) { | |
| 4014 InstructionMark im(this); | |
|
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changeset
|
4015 emit_int8((unsigned char)0xDD); |
| 304 | 4016 emit_operand32(rdx, adr); |
| 4017 } | |
| 4018 | |
| 4019 void Assembler::fst_s(Address adr) { | |
| 4020 InstructionMark im(this); | |
|
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changeset
|
4021 emit_int8((unsigned char)0xD9); |
| 304 | 4022 emit_operand32(rdx, adr); |
| 4023 } | |
| 4024 | |
| 4025 void Assembler::fstp_d(Address adr) { | |
| 4026 InstructionMark im(this); | |
|
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changeset
|
4027 emit_int8((unsigned char)0xDD); |
| 304 | 4028 emit_operand32(rbx, adr); |
| 4029 } | |
| 4030 | |
| 4031 void Assembler::fstp_d(int index) { | |
| 4032 emit_farith(0xDD, 0xD8, index); | |
| 4033 } | |
| 4034 | |
| 4035 void Assembler::fstp_s(Address adr) { | |
| 4036 InstructionMark im(this); | |
|
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changeset
|
4037 emit_int8((unsigned char)0xD9); |
| 304 | 4038 emit_operand32(rbx, adr); |
| 4039 } | |
| 4040 | |
| 4041 void Assembler::fstp_x(Address adr) { | |
| 4042 InstructionMark im(this); | |
|
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|
4043 emit_int8((unsigned char)0xDB); |
| 304 | 4044 emit_operand32(rdi, adr); |
| 4045 } | |
| 4046 | |
| 4047 void Assembler::fsub(int i) { | |
| 4048 emit_farith(0xD8, 0xE0, i); | |
| 4049 } | |
| 4050 | |
| 4051 void Assembler::fsub_d(Address src) { | |
| 4052 InstructionMark im(this); | |
|
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|
4053 emit_int8((unsigned char)0xDC); |
| 304 | 4054 emit_operand32(rsp, src); |
| 4055 } | |
| 4056 | |
| 4057 void Assembler::fsub_s(Address src) { | |
| 4058 InstructionMark im(this); | |
|
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|
4059 emit_int8((unsigned char)0xD8); |
| 304 | 4060 emit_operand32(rsp, src); |
| 4061 } | |
| 4062 | |
| 4063 void Assembler::fsuba(int i) { | |
| 4064 emit_farith(0xDC, 0xE8, i); | |
| 4065 } | |
| 4066 | |
| 4067 void Assembler::fsubp(int i) { | |
| 4068 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) | |
| 4069 } | |
| 4070 | |
| 4071 void Assembler::fsubr(int i) { | |
| 4072 emit_farith(0xD8, 0xE8, i); | |
| 4073 } | |
| 4074 | |
| 4075 void Assembler::fsubr_d(Address src) { | |
| 4076 InstructionMark im(this); | |
|
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|
4077 emit_int8((unsigned char)0xDC); |
| 304 | 4078 emit_operand32(rbp, src); |
| 4079 } | |
| 4080 | |
| 4081 void Assembler::fsubr_s(Address src) { | |
| 4082 InstructionMark im(this); | |
|
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|
4083 emit_int8((unsigned char)0xD8); |
| 304 | 4084 emit_operand32(rbp, src); |
| 4085 } | |
| 4086 | |
| 4087 void Assembler::fsubra(int i) { | |
| 4088 emit_farith(0xDC, 0xE0, i); | |
| 4089 } | |
| 4090 | |
| 4091 void Assembler::fsubrp(int i) { | |
| 4092 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) | |
| 0 | 4093 } |
| 4094 | |
| 4095 void Assembler::ftan() { | |
|
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|
4096 emit_int8((unsigned char)0xD9); |
|
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|
4097 emit_int8((unsigned char)0xF2); |
|
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|
4098 emit_int8((unsigned char)0xDD); |
|
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|
4099 emit_int8((unsigned char)0xD8); |
| 0 | 4100 } |
| 4101 | |
| 304 | 4102 void Assembler::ftst() { |
|
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|
4103 emit_int8((unsigned char)0xD9); |
|
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|
4104 emit_int8((unsigned char)0xE4); |
| 304 | 4105 } |
| 0 | 4106 |
| 4107 void Assembler::fucomi(int i) { | |
| 4108 // make sure the instruction is supported (introduced for P6, together with cmov) | |
| 4109 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
| 4110 emit_farith(0xDB, 0xE8, i); | |
| 4111 } | |
| 4112 | |
| 4113 void Assembler::fucomip(int i) { | |
| 4114 // make sure the instruction is supported (introduced for P6, together with cmov) | |
| 4115 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
| 4116 emit_farith(0xDF, 0xE8, i); | |
| 4117 } | |
| 4118 | |
| 4119 void Assembler::fwait() { | |
|
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|
4120 emit_int8((unsigned char)0x9B); |
| 0 | 4121 } |
| 4122 | |
| 304 | 4123 void Assembler::fxch(int i) { |
| 4124 emit_farith(0xD9, 0xC8, i); | |
| 4125 } | |
| 4126 | |
| 4127 void Assembler::fyl2x() { | |
|
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|
4128 emit_int8((unsigned char)0xD9); |
|
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|
4129 emit_int8((unsigned char)0xF1); |
| 304 | 4130 } |
| 4131 | |
|
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|
4132 void Assembler::frndint() { |
|
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|
4133 emit_int8((unsigned char)0xD9); |
|
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|
4134 emit_int8((unsigned char)0xFC); |
|
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|
4135 } |
|
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|
4136 |
|
6759698e3140
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|
4137 void Assembler::f2xm1() { |
|
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|
4138 emit_int8((unsigned char)0xD9); |
|
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|
4139 emit_int8((unsigned char)0xF0); |
|
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|
4140 } |
|
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|
4141 |
|
6759698e3140
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|
4142 void Assembler::fldl2e() { |
|
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|
4143 emit_int8((unsigned char)0xD9); |
|
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|
4144 emit_int8((unsigned char)0xEA); |
|
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|
4145 } |
|
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|
4146 |
| 4759 | 4147 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. |
| 4148 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; | |
| 4149 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. | |
| 4150 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; | |
| 4151 | |
| 4152 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. | |
| 4153 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
| 4154 if (pre > 0) { | |
|
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|
4155 emit_int8(simd_pre[pre]); |
| 4759 | 4156 } |
| 4157 if (rex_w) { | |
| 4158 prefixq(adr, xreg); | |
| 4159 } else { | |
| 4160 prefix(adr, xreg); | |
| 4161 } | |
| 4162 if (opc > 0) { | |
|
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|
4163 emit_int8(0x0F); |
| 4759 | 4164 int opc2 = simd_opc[opc]; |
| 4165 if (opc2 > 0) { | |
|
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|
4166 emit_int8(opc2); |
| 4759 | 4167 } |
| 4168 } | |
| 4169 } | |
| 4170 | |
| 4171 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
| 4172 if (pre > 0) { | |
|
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|
4173 emit_int8(simd_pre[pre]); |
| 4759 | 4174 } |
| 4175 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : | |
| 4176 prefix_and_encode(dst_enc, src_enc); | |
| 4177 if (opc > 0) { | |
|
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|
4178 emit_int8(0x0F); |
| 4759 | 4179 int opc2 = simd_opc[opc]; |
| 4180 if (opc2 > 0) { | |
|
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|
4181 emit_int8(opc2); |
| 4759 | 4182 } |
| 4183 } | |
| 4184 return encode; | |
| 4185 } | |
| 4186 | |
| 4187 | |
| 4188 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) { | |
| 4189 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { | |
| 4190 prefix(VEX_3bytes); | |
| 4191 | |
| 4192 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); | |
| 4193 byte1 = (~byte1) & 0xE0; | |
| 4194 byte1 |= opc; | |
|
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changeset
|
4195 emit_int8(byte1); |
| 4759 | 4196 |
| 4197 int byte2 = ((~nds_enc) & 0xf) << 3; | |
| 4198 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre; | |
|
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|
4199 emit_int8(byte2); |
| 4759 | 4200 } else { |
| 4201 prefix(VEX_2bytes); | |
| 4202 | |
| 4203 int byte1 = vex_r ? VEX_R : 0; | |
| 4204 byte1 = (~byte1) & 0x80; | |
| 4205 byte1 |= ((~nds_enc) & 0xf) << 3; | |
| 4206 byte1 |= (vector256 ? 4 : 0) | pre; | |
|
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changeset
|
4207 emit_int8(byte1); |
| 4759 | 4208 } |
| 4209 } | |
| 4210 | |
| 4211 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){ | |
| 4212 bool vex_r = (xreg_enc >= 8); | |
| 4213 bool vex_b = adr.base_needs_rex(); | |
| 4214 bool vex_x = adr.index_needs_rex(); | |
| 4215 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
| 4216 } | |
| 4217 | |
| 4218 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) { | |
| 4219 bool vex_r = (dst_enc >= 8); | |
| 4220 bool vex_b = (src_enc >= 8); | |
| 4221 bool vex_x = false; | |
| 4222 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
| 4223 return (((dst_enc & 7) << 3) | (src_enc & 7)); | |
| 4224 } | |
| 4225 | |
| 4226 | |
| 4227 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
| 4228 if (UseAVX > 0) { | |
| 4229 int xreg_enc = xreg->encoding(); | |
| 4230 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
| 4231 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256); | |
| 4232 } else { | |
| 4233 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); | |
| 4234 rex_prefix(adr, xreg, pre, opc, rex_w); | |
| 4235 } | |
| 4236 } | |
| 4237 | |
| 4238 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
| 4239 int dst_enc = dst->encoding(); | |
| 4240 int src_enc = src->encoding(); | |
| 4241 if (UseAVX > 0) { | |
| 4242 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
| 4243 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256); | |
| 4244 } else { | |
| 4245 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); | |
| 4246 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w); | |
| 4247 } | |
| 4248 } | |
| 304 | 4249 |
|
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|
4250 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { |
|
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|
4251 InstructionMark im(this); |
|
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|
4252 simd_prefix(dst, dst, src, pre); |
|
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|
4253 emit_int8(opcode); |
|
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|
4254 emit_operand(dst, src); |
|
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|
4255 } |
|
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|
4256 |
|
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|
4257 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { |
|
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|
4258 int encode = simd_prefix_and_encode(dst, dst, src, pre); |
|
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|
4259 emit_int8(opcode); |
|
d02120b7a34f
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|
4260 emit_int8((unsigned char)(0xC0 | encode)); |
|
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|
4261 } |
|
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|
4262 |
|
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changeset
|
4263 // Versions with no second source register (non-destructive source). |
|
006050192a5a
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changeset
|
4264 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { |
|
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|
4265 InstructionMark im(this); |
|
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|
4266 simd_prefix(dst, xnoreg, src, pre); |
|
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|
4267 emit_int8(opcode); |
|
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|
4268 emit_operand(dst, src); |
|
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|
4269 } |
|
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|
4270 |
|
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|
4271 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { |
|
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|
4272 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre); |
|
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changeset
|
4273 emit_int8(opcode); |
|
d02120b7a34f
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changeset
|
4274 emit_int8((unsigned char)(0xC0 | encode)); |
|
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|
4275 } |
|
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|
4276 |
|
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changeset
|
4277 // 3-operands AVX instructions |
|
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changeset
|
4278 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
|
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4279 Address src, VexSimdPrefix pre, bool vector256) { |
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4280 InstructionMark im(this); |
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|
4281 vex_prefix(dst, nds, src, pre, vector256); |
|
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|
4282 emit_int8(opcode); |
|
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4283 emit_operand(dst, src); |
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|
4284 } |
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|
4285 |
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|
4286 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
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4287 XMMRegister src, VexSimdPrefix pre, bool vector256) { |
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4288 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256); |
|
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|
4289 emit_int8(opcode); |
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|
4290 emit_int8((unsigned char)(0xC0 | encode)); |
|
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|
4291 } |
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|
4292 |
| 304 | 4293 #ifndef _LP64 |
| 4294 | |
| 4295 void Assembler::incl(Register dst) { | |
| 4296 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
|
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|
4297 emit_int8(0x40 | dst->encoding()); |
| 304 | 4298 } |
| 4299 | |
| 4300 void Assembler::lea(Register dst, Address src) { | |
| 4301 leal(dst, src); | |
| 4302 } | |
| 4303 | |
| 4304 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { | |
| 4305 InstructionMark im(this); | |
|
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|
4306 emit_int8((unsigned char)0xC7); |
| 304 | 4307 emit_operand(rax, dst); |
| 4308 emit_data((int)imm32, rspec, 0); | |
| 4309 } | |
| 4310 | |
|
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|
4311 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
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|
4312 InstructionMark im(this); |
|
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|
4313 int encode = prefix_and_encode(dst->encoding()); |
|
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|
4314 emit_int8((unsigned char)(0xB8 | encode)); |
|
642
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|
4315 emit_data((int)imm32, rspec, 0); |
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|
4316 } |
| 304 | 4317 |
| 4318 void Assembler::popa() { // 32bit | |
|
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|
4319 emit_int8(0x61); |
| 304 | 4320 } |
| 4321 | |
| 4322 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { | |
| 4323 InstructionMark im(this); | |
|
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|
4324 emit_int8(0x68); |
| 304 | 4325 emit_data(imm32, rspec, 0); |
| 4326 } | |
| 4327 | |
| 4328 void Assembler::pusha() { // 32bit | |
|
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|
4329 emit_int8(0x60); |
| 304 | 4330 } |
| 4331 | |
| 4332 void Assembler::set_byte_if_not_zero(Register dst) { | |
|
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|
4333 emit_int8(0x0F); |
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|
4334 emit_int8((unsigned char)0x95); |
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|
4335 emit_int8((unsigned char)(0xE0 | dst->encoding())); |
| 304 | 4336 } |
| 4337 | |
| 4338 void Assembler::shldl(Register dst, Register src) { | |
|
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|
4339 emit_int8(0x0F); |
|
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|
4340 emit_int8((unsigned char)0xA5); |
|
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|
4341 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); |
| 304 | 4342 } |
| 4343 | |
| 4344 void Assembler::shrdl(Register dst, Register src) { | |
|
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|
4345 emit_int8(0x0F); |
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|
4346 emit_int8((unsigned char)0xAD); |
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|
4347 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); |
| 304 | 4348 } |
| 4349 | |
| 4350 #else // LP64 | |
| 4351 | |
| 1369 | 4352 void Assembler::set_byte_if_not_zero(Register dst) { |
| 4353 int enc = prefix_and_encode(dst->encoding(), true); | |
|
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|
4354 emit_int8(0x0F); |
|
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|
4355 emit_int8((unsigned char)0x95); |
|
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|
4356 emit_int8((unsigned char)(0xE0 | enc)); |
| 1369 | 4357 } |
| 4358 | |
| 304 | 4359 // 64bit only pieces of the assembler |
| 4360 // This should only be used by 64bit instructions that can use rip-relative | |
| 4361 // it cannot be used by instructions that want an immediate value. | |
| 4362 | |
| 4363 bool Assembler::reachable(AddressLiteral adr) { | |
| 4364 int64_t disp; | |
| 4365 // None will force a 64bit literal to the code stream. Likely a placeholder | |
| 4366 // for something that will be patched later and we need to certain it will | |
| 4367 // always be reachable. | |
| 4368 if (adr.reloc() == relocInfo::none) { | |
| 4369 return false; | |
| 4370 } | |
| 4371 if (adr.reloc() == relocInfo::internal_word_type) { | |
| 4372 // This should be rip relative and easily reachable. | |
| 4373 return true; | |
| 4374 } | |
| 4375 if (adr.reloc() == relocInfo::virtual_call_type || | |
| 4376 adr.reloc() == relocInfo::opt_virtual_call_type || | |
| 4377 adr.reloc() == relocInfo::static_call_type || | |
| 4378 adr.reloc() == relocInfo::static_stub_type ) { | |
| 4379 // This should be rip relative within the code cache and easily | |
| 4380 // reachable until we get huge code caches. (At which point | |
| 4381 // ic code is going to have issues). | |
| 4382 return true; | |
| 4383 } | |
| 4384 if (adr.reloc() != relocInfo::external_word_type && | |
| 4385 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special | |
| 4386 adr.reloc() != relocInfo::poll_type && // relocs to identify them | |
| 4387 adr.reloc() != relocInfo::runtime_call_type ) { | |
| 4388 return false; | |
| 4389 } | |
| 4390 | |
| 4391 // Stress the correction code | |
| 4392 if (ForceUnreachable) { | |
| 4393 // Must be runtimecall reloc, see if it is in the codecache | |
| 4394 // Flipping stuff in the codecache to be unreachable causes issues | |
| 4395 // with things like inline caches where the additional instructions | |
| 4396 // are not handled. | |
| 4397 if (CodeCache::find_blob(adr._target) == NULL) { | |
| 4398 return false; | |
| 4399 } | |
| 4400 } | |
| 4401 // For external_word_type/runtime_call_type if it is reachable from where we | |
| 4402 // are now (possibly a temp buffer) and where we might end up | |
| 4403 // anywhere in the codeCache then we are always reachable. | |
| 4404 // This would have to change if we ever save/restore shared code | |
| 4405 // to be more pessimistic. | |
| 4406 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); | |
| 4407 if (!is_simm32(disp)) return false; | |
| 4408 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); | |
| 4409 if (!is_simm32(disp)) return false; | |
| 4410 | |
|
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|
4411 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int)); |
| 304 | 4412 |
| 4413 // Because rip relative is a disp + address_of_next_instruction and we | |
| 4414 // don't know the value of address_of_next_instruction we apply a fudge factor | |
| 4415 // to make sure we will be ok no matter the size of the instruction we get placed into. | |
| 4416 // We don't have to fudge the checks above here because they are already worst case. | |
| 4417 | |
| 4418 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal | |
| 4419 // + 4 because better safe than sorry. | |
| 4420 const int fudge = 12 + 4; | |
| 4421 if (disp < 0) { | |
| 4422 disp -= fudge; | |
| 4423 } else { | |
| 4424 disp += fudge; | |
| 4425 } | |
| 4426 return is_simm32(disp); | |
| 4427 } | |
| 4428 | |
|
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changeset
|
4429 // Check if the polling page is not reachable from the code cache using rip-relative |
|
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|
4430 // addressing. |
|
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|
4431 bool Assembler::is_polling_page_far() { |
|
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|
4432 intptr_t addr = (intptr_t)os::get_polling_page(); |
|
4118
59bc0d4d9ea3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
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3938
diff
changeset
|
4433 return ForceUnreachable || |
|
59bc0d4d9ea3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
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3938
diff
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|
4434 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) || |
|
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|
4435 !is_simm32(addr - (intptr_t)CodeCache::high_bound()); |
|
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|
4436 } |
|
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|
4437 |
| 304 | 4438 void Assembler::emit_data64(jlong data, |
| 4439 relocInfo::relocType rtype, | |
| 4440 int format) { | |
| 4441 if (rtype == relocInfo::none) { | |
|
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|
4442 emit_int64(data); |
| 304 | 4443 } else { |
| 4444 emit_data64(data, Relocation::spec_simple(rtype), format); | |
| 4445 } | |
| 4446 } | |
| 4447 | |
| 4448 void Assembler::emit_data64(jlong data, | |
| 4449 RelocationHolder const& rspec, | |
| 4450 int format) { | |
| 4451 assert(imm_operand == 0, "default format must be immediate in this file"); | |
| 4452 assert(imm_operand == format, "must be immediate"); | |
| 4453 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
| 4454 // Do not use AbstractAssembler::relocate, which is not intended for | |
| 4455 // embedded words. Instead, relocate to the enclosing instruction. | |
| 4456 code_section()->relocate(inst_mark(), rspec, format); | |
| 4457 #ifdef ASSERT | |
| 4458 check_relocation(rspec, format); | |
| 4459 #endif | |
|
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|
4460 emit_int64(data); |
| 304 | 4461 } |
| 4462 | |
| 4463 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { | |
| 4464 if (reg_enc >= 8) { | |
| 4465 prefix(REX_B); | |
| 4466 reg_enc -= 8; | |
| 4467 } else if (byteinst && reg_enc >= 4) { | |
| 4468 prefix(REX); | |
| 4469 } | |
| 4470 return reg_enc; | |
| 4471 } | |
| 4472 | |
| 4473 int Assembler::prefixq_and_encode(int reg_enc) { | |
| 4474 if (reg_enc < 8) { | |
| 4475 prefix(REX_W); | |
| 4476 } else { | |
| 4477 prefix(REX_WB); | |
| 4478 reg_enc -= 8; | |
| 4479 } | |
| 4480 return reg_enc; | |
| 4481 } | |
| 4482 | |
| 4483 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { | |
| 4484 if (dst_enc < 8) { | |
| 4485 if (src_enc >= 8) { | |
| 4486 prefix(REX_B); | |
| 4487 src_enc -= 8; | |
| 4488 } else if (byteinst && src_enc >= 4) { | |
| 4489 prefix(REX); | |
| 4490 } | |
| 4491 } else { | |
| 4492 if (src_enc < 8) { | |
| 4493 prefix(REX_R); | |
| 4494 } else { | |
| 4495 prefix(REX_RB); | |
| 4496 src_enc -= 8; | |
| 4497 } | |
| 4498 dst_enc -= 8; | |
| 4499 } | |
| 4500 return dst_enc << 3 | src_enc; | |
| 4501 } | |
| 4502 | |
| 4503 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { | |
| 4504 if (dst_enc < 8) { | |
| 4505 if (src_enc < 8) { | |
| 4506 prefix(REX_W); | |
| 4507 } else { | |
| 4508 prefix(REX_WB); | |
| 4509 src_enc -= 8; | |
| 4510 } | |
| 4511 } else { | |
| 4512 if (src_enc < 8) { | |
| 4513 prefix(REX_WR); | |
| 4514 } else { | |
| 4515 prefix(REX_WRB); | |
| 4516 src_enc -= 8; | |
| 4517 } | |
| 4518 dst_enc -= 8; | |
| 4519 } | |
| 4520 return dst_enc << 3 | src_enc; | |
| 4521 } | |
| 4522 | |
| 4523 void Assembler::prefix(Register reg) { | |
| 4524 if (reg->encoding() >= 8) { | |
| 4525 prefix(REX_B); | |
| 4526 } | |
| 4527 } | |
| 4528 | |
| 4529 void Assembler::prefix(Address adr) { | |
| 4530 if (adr.base_needs_rex()) { | |
| 4531 if (adr.index_needs_rex()) { | |
| 4532 prefix(REX_XB); | |
| 4533 } else { | |
| 4534 prefix(REX_B); | |
| 4535 } | |
| 4536 } else { | |
| 4537 if (adr.index_needs_rex()) { | |
| 4538 prefix(REX_X); | |
| 4539 } | |
| 4540 } | |
| 4541 } | |
| 4542 | |
| 4543 void Assembler::prefixq(Address adr) { | |
| 4544 if (adr.base_needs_rex()) { | |
| 4545 if (adr.index_needs_rex()) { | |
| 4546 prefix(REX_WXB); | |
| 4547 } else { | |
| 4548 prefix(REX_WB); | |
| 4549 } | |
| 4550 } else { | |
| 4551 if (adr.index_needs_rex()) { | |
| 4552 prefix(REX_WX); | |
| 4553 } else { | |
| 4554 prefix(REX_W); | |
| 4555 } | |
| 4556 } | |
| 4557 } | |
| 4558 | |
| 4559 | |
| 4560 void Assembler::prefix(Address adr, Register reg, bool byteinst) { | |
| 4561 if (reg->encoding() < 8) { | |
| 4562 if (adr.base_needs_rex()) { | |
| 4563 if (adr.index_needs_rex()) { | |
| 4564 prefix(REX_XB); | |
| 4565 } else { | |
| 4566 prefix(REX_B); | |
| 4567 } | |
| 4568 } else { | |
| 4569 if (adr.index_needs_rex()) { | |
| 4570 prefix(REX_X); | |
| 3855 | 4571 } else if (byteinst && reg->encoding() >= 4 ) { |
| 304 | 4572 prefix(REX); |
| 4573 } | |
| 4574 } | |
| 4575 } else { | |
| 4576 if (adr.base_needs_rex()) { | |
| 4577 if (adr.index_needs_rex()) { | |
| 4578 prefix(REX_RXB); | |
| 4579 } else { | |
| 4580 prefix(REX_RB); | |
| 4581 } | |
| 4582 } else { | |
| 4583 if (adr.index_needs_rex()) { | |
| 4584 prefix(REX_RX); | |
| 4585 } else { | |
| 4586 prefix(REX_R); | |
| 4587 } | |
| 4588 } | |
| 4589 } | |
| 4590 } | |
| 4591 | |
| 4592 void Assembler::prefixq(Address adr, Register src) { | |
| 4593 if (src->encoding() < 8) { | |
| 4594 if (adr.base_needs_rex()) { | |
| 4595 if (adr.index_needs_rex()) { | |
| 4596 prefix(REX_WXB); | |
| 4597 } else { | |
| 4598 prefix(REX_WB); | |
| 4599 } | |
| 4600 } else { | |
| 4601 if (adr.index_needs_rex()) { | |
| 4602 prefix(REX_WX); | |
| 4603 } else { | |
| 4604 prefix(REX_W); | |
| 4605 } | |
| 4606 } | |
| 4607 } else { | |
| 4608 if (adr.base_needs_rex()) { | |
| 4609 if (adr.index_needs_rex()) { | |
| 4610 prefix(REX_WRXB); | |
| 4611 } else { | |
| 4612 prefix(REX_WRB); | |
| 4613 } | |
| 4614 } else { | |
| 4615 if (adr.index_needs_rex()) { | |
| 4616 prefix(REX_WRX); | |
| 4617 } else { | |
| 4618 prefix(REX_WR); | |
| 4619 } | |
| 4620 } | |
| 4621 } | |
| 4622 } | |
| 4623 | |
| 4624 void Assembler::prefix(Address adr, XMMRegister reg) { | |
| 4625 if (reg->encoding() < 8) { | |
| 4626 if (adr.base_needs_rex()) { | |
| 4627 if (adr.index_needs_rex()) { | |
| 4628 prefix(REX_XB); | |
| 4629 } else { | |
| 4630 prefix(REX_B); | |
| 4631 } | |
| 4632 } else { | |
| 4633 if (adr.index_needs_rex()) { | |
| 4634 prefix(REX_X); | |
| 4635 } | |
| 4636 } | |
| 4637 } else { | |
| 4638 if (adr.base_needs_rex()) { | |
| 4639 if (adr.index_needs_rex()) { | |
| 4640 prefix(REX_RXB); | |
| 4641 } else { | |
| 4642 prefix(REX_RB); | |
| 4643 } | |
| 4644 } else { | |
| 4645 if (adr.index_needs_rex()) { | |
| 4646 prefix(REX_RX); | |
| 4647 } else { | |
| 4648 prefix(REX_R); | |
| 4649 } | |
| 4650 } | |
| 4651 } | |
| 4652 } | |
| 4653 | |
| 4759 | 4654 void Assembler::prefixq(Address adr, XMMRegister src) { |
| 4655 if (src->encoding() < 8) { | |
| 4656 if (adr.base_needs_rex()) { | |
| 4657 if (adr.index_needs_rex()) { | |
| 4658 prefix(REX_WXB); | |
| 4659 } else { | |
| 4660 prefix(REX_WB); | |
| 4661 } | |
| 4662 } else { | |
| 4663 if (adr.index_needs_rex()) { | |
| 4664 prefix(REX_WX); | |
| 4665 } else { | |
| 4666 prefix(REX_W); | |
| 4667 } | |
| 4668 } | |
| 4669 } else { | |
| 4670 if (adr.base_needs_rex()) { | |
| 4671 if (adr.index_needs_rex()) { | |
| 4672 prefix(REX_WRXB); | |
| 4673 } else { | |
| 4674 prefix(REX_WRB); | |
| 4675 } | |
| 4676 } else { | |
| 4677 if (adr.index_needs_rex()) { | |
| 4678 prefix(REX_WRX); | |
| 4679 } else { | |
| 4680 prefix(REX_WR); | |
| 4681 } | |
| 4682 } | |
| 4683 } | |
| 4684 } | |
| 4685 | |
| 304 | 4686 void Assembler::adcq(Register dst, int32_t imm32) { |
| 4687 (void) prefixq_and_encode(dst->encoding()); | |
| 4688 emit_arith(0x81, 0xD0, dst, imm32); | |
| 4689 } | |
| 4690 | |
| 4691 void Assembler::adcq(Register dst, Address src) { | |
| 4692 InstructionMark im(this); | |
| 4693 prefixq(src, dst); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4694 emit_int8(0x13); |
| 304 | 4695 emit_operand(dst, src); |
| 4696 } | |
| 4697 | |
| 4698 void Assembler::adcq(Register dst, Register src) { | |
| 4699 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4700 emit_arith(0x13, 0xC0, dst, src); | |
| 4701 } | |
| 4702 | |
| 4703 void Assembler::addq(Address dst, int32_t imm32) { | |
| 4704 InstructionMark im(this); | |
| 4705 prefixq(dst); | |
| 4706 emit_arith_operand(0x81, rax, dst,imm32); | |
| 4707 } | |
| 4708 | |
| 4709 void Assembler::addq(Address dst, Register src) { | |
| 4710 InstructionMark im(this); | |
| 4711 prefixq(dst, src); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4712 emit_int8(0x01); |
| 304 | 4713 emit_operand(src, dst); |
| 4714 } | |
| 4715 | |
| 4716 void Assembler::addq(Register dst, int32_t imm32) { | |
| 4717 (void) prefixq_and_encode(dst->encoding()); | |
| 4718 emit_arith(0x81, 0xC0, dst, imm32); | |
| 4719 } | |
| 4720 | |
| 4721 void Assembler::addq(Register dst, Address src) { | |
| 4722 InstructionMark im(this); | |
| 4723 prefixq(src, dst); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4724 emit_int8(0x03); |
| 304 | 4725 emit_operand(dst, src); |
| 4726 } | |
| 4727 | |
| 4728 void Assembler::addq(Register dst, Register src) { | |
| 4729 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4730 emit_arith(0x03, 0xC0, dst, src); | |
| 4731 } | |
| 4732 | |
| 3783 | 4733 void Assembler::andq(Address dst, int32_t imm32) { |
| 4734 InstructionMark im(this); | |
| 4735 prefixq(dst); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4736 emit_int8((unsigned char)0x81); |
| 3783 | 4737 emit_operand(rsp, dst, 4); |
|
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
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7475
diff
changeset
|
4738 emit_int32(imm32); |
| 3783 | 4739 } |
| 4740 | |
| 304 | 4741 void Assembler::andq(Register dst, int32_t imm32) { |
| 4742 (void) prefixq_and_encode(dst->encoding()); | |
| 4743 emit_arith(0x81, 0xE0, dst, imm32); | |
| 4744 } | |
| 4745 | |
| 4746 void Assembler::andq(Register dst, Address src) { | |
| 4747 InstructionMark im(this); | |
| 4748 prefixq(src, dst); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4749 emit_int8(0x23); |
| 304 | 4750 emit_operand(dst, src); |
| 4751 } | |
| 4752 | |
| 4753 void Assembler::andq(Register dst, Register src) { | |
| 4754 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4755 emit_arith(0x23, 0xC0, dst, src); | |
| 4756 } | |
| 4757 | |
|
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93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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710
diff
changeset
|
4758 void Assembler::bsfq(Register dst, Register src) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
|
4759 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4760 emit_int8(0x0F); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4761 emit_int8((unsigned char)0xBC); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4762 emit_int8((unsigned char)(0xC0 | encode)); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4763 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4764 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4765 void Assembler::bsrq(Register dst, Register src) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4766 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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710
diff
changeset
|
4767 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4768 emit_int8(0x0F); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4769 emit_int8((unsigned char)0xBD); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4770 emit_int8((unsigned char)(0xC0 | encode)); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4771 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4772 |
| 304 | 4773 void Assembler::bswapq(Register reg) { |
| 4774 int encode = prefixq_and_encode(reg->encoding()); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4775 emit_int8(0x0F); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4776 emit_int8((unsigned char)(0xC8 | encode)); |
| 304 | 4777 } |
| 4778 | |
| 4779 void Assembler::cdqq() { | |
| 4780 prefix(REX_W); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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diff
changeset
|
4781 emit_int8((unsigned char)0x99); |
| 304 | 4782 } |
| 4783 | |
| 4784 void Assembler::clflush(Address adr) { | |
| 4785 prefix(adr); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4786 emit_int8(0x0F); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4787 emit_int8((unsigned char)0xAE); |
| 304 | 4788 emit_operand(rdi, adr); |
| 4789 } | |
| 4790 | |
| 4791 void Assembler::cmovq(Condition cc, Register dst, Register src) { | |
| 4792 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4793 emit_int8(0x0F); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4794 emit_int8(0x40 | cc); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4795 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 4796 } |
| 4797 | |
| 4798 void Assembler::cmovq(Condition cc, Register dst, Address src) { | |
| 4799 InstructionMark im(this); | |
| 4800 prefixq(src, dst); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4801 emit_int8(0x0F); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4802 emit_int8(0x40 | cc); |
| 304 | 4803 emit_operand(dst, src); |
| 4804 } | |
| 4805 | |
| 4806 void Assembler::cmpq(Address dst, int32_t imm32) { | |
| 4807 InstructionMark im(this); | |
| 4808 prefixq(dst); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4809 emit_int8((unsigned char)0x81); |
| 304 | 4810 emit_operand(rdi, dst, 4); |
|
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
twisti
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7475
diff
changeset
|
4811 emit_int32(imm32); |
| 304 | 4812 } |
| 4813 | |
| 4814 void Assembler::cmpq(Register dst, int32_t imm32) { | |
| 4815 (void) prefixq_and_encode(dst->encoding()); | |
| 4816 emit_arith(0x81, 0xF8, dst, imm32); | |
| 4817 } | |
| 4818 | |
| 4819 void Assembler::cmpq(Address dst, Register src) { | |
| 4820 InstructionMark im(this); | |
| 4821 prefixq(dst, src); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4822 emit_int8(0x3B); |
| 304 | 4823 emit_operand(src, dst); |
| 4824 } | |
| 4825 | |
| 4826 void Assembler::cmpq(Register dst, Register src) { | |
| 4827 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4828 emit_arith(0x3B, 0xC0, dst, src); | |
| 4829 } | |
| 4830 | |
| 4831 void Assembler::cmpq(Register dst, Address src) { | |
| 4832 InstructionMark im(this); | |
| 4833 prefixq(src, dst); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4834 emit_int8(0x3B); |
| 304 | 4835 emit_operand(dst, src); |
| 4836 } | |
| 4837 | |
| 4838 void Assembler::cmpxchgq(Register reg, Address adr) { | |
| 4839 InstructionMark im(this); | |
| 4840 prefixq(adr, reg); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4841 emit_int8(0x0F); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4842 emit_int8((unsigned char)0xB1); |
| 304 | 4843 emit_operand(reg, adr); |
| 4844 } | |
| 4845 | |
| 4846 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | |
| 4847 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 4848 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4849 emit_int8(0x2A); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4850 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 4851 } |
| 4852 | |
| 4759 | 4853 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { |
| 4854 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4855 InstructionMark im(this); | |
| 4856 simd_prefix_q(dst, dst, src, VEX_SIMD_F2); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4857 emit_int8(0x2A); |
| 4759 | 4858 emit_operand(dst, src); |
| 4859 } | |
| 4860 | |
| 304 | 4861 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { |
| 4862 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 4863 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
4864 emit_int8(0x2A); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4865 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 4866 } |
| 4867 | |
| 4759 | 4868 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { |
| 4869 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4870 InstructionMark im(this); | |
| 4871 simd_prefix_q(dst, dst, src, VEX_SIMD_F3); | |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4872 emit_int8(0x2A); |
| 4759 | 4873 emit_operand(dst, src); |
| 4874 } | |
| 4875 | |
| 304 | 4876 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { |
| 4877 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 4878 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4879 emit_int8(0x2C); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4880 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 4881 } |
| 4882 | |
| 4883 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | |
| 4884 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 4885 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3); |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4886 emit_int8(0x2C); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4887 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 4888 } |
| 4889 | |
| 4890 void Assembler::decl(Register dst) { | |
| 4891 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
| 4892 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) | |
| 4893 int encode = prefix_and_encode(dst->encoding()); | |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4894 emit_int8((unsigned char)0xFF); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4895 emit_int8((unsigned char)(0xC8 | encode)); |
| 304 | 4896 } |
| 4897 | |
| 4898 void Assembler::decq(Register dst) { | |
| 4899 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
| 4900 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 4901 int encode = prefixq_and_encode(dst->encoding()); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4902 emit_int8((unsigned char)0xFF); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4903 emit_int8(0xC8 | encode); |
| 304 | 4904 } |
| 4905 | |
| 4906 void Assembler::decq(Address dst) { | |
| 4907 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
| 4908 InstructionMark im(this); | |
| 4909 prefixq(dst); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4910 emit_int8((unsigned char)0xFF); |
| 304 | 4911 emit_operand(rcx, dst); |
| 4912 } | |
| 4913 | |
| 4914 void Assembler::fxrstor(Address src) { | |
| 4915 prefixq(src); | |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4916 emit_int8(0x0F); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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diff
changeset
|
4917 emit_int8((unsigned char)0xAE); |
| 304 | 4918 emit_operand(as_Register(1), src); |
| 4919 } | |
| 4920 | |
| 4921 void Assembler::fxsave(Address dst) { | |
| 4922 prefixq(dst); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
4923 emit_int8(0x0F); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4924 emit_int8((unsigned char)0xAE); |
| 304 | 4925 emit_operand(as_Register(0), dst); |
| 4926 } | |
| 4927 | |
| 4928 void Assembler::idivq(Register src) { | |
| 4929 int encode = prefixq_and_encode(src->encoding()); | |
|
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4930 emit_int8((unsigned char)0xF7); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4931 emit_int8((unsigned char)(0xF8 | encode)); |
| 304 | 4932 } |
| 4933 | |
| 4934 void Assembler::imulq(Register dst, Register src) { | |
| 4935 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4936 emit_int8(0x0F); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
4937 emit_int8((unsigned char)0xAF); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4938 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 4939 } |
| 4940 | |
| 4941 void Assembler::imulq(Register dst, Register src, int value) { | |
| 4942 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4943 if (is8bit(value)) { | |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4944 emit_int8(0x6B); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4945 emit_int8((unsigned char)(0xC0 | encode)); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4946 emit_int8(value & 0xFF); |
| 304 | 4947 } else { |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4948 emit_int8(0x69); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
4949 emit_int8((unsigned char)(0xC0 | encode)); |
|
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
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7475
diff
changeset
|
4950 emit_int32(value); |
| 304 | 4951 } |
| 4952 } | |
| 4953 | |
| 4954 void Assembler::incl(Register dst) { | |
| 4955 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
| 4956 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 4957 int encode = prefix_and_encode(dst->encoding()); | |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4958 emit_int8((unsigned char)0xFF); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4959 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 4960 } |
| 4961 | |
| 4962 void Assembler::incq(Register dst) { | |
| 4963 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
| 4964 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 4965 int encode = prefixq_and_encode(dst->encoding()); | |
|
7430
d02120b7a34f
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7427
diff
changeset
|
4966 emit_int8((unsigned char)0xFF); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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diff
changeset
|
4967 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 4968 } |
| 4969 | |
| 4970 void Assembler::incq(Address dst) { | |
| 4971 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
| 4972 InstructionMark im(this); | |
| 4973 prefixq(dst); | |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4974 emit_int8((unsigned char)0xFF); |
| 304 | 4975 emit_operand(rax, dst); |
| 4976 } | |
| 4977 | |
| 4978 void Assembler::lea(Register dst, Address src) { | |
| 4979 leaq(dst, src); | |
| 4980 } | |
| 4981 | |
| 4982 void Assembler::leaq(Register dst, Address src) { | |
| 4983 InstructionMark im(this); | |
| 4984 prefixq(src, dst); | |
|
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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diff
changeset
|
4985 emit_int8((unsigned char)0x8D); |
| 304 | 4986 emit_operand(dst, src); |
| 4987 } | |
| 4988 | |
| 4989 void Assembler::mov64(Register dst, int64_t imm64) { | |
| 4990 InstructionMark im(this); | |
| 4991 int encode = prefixq_and_encode(dst->encoding()); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4992 emit_int8((unsigned char)(0xB8 | encode)); |
|
7198
6ab62ad83507
8003195: AbstractAssembler should not store code pointers but use the CodeSection directly
twisti
parents:
6894
diff
changeset
|
4993 emit_int64(imm64); |
| 304 | 4994 } |
| 4995 | |
| 4996 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { | |
| 4997 InstructionMark im(this); | |
| 4998 int encode = prefixq_and_encode(dst->encoding()); | |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4999 emit_int8(0xB8 | encode); |
| 304 | 5000 emit_data64(imm64, rspec); |
| 5001 } | |
| 5002 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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parents:
624
diff
changeset
|
5003 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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diff
changeset
|
5004 InstructionMark im(this); |
|
660978a2a31a
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parents:
624
diff
changeset
|
5005 int encode = prefix_and_encode(dst->encoding()); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5006 emit_int8((unsigned char)(0xB8 | encode)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5007 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5008 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5009 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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parents:
624
diff
changeset
|
5010 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5011 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5012 prefix(dst); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5013 emit_int8((unsigned char)0xC7); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5014 emit_operand(rax, dst, 4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5015 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5016 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5017 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5018 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5019 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5020 int encode = prefix_and_encode(src1->encoding()); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
5021 emit_int8((unsigned char)0x81); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5022 emit_int8((unsigned char)(0xF8 | encode)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5023 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5024 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5025 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5026 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5027 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5028 prefix(src1); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5029 emit_int8((unsigned char)0x81); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5030 emit_operand(rax, src1, 4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5031 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5032 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5033 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
5034 void Assembler::lzcntq(Register dst, Register src) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
5035 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5036 emit_int8((unsigned char)0xF3); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
5037 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5038 emit_int8(0x0F); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5039 emit_int8((unsigned char)0xBD); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5040 emit_int8((unsigned char)(0xC0 | encode)); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
5041 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
5042 |
| 304 | 5043 void Assembler::movdq(XMMRegister dst, Register src) { |
| 5044 // table D-1 says MMX/SSE2 | |
| 4759 | 5045 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
| 5046 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5047 emit_int8(0x6E); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5048 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 5049 } |
| 5050 | |
| 5051 void Assembler::movdq(Register dst, XMMRegister src) { | |
| 5052 // table D-1 says MMX/SSE2 | |
| 4759 | 5053 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
| 304 | 5054 // swap src/dst to get correct prefix |
| 4759 | 5055 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66); |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5056 emit_int8(0x7E); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5057 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 5058 } |
| 5059 | |
| 5060 void Assembler::movq(Register dst, Register src) { | |
| 5061 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
5062 emit_int8((unsigned char)0x8B); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5063 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 5064 } |
| 5065 | |
| 5066 void Assembler::movq(Register dst, Address src) { | |
| 5067 InstructionMark im(this); | |
| 5068 prefixq(src, dst); | |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5069 emit_int8((unsigned char)0x8B); |
| 304 | 5070 emit_operand(dst, src); |
| 5071 } | |
| 5072 | |
| 5073 void Assembler::movq(Address dst, Register src) { | |
| 5074 InstructionMark im(this); | |
| 5075 prefixq(dst, src); | |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5076 emit_int8((unsigned char)0x89); |
| 304 | 5077 emit_operand(src, dst); |
| 5078 } | |
| 5079 | |
| 624 | 5080 void Assembler::movsbq(Register dst, Address src) { |
| 5081 InstructionMark im(this); | |
| 5082 prefixq(src, dst); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5083 emit_int8(0x0F); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5084 emit_int8((unsigned char)0xBE); |
| 624 | 5085 emit_operand(dst, src); |
| 5086 } | |
| 5087 | |
| 5088 void Assembler::movsbq(Register dst, Register src) { | |
| 5089 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5090 emit_int8(0x0F); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5091 emit_int8((unsigned char)0xBE); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5092 emit_int8((unsigned char)(0xC0 | encode)); |
| 624 | 5093 } |
| 5094 | |
| 304 | 5095 void Assembler::movslq(Register dst, int32_t imm32) { |
| 5096 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) | |
| 5097 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) | |
| 5098 // as a result we shouldn't use until tested at runtime... | |
| 5099 ShouldNotReachHere(); | |
| 5100 InstructionMark im(this); | |
| 5101 int encode = prefixq_and_encode(dst->encoding()); | |
|
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
5102 emit_int8((unsigned char)(0xC7 | encode)); |
|
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
twisti
parents:
7475
diff
changeset
|
5103 emit_int32(imm32); |
| 304 | 5104 } |
| 5105 | |
| 5106 void Assembler::movslq(Address dst, int32_t imm32) { | |
| 5107 assert(is_simm32(imm32), "lost bits"); | |
| 5108 InstructionMark im(this); | |
| 5109 prefixq(dst); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
5110 emit_int8((unsigned char)0xC7); |
| 304 | 5111 emit_operand(rax, dst, 4); |
|
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
twisti
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7475
diff
changeset
|
5112 emit_int32(imm32); |
| 304 | 5113 } |
| 5114 | |
| 5115 void Assembler::movslq(Register dst, Address src) { | |
| 5116 InstructionMark im(this); | |
| 5117 prefixq(src, dst); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
5118 emit_int8(0x63); |
| 304 | 5119 emit_operand(dst, src); |
| 5120 } | |
| 5121 | |
| 5122 void Assembler::movslq(Register dst, Register src) { | |
| 5123 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
|
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5124 emit_int8(0x63); |
|
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5125 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 5126 } |
| 5127 | |
| 624 | 5128 void Assembler::movswq(Register dst, Address src) { |
| 5129 InstructionMark im(this); | |
| 5130 prefixq(src, dst); | |
|
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|
5131 emit_int8(0x0F); |
|
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|
5132 emit_int8((unsigned char)0xBF); |
| 624 | 5133 emit_operand(dst, src); |
| 5134 } | |
| 5135 | |
| 5136 void Assembler::movswq(Register dst, Register src) { | |
| 5137 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
|
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|
5138 emit_int8((unsigned char)0x0F); |
|
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|
5139 emit_int8((unsigned char)0xBF); |
|
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|
5140 emit_int8((unsigned char)(0xC0 | encode)); |
| 624 | 5141 } |
| 5142 | |
| 5143 void Assembler::movzbq(Register dst, Address src) { | |
| 5144 InstructionMark im(this); | |
| 5145 prefixq(src, dst); | |
|
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|
5146 emit_int8((unsigned char)0x0F); |
|
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|
5147 emit_int8((unsigned char)0xB6); |
| 624 | 5148 emit_operand(dst, src); |
| 5149 } | |
| 5150 | |
| 5151 void Assembler::movzbq(Register dst, Register src) { | |
| 5152 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
|
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|
5153 emit_int8(0x0F); |
|
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|
5154 emit_int8((unsigned char)0xB6); |
|
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|
5155 emit_int8(0xC0 | encode); |
| 624 | 5156 } |
| 5157 | |
| 5158 void Assembler::movzwq(Register dst, Address src) { | |
| 5159 InstructionMark im(this); | |
| 5160 prefixq(src, dst); | |
|
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|
5161 emit_int8((unsigned char)0x0F); |
|
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|
5162 emit_int8((unsigned char)0xB7); |
| 624 | 5163 emit_operand(dst, src); |
| 5164 } | |
| 5165 | |
| 5166 void Assembler::movzwq(Register dst, Register src) { | |
| 5167 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
|
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|
5168 emit_int8((unsigned char)0x0F); |
|
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changeset
|
5169 emit_int8((unsigned char)0xB7); |
|
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|
5170 emit_int8((unsigned char)(0xC0 | encode)); |
| 624 | 5171 } |
| 5172 | |
| 304 | 5173 void Assembler::negq(Register dst) { |
| 5174 int encode = prefixq_and_encode(dst->encoding()); | |
|
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|
5175 emit_int8((unsigned char)0xF7); |
|
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|
5176 emit_int8((unsigned char)(0xD8 | encode)); |
| 304 | 5177 } |
| 5178 | |
| 5179 void Assembler::notq(Register dst) { | |
| 5180 int encode = prefixq_and_encode(dst->encoding()); | |
|
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|
5181 emit_int8((unsigned char)0xF7); |
|
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|
5182 emit_int8((unsigned char)(0xD0 | encode)); |
| 304 | 5183 } |
| 5184 | |
| 5185 void Assembler::orq(Address dst, int32_t imm32) { | |
| 5186 InstructionMark im(this); | |
| 5187 prefixq(dst); | |
|
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|
5188 emit_int8((unsigned char)0x81); |
| 304 | 5189 emit_operand(rcx, dst, 4); |
|
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7475
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|
5190 emit_int32(imm32); |
| 304 | 5191 } |
| 5192 | |
| 5193 void Assembler::orq(Register dst, int32_t imm32) { | |
| 5194 (void) prefixq_and_encode(dst->encoding()); | |
| 5195 emit_arith(0x81, 0xC8, dst, imm32); | |
| 5196 } | |
| 5197 | |
| 5198 void Assembler::orq(Register dst, Address src) { | |
| 5199 InstructionMark im(this); | |
| 5200 prefixq(src, dst); | |
|
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|
5201 emit_int8(0x0B); |
| 304 | 5202 emit_operand(dst, src); |
| 5203 } | |
| 5204 | |
| 5205 void Assembler::orq(Register dst, Register src) { | |
| 5206 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 5207 emit_arith(0x0B, 0xC0, dst, src); | |
| 5208 } | |
| 5209 | |
| 5210 void Assembler::popa() { // 64bit | |
| 5211 movq(r15, Address(rsp, 0)); | |
| 5212 movq(r14, Address(rsp, wordSize)); | |
| 5213 movq(r13, Address(rsp, 2 * wordSize)); | |
| 5214 movq(r12, Address(rsp, 3 * wordSize)); | |
| 5215 movq(r11, Address(rsp, 4 * wordSize)); | |
| 5216 movq(r10, Address(rsp, 5 * wordSize)); | |
| 5217 movq(r9, Address(rsp, 6 * wordSize)); | |
| 5218 movq(r8, Address(rsp, 7 * wordSize)); | |
| 5219 movq(rdi, Address(rsp, 8 * wordSize)); | |
| 5220 movq(rsi, Address(rsp, 9 * wordSize)); | |
| 5221 movq(rbp, Address(rsp, 10 * wordSize)); | |
| 5222 // skip rsp | |
| 5223 movq(rbx, Address(rsp, 12 * wordSize)); | |
| 5224 movq(rdx, Address(rsp, 13 * wordSize)); | |
| 5225 movq(rcx, Address(rsp, 14 * wordSize)); | |
| 5226 movq(rax, Address(rsp, 15 * wordSize)); | |
| 5227 | |
| 5228 addq(rsp, 16 * wordSize); | |
| 5229 } | |
| 5230 | |
|
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|
5231 void Assembler::popcntq(Register dst, Address src) { |
|
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changeset
|
5232 assert(VM_Version::supports_popcnt(), "must support"); |
|
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|
5233 InstructionMark im(this); |
|
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|
5234 emit_int8((unsigned char)0xF3); |
|
643
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|
5235 prefixq(src, dst); |
|
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|
5236 emit_int8((unsigned char)0x0F); |
|
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|
5237 emit_int8((unsigned char)0xB8); |
|
643
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|
5238 emit_operand(dst, src); |
|
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|
5239 } |
|
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|
5240 |
|
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|
5241 void Assembler::popcntq(Register dst, Register src) { |
|
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changeset
|
5242 assert(VM_Version::supports_popcnt(), "must support"); |
|
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changeset
|
5243 emit_int8((unsigned char)0xF3); |
|
643
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|
5244 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
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|
5245 emit_int8((unsigned char)0x0F); |
|
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|
5246 emit_int8((unsigned char)0xB8); |
|
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|
5247 emit_int8((unsigned char)(0xC0 | encode)); |
|
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|
5248 } |
|
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|
5249 |
| 304 | 5250 void Assembler::popq(Address dst) { |
| 5251 InstructionMark im(this); | |
| 5252 prefixq(dst); | |
|
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changeset
|
5253 emit_int8((unsigned char)0x8F); |
| 304 | 5254 emit_operand(rax, dst); |
| 5255 } | |
| 5256 | |
| 5257 void Assembler::pusha() { // 64bit | |
| 5258 // we have to store original rsp. ABI says that 128 bytes | |
| 5259 // below rsp are local scratch. | |
| 5260 movq(Address(rsp, -5 * wordSize), rsp); | |
| 5261 | |
| 5262 subq(rsp, 16 * wordSize); | |
| 5263 | |
| 5264 movq(Address(rsp, 15 * wordSize), rax); | |
| 5265 movq(Address(rsp, 14 * wordSize), rcx); | |
| 5266 movq(Address(rsp, 13 * wordSize), rdx); | |
| 5267 movq(Address(rsp, 12 * wordSize), rbx); | |
| 5268 // skip rsp | |
| 5269 movq(Address(rsp, 10 * wordSize), rbp); | |
| 5270 movq(Address(rsp, 9 * wordSize), rsi); | |
| 5271 movq(Address(rsp, 8 * wordSize), rdi); | |
| 5272 movq(Address(rsp, 7 * wordSize), r8); | |
| 5273 movq(Address(rsp, 6 * wordSize), r9); | |
| 5274 movq(Address(rsp, 5 * wordSize), r10); | |
| 5275 movq(Address(rsp, 4 * wordSize), r11); | |
| 5276 movq(Address(rsp, 3 * wordSize), r12); | |
| 5277 movq(Address(rsp, 2 * wordSize), r13); | |
| 5278 movq(Address(rsp, wordSize), r14); | |
| 5279 movq(Address(rsp, 0), r15); | |
| 5280 } | |
| 5281 | |
| 5282 void Assembler::pushq(Address src) { | |
| 5283 InstructionMark im(this); | |
| 5284 prefixq(src); | |
|
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changeset
|
5285 emit_int8((unsigned char)0xFF); |
| 304 | 5286 emit_operand(rsi, src); |
| 5287 } | |
| 5288 | |
| 5289 void Assembler::rclq(Register dst, int imm8) { | |
| 5290 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 5291 int encode = prefixq_and_encode(dst->encoding()); | |
| 5292 if (imm8 == 1) { | |
|
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changeset
|
5293 emit_int8((unsigned char)0xD1); |
|
d02120b7a34f
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|
5294 emit_int8((unsigned char)(0xD0 | encode)); |
| 304 | 5295 } else { |
|
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changeset
|
5296 emit_int8((unsigned char)0xC1); |
|
d02120b7a34f
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changeset
|
5297 emit_int8((unsigned char)(0xD0 | encode)); |
|
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|
5298 emit_int8(imm8); |
| 304 | 5299 } |
| 5300 } | |
| 5301 void Assembler::sarq(Register dst, int imm8) { | |
| 5302 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 5303 int encode = prefixq_and_encode(dst->encoding()); | |
| 5304 if (imm8 == 1) { | |
|
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changeset
|
5305 emit_int8((unsigned char)0xD1); |
|
d02120b7a34f
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changeset
|
5306 emit_int8((unsigned char)(0xF8 | encode)); |
| 304 | 5307 } else { |
|
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changeset
|
5308 emit_int8((unsigned char)0xC1); |
|
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changeset
|
5309 emit_int8((unsigned char)(0xF8 | encode)); |
|
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|
5310 emit_int8(imm8); |
| 304 | 5311 } |
| 5312 } | |
| 5313 | |
| 5314 void Assembler::sarq(Register dst) { | |
| 5315 int encode = prefixq_and_encode(dst->encoding()); | |
|
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changeset
|
5316 emit_int8((unsigned char)0xD3); |
|
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|
5317 emit_int8((unsigned char)(0xF8 | encode)); |
| 304 | 5318 } |
|
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changeset
|
5319 |
| 304 | 5320 void Assembler::sbbq(Address dst, int32_t imm32) { |
| 5321 InstructionMark im(this); | |
| 5322 prefixq(dst); | |
| 5323 emit_arith_operand(0x81, rbx, dst, imm32); | |
| 5324 } | |
| 5325 | |
| 5326 void Assembler::sbbq(Register dst, int32_t imm32) { | |
| 5327 (void) prefixq_and_encode(dst->encoding()); | |
| 5328 emit_arith(0x81, 0xD8, dst, imm32); | |
| 5329 } | |
| 5330 | |
| 5331 void Assembler::sbbq(Register dst, Address src) { | |
| 5332 InstructionMark im(this); | |
| 5333 prefixq(src, dst); | |
|
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changeset
|
5334 emit_int8(0x1B); |
| 304 | 5335 emit_operand(dst, src); |
| 5336 } | |
| 5337 | |
| 5338 void Assembler::sbbq(Register dst, Register src) { | |
| 5339 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 5340 emit_arith(0x1B, 0xC0, dst, src); | |
| 5341 } | |
| 5342 | |
| 5343 void Assembler::shlq(Register dst, int imm8) { | |
| 5344 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 5345 int encode = prefixq_and_encode(dst->encoding()); | |
| 5346 if (imm8 == 1) { | |
|
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changeset
|
5347 emit_int8((unsigned char)0xD1); |
|
d02120b7a34f
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|
5348 emit_int8((unsigned char)(0xE0 | encode)); |
| 304 | 5349 } else { |
|
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changeset
|
5350 emit_int8((unsigned char)0xC1); |
|
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changeset
|
5351 emit_int8((unsigned char)(0xE0 | encode)); |
|
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|
5352 emit_int8(imm8); |
| 304 | 5353 } |
| 5354 } | |
| 5355 | |
| 5356 void Assembler::shlq(Register dst) { | |
| 5357 int encode = prefixq_and_encode(dst->encoding()); | |
|
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changeset
|
5358 emit_int8((unsigned char)0xD3); |
|
d02120b7a34f
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|
5359 emit_int8((unsigned char)(0xE0 | encode)); |
| 304 | 5360 } |
| 5361 | |
| 5362 void Assembler::shrq(Register dst, int imm8) { | |
| 5363 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 5364 int encode = prefixq_and_encode(dst->encoding()); | |
|
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changeset
|
5365 emit_int8((unsigned char)0xC1); |
|
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changeset
|
5366 emit_int8((unsigned char)(0xE8 | encode)); |
|
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|
5367 emit_int8(imm8); |
| 304 | 5368 } |
| 5369 | |
| 5370 void Assembler::shrq(Register dst) { | |
| 5371 int encode = prefixq_and_encode(dst->encoding()); | |
|
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|
5372 emit_int8((unsigned char)0xD3); |
|
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|
5373 emit_int8(0xE8 | encode); |
| 304 | 5374 } |
| 5375 | |
| 5376 void Assembler::subq(Address dst, int32_t imm32) { | |
| 5377 InstructionMark im(this); | |
| 5378 prefixq(dst); | |
|
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diff
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|
5379 emit_arith_operand(0x81, rbp, dst, imm32); |
| 304 | 5380 } |
| 5381 | |
| 5382 void Assembler::subq(Address dst, Register src) { | |
| 5383 InstructionMark im(this); | |
| 5384 prefixq(dst, src); | |
|
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|
5385 emit_int8(0x29); |
| 304 | 5386 emit_operand(src, dst); |
| 5387 } | |
| 5388 | |
|
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|
5389 void Assembler::subq(Register dst, int32_t imm32) { |
|
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diff
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|
5390 (void) prefixq_and_encode(dst->encoding()); |
|
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diff
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|
5391 emit_arith(0x81, 0xE8, dst, imm32); |
|
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|
5392 } |
|
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|
5393 |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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changeset
|
5394 // Force generation of a 4 byte immediate value even if it fits into 8bit |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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|
5395 void Assembler::subq_imm32(Register dst, int32_t imm32) { |
|
fd8114661503
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|
5396 (void) prefixq_and_encode(dst->encoding()); |
|
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7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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|
5397 emit_arith_imm32(0x81, 0xE8, dst, imm32); |
|
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7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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|
5398 } |
|
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|
5399 |
| 304 | 5400 void Assembler::subq(Register dst, Address src) { |
| 5401 InstructionMark im(this); | |
| 5402 prefixq(src, dst); | |
|
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|
5403 emit_int8(0x2B); |
| 304 | 5404 emit_operand(dst, src); |
| 5405 } | |
| 5406 | |
| 5407 void Assembler::subq(Register dst, Register src) { | |
| 5408 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 5409 emit_arith(0x2B, 0xC0, dst, src); | |
| 5410 } | |
| 5411 | |
| 5412 void Assembler::testq(Register dst, int32_t imm32) { | |
| 5413 // not using emit_arith because test | |
| 5414 // doesn't support sign-extension of | |
| 5415 // 8bit operands | |
| 5416 int encode = dst->encoding(); | |
| 5417 if (encode == 0) { | |
| 5418 prefix(REX_W); | |
|
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|
5419 emit_int8((unsigned char)0xA9); |
| 304 | 5420 } else { |
| 5421 encode = prefixq_and_encode(encode); | |
|
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|
5422 emit_int8((unsigned char)0xF7); |
|
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|
5423 emit_int8((unsigned char)(0xC0 | encode)); |
| 304 | 5424 } |
|
7476
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7475
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changeset
|
5425 emit_int32(imm32); |
| 304 | 5426 } |
| 5427 | |
| 5428 void Assembler::testq(Register dst, Register src) { | |
| 5429 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 5430 emit_arith(0x85, 0xC0, dst, src); | |
| 5431 } | |
| 5432 | |
| 5433 void Assembler::xaddq(Address dst, Register src) { | |
| 5434 InstructionMark im(this); | |
| 5435 prefixq(dst, src); | |
|
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|
5436 emit_int8(0x0F); |
|
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|
5437 emit_int8((unsigned char)0xC1); |
| 304 | 5438 emit_operand(src, dst); |
| 5439 } | |
| 5440 | |
| 5441 void Assembler::xchgq(Register dst, Address src) { | |
| 5442 InstructionMark im(this); | |
| 5443 prefixq(src, dst); | |
|
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changeset
|
5444 emit_int8((unsigned char)0x87); |
| 304 | 5445 emit_operand(dst, src); |
| 5446 } | |
| 5447 | |
| 5448 void Assembler::xchgq(Register dst, Register src) { | |
| 5449 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
|
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changeset
|
5450 emit_int8((unsigned char)0x87); |
|
d02120b7a34f
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diff
changeset
|
5451 emit_int8((unsigned char)(0xc0 | encode)); |
| 304 | 5452 } |
| 5453 | |
| 5454 void Assembler::xorq(Register dst, Register src) { | |
| 5455 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 5456 emit_arith(0x33, 0xC0, dst, src); | |
| 5457 } | |
| 5458 | |
| 5459 void Assembler::xorq(Register dst, Address src) { | |
| 5460 InstructionMark im(this); | |
| 5461 prefixq(src, dst); | |
|
7430
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diff
changeset
|
5462 emit_int8(0x33); |
| 304 | 5463 emit_operand(dst, src); |
| 5464 } | |
| 5465 | |
| 5466 #endif // !LP64 |