Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sparc.ad @ 15875:2d5f9c7379c1
Propagate 0.0 probabilities when simplifying IfNode.
author | Thomas Wuerthinger <thomas.wuerthinger@oracle.com> |
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date | Tue, 13 May 2014 02:31:20 +0200 |
parents | 4ca6dc0799b6 |
children | 89152779163c |
rev | line source |
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0 | 1 // |
9154 | 2 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved. |
0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 // | |
5 // This code is free software; you can redistribute it and/or modify it | |
6 // under the terms of the GNU General Public License version 2 only, as | |
7 // published by the Free Software Foundation. | |
8 // | |
9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 // version 2 for more details (a copy is included in the LICENSE file that | |
13 // accompanied this code). | |
14 // | |
15 // You should have received a copy of the GNU General Public License version | |
16 // 2 along with this work; if not, write to the Free Software Foundation, | |
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 // | |
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
0 | 22 // |
23 // | |
24 | |
25 // SPARC Architecture Description File | |
26 | |
27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
28 // This information is used by the matcher and the register allocator to | |
29 // describe individual registers and classes of registers within the target | |
30 // archtecture. | |
31 register %{ | |
32 //----------Architecture Description Register Definitions---------------------- | |
33 // General Registers | |
34 // "reg_def" name ( register save type, C convention save type, | |
35 // ideal register type, encoding, vm name ); | |
36 // Register Save Types: | |
37 // | |
38 // NS = No-Save: The register allocator assumes that these registers | |
39 // can be used without saving upon entry to the method, & | |
40 // that they do not need to be saved at call sites. | |
41 // | |
42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
43 // can be used without saving upon entry to the method, | |
44 // but that they must be saved at call sites. | |
45 // | |
46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
47 // must be saved before using them upon entry to the | |
48 // method, but they do not need to be saved at call | |
49 // sites. | |
50 // | |
51 // AS = Always-Save: The register allocator assumes that these registers | |
52 // must be saved before using them upon entry to the | |
53 // method, & that they must be saved at call sites. | |
54 // | |
55 // Ideal Register Type is used to determine how to save & restore a | |
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
58 // | |
59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
60 | |
61 | |
62 // ---------------------------- | |
63 // Integer/Long Registers | |
64 // ---------------------------- | |
65 | |
66 // Need to expose the hi/lo aspect of 64-bit registers | |
67 // This register set is used for both the 64-bit build and | |
68 // the 32-bit build with 1-register longs. | |
69 | |
70 // Global Registers 0-7 | |
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
87 | |
88 // Output Registers 0-7 | |
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
105 | |
106 // Local Registers 0-7 | |
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
123 | |
124 // Input Registers 0-7 | |
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
141 | |
142 // ---------------------------- | |
143 // Float/Double Registers | |
144 // ---------------------------- | |
145 | |
146 // Float Registers | |
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
179 | |
180 // Double Registers | |
181 // The rules of ADL require that double registers be defined in pairs. | |
182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
183 // single float registers. In each pair, ADLC-assigned register numbers | |
184 // must be adjacent, with the lower number even. Finally, when the | |
185 // CPU stores such a register pair to memory, the word associated with | |
186 // the lower ADLC-assigned number must be stored to the lower address. | |
187 | |
188 // These definitions specify the actual bit encodings of the sparc | |
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
190 // wants 0-63, so we have to convert every time we want to use fp regs | |
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
605 | 192 // 255 is a flag meaning "don't go here". |
0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
194 // the place in the sparc stack crawler that asserts on the 255 is | |
195 // fixed up. | |
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196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
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197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
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198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
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199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
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200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
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201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
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202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
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203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
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204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
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205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
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206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
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207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
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208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
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209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
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210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
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211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
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212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
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213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
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214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
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215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
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216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
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217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
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218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
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219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
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220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
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221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
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222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
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223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
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224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
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225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
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226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
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227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
0 | 228 |
229 | |
230 // ---------------------------- | |
231 // Special Registers | |
232 // Condition Codes Flag Registers | |
233 // I tried to break out ICC and XCC but it's not very pretty. | |
234 // Every Sparc instruction which defs/kills one also kills the other. | |
235 // Hence every compare instruction which defs one kind of flags ends | |
236 // up needing a kill of the other. | |
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
238 | |
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
243 | |
244 // ---------------------------- | |
245 // Specify the enum values for the registers. These enums are only used by the | |
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
247 // for visibility to the rest of the vm. The order of this enum influences the | |
248 // register allocator so having the freedom to set this order and not be stuck | |
249 // with the order that is natural for the rest of the vm is worth it. | |
250 alloc_class chunk0( | |
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
255 | |
256 // Note that a register is not allocatable unless it is also mentioned | |
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
258 | |
259 alloc_class chunk1( | |
260 // The first registers listed here are those most likely to be used | |
261 // as temporaries. We move F0..F7 away from the front of the list, | |
262 // to reduce the likelihood of interferences with parameters and | |
263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
264 // since they are used for return values. | |
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
274 | |
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
276 | |
277 //----------Architecture Description Register Classes-------------------------- | |
278 // Several register classes are automatically defined based upon information in | |
279 // this architecture description. | |
280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
283 // | |
284 | |
285 // G0 is not included in integer class since it has special meaning. | |
286 reg_class g0_reg(R_G0); | |
287 | |
288 // ---------------------------- | |
289 // Integer Register Classes | |
290 // ---------------------------- | |
291 // Exclusions from i_reg: | |
292 // R_G0: hardwired zero | |
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
294 // R_G6: reserved by Solaris ABI to tools | |
295 // R_G7: reserved by Solaris ABI to libthread | |
296 // R_O7: Used as a temp in many encodings | |
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
298 | |
299 // Class for all integer registers, except the G registers. This is used for | |
300 // encodings which use G registers as temps. The regular inputs to such | |
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
302 // will not put an input into a temp register. | |
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
304 | |
305 reg_class g1_regI(R_G1); | |
306 reg_class g3_regI(R_G3); | |
307 reg_class g4_regI(R_G4); | |
308 reg_class o0_regI(R_O0); | |
309 reg_class o7_regI(R_O7); | |
310 | |
311 // ---------------------------- | |
312 // Pointer Register Classes | |
313 // ---------------------------- | |
314 #ifdef _LP64 | |
315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
320 // Lock encodings use G3 and G4 internally | |
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
326 // It is also used for memory addressing, allowing direct TLS addressing. | |
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
332 // We use it to save R_G2 across calls out of Java. | |
333 reg_class l7_regP(R_L7H,R_L7); | |
334 | |
335 // Other special pointer regs | |
336 reg_class g1_regP(R_G1H,R_G1); | |
337 reg_class g2_regP(R_G2H,R_G2); | |
338 reg_class g3_regP(R_G3H,R_G3); | |
339 reg_class g4_regP(R_G4H,R_G4); | |
340 reg_class g5_regP(R_G5H,R_G5); | |
341 reg_class i0_regP(R_I0H,R_I0); | |
342 reg_class o0_regP(R_O0H,R_O0); | |
343 reg_class o1_regP(R_O1H,R_O1); | |
344 reg_class o2_regP(R_O2H,R_O2); | |
345 reg_class o7_regP(R_O7H,R_O7); | |
346 | |
347 #else // _LP64 | |
348 // 32-bit build means 32-bit pointers means 1 register. | |
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
353 // Lock encodings use G3 and G4 internally | |
354 reg_class lock_ptr_reg(R_G1, R_G5, | |
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
359 // It is also used for memory addressing, allowing direct TLS addressing. | |
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
365 // We use it to save R_G2 across calls out of Java. | |
366 reg_class l7_regP(R_L7); | |
367 | |
368 // Other special pointer regs | |
369 reg_class g1_regP(R_G1); | |
370 reg_class g2_regP(R_G2); | |
371 reg_class g3_regP(R_G3); | |
372 reg_class g4_regP(R_G4); | |
373 reg_class g5_regP(R_G5); | |
374 reg_class i0_regP(R_I0); | |
375 reg_class o0_regP(R_O0); | |
376 reg_class o1_regP(R_O1); | |
377 reg_class o2_regP(R_O2); | |
378 reg_class o7_regP(R_O7); | |
379 #endif // _LP64 | |
380 | |
381 | |
382 // ---------------------------- | |
383 // Long Register Classes | |
384 // ---------------------------- | |
385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
389 #ifdef _LP64 | |
390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
394 #endif // _LP64 | |
395 ); | |
396 | |
397 reg_class g1_regL(R_G1H,R_G1); | |
420
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398 reg_class g3_regL(R_G3H,R_G3); |
0 | 399 reg_class o2_regL(R_O2H,R_O2); |
400 reg_class o7_regL(R_O7H,R_O7); | |
401 | |
402 // ---------------------------- | |
403 // Special Class for Condition Code Flags Register | |
404 reg_class int_flags(CCR); | |
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
406 reg_class float_flag0(FCC0); | |
407 | |
408 | |
409 // ---------------------------- | |
410 // Float Point Register Classes | |
411 // ---------------------------- | |
412 // Skip F30/F31, they are reserved for mem-mem copies | |
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
414 | |
415 // Paired floating point registers--they show up in the same order as the floats, | |
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
422 ); | |
423 | |
424 // Paired floating point registers--they show up in the same order as the floats, | |
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
3804 | 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); |
0 | 429 %} |
430 | |
431 //----------DEFINITION BLOCK--------------------------------------------------- | |
432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
434 // Format: | |
435 // int_def <name> ( <int_value>, <expression>); | |
436 // Generated Code in ad_<arch>.hpp | |
437 // #define <name> (<expression>) | |
438 // // value == <int_value> | |
439 // Generated code in ad_<arch>.cpp adlc_verification() | |
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
441 // | |
442 definitions %{ | |
443 // The default cost (of an ALU instruction). | |
444 int_def DEFAULT_COST ( 100, 100); | |
445 int_def HUGE_COST (1000000, 1000000); | |
446 | |
447 // Memory refs are twice as expensive as run-of-the-mill. | |
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
449 | |
450 // Branches are even more expensive. | |
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
453 %} | |
454 | |
455 | |
456 //----------SOURCE BLOCK------------------------------------------------------- | |
457 // This is a block of C++ code which provides values, functions, and | |
458 // definitions necessary in the rest of the architecture description | |
459 source_hpp %{ | |
460 // Must be visible to the DFA in dfa_sparc.cpp | |
461 extern bool can_branch_register( Node *bol, Node *cmp ); | |
462 | |
3892 | 463 extern bool use_block_zeroing(Node* count); |
464 | |
0 | 465 // Macros to extract hi & lo halves from a long pair. |
466 // G0 is not part of any long pair, so assert on that. | |
605 | 467 // Prevents accidentally using G1 instead of G0. |
0 | 468 #define LONG_HI_REG(x) (x) |
469 #define LONG_LO_REG(x) (x) | |
470 | |
471 %} | |
472 | |
473 source %{ | |
474 #define __ _masm. | |
475 | |
476 // tertiary op of a LoadP or StoreP encoding | |
477 #define REGP_OP true | |
478 | |
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
481 static Register reg_to_register_object(int register_encoding); | |
482 | |
483 // Used by the DFA in dfa_sparc.cpp. | |
484 // Check for being able to use a V9 branch-on-register. Requires a | |
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
486 // extended. Doesn't work following an integer ADD, for example, because of | |
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
489 // replace them with zero, which could become sign-extension in a different OS | |
490 // release. There's no obvious reason why an interrupt will ever fill these | |
491 // bits with non-zero junk (the registers are reloaded with standard LD | |
492 // instructions which either zero-fill or sign-fill). | |
493 bool can_branch_register( Node *bol, Node *cmp ) { | |
494 if( !BranchOnRegister ) return false; | |
495 #ifdef _LP64 | |
496 if( cmp->Opcode() == Op_CmpP ) | |
497 return true; // No problems with pointer compares | |
498 #endif | |
499 if( cmp->Opcode() == Op_CmpL ) | |
500 return true; // No problems with long compares | |
501 | |
502 if( !SparcV9RegsHiBitsZero ) return false; | |
503 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
504 bol->as_Bool()->_test._test != BoolTest::eq ) | |
505 return false; | |
506 | |
507 // Check for comparing against a 'safe' value. Any operation which | |
508 // clears out the high word is safe. Thus, loads and certain shifts | |
509 // are safe, as are non-negative constants. Any operation which | |
510 // preserves zero bits in the high word is safe as long as each of its | |
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
512 // inputs are safe. At present, the only important case to recognize | |
513 // seems to be loads. Constants should fold away, and shifts & | |
514 // logicals can use the 'cc' forms. | |
515 Node *x = cmp->in(1); | |
516 if( x->is_Load() ) return true; | |
517 if( x->is_Phi() ) { | |
518 for( uint i = 1; i < x->req(); i++ ) | |
519 if( !x->in(i)->is_Load() ) | |
520 return false; | |
521 return true; | |
522 } | |
523 return false; | |
524 } | |
525 | |
3892 | 526 bool use_block_zeroing(Node* count) { |
527 // Use BIS for zeroing if count is not constant | |
528 // or it is >= BlockZeroingLowLimit. | |
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit); | |
530 } | |
531 | |
0 | 532 // **************************************************************************** |
533 | |
534 // REQUIRED FUNCTIONALITY | |
535 | |
536 // !!!!! Special hack to get all type of calls to specify the byte offset | |
537 // from the start of the call to the point where the return address | |
538 // will point. | |
539 // The "return address" is the address of the call instruction, plus 8. | |
540 | |
541 int MachCallStaticJavaNode::ret_addr_offset() { | |
1567 | 542 int offset = NativeCall::instruction_size; // call; delay slot |
543 if (_method_handle_invoke) | |
544 offset += 4; // restore SP | |
545 return offset; | |
0 | 546 } |
547 | |
548 int MachCallDynamicJavaNode::ret_addr_offset() { | |
549 int vtable_index = this->_vtable_index; | |
550 if (vtable_index < 0) { | |
551 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
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552 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
0 | 553 return (NativeMovConstReg::instruction_size + |
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
555 } else { | |
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
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557 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
0 | 558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); |
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559 int klass_load_size; |
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560 if (UseCompressedClassPointers) { |
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561 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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562 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; |
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563 } else { |
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564 klass_load_size = 1*BytesPerInstWord; |
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565 } |
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566 if (Assembler::is_simm13(v_off)) { |
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567 return klass_load_size + |
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568 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
0 | 569 NativeCall::instruction_size); // call; delay slot |
570 } else { | |
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571 return klass_load_size + |
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572 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
0 | 573 NativeCall::instruction_size); // call; delay slot |
574 } | |
575 } | |
576 } | |
577 | |
578 int MachCallRuntimeNode::ret_addr_offset() { | |
579 #ifdef _LP64 | |
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580 if (MacroAssembler::is_far_target(entry_point())) { |
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581 return NativeFarCall::instruction_size; |
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582 } else { |
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583 return NativeCall::instruction_size; |
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584 } |
0 | 585 #else |
586 return NativeCall::instruction_size; // call; delay slot | |
587 #endif | |
588 } | |
589 | |
590 // Indicate if the safepoint node needs the polling page as an input. | |
591 // Since Sparc does not have absolute addressing, it does. | |
592 bool SafePointNode::needs_polling_address_input() { | |
593 return true; | |
594 } | |
595 | |
596 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
597 void emit_break(CodeBuffer &cbuf) { | |
598 MacroAssembler _masm(&cbuf); | |
599 __ breakpoint_trap(); | |
600 } | |
601 | |
602 #ifndef PRODUCT | |
603 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
604 st->print("TA"); | |
605 } | |
606 #endif | |
607 | |
608 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
609 emit_break(cbuf); | |
610 } | |
611 | |
612 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
613 return MachNode::size(ra_); | |
614 } | |
615 | |
616 // Traceable jump | |
617 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
618 MacroAssembler _masm(&cbuf); | |
619 Register rdest = reg_to_register_object(jump_target); | |
620 __ JMP(rdest, 0); | |
621 __ delayed()->nop(); | |
622 } | |
623 | |
624 // Traceable jump and set exception pc | |
625 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
626 MacroAssembler _masm(&cbuf); | |
627 Register rdest = reg_to_register_object(jump_target); | |
628 __ JMP(rdest, 0); | |
629 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
630 } | |
631 | |
632 void emit_nop(CodeBuffer &cbuf) { | |
633 MacroAssembler _masm(&cbuf); | |
634 __ nop(); | |
635 } | |
636 | |
637 void emit_illtrap(CodeBuffer &cbuf) { | |
638 MacroAssembler _masm(&cbuf); | |
639 __ illtrap(0); | |
640 } | |
641 | |
642 | |
643 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
644 assert(n->rule() != loadUB_rule, ""); | |
645 | |
646 intptr_t offset = 0; | |
647 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
648 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
649 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
650 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
651 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
652 atype = atype->add_offset(offset); | |
653 assert(disp32 == offset, "wrong disp32"); | |
654 return atype->_offset; | |
655 } | |
656 | |
657 | |
658 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
659 assert(n->rule() != loadUB_rule, ""); | |
660 | |
661 intptr_t offset = 0; | |
662 Node* addr = n->in(2); | |
663 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
664 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
665 Node* a = addr->in(2/*AddPNode::Address*/); | |
666 Node* o = addr->in(3/*AddPNode::Offset*/); | |
667 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
668 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
669 assert(atype->isa_oop_ptr(), "still an oop"); | |
670 } | |
671 offset = atype->is_ptr()->_offset; | |
672 if (offset != Type::OffsetBot) offset += disp32; | |
673 return offset; | |
674 } | |
675 | |
2008 | 676 static inline jdouble replicate_immI(int con, int count, int width) { |
677 // Load a constant replicated "count" times with width "width" | |
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678 assert(count*width == 8 && width <= 4, "sanity"); |
2008 | 679 int bit_width = width * 8; |
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680 jlong val = con; |
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681 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits |
2008 | 682 for (int i = 0; i < count - 1; i++) { |
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683 val |= (val << bit_width); |
2008 | 684 } |
685 jdouble dval = *((jdouble*) &val); // coerce to double type | |
686 return dval; | |
687 } | |
688 | |
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689 static inline jdouble replicate_immF(float con) { |
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690 // Replicate float con 2 times and pack into vector. |
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691 int val = *((int*)&con); |
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692 jlong lval = val; |
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693 lval = (lval << 32) | (lval & 0xFFFFFFFFl); |
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694 jdouble dval = *((jdouble*) &lval); // coerce to double type |
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695 return dval; |
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696 } |
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697 |
0 | 698 // Standard Sparc opcode form2 field breakdown |
699 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
700 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
701 int op = (f30 << 30) | | |
702 (f29 << 29) | | |
703 (f25 << 25) | | |
704 (f22 << 22) | | |
705 (f20 << 20) | | |
706 (f19 << 19) | | |
707 (f0 << 0); | |
1748 | 708 cbuf.insts()->emit_int32(op); |
0 | 709 } |
710 | |
711 // Standard Sparc opcode form2 field breakdown | |
712 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
713 f0 >>= 10; // Drop 10 bits | |
714 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
715 int op = (f30 << 30) | | |
716 (f25 << 25) | | |
717 (f22 << 22) | | |
718 (f0 << 0); | |
1748 | 719 cbuf.insts()->emit_int32(op); |
0 | 720 } |
721 | |
722 // Standard Sparc opcode form3 field breakdown | |
723 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
724 int op = (f30 << 30) | | |
725 (f25 << 25) | | |
726 (f19 << 19) | | |
727 (f14 << 14) | | |
728 (f5 << 5) | | |
729 (f0 << 0); | |
1748 | 730 cbuf.insts()->emit_int32(op); |
0 | 731 } |
732 | |
733 // Standard Sparc opcode form3 field breakdown | |
734 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
735 simm13 &= (1<<13)-1; // Mask to 13 bits | |
736 int op = (f30 << 30) | | |
737 (f25 << 25) | | |
738 (f19 << 19) | | |
739 (f14 << 14) | | |
740 (1 << 13) | // bit to indicate immediate-mode | |
741 (simm13<<0); | |
1748 | 742 cbuf.insts()->emit_int32(op); |
0 | 743 } |
744 | |
745 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
746 simm10 &= (1<<10)-1; // Mask to 10 bits | |
747 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
748 } | |
749 | |
750 #ifdef ASSERT | |
751 // Helper function for VerifyOops in emit_form3_mem_reg | |
752 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
753 warning("VerifyOops encountered unexpected instruction:"); | |
754 n->dump(2); | |
755 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
756 } | |
757 #endif | |
758 | |
759 | |
14909 | 760 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, |
0 | 761 int src1_enc, int disp32, int src2_enc, int dst_enc) { |
762 | |
763 #ifdef ASSERT | |
764 // The following code implements the +VerifyOops feature. | |
765 // It verifies oop values which are loaded into or stored out of | |
766 // the current method activation. +VerifyOops complements techniques | |
767 // like ScavengeALot, because it eagerly inspects oops in transit, | |
768 // as they enter or leave the stack, as opposed to ScavengeALot, | |
769 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
770 // For this reason, +VerifyOops can sometimes detect bugs very close | |
771 // to their point of creation. It can also serve as a cross-check | |
772 // on the validity of oop maps, when used toegether with ScavengeALot. | |
773 | |
774 // It would be good to verify oops at other points, especially | |
775 // when an oop is used as a base pointer for a load or store. | |
776 // This is presently difficult, because it is hard to know when | |
777 // a base address is biased or not. (If we had such information, | |
778 // it would be easy and useful to make a two-argument version of | |
779 // verify_oop which unbiases the base, and performs verification.) | |
780 | |
781 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
782 bool is_verified_oop_base = false; | |
783 bool is_verified_oop_load = false; | |
784 bool is_verified_oop_store = false; | |
785 int tmp_enc = -1; | |
786 if (VerifyOops && src1_enc != R_SP_enc) { | |
787 // classify the op, mainly for an assert check | |
788 int st_op = 0, ld_op = 0; | |
789 switch (primary) { | |
790 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
791 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
792 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
793 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
794 case Assembler::std_op3: st_op = Op_StoreL; break; | |
795 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
796 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
797 | |
798 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
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799 case Assembler::ldub_op3: ld_op = Op_LoadUB; break; |
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800 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
0 | 801 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
802 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
803 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
804 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
805 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
806 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
807 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
808 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
809 | |
810 default: ShouldNotReachHere(); | |
811 } | |
812 if (tertiary == REGP_OP) { | |
813 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
814 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
815 else ShouldNotReachHere(); | |
816 if (st_op) { | |
817 // a store | |
818 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
819 Node* n2 = n->in(3); | |
820 if (n2 != NULL) { | |
821 const Type* t = n2->bottom_type(); | |
822 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
823 } | |
824 } else { | |
825 // a load | |
826 const Type* t = n->bottom_type(); | |
827 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
828 } | |
829 } | |
830 | |
831 if (ld_op) { | |
832 // a Load | |
833 // inputs are (0:control, 1:memory, 2:address) | |
834 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
835 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
836 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
837 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
838 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
839 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
840 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
841 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
842 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
843 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
844 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
845 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
846 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
3898 | 847 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) && |
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848 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) && |
0 | 849 !(n->rule() == loadUB_rule)) { |
850 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
851 } | |
852 } else if (st_op) { | |
853 // a Store | |
854 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
855 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
856 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
857 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
858 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
859 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
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860 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) && |
0 | 861 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { |
862 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
863 } | |
864 } | |
865 | |
866 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
867 Node* addr = n->in(2); | |
868 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
869 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
870 if (atype != NULL) { | |
871 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
872 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
873 if (offset != offset_2) { | |
874 get_offset_from_base(n, atype, disp32); | |
875 get_offset_from_base_2(n, atype, disp32); | |
876 } | |
877 assert(offset == offset_2, "different offsets"); | |
878 if (offset == disp32) { | |
879 // we now know that src1 is a true oop pointer | |
880 is_verified_oop_base = true; | |
881 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
882 if( primary == Assembler::ldd_op3 ) { | |
883 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
884 } else { | |
885 tmp_enc = dst_enc; | |
886 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
887 assert(src1_enc != dst_enc, ""); | |
888 } | |
889 } | |
890 } | |
891 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
892 || offset == oopDesc::mark_offset_in_bytes())) { | |
893 // loading the mark should not be allowed either, but | |
894 // we don't check this since it conflicts with InlineObjectHash | |
895 // usage of LoadINode to get the mark. We could keep the | |
896 // check if we create a new LoadMarkNode | |
897 // but do not verify the object before its header is initialized | |
898 ShouldNotReachHere(); | |
899 } | |
900 } | |
901 } | |
902 } | |
903 } | |
904 #endif | |
905 | |
906 uint instr; | |
907 instr = (Assembler::ldst_op << 30) | |
908 | (dst_enc << 25) | |
909 | (primary << 19) | |
910 | (src1_enc << 14); | |
911 | |
912 uint index = src2_enc; | |
913 int disp = disp32; | |
914 | |
14909 | 915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) |
0 | 916 disp += STACK_BIAS; |
917 | |
918 // We should have a compiler bailout here rather than a guarantee. | |
919 // Better yet would be some mechanism to handle variable-size matches correctly. | |
920 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
921 | |
922 if( disp == 0 ) { | |
923 // use reg-reg form | |
924 // bit 13 is already zero | |
925 instr |= index; | |
926 } else { | |
927 // use reg-imm form | |
928 instr |= 0x00002000; // set bit 13 to one | |
929 instr |= disp & 0x1FFF; | |
930 } | |
931 | |
1748 | 932 cbuf.insts()->emit_int32(instr); |
0 | 933 |
934 #ifdef ASSERT | |
935 { | |
936 MacroAssembler _masm(&cbuf); | |
937 if (is_verified_oop_base) { | |
938 __ verify_oop(reg_to_register_object(src1_enc)); | |
939 } | |
940 if (is_verified_oop_store) { | |
941 __ verify_oop(reg_to_register_object(dst_enc)); | |
942 } | |
943 if (tmp_enc != -1) { | |
944 __ mov(O7, reg_to_register_object(tmp_enc)); | |
945 } | |
946 if (is_verified_oop_load) { | |
947 __ verify_oop(reg_to_register_object(dst_enc)); | |
948 } | |
949 } | |
950 #endif | |
951 } | |
952 | |
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953 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) { |
0 | 954 // The method which records debug information at every safepoint |
955 // expects the call to be the first instruction in the snippet as | |
956 // it creates a PcDesc structure which tracks the offset of a call | |
957 // from the start of the codeBlob. This offset is computed as | |
958 // code_end() - code_begin() of the code which has been emitted | |
959 // so far. | |
960 // In this particular case we have skirted around the problem by | |
961 // putting the "mov" instruction in the delay slot but the problem | |
962 // may bite us again at some other point and a cleaner/generic | |
963 // solution using relocations would be needed. | |
964 MacroAssembler _masm(&cbuf); | |
965 __ set_inst_mark(); | |
966 | |
967 // We flush the current window just so that there is a valid stack copy | |
968 // the fact that the current window becomes active again instantly is | |
969 // not a problem there is nothing live in it. | |
970 | |
971 #ifdef ASSERT | |
972 int startpos = __ offset(); | |
973 #endif /* ASSERT */ | |
974 | |
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975 __ call((address)entry_point, rtype); |
0 | 976 |
977 if (preserve_g2) __ delayed()->mov(G2, L7); | |
978 else __ delayed()->nop(); | |
979 | |
980 if (preserve_g2) __ mov(L7, G2); | |
981 | |
982 #ifdef ASSERT | |
983 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
984 #ifdef _LP64 | |
985 // Trash argument dump slots. | |
986 __ set(0xb0b8ac0db0b8ac0d, G1); | |
987 __ mov(G1, G5); | |
988 __ stx(G1, SP, STACK_BIAS + 0x80); | |
989 __ stx(G1, SP, STACK_BIAS + 0x88); | |
990 __ stx(G1, SP, STACK_BIAS + 0x90); | |
991 __ stx(G1, SP, STACK_BIAS + 0x98); | |
992 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
993 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
994 #else // _LP64 | |
995 // this is also a native call, so smash the first 7 stack locations, | |
996 // and the various registers | |
997 | |
998 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
999 // while [SP+0x44..0x58] are the argument dump slots. | |
1000 __ set((intptr_t)0xbaadf00d, G1); | |
1001 __ mov(G1, G5); | |
1002 __ sllx(G1, 32, G1); | |
1003 __ or3(G1, G5, G1); | |
1004 __ mov(G1, G5); | |
1005 __ stx(G1, SP, 0x40); | |
1006 __ stx(G1, SP, 0x48); | |
1007 __ stx(G1, SP, 0x50); | |
1008 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
1009 #endif // _LP64 | |
1010 } | |
1011 #endif /*ASSERT*/ | |
1012 } | |
1013 | |
1014 //============================================================================= | |
1015 // REQUIRED FUNCTIONALITY for encoding | |
1016 void emit_lo(CodeBuffer &cbuf, int val) { } | |
1017 void emit_hi(CodeBuffer &cbuf, int val) { } | |
1018 | |
1019 | |
1020 //============================================================================= | |
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1021 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask(); |
2008 | 1022 |
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1023 int Compile::ConstantTable::calculate_table_base_offset() const { |
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1024 if (UseRDPCForConstantTableBase) { |
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1025 // The table base offset might be less but then it fits into |
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1026 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit). |
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1027 return Assembler::min_simm13(); |
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1028 } else { |
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1029 int offset = -(size() / 2); |
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1030 if (!Assembler::is_simm13(offset)) { |
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1031 offset = Assembler::min_simm13(); |
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1032 } |
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1033 return offset; |
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1034 } |
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1035 } |
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1036 |
2008 | 1037 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
1038 Compile* C = ra_->C; | |
1039 Compile::ConstantTable& constant_table = C->constant_table(); | |
1040 MacroAssembler _masm(&cbuf); | |
1041 | |
1042 Register r = as_Register(ra_->get_encode(this)); | |
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1043 CodeSection* consts_section = __ code()->consts(); |
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1044 int consts_size = consts_section->align_at_start(consts_section->size()); |
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1045 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); |
2008 | 1046 |
1047 if (UseRDPCForConstantTableBase) { | |
1048 // For the following RDPC logic to work correctly the consts | |
1049 // section must be allocated right before the insts section. This | |
1050 // assert checks for that. The layout and the SECT_* constants | |
1051 // are defined in src/share/vm/asm/codeBuffer.hpp. | |
1052 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); | |
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1053 int insts_offset = __ offset(); |
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1054 |
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1055 // Layout: |
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1056 // |
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1057 // |----------- consts section ------------|----------- insts section -----------... |
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1058 // |------ constant table -----|- padding -|------------------x---- |
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1059 // \ current PC (RDPC instruction) |
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1060 // |<------------- consts_size ----------->|<- insts_offset ->| |
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1061 // \ table base |
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1062 // The table base offset is later added to the load displacement |
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1063 // so it has to be negative. |
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1064 int table_base_offset = -(consts_size + insts_offset); |
2008 | 1065 int disp; |
1066 | |
1067 // If the displacement from the current PC to the constant table | |
1068 // base fits into simm13 we set the constant table base to the | |
1069 // current PC. | |
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1070 if (Assembler::is_simm13(table_base_offset)) { |
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1071 constant_table.set_table_base_offset(table_base_offset); |
2008 | 1072 disp = 0; |
1073 } else { | |
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1074 // Otherwise we set the constant table base offset to the |
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1075 // maximum negative displacement of load instructions to keep |
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1076 // the disp as small as possible: |
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1077 // |
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1078 // |<------------- consts_size ----------->|<- insts_offset ->| |
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1079 // |<--------- min_simm13 --------->|<-------- disp --------->| |
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1080 // \ table base |
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1081 table_base_offset = Assembler::min_simm13(); |
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1082 constant_table.set_table_base_offset(table_base_offset); |
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1083 disp = (consts_size + insts_offset) + table_base_offset; |
2008 | 1084 } |
1085 | |
1086 __ rdpc(r); | |
1087 | |
1088 if (disp != 0) { | |
1089 assert(r != O7, "need temporary"); | |
1090 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); | |
1091 } | |
1092 } | |
1093 else { | |
1094 // Materialize the constant table base. | |
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1095 address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); |
2008 | 1096 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); |
1097 AddressLiteral base(baseaddr, rspec); | |
1098 __ set(base, r); | |
1099 } | |
1100 } | |
1101 | |
1102 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { | |
1103 if (UseRDPCForConstantTableBase) { | |
1104 // This is really the worst case but generally it's only 1 instruction. | |
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1105 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; |
2008 | 1106 } else { |
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1107 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; |
2008 | 1108 } |
1109 } | |
1110 | |
1111 #ifndef PRODUCT | |
1112 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
1113 char reg[128]; | |
1114 ra_->dump_register(this, reg); | |
1115 if (UseRDPCForConstantTableBase) { | |
1116 st->print("RDPC %s\t! constant table base", reg); | |
1117 } else { | |
1118 st->print("SET &constanttable,%s\t! constant table base", reg); | |
1119 } | |
1120 } | |
1121 #endif | |
1122 | |
1123 | |
1124 //============================================================================= | |
0 | 1125 |
1126 #ifndef PRODUCT | |
1127 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1128 Compile* C = ra_->C; | |
1129 | |
1130 for (int i = 0; i < OptoPrologueNops; i++) { | |
1131 st->print_cr("NOP"); st->print("\t"); | |
1132 } | |
1133 | |
1134 if( VerifyThread ) { | |
1135 st->print_cr("Verify_Thread"); st->print("\t"); | |
1136 } | |
1137 | |
1138 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
1139 | |
1140 // Calls to C2R adapters often do not accept exceptional returns. | |
1141 // We require that their callers must bang for them. But be careful, because | |
1142 // some VM calls (such as call site linkage) can use several kilobytes of | |
1143 // stack. But the stack safety zone should account for that. | |
1144 // See bugs 4446381, 4468289, 4497237. | |
1145 if (C->need_stack_bang(framesize)) { | |
1146 st->print_cr("! stack bang"); st->print("\t"); | |
1147 } | |
1148 | |
1149 if (Assembler::is_simm13(-framesize)) { | |
1150 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
1151 } else { | |
1152 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
1153 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
1154 st->print ("SAVE R_SP,R_G3,R_SP"); | |
1155 } | |
1156 | |
1157 } | |
1158 #endif | |
1159 | |
1160 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1161 Compile* C = ra_->C; | |
1162 MacroAssembler _masm(&cbuf); | |
1163 | |
1164 for (int i = 0; i < OptoPrologueNops; i++) { | |
1165 __ nop(); | |
1166 } | |
1167 | |
1168 __ verify_thread(); | |
1169 | |
1170 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
1171 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
1172 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
1173 | |
1174 // Calls to C2R adapters often do not accept exceptional returns. | |
1175 // We require that their callers must bang for them. But be careful, because | |
1176 // some VM calls (such as call site linkage) can use several kilobytes of | |
1177 // stack. But the stack safety zone should account for that. | |
1178 // See bugs 4446381, 4468289, 4497237. | |
1179 if (C->need_stack_bang(framesize)) { | |
1180 __ generate_stack_overflow_check(framesize); | |
1181 } | |
1182 | |
1183 if (Assembler::is_simm13(-framesize)) { | |
1184 __ save(SP, -framesize, SP); | |
1185 } else { | |
1186 __ sethi(-framesize & ~0x3ff, G3); | |
1187 __ add(G3, -framesize & 0x3ff, G3); | |
1188 __ save(SP, G3, SP); | |
1189 } | |
1190 C->set_frame_complete( __ offset() ); | |
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1191 |
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1192 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) { |
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1193 // NOTE: We set the table base offset here because users might be |
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1194 // emitted before MachConstantBaseNode. |
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1195 Compile::ConstantTable& constant_table = C->constant_table(); |
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1196 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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1197 } |
0 | 1198 } |
1199 | |
1200 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
1201 return MachNode::size(ra_); | |
1202 } | |
1203 | |
1204 int MachPrologNode::reloc() const { | |
1205 return 10; // a large enough number | |
1206 } | |
1207 | |
1208 //============================================================================= | |
1209 #ifndef PRODUCT | |
1210 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1211 Compile* C = ra_->C; | |
1212 | |
1213 if( do_polling() && ra_->C->is_method_compilation() ) { | |
1214 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
1215 #ifdef _LP64 | |
1216 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
1217 #else | |
1218 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
1219 #endif | |
1220 } | |
1221 | |
1222 if( do_polling() ) | |
1223 st->print("RET\n\t"); | |
1224 | |
1225 st->print("RESTORE"); | |
1226 } | |
1227 #endif | |
1228 | |
1229 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1230 MacroAssembler _masm(&cbuf); | |
1231 Compile* C = ra_->C; | |
1232 | |
1233 __ verify_thread(); | |
1234 | |
1235 // If this does safepoint polling, then do it here | |
1236 if( do_polling() && ra_->C->is_method_compilation() ) { | |
727 | 1237 AddressLiteral polling_page(os::get_polling_page()); |
1238 __ sethi(polling_page, L0); | |
0 | 1239 __ relocate(relocInfo::poll_return_type); |
1240 __ ld_ptr( L0, 0, G0 ); | |
1241 } | |
1242 | |
1243 // If this is a return, then stuff the restore in the delay slot | |
1244 if( do_polling() ) { | |
1245 __ ret(); | |
1246 __ delayed()->restore(); | |
1247 } else { | |
1248 __ restore(); | |
1249 } | |
1250 } | |
1251 | |
1252 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
1253 return MachNode::size(ra_); | |
1254 } | |
1255 | |
1256 int MachEpilogNode::reloc() const { | |
1257 return 16; // a large enough number | |
1258 } | |
1259 | |
1260 const Pipeline * MachEpilogNode::pipeline() const { | |
1261 return MachNode::pipeline_class(); | |
1262 } | |
1263 | |
1264 int MachEpilogNode::safepoint_offset() const { | |
1265 assert( do_polling(), "no return for this epilog node"); | |
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1266 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; |
0 | 1267 } |
1268 | |
1269 //============================================================================= | |
1270 | |
1271 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
1272 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
1273 static enum RC rc_class( OptoReg::Name reg ) { | |
1274 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
1275 if (OptoReg::is_stack(reg)) return rc_stack; | |
1276 VMReg r = OptoReg::as_VMReg(reg); | |
1277 if (r->is_Register()) return rc_int; | |
1278 assert(r->is_FloatRegister(), "must be"); | |
1279 return rc_float; | |
1280 } | |
1281 | |
14909 | 1282 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { |
1283 if( cbuf ) { | |
1284 // Better yet would be some mechanism to handle variable-size matches correctly | |
1285 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
1286 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
1287 } else { | |
1288 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
1289 } | |
0 | 1290 } |
1291 #ifndef PRODUCT | |
14909 | 1292 else if( !do_size ) { |
1293 if( size != 0 ) st->print("\n\t"); | |
1294 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | |
1295 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | |
0 | 1296 } |
1297 #endif | |
1298 return size+4; | |
1299 } | |
1300 | |
1301 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
1302 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
1303 #ifndef PRODUCT | |
1304 else if( !do_size ) { | |
1305 if( size != 0 ) st->print("\n\t"); | |
1306 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
1307 } | |
1308 #endif | |
1309 return size+4; | |
1310 } | |
1311 | |
1312 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
1313 PhaseRegAlloc *ra_, | |
1314 bool do_size, | |
1315 outputStream* st ) const { | |
1316 // Get registers to move | |
1317 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
1318 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
1319 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
1320 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
1321 | |
1322 enum RC src_second_rc = rc_class(src_second); | |
1323 enum RC src_first_rc = rc_class(src_first); | |
1324 enum RC dst_second_rc = rc_class(dst_second); | |
1325 enum RC dst_first_rc = rc_class(dst_first); | |
1326 | |
1327 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
1328 | |
1329 // Generate spill code! | |
1330 int size = 0; | |
1331 | |
1332 if( src_first == dst_first && src_second == dst_second ) | |
1333 return size; // Self copy, no move | |
1334 | |
1335 // -------------------------------------- | |
1336 // Check for mem-mem move. Load into unused float registers and fall into | |
1337 // the float-store case. | |
1338 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
1339 int offset = ra_->reg2offset(src_first); | |
1340 // Further check for aligned-adjacent pair, so we can use a double load | |
1341 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
1342 src_second = OptoReg::Name(R_F31_num); | |
1343 src_second_rc = rc_float; | |
1344 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
1345 } else { | |
1346 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
1347 } | |
1348 src_first = OptoReg::Name(R_F30_num); | |
1349 src_first_rc = rc_float; | |
1350 } | |
1351 | |
1352 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
1353 int offset = ra_->reg2offset(src_second); | |
1354 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
1355 src_second = OptoReg::Name(R_F31_num); | |
1356 src_second_rc = rc_float; | |
1357 } | |
1358 | |
1359 // -------------------------------------- | |
1360 // Check for float->int copy; requires a trip through memory | |
3804 | 1361 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { |
0 | 1362 int offset = frame::register_save_words*wordSize; |
3804 | 1363 if (cbuf) { |
0 | 1364 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); |
1365 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1366 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1367 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
1368 } | |
1369 #ifndef PRODUCT | |
3804 | 1370 else if (!do_size) { |
1371 if (size != 0) st->print("\n\t"); | |
0 | 1372 st->print( "SUB R_SP,16,R_SP\n"); |
1373 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1374 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1375 st->print("\tADD R_SP,16,R_SP\n"); | |
1376 } | |
1377 #endif | |
1378 size += 16; | |
1379 } | |
1380 | |
3804 | 1381 // Check for float->int copy on T4 |
1382 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { | |
1383 // Further check for aligned-adjacent pair, so we can use a double move | |
1384 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
1385 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st); | |
1386 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st); | |
1387 } | |
1388 // Check for int->float copy on T4 | |
1389 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { | |
1390 // Further check for aligned-adjacent pair, so we can use a double move | |
1391 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
1392 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st); | |
1393 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st); | |
1394 } | |
1395 | |
0 | 1396 // -------------------------------------- |
1397 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
1398 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
1399 // hardware does the flop for me. Doubles are always aligned, so no problem | |
1400 // there. Misaligned sources only come from native-long-returns (handled | |
1401 // special below). | |
1402 #ifndef _LP64 | |
1403 if( src_first_rc == rc_int && // source is already big-endian | |
1404 src_second_rc != rc_bad && // 64-bit move | |
1405 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
1406 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
1407 // Do the big-endian flop. | |
1408 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
1409 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
1410 } | |
1411 #endif | |
1412 | |
1413 // -------------------------------------- | |
1414 // Check for integer reg-reg copy | |
1415 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
1416 #ifndef _LP64 | |
1417 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
1418 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1419 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1420 // operand contains the least significant word of the 64-bit value and vice versa. | |
1421 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
1422 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
1423 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
1424 if( cbuf ) { | |
1425 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
1426 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
1427 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
1428 #ifndef PRODUCT | |
1429 } else if( !do_size ) { | |
1430 if( size != 0 ) st->print("\n\t"); | |
1431 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
1432 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
1433 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
1434 #endif | |
1435 } | |
1436 return size+12; | |
1437 } | |
1438 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
1439 // returning a long value in I0/I1 | |
1440 // a SpillCopy must be able to target a return instruction's reg_class | |
1441 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1442 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1443 // operand contains the least significant word of the 64-bit value and vice versa. | |
1444 OptoReg::Name tdest = dst_first; | |
1445 | |
1446 if (src_first == dst_first) { | |
1447 tdest = OptoReg::Name(R_O7_num); | |
1448 size += 4; | |
1449 } | |
1450 | |
1451 if( cbuf ) { | |
1452 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
1453 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
1454 // ShrL_reg_imm6 | |
1455 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
1456 // ShrR_reg_imm6 src, 0, dst | |
1457 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
1458 if (tdest != dst_first) { | |
1459 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
1460 } | |
1461 } | |
1462 #ifndef PRODUCT | |
1463 else if( !do_size ) { | |
1464 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
1465 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
1466 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
1467 if (tdest != dst_first) { | |
1468 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
1469 } | |
1470 } | |
1471 #endif // PRODUCT | |
1472 return size+8; | |
1473 } | |
1474 #endif // !_LP64 | |
1475 // Else normal reg-reg copy | |
1476 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
1477 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
1478 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
1479 // This moves an aligned adjacent pair. | |
1480 // See if we are done. | |
1481 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
1482 return size; | |
1483 } | |
1484 | |
1485 // Check for integer store | |
1486 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
1487 int offset = ra_->reg2offset(dst_first); | |
1488 // Further check for aligned-adjacent pair, so we can use a double store | |
1489 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1490 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
1491 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
1492 } | |
1493 | |
1494 // Check for integer load | |
1495 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
1496 int offset = ra_->reg2offset(src_first); | |
1497 // Further check for aligned-adjacent pair, so we can use a double load | |
1498 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1499 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
1500 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1501 } | |
1502 | |
1503 // Check for float reg-reg copy | |
1504 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
1505 // Further check for aligned-adjacent pair, so we can use a double move | |
1506 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1507 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
1508 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
1509 } | |
1510 | |
1511 // Check for float store | |
1512 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
1513 int offset = ra_->reg2offset(dst_first); | |
1514 // Further check for aligned-adjacent pair, so we can use a double store | |
1515 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1516 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
1517 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1518 } | |
1519 | |
1520 // Check for float load | |
1521 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
1522 int offset = ra_->reg2offset(src_first); | |
1523 // Further check for aligned-adjacent pair, so we can use a double load | |
1524 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1525 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
1526 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
1527 } | |
1528 | |
1529 // -------------------------------------------------------------------- | |
1530 // Check for hi bits still needing moving. Only happens for misaligned | |
1531 // arguments to native calls. | |
1532 if( src_second == dst_second ) | |
1533 return size; // Self copy; no move | |
1534 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
1535 | |
1536 #ifndef _LP64 | |
1537 // In the LP64 build, all registers can be moved as aligned/adjacent | |
605 | 1538 // pairs, so there's never any need to move the high bits separately. |
0 | 1539 // The 32-bit builds have to deal with the 32-bit ABI which can force |
1540 // all sorts of silly alignment problems. | |
1541 | |
1542 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
1543 // 32-bits of a 64-bit register, but are needed in low bits of another | |
1544 // register (else it's a hi-bits-to-hi-bits copy which should have | |
1545 // happened already as part of a 64-bit move) | |
1546 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
1547 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
1548 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
1549 // Shift src_second down to dst_second's low bits. | |
1550 if( cbuf ) { | |
1551 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1552 #ifndef PRODUCT | |
1553 } else if( !do_size ) { | |
1554 if( size != 0 ) st->print("\n\t"); | |
1555 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
1556 #endif | |
1557 } | |
1558 return size+4; | |
1559 } | |
1560 | |
1561 // Check for high word integer store. Must down-shift the hi bits | |
1562 // into a temp register, then fall into the case of storing int bits. | |
1563 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
1564 // Shift src_second down to dst_second's low bits. | |
1565 if( cbuf ) { | |
1566 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1567 #ifndef PRODUCT | |
1568 } else if( !do_size ) { | |
1569 if( size != 0 ) st->print("\n\t"); | |
1570 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
1571 #endif | |
1572 } | |
1573 size+=4; | |
1574 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
1575 } | |
1576 | |
1577 // Check for high word integer load | |
1578 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
1579 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
1580 | |
1581 // Check for high word integer store | |
1582 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
1583 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
1584 | |
1585 // Check for high word float store | |
1586 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
1587 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
1588 | |
1589 #endif // !_LP64 | |
1590 | |
1591 Unimplemented(); | |
1592 } | |
1593 | |
1594 #ifndef PRODUCT | |
1595 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1596 implementation( NULL, ra_, false, st ); | |
1597 } | |
1598 #endif | |
1599 | |
1600 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1601 implementation( &cbuf, ra_, false, NULL ); | |
1602 } | |
1603 | |
1604 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
1605 return implementation( NULL, ra_, true, NULL ); | |
1606 } | |
1607 | |
1608 //============================================================================= | |
1609 #ifndef PRODUCT | |
1610 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
1611 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
1612 } | |
1613 #endif | |
1614 | |
1615 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
1616 MacroAssembler _masm(&cbuf); | |
1617 for(int i = 0; i < _count; i += 1) { | |
1618 __ nop(); | |
1619 } | |
1620 } | |
1621 | |
1622 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
1623 return 4 * _count; | |
1624 } | |
1625 | |
1626 | |
1627 //============================================================================= | |
1628 #ifndef PRODUCT | |
1629 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1630 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
1631 int reg = ra_->get_reg_first(this); | |
1632 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
1633 } | |
1634 #endif | |
1635 | |
1636 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1637 MacroAssembler _masm(&cbuf); | |
1638 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
1639 int reg = ra_->get_encode(this); | |
1640 | |
1641 if (Assembler::is_simm13(offset)) { | |
1642 __ add(SP, offset, reg_to_register_object(reg)); | |
1643 } else { | |
1644 __ set(offset, O7); | |
1645 __ add(SP, O7, reg_to_register_object(reg)); | |
1646 } | |
1647 } | |
1648 | |
1649 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
1650 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
1651 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
1652 return ra_->C->scratch_emit_size(this); | |
1653 } | |
1654 | |
1655 //============================================================================= | |
1656 #ifndef PRODUCT | |
1657 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1658 st->print_cr("\nUEP:"); | |
1659 #ifdef _LP64 | |
12226
7944aba7ba41
8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents:
12056
diff
changeset
|
1660 if (UseCompressedClassPointers) { |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
1661 assert(Universe::heap() != NULL, "java heap should be initialized"); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1662 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
13000
209aa13ab8c0
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
12323
diff
changeset
|
1663 if (Universe::narrow_klass_base() != 0) { |
209aa13ab8c0
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
12323
diff
changeset
|
1664 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base"); |
209aa13ab8c0
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
12323
diff
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1665 if (Universe::narrow_klass_shift() != 0) { |
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1666 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); |
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1667 } |
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1668 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
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1669 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base"); |
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1670 } else { |
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1671 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); |
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1672 } |
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1673 } else { |
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1674 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
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1675 } |
0 | 1676 st->print_cr("\tCMP R_G5,R_G3" ); |
1677 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1678 #else // _LP64 | |
1679 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
1680 st->print_cr("\tCMP R_G5,R_G3" ); | |
1681 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1682 #endif // _LP64 | |
1683 } | |
1684 #endif | |
1685 | |
1686 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1687 MacroAssembler _masm(&cbuf); | |
1688 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
1689 Register temp_reg = G3; | |
1690 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
1691 | |
605 | 1692 // Load klass from receiver |
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1693 __ load_klass(O0, temp_reg); |
0 | 1694 // Compare against expected klass |
1695 __ cmp(temp_reg, G5_ic_reg); | |
1696 // Branch to miss code, checks xcc or icc depending | |
1697 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
1698 } | |
1699 | |
1700 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
1701 return MachNode::size(ra_); | |
1702 } | |
1703 | |
1704 | |
1705 //============================================================================= | |
1706 | |
1707 uint size_exception_handler() { | |
1708 if (TraceJumps) { | |
1709 return (400); // just a guess | |
1710 } | |
1711 return ( NativeJump::instruction_size ); // sethi;jmp;nop | |
1712 } | |
1713 | |
1714 uint size_deopt_handler() { | |
1715 if (TraceJumps) { | |
1716 return (400); // just a guess | |
1717 } | |
1718 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore | |
1719 } | |
1720 | |
1721 // Emit exception handler code. | |
1722 int emit_exception_handler(CodeBuffer& cbuf) { | |
1723 Register temp_reg = G3; | |
1748 | 1724 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); |
0 | 1725 MacroAssembler _masm(&cbuf); |
1726 | |
1727 address base = | |
1728 __ start_a_stub(size_exception_handler()); | |
1729 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1730 | |
1731 int offset = __ offset(); | |
1732 | |
727 | 1733 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
0 | 1734 __ delayed()->nop(); |
1735 | |
1736 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
1737 | |
1738 __ end_a_stub(); | |
1739 | |
1740 return offset; | |
1741 } | |
1742 | |
1743 int emit_deopt_handler(CodeBuffer& cbuf) { | |
1744 // Can't use any of the current frame's registers as we may have deopted | |
1745 // at a poll and everything (including G3) can be live. | |
1746 Register temp_reg = L0; | |
727 | 1747 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
0 | 1748 MacroAssembler _masm(&cbuf); |
1749 | |
1750 address base = | |
1751 __ start_a_stub(size_deopt_handler()); | |
1752 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1753 | |
1754 int offset = __ offset(); | |
1755 __ save_frame(0); | |
727 | 1756 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
0 | 1757 __ delayed()->restore(); |
1758 | |
1759 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
1760 | |
1761 __ end_a_stub(); | |
1762 return offset; | |
1763 | |
1764 } | |
1765 | |
1766 // Given a register encoding, produce a Integer Register object | |
1767 static Register reg_to_register_object(int register_encoding) { | |
1768 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
1769 return as_Register(register_encoding); | |
1770 } | |
1771 | |
1772 // Given a register encoding, produce a single-precision Float Register object | |
1773 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
1774 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
1775 return as_SingleFloatRegister(register_encoding); | |
1776 } | |
1777 | |
1778 // Given a register encoding, produce a double-precision Float Register object | |
1779 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
1780 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
1781 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
1782 return as_DoubleFloatRegister(register_encoding); | |
1783 } | |
1784 | |
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1785 const bool Matcher::match_rule_supported(int opcode) { |
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1786 if (!has_match_rule(opcode)) |
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1787 return false; |
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1788 |
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1789 switch (opcode) { |
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1790 case Op_CountLeadingZerosI: |
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1791 case Op_CountLeadingZerosL: |
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1792 case Op_CountTrailingZerosI: |
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1793 case Op_CountTrailingZerosL: |
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1794 case Op_PopCountI: |
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1795 case Op_PopCountL: |
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1796 if (!UsePopCountInstruction) |
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1797 return false; |
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1798 case Op_CompareAndSwapL: |
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1799 #ifdef _LP64 |
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1800 case Op_CompareAndSwapP: |
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1801 #endif |
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1802 if (!VM_Version::supports_cx8()) |
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1803 return false; |
775
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1804 break; |
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1805 } |
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1806 |
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1807 return true; // Per default match rules are supported. |
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1808 } |
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1809 |
0 | 1810 int Matcher::regnum_to_fpu_offset(int regnum) { |
1811 return regnum - 32; // The FP registers are in the second chunk | |
1812 } | |
1813 | |
1814 #ifdef ASSERT | |
1815 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
1816 #endif | |
1817 | |
1818 // Vector width in bytes | |
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1819 const int Matcher::vector_width_in_bytes(BasicType bt) { |
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1820 assert(MaxVectorSize == 8, ""); |
0 | 1821 return 8; |
1822 } | |
1823 | |
1824 // Vector ideal reg | |
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1825 const int Matcher::vector_ideal_reg(int size) { |
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1826 assert(MaxVectorSize == 8, ""); |
0 | 1827 return Op_RegD; |
1828 } | |
1829 | |
6823 | 1830 const int Matcher::vector_shift_count_ideal_reg(int size) { |
1831 fatal("vector shift is not supported"); | |
1832 return Node::NotAMachineReg; | |
1833 } | |
1834 | |
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1835 // Limits on vector size (number of elements) loaded into vector. |
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1836 const int Matcher::max_vector_size(const BasicType bt) { |
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1837 assert(is_java_primitive(bt), "only primitive type vectors"); |
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1838 return vector_width_in_bytes(bt)/type2aelembytes(bt); |
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1839 } |
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1840 |
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1841 const int Matcher::min_vector_size(const BasicType bt) { |
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1842 return max_vector_size(bt); // Same as max. |
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1843 } |
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1844 |
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1845 // SPARC doesn't support misaligned vectors store/load. |
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1846 const bool Matcher::misaligned_vectors_ok() { |
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1847 return false; |
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1848 } |
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1849 |
0 | 1850 // USII supports fxtof through the whole range of number, USIII doesn't |
1851 const bool Matcher::convL2FSupported(void) { | |
1852 return VM_Version::has_fast_fxtof(); | |
1853 } | |
1854 | |
1855 // Is this branch offset short enough that a short branch can be used? | |
1856 // | |
1857 // NOTE: If the platform does not provide any short branch variants, then | |
1858 // this method should return false for offset 0. | |
3851 | 1859 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
1860 // The passed offset is relative to address of the branch. | |
1861 // Don't need to adjust the offset. | |
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1862 return UseCBCond && Assembler::is_simm12(offset); |
0 | 1863 } |
1864 | |
1865 const bool Matcher::isSimpleConstant64(jlong value) { | |
1866 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
1867 // Depends on optimizations in MacroAssembler::setx. | |
1868 int hi = (int)(value >> 32); | |
1869 int lo = (int)(value & ~0); | |
1870 return (hi == 0) || (hi == -1) || (lo == 0); | |
1871 } | |
1872 | |
1873 // No scaling for the parameter the ClearArray node. | |
1874 const bool Matcher::init_array_count_is_in_bytes = true; | |
1875 | |
1876 // Threshold size for cleararray. | |
1877 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
1878 | |
4047 | 1879 // No additional cost for CMOVL. |
1880 const int Matcher::long_cmove_cost() { return 0; } | |
1881 | |
1882 // CMOVF/CMOVD are expensive on T4 and on SPARC64. | |
1883 const int Matcher::float_cmove_cost() { | |
1884 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; | |
1885 } | |
1886 | |
0 | 1887 // Should the Matcher clone shifts on addressing modes, expecting them to |
1888 // be subsumed into complex addressing expressions or compute them into | |
1889 // registers? True for Intel but false for most RISCs | |
1890 const bool Matcher::clone_shift_expressions = false; | |
1891 | |
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1892 // Do we need to mask the count passed to shift instructions or does |
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1893 // the cpu only look at the lower 5/6 bits anyway? |
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1894 const bool Matcher::need_masked_shift_count = false; |
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1895 |
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1896 bool Matcher::narrow_oop_use_complex_address() { |
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1897 NOT_LP64(ShouldNotCallThis()); |
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1898 assert(UseCompressedOops, "only for compressed oops code"); |
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1899 return false; |
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1900 } |
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1901 |
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1902 bool Matcher::narrow_klass_use_complex_address() { |
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1903 NOT_LP64(ShouldNotCallThis()); |
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1904 assert(UseCompressedClassPointers, "only for compressed klass code"); |
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1905 return false; |
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1906 } |
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1907 |
0 | 1908 // Is it better to copy float constants, or load them directly from memory? |
1909 // Intel can load a float constant from a direct address, requiring no | |
1910 // extra registers. Most RISCs will have to materialize an address into a | |
1911 // register first, so they would do better to copy the constant from stack. | |
1912 const bool Matcher::rematerialize_float_constants = false; | |
1913 | |
1914 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
1915 // needed. Else we split the double into 2 integer pieces and move it | |
1916 // piece-by-piece. Only happens when passing doubles into C code as the | |
1917 // Java calling convention forces doubles to be aligned. | |
1918 #ifdef _LP64 | |
1919 const bool Matcher::misaligned_doubles_ok = true; | |
1920 #else | |
1921 const bool Matcher::misaligned_doubles_ok = false; | |
1922 #endif | |
1923 | |
1924 // No-op on SPARC. | |
1925 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
1926 } | |
1927 | |
1928 // Advertise here if the CPU requires explicit rounding operations | |
1929 // to implement the UseStrictFP mode. | |
1930 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
1931 | |
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1932 // Are floats conerted to double when stored to stack during deoptimization? |
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1933 // Sparc does not handle callee-save floats. |
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1934 bool Matcher::float_in_double() { return false; } |
0 | 1935 |
1936 // Do ints take an entire long register or just half? | |
1937 // Note that we if-def off of _LP64. | |
1938 // The relevant question is how the int is callee-saved. In _LP64 | |
1939 // the whole long is written but de-opt'ing will have to extract | |
1940 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
1941 #ifdef _LP64 | |
1942 const bool Matcher::int_in_long = true; | |
1943 #else | |
1944 const bool Matcher::int_in_long = false; | |
1945 #endif | |
1946 | |
1947 // Return whether or not this register is ever used as an argument. This | |
1948 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
1949 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
1950 // arguments in those registers not be available to the callee. | |
1951 bool Matcher::can_be_java_arg( int reg ) { | |
1952 // Standard sparc 6 args in registers | |
1953 if( reg == R_I0_num || | |
1954 reg == R_I1_num || | |
1955 reg == R_I2_num || | |
1956 reg == R_I3_num || | |
1957 reg == R_I4_num || | |
1958 reg == R_I5_num ) return true; | |
1959 #ifdef _LP64 | |
1960 // 64-bit builds can pass 64-bit pointers and longs in | |
1961 // the high I registers | |
1962 if( reg == R_I0H_num || | |
1963 reg == R_I1H_num || | |
1964 reg == R_I2H_num || | |
1965 reg == R_I3H_num || | |
1966 reg == R_I4H_num || | |
1967 reg == R_I5H_num ) return true; | |
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1968 |
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1969 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
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1970 return true; |
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1971 } |
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1972 |
0 | 1973 #else |
1974 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
1975 // Longs cannot be passed in O regs, because O regs become I regs | |
1976 // after a 'save' and I regs get their high bits chopped off on | |
1977 // interrupt. | |
1978 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
1979 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
1980 #endif | |
1981 // A few float args in registers | |
1982 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
1983 | |
1984 return false; | |
1985 } | |
1986 | |
1987 bool Matcher::is_spillable_arg( int reg ) { | |
1988 return can_be_java_arg(reg); | |
1989 } | |
1990 | |
1914
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1991 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
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1992 // Use hardware SDIVX instruction when it is |
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1993 // faster than a code which use multiply. |
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1994 return VM_Version::has_fast_idiv(); |
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1995 } |
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1996 |
0 | 1997 // Register for DIVI projection of divmodI |
1998 RegMask Matcher::divI_proj_mask() { | |
1999 ShouldNotReachHere(); | |
2000 return RegMask(); | |
2001 } | |
2002 | |
2003 // Register for MODI projection of divmodI | |
2004 RegMask Matcher::modI_proj_mask() { | |
2005 ShouldNotReachHere(); | |
2006 return RegMask(); | |
2007 } | |
2008 | |
2009 // Register for DIVL projection of divmodL | |
2010 RegMask Matcher::divL_proj_mask() { | |
2011 ShouldNotReachHere(); | |
2012 return RegMask(); | |
2013 } | |
2014 | |
2015 // Register for MODL projection of divmodL | |
2016 RegMask Matcher::modL_proj_mask() { | |
2017 ShouldNotReachHere(); | |
2018 return RegMask(); | |
2019 } | |
2020 | |
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2021 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
4121
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2022 return L7_REGP_mask(); |
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2023 } |
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2024 |
14909 | 2025 const RegMask Matcher::mathExactI_result_proj_mask() { |
2026 return G1_REGI_mask(); | |
2027 } | |
2028 | |
2029 const RegMask Matcher::mathExactL_result_proj_mask() { | |
2030 return G1_REGL_mask(); | |
2031 } | |
2032 | |
2033 const RegMask Matcher::mathExactI_flags_proj_mask() { | |
2034 return INT_FLAGS_mask(); | |
2035 } | |
2036 | |
2037 | |
0 | 2038 %} |
2039 | |
2040 | |
2041 // The intptr_t operand types, defined by textual substitution. | |
2042 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
2043 #ifdef _LP64 | |
824 | 2044 #define immX immL |
2045 #define immX13 immL13 | |
2046 #define immX13m7 immL13m7 | |
2047 #define iRegX iRegL | |
2048 #define g1RegX g1RegL | |
0 | 2049 #else |
824 | 2050 #define immX immI |
2051 #define immX13 immI13 | |
2052 #define immX13m7 immI13m7 | |
2053 #define iRegX iRegI | |
2054 #define g1RegX g1RegI | |
0 | 2055 #endif |
2056 | |
2057 //----------ENCODING BLOCK----------------------------------------------------- | |
2058 // This block specifies the encoding classes used by the compiler to output | |
2059 // byte streams. Encoding classes are parameterized macros used by | |
2060 // Machine Instruction Nodes in order to generate the bit encoding of the | |
2061 // instruction. Operands specify their base encoding interface with the | |
2062 // interface keyword. There are currently supported four interfaces, | |
2063 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
2064 // operand to generate a function which returns its register number when | |
2065 // queried. CONST_INTER causes an operand to generate a function which | |
2066 // returns the value of the constant when queried. MEMORY_INTER causes an | |
2067 // operand to generate four functions which return the Base Register, the | |
2068 // Index Register, the Scale Value, and the Offset Value of the operand when | |
2069 // queried. COND_INTER causes an operand to generate six functions which | |
2070 // return the encoding code (ie - encoding bits for the instruction) | |
2071 // associated with each basic boolean condition for a conditional instruction. | |
2072 // | |
2073 // Instructions specify two basic values for encoding. Again, a function | |
2074 // is available to check if the constant displacement is an oop. They use the | |
2075 // ins_encode keyword to specify their encoding classes (which must be | |
2076 // a sequence of enc_class names, and their parameters, specified in | |
2077 // the encoding block), and they use the | |
2078 // opcode keyword to specify, in order, their primary, secondary, and | |
2079 // tertiary opcode. Only the opcode sections which a particular instruction | |
2080 // needs for encoding need to be specified. | |
2081 encode %{ | |
2082 enc_class enc_untested %{ | |
2083 #ifdef ASSERT | |
2084 MacroAssembler _masm(&cbuf); | |
2085 __ untested("encoding"); | |
2086 #endif | |
2087 %} | |
2088 | |
2089 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
14909 | 2090 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, |
0 | 2091 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
2092 %} | |
2093 | |
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2094 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
14909 | 2095 emit_form3_mem_reg(cbuf, this, $primary, -1, |
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2096 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
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2097 %} |
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2098 |
0 | 2099 enc_class form3_mem_prefetch_read( memory mem ) %{ |
14909 | 2100 emit_form3_mem_reg(cbuf, this, $primary, -1, |
0 | 2101 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
2102 %} | |
2103 | |
2104 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
14909 | 2105 emit_form3_mem_reg(cbuf, this, $primary, -1, |
0 | 2106 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
2107 %} | |
2108 | |
2109 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
4114
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2110 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
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2111 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
0 | 2112 guarantee($mem$$index == R_G0_enc, "double index?"); |
14909 | 2113 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
2114 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); | |
0 | 2115 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
2116 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
2117 %} | |
2118 | |
2119 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
4114
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2120 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
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2121 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
0 | 2122 guarantee($mem$$index == R_G0_enc, "double index?"); |
2123 // Load long with 2 instructions | |
14909 | 2124 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
2125 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); | |
0 | 2126 %} |
2127 | |
2128 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
2129 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
2130 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
14909 | 2131 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
0 | 2132 %} |
2133 | |
2134 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
2135 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2136 if( $rs2$$reg != $rd$$reg ) | |
2137 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
2138 %} | |
2139 | |
2140 // Target lo half of long | |
2141 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
2142 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2143 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
2144 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
2145 %} | |
2146 | |
2147 // Source lo half of long | |
2148 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
2149 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2150 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
2151 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
2152 %} | |
2153 | |
2154 // Target hi half of long | |
2155 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
2156 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
2157 %} | |
2158 | |
2159 // Source lo half of long, and leave it sign extended. | |
2160 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
2161 // Sign extend low half | |
2162 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
2163 %} | |
2164 | |
2165 // Source hi half of long, and leave it sign extended. | |
2166 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
2167 // Shift high half to low half | |
2168 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
2169 %} | |
2170 | |
2171 // Source hi half of long | |
2172 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
2173 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2174 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
2175 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
2176 %} | |
2177 | |
2178 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
2179 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
2180 %} | |
2181 | |
2182 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
2183 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
2184 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
2185 %} | |
2186 | |
2187 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
2188 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
2189 // clear if nothing else is happening | |
2190 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
2191 // blt,a,pn done | |
2192 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
2193 // mov dst,-1 in delay slot | |
2194 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2195 %} | |
2196 | |
2197 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
2198 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
2199 %} | |
2200 | |
2201 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
2202 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
2203 %} | |
2204 | |
2205 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
2206 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
2207 %} | |
2208 | |
2209 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
2210 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
2211 %} | |
2212 | |
2213 enc_class move_return_pc_to_o1() %{ | |
2214 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
2215 %} | |
2216 | |
2217 #ifdef _LP64 | |
2218 /* %%% merge with enc_to_bool */ | |
2219 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
2220 MacroAssembler _masm(&cbuf); | |
2221 | |
2222 Register src_reg = reg_to_register_object($src$$reg); | |
2223 Register dst_reg = reg_to_register_object($dst$$reg); | |
2224 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
2225 %} | |
2226 #endif | |
2227 | |
2228 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
2229 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
2230 MacroAssembler _masm(&cbuf); | |
2231 | |
2232 Register p_reg = reg_to_register_object($p$$reg); | |
2233 Register q_reg = reg_to_register_object($q$$reg); | |
2234 Register y_reg = reg_to_register_object($y$$reg); | |
2235 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
2236 | |
2237 __ subcc( p_reg, q_reg, p_reg ); | |
2238 __ add ( p_reg, y_reg, tmp_reg ); | |
2239 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
2240 %} | |
2241 | |
2242 enc_class form_d2i_helper(regD src, regF dst) %{ | |
2243 // fcmp %fcc0,$src,$src | |
2244 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2245 // branch %fcc0 not-nan, predict taken | |
2246 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2247 // fdtoi $src,$dst | |
2248 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
2249 // fitos $dst,$dst (if nan) | |
2250 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2251 // clear $dst (if nan) | |
2252 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2253 // carry on here... | |
2254 %} | |
2255 | |
2256 enc_class form_d2l_helper(regD src, regD dst) %{ | |
2257 // fcmp %fcc0,$src,$src check for NAN | |
2258 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2259 // branch %fcc0 not-nan, predict taken | |
2260 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2261 // fdtox $src,$dst convert in delay slot | |
2262 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
2263 // fxtod $dst,$dst (if nan) | |
2264 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2265 // clear $dst (if nan) | |
2266 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2267 // carry on here... | |
2268 %} | |
2269 | |
2270 enc_class form_f2i_helper(regF src, regF dst) %{ | |
2271 // fcmps %fcc0,$src,$src | |
2272 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2273 // branch %fcc0 not-nan, predict taken | |
2274 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2275 // fstoi $src,$dst | |
2276 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
2277 // fitos $dst,$dst (if nan) | |
2278 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2279 // clear $dst (if nan) | |
2280 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2281 // carry on here... | |
2282 %} | |
2283 | |
2284 enc_class form_f2l_helper(regF src, regD dst) %{ | |
2285 // fcmps %fcc0,$src,$src | |
2286 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2287 // branch %fcc0 not-nan, predict taken | |
2288 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2289 // fstox $src,$dst | |
2290 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
2291 // fxtod $dst,$dst (if nan) | |
2292 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2293 // clear $dst (if nan) | |
2294 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2295 // carry on here... | |
2296 %} | |
2297 | |
2298 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2299 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2300 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2301 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2302 | |
2303 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2304 | |
2305 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2306 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2307 | |
2308 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
2309 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2310 %} | |
2311 | |
2312 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
2313 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2314 %} | |
2315 | |
2316 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
2317 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2318 %} | |
2319 | |
2320 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
2321 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2322 %} | |
2323 | |
2324 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
2325 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
2326 %} | |
2327 | |
2328 // Encloding class for traceable jumps | |
2329 enc_class form_jmpl(g3RegP dest) %{ | |
2330 emit_jmpl(cbuf, $dest$$reg); | |
2331 %} | |
2332 | |
2333 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
2334 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
2335 %} | |
2336 | |
2337 enc_class form2_nop() %{ | |
2338 emit_nop(cbuf); | |
2339 %} | |
2340 | |
2341 enc_class form2_illtrap() %{ | |
2342 emit_illtrap(cbuf); | |
2343 %} | |
2344 | |
2345 | |
2346 // Compare longs and convert into -1, 0, 1. | |
2347 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
2348 // CMP $src1,$src2 | |
2349 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
2350 // blt,a,pn done | |
2351 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
2352 // mov dst,-1 in delay slot | |
2353 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2354 // bgt,a,pn done | |
2355 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
2356 // mov dst,1 in delay slot | |
2357 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
2358 // CLR $dst | |
2359 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
2360 %} | |
2361 | |
2362 enc_class enc_PartialSubtypeCheck() %{ | |
2363 MacroAssembler _masm(&cbuf); | |
2364 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
2365 __ delayed()->nop(); | |
2366 %} | |
2367 | |
3839 | 2368 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ |
0 | 2369 MacroAssembler _masm(&cbuf); |
3839 | 2370 Label* L = $labl$$label; |
0 | 2371 Assembler::Predict predict_taken = |
3839 | 2372 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
2373 | |
2374 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
0 | 2375 __ delayed()->nop(); |
2376 %} | |
2377 | |
3839 | 2378 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ |
0 | 2379 MacroAssembler _masm(&cbuf); |
3839 | 2380 Label* L = $labl$$label; |
0 | 2381 Assembler::Predict predict_taken = |
3839 | 2382 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
2383 | |
2384 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); | |
0 | 2385 __ delayed()->nop(); |
2386 %} | |
2387 | |
2388 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
2389 int op = (Assembler::arith_op << 30) | | |
2390 ($dst$$reg << 25) | | |
2391 (Assembler::movcc_op3 << 19) | | |
2392 (1 << 18) | // cc2 bit for 'icc' | |
2393 ($cmp$$cmpcode << 14) | | |
2394 (0 << 13) | // select register move | |
2395 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
2396 ($src$$reg << 0); | |
1748 | 2397 cbuf.insts()->emit_int32(op); |
0 | 2398 %} |
2399 | |
2400 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
2401 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2402 int op = (Assembler::arith_op << 30) | | |
2403 ($dst$$reg << 25) | | |
2404 (Assembler::movcc_op3 << 19) | | |
2405 (1 << 18) | // cc2 bit for 'icc' | |
2406 ($cmp$$cmpcode << 14) | | |
2407 (1 << 13) | // select immediate move | |
2408 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
2409 (simm11 << 0); | |
1748 | 2410 cbuf.insts()->emit_int32(op); |
0 | 2411 %} |
2412 | |
2413 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
2414 int op = (Assembler::arith_op << 30) | | |
2415 ($dst$$reg << 25) | | |
2416 (Assembler::movcc_op3 << 19) | | |
2417 (0 << 18) | // cc2 bit for 'fccX' | |
2418 ($cmp$$cmpcode << 14) | | |
2419 (0 << 13) | // select register move | |
2420 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2421 ($src$$reg << 0); | |
1748 | 2422 cbuf.insts()->emit_int32(op); |
0 | 2423 %} |
2424 | |
2425 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
2426 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2427 int op = (Assembler::arith_op << 30) | | |
2428 ($dst$$reg << 25) | | |
2429 (Assembler::movcc_op3 << 19) | | |
2430 (0 << 18) | // cc2 bit for 'fccX' | |
2431 ($cmp$$cmpcode << 14) | | |
2432 (1 << 13) | // select immediate move | |
2433 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2434 (simm11 << 0); | |
1748 | 2435 cbuf.insts()->emit_int32(op); |
0 | 2436 %} |
2437 | |
2438 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
2439 int op = (Assembler::arith_op << 30) | | |
2440 ($dst$$reg << 25) | | |
2441 (Assembler::fpop2_op3 << 19) | | |
2442 (0 << 18) | | |
2443 ($cmp$$cmpcode << 14) | | |
2444 (1 << 13) | // select register move | |
2445 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
2446 ($primary << 5) | // select single, double or quad | |
2447 ($src$$reg << 0); | |
1748 | 2448 cbuf.insts()->emit_int32(op); |
0 | 2449 %} |
2450 | |
2451 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
2452 int op = (Assembler::arith_op << 30) | | |
2453 ($dst$$reg << 25) | | |
2454 (Assembler::fpop2_op3 << 19) | | |
2455 (0 << 18) | | |
2456 ($cmp$$cmpcode << 14) | | |
2457 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
2458 ($primary << 5) | // select single, double or quad | |
2459 ($src$$reg << 0); | |
1748 | 2460 cbuf.insts()->emit_int32(op); |
0 | 2461 %} |
2462 | |
2463 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
2464 // the condition comes from opcode-field instead of an argument. | |
2465 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
2466 int op = (Assembler::arith_op << 30) | | |
2467 ($dst$$reg << 25) | | |
2468 (Assembler::movcc_op3 << 19) | | |
2469 (1 << 18) | // cc2 bit for 'icc' | |
2470 ($primary << 14) | | |
2471 (0 << 13) | // select register move | |
2472 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2473 ($src$$reg << 0); | |
1748 | 2474 cbuf.insts()->emit_int32(op); |
0 | 2475 %} |
2476 | |
2477 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
2478 int op = (Assembler::arith_op << 30) | | |
2479 ($dst$$reg << 25) | | |
2480 (Assembler::movcc_op3 << 19) | | |
2481 (6 << 16) | // cc2 bit for 'xcc' | |
2482 ($primary << 14) | | |
2483 (0 << 13) | // select register move | |
2484 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2485 ($src$$reg << 0); | |
1748 | 2486 cbuf.insts()->emit_int32(op); |
0 | 2487 %} |
2488 | |
2489 enc_class Set13( immI13 src, iRegI rd ) %{ | |
2490 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
2491 %} | |
2492 | |
2493 enc_class SetHi22( immI src, iRegI rd ) %{ | |
2494 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
2495 %} | |
2496 | |
2497 enc_class Set32( immI src, iRegI rd ) %{ | |
2498 MacroAssembler _masm(&cbuf); | |
2499 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
2500 %} | |
2501 | |
2502 enc_class call_epilog %{ | |
2503 if( VerifyStackAtCalls ) { | |
2504 MacroAssembler _masm(&cbuf); | |
2505 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
2506 Register temp_reg = G3; | |
2507 __ add(SP, framesize, temp_reg); | |
2508 __ cmp(temp_reg, FP); | |
2509 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
2510 } | |
2511 %} | |
2512 | |
2513 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
2514 // to G1 so the register allocator will not have to deal with the misaligned register | |
2515 // pair. | |
2516 enc_class adjust_long_from_native_call %{ | |
2517 #ifndef _LP64 | |
2518 if (returns_long()) { | |
2519 // sllx O0,32,O0 | |
2520 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
2521 // srl O1,0,O1 | |
2522 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
2523 // or O0,O1,G1 | |
2524 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
2525 } | |
2526 #endif | |
2527 %} | |
2528 | |
2529 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
2530 // CALL directly to the runtime | |
2531 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
2532 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
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2533 /*preserve_g2=*/true); |
0 | 2534 %} |
2535 | |
1567 | 2536 enc_class preserve_SP %{ |
2537 MacroAssembler _masm(&cbuf); | |
2538 __ mov(SP, L7_mh_SP_save); | |
2539 %} | |
2540 | |
2541 enc_class restore_SP %{ | |
2542 MacroAssembler _masm(&cbuf); | |
2543 __ mov(L7_mh_SP_save, SP); | |
2544 %} | |
2545 | |
0 | 2546 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
2547 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
2548 // who we intended to call. | |
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2549 if (!_method) { |
0 | 2550 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); |
2551 } else if (_optimized_virtual) { | |
2552 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
2553 } else { | |
2554 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
2555 } | |
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2556 if (_method) { // Emit stub for static call. |
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2557 CompiledStaticCall::emit_to_interp_stub(cbuf); |
0 | 2558 } |
2559 %} | |
2560 | |
2561 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
2562 MacroAssembler _masm(&cbuf); | |
2563 __ set_inst_mark(); | |
2564 int vtable_index = this->_vtable_index; | |
2565 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
2566 if (vtable_index < 0) { | |
2567 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
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2568 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
0 | 2569 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); |
2570 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
2571 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
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2572 __ ic_call((address)$meth$$method); |
0 | 2573 } else { |
2574 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
2575 // Just go thru the vtable | |
2576 // get receiver klass (receiver already checked for non-null) | |
2577 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
2578 int off = __ offset(); | |
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2579 __ load_klass(O0, G3_scratch); |
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2580 int klass_load_size; |
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2581 if (UseCompressedClassPointers) { |
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2582 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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2583 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; |
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2584 } else { |
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2585 klass_load_size = 1*BytesPerInstWord; |
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2586 } |
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2587 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
0 | 2588 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); |
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2589 if (Assembler::is_simm13(v_off)) { |
0 | 2590 __ ld_ptr(G3, v_off, G5_method); |
2591 } else { | |
2592 // Generate 2 instructions | |
2593 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
2594 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
2595 // ld_ptr, set_hi, set | |
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2596 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
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2597 "Unexpected instruction size(s)"); |
0 | 2598 __ ld_ptr(G3, G5_method, G5_method); |
2599 } | |
2600 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
2601 // However it may very well end up in handle_wrong_method if the | |
2602 // method is abstract for the particular class. | |
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2603 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch); |
0 | 2604 // jump to target (either compiled code or c2iadapter) |
2605 __ jmpl(G3_scratch, G0, O7); | |
2606 __ delayed()->nop(); | |
2607 } | |
2608 %} | |
2609 | |
2610 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
2611 MacroAssembler _masm(&cbuf); | |
2612 | |
2613 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
2614 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
2615 // we might be calling a C2I adapter which needs it. | |
2616 | |
2617 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
2618 // Load nmethod | |
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2619 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg); |
0 | 2620 |
2621 // CALL to compiled java, indirect the contents of G3 | |
2622 __ set_inst_mark(); | |
2623 __ callr(temp_reg, G0); | |
2624 __ delayed()->nop(); | |
2625 %} | |
2626 | |
2627 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
2628 MacroAssembler _masm(&cbuf); | |
2629 Register Rdividend = reg_to_register_object($src1$$reg); | |
2630 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2631 Register Rresult = reg_to_register_object($dst$$reg); | |
2632 | |
2633 __ sra(Rdivisor, 0, Rdivisor); | |
2634 __ sra(Rdividend, 0, Rdividend); | |
2635 __ sdivx(Rdividend, Rdivisor, Rresult); | |
2636 %} | |
2637 | |
2638 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
2639 MacroAssembler _masm(&cbuf); | |
2640 | |
2641 Register Rdividend = reg_to_register_object($src1$$reg); | |
2642 int divisor = $imm$$constant; | |
2643 Register Rresult = reg_to_register_object($dst$$reg); | |
2644 | |
2645 __ sra(Rdividend, 0, Rdividend); | |
2646 __ sdivx(Rdividend, divisor, Rresult); | |
2647 %} | |
2648 | |
2649 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
2650 MacroAssembler _masm(&cbuf); | |
2651 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
2652 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
2653 Register Rdst = reg_to_register_object($dst$$reg); | |
2654 | |
2655 __ sra( Rsrc1, 0, Rsrc1 ); | |
2656 __ sra( Rsrc2, 0, Rsrc2 ); | |
2657 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
2658 __ srlx( Rdst, 32, Rdst ); | |
2659 %} | |
2660 | |
2661 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
2662 MacroAssembler _masm(&cbuf); | |
2663 Register Rdividend = reg_to_register_object($src1$$reg); | |
2664 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2665 Register Rresult = reg_to_register_object($dst$$reg); | |
2666 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2667 | |
2668 assert(Rdividend != Rscratch, ""); | |
2669 assert(Rdivisor != Rscratch, ""); | |
2670 | |
2671 __ sra(Rdividend, 0, Rdividend); | |
2672 __ sra(Rdivisor, 0, Rdivisor); | |
2673 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
2674 __ mulx(Rscratch, Rdivisor, Rscratch); | |
2675 __ sub(Rdividend, Rscratch, Rresult); | |
2676 %} | |
2677 | |
2678 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
2679 MacroAssembler _masm(&cbuf); | |
2680 | |
2681 Register Rdividend = reg_to_register_object($src1$$reg); | |
2682 int divisor = $imm$$constant; | |
2683 Register Rresult = reg_to_register_object($dst$$reg); | |
2684 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2685 | |
2686 assert(Rdividend != Rscratch, ""); | |
2687 | |
2688 __ sra(Rdividend, 0, Rdividend); | |
2689 __ sdivx(Rdividend, divisor, Rscratch); | |
2690 __ mulx(Rscratch, divisor, Rscratch); | |
2691 __ sub(Rdividend, Rscratch, Rresult); | |
2692 %} | |
2693 | |
2694 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
2695 MacroAssembler _masm(&cbuf); | |
2696 | |
2697 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2698 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2699 | |
2700 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
2701 %} | |
2702 | |
2703 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
2704 MacroAssembler _masm(&cbuf); | |
2705 | |
2706 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2707 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2708 | |
2709 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
2710 %} | |
2711 | |
2712 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
2713 MacroAssembler _masm(&cbuf); | |
2714 | |
2715 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2716 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2717 | |
2718 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
2719 %} | |
2720 | |
2721 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
2722 MacroAssembler _masm(&cbuf); | |
2723 | |
2724 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2725 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2726 | |
2727 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
2728 %} | |
2729 | |
2730 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
2731 MacroAssembler _masm(&cbuf); | |
2732 | |
2733 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2734 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2735 | |
2736 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
2737 %} | |
2738 | |
2739 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
2740 MacroAssembler _masm(&cbuf); | |
2741 | |
2742 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2743 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2744 | |
2745 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
2746 %} | |
2747 | |
2748 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
2749 MacroAssembler _masm(&cbuf); | |
2750 | |
2751 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2752 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2753 | |
2754 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
2755 %} | |
2756 | |
2757 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2758 MacroAssembler _masm(&cbuf); | |
2759 | |
2760 Register Roop = reg_to_register_object($oop$$reg); | |
2761 Register Rbox = reg_to_register_object($box$$reg); | |
2762 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2763 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2764 | |
2765 assert(Roop != Rscratch, ""); | |
2766 assert(Roop != Rmark, ""); | |
2767 assert(Rbox != Rscratch, ""); | |
2768 assert(Rbox != Rmark, ""); | |
2769 | |
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2770 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2771 %} |
2772 | |
2773 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2774 MacroAssembler _masm(&cbuf); | |
2775 | |
2776 Register Roop = reg_to_register_object($oop$$reg); | |
2777 Register Rbox = reg_to_register_object($box$$reg); | |
2778 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2779 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2780 | |
2781 assert(Roop != Rscratch, ""); | |
2782 assert(Roop != Rmark, ""); | |
2783 assert(Rbox != Rscratch, ""); | |
2784 assert(Rbox != Rmark, ""); | |
2785 | |
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2786 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2787 %} |
2788 | |
2789 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
2790 MacroAssembler _masm(&cbuf); | |
2791 Register Rmem = reg_to_register_object($mem$$reg); | |
2792 Register Rold = reg_to_register_object($old$$reg); | |
2793 Register Rnew = reg_to_register_object($new$$reg); | |
2794 | |
10997 | 2795 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
0 | 2796 __ cmp( Rold, Rnew ); |
2797 %} | |
2798 | |
2799 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
2800 Register Rmem = reg_to_register_object($mem$$reg); | |
2801 Register Rold = reg_to_register_object($old$$reg); | |
2802 Register Rnew = reg_to_register_object($new$$reg); | |
2803 | |
2804 MacroAssembler _masm(&cbuf); | |
2805 __ mov(Rnew, O7); | |
2806 __ casx(Rmem, Rold, O7); | |
2807 __ cmp( Rold, O7 ); | |
2808 %} | |
2809 | |
2810 // raw int cas, used for compareAndSwap | |
2811 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
2812 Register Rmem = reg_to_register_object($mem$$reg); | |
2813 Register Rold = reg_to_register_object($old$$reg); | |
2814 Register Rnew = reg_to_register_object($new$$reg); | |
2815 | |
2816 MacroAssembler _masm(&cbuf); | |
2817 __ mov(Rnew, O7); | |
2818 __ cas(Rmem, Rold, O7); | |
2819 __ cmp( Rold, O7 ); | |
2820 %} | |
2821 | |
2822 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
2823 Register Rres = reg_to_register_object($res$$reg); | |
2824 | |
2825 MacroAssembler _masm(&cbuf); | |
2826 __ mov(1, Rres); | |
2827 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
2828 %} | |
2829 | |
2830 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
2831 Register Rres = reg_to_register_object($res$$reg); | |
2832 | |
2833 MacroAssembler _masm(&cbuf); | |
2834 __ mov(1, Rres); | |
2835 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
2836 %} | |
2837 | |
2838 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
2839 MacroAssembler _masm(&cbuf); | |
2840 Register Rdst = reg_to_register_object($dst$$reg); | |
2841 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
2842 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
2843 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
2844 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
2845 | |
2846 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
2847 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
2848 %} | |
2849 | |
2850 | |
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2851 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
0 | 2852 Label Ldone, Lloop; |
2853 MacroAssembler _masm(&cbuf); | |
2854 | |
2855 Register str1_reg = reg_to_register_object($str1$$reg); | |
2856 Register str2_reg = reg_to_register_object($str2$$reg); | |
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2857 Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
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2858 Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
0 | 2859 Register result_reg = reg_to_register_object($result$$reg); |
2860 | |
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2861 assert(result_reg != str1_reg && |
62001a362ce9
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2862 result_reg != str2_reg && |
62001a362ce9
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2863 result_reg != cnt1_reg && |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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2864 result_reg != cnt2_reg , |
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2865 "need different registers"); |
0 | 2866 |
2867 // Compute the minimum of the string lengths(str1_reg) and the | |
2868 // difference of the string lengths (stack) | |
2869 | |
2870 // See if the lengths are different, and calculate min in str1_reg. | |
2871 // Stash diff in O7 in case we need it for a tie-breaker. | |
2872 Label Lskip; | |
986
62001a362ce9
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2873 __ subcc(cnt1_reg, cnt2_reg, O7); |
62001a362ce9
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2874 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
0 | 2875 __ br(Assembler::greater, true, Assembler::pt, Lskip); |
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62001a362ce9
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2876 // cnt2 is shorter, so use its count: |
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2877 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
0 | 2878 __ bind(Lskip); |
2879 | |
986
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2880 // reallocate cnt1_reg, cnt2_reg, result_reg |
0 | 2881 // Note: limit_reg holds the string length pre-scaled by 2 |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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2882 Register limit_reg = cnt1_reg; |
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2883 Register chr2_reg = cnt2_reg; |
0 | 2884 Register chr1_reg = result_reg; |
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2885 // str{12} are the base pointers |
0 | 2886 |
2887 // Is the minimum length zero? | |
2888 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
2889 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2890 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2891 | |
2892 // Load first characters | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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2893 __ lduh(str1_reg, 0, chr1_reg); |
62001a362ce9
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2894 __ lduh(str2_reg, 0, chr2_reg); |
0 | 2895 |
2896 // Compare first characters | |
2897 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
2898 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2899 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2900 __ delayed()->nop(); | |
2901 | |
2902 { | |
2903 // Check after comparing first character to see if strings are equivalent | |
2904 Label LSkip2; | |
2905 // Check if the strings start at same location | |
986
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2906 __ cmp(str1_reg, str2_reg); |
0 | 2907 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
2908 __ delayed()->nop(); | |
2909 | |
2910 // Check if the length difference is zero (in O7) | |
2911 __ cmp(G0, O7); | |
2912 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2913 __ delayed()->mov(G0, result_reg); // result is zero | |
2914 | |
2915 // Strings might not be equal | |
2916 __ bind(LSkip2); | |
2917 } | |
2918 | |
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diff
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|
2919 // We have no guarantee that on 64 bit the higher half of limit_reg is 0 |
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8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
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|
2920 __ signx(limit_reg); |
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|
2921 |
0 | 2922 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); |
2923 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2924 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2925 | |
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2926 // Shift str1_reg and str2_reg to the end of the arrays, negate limit |
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2927 __ add(str1_reg, limit_reg, str1_reg); |
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2928 __ add(str2_reg, limit_reg, str2_reg); |
0 | 2929 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
2930 | |
2931 // Compare the rest of the characters | |
986
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2932 __ lduh(str1_reg, limit_reg, chr1_reg); |
0 | 2933 __ bind(Lloop); |
986
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2934 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
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2935 __ lduh(str2_reg, limit_reg, chr2_reg); |
0 | 2936 __ subcc(chr1_reg, chr2_reg, chr1_reg); |
2937 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2938 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2939 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
2940 // annul LDUH if branch is not taken to prevent access past end of string | |
2941 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
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2942 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
0 | 2943 |
2944 // If strings are equal up to min length, return the length difference. | |
2945 __ mov(O7, result_reg); | |
2946 | |
2947 // Otherwise, return the difference between the first mismatched chars. | |
2948 __ bind(Ldone); | |
2949 %} | |
2950 | |
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2951 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
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2952 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
681 | 2953 MacroAssembler _masm(&cbuf); |
2954 | |
2955 Register str1_reg = reg_to_register_object($str1$$reg); | |
2956 Register str2_reg = reg_to_register_object($str2$$reg); | |
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2957 Register cnt_reg = reg_to_register_object($cnt$$reg); |
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2958 Register tmp1_reg = O7; |
681 | 2959 Register result_reg = reg_to_register_object($result$$reg); |
2960 | |
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2961 assert(result_reg != str1_reg && |
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2962 result_reg != str2_reg && |
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2963 result_reg != cnt_reg && |
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2964 result_reg != tmp1_reg , |
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|
2965 "need different registers"); |
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|
2966 |
62001a362ce9
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2967 __ cmp(str1_reg, str2_reg); //same char[] ? |
681 | 2968 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
2969 __ delayed()->add(G0, 1, result_reg); | |
2970 | |
3839 | 2971 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn); |
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2972 __ delayed()->add(G0, 1, result_reg); // count == 0 |
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2973 |
681 | 2974 //rename registers |
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2975 Register limit_reg = cnt_reg; |
681 | 2976 Register chr1_reg = result_reg; |
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2977 Register chr2_reg = tmp1_reg; |
681 | 2978 |
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2979 // We have no guarantee that on 64 bit the higher half of limit_reg is 0 |
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2980 __ signx(limit_reg); |
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2981 |
681 | 2982 //check for alignment and position the pointers to the ends |
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2983 __ or3(str1_reg, str2_reg, chr1_reg); |
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2984 __ andcc(chr1_reg, 0x3, chr1_reg); |
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2985 // notZero means at least one not 4-byte aligned. |
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2986 // We could optimize the case when both arrays are not aligned |
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2987 // but it is not frequent case and it requires additional checks. |
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2988 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
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2989 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
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2990 |
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2991 // Compare char[] arrays aligned to 4 bytes. |
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2992 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
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2993 chr1_reg, chr2_reg, Ldone); |
3839 | 2994 __ ba(Ldone); |
681 | 2995 __ delayed()->add(G0, 1, result_reg); |
2996 | |
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2997 // char by char compare |
681 | 2998 __ bind(Lchar); |
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2999 __ add(str1_reg, limit_reg, str1_reg); |
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3000 __ add(str2_reg, limit_reg, str2_reg); |
681 | 3001 __ neg(limit_reg); //negate count |
3002 | |
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3003 __ lduh(str1_reg, limit_reg, chr1_reg); |
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3004 // Lchar_loop |
681 | 3005 __ bind(Lchar_loop); |
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3006 __ lduh(str2_reg, limit_reg, chr2_reg); |
681 | 3007 __ cmp(chr1_reg, chr2_reg); |
3008 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
3009 __ delayed()->mov(G0, result_reg); //not equal | |
3010 __ inccc(limit_reg, sizeof(jchar)); | |
3011 // annul LDUH if branch is not taken to prevent access past end of string | |
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3012 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
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3013 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
681 | 3014 |
3015 __ add(G0, 1, result_reg); //equal | |
3016 | |
3017 __ bind(Ldone); | |
3018 %} | |
3019 | |
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3020 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
681 | 3021 Label Lvector, Ldone, Lloop; |
3022 MacroAssembler _masm(&cbuf); | |
3023 | |
3024 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
3025 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
3026 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
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3027 Register tmp2_reg = O7; |
681 | 3028 Register result_reg = reg_to_register_object($result$$reg); |
3029 | |
3030 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
3031 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
3032 | |
3033 // return true if the same array | |
3034 __ cmp(ary1_reg, ary2_reg); | |
1016 | 3035 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
681 | 3036 __ delayed()->add(G0, 1, result_reg); // equal |
3037 | |
3038 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
3039 __ delayed()->mov(G0, result_reg); // not equal | |
3040 | |
3041 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
3042 __ delayed()->mov(G0, result_reg); // not equal | |
3043 | |
3044 //load the lengths of arrays | |
727 | 3045 __ ld(Address(ary1_reg, length_offset), tmp1_reg); |
3046 __ ld(Address(ary2_reg, length_offset), tmp2_reg); | |
681 | 3047 |
3048 // return false if the two arrays are not equal length | |
3049 __ cmp(tmp1_reg, tmp2_reg); | |
3050 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
3051 __ delayed()->mov(G0, result_reg); // not equal | |
3052 | |
3839 | 3053 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn); |
681 | 3054 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
3055 | |
3056 // load array addresses | |
3057 __ add(ary1_reg, base_offset, ary1_reg); | |
3058 __ add(ary2_reg, base_offset, ary2_reg); | |
3059 | |
3060 // renaming registers | |
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3061 Register chr1_reg = result_reg; // for characters in ary1 |
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3062 Register chr2_reg = tmp2_reg; // for characters in ary2 |
681 | 3063 Register limit_reg = tmp1_reg; // length |
3064 | |
3065 // set byte count | |
3066 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
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3067 |
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3068 // Compare char[] arrays aligned to 4 bytes. |
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3069 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
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3070 chr1_reg, chr2_reg, Ldone); |
681 | 3071 __ add(G0, 1, result_reg); // equals |
3072 | |
3073 __ bind(Ldone); | |
3074 %} | |
3075 | |
0 | 3076 enc_class enc_rethrow() %{ |
1748 | 3077 cbuf.set_insts_mark(); |
0 | 3078 Register temp_reg = G3; |
727 | 3079 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
0 | 3080 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
3081 MacroAssembler _masm(&cbuf); | |
3082 #ifdef ASSERT | |
3083 __ save_frame(0); | |
727 | 3084 AddressLiteral last_rethrow_addrlit(&last_rethrow); |
3085 __ sethi(last_rethrow_addrlit, L1); | |
3086 Address addr(L1, last_rethrow_addrlit.low10()); | |
10997 | 3087 __ rdpc(L2); |
0 | 3088 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to |
727 | 3089 __ st_ptr(L2, addr); |
0 | 3090 __ restore(); |
3091 #endif | |
727 | 3092 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
0 | 3093 __ delayed()->nop(); |
3094 %} | |
3095 | |
3096 enc_class emit_mem_nop() %{ | |
3097 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
1748 | 3098 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); |
0 | 3099 %} |
3100 | |
3101 enc_class emit_fadd_nop() %{ | |
3102 // Generates the instruction FMOVS f31,f31 | |
1748 | 3103 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); |
0 | 3104 %} |
3105 | |
3106 enc_class emit_br_nop() %{ | |
3107 // Generates the instruction BPN,PN . | |
1748 | 3108 cbuf.insts()->emit_int32((unsigned int) 0x00400000); |
0 | 3109 %} |
3110 | |
3111 enc_class enc_membar_acquire %{ | |
3112 MacroAssembler _masm(&cbuf); | |
3113 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
3114 %} | |
3115 | |
3116 enc_class enc_membar_release %{ | |
3117 MacroAssembler _masm(&cbuf); | |
3118 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
3119 %} | |
3120 | |
3121 enc_class enc_membar_volatile %{ | |
3122 MacroAssembler _masm(&cbuf); | |
3123 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
3124 %} | |
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3125 |
0 | 3126 %} |
3127 | |
3128 //----------FRAME-------------------------------------------------------------- | |
3129 // Definition of frame structure and management information. | |
3130 // | |
3131 // S T A C K L A Y O U T Allocators stack-slot number | |
3132 // | (to get allocators register number | |
3133 // G Owned by | | v add VMRegImpl::stack0) | |
3134 // r CALLER | | | |
3135 // o | +--------+ pad to even-align allocators stack-slot | |
3136 // w V | pad0 | numbers; owned by CALLER | |
3137 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
3138 // h ^ | in | 5 | |
3139 // | | args | 4 Holes in incoming args owned by SELF | |
3140 // | | | | 3 | |
3141 // | | +--------+ | |
3142 // V | | old out| Empty on Intel, window on Sparc | |
3143 // | old |preserve| Must be even aligned. | |
3144 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
3145 // | | in | 3 area for Intel ret address | |
3146 // Owned by |preserve| Empty on Sparc. | |
3147 // SELF +--------+ | |
3148 // | | pad2 | 2 pad to align old SP | |
3149 // | +--------+ 1 | |
3150 // | | locks | 0 | |
3151 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
3152 // | | pad1 | 11 pad to align new SP | |
3153 // | +--------+ | |
3154 // | | | 10 | |
3155 // | | spills | 9 spills | |
3156 // V | | 8 (pad0 slot for callee) | |
3157 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
3158 // ^ | out | 7 | |
3159 // | | args | 6 Holes in outgoing args owned by CALLEE | |
3160 // Owned by +--------+ | |
3161 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
3162 // | new |preserve| Must be even-aligned. | |
3163 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
3164 // | | | | |
3165 // | |
3166 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
3167 // known from SELF's arguments and the Java calling convention. | |
3168 // Region 6-7 is determined per call site. | |
3169 // Note 2: If the calling convention leaves holes in the incoming argument | |
3170 // area, those holes are owned by SELF. Holes in the outgoing area | |
3171 // are owned by the CALLEE. Holes should not be nessecary in the | |
3172 // incoming area, as the Java calling convention is completely under | |
3173 // the control of the AD file. Doubles can be sorted and packed to | |
3174 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
3175 // varargs C calling conventions. | |
3176 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
3177 // even aligned with pad0 as needed. | |
3178 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
3179 // region 6-11 is even aligned; it may be padded out more so that | |
3180 // the region from SP to FP meets the minimum stack alignment. | |
3181 | |
3182 frame %{ | |
3183 // What direction does stack grow in (assumed to be same for native & Java) | |
3184 stack_direction(TOWARDS_LOW); | |
3185 | |
3186 // These two registers define part of the calling convention | |
3187 // between compiled code and the interpreter. | |
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3188 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C |
0 | 3189 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter |
3190 | |
3191 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
3192 cisc_spilling_operand_name(indOffset); | |
3193 | |
3194 // Number of stack slots consumed by a Monitor enter | |
3195 #ifdef _LP64 | |
3196 sync_stack_slots(2); | |
3197 #else | |
3198 sync_stack_slots(1); | |
3199 #endif | |
3200 | |
3201 // Compiled code's Frame Pointer | |
3202 frame_pointer(R_SP); | |
3203 | |
3204 // Stack alignment requirement | |
3205 stack_alignment(StackAlignmentInBytes); | |
3206 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
3207 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
3208 | |
3209 // Number of stack slots between incoming argument block and the start of | |
3210 // a new frame. The PROLOG must add this many slots to the stack. The | |
3211 // EPILOG must remove this many slots. | |
3212 in_preserve_stack_slots(0); | |
3213 | |
3214 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
3215 // for calls to C. Supports the var-args backing area for register parms. | |
3216 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
3217 #ifdef _LP64 | |
3218 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
3219 varargs_C_out_slots_killed(12); | |
3220 #else | |
3221 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
3222 varargs_C_out_slots_killed( 7); | |
3223 #endif | |
3224 | |
3225 // The after-PROLOG location of the return address. Location of | |
3226 // return address specifies a type (REG or STACK) and a number | |
3227 // representing the register number (i.e. - use a register name) or | |
3228 // stack slot. | |
3229 return_addr(REG R_I7); // Ret Addr is in register I7 | |
3230 | |
3231 // Body of function which returns an OptoRegs array locating | |
3232 // arguments either in registers or in stack slots for calling | |
3233 // java | |
3234 calling_convention %{ | |
3235 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
3236 | |
3237 %} | |
3238 | |
3239 // Body of function which returns an OptoRegs array locating | |
3240 // arguments either in registers or in stack slots for callin | |
3241 // C. | |
3242 c_calling_convention %{ | |
3243 // This is obviously always outgoing | |
14909 | 3244 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); |
0 | 3245 %} |
3246 | |
3247 // Location of native (C/C++) and interpreter return values. This is specified to | |
3248 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
3249 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
3250 // to and from the register pairs is done by the appropriate call and epilog | |
3251 // opcodes. This simplifies the register allocator. | |
3252 c_return_value %{ | |
3253 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3254 #ifdef _LP64 | |
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3255 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3256 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3257 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3258 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3259 #else // !_LP64 |
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3260 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3261 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
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3262 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3263 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
0 | 3264 #endif |
3265 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3266 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3267 %} | |
3268 | |
3269 // Location of compiled Java return values. Same as C | |
3270 return_value %{ | |
3271 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3272 #ifdef _LP64 | |
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3273 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3274 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3275 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3276 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3277 #else // !_LP64 |
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3278 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3279 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
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3280 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3281 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
0 | 3282 #endif |
3283 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3284 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3285 %} | |
3286 | |
3287 %} | |
3288 | |
3289 | |
3290 //----------ATTRIBUTES--------------------------------------------------------- | |
3291 //----------Operand Attributes------------------------------------------------- | |
3292 op_attrib op_cost(1); // Required cost attribute | |
3293 | |
3294 //----------Instruction Attributes--------------------------------------------- | |
3295 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
3842 | 3296 ins_attrib ins_size(32); // Required size attribute (in bits) |
3851 | 3297 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back |
3842 | 3298 ins_attrib ins_short_branch(0); // Required flag: is this instruction a |
3299 // non-matching short branch variant of some | |
0 | 3300 // long branch? |
3301 | |
3302 //----------OPERANDS----------------------------------------------------------- | |
3303 // Operand definitions must precede instruction definitions for correct parsing | |
3304 // in the ADLC because operands constitute user defined types which are used in | |
3305 // instruction definitions. | |
3306 | |
3307 //----------Simple Operands---------------------------------------------------- | |
3308 // Immediate Operands | |
3309 // Integer Immediate: 32-bit | |
3310 operand immI() %{ | |
3311 match(ConI); | |
3312 | |
3313 op_cost(0); | |
3314 // formats are generated automatically for constants and base registers | |
3315 format %{ %} | |
3316 interface(CONST_INTER); | |
3317 %} | |
3318 | |
824 | 3319 // Integer Immediate: 8-bit |
3320 operand immI8() %{ | |
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3321 predicate(Assembler::is_simm8(n->get_int())); |
824 | 3322 match(ConI); |
3323 op_cost(0); | |
3324 format %{ %} | |
3325 interface(CONST_INTER); | |
3326 %} | |
3327 | |
0 | 3328 // Integer Immediate: 13-bit |
3329 operand immI13() %{ | |
3330 predicate(Assembler::is_simm13(n->get_int())); | |
3331 match(ConI); | |
3332 op_cost(0); | |
3333 | |
3334 format %{ %} | |
3335 interface(CONST_INTER); | |
3336 %} | |
3337 | |
785 | 3338 // Integer Immediate: 13-bit minus 7 |
3339 operand immI13m7() %{ | |
3340 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); | |
3341 match(ConI); | |
3342 op_cost(0); | |
3343 | |
3344 format %{ %} | |
3345 interface(CONST_INTER); | |
3346 %} | |
3347 | |
824 | 3348 // Integer Immediate: 16-bit |
3349 operand immI16() %{ | |
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3350 predicate(Assembler::is_simm16(n->get_int())); |
824 | 3351 match(ConI); |
3352 op_cost(0); | |
3353 format %{ %} | |
3354 interface(CONST_INTER); | |
3355 %} | |
3356 | |
14909 | 3357 // Unsigned (positive) Integer Immediate: 13-bit |
3358 operand immU13() %{ | |
0 | 3359 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); |
3360 match(ConI); | |
3361 op_cost(0); | |
3362 | |
3363 format %{ %} | |
3364 interface(CONST_INTER); | |
3365 %} | |
3366 | |
3367 // Integer Immediate: 6-bit | |
3368 operand immU6() %{ | |
3369 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
3370 match(ConI); | |
3371 op_cost(0); | |
3372 format %{ %} | |
3373 interface(CONST_INTER); | |
3374 %} | |
3375 | |
3376 // Integer Immediate: 11-bit | |
3377 operand immI11() %{ | |
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3378 predicate(Assembler::is_simm11(n->get_int())); |
0 | 3379 match(ConI); |
3380 op_cost(0); | |
3381 format %{ %} | |
3382 interface(CONST_INTER); | |
3383 %} | |
3384 | |
3851 | 3385 // Integer Immediate: 5-bit |
3386 operand immI5() %{ | |
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3387 predicate(Assembler::is_simm5(n->get_int())); |
3851 | 3388 match(ConI); |
3389 op_cost(0); | |
3390 format %{ %} | |
3391 interface(CONST_INTER); | |
3392 %} | |
3393 | |
0 | 3394 // Integer Immediate: 0-bit |
3395 operand immI0() %{ | |
3396 predicate(n->get_int() == 0); | |
3397 match(ConI); | |
3398 op_cost(0); | |
3399 | |
3400 format %{ %} | |
3401 interface(CONST_INTER); | |
3402 %} | |
3403 | |
3404 // Integer Immediate: the value 10 | |
3405 operand immI10() %{ | |
3406 predicate(n->get_int() == 10); | |
3407 match(ConI); | |
3408 op_cost(0); | |
3409 | |
3410 format %{ %} | |
3411 interface(CONST_INTER); | |
3412 %} | |
3413 | |
3414 // Integer Immediate: the values 0-31 | |
3415 operand immU5() %{ | |
3416 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
3417 match(ConI); | |
3418 op_cost(0); | |
3419 | |
3420 format %{ %} | |
3421 interface(CONST_INTER); | |
3422 %} | |
3423 | |
3424 // Integer Immediate: the values 1-31 | |
3425 operand immI_1_31() %{ | |
3426 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
3427 match(ConI); | |
3428 op_cost(0); | |
3429 | |
3430 format %{ %} | |
3431 interface(CONST_INTER); | |
3432 %} | |
3433 | |
3434 // Integer Immediate: the values 32-63 | |
3435 operand immI_32_63() %{ | |
3436 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
3437 match(ConI); | |
3438 op_cost(0); | |
3439 | |
3440 format %{ %} | |
3441 interface(CONST_INTER); | |
3442 %} | |
3443 | |
785 | 3444 // Immediates for special shifts (sign extend) |
3445 | |
3446 // Integer Immediate: the value 16 | |
3447 operand immI_16() %{ | |
3448 predicate(n->get_int() == 16); | |
3449 match(ConI); | |
3450 op_cost(0); | |
3451 | |
3452 format %{ %} | |
3453 interface(CONST_INTER); | |
3454 %} | |
3455 | |
3456 // Integer Immediate: the value 24 | |
3457 operand immI_24() %{ | |
3458 predicate(n->get_int() == 24); | |
3459 match(ConI); | |
3460 op_cost(0); | |
3461 | |
3462 format %{ %} | |
3463 interface(CONST_INTER); | |
3464 %} | |
3465 | |
0 | 3466 // Integer Immediate: the value 255 |
3467 operand immI_255() %{ | |
3468 predicate( n->get_int() == 255 ); | |
3469 match(ConI); | |
3470 op_cost(0); | |
3471 | |
3472 format %{ %} | |
3473 interface(CONST_INTER); | |
3474 %} | |
3475 | |
785 | 3476 // Integer Immediate: the value 65535 |
3477 operand immI_65535() %{ | |
3478 predicate(n->get_int() == 65535); | |
3479 match(ConI); | |
3480 op_cost(0); | |
3481 | |
3482 format %{ %} | |
3483 interface(CONST_INTER); | |
3484 %} | |
3485 | |
0 | 3486 // Long Immediate: the value FF |
3487 operand immL_FF() %{ | |
3488 predicate( n->get_long() == 0xFFL ); | |
3489 match(ConL); | |
3490 op_cost(0); | |
3491 | |
3492 format %{ %} | |
3493 interface(CONST_INTER); | |
3494 %} | |
3495 | |
3496 // Long Immediate: the value FFFF | |
3497 operand immL_FFFF() %{ | |
3498 predicate( n->get_long() == 0xFFFFL ); | |
3499 match(ConL); | |
3500 op_cost(0); | |
3501 | |
3502 format %{ %} | |
3503 interface(CONST_INTER); | |
3504 %} | |
3505 | |
3506 // Pointer Immediate: 32 or 64-bit | |
3507 operand immP() %{ | |
3508 match(ConP); | |
3509 | |
3510 op_cost(5); | |
3511 // formats are generated automatically for constants and base registers | |
3512 format %{ %} | |
3513 interface(CONST_INTER); | |
3514 %} | |
3515 | |
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3516 #ifdef _LP64 |
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3517 // Pointer Immediate: 64-bit |
2008 | 3518 operand immP_set() %{ |
2080 | 3519 predicate(!VM_Version::is_niagara_plus()); |
2008 | 3520 match(ConP); |
3521 | |
3522 op_cost(5); | |
3523 // formats are generated automatically for constants and base registers | |
3524 format %{ %} | |
3525 interface(CONST_INTER); | |
3526 %} | |
3527 | |
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3528 // Pointer Immediate: 64-bit |
2008 | 3529 // From Niagara2 processors on a load should be better than materializing. |
3530 operand immP_load() %{ | |
2080 | 3531 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); |
2008 | 3532 match(ConP); |
3533 | |
3534 op_cost(5); | |
3535 // formats are generated automatically for constants and base registers | |
3536 format %{ %} | |
3537 interface(CONST_INTER); | |
3538 %} | |
3539 | |
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3540 // Pointer Immediate: 64-bit |
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3541 operand immP_no_oop_cheap() %{ |
2080 | 3542 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); |
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3543 match(ConP); |
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3544 |
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3545 op_cost(5); |
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3546 // formats are generated automatically for constants and base registers |
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3547 format %{ %} |
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3548 interface(CONST_INTER); |
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3549 %} |
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3550 #endif |
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3551 |
0 | 3552 operand immP13() %{ |
3553 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
3554 match(ConP); | |
3555 op_cost(0); | |
3556 | |
3557 format %{ %} | |
3558 interface(CONST_INTER); | |
3559 %} | |
3560 | |
3561 operand immP0() %{ | |
3562 predicate(n->get_ptr() == 0); | |
3563 match(ConP); | |
3564 op_cost(0); | |
3565 | |
3566 format %{ %} | |
3567 interface(CONST_INTER); | |
3568 %} | |
3569 | |
3570 operand immP_poll() %{ | |
3571 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
3572 match(ConP); | |
3573 | |
3574 // formats are generated automatically for constants and base registers | |
3575 format %{ %} | |
3576 interface(CONST_INTER); | |
3577 %} | |
3578 | |
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3579 // Pointer Immediate |
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3580 operand immN() |
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3581 %{ |
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3582 match(ConN); |
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3583 |
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3584 op_cost(10); |
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3585 format %{ %} |
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3586 interface(CONST_INTER); |
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3587 %} |
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3588 |
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3589 operand immNKlass() |
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3590 %{ |
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3591 match(ConNKlass); |
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3592 |
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3593 op_cost(10); |
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3594 format %{ %} |
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3595 interface(CONST_INTER); |
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3596 %} |
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3597 |
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3598 // NULL Pointer Immediate |
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3599 operand immN0() |
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3600 %{ |
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3601 predicate(n->get_narrowcon() == 0); |
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3602 match(ConN); |
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3603 |
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3604 op_cost(0); |
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3605 format %{ %} |
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3606 interface(CONST_INTER); |
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3607 %} |
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3608 |
0 | 3609 operand immL() %{ |
3610 match(ConL); | |
3611 op_cost(40); | |
3612 // formats are generated automatically for constants and base registers | |
3613 format %{ %} | |
3614 interface(CONST_INTER); | |
3615 %} | |
3616 | |
3617 operand immL0() %{ | |
3618 predicate(n->get_long() == 0L); | |
3619 match(ConL); | |
3620 op_cost(0); | |
3621 // formats are generated automatically for constants and base registers | |
3622 format %{ %} | |
3623 interface(CONST_INTER); | |
3624 %} | |
3625 | |
3851 | 3626 // Integer Immediate: 5-bit |
3627 operand immL5() %{ | |
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3628 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long())); |
3851 | 3629 match(ConL); |
3630 op_cost(0); | |
3631 format %{ %} | |
3632 interface(CONST_INTER); | |
3633 %} | |
3634 | |
0 | 3635 // Long Immediate: 13-bit |
3636 operand immL13() %{ | |
3637 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
3638 match(ConL); | |
3639 op_cost(0); | |
3640 | |
3641 format %{ %} | |
3642 interface(CONST_INTER); | |
3643 %} | |
3644 | |
785 | 3645 // Long Immediate: 13-bit minus 7 |
3646 operand immL13m7() %{ | |
3647 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); | |
3648 match(ConL); | |
3649 op_cost(0); | |
3650 | |
3651 format %{ %} | |
3652 interface(CONST_INTER); | |
3653 %} | |
3654 | |
0 | 3655 // Long Immediate: low 32-bit mask |
3656 operand immL_32bits() %{ | |
3657 predicate(n->get_long() == 0xFFFFFFFFL); | |
3658 match(ConL); | |
3659 op_cost(0); | |
3660 | |
3661 format %{ %} | |
3662 interface(CONST_INTER); | |
3663 %} | |
3664 | |
2008 | 3665 // Long Immediate: cheap (materialize in <= 3 instructions) |
3666 operand immL_cheap() %{ | |
2080 | 3667 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); |
2008 | 3668 match(ConL); |
3669 op_cost(0); | |
3670 | |
3671 format %{ %} | |
3672 interface(CONST_INTER); | |
3673 %} | |
3674 | |
3675 // Long Immediate: expensive (materialize in > 3 instructions) | |
3676 operand immL_expensive() %{ | |
2080 | 3677 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3); |
2008 | 3678 match(ConL); |
3679 op_cost(0); | |
3680 | |
3681 format %{ %} | |
3682 interface(CONST_INTER); | |
3683 %} | |
3684 | |
0 | 3685 // Double Immediate |
3686 operand immD() %{ | |
3687 match(ConD); | |
3688 | |
3689 op_cost(40); | |
3690 format %{ %} | |
3691 interface(CONST_INTER); | |
3692 %} | |
3693 | |
3694 operand immD0() %{ | |
3695 #ifdef _LP64 | |
3696 // on 64-bit architectures this comparision is faster | |
3697 predicate(jlong_cast(n->getd()) == 0); | |
3698 #else | |
3699 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
3700 #endif | |
3701 match(ConD); | |
3702 | |
3703 op_cost(0); | |
3704 format %{ %} | |
3705 interface(CONST_INTER); | |
3706 %} | |
3707 | |
3708 // Float Immediate | |
3709 operand immF() %{ | |
3710 match(ConF); | |
3711 | |
3712 op_cost(20); | |
3713 format %{ %} | |
3714 interface(CONST_INTER); | |
3715 %} | |
3716 | |
3717 // Float Immediate: 0 | |
3718 operand immF0() %{ | |
3719 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
3720 match(ConF); | |
3721 | |
3722 op_cost(0); | |
3723 format %{ %} | |
3724 interface(CONST_INTER); | |
3725 %} | |
3726 | |
3727 // Integer Register Operands | |
3728 // Integer Register | |
3729 operand iRegI() %{ | |
3730 constraint(ALLOC_IN_RC(int_reg)); | |
3731 match(RegI); | |
3732 | |
3733 match(notemp_iRegI); | |
3734 match(g1RegI); | |
3735 match(o0RegI); | |
3736 match(iRegIsafe); | |
3737 | |
3738 format %{ %} | |
3739 interface(REG_INTER); | |
3740 %} | |
3741 | |
3742 operand notemp_iRegI() %{ | |
3743 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
3744 match(RegI); | |
3745 | |
3746 match(o0RegI); | |
3747 | |
3748 format %{ %} | |
3749 interface(REG_INTER); | |
3750 %} | |
3751 | |
3752 operand o0RegI() %{ | |
3753 constraint(ALLOC_IN_RC(o0_regI)); | |
3754 match(iRegI); | |
3755 | |
3756 format %{ %} | |
3757 interface(REG_INTER); | |
3758 %} | |
3759 | |
3760 // Pointer Register | |
3761 operand iRegP() %{ | |
3762 constraint(ALLOC_IN_RC(ptr_reg)); | |
3763 match(RegP); | |
3764 | |
3765 match(lock_ptr_RegP); | |
3766 match(g1RegP); | |
3767 match(g2RegP); | |
3768 match(g3RegP); | |
3769 match(g4RegP); | |
3770 match(i0RegP); | |
3771 match(o0RegP); | |
3772 match(o1RegP); | |
3773 match(l7RegP); | |
3774 | |
3775 format %{ %} | |
3776 interface(REG_INTER); | |
3777 %} | |
3778 | |
3779 operand sp_ptr_RegP() %{ | |
3780 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
3781 match(RegP); | |
3782 match(iRegP); | |
3783 | |
3784 format %{ %} | |
3785 interface(REG_INTER); | |
3786 %} | |
3787 | |
3788 operand lock_ptr_RegP() %{ | |
3789 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
3790 match(RegP); | |
3791 match(i0RegP); | |
3792 match(o0RegP); | |
3793 match(o1RegP); | |
3794 match(l7RegP); | |
3795 | |
3796 format %{ %} | |
3797 interface(REG_INTER); | |
3798 %} | |
3799 | |
3800 operand g1RegP() %{ | |
3801 constraint(ALLOC_IN_RC(g1_regP)); | |
3802 match(iRegP); | |
3803 | |
3804 format %{ %} | |
3805 interface(REG_INTER); | |
3806 %} | |
3807 | |
3808 operand g2RegP() %{ | |
3809 constraint(ALLOC_IN_RC(g2_regP)); | |
3810 match(iRegP); | |
3811 | |
3812 format %{ %} | |
3813 interface(REG_INTER); | |
3814 %} | |
3815 | |
3816 operand g3RegP() %{ | |
3817 constraint(ALLOC_IN_RC(g3_regP)); | |
3818 match(iRegP); | |
3819 | |
3820 format %{ %} | |
3821 interface(REG_INTER); | |
3822 %} | |
3823 | |
3824 operand g1RegI() %{ | |
3825 constraint(ALLOC_IN_RC(g1_regI)); | |
3826 match(iRegI); | |
3827 | |
3828 format %{ %} | |
3829 interface(REG_INTER); | |
3830 %} | |
3831 | |
3832 operand g3RegI() %{ | |
3833 constraint(ALLOC_IN_RC(g3_regI)); | |
3834 match(iRegI); | |
3835 | |
3836 format %{ %} | |
3837 interface(REG_INTER); | |
3838 %} | |
3839 | |
3840 operand g4RegI() %{ | |
3841 constraint(ALLOC_IN_RC(g4_regI)); | |
3842 match(iRegI); | |
3843 | |
3844 format %{ %} | |
3845 interface(REG_INTER); | |
3846 %} | |
3847 | |
3848 operand g4RegP() %{ | |
3849 constraint(ALLOC_IN_RC(g4_regP)); | |
3850 match(iRegP); | |
3851 | |
3852 format %{ %} | |
3853 interface(REG_INTER); | |
3854 %} | |
3855 | |
3856 operand i0RegP() %{ | |
3857 constraint(ALLOC_IN_RC(i0_regP)); | |
3858 match(iRegP); | |
3859 | |
3860 format %{ %} | |
3861 interface(REG_INTER); | |
3862 %} | |
3863 | |
3864 operand o0RegP() %{ | |
3865 constraint(ALLOC_IN_RC(o0_regP)); | |
3866 match(iRegP); | |
3867 | |
3868 format %{ %} | |
3869 interface(REG_INTER); | |
3870 %} | |
3871 | |
3872 operand o1RegP() %{ | |
3873 constraint(ALLOC_IN_RC(o1_regP)); | |
3874 match(iRegP); | |
3875 | |
3876 format %{ %} | |
3877 interface(REG_INTER); | |
3878 %} | |
3879 | |
3880 operand o2RegP() %{ | |
3881 constraint(ALLOC_IN_RC(o2_regP)); | |
3882 match(iRegP); | |
3883 | |
3884 format %{ %} | |
3885 interface(REG_INTER); | |
3886 %} | |
3887 | |
3888 operand o7RegP() %{ | |
3889 constraint(ALLOC_IN_RC(o7_regP)); | |
3890 match(iRegP); | |
3891 | |
3892 format %{ %} | |
3893 interface(REG_INTER); | |
3894 %} | |
3895 | |
3896 operand l7RegP() %{ | |
3897 constraint(ALLOC_IN_RC(l7_regP)); | |
3898 match(iRegP); | |
3899 | |
3900 format %{ %} | |
3901 interface(REG_INTER); | |
3902 %} | |
3903 | |
3904 operand o7RegI() %{ | |
3905 constraint(ALLOC_IN_RC(o7_regI)); | |
3906 match(iRegI); | |
3907 | |
3908 format %{ %} | |
3909 interface(REG_INTER); | |
3910 %} | |
3911 | |
113
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3912 operand iRegN() %{ |
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3913 constraint(ALLOC_IN_RC(int_reg)); |
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3914 match(RegN); |
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3915 |
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3916 format %{ %} |
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3917 interface(REG_INTER); |
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3918 %} |
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3919 |
0 | 3920 // Long Register |
3921 operand iRegL() %{ | |
3922 constraint(ALLOC_IN_RC(long_reg)); | |
3923 match(RegL); | |
3924 | |
3925 format %{ %} | |
3926 interface(REG_INTER); | |
3927 %} | |
3928 | |
3929 operand o2RegL() %{ | |
3930 constraint(ALLOC_IN_RC(o2_regL)); | |
3931 match(iRegL); | |
3932 | |
3933 format %{ %} | |
3934 interface(REG_INTER); | |
3935 %} | |
3936 | |
3937 operand o7RegL() %{ | |
3938 constraint(ALLOC_IN_RC(o7_regL)); | |
3939 match(iRegL); | |
3940 | |
3941 format %{ %} | |
3942 interface(REG_INTER); | |
3943 %} | |
3944 | |
3945 operand g1RegL() %{ | |
3946 constraint(ALLOC_IN_RC(g1_regL)); | |
3947 match(iRegL); | |
3948 | |
3949 format %{ %} | |
3950 interface(REG_INTER); | |
3951 %} | |
3952 | |
420
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3953 operand g3RegL() %{ |
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3954 constraint(ALLOC_IN_RC(g3_regL)); |
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3955 match(iRegL); |
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|
3956 |
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3957 format %{ %} |
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3958 interface(REG_INTER); |
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3959 %} |
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3960 |
0 | 3961 // Int Register safe |
3962 // This is 64bit safe | |
3963 operand iRegIsafe() %{ | |
3964 constraint(ALLOC_IN_RC(long_reg)); | |
3965 | |
3966 match(iRegI); | |
3967 | |
3968 format %{ %} | |
3969 interface(REG_INTER); | |
3970 %} | |
3971 | |
3972 // Condition Code Flag Register | |
3973 operand flagsReg() %{ | |
3974 constraint(ALLOC_IN_RC(int_flags)); | |
3975 match(RegFlags); | |
3976 | |
3977 format %{ "ccr" %} // both ICC and XCC | |
3978 interface(REG_INTER); | |
3979 %} | |
3980 | |
3981 // Condition Code Register, unsigned comparisons. | |
3982 operand flagsRegU() %{ | |
3983 constraint(ALLOC_IN_RC(int_flags)); | |
3984 match(RegFlags); | |
3985 | |
3986 format %{ "icc_U" %} | |
3987 interface(REG_INTER); | |
3988 %} | |
3989 | |
3990 // Condition Code Register, pointer comparisons. | |
3991 operand flagsRegP() %{ | |
3992 constraint(ALLOC_IN_RC(int_flags)); | |
3993 match(RegFlags); | |
3994 | |
3995 #ifdef _LP64 | |
3996 format %{ "xcc_P" %} | |
3997 #else | |
3998 format %{ "icc_P" %} | |
3999 #endif | |
4000 interface(REG_INTER); | |
4001 %} | |
4002 | |
4003 // Condition Code Register, long comparisons. | |
4004 operand flagsRegL() %{ | |
4005 constraint(ALLOC_IN_RC(int_flags)); | |
4006 match(RegFlags); | |
4007 | |
4008 format %{ "xcc_L" %} | |
4009 interface(REG_INTER); | |
4010 %} | |
4011 | |
4012 // Condition Code Register, floating comparisons, unordered same as "less". | |
4013 operand flagsRegF() %{ | |
4014 constraint(ALLOC_IN_RC(float_flags)); | |
4015 match(RegFlags); | |
4016 match(flagsRegF0); | |
4017 | |
4018 format %{ %} | |
4019 interface(REG_INTER); | |
4020 %} | |
4021 | |
4022 operand flagsRegF0() %{ | |
4023 constraint(ALLOC_IN_RC(float_flag0)); | |
4024 match(RegFlags); | |
4025 | |
4026 format %{ %} | |
4027 interface(REG_INTER); | |
4028 %} | |
4029 | |
4030 | |
4031 // Condition Code Flag Register used by long compare | |
4032 operand flagsReg_long_LTGE() %{ | |
4033 constraint(ALLOC_IN_RC(int_flags)); | |
4034 match(RegFlags); | |
4035 format %{ "icc_LTGE" %} | |
4036 interface(REG_INTER); | |
4037 %} | |
4038 operand flagsReg_long_EQNE() %{ | |
4039 constraint(ALLOC_IN_RC(int_flags)); | |
4040 match(RegFlags); | |
4041 format %{ "icc_EQNE" %} | |
4042 interface(REG_INTER); | |
4043 %} | |
4044 operand flagsReg_long_LEGT() %{ | |
4045 constraint(ALLOC_IN_RC(int_flags)); | |
4046 match(RegFlags); | |
4047 format %{ "icc_LEGT" %} | |
4048 interface(REG_INTER); | |
4049 %} | |
4050 | |
4051 | |
4052 operand regD() %{ | |
4053 constraint(ALLOC_IN_RC(dflt_reg)); | |
4054 match(RegD); | |
4055 | |
551 | 4056 match(regD_low); |
4057 | |
0 | 4058 format %{ %} |
4059 interface(REG_INTER); | |
4060 %} | |
4061 | |
4062 operand regF() %{ | |
4063 constraint(ALLOC_IN_RC(sflt_reg)); | |
4064 match(RegF); | |
4065 | |
4066 format %{ %} | |
4067 interface(REG_INTER); | |
4068 %} | |
4069 | |
4070 operand regD_low() %{ | |
4071 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
551 | 4072 match(regD); |
0 | 4073 |
4074 format %{ %} | |
4075 interface(REG_INTER); | |
4076 %} | |
4077 | |
4078 // Special Registers | |
4079 | |
4080 // Method Register | |
4081 operand inline_cache_regP(iRegP reg) %{ | |
4082 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
4083 match(reg); | |
4084 format %{ %} | |
4085 interface(REG_INTER); | |
4086 %} | |
4087 | |
4088 operand interpreter_method_oop_regP(iRegP reg) %{ | |
4089 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
4090 match(reg); | |
4091 format %{ %} | |
4092 interface(REG_INTER); | |
4093 %} | |
4094 | |
4095 | |
4096 //----------Complex Operands--------------------------------------------------- | |
4097 // Indirect Memory Reference | |
4098 operand indirect(sp_ptr_RegP reg) %{ | |
4099 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4100 match(reg); | |
4101 | |
4102 op_cost(100); | |
4103 format %{ "[$reg]" %} | |
4104 interface(MEMORY_INTER) %{ | |
4105 base($reg); | |
4106 index(0x0); | |
4107 scale(0x0); | |
4108 disp(0x0); | |
4109 %} | |
4110 %} | |
4111 | |
785 | 4112 // Indirect with simm13 Offset |
0 | 4113 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
4114 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4115 match(AddP reg offset); | |
4116 | |
4117 op_cost(100); | |
4118 format %{ "[$reg + $offset]" %} | |
4119 interface(MEMORY_INTER) %{ | |
4120 base($reg); | |
4121 index(0x0); | |
4122 scale(0x0); | |
4123 disp($offset); | |
4124 %} | |
4125 %} | |
4126 | |
785 | 4127 // Indirect with simm13 Offset minus 7 |
4128 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ | |
4129 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4130 match(AddP reg offset); | |
4131 | |
4132 op_cost(100); | |
4133 format %{ "[$reg + $offset]" %} | |
4134 interface(MEMORY_INTER) %{ | |
4135 base($reg); | |
4136 index(0x0); | |
4137 scale(0x0); | |
4138 disp($offset); | |
4139 %} | |
4140 %} | |
4141 | |
0 | 4142 // Note: Intel has a swapped version also, like this: |
4143 //operand indOffsetX(iRegI reg, immP offset) %{ | |
4144 // constraint(ALLOC_IN_RC(int_reg)); | |
4145 // match(AddP offset reg); | |
4146 // | |
4147 // op_cost(100); | |
4148 // format %{ "[$reg + $offset]" %} | |
4149 // interface(MEMORY_INTER) %{ | |
4150 // base($reg); | |
4151 // index(0x0); | |
4152 // scale(0x0); | |
4153 // disp($offset); | |
4154 // %} | |
4155 //%} | |
4156 //// However, it doesn't make sense for SPARC, since | |
4157 // we have no particularly good way to embed oops in | |
4158 // single instructions. | |
4159 | |
4160 // Indirect with Register Index | |
4161 operand indIndex(iRegP addr, iRegX index) %{ | |
4162 constraint(ALLOC_IN_RC(ptr_reg)); | |
4163 match(AddP addr index); | |
4164 | |
4165 op_cost(100); | |
4166 format %{ "[$addr + $index]" %} | |
4167 interface(MEMORY_INTER) %{ | |
4168 base($addr); | |
4169 index($index); | |
4170 scale(0x0); | |
4171 disp(0x0); | |
4172 %} | |
4173 %} | |
4174 | |
4175 //----------Special Memory Operands-------------------------------------------- | |
4176 // Stack Slot Operand - This operand is used for loading and storing temporary | |
4177 // values on the stack where a match requires a value to | |
4178 // flow through memory. | |
4179 operand stackSlotI(sRegI reg) %{ | |
4180 constraint(ALLOC_IN_RC(stack_slots)); | |
4181 op_cost(100); | |
4182 //match(RegI); | |
4183 format %{ "[$reg]" %} | |
4184 interface(MEMORY_INTER) %{ | |
4185 base(0xE); // R_SP | |
4186 index(0x0); | |
4187 scale(0x0); | |
4188 disp($reg); // Stack Offset | |
4189 %} | |
4190 %} | |
4191 | |
4192 operand stackSlotP(sRegP reg) %{ | |
4193 constraint(ALLOC_IN_RC(stack_slots)); | |
4194 op_cost(100); | |
4195 //match(RegP); | |
4196 format %{ "[$reg]" %} | |
4197 interface(MEMORY_INTER) %{ | |
4198 base(0xE); // R_SP | |
4199 index(0x0); | |
4200 scale(0x0); | |
4201 disp($reg); // Stack Offset | |
4202 %} | |
4203 %} | |
4204 | |
4205 operand stackSlotF(sRegF reg) %{ | |
4206 constraint(ALLOC_IN_RC(stack_slots)); | |
4207 op_cost(100); | |
4208 //match(RegF); | |
4209 format %{ "[$reg]" %} | |
4210 interface(MEMORY_INTER) %{ | |
4211 base(0xE); // R_SP | |
4212 index(0x0); | |
4213 scale(0x0); | |
4214 disp($reg); // Stack Offset | |
4215 %} | |
4216 %} | |
4217 operand stackSlotD(sRegD reg) %{ | |
4218 constraint(ALLOC_IN_RC(stack_slots)); | |
4219 op_cost(100); | |
4220 //match(RegD); | |
4221 format %{ "[$reg]" %} | |
4222 interface(MEMORY_INTER) %{ | |
4223 base(0xE); // R_SP | |
4224 index(0x0); | |
4225 scale(0x0); | |
4226 disp($reg); // Stack Offset | |
4227 %} | |
4228 %} | |
4229 operand stackSlotL(sRegL reg) %{ | |
4230 constraint(ALLOC_IN_RC(stack_slots)); | |
4231 op_cost(100); | |
4232 //match(RegL); | |
4233 format %{ "[$reg]" %} | |
4234 interface(MEMORY_INTER) %{ | |
4235 base(0xE); // R_SP | |
4236 index(0x0); | |
4237 scale(0x0); | |
4238 disp($reg); // Stack Offset | |
4239 %} | |
4240 %} | |
4241 | |
4242 // Operands for expressing Control Flow | |
4243 // NOTE: Label is a predefined operand which should not be redefined in | |
4244 // the AD file. It is generically handled within the ADLC. | |
4245 | |
4246 //----------Conditional Branch Operands---------------------------------------- | |
4247 // Comparison Op - This is the operation of the comparison, and is limited to | |
4248 // the following set of codes: | |
4249 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
4250 // | |
4251 // Other attributes of the comparison, such as unsignedness, are specified | |
4252 // by the comparison instruction that sets a condition code flags register. | |
4253 // That result is represented by a flags operand whose subtype is appropriate | |
4254 // to the unsignedness (etc.) of the comparison. | |
4255 // | |
4256 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
4257 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
4258 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
4259 | |
4260 operand cmpOp() %{ | |
4261 match(Bool); | |
4262 | |
4263 format %{ "" %} | |
4264 interface(COND_INTER) %{ | |
4265 equal(0x1); | |
4266 not_equal(0x9); | |
4267 less(0x3); | |
4268 greater_equal(0xB); | |
4269 less_equal(0x2); | |
4270 greater(0xA); | |
12323 | 4271 overflow(0x7); |
4272 no_overflow(0xF); | |
0 | 4273 %} |
4274 %} | |
4275 | |
4276 // Comparison Op, unsigned | |
4277 operand cmpOpU() %{ | |
4278 match(Bool); | |
12323 | 4279 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4280 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
0 | 4281 |
4282 format %{ "u" %} | |
4283 interface(COND_INTER) %{ | |
4284 equal(0x1); | |
4285 not_equal(0x9); | |
4286 less(0x5); | |
4287 greater_equal(0xD); | |
4288 less_equal(0x4); | |
4289 greater(0xC); | |
12323 | 4290 overflow(0x7); |
4291 no_overflow(0xF); | |
0 | 4292 %} |
4293 %} | |
4294 | |
4295 // Comparison Op, pointer (same as unsigned) | |
4296 operand cmpOpP() %{ | |
4297 match(Bool); | |
12323 | 4298 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4299 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
0 | 4300 |
4301 format %{ "p" %} | |
4302 interface(COND_INTER) %{ | |
4303 equal(0x1); | |
4304 not_equal(0x9); | |
4305 less(0x5); | |
4306 greater_equal(0xD); | |
4307 less_equal(0x4); | |
4308 greater(0xC); | |
12323 | 4309 overflow(0x7); |
4310 no_overflow(0xF); | |
0 | 4311 %} |
4312 %} | |
4313 | |
4314 // Comparison Op, branch-register encoding | |
4315 operand cmpOp_reg() %{ | |
4316 match(Bool); | |
12323 | 4317 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4318 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
0 | 4319 |
4320 format %{ "" %} | |
4321 interface(COND_INTER) %{ | |
4322 equal (0x1); | |
4323 not_equal (0x5); | |
4324 less (0x3); | |
4325 greater_equal(0x7); | |
4326 less_equal (0x2); | |
4327 greater (0x6); | |
12323 | 4328 overflow(0x7); // not supported |
4329 no_overflow(0xF); // not supported | |
0 | 4330 %} |
4331 %} | |
4332 | |
4333 // Comparison Code, floating, unordered same as less | |
4334 operand cmpOpF() %{ | |
4335 match(Bool); | |
12323 | 4336 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4337 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
0 | 4338 |
4339 format %{ "fl" %} | |
4340 interface(COND_INTER) %{ | |
4341 equal(0x9); | |
4342 not_equal(0x1); | |
4343 less(0x3); | |
4344 greater_equal(0xB); | |
4345 less_equal(0xE); | |
4346 greater(0x6); | |
12323 | 4347 |
4348 overflow(0x7); // not supported | |
4349 no_overflow(0xF); // not supported | |
0 | 4350 %} |
4351 %} | |
4352 | |
4353 // Used by long compare | |
4354 operand cmpOp_commute() %{ | |
4355 match(Bool); | |
12323 | 4356 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4357 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
0 | 4358 |
4359 format %{ "" %} | |
4360 interface(COND_INTER) %{ | |
4361 equal(0x1); | |
4362 not_equal(0x9); | |
4363 less(0xA); | |
4364 greater_equal(0x2); | |
4365 less_equal(0xB); | |
4366 greater(0x3); | |
12323 | 4367 overflow(0x7); |
4368 no_overflow(0xF); | |
0 | 4369 %} |
4370 %} | |
4371 | |
4372 //----------OPERAND CLASSES---------------------------------------------------- | |
4373 // Operand Classes are groups of operands that are used to simplify | |
605 | 4374 // instruction definitions by not requiring the AD writer to specify separate |
0 | 4375 // instructions for every form of operand when the instruction accepts |
4376 // multiple operand types with the same basic encoding and format. The classic | |
4377 // case of this is memory operands. | |
4378 opclass memory( indirect, indOffset13, indIndex ); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
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parents:
1367
diff
changeset
|
4379 opclass indIndexMemory( indIndex ); |
0 | 4380 |
4381 //----------PIPELINE----------------------------------------------------------- | |
4382 pipeline %{ | |
4383 | |
4384 //----------ATTRIBUTES--------------------------------------------------------- | |
4385 attributes %{ | |
4386 fixed_size_instructions; // Fixed size instructions | |
4387 branch_has_delay_slot; // Branch has delay slot following | |
4388 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
4389 instruction_unit_size = 4; // An instruction is 4 bytes long | |
4390 instruction_fetch_unit_size = 16; // The processor fetches one line | |
4391 instruction_fetch_units = 1; // of 16 bytes | |
4392 | |
4393 // List of nop instructions | |
4394 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
4395 %} | |
4396 | |
4397 //----------RESOURCES---------------------------------------------------------- | |
4398 // Resources are the functional units available to the machine | |
4399 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
4400 | |
4401 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
4402 // Pipeline Description specifies the stages in the machine's pipeline | |
4403 | |
4404 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
4405 | |
4406 //----------PIPELINE CLASSES--------------------------------------------------- | |
4407 // Pipeline Classes describe the stages in which input and output are | |
4408 // referenced by the hardware pipeline. | |
4409 | |
4410 // Integer ALU reg-reg operation | |
4411 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4412 single_instruction; | |
4413 dst : E(write); | |
4414 src1 : R(read); | |
4415 src2 : R(read); | |
4416 IALU : R; | |
4417 %} | |
4418 | |
4419 // Integer ALU reg-reg long operation | |
4420 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
4421 instruction_count(2); | |
4422 dst : E(write); | |
4423 src1 : R(read); | |
4424 src2 : R(read); | |
4425 IALU : R; | |
4426 IALU : R; | |
4427 %} | |
4428 | |
4429 // Integer ALU reg-reg long dependent operation | |
4430 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
4431 instruction_count(1); multiple_bundles; | |
4432 dst : E(write); | |
4433 src1 : R(read); | |
4434 src2 : R(read); | |
4435 cr : E(write); | |
4436 IALU : R(2); | |
4437 %} | |
4438 | |
4439 // Integer ALU reg-imm operaion | |
4440 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4441 single_instruction; | |
4442 dst : E(write); | |
4443 src1 : R(read); | |
4444 IALU : R; | |
4445 %} | |
4446 | |
4447 // Integer ALU reg-reg operation with condition code | |
4448 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
4449 single_instruction; | |
4450 dst : E(write); | |
4451 cr : E(write); | |
4452 src1 : R(read); | |
4453 src2 : R(read); | |
4454 IALU : R; | |
4455 %} | |
4456 | |
4457 // Integer ALU reg-imm operation with condition code | |
4458 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
4459 single_instruction; | |
4460 dst : E(write); | |
4461 cr : E(write); | |
4462 src1 : R(read); | |
4463 IALU : R; | |
4464 %} | |
4465 | |
4466 // Integer ALU zero-reg operation | |
4467 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
4468 single_instruction; | |
4469 dst : E(write); | |
4470 src2 : R(read); | |
4471 IALU : R; | |
4472 %} | |
4473 | |
4474 // Integer ALU zero-reg operation with condition code only | |
4475 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
4476 single_instruction; | |
4477 cr : E(write); | |
4478 src : R(read); | |
4479 IALU : R; | |
4480 %} | |
4481 | |
4482 // Integer ALU reg-reg operation with condition code only | |
4483 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4484 single_instruction; | |
4485 cr : E(write); | |
4486 src1 : R(read); | |
4487 src2 : R(read); | |
4488 IALU : R; | |
4489 %} | |
4490 | |
4491 // Integer ALU reg-imm operation with condition code only | |
4492 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4493 single_instruction; | |
4494 cr : E(write); | |
4495 src1 : R(read); | |
4496 IALU : R; | |
4497 %} | |
4498 | |
4499 // Integer ALU reg-reg-zero operation with condition code only | |
4500 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
4501 single_instruction; | |
4502 cr : E(write); | |
4503 src1 : R(read); | |
4504 src2 : R(read); | |
4505 IALU : R; | |
4506 %} | |
4507 | |
4508 // Integer ALU reg-imm-zero operation with condition code only | |
4509 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
4510 single_instruction; | |
4511 cr : E(write); | |
4512 src1 : R(read); | |
4513 IALU : R; | |
4514 %} | |
4515 | |
4516 // Integer ALU reg-reg operation with condition code, src1 modified | |
4517 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4518 single_instruction; | |
4519 cr : E(write); | |
4520 src1 : E(write); | |
4521 src1 : R(read); | |
4522 src2 : R(read); | |
4523 IALU : R; | |
4524 %} | |
4525 | |
4526 // Integer ALU reg-imm operation with condition code, src1 modified | |
4527 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4528 single_instruction; | |
4529 cr : E(write); | |
4530 src1 : E(write); | |
4531 src1 : R(read); | |
4532 IALU : R; | |
4533 %} | |
4534 | |
4535 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
4536 multiple_bundles; | |
4537 dst : E(write)+4; | |
4538 cr : E(write); | |
4539 src1 : R(read); | |
4540 src2 : R(read); | |
4541 IALU : R(3); | |
4542 BR : R(2); | |
4543 %} | |
4544 | |
4545 // Integer ALU operation | |
4546 pipe_class ialu_none(iRegI dst) %{ | |
4547 single_instruction; | |
4548 dst : E(write); | |
4549 IALU : R; | |
4550 %} | |
4551 | |
4552 // Integer ALU reg operation | |
4553 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
4554 single_instruction; may_have_no_code; | |
4555 dst : E(write); | |
4556 src : R(read); | |
4557 IALU : R; | |
4558 %} | |
4559 | |
4560 // Integer ALU reg conditional operation | |
4561 // This instruction has a 1 cycle stall, and cannot execute | |
4562 // in the same cycle as the instruction setting the condition | |
4563 // code. We kludge this by pretending to read the condition code | |
4564 // 1 cycle earlier, and by marking the functional units as busy | |
4565 // for 2 cycles with the result available 1 cycle later than | |
4566 // is really the case. | |
4567 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
4568 single_instruction; | |
4569 op2_out : C(write); | |
4570 op1 : R(read); | |
4571 cr : R(read); // This is really E, with a 1 cycle stall | |
4572 BR : R(2); | |
4573 MS : R(2); | |
4574 %} | |
4575 | |
4576 #ifdef _LP64 | |
4577 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
4578 instruction_count(1); multiple_bundles; | |
4579 dst : C(write)+1; | |
4580 src : R(read)+1; | |
4581 IALU : R(1); | |
4582 BR : E(2); | |
4583 MS : E(2); | |
4584 %} | |
4585 #endif | |
4586 | |
4587 // Integer ALU reg operation | |
4588 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
4589 single_instruction; may_have_no_code; | |
4590 dst : E(write); | |
4591 src : R(read); | |
4592 IALU : R; | |
4593 %} | |
4594 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
4595 single_instruction; may_have_no_code; | |
4596 dst : E(write); | |
4597 src : R(read); | |
4598 IALU : R; | |
4599 %} | |
4600 | |
4601 // Two integer ALU reg operations | |
4602 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
4603 instruction_count(2); | |
4604 dst : E(write); | |
4605 src : R(read); | |
4606 A0 : R; | |
4607 A1 : R; | |
4608 %} | |
4609 | |
4610 // Two integer ALU reg operations | |
4611 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
4612 instruction_count(2); may_have_no_code; | |
4613 dst : E(write); | |
4614 src : R(read); | |
4615 A0 : R; | |
4616 A1 : R; | |
4617 %} | |
4618 | |
4619 // Integer ALU imm operation | |
4620 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
4621 single_instruction; | |
4622 dst : E(write); | |
4623 IALU : R; | |
4624 %} | |
4625 | |
4626 // Integer ALU reg-reg with carry operation | |
4627 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
4628 single_instruction; | |
4629 dst : E(write); | |
4630 src1 : R(read); | |
4631 src2 : R(read); | |
4632 IALU : R; | |
4633 %} | |
4634 | |
4635 // Integer ALU cc operation | |
4636 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
4637 single_instruction; | |
4638 dst : E(write); | |
4639 cc : R(read); | |
4640 IALU : R; | |
4641 %} | |
4642 | |
4643 // Integer ALU cc / second IALU operation | |
4644 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
4645 instruction_count(1); multiple_bundles; | |
4646 dst : E(write)+1; | |
4647 src : R(read); | |
4648 IALU : R; | |
4649 %} | |
4650 | |
4651 // Integer ALU cc / second IALU operation | |
4652 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
4653 instruction_count(1); multiple_bundles; | |
4654 dst : E(write)+1; | |
4655 p : R(read); | |
4656 q : R(read); | |
4657 IALU : R; | |
4658 %} | |
4659 | |
4660 // Integer ALU hi-lo-reg operation | |
4661 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
4662 instruction_count(1); multiple_bundles; | |
4663 dst : E(write)+1; | |
4664 IALU : R(2); | |
4665 %} | |
4666 | |
4667 // Float ALU hi-lo-reg operation (with temp) | |
4668 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
4669 instruction_count(1); multiple_bundles; | |
4670 dst : E(write)+1; | |
4671 IALU : R(2); | |
4672 %} | |
4673 | |
4674 // Long Constant | |
4675 pipe_class loadConL( iRegL dst, immL src ) %{ | |
4676 instruction_count(2); multiple_bundles; | |
4677 dst : E(write)+1; | |
4678 IALU : R(2); | |
4679 IALU : R(2); | |
4680 %} | |
4681 | |
4682 // Pointer Constant | |
4683 pipe_class loadConP( iRegP dst, immP src ) %{ | |
4684 instruction_count(0); multiple_bundles; | |
4685 fixed_latency(6); | |
4686 %} | |
4687 | |
4688 // Polling Address | |
4689 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
4690 #ifdef _LP64 | |
4691 instruction_count(0); multiple_bundles; | |
4692 fixed_latency(6); | |
4693 #else | |
4694 dst : E(write); | |
4695 IALU : R; | |
4696 #endif | |
4697 %} | |
4698 | |
4699 // Long Constant small | |
4700 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
4701 instruction_count(2); | |
4702 dst : E(write); | |
4703 IALU : R; | |
4704 IALU : R; | |
4705 %} | |
4706 | |
4707 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
4708 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
4709 instruction_count(1); multiple_bundles; | |
4710 src : R(read); | |
4711 dst : M(write)+1; | |
4712 IALU : R; | |
4713 MS : E; | |
4714 %} | |
4715 | |
4716 // Integer ALU nop operation | |
4717 pipe_class ialu_nop() %{ | |
4718 single_instruction; | |
4719 IALU : R; | |
4720 %} | |
4721 | |
4722 // Integer ALU nop operation | |
4723 pipe_class ialu_nop_A0() %{ | |
4724 single_instruction; | |
4725 A0 : R; | |
4726 %} | |
4727 | |
4728 // Integer ALU nop operation | |
4729 pipe_class ialu_nop_A1() %{ | |
4730 single_instruction; | |
4731 A1 : R; | |
4732 %} | |
4733 | |
4734 // Integer Multiply reg-reg operation | |
4735 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4736 single_instruction; | |
4737 dst : E(write); | |
4738 src1 : R(read); | |
4739 src2 : R(read); | |
4740 MS : R(5); | |
4741 %} | |
4742 | |
4743 // Integer Multiply reg-imm operation | |
4744 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4745 single_instruction; | |
4746 dst : E(write); | |
4747 src1 : R(read); | |
4748 MS : R(5); | |
4749 %} | |
4750 | |
4751 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4752 single_instruction; | |
4753 dst : E(write)+4; | |
4754 src1 : R(read); | |
4755 src2 : R(read); | |
4756 MS : R(6); | |
4757 %} | |
4758 | |
4759 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4760 single_instruction; | |
4761 dst : E(write)+4; | |
4762 src1 : R(read); | |
4763 MS : R(6); | |
4764 %} | |
4765 | |
4766 // Integer Divide reg-reg | |
4767 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
4768 instruction_count(1); multiple_bundles; | |
4769 dst : E(write); | |
4770 temp : E(write); | |
4771 src1 : R(read); | |
4772 src2 : R(read); | |
4773 temp : R(read); | |
4774 MS : R(38); | |
4775 %} | |
4776 | |
4777 // Integer Divide reg-imm | |
4778 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
4779 instruction_count(1); multiple_bundles; | |
4780 dst : E(write); | |
4781 temp : E(write); | |
4782 src1 : R(read); | |
4783 temp : R(read); | |
4784 MS : R(38); | |
4785 %} | |
4786 | |
4787 // Long Divide | |
4788 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4789 dst : E(write)+71; | |
4790 src1 : R(read); | |
4791 src2 : R(read)+1; | |
4792 MS : R(70); | |
4793 %} | |
4794 | |
4795 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4796 dst : E(write)+71; | |
4797 src1 : R(read); | |
4798 MS : R(70); | |
4799 %} | |
4800 | |
4801 // Floating Point Add Float | |
4802 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4803 single_instruction; | |
4804 dst : X(write); | |
4805 src1 : E(read); | |
4806 src2 : E(read); | |
4807 FA : R; | |
4808 %} | |
4809 | |
4810 // Floating Point Add Double | |
4811 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4812 single_instruction; | |
4813 dst : X(write); | |
4814 src1 : E(read); | |
4815 src2 : E(read); | |
4816 FA : R; | |
4817 %} | |
4818 | |
4819 // Floating Point Conditional Move based on integer flags | |
4820 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
4821 single_instruction; | |
4822 dst : X(write); | |
4823 src : E(read); | |
4824 cr : R(read); | |
4825 FA : R(2); | |
4826 BR : R(2); | |
4827 %} | |
4828 | |
4829 // Floating Point Conditional Move based on integer flags | |
4830 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
4831 single_instruction; | |
4832 dst : X(write); | |
4833 src : E(read); | |
4834 cr : R(read); | |
4835 FA : R(2); | |
4836 BR : R(2); | |
4837 %} | |
4838 | |
4839 // Floating Point Multiply Float | |
4840 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4841 single_instruction; | |
4842 dst : X(write); | |
4843 src1 : E(read); | |
4844 src2 : E(read); | |
4845 FM : R; | |
4846 %} | |
4847 | |
4848 // Floating Point Multiply Double | |
4849 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4850 single_instruction; | |
4851 dst : X(write); | |
4852 src1 : E(read); | |
4853 src2 : E(read); | |
4854 FM : R; | |
4855 %} | |
4856 | |
4857 // Floating Point Divide Float | |
4858 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4859 single_instruction; | |
4860 dst : X(write); | |
4861 src1 : E(read); | |
4862 src2 : E(read); | |
4863 FM : R; | |
4864 FDIV : C(14); | |
4865 %} | |
4866 | |
4867 // Floating Point Divide Double | |
4868 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4869 single_instruction; | |
4870 dst : X(write); | |
4871 src1 : E(read); | |
4872 src2 : E(read); | |
4873 FM : R; | |
4874 FDIV : C(17); | |
4875 %} | |
4876 | |
4877 // Floating Point Move/Negate/Abs Float | |
4878 pipe_class faddF_reg(regF dst, regF src) %{ | |
4879 single_instruction; | |
4880 dst : W(write); | |
4881 src : E(read); | |
4882 FA : R(1); | |
4883 %} | |
4884 | |
4885 // Floating Point Move/Negate/Abs Double | |
4886 pipe_class faddD_reg(regD dst, regD src) %{ | |
4887 single_instruction; | |
4888 dst : W(write); | |
4889 src : E(read); | |
4890 FA : R; | |
4891 %} | |
4892 | |
4893 // Floating Point Convert F->D | |
4894 pipe_class fcvtF2D(regD dst, regF src) %{ | |
4895 single_instruction; | |
4896 dst : X(write); | |
4897 src : E(read); | |
4898 FA : R; | |
4899 %} | |
4900 | |
4901 // Floating Point Convert I->D | |
4902 pipe_class fcvtI2D(regD dst, regF src) %{ | |
4903 single_instruction; | |
4904 dst : X(write); | |
4905 src : E(read); | |
4906 FA : R; | |
4907 %} | |
4908 | |
4909 // Floating Point Convert LHi->D | |
4910 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
4911 single_instruction; | |
4912 dst : X(write); | |
4913 src : E(read); | |
4914 FA : R; | |
4915 %} | |
4916 | |
4917 // Floating Point Convert L->D | |
4918 pipe_class fcvtL2D(regD dst, regF src) %{ | |
4919 single_instruction; | |
4920 dst : X(write); | |
4921 src : E(read); | |
4922 FA : R; | |
4923 %} | |
4924 | |
4925 // Floating Point Convert L->F | |
4926 pipe_class fcvtL2F(regD dst, regF src) %{ | |
4927 single_instruction; | |
4928 dst : X(write); | |
4929 src : E(read); | |
4930 FA : R; | |
4931 %} | |
4932 | |
4933 // Floating Point Convert D->F | |
4934 pipe_class fcvtD2F(regD dst, regF src) %{ | |
4935 single_instruction; | |
4936 dst : X(write); | |
4937 src : E(read); | |
4938 FA : R; | |
4939 %} | |
4940 | |
4941 // Floating Point Convert I->L | |
4942 pipe_class fcvtI2L(regD dst, regF src) %{ | |
4943 single_instruction; | |
4944 dst : X(write); | |
4945 src : E(read); | |
4946 FA : R; | |
4947 %} | |
4948 | |
4949 // Floating Point Convert D->F | |
4950 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
4951 instruction_count(1); multiple_bundles; | |
4952 dst : X(write)+6; | |
4953 src : E(read); | |
4954 FA : R; | |
4955 %} | |
4956 | |
4957 // Floating Point Convert D->L | |
4958 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
4959 instruction_count(1); multiple_bundles; | |
4960 dst : X(write)+6; | |
4961 src : E(read); | |
4962 FA : R; | |
4963 %} | |
4964 | |
4965 // Floating Point Convert F->I | |
4966 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
4967 instruction_count(1); multiple_bundles; | |
4968 dst : X(write)+6; | |
4969 src : E(read); | |
4970 FA : R; | |
4971 %} | |
4972 | |
4973 // Floating Point Convert F->L | |
4974 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
4975 instruction_count(1); multiple_bundles; | |
4976 dst : X(write)+6; | |
4977 src : E(read); | |
4978 FA : R; | |
4979 %} | |
4980 | |
4981 // Floating Point Convert I->F | |
4982 pipe_class fcvtI2F(regF dst, regF src) %{ | |
4983 single_instruction; | |
4984 dst : X(write); | |
4985 src : E(read); | |
4986 FA : R; | |
4987 %} | |
4988 | |
4989 // Floating Point Compare | |
4990 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
4991 single_instruction; | |
4992 cr : X(write); | |
4993 src1 : E(read); | |
4994 src2 : E(read); | |
4995 FA : R; | |
4996 %} | |
4997 | |
4998 // Floating Point Compare | |
4999 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
5000 single_instruction; | |
5001 cr : X(write); | |
5002 src1 : E(read); | |
5003 src2 : E(read); | |
5004 FA : R; | |
5005 %} | |
5006 | |
5007 // Floating Add Nop | |
5008 pipe_class fadd_nop() %{ | |
5009 single_instruction; | |
5010 FA : R; | |
5011 %} | |
5012 | |
5013 // Integer Store to Memory | |
5014 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
5015 single_instruction; | |
5016 mem : R(read); | |
5017 src : C(read); | |
5018 MS : R; | |
5019 %} | |
5020 | |
5021 // Integer Store to Memory | |
5022 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
5023 single_instruction; | |
5024 mem : R(read); | |
5025 src : C(read); | |
5026 MS : R; | |
5027 %} | |
5028 | |
5029 // Integer Store Zero to Memory | |
5030 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
5031 single_instruction; | |
5032 mem : R(read); | |
5033 MS : R; | |
5034 %} | |
5035 | |
5036 // Special Stack Slot Store | |
5037 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
5038 single_instruction; | |
5039 stkSlot : R(read); | |
5040 src : C(read); | |
5041 MS : R; | |
5042 %} | |
5043 | |
5044 // Special Stack Slot Store | |
5045 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
5046 instruction_count(2); multiple_bundles; | |
5047 stkSlot : R(read); | |
5048 src : C(read); | |
5049 MS : R(2); | |
5050 %} | |
5051 | |
5052 // Float Store | |
5053 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
5054 single_instruction; | |
5055 mem : R(read); | |
5056 src : C(read); | |
5057 MS : R; | |
5058 %} | |
5059 | |
5060 // Float Store | |
5061 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
5062 single_instruction; | |
5063 mem : R(read); | |
5064 MS : R; | |
5065 %} | |
5066 | |
5067 // Double Store | |
5068 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
5069 instruction_count(1); | |
5070 mem : R(read); | |
5071 src : C(read); | |
5072 MS : R; | |
5073 %} | |
5074 | |
5075 // Double Store | |
5076 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
5077 single_instruction; | |
5078 mem : R(read); | |
5079 MS : R; | |
5080 %} | |
5081 | |
5082 // Special Stack Slot Float Store | |
5083 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
5084 single_instruction; | |
5085 stkSlot : R(read); | |
5086 src : C(read); | |
5087 MS : R; | |
5088 %} | |
5089 | |
5090 // Special Stack Slot Double Store | |
5091 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
5092 single_instruction; | |
5093 stkSlot : R(read); | |
5094 src : C(read); | |
5095 MS : R; | |
5096 %} | |
5097 | |
5098 // Integer Load (when sign bit propagation not needed) | |
5099 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
5100 single_instruction; | |
5101 mem : R(read); | |
5102 dst : C(write); | |
5103 MS : R; | |
5104 %} | |
5105 | |
5106 // Integer Load from stack operand | |
5107 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
5108 single_instruction; | |
5109 mem : R(read); | |
5110 dst : C(write); | |
5111 MS : R; | |
5112 %} | |
5113 | |
5114 // Integer Load (when sign bit propagation or masking is needed) | |
5115 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
5116 single_instruction; | |
5117 mem : R(read); | |
5118 dst : M(write); | |
5119 MS : R; | |
5120 %} | |
5121 | |
5122 // Float Load | |
5123 pipe_class floadF_mem(regF dst, memory mem) %{ | |
5124 single_instruction; | |
5125 mem : R(read); | |
5126 dst : M(write); | |
5127 MS : R; | |
5128 %} | |
5129 | |
5130 // Float Load | |
5131 pipe_class floadD_mem(regD dst, memory mem) %{ | |
5132 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
5133 mem : R(read); | |
5134 dst : M(write); | |
5135 MS : R; | |
5136 %} | |
5137 | |
5138 // Float Load | |
5139 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
5140 single_instruction; | |
5141 stkSlot : R(read); | |
5142 dst : M(write); | |
5143 MS : R; | |
5144 %} | |
5145 | |
5146 // Float Load | |
5147 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
5148 single_instruction; | |
5149 stkSlot : R(read); | |
5150 dst : M(write); | |
5151 MS : R; | |
5152 %} | |
5153 | |
5154 // Memory Nop | |
5155 pipe_class mem_nop() %{ | |
5156 single_instruction; | |
5157 MS : R; | |
5158 %} | |
5159 | |
5160 pipe_class sethi(iRegP dst, immI src) %{ | |
5161 single_instruction; | |
5162 dst : E(write); | |
5163 IALU : R; | |
5164 %} | |
5165 | |
5166 pipe_class loadPollP(iRegP poll) %{ | |
5167 single_instruction; | |
5168 poll : R(read); | |
5169 MS : R; | |
5170 %} | |
5171 | |
5172 pipe_class br(Universe br, label labl) %{ | |
5173 single_instruction_with_delay_slot; | |
5174 BR : R; | |
5175 %} | |
5176 | |
5177 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
5178 single_instruction_with_delay_slot; | |
5179 cr : E(read); | |
5180 BR : R; | |
5181 %} | |
5182 | |
5183 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
5184 single_instruction_with_delay_slot; | |
5185 op1 : E(read); | |
5186 BR : R; | |
5187 MS : R; | |
5188 %} | |
5189 | |
3851 | 5190 // Compare and branch |
5191 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ | |
5192 instruction_count(2); has_delay_slot; | |
5193 cr : E(write); | |
5194 src1 : R(read); | |
5195 src2 : R(read); | |
5196 IALU : R; | |
5197 BR : R; | |
5198 %} | |
5199 | |
5200 // Compare and branch | |
5201 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ | |
5202 instruction_count(2); has_delay_slot; | |
5203 cr : E(write); | |
5204 src1 : R(read); | |
5205 IALU : R; | |
5206 BR : R; | |
5207 %} | |
5208 | |
5209 // Compare and branch using cbcond | |
5210 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ | |
5211 single_instruction; | |
5212 src1 : E(read); | |
5213 src2 : E(read); | |
5214 IALU : R; | |
5215 BR : R; | |
5216 %} | |
5217 | |
5218 // Compare and branch using cbcond | |
5219 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ | |
5220 single_instruction; | |
5221 src1 : E(read); | |
5222 IALU : R; | |
5223 BR : R; | |
5224 %} | |
5225 | |
0 | 5226 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ |
5227 single_instruction_with_delay_slot; | |
5228 cr : E(read); | |
5229 BR : R; | |
5230 %} | |
5231 | |
5232 pipe_class br_nop() %{ | |
5233 single_instruction; | |
5234 BR : R; | |
5235 %} | |
5236 | |
5237 pipe_class simple_call(method meth) %{ | |
5238 instruction_count(2); multiple_bundles; force_serialization; | |
5239 fixed_latency(100); | |
5240 BR : R(1); | |
5241 MS : R(1); | |
5242 A0 : R(1); | |
5243 %} | |
5244 | |
5245 pipe_class compiled_call(method meth) %{ | |
5246 instruction_count(1); multiple_bundles; force_serialization; | |
5247 fixed_latency(100); | |
5248 MS : R(1); | |
5249 %} | |
5250 | |
5251 pipe_class call(method meth) %{ | |
5252 instruction_count(0); multiple_bundles; force_serialization; | |
5253 fixed_latency(100); | |
5254 %} | |
5255 | |
5256 pipe_class tail_call(Universe ignore, label labl) %{ | |
5257 single_instruction; has_delay_slot; | |
5258 fixed_latency(100); | |
5259 BR : R(1); | |
5260 MS : R(1); | |
5261 %} | |
5262 | |
5263 pipe_class ret(Universe ignore) %{ | |
5264 single_instruction; has_delay_slot; | |
5265 BR : R(1); | |
5266 MS : R(1); | |
5267 %} | |
5268 | |
5269 pipe_class ret_poll(g3RegP poll) %{ | |
5270 instruction_count(3); has_delay_slot; | |
5271 poll : E(read); | |
5272 MS : R; | |
5273 %} | |
5274 | |
5275 // The real do-nothing guy | |
5276 pipe_class empty( ) %{ | |
5277 instruction_count(0); | |
5278 %} | |
5279 | |
5280 pipe_class long_memory_op() %{ | |
5281 instruction_count(0); multiple_bundles; force_serialization; | |
5282 fixed_latency(25); | |
5283 MS : R(1); | |
5284 %} | |
5285 | |
5286 // Check-cast | |
5287 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
5288 array : R(read); | |
5289 match : R(read); | |
5290 IALU : R(2); | |
5291 BR : R(2); | |
5292 MS : R; | |
5293 %} | |
5294 | |
5295 // Convert FPU flags into +1,0,-1 | |
5296 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
5297 src1 : E(read); | |
5298 src2 : E(read); | |
5299 dst : E(write); | |
5300 FA : R; | |
5301 MS : R(2); | |
5302 BR : R(2); | |
5303 %} | |
5304 | |
5305 // Compare for p < q, and conditionally add y | |
5306 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
5307 p : E(read); | |
5308 q : E(read); | |
5309 y : E(read); | |
5310 IALU : R(3) | |
5311 %} | |
5312 | |
5313 // Perform a compare, then move conditionally in a branch delay slot. | |
5314 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
5315 src2 : E(read); | |
5316 srcdst : E(read); | |
5317 IALU : R; | |
5318 BR : R; | |
5319 %} | |
5320 | |
5321 // Define the class for the Nop node | |
5322 define %{ | |
5323 MachNop = ialu_nop; | |
5324 %} | |
5325 | |
5326 %} | |
5327 | |
5328 //----------INSTRUCTIONS------------------------------------------------------- | |
5329 | |
5330 //------------Special Stack Slot instructions - no match rules----------------- | |
5331 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
5332 // No match rule to avoid chain rule match. | |
5333 effect(DEF dst, USE src); | |
5334 ins_cost(MEMORY_REF_COST); | |
5335 size(4); | |
5336 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
5337 opcode(Assembler::ldf_op3); | |
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5338 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5339 ins_pipe(floadF_stk); |
5340 %} | |
5341 | |
5342 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
5343 // No match rule to avoid chain rule match. | |
5344 effect(DEF dst, USE src); | |
5345 ins_cost(MEMORY_REF_COST); | |
5346 size(4); | |
5347 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
5348 opcode(Assembler::lddf_op3); | |
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5349 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5350 ins_pipe(floadD_stk); |
5351 %} | |
5352 | |
5353 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
5354 // No match rule to avoid chain rule match. | |
5355 effect(DEF dst, USE src); | |
5356 ins_cost(MEMORY_REF_COST); | |
5357 size(4); | |
5358 format %{ "STF $src,$dst\t! regF to stkI" %} | |
5359 opcode(Assembler::stf_op3); | |
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5360 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5361 ins_pipe(fstoreF_stk_reg); |
5362 %} | |
5363 | |
5364 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
5365 // No match rule to avoid chain rule match. | |
5366 effect(DEF dst, USE src); | |
5367 ins_cost(MEMORY_REF_COST); | |
5368 size(4); | |
5369 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
5370 opcode(Assembler::stdf_op3); | |
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5371 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5372 ins_pipe(fstoreD_stk_reg); |
5373 %} | |
5374 | |
5375 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
5376 effect(DEF dst, USE src); | |
5377 ins_cost(MEMORY_REF_COST*2); | |
5378 size(8); | |
5379 format %{ "STW $src,$dst.hi\t! long\n\t" | |
5380 "STW R_G0,$dst.lo" %} | |
5381 opcode(Assembler::stw_op3); | |
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5382 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
0 | 5383 ins_pipe(lstoreI_stk_reg); |
5384 %} | |
5385 | |
5386 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
5387 // No match rule to avoid chain rule match. | |
5388 effect(DEF dst, USE src); | |
5389 ins_cost(MEMORY_REF_COST); | |
5390 size(4); | |
5391 format %{ "STX $src,$dst\t! regL to stkD" %} | |
5392 opcode(Assembler::stx_op3); | |
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5393 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5394 ins_pipe(istore_stk_reg); |
5395 %} | |
5396 | |
5397 //---------- Chain stack slots between similar types -------- | |
5398 | |
5399 // Load integer from stack slot | |
5400 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
5401 match(Set dst src); | |
5402 ins_cost(MEMORY_REF_COST); | |
5403 | |
5404 size(4); | |
5405 format %{ "LDUW $src,$dst\t!stk" %} | |
5406 opcode(Assembler::lduw_op3); | |
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5407 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5408 ins_pipe(iload_mem); |
5409 %} | |
5410 | |
5411 // Store integer to stack slot | |
5412 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
5413 match(Set dst src); | |
5414 ins_cost(MEMORY_REF_COST); | |
5415 | |
5416 size(4); | |
5417 format %{ "STW $src,$dst\t!stk" %} | |
5418 opcode(Assembler::stw_op3); | |
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5419 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5420 ins_pipe(istore_mem_reg); |
5421 %} | |
5422 | |
5423 // Load long from stack slot | |
5424 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
5425 match(Set dst src); | |
5426 | |
5427 ins_cost(MEMORY_REF_COST); | |
5428 size(4); | |
5429 format %{ "LDX $src,$dst\t! long" %} | |
5430 opcode(Assembler::ldx_op3); | |
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5431 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5432 ins_pipe(iload_mem); |
5433 %} | |
5434 | |
5435 // Store long to stack slot | |
5436 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
5437 match(Set dst src); | |
5438 | |
5439 ins_cost(MEMORY_REF_COST); | |
5440 size(4); | |
5441 format %{ "STX $src,$dst\t! long" %} | |
5442 opcode(Assembler::stx_op3); | |
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5443 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5444 ins_pipe(istore_mem_reg); |
5445 %} | |
5446 | |
5447 #ifdef _LP64 | |
5448 // Load pointer from stack slot, 64-bit encoding | |
5449 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5450 match(Set dst src); | |
5451 ins_cost(MEMORY_REF_COST); | |
5452 size(4); | |
5453 format %{ "LDX $src,$dst\t!ptr" %} | |
5454 opcode(Assembler::ldx_op3); | |
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5455 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5456 ins_pipe(iload_mem); |
5457 %} | |
5458 | |
5459 // Store pointer to stack slot | |
5460 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5461 match(Set dst src); | |
5462 ins_cost(MEMORY_REF_COST); | |
5463 size(4); | |
5464 format %{ "STX $src,$dst\t!ptr" %} | |
5465 opcode(Assembler::stx_op3); | |
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5466 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5467 ins_pipe(istore_mem_reg); |
5468 %} | |
5469 #else // _LP64 | |
5470 // Load pointer from stack slot, 32-bit encoding | |
5471 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5472 match(Set dst src); | |
5473 ins_cost(MEMORY_REF_COST); | |
5474 format %{ "LDUW $src,$dst\t!ptr" %} | |
5475 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
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5476 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5477 ins_pipe(iload_mem); |
5478 %} | |
5479 | |
5480 // Store pointer to stack slot | |
5481 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5482 match(Set dst src); | |
5483 ins_cost(MEMORY_REF_COST); | |
5484 format %{ "STW $src,$dst\t!ptr" %} | |
5485 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
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5486 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5487 ins_pipe(istore_mem_reg); |
5488 %} | |
5489 #endif // _LP64 | |
5490 | |
5491 //------------Special Nop instructions for bundling - no match rules----------- | |
5492 // Nop using the A0 functional unit | |
5493 instruct Nop_A0() %{ | |
5494 ins_cost(0); | |
5495 | |
5496 format %{ "NOP ! Alu Pipeline" %} | |
5497 opcode(Assembler::or_op3, Assembler::arith_op); | |
5498 ins_encode( form2_nop() ); | |
5499 ins_pipe(ialu_nop_A0); | |
5500 %} | |
5501 | |
5502 // Nop using the A1 functional unit | |
5503 instruct Nop_A1( ) %{ | |
5504 ins_cost(0); | |
5505 | |
5506 format %{ "NOP ! Alu Pipeline" %} | |
5507 opcode(Assembler::or_op3, Assembler::arith_op); | |
5508 ins_encode( form2_nop() ); | |
5509 ins_pipe(ialu_nop_A1); | |
5510 %} | |
5511 | |
5512 // Nop using the memory functional unit | |
5513 instruct Nop_MS( ) %{ | |
5514 ins_cost(0); | |
5515 | |
5516 format %{ "NOP ! Memory Pipeline" %} | |
5517 ins_encode( emit_mem_nop ); | |
5518 ins_pipe(mem_nop); | |
5519 %} | |
5520 | |
5521 // Nop using the floating add functional unit | |
5522 instruct Nop_FA( ) %{ | |
5523 ins_cost(0); | |
5524 | |
5525 format %{ "NOP ! Floating Add Pipeline" %} | |
5526 ins_encode( emit_fadd_nop ); | |
5527 ins_pipe(fadd_nop); | |
5528 %} | |
5529 | |
5530 // Nop using the branch functional unit | |
5531 instruct Nop_BR( ) %{ | |
5532 ins_cost(0); | |
5533 | |
5534 format %{ "NOP ! Branch Pipeline" %} | |
5535 ins_encode( emit_br_nop ); | |
5536 ins_pipe(br_nop); | |
5537 %} | |
5538 | |
5539 //----------Load/Store/Move Instructions--------------------------------------- | |
5540 //----------Load Instructions-------------------------------------------------- | |
5541 // Load Byte (8bit signed) | |
5542 instruct loadB(iRegI dst, memory mem) %{ | |
5543 match(Set dst (LoadB mem)); | |
5544 ins_cost(MEMORY_REF_COST); | |
5545 | |
5546 size(4); | |
624 | 5547 format %{ "LDSB $mem,$dst\t! byte" %} |
727 | 5548 ins_encode %{ |
5549 __ ldsb($mem$$Address, $dst$$Register); | |
5550 %} | |
624 | 5551 ins_pipe(iload_mask_mem); |
5552 %} | |
5553 | |
5554 // Load Byte (8bit signed) into a Long Register | |
5555 instruct loadB2L(iRegL dst, memory mem) %{ | |
5556 match(Set dst (ConvI2L (LoadB mem))); | |
5557 ins_cost(MEMORY_REF_COST); | |
5558 | |
5559 size(4); | |
5560 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
727 | 5561 ins_encode %{ |
5562 __ ldsb($mem$$Address, $dst$$Register); | |
5563 %} | |
0 | 5564 ins_pipe(iload_mask_mem); |
5565 %} | |
5566 | |
624 | 5567 // Load Unsigned Byte (8bit UNsigned) into an int reg |
5568 instruct loadUB(iRegI dst, memory mem) %{ | |
5569 match(Set dst (LoadUB mem)); | |
0 | 5570 ins_cost(MEMORY_REF_COST); |
5571 | |
5572 size(4); | |
624 | 5573 format %{ "LDUB $mem,$dst\t! ubyte" %} |
727 | 5574 ins_encode %{ |
5575 __ ldub($mem$$Address, $dst$$Register); | |
5576 %} | |
824 | 5577 ins_pipe(iload_mem); |
624 | 5578 %} |
5579 | |
5580 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
5581 instruct loadUB2L(iRegL dst, memory mem) %{ | |
5582 match(Set dst (ConvI2L (LoadUB mem))); | |
5583 ins_cost(MEMORY_REF_COST); | |
5584 | |
5585 size(4); | |
5586 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
727 | 5587 ins_encode %{ |
5588 __ ldub($mem$$Address, $dst$$Register); | |
5589 %} | |
824 | 5590 ins_pipe(iload_mem); |
5591 %} | |
5592 | |
5593 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register | |
5594 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ | |
5595 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
5596 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5597 | |
5598 size(2*4); | |
5599 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" | |
5600 "AND $dst,$mask,$dst" %} | |
5601 ins_encode %{ | |
5602 __ ldub($mem$$Address, $dst$$Register); | |
5603 __ and3($dst$$Register, $mask$$constant, $dst$$Register); | |
5604 %} | |
5605 ins_pipe(iload_mem); | |
0 | 5606 %} |
5607 | |
624 | 5608 // Load Short (16bit signed) |
5609 instruct loadS(iRegI dst, memory mem) %{ | |
5610 match(Set dst (LoadS mem)); | |
5611 ins_cost(MEMORY_REF_COST); | |
5612 | |
5613 size(4); | |
5614 format %{ "LDSH $mem,$dst\t! short" %} | |
727 | 5615 ins_encode %{ |
5616 __ ldsh($mem$$Address, $dst$$Register); | |
5617 %} | |
624 | 5618 ins_pipe(iload_mask_mem); |
5619 %} | |
5620 | |
785 | 5621 // Load Short (16 bit signed) to Byte (8 bit signed) |
5622 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5623 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
5624 ins_cost(MEMORY_REF_COST); | |
5625 | |
5626 size(4); | |
5627 | |
5628 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} | |
5629 ins_encode %{ | |
5630 __ ldsb($mem$$Address, $dst$$Register, 1); | |
5631 %} | |
5632 ins_pipe(iload_mask_mem); | |
5633 %} | |
5634 | |
624 | 5635 // Load Short (16bit signed) into a Long Register |
5636 instruct loadS2L(iRegL dst, memory mem) %{ | |
5637 match(Set dst (ConvI2L (LoadS mem))); | |
0 | 5638 ins_cost(MEMORY_REF_COST); |
5639 | |
5640 size(4); | |
624 | 5641 format %{ "LDSH $mem,$dst\t! short -> long" %} |
727 | 5642 ins_encode %{ |
5643 __ ldsh($mem$$Address, $dst$$Register); | |
5644 %} | |
624 | 5645 ins_pipe(iload_mask_mem); |
5646 %} | |
5647 | |
5648 // Load Unsigned Short/Char (16bit UNsigned) | |
5649 instruct loadUS(iRegI dst, memory mem) %{ | |
5650 match(Set dst (LoadUS mem)); | |
5651 ins_cost(MEMORY_REF_COST); | |
5652 | |
5653 size(4); | |
5654 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
727 | 5655 ins_encode %{ |
5656 __ lduh($mem$$Address, $dst$$Register); | |
5657 %} | |
824 | 5658 ins_pipe(iload_mem); |
0 | 5659 %} |
5660 | |
785 | 5661 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
5662 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5663 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
5664 ins_cost(MEMORY_REF_COST); | |
5665 | |
5666 size(4); | |
5667 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} | |
5668 ins_encode %{ | |
5669 __ ldsb($mem$$Address, $dst$$Register, 1); | |
5670 %} | |
5671 ins_pipe(iload_mask_mem); | |
5672 %} | |
5673 | |
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5674 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
624 | 5675 instruct loadUS2L(iRegL dst, memory mem) %{ |
5676 match(Set dst (ConvI2L (LoadUS mem))); | |
0 | 5677 ins_cost(MEMORY_REF_COST); |
5678 | |
5679 size(4); | |
624 | 5680 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
727 | 5681 ins_encode %{ |
5682 __ lduh($mem$$Address, $dst$$Register); | |
5683 %} | |
824 | 5684 ins_pipe(iload_mem); |
5685 %} | |
5686 | |
5687 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register | |
5688 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
5689 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5690 ins_cost(MEMORY_REF_COST); | |
5691 | |
5692 size(4); | |
5693 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} | |
5694 ins_encode %{ | |
5695 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE | |
5696 %} | |
5697 ins_pipe(iload_mem); | |
5698 %} | |
5699 | |
5700 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register | |
5701 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
5702 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5703 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5704 | |
5705 size(2*4); | |
5706 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" | |
5707 "AND $dst,$mask,$dst" %} | |
5708 ins_encode %{ | |
5709 Register Rdst = $dst$$Register; | |
5710 __ lduh($mem$$Address, Rdst); | |
5711 __ and3(Rdst, $mask$$constant, Rdst); | |
5712 %} | |
5713 ins_pipe(iload_mem); | |
5714 %} | |
5715 | |
5716 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register | |
5717 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | |
5718 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5719 effect(TEMP dst, TEMP tmp); | |
5720 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
5721 | |
14909 | 5722 size((3+1)*4); // set may use two instructions. |
824 | 5723 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
5724 "SET $mask,$tmp\n\t" | |
5725 "AND $dst,$tmp,$dst" %} | |
5726 ins_encode %{ | |
5727 Register Rdst = $dst$$Register; | |
5728 Register Rtmp = $tmp$$Register; | |
5729 __ lduh($mem$$Address, Rdst); | |
5730 __ set($mask$$constant, Rtmp); | |
5731 __ and3(Rdst, Rtmp, Rdst); | |
5732 %} | |
5733 ins_pipe(iload_mem); | |
0 | 5734 %} |
5735 | |
5736 // Load Integer | |
5737 instruct loadI(iRegI dst, memory mem) %{ | |
5738 match(Set dst (LoadI mem)); | |
5739 ins_cost(MEMORY_REF_COST); | |
624 | 5740 |
5741 size(4); | |
5742 format %{ "LDUW $mem,$dst\t! int" %} | |
727 | 5743 ins_encode %{ |
5744 __ lduw($mem$$Address, $dst$$Register); | |
5745 %} | |
624 | 5746 ins_pipe(iload_mem); |
5747 %} | |
5748 | |
785 | 5749 // Load Integer to Byte (8 bit signed) |
5750 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5751 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
5752 ins_cost(MEMORY_REF_COST); | |
5753 | |
5754 size(4); | |
5755 | |
5756 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} | |
5757 ins_encode %{ | |
5758 __ ldsb($mem$$Address, $dst$$Register, 3); | |
5759 %} | |
5760 ins_pipe(iload_mask_mem); | |
5761 %} | |
5762 | |
5763 // Load Integer to Unsigned Byte (8 bit UNsigned) | |
5764 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ | |
5765 match(Set dst (AndI (LoadI mem) mask)); | |
5766 ins_cost(MEMORY_REF_COST); | |
5767 | |
5768 size(4); | |
5769 | |
5770 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} | |
5771 ins_encode %{ | |
5772 __ ldub($mem$$Address, $dst$$Register, 3); | |
5773 %} | |
5774 ins_pipe(iload_mask_mem); | |
5775 %} | |
5776 | |
5777 // Load Integer to Short (16 bit signed) | |
5778 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ | |
5779 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
5780 ins_cost(MEMORY_REF_COST); | |
5781 | |
5782 size(4); | |
5783 | |
5784 format %{ "LDSH $mem+2,$dst\t! int -> short" %} | |
5785 ins_encode %{ | |
5786 __ ldsh($mem$$Address, $dst$$Register, 2); | |
5787 %} | |
5788 ins_pipe(iload_mask_mem); | |
5789 %} | |
5790 | |
5791 // Load Integer to Unsigned Short (16 bit UNsigned) | |
5792 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ | |
5793 match(Set dst (AndI (LoadI mem) mask)); | |
5794 ins_cost(MEMORY_REF_COST); | |
5795 | |
5796 size(4); | |
5797 | |
5798 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} | |
5799 ins_encode %{ | |
5800 __ lduh($mem$$Address, $dst$$Register, 2); | |
5801 %} | |
5802 ins_pipe(iload_mask_mem); | |
5803 %} | |
5804 | |
624 | 5805 // Load Integer into a Long Register |
5806 instruct loadI2L(iRegL dst, memory mem) %{ | |
5807 match(Set dst (ConvI2L (LoadI mem))); | |
5808 ins_cost(MEMORY_REF_COST); | |
5809 | |
5810 size(4); | |
5811 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
727 | 5812 ins_encode %{ |
5813 __ ldsw($mem$$Address, $dst$$Register); | |
5814 %} | |
824 | 5815 ins_pipe(iload_mask_mem); |
5816 %} | |
5817 | |
5818 // Load Integer with mask 0xFF into a Long Register | |
5819 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
5820 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5821 ins_cost(MEMORY_REF_COST); | |
5822 | |
5823 size(4); | |
5824 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} | |
5825 ins_encode %{ | |
5826 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE | |
5827 %} | |
5828 ins_pipe(iload_mem); | |
5829 %} | |
5830 | |
5831 // Load Integer with mask 0xFFFF into a Long Register | |
5832 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ | |
5833 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5834 ins_cost(MEMORY_REF_COST); | |
5835 | |
5836 size(4); | |
5837 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} | |
5838 ins_encode %{ | |
5839 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | |
5840 %} | |
5841 ins_pipe(iload_mem); | |
5842 %} | |
5843 | |
14909 | 5844 // Load Integer with a 13-bit mask into a Long Register |
5845 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
824 | 5846 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
5847 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5848 | |
5849 size(2*4); | |
14909 | 5850 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" |
824 | 5851 "AND $dst,$mask,$dst" %} |
5852 ins_encode %{ | |
5853 Register Rdst = $dst$$Register; | |
5854 __ lduw($mem$$Address, Rdst); | |
5855 __ and3(Rdst, $mask$$constant, Rdst); | |
5856 %} | |
5857 ins_pipe(iload_mem); | |
5858 %} | |
5859 | |
14909 | 5860 // Load Integer with a 32-bit mask into a Long Register |
5861 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ | |
824 | 5862 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
5863 effect(TEMP dst, TEMP tmp); | |
5864 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
5865 | |
14909 | 5866 size((3+1)*4); // set may use two instructions. |
5867 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" | |
824 | 5868 "SET $mask,$tmp\n\t" |
5869 "AND $dst,$tmp,$dst" %} | |
5870 ins_encode %{ | |
5871 Register Rdst = $dst$$Register; | |
5872 Register Rtmp = $tmp$$Register; | |
5873 __ lduw($mem$$Address, Rdst); | |
5874 __ set($mask$$constant, Rtmp); | |
5875 __ and3(Rdst, Rtmp, Rdst); | |
5876 %} | |
624 | 5877 ins_pipe(iload_mem); |
5878 %} | |
5879 | |
5880 // Load Unsigned Integer into a Long Register | |
6849 | 5881 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{ |
5882 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
624 | 5883 ins_cost(MEMORY_REF_COST); |
5884 | |
5885 size(4); | |
5886 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
727 | 5887 ins_encode %{ |
5888 __ lduw($mem$$Address, $dst$$Register); | |
5889 %} | |
0 | 5890 ins_pipe(iload_mem); |
5891 %} | |
5892 | |
5893 // Load Long - aligned | |
5894 instruct loadL(iRegL dst, memory mem ) %{ | |
5895 match(Set dst (LoadL mem)); | |
5896 ins_cost(MEMORY_REF_COST); | |
624 | 5897 |
0 | 5898 size(4); |
5899 format %{ "LDX $mem,$dst\t! long" %} | |
727 | 5900 ins_encode %{ |
5901 __ ldx($mem$$Address, $dst$$Register); | |
5902 %} | |
0 | 5903 ins_pipe(iload_mem); |
5904 %} | |
5905 | |
5906 // Load Long - UNaligned | |
5907 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
5908 match(Set dst (LoadL_unaligned mem)); | |
5909 effect(KILL tmp); | |
5910 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
5911 size(16); | |
5912 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
5913 "\tLDUW $mem ,$dst\n" | |
5914 "\tSLLX #32, $dst, $dst\n" | |
5915 "\tOR $dst, R_O7, $dst" %} | |
5916 opcode(Assembler::lduw_op3); | |
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5917 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
0 | 5918 ins_pipe(iload_mem); |
5919 %} | |
5920 | |
5921 // Load Range | |
5922 instruct loadRange(iRegI dst, memory mem) %{ | |
5923 match(Set dst (LoadRange mem)); | |
5924 ins_cost(MEMORY_REF_COST); | |
5925 | |
5926 size(4); | |
5927 format %{ "LDUW $mem,$dst\t! range" %} | |
5928 opcode(Assembler::lduw_op3); | |
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5929 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5930 ins_pipe(iload_mem); |
5931 %} | |
5932 | |
5933 // Load Integer into %f register (for fitos/fitod) | |
5934 instruct loadI_freg(regF dst, memory mem) %{ | |
5935 match(Set dst (LoadI mem)); | |
5936 ins_cost(MEMORY_REF_COST); | |
5937 size(4); | |
5938 | |
5939 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
5940 opcode(Assembler::ldf_op3); | |
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5941 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5942 ins_pipe(floadF_mem); |
5943 %} | |
5944 | |
5945 // Load Pointer | |
5946 instruct loadP(iRegP dst, memory mem) %{ | |
5947 match(Set dst (LoadP mem)); | |
5948 ins_cost(MEMORY_REF_COST); | |
5949 size(4); | |
5950 | |
5951 #ifndef _LP64 | |
5952 format %{ "LDUW $mem,$dst\t! ptr" %} | |
727 | 5953 ins_encode %{ |
5954 __ lduw($mem$$Address, $dst$$Register); | |
5955 %} | |
0 | 5956 #else |
5957 format %{ "LDX $mem,$dst\t! ptr" %} | |
727 | 5958 ins_encode %{ |
5959 __ ldx($mem$$Address, $dst$$Register); | |
5960 %} | |
0 | 5961 #endif |
5962 ins_pipe(iload_mem); | |
5963 %} | |
5964 | |
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5965 // Load Compressed Pointer |
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5966 instruct loadN(iRegN dst, memory mem) %{ |
727 | 5967 match(Set dst (LoadN mem)); |
5968 ins_cost(MEMORY_REF_COST); | |
5969 size(4); | |
5970 | |
5971 format %{ "LDUW $mem,$dst\t! compressed ptr" %} | |
5972 ins_encode %{ | |
5973 __ lduw($mem$$Address, $dst$$Register); | |
5974 %} | |
5975 ins_pipe(iload_mem); | |
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5976 %} |
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5977 |
0 | 5978 // Load Klass Pointer |
5979 instruct loadKlass(iRegP dst, memory mem) %{ | |
5980 match(Set dst (LoadKlass mem)); | |
5981 ins_cost(MEMORY_REF_COST); | |
5982 size(4); | |
5983 | |
5984 #ifndef _LP64 | |
5985 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
727 | 5986 ins_encode %{ |
5987 __ lduw($mem$$Address, $dst$$Register); | |
5988 %} | |
0 | 5989 #else |
5990 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
727 | 5991 ins_encode %{ |
5992 __ ldx($mem$$Address, $dst$$Register); | |
5993 %} | |
0 | 5994 #endif |
5995 ins_pipe(iload_mem); | |
5996 %} | |
5997 | |
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5998 // Load narrow Klass Pointer |
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5999 instruct loadNKlass(iRegN dst, memory mem) %{ |
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6000 match(Set dst (LoadNKlass mem)); |
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6001 ins_cost(MEMORY_REF_COST); |
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6002 size(4); |
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6003 |
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6004 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
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6005 ins_encode %{ |
727 | 6006 __ lduw($mem$$Address, $dst$$Register); |
113
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6007 %} |
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6008 ins_pipe(iload_mem); |
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6009 %} |
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6010 |
0 | 6011 // Load Double |
6012 instruct loadD(regD dst, memory mem) %{ | |
6013 match(Set dst (LoadD mem)); | |
6014 ins_cost(MEMORY_REF_COST); | |
6015 | |
6016 size(4); | |
6017 format %{ "LDDF $mem,$dst" %} | |
6018 opcode(Assembler::lddf_op3); | |
415
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6019 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 6020 ins_pipe(floadD_mem); |
6021 %} | |
6022 | |
6023 // Load Double - UNaligned | |
6024 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
6025 match(Set dst (LoadD_unaligned mem)); | |
6026 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
6027 size(8); | |
6028 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
6029 "\tLDF $mem+4,$dst.lo\t!" %} | |
6030 opcode(Assembler::ldf_op3); | |
6031 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
6032 ins_pipe(iload_mem); | |
6033 %} | |
6034 | |
6035 // Load Float | |
6036 instruct loadF(regF dst, memory mem) %{ | |
6037 match(Set dst (LoadF mem)); | |
6038 ins_cost(MEMORY_REF_COST); | |
6039 | |
6040 size(4); | |
6041 format %{ "LDF $mem,$dst" %} | |
6042 opcode(Assembler::ldf_op3); | |
415
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6043 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 6044 ins_pipe(floadF_mem); |
6045 %} | |
6046 | |
6047 // Load Constant | |
6048 instruct loadConI( iRegI dst, immI src ) %{ | |
6049 match(Set dst src); | |
6050 ins_cost(DEFAULT_COST * 3/2); | |
6051 format %{ "SET $src,$dst" %} | |
6052 ins_encode( Set32(src, dst) ); | |
6053 ins_pipe(ialu_hi_lo_reg); | |
6054 %} | |
6055 | |
6056 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
6057 match(Set dst src); | |
6058 | |
6059 size(4); | |
6060 format %{ "MOV $src,$dst" %} | |
6061 ins_encode( Set13( src, dst ) ); | |
6062 ins_pipe(ialu_imm); | |
6063 %} | |
6064 | |
2008 | 6065 #ifndef _LP64 |
6066 instruct loadConP(iRegP dst, immP con) %{ | |
6067 match(Set dst con); | |
6068 ins_cost(DEFAULT_COST * 3/2); | |
6069 format %{ "SET $con,$dst\t!ptr" %} | |
6070 ins_encode %{ | |
6725
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|
6071 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); |
2008 | 6072 intptr_t val = $con$$constant; |
6725
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|
6073 if (constant_reloc == relocInfo::oop_type) { |
2008 | 6074 __ set_oop_constant((jobject) val, $dst$$Register); |
6725
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|
6075 } else if (constant_reloc == relocInfo::metadata_type) { |
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|
6076 __ set_metadata_constant((Metadata*)val, $dst$$Register); |
2008 | 6077 } else { // non-oop pointers, e.g. card mark base, heap top |
6725
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6179
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|
6078 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); |
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|
6079 __ set(val, $dst$$Register); |
2008 | 6080 } |
6081 %} | |
6082 ins_pipe(loadConP); | |
6083 %} | |
6084 #else | |
6085 instruct loadConP_set(iRegP dst, immP_set con) %{ | |
6086 match(Set dst con); | |
0 | 6087 ins_cost(DEFAULT_COST * 3/2); |
2008 | 6088 format %{ "SET $con,$dst\t! ptr" %} |
6089 ins_encode %{ | |
6725
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|
6090 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); |
2008 | 6091 intptr_t val = $con$$constant; |
6725
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|
6092 if (constant_reloc == relocInfo::oop_type) { |
2008 | 6093 __ set_oop_constant((jobject) val, $dst$$Register); |
6725
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|
6094 } else if (constant_reloc == relocInfo::metadata_type) { |
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|
6095 __ set_metadata_constant((Metadata*)val, $dst$$Register); |
2008 | 6096 } else { // non-oop pointers, e.g. card mark base, heap top |
6725
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|
6097 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); |
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|
6098 __ set(val, $dst$$Register); |
2008 | 6099 } |
6100 %} | |
0 | 6101 ins_pipe(loadConP); |
2008 | 6102 %} |
6103 | |
6104 instruct loadConP_load(iRegP dst, immP_load con) %{ | |
6105 match(Set dst con); | |
6106 ins_cost(MEMORY_REF_COST); | |
6107 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} | |
6108 ins_encode %{ | |
2076
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|
6109 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
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|
6110 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); |
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|
6111 %} |
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|
6112 ins_pipe(loadConP); |
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|
6113 %} |
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|
6114 |
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|
6115 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ |
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|
6116 match(Set dst con); |
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|
6117 ins_cost(DEFAULT_COST * 3/2); |
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|
6118 format %{ "SET $con,$dst\t! non-oop ptr" %} |
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|
6119 ins_encode %{ |
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|
6120 __ set($con$$constant, $dst$$Register); |
2008 | 6121 %} |
6122 ins_pipe(loadConP); | |
6123 %} | |
6124 #endif // _LP64 | |
0 | 6125 |
6126 instruct loadConP0(iRegP dst, immP0 src) %{ | |
6127 match(Set dst src); | |
6128 | |
6129 size(4); | |
6130 format %{ "CLR $dst\t!ptr" %} | |
2008 | 6131 ins_encode %{ |
6132 __ clr($dst$$Register); | |
6133 %} | |
0 | 6134 ins_pipe(ialu_imm); |
6135 %} | |
6136 | |
6137 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
6138 match(Set dst src); | |
6139 ins_cost(DEFAULT_COST); | |
6140 format %{ "SET $src,$dst\t!ptr" %} | |
6141 ins_encode %{ | |
727 | 6142 AddressLiteral polling_page(os::get_polling_page()); |
6143 __ sethi(polling_page, reg_to_register_object($dst$$reg)); | |
0 | 6144 %} |
6145 ins_pipe(loadConP_poll); | |
6146 %} | |
6147 | |
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6148 instruct loadConN0(iRegN dst, immN0 src) %{ |
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6149 match(Set dst src); |
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|
6150 |
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|
6151 size(4); |
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|
6152 format %{ "CLR $dst\t! compressed NULL ptr" %} |
2008 | 6153 ins_encode %{ |
6154 __ clr($dst$$Register); | |
6155 %} | |
164
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|
6156 ins_pipe(ialu_imm); |
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|
6157 %} |
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|
6158 |
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|
6159 instruct loadConN(iRegN dst, immN src) %{ |
ba764ed4b6f2
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|
6160 match(Set dst src); |
164
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|
6161 ins_cost(DEFAULT_COST * 3/2); |
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|
6162 format %{ "SET $src,$dst\t! compressed ptr" %} |
113
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|
6163 ins_encode %{ |
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|
6164 Register dst = $dst$$Register; |
164
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|
6165 __ set_narrow_oop((jobject)$src$$constant, dst); |
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|
6166 %} |
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|
6167 ins_pipe(ialu_hi_lo_reg); |
113
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|
6168 %} |
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|
6169 |
6848
8e47bac5643a
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6823
diff
changeset
|
6170 instruct loadConNKlass(iRegN dst, immNKlass src) %{ |
8e47bac5643a
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roland
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6823
diff
changeset
|
6171 match(Set dst src); |
8e47bac5643a
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6823
diff
changeset
|
6172 ins_cost(DEFAULT_COST * 3/2); |
8e47bac5643a
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6823
diff
changeset
|
6173 format %{ "SET $src,$dst\t! compressed klass ptr" %} |
8e47bac5643a
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roland
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6823
diff
changeset
|
6174 ins_encode %{ |
8e47bac5643a
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6823
diff
changeset
|
6175 Register dst = $dst$$Register; |
8e47bac5643a
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6823
diff
changeset
|
6176 __ set_narrow_klass((Klass*)$src$$constant, dst); |
8e47bac5643a
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roland
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6823
diff
changeset
|
6177 %} |
8e47bac5643a
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6823
diff
changeset
|
6178 ins_pipe(ialu_hi_lo_reg); |
8e47bac5643a
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6823
diff
changeset
|
6179 %} |
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|
6180 |
2008 | 6181 // Materialize long value (predicated by immL_cheap). |
6182 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ | |
6183 match(Set dst con); | |
0 | 6184 effect(KILL tmp); |
2008 | 6185 ins_cost(DEFAULT_COST * 3); |
6186 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} | |
6187 ins_encode %{ | |
6188 __ set64($con$$constant, $dst$$Register, $tmp$$Register); | |
6189 %} | |
6190 ins_pipe(loadConL); | |
6191 %} | |
6192 | |
6193 // Load long value from constant table (predicated by immL_expensive). | |
6194 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ | |
6195 match(Set dst con); | |
6196 ins_cost(MEMORY_REF_COST); | |
6197 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} | |
6198 ins_encode %{ | |
2012
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|
6199 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
5fe0781a8560
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diff
changeset
|
6200 __ ldx($constanttablebase, con_offset, $dst$$Register); |
2008 | 6201 %} |
0 | 6202 ins_pipe(loadConL); |
6203 %} | |
6204 | |
6205 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
6206 match(Set dst src); | |
6207 ins_cost(DEFAULT_COST); | |
6208 size(4); | |
6209 format %{ "CLR $dst\t! long" %} | |
6210 ins_encode( Set13( src, dst ) ); | |
6211 ins_pipe(ialu_imm); | |
6212 %} | |
6213 | |
6214 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
6215 match(Set dst src); | |
6216 ins_cost(DEFAULT_COST * 2); | |
6217 | |
6218 size(4); | |
6219 format %{ "MOV $src,$dst\t! long" %} | |
6220 ins_encode( Set13( src, dst ) ); | |
6221 ins_pipe(ialu_imm); | |
6222 %} | |
6223 | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
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diff
changeset
|
6224 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ |
2008 | 6225 match(Set dst con); |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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2008
diff
changeset
|
6226 effect(KILL tmp); |
2008 | 6227 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} |
727 | 6228 ins_encode %{ |
2012
5fe0781a8560
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kvn
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diff
changeset
|
6229 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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2008
diff
changeset
|
6230 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); |
727 | 6231 %} |
0 | 6232 ins_pipe(loadConFD); |
6233 %} | |
6234 | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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2008
diff
changeset
|
6235 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ |
2008 | 6236 match(Set dst con); |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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2008
diff
changeset
|
6237 effect(KILL tmp); |
2008 | 6238 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} |
727 | 6239 ins_encode %{ |
732
fb4c18a2ec66
6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents:
727
diff
changeset
|
6240 // XXX This is a quick fix for 6833573. |
2008 | 6241 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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2008
diff
changeset
|
6242 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
5fe0781a8560
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diff
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|
6243 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
727 | 6244 %} |
0 | 6245 ins_pipe(loadConFD); |
6246 %} | |
6247 | |
6248 // Prefetch instructions. | |
6249 // Must be safe to execute with invalid address (cannot fault). | |
6250 | |
6251 instruct prefetchr( memory mem ) %{ | |
6252 match( PrefetchRead mem ); | |
6253 ins_cost(MEMORY_REF_COST); | |
3854 | 6254 size(4); |
0 | 6255 |
6256 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
6257 opcode(Assembler::prefetch_op3); | |
6258 ins_encode( form3_mem_prefetch_read( mem ) ); | |
6259 ins_pipe(iload_mem); | |
6260 %} | |
6261 | |
6262 instruct prefetchw( memory mem ) %{ | |
6263 match( PrefetchWrite mem ); | |
6264 ins_cost(MEMORY_REF_COST); | |
3854 | 6265 size(4); |
0 | 6266 |
6267 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
6268 opcode(Assembler::prefetch_op3); | |
6269 ins_encode( form3_mem_prefetch_write( mem ) ); | |
6270 ins_pipe(iload_mem); | |
6271 %} | |
6272 | |
3854 | 6273 // Prefetch instructions for allocation. |
6274 | |
6275 instruct prefetchAlloc( memory mem ) %{ | |
6276 predicate(AllocatePrefetchInstr == 0); | |
6277 match( PrefetchAllocation mem ); | |
6278 ins_cost(MEMORY_REF_COST); | |
6279 size(4); | |
6280 | |
6281 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %} | |
6282 opcode(Assembler::prefetch_op3); | |
6283 ins_encode( form3_mem_prefetch_write( mem ) ); | |
6284 ins_pipe(iload_mem); | |
6285 %} | |
6286 | |
6287 // Use BIS instruction to prefetch for allocation. | |
6288 // Could fault, need space at the end of TLAB. | |
6289 instruct prefetchAlloc_bis( iRegP dst ) %{ | |
6290 predicate(AllocatePrefetchInstr == 1); | |
6291 match( PrefetchAllocation dst ); | |
6292 ins_cost(MEMORY_REF_COST); | |
6293 size(4); | |
6294 | |
6295 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %} | |
6296 ins_encode %{ | |
6297 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); | |
1367
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1274
diff
changeset
|
6298 %} |
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changeset
|
6299 ins_pipe(istore_mem_reg); |
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|
6300 %} |
0 | 6301 |
3854 | 6302 // Next code is used for finding next cache line address to prefetch. |
6303 #ifndef _LP64 | |
6304 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{ | |
6305 match(Set dst (CastX2P (AndI (CastP2X src) mask))); | |
6306 ins_cost(DEFAULT_COST); | |
6307 size(4); | |
6308 | |
6309 format %{ "AND $src,$mask,$dst\t! next cache line address" %} | |
6310 ins_encode %{ | |
6311 __ and3($src$$Register, $mask$$constant, $dst$$Register); | |
6312 %} | |
6313 ins_pipe(ialu_reg_imm); | |
6314 %} | |
6315 #else | |
6316 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{ | |
6317 match(Set dst (CastX2P (AndL (CastP2X src) mask))); | |
6318 ins_cost(DEFAULT_COST); | |
6319 size(4); | |
6320 | |
6321 format %{ "AND $src,$mask,$dst\t! next cache line address" %} | |
6322 ins_encode %{ | |
6323 __ and3($src$$Register, $mask$$constant, $dst$$Register); | |
6324 %} | |
6325 ins_pipe(ialu_reg_imm); | |
6326 %} | |
6327 #endif | |
6328 | |
0 | 6329 //----------Store Instructions------------------------------------------------- |
6330 // Store Byte | |
6331 instruct storeB(memory mem, iRegI src) %{ | |
6332 match(Set mem (StoreB mem src)); | |
6333 ins_cost(MEMORY_REF_COST); | |
6334 | |
6335 size(4); | |
6336 format %{ "STB $src,$mem\t! byte" %} | |
6337 opcode(Assembler::stb_op3); | |
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|
6338 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6339 ins_pipe(istore_mem_reg); |
6340 %} | |
6341 | |
6342 instruct storeB0(memory mem, immI0 src) %{ | |
6343 match(Set mem (StoreB mem src)); | |
6344 ins_cost(MEMORY_REF_COST); | |
6345 | |
6346 size(4); | |
6347 format %{ "STB $src,$mem\t! byte" %} | |
6348 opcode(Assembler::stb_op3); | |
415
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|
6349 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6350 ins_pipe(istore_mem_zero); |
6351 %} | |
6352 | |
6353 instruct storeCM0(memory mem, immI0 src) %{ | |
6354 match(Set mem (StoreCM mem src)); | |
6355 ins_cost(MEMORY_REF_COST); | |
6356 | |
6357 size(4); | |
6358 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
6359 opcode(Assembler::stb_op3); | |
415
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|
6360 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6361 ins_pipe(istore_mem_zero); |
6362 %} | |
6363 | |
6364 // Store Char/Short | |
6365 instruct storeC(memory mem, iRegI src) %{ | |
6366 match(Set mem (StoreC mem src)); | |
6367 ins_cost(MEMORY_REF_COST); | |
6368 | |
6369 size(4); | |
6370 format %{ "STH $src,$mem\t! short" %} | |
6371 opcode(Assembler::sth_op3); | |
415
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|
6372 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6373 ins_pipe(istore_mem_reg); |
6374 %} | |
6375 | |
6376 instruct storeC0(memory mem, immI0 src) %{ | |
6377 match(Set mem (StoreC mem src)); | |
6378 ins_cost(MEMORY_REF_COST); | |
6379 | |
6380 size(4); | |
6381 format %{ "STH $src,$mem\t! short" %} | |
6382 opcode(Assembler::sth_op3); | |
415
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|
6383 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6384 ins_pipe(istore_mem_zero); |
6385 %} | |
6386 | |
6387 // Store Integer | |
6388 instruct storeI(memory mem, iRegI src) %{ | |
6389 match(Set mem (StoreI mem src)); | |
6390 ins_cost(MEMORY_REF_COST); | |
6391 | |
6392 size(4); | |
6393 format %{ "STW $src,$mem" %} | |
6394 opcode(Assembler::stw_op3); | |
415
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6395 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6396 ins_pipe(istore_mem_reg); |
6397 %} | |
6398 | |
6399 // Store Long | |
6400 instruct storeL(memory mem, iRegL src) %{ | |
6401 match(Set mem (StoreL mem src)); | |
6402 ins_cost(MEMORY_REF_COST); | |
6403 size(4); | |
6404 format %{ "STX $src,$mem\t! long" %} | |
6405 opcode(Assembler::stx_op3); | |
415
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parents:
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|
6406 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6407 ins_pipe(istore_mem_reg); |
6408 %} | |
6409 | |
6410 instruct storeI0(memory mem, immI0 src) %{ | |
6411 match(Set mem (StoreI mem src)); | |
6412 ins_cost(MEMORY_REF_COST); | |
6413 | |
6414 size(4); | |
6415 format %{ "STW $src,$mem" %} | |
6416 opcode(Assembler::stw_op3); | |
415
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|
6417 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6418 ins_pipe(istore_mem_zero); |
6419 %} | |
6420 | |
6421 instruct storeL0(memory mem, immL0 src) %{ | |
6422 match(Set mem (StoreL mem src)); | |
6423 ins_cost(MEMORY_REF_COST); | |
6424 | |
6425 size(4); | |
6426 format %{ "STX $src,$mem" %} | |
6427 opcode(Assembler::stx_op3); | |
415
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6428 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6429 ins_pipe(istore_mem_zero); |
6430 %} | |
6431 | |
6432 // Store Integer from float register (used after fstoi) | |
6433 instruct storeI_Freg(memory mem, regF src) %{ | |
6434 match(Set mem (StoreI mem src)); | |
6435 ins_cost(MEMORY_REF_COST); | |
6436 | |
6437 size(4); | |
6438 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
6439 opcode(Assembler::stf_op3); | |
415
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6440 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6441 ins_pipe(fstoreF_mem_reg); |
6442 %} | |
6443 | |
6444 // Store Pointer | |
6445 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
6446 match(Set dst (StoreP dst src)); | |
6447 ins_cost(MEMORY_REF_COST); | |
6448 size(4); | |
6449 | |
6450 #ifndef _LP64 | |
6451 format %{ "STW $src,$dst\t! ptr" %} | |
6452 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6453 #else | |
6454 format %{ "STX $src,$dst\t! ptr" %} | |
6455 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6456 #endif | |
6457 ins_encode( form3_mem_reg( dst, src ) ); | |
6458 ins_pipe(istore_mem_spORreg); | |
6459 %} | |
6460 | |
6461 instruct storeP0(memory dst, immP0 src) %{ | |
6462 match(Set dst (StoreP dst src)); | |
6463 ins_cost(MEMORY_REF_COST); | |
6464 size(4); | |
6465 | |
6466 #ifndef _LP64 | |
6467 format %{ "STW $src,$dst\t! ptr" %} | |
6468 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6469 #else | |
6470 format %{ "STX $src,$dst\t! ptr" %} | |
6471 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6472 #endif | |
6473 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
6474 ins_pipe(istore_mem_zero); | |
6475 %} | |
6476 | |
113
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6477 // Store Compressed Pointer |
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6478 instruct storeN(memory dst, iRegN src) %{ |
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6479 match(Set dst (StoreN dst src)); |
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6480 ins_cost(MEMORY_REF_COST); |
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|
6481 size(4); |
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|
6482 |
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|
6483 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6484 ins_encode %{ |
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|
6485 Register base = as_Register($dst$$base); |
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6486 Register index = as_Register($dst$$index); |
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|
6487 Register src = $src$$Register; |
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|
6488 if (index != G0) { |
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|
6489 __ stw(src, base, index); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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6490 } else { |
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|
6491 __ stw(src, base, $dst$$disp); |
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|
6492 } |
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|
6493 %} |
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|
6494 ins_pipe(istore_mem_spORreg); |
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|
6495 %} |
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|
6496 |
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
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6823
diff
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|
6497 instruct storeNKlass(memory dst, iRegN src) %{ |
8e47bac5643a
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roland
parents:
6823
diff
changeset
|
6498 match(Set dst (StoreNKlass dst src)); |
8e47bac5643a
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parents:
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diff
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|
6499 ins_cost(MEMORY_REF_COST); |
8e47bac5643a
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diff
changeset
|
6500 size(4); |
8e47bac5643a
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diff
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|
6501 |
8e47bac5643a
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|
6502 format %{ "STW $src,$dst\t! compressed klass ptr" %} |
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diff
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|
6503 ins_encode %{ |
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diff
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|
6504 Register base = as_Register($dst$$base); |
8e47bac5643a
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diff
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|
6505 Register index = as_Register($dst$$index); |
8e47bac5643a
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diff
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|
6506 Register src = $src$$Register; |
8e47bac5643a
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diff
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|
6507 if (index != G0) { |
8e47bac5643a
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diff
changeset
|
6508 __ stw(src, base, index); |
8e47bac5643a
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diff
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|
6509 } else { |
8e47bac5643a
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diff
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|
6510 __ stw(src, base, $dst$$disp); |
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diff
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|
6511 } |
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diff
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|
6512 %} |
8e47bac5643a
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diff
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|
6513 ins_pipe(istore_mem_spORreg); |
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diff
changeset
|
6514 %} |
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|
6515 |
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6516 instruct storeN0(memory dst, immN0 src) %{ |
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6517 match(Set dst (StoreN dst src)); |
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6518 ins_cost(MEMORY_REF_COST); |
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6519 size(4); |
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6520 |
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|
6521 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6522 ins_encode %{ |
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6523 Register base = as_Register($dst$$base); |
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6524 Register index = as_Register($dst$$index); |
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6525 if (index != G0) { |
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6526 __ stw(0, base, index); |
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6527 } else { |
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6528 __ stw(0, base, $dst$$disp); |
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|
6529 } |
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|
6530 %} |
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|
6531 ins_pipe(istore_mem_zero); |
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|
6532 %} |
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|
6533 |
0 | 6534 // Store Double |
6535 instruct storeD( memory mem, regD src) %{ | |
6536 match(Set mem (StoreD mem src)); | |
6537 ins_cost(MEMORY_REF_COST); | |
6538 | |
6539 size(4); | |
6540 format %{ "STDF $src,$mem" %} | |
6541 opcode(Assembler::stdf_op3); | |
415
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|
6542 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6543 ins_pipe(fstoreD_mem_reg); |
6544 %} | |
6545 | |
6546 instruct storeD0( memory mem, immD0 src) %{ | |
6547 match(Set mem (StoreD mem src)); | |
6548 ins_cost(MEMORY_REF_COST); | |
6549 | |
6550 size(4); | |
6551 format %{ "STX $src,$mem" %} | |
6552 opcode(Assembler::stx_op3); | |
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|
6553 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6554 ins_pipe(fstoreD_mem_zero); |
6555 %} | |
6556 | |
6557 // Store Float | |
6558 instruct storeF( memory mem, regF src) %{ | |
6559 match(Set mem (StoreF mem src)); | |
6560 ins_cost(MEMORY_REF_COST); | |
6561 | |
6562 size(4); | |
6563 format %{ "STF $src,$mem" %} | |
6564 opcode(Assembler::stf_op3); | |
415
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|
6565 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6566 ins_pipe(fstoreF_mem_reg); |
6567 %} | |
6568 | |
6569 instruct storeF0( memory mem, immF0 src) %{ | |
6570 match(Set mem (StoreF mem src)); | |
6571 ins_cost(MEMORY_REF_COST); | |
6572 | |
6573 size(4); | |
6574 format %{ "STW $src,$mem\t! storeF0" %} | |
6575 opcode(Assembler::stw_op3); | |
415
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|
6576 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6577 ins_pipe(fstoreF_mem_zero); |
6578 %} | |
6579 | |
113
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diff
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|
6580 // Convert oop pointer into compressed form |
ba764ed4b6f2
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|
6581 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
221
1e026f8da827
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|
6582 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
113
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|
6583 match(Set dst (EncodeP src)); |
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|
6584 format %{ "encode_heap_oop $src, $dst" %} |
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|
6585 ins_encode %{ |
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diff
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|
6586 __ encode_heap_oop($src$$Register, $dst$$Register); |
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|
6587 %} |
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|
6588 ins_pipe(ialu_reg); |
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|
6589 %} |
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|
6590 |
124
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changeset
|
6591 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
221
1e026f8da827
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|
6592 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
124
b130b98db9cf
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113
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|
6593 match(Set dst (EncodeP src)); |
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diff
changeset
|
6594 format %{ "encode_heap_oop_not_null $src, $dst" %} |
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6689060: Escape Analysis does not work with Compressed Oops
kvn
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diff
changeset
|
6595 ins_encode %{ |
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diff
changeset
|
6596 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
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|
6597 %} |
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
6598 ins_pipe(ialu_reg); |
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
6599 %} |
b130b98db9cf
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113
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changeset
|
6600 |
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|
6601 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
182
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diff
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|
6602 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
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181
diff
changeset
|
6603 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
113
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|
6604 match(Set dst (DecodeN src)); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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diff
changeset
|
6605 format %{ "decode_heap_oop $src, $dst" %} |
ba764ed4b6f2
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diff
changeset
|
6606 ins_encode %{ |
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changeset
|
6607 __ decode_heap_oop($src$$Register, $dst$$Register); |
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|
6608 %} |
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diff
changeset
|
6609 ins_pipe(ialu_reg); |
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81
diff
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|
6610 %} |
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changeset
|
6611 |
124
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113
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changeset
|
6612 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
182
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diff
changeset
|
6613 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
44abbb0d4c18
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kvn
parents:
181
diff
changeset
|
6614 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
124
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kvn
parents:
113
diff
changeset
|
6615 match(Set dst (DecodeN src)); |
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kvn
parents:
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changeset
|
6616 format %{ "decode_heap_oop_not_null $src, $dst" %} |
b130b98db9cf
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kvn
parents:
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diff
changeset
|
6617 ins_encode %{ |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6618 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
6619 %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6620 ins_pipe(ialu_reg); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6621 %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6622 |
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6623 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6624 match(Set dst (EncodePKlass src)); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6625 format %{ "encode_klass_not_null $src, $dst" %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6626 ins_encode %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6627 __ encode_klass_not_null($src$$Register, $dst$$Register); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6628 %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6629 ins_pipe(ialu_reg); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6630 %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6631 |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6632 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6633 match(Set dst (DecodeNKlass src)); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6634 format %{ "decode_klass_not_null $src, $dst" %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6635 ins_encode %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6636 __ decode_klass_not_null($src$$Register, $dst$$Register); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6637 %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6638 ins_pipe(ialu_reg); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6639 %} |
113
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|
6640 |
0 | 6641 //----------MemBar Instructions----------------------------------------------- |
6642 // Memory barrier flavors | |
6643 | |
6644 instruct membar_acquire() %{ | |
6645 match(MemBarAcquire); | |
6646 ins_cost(4*MEMORY_REF_COST); | |
6647 | |
6648 size(0); | |
6649 format %{ "MEMBAR-acquire" %} | |
6650 ins_encode( enc_membar_acquire ); | |
6651 ins_pipe(long_memory_op); | |
6652 %} | |
6653 | |
6654 instruct membar_acquire_lock() %{ | |
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6655 match(MemBarAcquireLock); |
0 | 6656 ins_cost(0); |
6657 | |
6658 size(0); | |
6659 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
6660 ins_encode( ); | |
6661 ins_pipe(empty); | |
6662 %} | |
6663 | |
6664 instruct membar_release() %{ | |
6665 match(MemBarRelease); | |
6666 ins_cost(4*MEMORY_REF_COST); | |
6667 | |
6668 size(0); | |
6669 format %{ "MEMBAR-release" %} | |
6670 ins_encode( enc_membar_release ); | |
6671 ins_pipe(long_memory_op); | |
6672 %} | |
6673 | |
6674 instruct membar_release_lock() %{ | |
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6675 match(MemBarReleaseLock); |
0 | 6676 ins_cost(0); |
6677 | |
6678 size(0); | |
6679 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
6680 ins_encode( ); | |
6681 ins_pipe(empty); | |
6682 %} | |
6683 | |
6684 instruct membar_volatile() %{ | |
6685 match(MemBarVolatile); | |
6686 ins_cost(4*MEMORY_REF_COST); | |
6687 | |
6688 size(4); | |
6689 format %{ "MEMBAR-volatile" %} | |
6690 ins_encode( enc_membar_volatile ); | |
6691 ins_pipe(long_memory_op); | |
6692 %} | |
6693 | |
6694 instruct unnecessary_membar_volatile() %{ | |
6695 match(MemBarVolatile); | |
6696 predicate(Matcher::post_store_load_barrier(n)); | |
6697 ins_cost(0); | |
6698 | |
6699 size(0); | |
6700 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
6701 ins_encode( ); | |
6702 ins_pipe(empty); | |
6703 %} | |
6704 | |
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6705 instruct membar_storestore() %{ |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6706 match(MemBarStoreStore); |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6707 ins_cost(0); |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6708 |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6709 size(0); |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6710 format %{ "!MEMBAR-storestore (empty encoding)" %} |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6711 ins_encode( ); |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6712 ins_pipe(empty); |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6713 %} |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6714 |
0 | 6715 //----------Register Move Instructions----------------------------------------- |
6716 instruct roundDouble_nop(regD dst) %{ | |
6717 match(Set dst (RoundDouble dst)); | |
6718 ins_cost(0); | |
6719 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6720 ins_encode( ); | |
6721 ins_pipe(empty); | |
6722 %} | |
6723 | |
6724 | |
6725 instruct roundFloat_nop(regF dst) %{ | |
6726 match(Set dst (RoundFloat dst)); | |
6727 ins_cost(0); | |
6728 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6729 ins_encode( ); | |
6730 ins_pipe(empty); | |
6731 %} | |
6732 | |
6733 | |
6734 // Cast Index to Pointer for unsafe natives | |
6735 instruct castX2P(iRegX src, iRegP dst) %{ | |
6736 match(Set dst (CastX2P src)); | |
6737 | |
6738 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
6739 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6740 ins_pipe(ialu_reg); | |
6741 %} | |
6742 | |
6743 // Cast Pointer to Index for unsafe natives | |
6744 instruct castP2X(iRegP src, iRegX dst) %{ | |
6745 match(Set dst (CastP2X src)); | |
6746 | |
6747 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
6748 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6749 ins_pipe(ialu_reg); | |
6750 %} | |
6751 | |
6752 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
6753 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6754 match(Set stkSlot src); // chain rule | |
6755 ins_cost(MEMORY_REF_COST); | |
6756 format %{ "STDF $src,$stkSlot\t!stk" %} | |
6757 opcode(Assembler::stdf_op3); | |
415
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parents:
235
diff
changeset
|
6758 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6759 ins_pipe(fstoreD_stk_reg); |
6760 %} | |
6761 | |
6762 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
6763 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6764 match(Set dst stkSlot); // chain rule | |
6765 ins_cost(MEMORY_REF_COST); | |
6766 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
6767 opcode(Assembler::lddf_op3); | |
415
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parents:
235
diff
changeset
|
6768 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
0 | 6769 ins_pipe(floadD_stk); |
6770 %} | |
6771 | |
6772 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
6773 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6774 match(Set stkSlot src); // chain rule | |
6775 ins_cost(MEMORY_REF_COST); | |
6776 format %{ "STF $src,$stkSlot\t!stk" %} | |
6777 opcode(Assembler::stf_op3); | |
415
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parents:
235
diff
changeset
|
6778 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6779 ins_pipe(fstoreF_stk_reg); |
6780 %} | |
6781 | |
6782 //----------Conditional Move--------------------------------------------------- | |
6783 // Conditional move | |
6784 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
6785 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6786 ins_cost(150); | |
6787 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6788 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6789 ins_pipe(ialu_reg); | |
6790 %} | |
6791 | |
6792 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
6793 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6794 ins_cost(140); | |
6795 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6796 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6797 ins_pipe(ialu_imm); | |
6798 %} | |
6799 | |
6800 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
6801 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6802 ins_cost(150); | |
6803 size(4); | |
6804 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6805 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6806 ins_pipe(ialu_reg); | |
6807 %} | |
6808 | |
6809 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
6810 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6811 ins_cost(140); | |
6812 size(4); | |
6813 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6814 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6815 ins_pipe(ialu_imm); | |
6816 %} | |
6817 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6818 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
0 | 6819 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6820 ins_cost(150); | |
6821 size(4); | |
6822 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6823 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6824 ins_pipe(ialu_reg); | |
6825 %} | |
6826 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6827 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
0 | 6828 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6829 ins_cost(140); | |
6830 size(4); | |
6831 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6832 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6833 ins_pipe(ialu_imm); | |
6834 %} | |
6835 | |
6836 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
6837 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6838 ins_cost(150); | |
6839 size(4); | |
6840 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6841 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6842 ins_pipe(ialu_reg); | |
6843 %} | |
6844 | |
6845 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
6846 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6847 ins_cost(140); | |
6848 size(4); | |
6849 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6850 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
6851 ins_pipe(ialu_imm); | |
6852 %} | |
6853 | |
164
c436414a719e
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163
diff
changeset
|
6854 // Conditional move for RegN. Only cmov(reg,reg). |
c436414a719e
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diff
changeset
|
6855 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
c436414a719e
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parents:
163
diff
changeset
|
6856 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
c436414a719e
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parents:
163
diff
changeset
|
6857 ins_cost(150); |
c436414a719e
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parents:
163
diff
changeset
|
6858 format %{ "MOV$cmp $pcc,$src,$dst" %} |
c436414a719e
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parents:
163
diff
changeset
|
6859 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
c436414a719e
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parents:
163
diff
changeset
|
6860 ins_pipe(ialu_reg); |
c436414a719e
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parents:
163
diff
changeset
|
6861 %} |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6862 |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6863 // This instruction also works with CmpN so we don't need cmovNN_reg. |
c436414a719e
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parents:
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diff
changeset
|
6864 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
c436414a719e
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parents:
163
diff
changeset
|
6865 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
c436414a719e
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parents:
163
diff
changeset
|
6866 ins_cost(150); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
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parents:
163
diff
changeset
|
6867 size(4); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
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parents:
163
diff
changeset
|
6868 format %{ "MOV$cmp $icc,$src,$dst" %} |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6869 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6870 ins_pipe(ialu_reg); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6871 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6872 |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6873 // This instruction also works with CmpN so we don't need cmovNN_reg. |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6874 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6875 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6876 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6877 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6878 format %{ "MOV$cmp $icc,$src,$dst" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6879 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6880 ins_pipe(ialu_reg); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6881 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6882 |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6883 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6884 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6885 ins_cost(150); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6886 size(4); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6887 format %{ "MOV$cmp $fcc,$src,$dst" %} |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6888 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6889 ins_pipe(ialu_reg); |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6890 %} |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6891 |
0 | 6892 // Conditional move |
6893 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
6894 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6895 ins_cost(150); | |
6896 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6897 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6898 ins_pipe(ialu_reg); | |
6899 %} | |
6900 | |
6901 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
6902 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6903 ins_cost(140); | |
6904 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6905 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6906 ins_pipe(ialu_imm); | |
6907 %} | |
6908 | |
164
c436414a719e
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parents:
163
diff
changeset
|
6909 // This instruction also works with CmpN so we don't need cmovPN_reg. |
0 | 6910 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
6911 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
6912 ins_cost(150); | |
6913 | |
6914 size(4); | |
6915 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
6916 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6917 ins_pipe(ialu_reg); | |
6918 %} | |
6919 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6920 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6921 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6922 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6923 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6924 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6925 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6926 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6927 ins_pipe(ialu_reg); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6928 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6929 |
0 | 6930 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ |
6931 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
6932 ins_cost(140); | |
6933 | |
6934 size(4); | |
6935 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
6936 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6937 ins_pipe(ialu_imm); | |
6938 %} | |
6939 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6940 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6941 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6942 ins_cost(140); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6943 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6944 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6945 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6946 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6947 ins_pipe(ialu_imm); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6948 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
6949 |
0 | 6950 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ |
6951 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
6952 ins_cost(150); | |
6953 size(4); | |
6954 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6955 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6956 ins_pipe(ialu_imm); | |
6957 %} | |
6958 | |
6959 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
6960 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
6961 ins_cost(140); | |
6962 size(4); | |
6963 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6964 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
6965 ins_pipe(ialu_imm); | |
6966 %} | |
6967 | |
6968 // Conditional move | |
6969 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
6970 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
6971 ins_cost(150); | |
6972 opcode(0x101); | |
6973 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
6974 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6975 ins_pipe(int_conditional_float_move); | |
6976 %} | |
6977 | |
6978 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
6979 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
6980 ins_cost(150); | |
6981 | |
6982 size(4); | |
6983 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
6984 opcode(0x101); | |
6985 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
6986 ins_pipe(int_conditional_float_move); | |
6987 %} | |
6988 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6989 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6990 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6991 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
6992 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
6993 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6994 format %{ "FMOVS$cmp $icc,$src,$dst" %} |
f24201449cac
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diff
changeset
|
6995 opcode(0x101); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6996 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6997 ins_pipe(int_conditional_float_move); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6998 %} |
f24201449cac
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1137
diff
changeset
|
6999 |
0 | 7000 // Conditional move, |
7001 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
7002 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
7003 ins_cost(150); | |
7004 size(4); | |
7005 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
7006 opcode(0x1); | |
7007 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
7008 ins_pipe(int_conditional_double_move); | |
7009 %} | |
7010 | |
7011 // Conditional move | |
7012 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
7013 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
7014 ins_cost(150); | |
7015 size(4); | |
7016 opcode(0x102); | |
7017 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
7018 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
7019 ins_pipe(int_conditional_double_move); | |
7020 %} | |
7021 | |
7022 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
7023 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
7024 ins_cost(150); | |
7025 | |
7026 size(4); | |
7027 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
7028 opcode(0x102); | |
7029 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
7030 ins_pipe(int_conditional_double_move); | |
7031 %} | |
7032 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
7033 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
7034 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
7035 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7036 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7037 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
7038 format %{ "FMOVD$cmp $icc,$src,$dst" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
7039 opcode(0x102); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
7040 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
7041 ins_pipe(int_conditional_double_move); |
f24201449cac
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|
7042 %} |
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|
7043 |
0 | 7044 // Conditional move, |
7045 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
7046 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
7047 ins_cost(150); | |
7048 size(4); | |
7049 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
7050 opcode(0x2); | |
7051 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
7052 ins_pipe(int_conditional_double_move); | |
7053 %} | |
7054 | |
7055 // Conditional move | |
7056 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
7057 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
7058 ins_cost(150); | |
7059 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
7060 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
7061 ins_pipe(ialu_reg); | |
7062 %} | |
7063 | |
7064 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
7065 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
7066 ins_cost(140); | |
7067 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
7068 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
7069 ins_pipe(ialu_imm); | |
7070 %} | |
7071 | |
7072 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
7073 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
7074 ins_cost(150); | |
7075 | |
7076 size(4); | |
7077 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
7078 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
7079 ins_pipe(ialu_reg); | |
7080 %} | |
7081 | |
7082 | |
1160
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|
7083 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ |
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7084 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
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changeset
|
7085 ins_cost(150); |
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changeset
|
7086 |
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changeset
|
7087 size(4); |
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changeset
|
7088 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
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|
7089 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
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changeset
|
7090 ins_pipe(ialu_reg); |
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changeset
|
7091 %} |
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changeset
|
7092 |
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|
7093 |
0 | 7094 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ |
7095 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
7096 ins_cost(150); | |
7097 | |
7098 size(4); | |
7099 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
7100 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
7101 ins_pipe(ialu_reg); | |
7102 %} | |
7103 | |
7104 | |
7105 | |
7106 //----------OS and Locking Instructions---------------------------------------- | |
7107 | |
7108 // This name is KNOWN by the ADLC and cannot be changed. | |
7109 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
7110 // for this guy. | |
7111 instruct tlsLoadP(g2RegP dst) %{ | |
7112 match(Set dst (ThreadLocal)); | |
7113 | |
7114 size(0); | |
7115 ins_cost(0); | |
7116 format %{ "# TLS is in G2" %} | |
7117 ins_encode( /*empty encoding*/ ); | |
7118 ins_pipe(ialu_none); | |
7119 %} | |
7120 | |
7121 instruct checkCastPP( iRegP dst ) %{ | |
7122 match(Set dst (CheckCastPP dst)); | |
7123 | |
7124 size(0); | |
7125 format %{ "# checkcastPP of $dst" %} | |
7126 ins_encode( /*empty encoding*/ ); | |
7127 ins_pipe(empty); | |
7128 %} | |
7129 | |
7130 | |
7131 instruct castPP( iRegP dst ) %{ | |
7132 match(Set dst (CastPP dst)); | |
7133 format %{ "# castPP of $dst" %} | |
7134 ins_encode( /*empty encoding*/ ); | |
7135 ins_pipe(empty); | |
7136 %} | |
7137 | |
7138 instruct castII( iRegI dst ) %{ | |
7139 match(Set dst (CastII dst)); | |
7140 format %{ "# castII of $dst" %} | |
7141 ins_encode( /*empty encoding*/ ); | |
7142 ins_cost(0); | |
7143 ins_pipe(empty); | |
7144 %} | |
7145 | |
7146 //----------Arithmetic Instructions-------------------------------------------- | |
7147 // Addition Instructions | |
7148 // Register Addition | |
7149 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7150 match(Set dst (AddI src1 src2)); | |
7151 | |
7152 size(4); | |
7153 format %{ "ADD $src1,$src2,$dst" %} | |
7154 ins_encode %{ | |
7155 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
7156 %} | |
7157 ins_pipe(ialu_reg_reg); | |
7158 %} | |
7159 | |
7160 // Immediate Addition | |
7161 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7162 match(Set dst (AddI src1 src2)); | |
7163 | |
7164 size(4); | |
7165 format %{ "ADD $src1,$src2,$dst" %} | |
7166 opcode(Assembler::add_op3, Assembler::arith_op); | |
7167 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7168 ins_pipe(ialu_reg_imm); | |
7169 %} | |
7170 | |
7171 // Pointer Register Addition | |
7172 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
7173 match(Set dst (AddP src1 src2)); | |
7174 | |
7175 size(4); | |
7176 format %{ "ADD $src1,$src2,$dst" %} | |
7177 opcode(Assembler::add_op3, Assembler::arith_op); | |
7178 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7179 ins_pipe(ialu_reg_reg); | |
7180 %} | |
7181 | |
7182 // Pointer Immediate Addition | |
7183 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
7184 match(Set dst (AddP src1 src2)); | |
7185 | |
7186 size(4); | |
7187 format %{ "ADD $src1,$src2,$dst" %} | |
7188 opcode(Assembler::add_op3, Assembler::arith_op); | |
7189 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7190 ins_pipe(ialu_reg_imm); | |
7191 %} | |
7192 | |
7193 // Long Addition | |
7194 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7195 match(Set dst (AddL src1 src2)); | |
7196 | |
7197 size(4); | |
7198 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
7199 opcode(Assembler::add_op3, Assembler::arith_op); | |
7200 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7201 ins_pipe(ialu_reg_reg); | |
7202 %} | |
7203 | |
7204 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7205 match(Set dst (AddL src1 con)); | |
7206 | |
7207 size(4); | |
7208 format %{ "ADD $src1,$con,$dst" %} | |
7209 opcode(Assembler::add_op3, Assembler::arith_op); | |
7210 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7211 ins_pipe(ialu_reg_imm); | |
7212 %} | |
7213 | |
7214 //----------Conditional_store-------------------------------------------------- | |
7215 // Conditional-store of the updated heap-top. | |
7216 // Used during allocation of the shared heap. | |
7217 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
7218 | |
7219 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
7220 instruct loadPLocked(iRegP dst, memory mem) %{ | |
7221 match(Set dst (LoadPLocked mem)); | |
7222 ins_cost(MEMORY_REF_COST); | |
7223 | |
7224 #ifndef _LP64 | |
7225 size(4); | |
7226 format %{ "LDUW $mem,$dst\t! ptr" %} | |
7227 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
7228 #else | |
7229 format %{ "LDX $mem,$dst\t! ptr" %} | |
7230 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
7231 #endif | |
7232 ins_encode( form3_mem_reg( mem, dst ) ); | |
7233 ins_pipe(iload_mem); | |
7234 %} | |
7235 | |
7236 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
7237 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
7238 effect( KILL newval ); | |
7239 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
7240 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
7241 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
7242 ins_pipe( long_memory_op ); | |
7243 %} | |
7244 | |
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7245 // Conditional-store of an int value. |
a1980da045cc
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7246 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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7247 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
a1980da045cc
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7248 effect( KILL newval ); |
a1980da045cc
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|
7249 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
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|
7250 "CMP $oldval,$newval\t\t! See if we made progress" %} |
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|
7251 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 7252 ins_pipe( long_memory_op ); |
7253 %} | |
7254 | |
420
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|
7255 // Conditional-store of a long value. |
a1980da045cc
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7256 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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7257 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
a1980da045cc
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|
7258 effect( KILL newval ); |
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|
7259 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
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changeset
|
7260 "CMP $oldval,$newval\t\t! See if we made progress" %} |
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|
7261 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 7262 ins_pipe( long_memory_op ); |
7263 %} | |
7264 | |
7265 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
7266 | |
7267 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
6795
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7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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|
7268 predicate(VM_Version::supports_cx8()); |
0 | 7269 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
7270 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7271 format %{ | |
7272 "MOV $newval,O7\n\t" | |
7273 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7274 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7275 "MOV 1,$res\n\t" | |
7276 "MOVne xcc,R_G0,$res" | |
7277 %} | |
7278 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
7279 enc_lflags_ne_to_boolean(res) ); | |
7280 ins_pipe( long_memory_op ); | |
7281 %} | |
7282 | |
7283 | |
7284 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
7285 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
7286 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7287 format %{ | |
7288 "MOV $newval,O7\n\t" | |
7289 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7290 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7291 "MOV 1,$res\n\t" | |
7292 "MOVne icc,R_G0,$res" | |
7293 %} | |
7294 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
7295 enc_iflags_ne_to_boolean(res) ); | |
7296 ins_pipe( long_memory_op ); | |
7297 %} | |
7298 | |
7299 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
6795
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7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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|
7300 #ifdef _LP64 |
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7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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|
7301 predicate(VM_Version::supports_cx8()); |
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7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
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7302 #endif |
0 | 7303 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
7304 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7305 format %{ | |
7306 "MOV $newval,O7\n\t" | |
113
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7307 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
0 | 7308 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
7309 "MOV 1,$res\n\t" | |
7310 "MOVne xcc,R_G0,$res" | |
7311 %} | |
113
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7312 #ifdef _LP64 |
0 | 7313 ins_encode( enc_casx(mem_ptr, oldval, newval), |
7314 enc_lflags_ne_to_boolean(res) ); | |
7315 #else | |
113
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7316 ins_encode( enc_casi(mem_ptr, oldval, newval), |
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7317 enc_iflags_ne_to_boolean(res) ); |
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7318 #endif |
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7319 ins_pipe( long_memory_op ); |
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|
7320 %} |
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|
7321 |
181
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|
7322 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
113
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7323 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
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|
7324 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
0 | 7325 format %{ |
7326 "MOV $newval,O7\n\t" | |
7327 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7328 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7329 "MOV 1,$res\n\t" | |
7330 "MOVne icc,R_G0,$res" | |
7331 %} | |
181
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|
7332 ins_encode( enc_casi(mem_ptr, oldval, newval), |
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|
7333 enc_iflags_ne_to_boolean(res) ); |
0 | 7334 ins_pipe( long_memory_op ); |
7335 %} | |
7336 | |
6795
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|
7337 instruct xchgI( memory mem, iRegI newval) %{ |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
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|
7338 match(Set newval (GetAndSetI mem newval)); |
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|
7339 format %{ "SWAP [$mem],$newval" %} |
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|
7340 size(4); |
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|
7341 ins_encode %{ |
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diff
changeset
|
7342 __ swap($mem$$Address, $newval$$Register); |
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|
7343 %} |
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|
7344 ins_pipe( long_memory_op ); |
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|
7345 %} |
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|
7346 |
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|
7347 #ifndef _LP64 |
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7348 instruct xchgP( memory mem, iRegP newval) %{ |
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7349 match(Set newval (GetAndSetP mem newval)); |
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7350 format %{ "SWAP [$mem],$newval" %} |
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7351 size(4); |
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7352 ins_encode %{ |
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7353 __ swap($mem$$Address, $newval$$Register); |
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7354 %} |
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7355 ins_pipe( long_memory_op ); |
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7356 %} |
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7357 #endif |
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7358 |
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7359 instruct xchgN( memory mem, iRegN newval) %{ |
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7360 match(Set newval (GetAndSetN mem newval)); |
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7361 format %{ "SWAP [$mem],$newval" %} |
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7362 size(4); |
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7363 ins_encode %{ |
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7364 __ swap($mem$$Address, $newval$$Register); |
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7365 %} |
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7366 ins_pipe( long_memory_op ); |
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7367 %} |
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7368 |
0 | 7369 //--------------------- |
7370 // Subtraction Instructions | |
7371 // Register Subtraction | |
7372 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7373 match(Set dst (SubI src1 src2)); | |
7374 | |
7375 size(4); | |
7376 format %{ "SUB $src1,$src2,$dst" %} | |
7377 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7378 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7379 ins_pipe(ialu_reg_reg); | |
7380 %} | |
7381 | |
7382 // Immediate Subtraction | |
7383 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7384 match(Set dst (SubI src1 src2)); | |
7385 | |
7386 size(4); | |
7387 format %{ "SUB $src1,$src2,$dst" %} | |
7388 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7389 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7390 ins_pipe(ialu_reg_imm); | |
7391 %} | |
7392 | |
7393 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
7394 match(Set dst (SubI zero src2)); | |
7395 | |
7396 size(4); | |
7397 format %{ "NEG $src2,$dst" %} | |
7398 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7399 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
7400 ins_pipe(ialu_zero_reg); | |
7401 %} | |
7402 | |
7403 // Long subtraction | |
7404 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7405 match(Set dst (SubL src1 src2)); | |
7406 | |
7407 size(4); | |
7408 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7409 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7410 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7411 ins_pipe(ialu_reg_reg); | |
7412 %} | |
7413 | |
7414 // Immediate Subtraction | |
7415 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7416 match(Set dst (SubL src1 con)); | |
7417 | |
7418 size(4); | |
7419 format %{ "SUB $src1,$con,$dst\t! long" %} | |
7420 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7421 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7422 ins_pipe(ialu_reg_imm); | |
7423 %} | |
7424 | |
7425 // Long negation | |
7426 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
7427 match(Set dst (SubL zero src2)); | |
7428 | |
7429 size(4); | |
7430 format %{ "NEG $src2,$dst\t! long" %} | |
7431 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7432 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
7433 ins_pipe(ialu_zero_reg); | |
7434 %} | |
7435 | |
7436 // Multiplication Instructions | |
7437 // Integer Multiplication | |
7438 // Register Multiplication | |
7439 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7440 match(Set dst (MulI src1 src2)); | |
7441 | |
7442 size(4); | |
7443 format %{ "MULX $src1,$src2,$dst" %} | |
7444 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7445 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7446 ins_pipe(imul_reg_reg); | |
7447 %} | |
7448 | |
7449 // Immediate Multiplication | |
7450 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7451 match(Set dst (MulI src1 src2)); | |
7452 | |
7453 size(4); | |
7454 format %{ "MULX $src1,$src2,$dst" %} | |
7455 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7456 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7457 ins_pipe(imul_reg_imm); | |
7458 %} | |
7459 | |
7460 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7461 match(Set dst (MulL src1 src2)); | |
7462 ins_cost(DEFAULT_COST * 5); | |
7463 size(4); | |
7464 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7465 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7466 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7467 ins_pipe(mulL_reg_reg); | |
7468 %} | |
7469 | |
7470 // Immediate Multiplication | |
7471 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7472 match(Set dst (MulL src1 src2)); | |
7473 ins_cost(DEFAULT_COST * 5); | |
7474 size(4); | |
7475 format %{ "MULX $src1,$src2,$dst" %} | |
7476 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7477 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7478 ins_pipe(mulL_reg_imm); | |
7479 %} | |
7480 | |
7481 // Integer Division | |
7482 // Register Division | |
7483 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
7484 match(Set dst (DivI src1 src2)); | |
7485 ins_cost((2+71)*DEFAULT_COST); | |
7486 | |
7487 format %{ "SRA $src2,0,$src2\n\t" | |
7488 "SRA $src1,0,$src1\n\t" | |
7489 "SDIVX $src1,$src2,$dst" %} | |
7490 ins_encode( idiv_reg( src1, src2, dst ) ); | |
7491 ins_pipe(sdiv_reg_reg); | |
7492 %} | |
7493 | |
7494 // Immediate Division | |
7495 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
7496 match(Set dst (DivI src1 src2)); | |
7497 ins_cost((2+71)*DEFAULT_COST); | |
7498 | |
7499 format %{ "SRA $src1,0,$src1\n\t" | |
7500 "SDIVX $src1,$src2,$dst" %} | |
7501 ins_encode( idiv_imm( src1, src2, dst ) ); | |
7502 ins_pipe(sdiv_reg_imm); | |
7503 %} | |
7504 | |
7505 //----------Div-By-10-Expansion------------------------------------------------ | |
7506 // Extract hi bits of a 32x32->64 bit multiply. | |
7507 // Expand rule only, not matched | |
7508 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
7509 effect( DEF dst, USE src1, USE src2 ); | |
7510 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
7511 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
7512 ins_encode( enc_mul_hi(dst,src1,src2)); | |
7513 ins_pipe(sdiv_reg_reg); | |
7514 %} | |
7515 | |
605 | 7516 // Magic constant, reciprocal of 10 |
0 | 7517 instruct loadConI_x66666667(iRegIsafe dst) %{ |
7518 effect( DEF dst ); | |
7519 | |
7520 size(8); | |
7521 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
7522 ins_encode( Set32(0x66666667, dst) ); | |
7523 ins_pipe(ialu_hi_lo_reg); | |
7524 %} | |
7525 | |
605 | 7526 // Register Shift Right Arithmetic Long by 32-63 |
0 | 7527 instruct sra_31( iRegI dst, iRegI src ) %{ |
7528 effect( DEF dst, USE src ); | |
7529 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
7530 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
7531 ins_pipe(ialu_reg_reg); | |
7532 %} | |
7533 | |
7534 // Arithmetic Shift Right by 8-bit immediate | |
7535 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
7536 effect( DEF dst, USE src ); | |
7537 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
7538 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7539 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
7540 ins_pipe(ialu_reg_imm); | |
7541 %} | |
7542 | |
7543 // Integer DIV with 10 | |
7544 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
7545 match(Set dst (DivI src div)); | |
7546 ins_cost((6+6)*DEFAULT_COST); | |
7547 expand %{ | |
7548 iRegIsafe tmp1; // Killed temps; | |
7549 iRegIsafe tmp2; // Killed temps; | |
7550 iRegI tmp3; // Killed temps; | |
7551 iRegI tmp4; // Killed temps; | |
7552 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
7553 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
7554 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
7555 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
7556 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
7557 %} | |
7558 %} | |
7559 | |
7560 // Register Long Division | |
7561 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7562 match(Set dst (DivL src1 src2)); | |
7563 ins_cost(DEFAULT_COST*71); | |
7564 size(4); | |
7565 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7566 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7567 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7568 ins_pipe(divL_reg_reg); | |
7569 %} | |
7570 | |
7571 // Register Long Division | |
7572 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7573 match(Set dst (DivL src1 src2)); | |
7574 ins_cost(DEFAULT_COST*71); | |
7575 size(4); | |
7576 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7577 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7578 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7579 ins_pipe(divL_reg_imm); | |
7580 %} | |
7581 | |
7582 // Integer Remainder | |
7583 // Register Remainder | |
7584 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
7585 match(Set dst (ModI src1 src2)); | |
7586 effect( KILL ccr, KILL temp); | |
7587 | |
7588 format %{ "SREM $src1,$src2,$dst" %} | |
7589 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
7590 ins_pipe(sdiv_reg_reg); | |
7591 %} | |
7592 | |
7593 // Immediate Remainder | |
7594 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
7595 match(Set dst (ModI src1 src2)); | |
7596 effect( KILL ccr, KILL temp); | |
7597 | |
7598 format %{ "SREM $src1,$src2,$dst" %} | |
7599 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
7600 ins_pipe(sdiv_reg_imm); | |
7601 %} | |
7602 | |
7603 // Register Long Remainder | |
7604 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7605 effect(DEF dst, USE src1, USE src2); | |
7606 size(4); | |
7607 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7608 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7609 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7610 ins_pipe(divL_reg_reg); | |
7611 %} | |
7612 | |
7613 // Register Long Division | |
7614 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7615 effect(DEF dst, USE src1, USE src2); | |
7616 size(4); | |
7617 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7618 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7619 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7620 ins_pipe(divL_reg_imm); | |
7621 %} | |
7622 | |
7623 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7624 effect(DEF dst, USE src1, USE src2); | |
7625 size(4); | |
7626 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7627 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7628 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7629 ins_pipe(mulL_reg_reg); | |
7630 %} | |
7631 | |
7632 // Immediate Multiplication | |
7633 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7634 effect(DEF dst, USE src1, USE src2); | |
7635 size(4); | |
7636 format %{ "MULX $src1,$src2,$dst" %} | |
7637 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7638 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7639 ins_pipe(mulL_reg_imm); | |
7640 %} | |
7641 | |
7642 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7643 effect(DEF dst, USE src1, USE src2); | |
7644 size(4); | |
7645 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7646 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7647 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7648 ins_pipe(ialu_reg_reg); | |
7649 %} | |
7650 | |
7651 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
7652 effect(DEF dst, USE src1, USE src2); | |
7653 size(4); | |
7654 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7655 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7656 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7657 ins_pipe(ialu_reg_reg); | |
7658 %} | |
7659 | |
7660 // Register Long Remainder | |
7661 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7662 match(Set dst (ModL src1 src2)); | |
7663 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7664 expand %{ | |
7665 iRegL tmp1; | |
7666 iRegL tmp2; | |
7667 divL_reg_reg_1(tmp1, src1, src2); | |
7668 mulL_reg_reg_1(tmp2, tmp1, src2); | |
7669 subL_reg_reg_1(dst, src1, tmp2); | |
7670 %} | |
7671 %} | |
7672 | |
7673 // Register Long Remainder | |
7674 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7675 match(Set dst (ModL src1 src2)); | |
7676 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7677 expand %{ | |
7678 iRegL tmp1; | |
7679 iRegL tmp2; | |
7680 divL_reg_imm13_1(tmp1, src1, src2); | |
7681 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
7682 subL_reg_reg_2 (dst, src1, tmp2); | |
7683 %} | |
7684 %} | |
7685 | |
7686 // Integer Shift Instructions | |
7687 // Register Shift Left | |
7688 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7689 match(Set dst (LShiftI src1 src2)); | |
7690 | |
7691 size(4); | |
7692 format %{ "SLL $src1,$src2,$dst" %} | |
7693 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7694 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7695 ins_pipe(ialu_reg_reg); | |
7696 %} | |
7697 | |
7698 // Register Shift Left Immediate | |
7699 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7700 match(Set dst (LShiftI src1 src2)); | |
7701 | |
7702 size(4); | |
7703 format %{ "SLL $src1,$src2,$dst" %} | |
7704 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7705 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7706 ins_pipe(ialu_reg_imm); | |
7707 %} | |
7708 | |
7709 // Register Shift Left | |
7710 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7711 match(Set dst (LShiftL src1 src2)); | |
7712 | |
7713 size(4); | |
7714 format %{ "SLLX $src1,$src2,$dst" %} | |
7715 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7716 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7717 ins_pipe(ialu_reg_reg); | |
7718 %} | |
7719 | |
7720 // Register Shift Left Immediate | |
7721 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7722 match(Set dst (LShiftL src1 src2)); | |
7723 | |
7724 size(4); | |
7725 format %{ "SLLX $src1,$src2,$dst" %} | |
7726 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7727 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7728 ins_pipe(ialu_reg_imm); | |
7729 %} | |
7730 | |
7731 // Register Arithmetic Shift Right | |
7732 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7733 match(Set dst (RShiftI src1 src2)); | |
7734 size(4); | |
7735 format %{ "SRA $src1,$src2,$dst" %} | |
7736 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7737 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7738 ins_pipe(ialu_reg_reg); | |
7739 %} | |
7740 | |
7741 // Register Arithmetic Shift Right Immediate | |
7742 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7743 match(Set dst (RShiftI src1 src2)); | |
7744 | |
7745 size(4); | |
7746 format %{ "SRA $src1,$src2,$dst" %} | |
7747 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7748 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7749 ins_pipe(ialu_reg_imm); | |
7750 %} | |
7751 | |
7752 // Register Shift Right Arithmatic Long | |
7753 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7754 match(Set dst (RShiftL src1 src2)); | |
7755 | |
7756 size(4); | |
7757 format %{ "SRAX $src1,$src2,$dst" %} | |
7758 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7759 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7760 ins_pipe(ialu_reg_reg); | |
7761 %} | |
7762 | |
7763 // Register Shift Left Immediate | |
7764 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7765 match(Set dst (RShiftL src1 src2)); | |
7766 | |
7767 size(4); | |
7768 format %{ "SRAX $src1,$src2,$dst" %} | |
7769 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7770 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7771 ins_pipe(ialu_reg_imm); | |
7772 %} | |
7773 | |
7774 // Register Shift Right | |
7775 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7776 match(Set dst (URShiftI src1 src2)); | |
7777 | |
7778 size(4); | |
7779 format %{ "SRL $src1,$src2,$dst" %} | |
7780 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7781 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7782 ins_pipe(ialu_reg_reg); | |
7783 %} | |
7784 | |
7785 // Register Shift Right Immediate | |
7786 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7787 match(Set dst (URShiftI src1 src2)); | |
7788 | |
7789 size(4); | |
7790 format %{ "SRL $src1,$src2,$dst" %} | |
7791 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7792 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7793 ins_pipe(ialu_reg_imm); | |
7794 %} | |
7795 | |
7796 // Register Shift Right | |
7797 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7798 match(Set dst (URShiftL src1 src2)); | |
7799 | |
7800 size(4); | |
7801 format %{ "SRLX $src1,$src2,$dst" %} | |
7802 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7803 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7804 ins_pipe(ialu_reg_reg); | |
7805 %} | |
7806 | |
7807 // Register Shift Right Immediate | |
7808 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7809 match(Set dst (URShiftL src1 src2)); | |
7810 | |
7811 size(4); | |
7812 format %{ "SRLX $src1,$src2,$dst" %} | |
7813 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7814 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7815 ins_pipe(ialu_reg_imm); | |
7816 %} | |
7817 | |
7818 // Register Shift Right Immediate with a CastP2X | |
7819 #ifdef _LP64 | |
7820 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
7821 match(Set dst (URShiftL (CastP2X src1) src2)); | |
7822 size(4); | |
7823 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
7824 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7825 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7826 ins_pipe(ialu_reg_imm); | |
7827 %} | |
7828 #else | |
7829 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
7830 match(Set dst (URShiftI (CastP2X src1) src2)); | |
7831 size(4); | |
7832 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
7833 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7834 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7835 ins_pipe(ialu_reg_imm); | |
7836 %} | |
7837 #endif | |
7838 | |
7839 | |
7840 //----------Floating Point Arithmetic Instructions----------------------------- | |
7841 | |
7842 // Add float single precision | |
7843 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7844 match(Set dst (AddF src1 src2)); | |
7845 | |
7846 size(4); | |
7847 format %{ "FADDS $src1,$src2,$dst" %} | |
7848 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
7849 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7850 ins_pipe(faddF_reg_reg); | |
7851 %} | |
7852 | |
7853 // Add float double precision | |
7854 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7855 match(Set dst (AddD src1 src2)); | |
7856 | |
7857 size(4); | |
7858 format %{ "FADDD $src1,$src2,$dst" %} | |
7859 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
7860 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7861 ins_pipe(faddD_reg_reg); | |
7862 %} | |
7863 | |
7864 // Sub float single precision | |
7865 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7866 match(Set dst (SubF src1 src2)); | |
7867 | |
7868 size(4); | |
7869 format %{ "FSUBS $src1,$src2,$dst" %} | |
7870 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
7871 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7872 ins_pipe(faddF_reg_reg); | |
7873 %} | |
7874 | |
7875 // Sub float double precision | |
7876 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7877 match(Set dst (SubD src1 src2)); | |
7878 | |
7879 size(4); | |
7880 format %{ "FSUBD $src1,$src2,$dst" %} | |
7881 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
7882 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7883 ins_pipe(faddD_reg_reg); | |
7884 %} | |
7885 | |
7886 // Mul float single precision | |
7887 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7888 match(Set dst (MulF src1 src2)); | |
7889 | |
7890 size(4); | |
7891 format %{ "FMULS $src1,$src2,$dst" %} | |
7892 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
7893 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7894 ins_pipe(fmulF_reg_reg); | |
7895 %} | |
7896 | |
7897 // Mul float double precision | |
7898 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7899 match(Set dst (MulD src1 src2)); | |
7900 | |
7901 size(4); | |
7902 format %{ "FMULD $src1,$src2,$dst" %} | |
7903 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
7904 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7905 ins_pipe(fmulD_reg_reg); | |
7906 %} | |
7907 | |
7908 // Div float single precision | |
7909 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7910 match(Set dst (DivF src1 src2)); | |
7911 | |
7912 size(4); | |
7913 format %{ "FDIVS $src1,$src2,$dst" %} | |
7914 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
7915 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7916 ins_pipe(fdivF_reg_reg); | |
7917 %} | |
7918 | |
7919 // Div float double precision | |
7920 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7921 match(Set dst (DivD src1 src2)); | |
7922 | |
7923 size(4); | |
7924 format %{ "FDIVD $src1,$src2,$dst" %} | |
7925 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
7926 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7927 ins_pipe(fdivD_reg_reg); | |
7928 %} | |
7929 | |
7930 // Absolute float double precision | |
7931 instruct absD_reg(regD dst, regD src) %{ | |
7932 match(Set dst (AbsD src)); | |
7933 | |
7934 format %{ "FABSd $src,$dst" %} | |
7935 ins_encode(fabsd(dst, src)); | |
7936 ins_pipe(faddD_reg); | |
7937 %} | |
7938 | |
7939 // Absolute float single precision | |
7940 instruct absF_reg(regF dst, regF src) %{ | |
7941 match(Set dst (AbsF src)); | |
7942 | |
7943 format %{ "FABSs $src,$dst" %} | |
7944 ins_encode(fabss(dst, src)); | |
7945 ins_pipe(faddF_reg); | |
7946 %} | |
7947 | |
7948 instruct negF_reg(regF dst, regF src) %{ | |
7949 match(Set dst (NegF src)); | |
7950 | |
7951 size(4); | |
7952 format %{ "FNEGs $src,$dst" %} | |
7953 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
7954 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
7955 ins_pipe(faddF_reg); | |
7956 %} | |
7957 | |
7958 instruct negD_reg(regD dst, regD src) %{ | |
7959 match(Set dst (NegD src)); | |
7960 | |
7961 format %{ "FNEGd $src,$dst" %} | |
7962 ins_encode(fnegd(dst, src)); | |
7963 ins_pipe(faddD_reg); | |
7964 %} | |
7965 | |
7966 // Sqrt float double precision | |
7967 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
7968 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
7969 | |
7970 size(4); | |
7971 format %{ "FSQRTS $src,$dst" %} | |
7972 ins_encode(fsqrts(dst, src)); | |
7973 ins_pipe(fdivF_reg_reg); | |
7974 %} | |
7975 | |
7976 // Sqrt float double precision | |
7977 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
7978 match(Set dst (SqrtD src)); | |
7979 | |
7980 size(4); | |
7981 format %{ "FSQRTD $src,$dst" %} | |
7982 ins_encode(fsqrtd(dst, src)); | |
7983 ins_pipe(fdivD_reg_reg); | |
7984 %} | |
7985 | |
7986 //----------Logical Instructions----------------------------------------------- | |
7987 // And Instructions | |
7988 // Register And | |
7989 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7990 match(Set dst (AndI src1 src2)); | |
7991 | |
7992 size(4); | |
7993 format %{ "AND $src1,$src2,$dst" %} | |
7994 opcode(Assembler::and_op3, Assembler::arith_op); | |
7995 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7996 ins_pipe(ialu_reg_reg); | |
7997 %} | |
7998 | |
7999 // Immediate And | |
8000 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
8001 match(Set dst (AndI src1 src2)); | |
8002 | |
8003 size(4); | |
8004 format %{ "AND $src1,$src2,$dst" %} | |
8005 opcode(Assembler::and_op3, Assembler::arith_op); | |
8006 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
8007 ins_pipe(ialu_reg_imm); | |
8008 %} | |
8009 | |
8010 // Register And Long | |
8011 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
8012 match(Set dst (AndL src1 src2)); | |
8013 | |
8014 ins_cost(DEFAULT_COST); | |
8015 size(4); | |
8016 format %{ "AND $src1,$src2,$dst\t! long" %} | |
8017 opcode(Assembler::and_op3, Assembler::arith_op); | |
8018 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8019 ins_pipe(ialu_reg_reg); | |
8020 %} | |
8021 | |
8022 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
8023 match(Set dst (AndL src1 con)); | |
8024 | |
8025 ins_cost(DEFAULT_COST); | |
8026 size(4); | |
8027 format %{ "AND $src1,$con,$dst\t! long" %} | |
8028 opcode(Assembler::and_op3, Assembler::arith_op); | |
8029 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
8030 ins_pipe(ialu_reg_imm); | |
8031 %} | |
8032 | |
8033 // Or Instructions | |
8034 // Register Or | |
8035 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
8036 match(Set dst (OrI src1 src2)); | |
8037 | |
8038 size(4); | |
8039 format %{ "OR $src1,$src2,$dst" %} | |
8040 opcode(Assembler::or_op3, Assembler::arith_op); | |
8041 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8042 ins_pipe(ialu_reg_reg); | |
8043 %} | |
8044 | |
8045 // Immediate Or | |
8046 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
8047 match(Set dst (OrI src1 src2)); | |
8048 | |
8049 size(4); | |
8050 format %{ "OR $src1,$src2,$dst" %} | |
8051 opcode(Assembler::or_op3, Assembler::arith_op); | |
8052 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
8053 ins_pipe(ialu_reg_imm); | |
8054 %} | |
8055 | |
8056 // Register Or Long | |
8057 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
8058 match(Set dst (OrL src1 src2)); | |
8059 | |
8060 ins_cost(DEFAULT_COST); | |
8061 size(4); | |
8062 format %{ "OR $src1,$src2,$dst\t! long" %} | |
8063 opcode(Assembler::or_op3, Assembler::arith_op); | |
8064 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8065 ins_pipe(ialu_reg_reg); | |
8066 %} | |
8067 | |
8068 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
8069 match(Set dst (OrL src1 con)); | |
8070 ins_cost(DEFAULT_COST*2); | |
8071 | |
8072 ins_cost(DEFAULT_COST); | |
8073 size(4); | |
8074 format %{ "OR $src1,$con,$dst\t! long" %} | |
8075 opcode(Assembler::or_op3, Assembler::arith_op); | |
8076 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
8077 ins_pipe(ialu_reg_imm); | |
8078 %} | |
8079 | |
420
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8080 #ifndef _LP64 |
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8081 |
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8082 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
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8083 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
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8084 match(Set dst (OrI src1 (CastP2X src2))); |
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8085 |
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8086 size(4); |
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8087 format %{ "OR $src1,$src2,$dst" %} |
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8088 opcode(Assembler::or_op3, Assembler::arith_op); |
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8089 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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8090 ins_pipe(ialu_reg_reg); |
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8091 %} |
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8092 |
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8093 #else |
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8094 |
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8095 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
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8096 match(Set dst (OrL src1 (CastP2X src2))); |
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8097 |
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8098 ins_cost(DEFAULT_COST); |
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8099 size(4); |
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8100 format %{ "OR $src1,$src2,$dst\t! long" %} |
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8101 opcode(Assembler::or_op3, Assembler::arith_op); |
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8102 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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8103 ins_pipe(ialu_reg_reg); |
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8104 %} |
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8105 |
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8106 #endif |
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8107 |
0 | 8108 // Xor Instructions |
8109 // Register Xor | |
8110 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
8111 match(Set dst (XorI src1 src2)); | |
8112 | |
8113 size(4); | |
8114 format %{ "XOR $src1,$src2,$dst" %} | |
8115 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8116 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8117 ins_pipe(ialu_reg_reg); | |
8118 %} | |
8119 | |
8120 // Immediate Xor | |
8121 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
8122 match(Set dst (XorI src1 src2)); | |
8123 | |
8124 size(4); | |
8125 format %{ "XOR $src1,$src2,$dst" %} | |
8126 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8127 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
8128 ins_pipe(ialu_reg_imm); | |
8129 %} | |
8130 | |
8131 // Register Xor Long | |
8132 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
8133 match(Set dst (XorL src1 src2)); | |
8134 | |
8135 ins_cost(DEFAULT_COST); | |
8136 size(4); | |
8137 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
8138 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8139 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8140 ins_pipe(ialu_reg_reg); | |
8141 %} | |
8142 | |
8143 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
8144 match(Set dst (XorL src1 con)); | |
8145 | |
8146 ins_cost(DEFAULT_COST); | |
8147 size(4); | |
8148 format %{ "XOR $src1,$con,$dst\t! long" %} | |
8149 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8150 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
8151 ins_pipe(ialu_reg_imm); | |
8152 %} | |
8153 | |
8154 //----------Convert to Boolean------------------------------------------------- | |
8155 // Nice hack for 32-bit tests but doesn't work for | |
8156 // 64-bit pointers. | |
8157 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
8158 match(Set dst (Conv2B src)); | |
8159 effect( KILL ccr ); | |
8160 ins_cost(DEFAULT_COST*2); | |
8161 format %{ "CMP R_G0,$src\n\t" | |
8162 "ADDX R_G0,0,$dst" %} | |
8163 ins_encode( enc_to_bool( src, dst ) ); | |
8164 ins_pipe(ialu_reg_ialu); | |
8165 %} | |
8166 | |
8167 #ifndef _LP64 | |
8168 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
8169 match(Set dst (Conv2B src)); | |
8170 effect( KILL ccr ); | |
8171 ins_cost(DEFAULT_COST*2); | |
8172 format %{ "CMP R_G0,$src\n\t" | |
8173 "ADDX R_G0,0,$dst" %} | |
8174 ins_encode( enc_to_bool( src, dst ) ); | |
8175 ins_pipe(ialu_reg_ialu); | |
8176 %} | |
8177 #else | |
8178 instruct convP2B( iRegI dst, iRegP src ) %{ | |
8179 match(Set dst (Conv2B src)); | |
8180 ins_cost(DEFAULT_COST*2); | |
8181 format %{ "MOV $src,$dst\n\t" | |
8182 "MOVRNZ $src,1,$dst" %} | |
8183 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
8184 ins_pipe(ialu_clr_and_mover); | |
8185 %} | |
8186 #endif | |
8187 | |
2254
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8188 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8189 match(Set dst (CmpLTMask src zero)); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8190 effect(KILL ccr); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8191 size(4); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8192 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8193 ins_encode %{ |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8194 __ sra($src$$Register, 31, $dst$$Register); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8195 %} |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8196 ins_pipe(ialu_reg_imm); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8197 %} |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8198 |
0 | 8199 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ |
8200 match(Set dst (CmpLTMask p q)); | |
8201 effect( KILL ccr ); | |
8202 ins_cost(DEFAULT_COST*4); | |
8203 format %{ "CMP $p,$q\n\t" | |
8204 "MOV #0,$dst\n\t" | |
8205 "BLT,a .+8\n\t" | |
8206 "MOV #-1,$dst" %} | |
8207 ins_encode( enc_ltmask(p,q,dst) ); | |
8208 ins_pipe(ialu_reg_reg_ialu); | |
8209 %} | |
8210 | |
8211 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
8212 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
8213 effect(KILL ccr, TEMP tmp); | |
8214 ins_cost(DEFAULT_COST*3); | |
8215 | |
8216 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
8217 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
2254
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8218 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} |
9154 | 8219 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp)); |
8220 ins_pipe(cadd_cmpltmask); | |
8221 %} | |
8222 | |
8223 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{ | |
8224 match(Set p (AndI (CmpLTMask p q) y)); | |
8225 effect(KILL ccr); | |
8226 ins_cost(DEFAULT_COST*3); | |
8227 | |
8228 format %{ "CMP $p,$q\n\t" | |
8229 "MOV $y,$p\n\t" | |
8230 "MOVge G0,$p" %} | |
8231 ins_encode %{ | |
8232 __ cmp($p$$Register, $q$$Register); | |
8233 __ mov($y$$Register, $p$$Register); | |
8234 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register); | |
8235 %} | |
8236 ins_pipe(ialu_reg_reg_ialu); | |
8237 %} | |
3804 | 8238 |
8239 //----------------------------------------------------------------- | |
8240 // Direct raw moves between float and general registers using VIS3. | |
8241 | |
8242 // ins_pipe(faddF_reg); | |
8243 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ | |
8244 predicate(UseVIS >= 3); | |
8245 match(Set dst (MoveF2I src)); | |
8246 | |
8247 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} | |
8248 ins_encode %{ | |
8249 __ movstouw($src$$FloatRegister, $dst$$Register); | |
8250 %} | |
8251 ins_pipe(ialu_reg_reg); | |
8252 %} | |
8253 | |
8254 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ | |
8255 predicate(UseVIS >= 3); | |
8256 match(Set dst (MoveI2F src)); | |
8257 | |
8258 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} | |
8259 ins_encode %{ | |
8260 __ movwtos($src$$Register, $dst$$FloatRegister); | |
8261 %} | |
0 | 8262 ins_pipe(ialu_reg_reg); |
8263 %} | |
8264 | |
3804 | 8265 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ |
8266 predicate(UseVIS >= 3); | |
8267 match(Set dst (MoveD2L src)); | |
8268 | |
8269 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} | |
8270 ins_encode %{ | |
8271 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); | |
8272 %} | |
0 | 8273 ins_pipe(ialu_reg_reg); |
8274 %} | |
8275 | |
3804 | 8276 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ |
8277 predicate(UseVIS >= 3); | |
8278 match(Set dst (MoveL2D src)); | |
8279 | |
8280 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} | |
8281 ins_encode %{ | |
8282 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); | |
8283 %} | |
0 | 8284 ins_pipe(ialu_reg_reg); |
8285 %} | |
8286 | |
3804 | 8287 |
8288 // Raw moves between float and general registers using stack. | |
8289 | |
0 | 8290 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ |
8291 match(Set dst (MoveF2I src)); | |
8292 effect(DEF dst, USE src); | |
8293 ins_cost(MEMORY_REF_COST); | |
8294 | |
8295 size(4); | |
8296 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
8297 opcode(Assembler::lduw_op3); | |
415
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never
parents:
235
diff
changeset
|
8298 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8299 ins_pipe(iload_mem); |
8300 %} | |
8301 | |
8302 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
8303 match(Set dst (MoveI2F src)); | |
8304 effect(DEF dst, USE src); | |
8305 ins_cost(MEMORY_REF_COST); | |
8306 | |
8307 size(4); | |
8308 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
8309 opcode(Assembler::ldf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8310 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8311 ins_pipe(floadF_stk); |
8312 %} | |
8313 | |
8314 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
8315 match(Set dst (MoveD2L src)); | |
8316 effect(DEF dst, USE src); | |
8317 ins_cost(MEMORY_REF_COST); | |
8318 | |
8319 size(4); | |
8320 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
8321 opcode(Assembler::ldx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8322 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8323 ins_pipe(iload_mem); |
8324 %} | |
8325 | |
8326 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
8327 match(Set dst (MoveL2D src)); | |
8328 effect(DEF dst, USE src); | |
8329 ins_cost(MEMORY_REF_COST); | |
8330 | |
8331 size(4); | |
8332 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
8333 opcode(Assembler::lddf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8334 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8335 ins_pipe(floadD_stk); |
8336 %} | |
8337 | |
8338 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
8339 match(Set dst (MoveF2I src)); | |
8340 effect(DEF dst, USE src); | |
8341 ins_cost(MEMORY_REF_COST); | |
8342 | |
8343 size(4); | |
3804 | 8344 format %{ "STF $src,$dst\t! MoveF2I" %} |
0 | 8345 opcode(Assembler::stf_op3); |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8346 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8347 ins_pipe(fstoreF_stk_reg); |
8348 %} | |
8349 | |
8350 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
8351 match(Set dst (MoveI2F src)); | |
8352 effect(DEF dst, USE src); | |
8353 ins_cost(MEMORY_REF_COST); | |
8354 | |
8355 size(4); | |
3804 | 8356 format %{ "STW $src,$dst\t! MoveI2F" %} |
0 | 8357 opcode(Assembler::stw_op3); |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8358 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8359 ins_pipe(istore_mem_reg); |
8360 %} | |
8361 | |
8362 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
8363 match(Set dst (MoveD2L src)); | |
8364 effect(DEF dst, USE src); | |
8365 ins_cost(MEMORY_REF_COST); | |
8366 | |
8367 size(4); | |
3804 | 8368 format %{ "STDF $src,$dst\t! MoveD2L" %} |
0 | 8369 opcode(Assembler::stdf_op3); |
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8370 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8371 ins_pipe(fstoreD_stk_reg); |
8372 %} | |
8373 | |
8374 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
8375 match(Set dst (MoveL2D src)); | |
8376 effect(DEF dst, USE src); | |
8377 ins_cost(MEMORY_REF_COST); | |
8378 | |
8379 size(4); | |
3804 | 8380 format %{ "STX $src,$dst\t! MoveL2D" %} |
0 | 8381 opcode(Assembler::stx_op3); |
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
235
diff
changeset
|
8382 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8383 ins_pipe(istore_mem_reg); |
8384 %} | |
8385 | |
8386 | |
3804 | 8387 //----------Arithmetic Conversion Instructions--------------------------------- |
8388 // The conversions operations are all Alpha sorted. Please keep it that way! | |
8389 | |
8390 instruct convD2F_reg(regF dst, regD src) %{ | |
8391 match(Set dst (ConvD2F src)); | |
8392 size(4); | |
8393 format %{ "FDTOS $src,$dst" %} | |
8394 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
8395 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
8396 ins_pipe(fcvtD2F); | |
8397 %} | |
8398 | |
8399 | |
8400 // Convert a double to an int in a float register. | |
8401 // If the double is a NAN, stuff a zero in instead. | |
8402 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
8403 effect(DEF dst, USE src, KILL fcc0); | |
8404 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
8405 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8406 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
8407 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
8408 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
8409 "skip:" %} | |
8410 ins_encode(form_d2i_helper(src,dst)); | |
8411 ins_pipe(fcvtD2I); | |
8412 %} | |
8413 | |
8414 instruct convD2I_stk(stackSlotI dst, regD src) %{ | |
8415 match(Set dst (ConvD2I src)); | |
8416 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8417 expand %{ | |
8418 regF tmp; | |
8419 convD2I_helper(tmp, src); | |
8420 regF_to_stkI(dst, tmp); | |
8421 %} | |
8422 %} | |
8423 | |
8424 instruct convD2I_reg(iRegI dst, regD src) %{ | |
8425 predicate(UseVIS >= 3); | |
8426 match(Set dst (ConvD2I src)); | |
8427 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
8428 expand %{ | |
8429 regF tmp; | |
8430 convD2I_helper(tmp, src); | |
8431 MoveF2I_reg_reg(dst, tmp); | |
8432 %} | |
8433 %} | |
8434 | |
8435 | |
8436 // Convert a double to a long in a double register. | |
8437 // If the double is a NAN, stuff a zero in instead. | |
8438 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
8439 effect(DEF dst, USE src, KILL fcc0); | |
8440 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
8441 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8442 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
8443 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
8444 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
8445 "skip:" %} | |
8446 ins_encode(form_d2l_helper(src,dst)); | |
8447 ins_pipe(fcvtD2L); | |
8448 %} | |
8449 | |
8450 instruct convD2L_stk(stackSlotL dst, regD src) %{ | |
8451 match(Set dst (ConvD2L src)); | |
8452 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8453 expand %{ | |
8454 regD tmp; | |
8455 convD2L_helper(tmp, src); | |
8456 regD_to_stkL(dst, tmp); | |
8457 %} | |
8458 %} | |
8459 | |
8460 instruct convD2L_reg(iRegL dst, regD src) %{ | |
8461 predicate(UseVIS >= 3); | |
8462 match(Set dst (ConvD2L src)); | |
8463 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
8464 expand %{ | |
8465 regD tmp; | |
8466 convD2L_helper(tmp, src); | |
8467 MoveD2L_reg_reg(dst, tmp); | |
8468 %} | |
8469 %} | |
8470 | |
8471 | |
8472 instruct convF2D_reg(regD dst, regF src) %{ | |
8473 match(Set dst (ConvF2D src)); | |
8474 format %{ "FSTOD $src,$dst" %} | |
8475 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
8476 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
8477 ins_pipe(fcvtF2D); | |
8478 %} | |
8479 | |
8480 | |
8481 // Convert a float to an int in a float register. | |
8482 // If the float is a NAN, stuff a zero in instead. | |
8483 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
8484 effect(DEF dst, USE src, KILL fcc0); | |
8485 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
8486 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8487 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
8488 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
8489 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
8490 "skip:" %} | |
8491 ins_encode(form_f2i_helper(src,dst)); | |
8492 ins_pipe(fcvtF2I); | |
8493 %} | |
8494 | |
8495 instruct convF2I_stk(stackSlotI dst, regF src) %{ | |
8496 match(Set dst (ConvF2I src)); | |
8497 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8498 expand %{ | |
8499 regF tmp; | |
8500 convF2I_helper(tmp, src); | |
8501 regF_to_stkI(dst, tmp); | |
8502 %} | |
8503 %} | |
8504 | |
8505 instruct convF2I_reg(iRegI dst, regF src) %{ | |
8506 predicate(UseVIS >= 3); | |
8507 match(Set dst (ConvF2I src)); | |
8508 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
8509 expand %{ | |
8510 regF tmp; | |
8511 convF2I_helper(tmp, src); | |
8512 MoveF2I_reg_reg(dst, tmp); | |
8513 %} | |
8514 %} | |
8515 | |
8516 | |
8517 // Convert a float to a long in a float register. | |
8518 // If the float is a NAN, stuff a zero in instead. | |
8519 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
8520 effect(DEF dst, USE src, KILL fcc0); | |
8521 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
8522 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8523 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
8524 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
8525 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
8526 "skip:" %} | |
8527 ins_encode(form_f2l_helper(src,dst)); | |
8528 ins_pipe(fcvtF2L); | |
8529 %} | |
8530 | |
8531 instruct convF2L_stk(stackSlotL dst, regF src) %{ | |
8532 match(Set dst (ConvF2L src)); | |
8533 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8534 expand %{ | |
8535 regD tmp; | |
8536 convF2L_helper(tmp, src); | |
8537 regD_to_stkL(dst, tmp); | |
8538 %} | |
8539 %} | |
8540 | |
8541 instruct convF2L_reg(iRegL dst, regF src) %{ | |
8542 predicate(UseVIS >= 3); | |
8543 match(Set dst (ConvF2L src)); | |
8544 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
8545 expand %{ | |
8546 regD tmp; | |
8547 convF2L_helper(tmp, src); | |
8548 MoveD2L_reg_reg(dst, tmp); | |
8549 %} | |
8550 %} | |
8551 | |
8552 | |
8553 instruct convI2D_helper(regD dst, regF tmp) %{ | |
8554 effect(USE tmp, DEF dst); | |
8555 format %{ "FITOD $tmp,$dst" %} | |
8556 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
8557 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
8558 ins_pipe(fcvtI2D); | |
8559 %} | |
8560 | |
8561 instruct convI2D_stk(stackSlotI src, regD dst) %{ | |
8562 match(Set dst (ConvI2D src)); | |
8563 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8564 expand %{ | |
8565 regF tmp; | |
8566 stkI_to_regF(tmp, src); | |
8567 convI2D_helper(dst, tmp); | |
8568 %} | |
8569 %} | |
8570 | |
8571 instruct convI2D_reg(regD_low dst, iRegI src) %{ | |
8572 predicate(UseVIS >= 3); | |
8573 match(Set dst (ConvI2D src)); | |
8574 expand %{ | |
8575 regF tmp; | |
8576 MoveI2F_reg_reg(tmp, src); | |
8577 convI2D_helper(dst, tmp); | |
8578 %} | |
8579 %} | |
8580 | |
8581 instruct convI2D_mem(regD_low dst, memory mem) %{ | |
8582 match(Set dst (ConvI2D (LoadI mem))); | |
8583 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8584 size(8); | |
8585 format %{ "LDF $mem,$dst\n\t" | |
8586 "FITOD $dst,$dst" %} | |
8587 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
8588 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
8589 ins_pipe(floadF_mem); | |
8590 %} | |
8591 | |
8592 | |
8593 instruct convI2F_helper(regF dst, regF tmp) %{ | |
8594 effect(DEF dst, USE tmp); | |
8595 format %{ "FITOS $tmp,$dst" %} | |
8596 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
8597 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
8598 ins_pipe(fcvtI2F); | |
8599 %} | |
8600 | |
8601 instruct convI2F_stk(regF dst, stackSlotI src) %{ | |
8602 match(Set dst (ConvI2F src)); | |
8603 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8604 expand %{ | |
8605 regF tmp; | |
8606 stkI_to_regF(tmp,src); | |
8607 convI2F_helper(dst, tmp); | |
8608 %} | |
8609 %} | |
8610 | |
8611 instruct convI2F_reg(regF dst, iRegI src) %{ | |
8612 predicate(UseVIS >= 3); | |
8613 match(Set dst (ConvI2F src)); | |
8614 ins_cost(DEFAULT_COST); | |
8615 expand %{ | |
8616 regF tmp; | |
8617 MoveI2F_reg_reg(tmp, src); | |
8618 convI2F_helper(dst, tmp); | |
8619 %} | |
8620 %} | |
8621 | |
8622 instruct convI2F_mem( regF dst, memory mem ) %{ | |
8623 match(Set dst (ConvI2F (LoadI mem))); | |
8624 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8625 size(8); | |
8626 format %{ "LDF $mem,$dst\n\t" | |
8627 "FITOS $dst,$dst" %} | |
8628 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
8629 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
8630 ins_pipe(floadF_mem); | |
8631 %} | |
8632 | |
8633 | |
8634 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
8635 match(Set dst (ConvI2L src)); | |
8636 size(4); | |
8637 format %{ "SRA $src,0,$dst\t! int->long" %} | |
8638 opcode(Assembler::sra_op3, Assembler::arith_op); | |
8639 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8640 ins_pipe(ialu_reg_reg); | |
8641 %} | |
8642 | |
8643 // Zero-extend convert int to long | |
8644 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
8645 match(Set dst (AndL (ConvI2L src) mask) ); | |
8646 size(4); | |
8647 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
8648 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8649 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8650 ins_pipe(ialu_reg_reg); | |
8651 %} | |
8652 | |
8653 // Zero-extend long | |
8654 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
8655 match(Set dst (AndL src mask) ); | |
8656 size(4); | |
8657 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
8658 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8659 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8660 ins_pipe(ialu_reg_reg); | |
8661 %} | |
8662 | |
8663 | |
0 | 8664 //----------- |
8665 // Long to Double conversion using V8 opcodes. | |
8666 // Still useful because cheetah traps and becomes | |
8667 // amazingly slow for some common numbers. | |
8668 | |
8669 // Magic constant, 0x43300000 | |
8670 instruct loadConI_x43300000(iRegI dst) %{ | |
8671 effect(DEF dst); | |
8672 size(4); | |
8673 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
8674 ins_encode(SetHi22(0x43300000, dst)); | |
8675 ins_pipe(ialu_none); | |
8676 %} | |
8677 | |
8678 // Magic constant, 0x41f00000 | |
8679 instruct loadConI_x41f00000(iRegI dst) %{ | |
8680 effect(DEF dst); | |
8681 size(4); | |
8682 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
8683 ins_encode(SetHi22(0x41f00000, dst)); | |
8684 ins_pipe(ialu_none); | |
8685 %} | |
8686 | |
8687 // Construct a double from two float halves | |
8688 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
8689 effect(DEF dst, USE src1, USE src2); | |
8690 size(8); | |
8691 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
8692 "FMOVS $src2.lo,$dst.lo" %} | |
8693 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
8694 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
8695 ins_pipe(faddD_reg_reg); | |
8696 %} | |
8697 | |
8698 // Convert integer in high half of a double register (in the lower half of | |
8699 // the double register file) to double | |
8700 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
8701 effect(DEF dst, USE src); | |
8702 size(4); | |
8703 format %{ "FITOD $src,$dst" %} | |
8704 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
8705 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
8706 ins_pipe(fcvtLHi2D); | |
8707 %} | |
8708 | |
8709 // Add float double precision | |
8710 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8711 effect(DEF dst, USE src1, USE src2); | |
8712 size(4); | |
8713 format %{ "FADDD $src1,$src2,$dst" %} | |
8714 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
8715 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8716 ins_pipe(faddD_reg_reg); | |
8717 %} | |
8718 | |
8719 // Sub float double precision | |
8720 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8721 effect(DEF dst, USE src1, USE src2); | |
8722 size(4); | |
8723 format %{ "FSUBD $src1,$src2,$dst" %} | |
8724 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
8725 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8726 ins_pipe(faddD_reg_reg); | |
8727 %} | |
8728 | |
8729 // Mul float double precision | |
8730 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8731 effect(DEF dst, USE src1, USE src2); | |
8732 size(4); | |
8733 format %{ "FMULD $src1,$src2,$dst" %} | |
8734 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
8735 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8736 ins_pipe(fmulD_reg_reg); | |
8737 %} | |
8738 | |
8739 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
8740 match(Set dst (ConvL2D src)); | |
8741 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
8742 | |
8743 expand %{ | |
8744 regD_low tmpsrc; | |
8745 iRegI ix43300000; | |
8746 iRegI ix41f00000; | |
8747 stackSlotL lx43300000; | |
8748 stackSlotL lx41f00000; | |
8749 regD_low dx43300000; | |
8750 regD dx41f00000; | |
8751 regD tmp1; | |
8752 regD_low tmp2; | |
8753 regD tmp3; | |
8754 regD tmp4; | |
8755 | |
8756 stkL_to_regD(tmpsrc, src); | |
8757 | |
8758 loadConI_x43300000(ix43300000); | |
8759 loadConI_x41f00000(ix41f00000); | |
8760 regI_to_stkLHi(lx43300000, ix43300000); | |
8761 regI_to_stkLHi(lx41f00000, ix41f00000); | |
8762 stkL_to_regD(dx43300000, lx43300000); | |
8763 stkL_to_regD(dx41f00000, lx41f00000); | |
8764 | |
8765 convI2D_regDHi_regD(tmp1, tmpsrc); | |
8766 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
8767 subD_regD_regD(tmp3, tmp2, dx43300000); | |
8768 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
8769 addD_regD_regD(dst, tmp3, tmp4); | |
8770 %} | |
8771 %} | |
8772 | |
8773 // Long to Double conversion using fast fxtof | |
8774 instruct convL2D_helper(regD dst, regD tmp) %{ | |
8775 effect(DEF dst, USE tmp); | |
8776 size(4); | |
8777 format %{ "FXTOD $tmp,$dst" %} | |
8778 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
8779 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
8780 ins_pipe(fcvtL2D); | |
8781 %} | |
8782 | |
3804 | 8783 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ |
0 | 8784 predicate(VM_Version::has_fast_fxtof()); |
8785 match(Set dst (ConvL2D src)); | |
8786 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
8787 expand %{ | |
8788 regD tmp; | |
8789 stkL_to_regD(tmp, src); | |
8790 convL2D_helper(dst, tmp); | |
8791 %} | |
8792 %} | |
8793 | |
3804 | 8794 instruct convL2D_reg(regD dst, iRegL src) %{ |
8795 predicate(UseVIS >= 3); | |
8796 match(Set dst (ConvL2D src)); | |
8797 expand %{ | |
8798 regD tmp; | |
8799 MoveL2D_reg_reg(tmp, src); | |
8800 convL2D_helper(dst, tmp); | |
8801 %} | |
8802 %} | |
0 | 8803 |
8804 // Long to Float conversion using fast fxtof | |
8805 instruct convL2F_helper(regF dst, regD tmp) %{ | |
8806 effect(DEF dst, USE tmp); | |
8807 size(4); | |
8808 format %{ "FXTOS $tmp,$dst" %} | |
8809 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
8810 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
8811 ins_pipe(fcvtL2F); | |
8812 %} | |
8813 | |
3804 | 8814 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ |
0 | 8815 match(Set dst (ConvL2F src)); |
8816 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8817 expand %{ | |
8818 regD tmp; | |
8819 stkL_to_regD(tmp, src); | |
8820 convL2F_helper(dst, tmp); | |
8821 %} | |
8822 %} | |
3804 | 8823 |
8824 instruct convL2F_reg(regF dst, iRegL src) %{ | |
8825 predicate(UseVIS >= 3); | |
8826 match(Set dst (ConvL2F src)); | |
8827 ins_cost(DEFAULT_COST); | |
8828 expand %{ | |
8829 regD tmp; | |
8830 MoveL2D_reg_reg(tmp, src); | |
8831 convL2F_helper(dst, tmp); | |
8832 %} | |
8833 %} | |
8834 | |
0 | 8835 //----------- |
8836 | |
8837 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
8838 match(Set dst (ConvL2I src)); | |
8839 #ifndef _LP64 | |
8840 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
8841 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
8842 ins_pipe(ialu_move_reg_I_to_L); | |
8843 #else | |
8844 size(4); | |
8845 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
8846 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
8847 ins_pipe(ialu_reg); | |
8848 #endif | |
8849 %} | |
8850 | |
8851 // Register Shift Right Immediate | |
8852 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
8853 match(Set dst (ConvL2I (RShiftL src cnt))); | |
8854 | |
8855 size(4); | |
8856 format %{ "SRAX $src,$cnt,$dst" %} | |
8857 opcode(Assembler::srax_op3, Assembler::arith_op); | |
8858 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
8859 ins_pipe(ialu_reg_imm); | |
8860 %} | |
8861 | |
8862 //----------Control Flow Instructions------------------------------------------ | |
8863 // Compare Instructions | |
8864 // Compare Integers | |
8865 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
8866 match(Set icc (CmpI op1 op2)); | |
8867 effect( DEF icc, USE op1, USE op2 ); | |
8868 | |
8869 size(4); | |
8870 format %{ "CMP $op1,$op2" %} | |
8871 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8872 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8873 ins_pipe(ialu_cconly_reg_reg); | |
8874 %} | |
8875 | |
8876 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
8877 match(Set icc (CmpU op1 op2)); | |
8878 | |
8879 size(4); | |
8880 format %{ "CMP $op1,$op2\t! unsigned" %} | |
8881 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8882 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8883 ins_pipe(ialu_cconly_reg_reg); | |
8884 %} | |
8885 | |
8886 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
8887 match(Set icc (CmpI op1 op2)); | |
8888 effect( DEF icc, USE op1 ); | |
8889 | |
8890 size(4); | |
8891 format %{ "CMP $op1,$op2" %} | |
8892 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8893 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8894 ins_pipe(ialu_cconly_reg_imm); | |
8895 %} | |
8896 | |
8897 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
8898 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8899 | |
8900 size(4); | |
8901 format %{ "BTST $op2,$op1" %} | |
8902 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8903 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8904 ins_pipe(ialu_cconly_reg_reg_zero); | |
8905 %} | |
8906 | |
8907 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
8908 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8909 | |
8910 size(4); | |
8911 format %{ "BTST $op2,$op1" %} | |
8912 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8913 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8914 ins_pipe(ialu_cconly_reg_imm_zero); | |
8915 %} | |
8916 | |
8917 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
8918 match(Set xcc (CmpL op1 op2)); | |
8919 effect( DEF xcc, USE op1, USE op2 ); | |
8920 | |
8921 size(4); | |
8922 format %{ "CMP $op1,$op2\t\t! long" %} | |
8923 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8924 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8925 ins_pipe(ialu_cconly_reg_reg); | |
8926 %} | |
8927 | |
8928 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
8929 match(Set xcc (CmpL op1 con)); | |
8930 effect( DEF xcc, USE op1, USE con ); | |
8931 | |
8932 size(4); | |
8933 format %{ "CMP $op1,$con\t\t! long" %} | |
8934 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8935 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
8936 ins_pipe(ialu_cconly_reg_reg); | |
8937 %} | |
8938 | |
8939 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
8940 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
8941 effect( DEF xcc, USE op1, USE op2 ); | |
8942 | |
8943 size(4); | |
8944 format %{ "BTST $op1,$op2\t\t! long" %} | |
8945 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8946 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8947 ins_pipe(ialu_cconly_reg_reg); | |
8948 %} | |
8949 | |
8950 // useful for checking the alignment of a pointer: | |
8951 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
8952 match(Set xcc (CmpL (AndL op1 con) zero)); | |
8953 effect( DEF xcc, USE op1, USE con ); | |
8954 | |
8955 size(4); | |
8956 format %{ "BTST $op1,$con\t\t! long" %} | |
8957 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8958 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
8959 ins_pipe(ialu_cconly_reg_reg); | |
8960 %} | |
8961 | |
14909 | 8962 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ |
0 | 8963 match(Set icc (CmpU op1 op2)); |
8964 | |
8965 size(4); | |
8966 format %{ "CMP $op1,$op2\t! unsigned" %} | |
8967 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8968 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8969 ins_pipe(ialu_cconly_reg_imm); | |
8970 %} | |
8971 | |
8972 // Compare Pointers | |
8973 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
8974 match(Set pcc (CmpP op1 op2)); | |
8975 | |
8976 size(4); | |
8977 format %{ "CMP $op1,$op2\t! ptr" %} | |
8978 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8979 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8980 ins_pipe(ialu_cconly_reg_reg); | |
8981 %} | |
8982 | |
8983 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
8984 match(Set pcc (CmpP op1 op2)); | |
8985 | |
8986 size(4); | |
8987 format %{ "CMP $op1,$op2\t! ptr" %} | |
8988 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8989 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8990 ins_pipe(ialu_cconly_reg_imm); | |
8991 %} | |
8992 | |
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8993 // Compare Narrow oops |
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8994 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
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8995 match(Set icc (CmpN op1 op2)); |
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8996 |
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8997 size(4); |
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8998 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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8999 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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9000 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
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9001 ins_pipe(ialu_cconly_reg_reg); |
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9002 %} |
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9003 |
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9004 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
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9005 match(Set icc (CmpN op1 op2)); |
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9006 |
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9007 size(4); |
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9008 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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9009 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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9010 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
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9011 ins_pipe(ialu_cconly_reg_imm); |
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9012 %} |
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9013 |
0 | 9014 //----------Max and Min-------------------------------------------------------- |
9015 // Min Instructions | |
9016 // Conditional move for min | |
9017 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
9018 effect( USE_DEF op2, USE op1, USE icc ); | |
9019 | |
9020 size(4); | |
9021 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
9022 opcode(Assembler::less); | |
9023 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
9024 ins_pipe(ialu_reg_flags); | |
9025 %} | |
9026 | |
9027 // Min Register with Register. | |
9028 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
9029 match(Set op2 (MinI op1 op2)); | |
9030 ins_cost(DEFAULT_COST*2); | |
9031 expand %{ | |
9032 flagsReg icc; | |
9033 compI_iReg(icc,op1,op2); | |
9034 cmovI_reg_lt(op2,op1,icc); | |
9035 %} | |
9036 %} | |
9037 | |
9038 // Max Instructions | |
9039 // Conditional move for max | |
9040 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
9041 effect( USE_DEF op2, USE op1, USE icc ); | |
9042 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
9043 opcode(Assembler::greater); | |
9044 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
9045 ins_pipe(ialu_reg_flags); | |
9046 %} | |
9047 | |
9048 // Max Register with Register | |
9049 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
9050 match(Set op2 (MaxI op1 op2)); | |
9051 ins_cost(DEFAULT_COST*2); | |
9052 expand %{ | |
9053 flagsReg icc; | |
9054 compI_iReg(icc,op1,op2); | |
9055 cmovI_reg_gt(op2,op1,icc); | |
9056 %} | |
9057 %} | |
9058 | |
9059 | |
9060 //----------Float Compares---------------------------------------------------- | |
9061 // Compare floating, generate condition code | |
9062 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
9063 match(Set fcc (CmpF src1 src2)); | |
9064 | |
9065 size(4); | |
9066 format %{ "FCMPs $fcc,$src1,$src2" %} | |
9067 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
9068 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
9069 ins_pipe(faddF_fcc_reg_reg_zero); | |
9070 %} | |
9071 | |
9072 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
9073 match(Set fcc (CmpD src1 src2)); | |
9074 | |
9075 size(4); | |
9076 format %{ "FCMPd $fcc,$src1,$src2" %} | |
9077 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
9078 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
9079 ins_pipe(faddD_fcc_reg_reg_zero); | |
9080 %} | |
9081 | |
9082 | |
9083 // Compare floating, generate -1,0,1 | |
9084 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
9085 match(Set dst (CmpF3 src1 src2)); | |
9086 effect(KILL fcc0); | |
9087 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
9088 format %{ "fcmpl $dst,$src1,$src2" %} | |
9089 // Primary = float | |
9090 opcode( true ); | |
9091 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
9092 ins_pipe( floating_cmp ); | |
9093 %} | |
9094 | |
9095 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
9096 match(Set dst (CmpD3 src1 src2)); | |
9097 effect(KILL fcc0); | |
9098 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
9099 format %{ "dcmpl $dst,$src1,$src2" %} | |
9100 // Primary = double (not float) | |
9101 opcode( false ); | |
9102 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
9103 ins_pipe( floating_cmp ); | |
9104 %} | |
9105 | |
9106 //----------Branches--------------------------------------------------------- | |
9107 // Jump | |
9108 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
9109 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
9110 match(Jump switch_val); | |
4776
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9111 effect(TEMP table); |
0 | 9112 |
9113 ins_cost(350); | |
9114 | |
2008 | 9115 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" |
9116 "LD [O7 + $switch_val], O7\n\t" | |
4114
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9117 "JUMP O7" %} |
2008 | 9118 ins_encode %{ |
9119 // Calculate table address into a register. | |
9120 Register table_reg; | |
9121 Register label_reg = O7; | |
4114
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9122 // If we are calculating the size of this instruction don't trust |
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9123 // zero offsets because they might change when |
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9124 // MachConstantBaseNode decides to optimize the constant table |
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9125 // base. |
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9126 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) { |
2008 | 9127 table_reg = $constanttablebase; |
9128 } else { | |
9129 table_reg = O7; | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
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9130 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); |
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9131 __ add($constanttablebase, con_offset, table_reg); |
2008 | 9132 } |
9133 | |
9134 // Jump to base address + switch value | |
9135 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); | |
9136 __ jmp(label_reg, G0); | |
9137 __ delayed()->nop(); | |
9138 %} | |
0 | 9139 ins_pipe(ialu_reg_reg); |
9140 %} | |
9141 | |
9142 // Direct Branch. Use V8 version with longer range. | |
9143 instruct branch(label labl) %{ | |
9144 match(Goto); | |
9145 effect(USE labl); | |
9146 | |
9147 size(8); | |
9148 ins_cost(BRANCH_COST); | |
9149 format %{ "BA $labl" %} | |
3839 | 9150 ins_encode %{ |
9151 Label* L = $labl$$label; | |
9152 __ ba(*L); | |
9153 __ delayed()->nop(); | |
9154 %} | |
0 | 9155 ins_pipe(br); |
9156 %} | |
9157 | |
3851 | 9158 // Direct Branch, short with no delay slot |
9159 instruct branch_short(label labl) %{ | |
9160 match(Goto); | |
9161 predicate(UseCBCond); | |
9162 effect(USE labl); | |
9163 | |
9164 size(4); | |
9165 ins_cost(BRANCH_COST); | |
9166 format %{ "BA $labl\t! short branch" %} | |
14909 | 9167 ins_encode %{ |
3851 | 9168 Label* L = $labl$$label; |
9169 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9170 __ ba_short(*L); | |
9171 %} | |
9172 ins_short_branch(1); | |
9173 ins_avoid_back_to_back(1); | |
9174 ins_pipe(cbcond_reg_imm); | |
9175 %} | |
9176 | |
0 | 9177 // Conditional Direct Branch |
9178 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
9179 match(If cmp icc); | |
9180 effect(USE labl); | |
9181 | |
9182 size(8); | |
9183 ins_cost(BRANCH_COST); | |
9184 format %{ "BP$cmp $icc,$labl" %} | |
9185 // Prim = bits 24-22, Secnd = bits 31-30 | |
9186 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9187 ins_pipe(br_cc); | |
9188 %} | |
9189 | |
9190 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9191 match(If cmp icc); | |
9192 effect(USE labl); | |
9193 | |
3851 | 9194 ins_cost(BRANCH_COST); |
0 | 9195 format %{ "BP$cmp $icc,$labl" %} |
9196 // Prim = bits 24-22, Secnd = bits 31-30 | |
9197 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9198 ins_pipe(br_cc); | |
9199 %} | |
9200 | |
9201 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
9202 match(If cmp pcc); | |
9203 effect(USE labl); | |
9204 | |
9205 size(8); | |
9206 ins_cost(BRANCH_COST); | |
9207 format %{ "BP$cmp $pcc,$labl" %} | |
3839 | 9208 ins_encode %{ |
9209 Label* L = $labl$$label; | |
9210 Assembler::Predict predict_taken = | |
9211 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9212 | |
9213 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
9214 __ delayed()->nop(); | |
9215 %} | |
0 | 9216 ins_pipe(br_cc); |
9217 %} | |
9218 | |
9219 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
9220 match(If cmp fcc); | |
9221 effect(USE labl); | |
9222 | |
9223 size(8); | |
9224 ins_cost(BRANCH_COST); | |
9225 format %{ "FBP$cmp $fcc,$labl" %} | |
3839 | 9226 ins_encode %{ |
9227 Label* L = $labl$$label; | |
9228 Assembler::Predict predict_taken = | |
9229 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9230 | |
9231 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); | |
9232 __ delayed()->nop(); | |
9233 %} | |
0 | 9234 ins_pipe(br_fcc); |
9235 %} | |
9236 | |
9237 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
9238 match(CountedLoopEnd cmp icc); | |
9239 effect(USE labl); | |
9240 | |
9241 size(8); | |
9242 ins_cost(BRANCH_COST); | |
9243 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9244 // Prim = bits 24-22, Secnd = bits 31-30 | |
9245 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9246 ins_pipe(br_cc); | |
9247 %} | |
9248 | |
9249 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9250 match(CountedLoopEnd cmp icc); | |
9251 effect(USE labl); | |
9252 | |
9253 size(8); | |
9254 ins_cost(BRANCH_COST); | |
9255 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9256 // Prim = bits 24-22, Secnd = bits 31-30 | |
9257 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9258 ins_pipe(br_cc); | |
9259 %} | |
9260 | |
3851 | 9261 // Compare and branch instructions |
9262 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9263 match(If cmp (CmpI op1 op2)); | |
9264 effect(USE labl, KILL icc); | |
9265 | |
9266 size(12); | |
9267 ins_cost(BRANCH_COST); | |
9268 format %{ "CMP $op1,$op2\t! int\n\t" | |
9269 "BP$cmp $labl" %} | |
9270 ins_encode %{ | |
9271 Label* L = $labl$$label; | |
9272 Assembler::Predict predict_taken = | |
9273 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9274 __ cmp($op1$$Register, $op2$$Register); | |
9275 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9276 __ delayed()->nop(); | |
9277 %} | |
9278 ins_pipe(cmp_br_reg_reg); | |
9279 %} | |
9280 | |
9281 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9282 match(If cmp (CmpI op1 op2)); | |
9283 effect(USE labl, KILL icc); | |
9284 | |
9285 size(12); | |
9286 ins_cost(BRANCH_COST); | |
9287 format %{ "CMP $op1,$op2\t! int\n\t" | |
9288 "BP$cmp $labl" %} | |
9289 ins_encode %{ | |
9290 Label* L = $labl$$label; | |
9291 Assembler::Predict predict_taken = | |
9292 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9293 __ cmp($op1$$Register, $op2$$constant); | |
9294 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9295 __ delayed()->nop(); | |
9296 %} | |
9297 ins_pipe(cmp_br_reg_imm); | |
9298 %} | |
9299 | |
9300 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
9301 match(If cmp (CmpU op1 op2)); | |
9302 effect(USE labl, KILL icc); | |
9303 | |
9304 size(12); | |
9305 ins_cost(BRANCH_COST); | |
9306 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
9307 "BP$cmp $labl" %} | |
9308 ins_encode %{ | |
9309 Label* L = $labl$$label; | |
9310 Assembler::Predict predict_taken = | |
9311 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9312 __ cmp($op1$$Register, $op2$$Register); | |
9313 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9314 __ delayed()->nop(); | |
9315 %} | |
9316 ins_pipe(cmp_br_reg_reg); | |
9317 %} | |
9318 | |
9319 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
9320 match(If cmp (CmpU op1 op2)); | |
9321 effect(USE labl, KILL icc); | |
9322 | |
9323 size(12); | |
9324 ins_cost(BRANCH_COST); | |
9325 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
9326 "BP$cmp $labl" %} | |
9327 ins_encode %{ | |
9328 Label* L = $labl$$label; | |
9329 Assembler::Predict predict_taken = | |
9330 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9331 __ cmp($op1$$Register, $op2$$constant); | |
9332 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9333 __ delayed()->nop(); | |
9334 %} | |
9335 ins_pipe(cmp_br_reg_imm); | |
9336 %} | |
9337 | |
9338 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
9339 match(If cmp (CmpL op1 op2)); | |
9340 effect(USE labl, KILL xcc); | |
9341 | |
9342 size(12); | |
9343 ins_cost(BRANCH_COST); | |
9344 format %{ "CMP $op1,$op2\t! long\n\t" | |
9345 "BP$cmp $labl" %} | |
9346 ins_encode %{ | |
9347 Label* L = $labl$$label; | |
9348 Assembler::Predict predict_taken = | |
9349 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9350 __ cmp($op1$$Register, $op2$$Register); | |
9351 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
9352 __ delayed()->nop(); | |
9353 %} | |
9354 ins_pipe(cmp_br_reg_reg); | |
9355 %} | |
9356 | |
9357 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
9358 match(If cmp (CmpL op1 op2)); | |
9359 effect(USE labl, KILL xcc); | |
9360 | |
9361 size(12); | |
9362 ins_cost(BRANCH_COST); | |
9363 format %{ "CMP $op1,$op2\t! long\n\t" | |
9364 "BP$cmp $labl" %} | |
9365 ins_encode %{ | |
9366 Label* L = $labl$$label; | |
9367 Assembler::Predict predict_taken = | |
9368 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9369 __ cmp($op1$$Register, $op2$$constant); | |
9370 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
9371 __ delayed()->nop(); | |
9372 %} | |
9373 ins_pipe(cmp_br_reg_imm); | |
9374 %} | |
9375 | |
9376 // Compare Pointers and branch | |
9377 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
9378 match(If cmp (CmpP op1 op2)); | |
9379 effect(USE labl, KILL pcc); | |
9380 | |
9381 size(12); | |
9382 ins_cost(BRANCH_COST); | |
9383 format %{ "CMP $op1,$op2\t! ptr\n\t" | |
9384 "B$cmp $labl" %} | |
9385 ins_encode %{ | |
9386 Label* L = $labl$$label; | |
9387 Assembler::Predict predict_taken = | |
9388 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9389 __ cmp($op1$$Register, $op2$$Register); | |
9390 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
9391 __ delayed()->nop(); | |
9392 %} | |
9393 ins_pipe(cmp_br_reg_reg); | |
9394 %} | |
9395 | |
9396 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
9397 match(If cmp (CmpP op1 null)); | |
9398 effect(USE labl, KILL pcc); | |
9399 | |
9400 size(12); | |
9401 ins_cost(BRANCH_COST); | |
9402 format %{ "CMP $op1,0\t! ptr\n\t" | |
9403 "B$cmp $labl" %} | |
9404 ins_encode %{ | |
9405 Label* L = $labl$$label; | |
9406 Assembler::Predict predict_taken = | |
9407 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9408 __ cmp($op1$$Register, G0); | |
9409 // bpr() is not used here since it has shorter distance. | |
9410 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
9411 __ delayed()->nop(); | |
9412 %} | |
9413 ins_pipe(cmp_br_reg_reg); | |
9414 %} | |
9415 | |
9416 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
9417 match(If cmp (CmpN op1 op2)); | |
9418 effect(USE labl, KILL icc); | |
9419 | |
9420 size(12); | |
9421 ins_cost(BRANCH_COST); | |
9422 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" | |
9423 "BP$cmp $labl" %} | |
9424 ins_encode %{ | |
9425 Label* L = $labl$$label; | |
9426 Assembler::Predict predict_taken = | |
9427 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9428 __ cmp($op1$$Register, $op2$$Register); | |
9429 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9430 __ delayed()->nop(); | |
9431 %} | |
9432 ins_pipe(cmp_br_reg_reg); | |
9433 %} | |
9434 | |
9435 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
9436 match(If cmp (CmpN op1 null)); | |
9437 effect(USE labl, KILL icc); | |
9438 | |
9439 size(12); | |
9440 ins_cost(BRANCH_COST); | |
9441 format %{ "CMP $op1,0\t! compressed ptr\n\t" | |
9442 "BP$cmp $labl" %} | |
9443 ins_encode %{ | |
9444 Label* L = $labl$$label; | |
9445 Assembler::Predict predict_taken = | |
9446 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9447 __ cmp($op1$$Register, G0); | |
9448 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9449 __ delayed()->nop(); | |
9450 %} | |
9451 ins_pipe(cmp_br_reg_reg); | |
9452 %} | |
9453 | |
9454 // Loop back branch | |
9455 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9456 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9457 effect(USE labl, KILL icc); | |
9458 | |
9459 size(12); | |
9460 ins_cost(BRANCH_COST); | |
9461 format %{ "CMP $op1,$op2\t! int\n\t" | |
9462 "BP$cmp $labl\t! Loop end" %} | |
9463 ins_encode %{ | |
9464 Label* L = $labl$$label; | |
9465 Assembler::Predict predict_taken = | |
9466 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9467 __ cmp($op1$$Register, $op2$$Register); | |
9468 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9469 __ delayed()->nop(); | |
9470 %} | |
9471 ins_pipe(cmp_br_reg_reg); | |
9472 %} | |
9473 | |
9474 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9475 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9476 effect(USE labl, KILL icc); | |
9477 | |
9478 size(12); | |
9479 ins_cost(BRANCH_COST); | |
9480 format %{ "CMP $op1,$op2\t! int\n\t" | |
9481 "BP$cmp $labl\t! Loop end" %} | |
9482 ins_encode %{ | |
9483 Label* L = $labl$$label; | |
9484 Assembler::Predict predict_taken = | |
9485 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9486 __ cmp($op1$$Register, $op2$$constant); | |
9487 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9488 __ delayed()->nop(); | |
9489 %} | |
9490 ins_pipe(cmp_br_reg_imm); | |
9491 %} | |
9492 | |
9493 // Short compare and branch instructions | |
9494 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9495 match(If cmp (CmpI op1 op2)); | |
9496 predicate(UseCBCond); | |
9497 effect(USE labl, KILL icc); | |
9498 | |
9499 size(4); | |
9500 ins_cost(BRANCH_COST); | |
9501 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
9502 ins_encode %{ | |
9503 Label* L = $labl$$label; | |
9504 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9505 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9506 %} | |
9507 ins_short_branch(1); | |
9508 ins_avoid_back_to_back(1); | |
9509 ins_pipe(cbcond_reg_reg); | |
9510 %} | |
9511 | |
9512 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9513 match(If cmp (CmpI op1 op2)); | |
9514 predicate(UseCBCond); | |
9515 effect(USE labl, KILL icc); | |
9516 | |
9517 size(4); | |
9518 ins_cost(BRANCH_COST); | |
9519 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
9520 ins_encode %{ | |
9521 Label* L = $labl$$label; | |
9522 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9523 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
9524 %} | |
9525 ins_short_branch(1); | |
9526 ins_avoid_back_to_back(1); | |
9527 ins_pipe(cbcond_reg_imm); | |
9528 %} | |
9529 | |
9530 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
9531 match(If cmp (CmpU op1 op2)); | |
9532 predicate(UseCBCond); | |
9533 effect(USE labl, KILL icc); | |
9534 | |
9535 size(4); | |
9536 ins_cost(BRANCH_COST); | |
9537 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
9538 ins_encode %{ | |
9539 Label* L = $labl$$label; | |
9540 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9541 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9542 %} | |
9543 ins_short_branch(1); | |
9544 ins_avoid_back_to_back(1); | |
9545 ins_pipe(cbcond_reg_reg); | |
9546 %} | |
9547 | |
9548 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
9549 match(If cmp (CmpU op1 op2)); | |
9550 predicate(UseCBCond); | |
9551 effect(USE labl, KILL icc); | |
9552 | |
9553 size(4); | |
9554 ins_cost(BRANCH_COST); | |
9555 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
9556 ins_encode %{ | |
9557 Label* L = $labl$$label; | |
9558 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9559 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
9560 %} | |
9561 ins_short_branch(1); | |
9562 ins_avoid_back_to_back(1); | |
9563 ins_pipe(cbcond_reg_imm); | |
9564 %} | |
9565 | |
9566 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
9567 match(If cmp (CmpL op1 op2)); | |
9568 predicate(UseCBCond); | |
9569 effect(USE labl, KILL xcc); | |
9570 | |
9571 size(4); | |
9572 ins_cost(BRANCH_COST); | |
9573 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
9574 ins_encode %{ | |
9575 Label* L = $labl$$label; | |
9576 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9577 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); | |
9578 %} | |
9579 ins_short_branch(1); | |
9580 ins_avoid_back_to_back(1); | |
9581 ins_pipe(cbcond_reg_reg); | |
9582 %} | |
9583 | |
9584 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
9585 match(If cmp (CmpL op1 op2)); | |
9586 predicate(UseCBCond); | |
9587 effect(USE labl, KILL xcc); | |
9588 | |
9589 size(4); | |
9590 ins_cost(BRANCH_COST); | |
9591 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
9592 ins_encode %{ | |
9593 Label* L = $labl$$label; | |
9594 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9595 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); | |
9596 %} | |
9597 ins_short_branch(1); | |
9598 ins_avoid_back_to_back(1); | |
9599 ins_pipe(cbcond_reg_imm); | |
9600 %} | |
9601 | |
9602 // Compare Pointers and branch | |
9603 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
9604 match(If cmp (CmpP op1 op2)); | |
9605 predicate(UseCBCond); | |
9606 effect(USE labl, KILL pcc); | |
9607 | |
9608 size(4); | |
9609 ins_cost(BRANCH_COST); | |
9610 #ifdef _LP64 | |
9611 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} | |
9612 #else | |
9613 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %} | |
9614 #endif | |
9615 ins_encode %{ | |
9616 Label* L = $labl$$label; | |
9617 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9618 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); | |
9619 %} | |
9620 ins_short_branch(1); | |
9621 ins_avoid_back_to_back(1); | |
9622 ins_pipe(cbcond_reg_reg); | |
9623 %} | |
9624 | |
9625 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
9626 match(If cmp (CmpP op1 null)); | |
9627 predicate(UseCBCond); | |
9628 effect(USE labl, KILL pcc); | |
9629 | |
9630 size(4); | |
9631 ins_cost(BRANCH_COST); | |
9632 #ifdef _LP64 | |
9633 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} | |
9634 #else | |
9635 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %} | |
9636 #endif | |
9637 ins_encode %{ | |
9638 Label* L = $labl$$label; | |
9639 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9640 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); | |
9641 %} | |
9642 ins_short_branch(1); | |
9643 ins_avoid_back_to_back(1); | |
9644 ins_pipe(cbcond_reg_reg); | |
9645 %} | |
9646 | |
9647 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
9648 match(If cmp (CmpN op1 op2)); | |
9649 predicate(UseCBCond); | |
9650 effect(USE labl, KILL icc); | |
9651 | |
9652 size(4); | |
9653 ins_cost(BRANCH_COST); | |
9654 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %} | |
9655 ins_encode %{ | |
9656 Label* L = $labl$$label; | |
9657 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9658 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9659 %} | |
9660 ins_short_branch(1); | |
9661 ins_avoid_back_to_back(1); | |
9662 ins_pipe(cbcond_reg_reg); | |
9663 %} | |
9664 | |
9665 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
9666 match(If cmp (CmpN op1 null)); | |
9667 predicate(UseCBCond); | |
9668 effect(USE labl, KILL icc); | |
9669 | |
9670 size(4); | |
9671 ins_cost(BRANCH_COST); | |
9672 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} | |
9673 ins_encode %{ | |
9674 Label* L = $labl$$label; | |
9675 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9676 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); | |
9677 %} | |
9678 ins_short_branch(1); | |
9679 ins_avoid_back_to_back(1); | |
9680 ins_pipe(cbcond_reg_reg); | |
9681 %} | |
9682 | |
9683 // Loop back branch | |
9684 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9685 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9686 predicate(UseCBCond); | |
9687 effect(USE labl, KILL icc); | |
9688 | |
9689 size(4); | |
9690 ins_cost(BRANCH_COST); | |
9691 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
9692 ins_encode %{ | |
9693 Label* L = $labl$$label; | |
9694 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9695 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9696 %} | |
9697 ins_short_branch(1); | |
9698 ins_avoid_back_to_back(1); | |
9699 ins_pipe(cbcond_reg_reg); | |
9700 %} | |
9701 | |
9702 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9703 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9704 predicate(UseCBCond); | |
9705 effect(USE labl, KILL icc); | |
9706 | |
9707 size(4); | |
9708 ins_cost(BRANCH_COST); | |
9709 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
9710 ins_encode %{ | |
9711 Label* L = $labl$$label; | |
9712 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9713 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
9714 %} | |
9715 ins_short_branch(1); | |
9716 ins_avoid_back_to_back(1); | |
9717 ins_pipe(cbcond_reg_imm); | |
9718 %} | |
9719 | |
9720 // Branch-on-register tests all 64 bits. We assume that values | |
9721 // in 64-bit registers always remains zero or sign extended | |
9722 // unless our code munges the high bits. Interrupts can chop | |
9723 // the high order bits to zero or sign at any time. | |
9724 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
9725 match(If cmp (CmpI op1 zero)); | |
9726 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
9727 effect(USE labl); | |
9728 | |
9729 size(8); | |
9730 ins_cost(BRANCH_COST); | |
9731 format %{ "BR$cmp $op1,$labl" %} | |
9732 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
9733 ins_pipe(br_reg); | |
9734 %} | |
9735 | |
9736 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
9737 match(If cmp (CmpP op1 null)); | |
9738 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
9739 effect(USE labl); | |
9740 | |
9741 size(8); | |
9742 ins_cost(BRANCH_COST); | |
9743 format %{ "BR$cmp $op1,$labl" %} | |
9744 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
9745 ins_pipe(br_reg); | |
9746 %} | |
9747 | |
9748 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
9749 match(If cmp (CmpL op1 zero)); | |
9750 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
9751 effect(USE labl); | |
9752 | |
9753 size(8); | |
9754 ins_cost(BRANCH_COST); | |
9755 format %{ "BR$cmp $op1,$labl" %} | |
9756 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
9757 ins_pipe(br_reg); | |
9758 %} | |
9759 | |
9760 | |
0 | 9761 // ============================================================================ |
9762 // Long Compare | |
9763 // | |
9764 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
9765 // is tricky. The flavor of compare used depends on whether we are testing | |
9766 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
9767 // The GE test is the negated LT test. The LE test can be had by commuting | |
9768 // the operands (yielding a GE test) and then negating; negate again for the | |
9769 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
9770 // NE test is negated from that. | |
9771 | |
9772 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
9773 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
9774 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
9775 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
9776 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
9777 // foo match ends up with the wrong leaf. One fix is to not match both | |
9778 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
9779 // both forms beat the trinary form of long-compare and both are very useful | |
9780 // on Intel which has so few registers. | |
9781 | |
9782 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
9783 match(If cmp xcc); | |
9784 effect(USE labl); | |
9785 | |
9786 size(8); | |
9787 ins_cost(BRANCH_COST); | |
9788 format %{ "BP$cmp $xcc,$labl" %} | |
3839 | 9789 ins_encode %{ |
9790 Label* L = $labl$$label; | |
9791 Assembler::Predict predict_taken = | |
9792 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9793 | |
9794 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
9795 __ delayed()->nop(); | |
9796 %} | |
0 | 9797 ins_pipe(br_cc); |
9798 %} | |
9799 | |
9800 // Manifest a CmpL3 result in an integer register. Very painful. | |
9801 // This is the test to avoid. | |
9802 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
9803 match(Set dst (CmpL3 src1 src2) ); | |
9804 effect( KILL ccr ); | |
9805 ins_cost(6*DEFAULT_COST); | |
9806 size(24); | |
9807 format %{ "CMP $src1,$src2\t\t! long\n" | |
9808 "\tBLT,a,pn done\n" | |
9809 "\tMOV -1,$dst\t! delay slot\n" | |
9810 "\tBGT,a,pn done\n" | |
9811 "\tMOV 1,$dst\t! delay slot\n" | |
9812 "\tCLR $dst\n" | |
9813 "done:" %} | |
9814 ins_encode( cmpl_flag(src1,src2,dst) ); | |
9815 ins_pipe(cmpL_reg); | |
9816 %} | |
9817 | |
9818 // Conditional move | |
9819 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
9820 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
9821 ins_cost(150); | |
9822 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
9823 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9824 ins_pipe(ialu_reg); | |
9825 %} | |
9826 | |
9827 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
9828 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
9829 ins_cost(140); | |
9830 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
9831 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9832 ins_pipe(ialu_imm); | |
9833 %} | |
9834 | |
9835 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
9836 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
9837 ins_cost(150); | |
9838 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9839 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9840 ins_pipe(ialu_reg); | |
9841 %} | |
9842 | |
9843 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
9844 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
9845 ins_cost(140); | |
9846 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9847 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9848 ins_pipe(ialu_imm); | |
9849 %} | |
9850 | |
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9851 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
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9852 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
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9853 ins_cost(150); |
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9854 format %{ "MOV$cmp $xcc,$src,$dst" %} |
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9855 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
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9856 ins_pipe(ialu_reg); |
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9857 %} |
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9858 |
0 | 9859 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
9860 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
9861 ins_cost(150); | |
9862 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9863 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9864 ins_pipe(ialu_reg); | |
9865 %} | |
9866 | |
9867 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
9868 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
9869 ins_cost(140); | |
9870 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9871 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9872 ins_pipe(ialu_imm); | |
9873 %} | |
9874 | |
9875 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
9876 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
9877 ins_cost(150); | |
9878 opcode(0x101); | |
9879 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
9880 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9881 ins_pipe(int_conditional_float_move); | |
9882 %} | |
9883 | |
9884 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
9885 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
9886 ins_cost(150); | |
9887 opcode(0x102); | |
9888 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
9889 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9890 ins_pipe(int_conditional_float_move); | |
9891 %} | |
9892 | |
9893 // ============================================================================ | |
9894 // Safepoint Instruction | |
9895 instruct safePoint_poll(iRegP poll) %{ | |
9896 match(SafePoint poll); | |
9897 effect(USE poll); | |
9898 | |
9899 size(4); | |
9900 #ifdef _LP64 | |
9901 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
9902 #else | |
9903 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
9904 #endif | |
9905 ins_encode %{ | |
9906 __ relocate(relocInfo::poll_type); | |
9907 __ ld_ptr($poll$$Register, 0, G0); | |
9908 %} | |
9909 ins_pipe(loadPollP); | |
9910 %} | |
9911 | |
9912 // ============================================================================ | |
9913 // Call Instructions | |
9914 // Call Java Static Instruction | |
9915 instruct CallStaticJavaDirect( method meth ) %{ | |
9916 match(CallStaticJava); | |
1567 | 9917 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
0 | 9918 effect(USE meth); |
9919 | |
9920 size(8); | |
9921 ins_cost(CALL_COST); | |
9922 format %{ "CALL,static ; NOP ==> " %} | |
9923 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
9924 ins_pipe(simple_call); | |
9925 %} | |
9926 | |
1567 | 9927 // Call Java Static Instruction (method handle version) |
9928 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ | |
9929 match(CallStaticJava); | |
9930 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); | |
9931 effect(USE meth, KILL l7_mh_SP_save); | |
9932 | |
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9933 size(16); |
1567 | 9934 ins_cost(CALL_COST); |
9935 format %{ "CALL,static/MethodHandle" %} | |
9936 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); | |
9937 ins_pipe(simple_call); | |
9938 %} | |
9939 | |
0 | 9940 // Call Java Dynamic Instruction |
9941 instruct CallDynamicJavaDirect( method meth ) %{ | |
9942 match(CallDynamicJava); | |
9943 effect(USE meth); | |
9944 | |
9945 ins_cost(CALL_COST); | |
9946 format %{ "SET (empty),R_G5\n\t" | |
9947 "CALL,dynamic ; NOP ==> " %} | |
9948 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
9949 ins_pipe(call); | |
9950 %} | |
9951 | |
9952 // Call Runtime Instruction | |
9953 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
9954 match(CallRuntime); | |
9955 effect(USE meth, KILL l7); | |
9956 ins_cost(CALL_COST); | |
9957 format %{ "CALL,runtime" %} | |
9958 ins_encode( Java_To_Runtime( meth ), | |
9959 call_epilog, adjust_long_from_native_call ); | |
9960 ins_pipe(simple_call); | |
9961 %} | |
9962 | |
9963 // Call runtime without safepoint - same as CallRuntime | |
9964 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
9965 match(CallLeaf); | |
9966 effect(USE meth, KILL l7); | |
9967 ins_cost(CALL_COST); | |
9968 format %{ "CALL,runtime leaf" %} | |
9969 ins_encode( Java_To_Runtime( meth ), | |
9970 call_epilog, | |
9971 adjust_long_from_native_call ); | |
9972 ins_pipe(simple_call); | |
9973 %} | |
9974 | |
9975 // Call runtime without safepoint - same as CallLeaf | |
9976 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
9977 match(CallLeafNoFP); | |
9978 effect(USE meth, KILL l7); | |
9979 ins_cost(CALL_COST); | |
9980 format %{ "CALL,runtime leaf nofp" %} | |
9981 ins_encode( Java_To_Runtime( meth ), | |
9982 call_epilog, | |
9983 adjust_long_from_native_call ); | |
9984 ins_pipe(simple_call); | |
9985 %} | |
9986 | |
9987 // Tail Call; Jump from runtime stub to Java code. | |
9988 // Also known as an 'interprocedural jump'. | |
9989 // Target of jump will eventually return to caller. | |
9990 // TailJump below removes the return address. | |
9991 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
9992 match(TailCall jump_target method_oop ); | |
9993 | |
9994 ins_cost(CALL_COST); | |
9995 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
9996 ins_encode(form_jmpl(jump_target)); | |
9997 ins_pipe(tail_call); | |
9998 %} | |
9999 | |
10000 | |
10001 // Return Instruction | |
10002 instruct Ret() %{ | |
10003 match(Return); | |
10004 | |
10005 // The epilogue node did the ret already. | |
10006 size(0); | |
10007 format %{ "! return" %} | |
10008 ins_encode(); | |
10009 ins_pipe(empty); | |
10010 %} | |
10011 | |
10012 | |
10013 // Tail Jump; remove the return address; jump to target. | |
10014 // TailCall above leaves the return address around. | |
10015 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
10016 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
10017 // "restore" before this instruction (in Epilogue), we need to materialize it | |
10018 // in %i0. | |
10019 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
10020 match( TailJump jump_target ex_oop ); | |
10021 ins_cost(CALL_COST); | |
10022 format %{ "! discard R_O7\n\t" | |
10023 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
10024 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
10025 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
10026 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
10027 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
10028 ins_pipe(tail_call); | |
10029 %} | |
10030 | |
10031 // Create exception oop: created by stack-crawling runtime code. | |
10032 // Created exception is now available to this handler, and is setup | |
10033 // just prior to jumping to this handler. No code emitted. | |
10034 instruct CreateException( o0RegP ex_oop ) | |
10035 %{ | |
10036 match(Set ex_oop (CreateEx)); | |
10037 ins_cost(0); | |
10038 | |
10039 size(0); | |
10040 // use the following format syntax | |
10041 format %{ "! exception oop is in R_O0; no code emitted" %} | |
10042 ins_encode(); | |
10043 ins_pipe(empty); | |
10044 %} | |
10045 | |
10046 | |
10047 // Rethrow exception: | |
10048 // The exception oop will come in the first argument position. | |
10049 // Then JUMP (not call) to the rethrow stub code. | |
10050 instruct RethrowException() | |
10051 %{ | |
10052 match(Rethrow); | |
10053 ins_cost(CALL_COST); | |
10054 | |
10055 // use the following format syntax | |
10056 format %{ "Jmp rethrow_stub" %} | |
10057 ins_encode(enc_rethrow); | |
10058 ins_pipe(tail_call); | |
10059 %} | |
10060 | |
10061 | |
10062 // Die now | |
10063 instruct ShouldNotReachHere( ) | |
10064 %{ | |
10065 match(Halt); | |
10066 ins_cost(CALL_COST); | |
10067 | |
10068 size(4); | |
10069 // Use the following format syntax | |
10070 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
10071 ins_encode( form2_illtrap() ); | |
10072 ins_pipe(tail_call); | |
10073 %} | |
10074 | |
10075 // ============================================================================ | |
10076 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
10077 // array for an instance of the superklass. Set a hidden internal cache on a | |
10078 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
10079 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
10080 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
10081 match(Set index (PartialSubtypeCheck sub super)); | |
10082 effect( KILL pcc, KILL o7 ); | |
10083 ins_cost(DEFAULT_COST*10); | |
10084 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
10085 ins_encode( enc_PartialSubtypeCheck() ); | |
10086 ins_pipe(partial_subtype_check_pipe); | |
10087 %} | |
10088 | |
10089 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
10090 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
10091 effect( KILL idx, KILL o7 ); | |
10092 ins_cost(DEFAULT_COST*10); | |
10093 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
10094 ins_encode( enc_PartialSubtypeCheck() ); | |
10095 ins_pipe(partial_subtype_check_pipe); | |
10096 %} | |
10097 | |
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10098 |
0 | 10099 // ============================================================================ |
10100 // inlined locking and unlocking | |
10101 | |
4777 | 10102 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ |
0 | 10103 match(Set pcc (FastLock object box)); |
10104 | |
4777 | 10105 effect(TEMP scratch2, USE_KILL box, KILL scratch); |
0 | 10106 ins_cost(100); |
10107 | |
4777 | 10108 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} |
0 | 10109 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); |
10110 ins_pipe(long_memory_op); | |
10111 %} | |
10112 | |
10113 | |
4777 | 10114 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ |
0 | 10115 match(Set pcc (FastUnlock object box)); |
4777 | 10116 effect(TEMP scratch2, USE_KILL box, KILL scratch); |
0 | 10117 ins_cost(100); |
10118 | |
4777 | 10119 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} |
0 | 10120 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); |
10121 ins_pipe(long_memory_op); | |
10122 %} | |
10123 | |
3892 | 10124 // The encodings are generic. |
0 | 10125 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ |
3892 | 10126 predicate(!use_block_zeroing(n->in(2)) ); |
0 | 10127 match(Set dummy (ClearArray cnt base)); |
10128 effect(TEMP temp, KILL ccr); | |
10129 ins_cost(300); | |
10130 format %{ "MOV $cnt,$temp\n" | |
10131 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
10132 " BRge loop\t\t! Clearing loop\n" | |
10133 " STX G0,[$base+$temp]\t! delay slot" %} | |
3892 | 10134 |
10135 ins_encode %{ | |
10136 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
10137 Register nof_bytes_arg = $cnt$$Register; | |
10138 Register nof_bytes_tmp = $temp$$Register; | |
10139 Register base_pointer_arg = $base$$Register; | |
10140 | |
10141 Label loop; | |
10142 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
10143 | |
10144 // Loop and clear, walking backwards through the array. | |
10145 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
10146 __ bind(loop); | |
10147 __ deccc(nof_bytes_tmp, 8); | |
10148 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
10149 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
10150 // %%%% this mini-loop must not cross a cache boundary! | |
10151 %} | |
10152 ins_pipe(long_memory_op); | |
10153 %} | |
10154 | |
10155 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{ | |
10156 predicate(use_block_zeroing(n->in(2))); | |
10157 match(Set dummy (ClearArray cnt base)); | |
10158 effect(USE_KILL cnt, USE_KILL base, KILL ccr); | |
10159 ins_cost(300); | |
10160 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} | |
10161 | |
10162 ins_encode %{ | |
10163 | |
10164 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); | |
10165 Register to = $base$$Register; | |
10166 Register count = $cnt$$Register; | |
10167 | |
10168 Label Ldone; | |
10169 __ nop(); // Separate short branches | |
10170 // Use BIS for zeroing (temp is not used). | |
10171 __ bis_zeroing(to, count, G0, Ldone); | |
10172 __ bind(Ldone); | |
10173 | |
10174 %} | |
10175 ins_pipe(long_memory_op); | |
10176 %} | |
10177 | |
10178 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{ | |
10179 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit)); | |
10180 match(Set dummy (ClearArray cnt base)); | |
10181 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr); | |
10182 ins_cost(300); | |
10183 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} | |
10184 | |
10185 ins_encode %{ | |
10186 | |
10187 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); | |
10188 Register to = $base$$Register; | |
10189 Register count = $cnt$$Register; | |
10190 Register temp = $tmp$$Register; | |
10191 | |
10192 Label Ldone; | |
10193 __ nop(); // Separate short branches | |
10194 // Use BIS for zeroing | |
10195 __ bis_zeroing(to, count, temp, Ldone); | |
10196 __ bind(Ldone); | |
10197 | |
10198 %} | |
0 | 10199 ins_pipe(long_memory_op); |
10200 %} | |
10201 | |
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10202 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
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10203 o7RegI tmp, flagsReg ccr) %{ |
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10204 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
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10205 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
0 | 10206 ins_cost(300); |
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10207 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
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10208 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
0 | 10209 ins_pipe(long_memory_op); |
10210 %} | |
10211 | |
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10212 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
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10213 o7RegI tmp, flagsReg ccr) %{ |
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10214 match(Set result (StrEquals (Binary str1 str2) cnt)); |
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10215 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
681 | 10216 ins_cost(300); |
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10217 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
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10218 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
681 | 10219 ins_pipe(long_memory_op); |
10220 %} | |
10221 | |
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10222 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
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10223 o7RegI tmp2, flagsReg ccr) %{ |
681 | 10224 match(Set result (AryEq ary1 ary2)); |
10225 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
10226 ins_cost(300); | |
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10227 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
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10228 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
681 | 10229 ins_pipe(long_memory_op); |
10230 %} | |
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10231 |
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10232 |
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10233 //---------- Zeros Count Instructions ------------------------------------------ |
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10234 |
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10235 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
775
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10236 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
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10237 match(Set dst (CountLeadingZerosI src)); |
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10238 effect(TEMP dst, TEMP tmp, KILL cr); |
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10239 |
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10240 // x |= (x >> 1); |
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10241 // x |= (x >> 2); |
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10242 // x |= (x >> 4); |
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10243 // x |= (x >> 8); |
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10244 // x |= (x >> 16); |
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10245 // return (WORDBITS - popc(x)); |
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10246 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
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10247 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
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10248 "OR $dst,$tmp,$dst\n\t" |
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10249 "SRL $dst,2,$tmp\n\t" |
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10250 "OR $dst,$tmp,$dst\n\t" |
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10251 "SRL $dst,4,$tmp\n\t" |
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10252 "OR $dst,$tmp,$dst\n\t" |
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10253 "SRL $dst,8,$tmp\n\t" |
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10254 "OR $dst,$tmp,$dst\n\t" |
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changeset
|
10255 "SRL $dst,16,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10256 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10257 "POPC $dst,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10258 "MOV 32,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10259 "SUB $tmp,$dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10260 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10261 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10262 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10263 Register Rtmp = $tmp$$Register; |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10264 __ srl(Rsrc, 1, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10265 __ srl(Rsrc, 0, Rdst); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10266 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10267 __ srl(Rdst, 2, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10268 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10269 __ srl(Rdst, 4, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10270 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10271 __ srl(Rdst, 8, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10272 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10273 __ srl(Rdst, 16, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10274 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10275 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10276 __ mov(BitsPerInt, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10277 __ sub(Rtmp, Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10278 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10279 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10280 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10281 |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10282 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10283 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10284 match(Set dst (CountLeadingZerosL src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10285 effect(TEMP dst, TEMP tmp, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10286 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10287 // x |= (x >> 1); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10288 // x |= (x >> 2); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10289 // x |= (x >> 4); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10290 // x |= (x >> 8); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10291 // x |= (x >> 16); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10292 // x |= (x >> 32); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10293 // return (WORDBITS - popc(x)); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10294 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10295 "OR $src,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10296 "SRLX $dst,2,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10297 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10298 "SRLX $dst,4,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10299 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10300 "SRLX $dst,8,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10301 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10302 "SRLX $dst,16,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10303 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10304 "SRLX $dst,32,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10305 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10306 "POPC $dst,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10307 "MOV 64,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10308 "SUB $tmp,$dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10309 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10310 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10311 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10312 Register Rtmp = $tmp$$Register; |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10313 __ srlx(Rsrc, 1, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10314 __ or3( Rsrc, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10315 __ srlx(Rdst, 2, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10316 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10317 __ srlx(Rdst, 4, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10318 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10319 __ srlx(Rdst, 8, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10320 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10321 __ srlx(Rdst, 16, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10322 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10323 __ srlx(Rdst, 32, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10324 __ or3( Rdst, Rtmp, Rdst); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10325 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10326 __ mov(BitsPerLong, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10327 __ sub(Rtmp, Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10328 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10329 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10330 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10331 |
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10332 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{ |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10333 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10334 match(Set dst (CountTrailingZerosI src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10335 effect(TEMP dst, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10336 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10337 // return popc(~x & (x - 1)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10338 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10339 "ANDN $dst,$src,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10340 "SRL $dst,R_G0,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10341 "POPC $dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10342 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10343 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10344 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10345 __ sub(Rsrc, 1, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10346 __ andn(Rdst, Rsrc, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10347 __ srl(Rdst, G0, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10348 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10349 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10350 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10351 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10352 |
4003
4bac06a82bc3
7100757: The BitSet.nextSetBit() produces incorrect result in 32bit VM on Sparc
kvn
parents:
3898
diff
changeset
|
10353 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{ |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10354 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10355 match(Set dst (CountTrailingZerosL src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10356 effect(TEMP dst, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10357 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10358 // return popc(~x & (x - 1)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10359 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10360 "ANDN $dst,$src,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10361 "POPC $dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10362 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10363 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10364 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10365 __ sub(Rsrc, 1, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10366 __ andn(Rdst, Rsrc, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10367 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10368 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10369 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10370 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10371 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10372 |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10373 //---------- Population Count Instructions ------------------------------------- |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10374 |
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10375 instruct popCountI(iRegIsafe dst, iRegI src) %{ |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10376 predicate(UsePopCountInstruction); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10377 match(Set dst (PopCountI src)); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10378 |
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10379 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t" |
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10380 "POPC $dst, $dst" %} |
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10381 ins_encode %{ |
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10382 __ srl($src$$Register, G0, $dst$$Register); |
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10383 __ popc($dst$$Register, $dst$$Register); |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10384 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10385 ins_pipe(ialu_reg); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10386 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10387 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10388 // Note: Long.bitCount(long) returns an int. |
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10389 instruct popCountL(iRegIsafe dst, iRegL src) %{ |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10390 predicate(UsePopCountInstruction); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10391 match(Set dst (PopCountL src)); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10392 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10393 format %{ "POPC $src, $dst" %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10394 ins_encode %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10395 __ popc($src$$Register, $dst$$Register); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10396 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10397 ins_pipe(ialu_reg); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10398 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10399 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10400 |
0 | 10401 // ============================================================================ |
10402 //------------Bytes reverse-------------------------------------------------- | |
10403 | |
10404 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
10405 match(Set dst (ReverseBytesI src)); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10406 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10407 // Op cost is artificially doubled to make sure that load or store |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10408 // instructions are preferred over this one which requires a spill |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10409 // onto a stack slot. |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10410 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10411 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10412 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10413 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10414 __ set($src$$disp + STACK_BIAS, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10415 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10416 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10417 ins_pipe( iload_mem ); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10418 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10419 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10420 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10421 match(Set dst (ReverseBytesL src)); |
0 | 10422 |
10423 // Op cost is artificially doubled to make sure that load or store | |
10424 // instructions are preferred over this one which requires a spill | |
10425 // onto a stack slot. | |
10426 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10427 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10428 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10429 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10430 __ set($src$$disp + STACK_BIAS, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10431 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10432 %} |
0 | 10433 ins_pipe( iload_mem ); |
10434 %} | |
10435 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10436 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10437 match(Set dst (ReverseBytesUS src)); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10438 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10439 // Op cost is artificially doubled to make sure that load or store |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10440 // instructions are preferred over this one which requires a spill |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10441 // onto a stack slot. |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10442 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10443 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10444 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10445 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10446 // the value was spilled as an int so bias the load |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10447 __ set($src$$disp + STACK_BIAS + 2, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10448 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10449 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10450 ins_pipe( iload_mem ); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10451 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10452 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10453 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10454 match(Set dst (ReverseBytesS src)); |
0 | 10455 |
10456 // Op cost is artificially doubled to make sure that load or store | |
10457 // instructions are preferred over this one which requires a spill | |
10458 // onto a stack slot. | |
10459 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10460 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10461 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10462 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10463 // the value was spilled as an int so bias the load |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10464 __ set($src$$disp + STACK_BIAS + 2, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10465 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10466 %} |
0 | 10467 ins_pipe( iload_mem ); |
10468 %} | |
10469 | |
10470 // Load Integer reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10471 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ |
0 | 10472 match(Set dst (ReverseBytesI (LoadI src))); |
10473 | |
10474 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10475 size(4); |
0 | 10476 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
10477 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10478 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10479 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10480 %} |
0 | 10481 ins_pipe(iload_mem); |
10482 %} | |
10483 | |
10484 // Load Long - aligned and reversed | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10485 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ |
0 | 10486 match(Set dst (ReverseBytesL (LoadL src))); |
10487 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10488 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10489 size(4); |
0 | 10490 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
10491 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10492 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10493 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10494 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10495 ins_pipe(iload_mem); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10496 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10497 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10498 // Load unsigned short / char reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10499 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10500 match(Set dst (ReverseBytesUS (LoadUS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10501 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10502 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10503 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10504 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10505 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10506 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10507 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10508 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10509 ins_pipe(iload_mem); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10510 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10511 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10512 // Load short reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10513 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10514 match(Set dst (ReverseBytesS (LoadS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10515 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10516 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10517 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10518 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10519 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10520 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10521 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10522 %} |
0 | 10523 ins_pipe(iload_mem); |
10524 %} | |
10525 | |
10526 // Store Integer reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10527 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ |
0 | 10528 match(Set dst (StoreI dst (ReverseBytesI src))); |
10529 | |
10530 ins_cost(MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10531 size(4); |
0 | 10532 format %{ "STWA $src, $dst\t!asi=primary_little" %} |
10533 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10534 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10535 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10536 %} |
0 | 10537 ins_pipe(istore_mem_reg); |
10538 %} | |
10539 | |
10540 // Store Long reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10541 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ |
0 | 10542 match(Set dst (StoreL dst (ReverseBytesL src))); |
10543 | |
10544 ins_cost(MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10545 size(4); |
0 | 10546 format %{ "STXA $src, $dst\t!asi=primary_little" %} |
10547 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10548 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10549 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10550 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10551 ins_pipe(istore_mem_reg); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10552 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10553 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10554 // Store unsighed short/char reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10555 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10556 match(Set dst (StoreC dst (ReverseBytesUS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10557 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10558 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10559 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10560 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10561 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10562 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10563 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10564 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10565 ins_pipe(istore_mem_reg); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10566 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10567 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10568 // Store short reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10569 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10570 match(Set dst (StoreC dst (ReverseBytesS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10571 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10572 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10573 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10574 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10575 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10576 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10577 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10578 %} |
0 | 10579 ins_pipe(istore_mem_reg); |
10580 %} | |
10581 | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10582 // ====================VECTOR INSTRUCTIONS===================================== |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10583 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10584 // Load Aligned Packed values into a Double Register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10585 instruct loadV8(regD dst, memory mem) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10586 predicate(n->as_LoadVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10587 match(Set dst (LoadVector mem)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10588 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10589 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10590 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10591 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10592 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10593 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10594 ins_pipe(floadD_mem); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10595 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10596 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10597 // Store Vector in Double register to memory |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10598 instruct storeV8(memory mem, regD src) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10599 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10600 match(Set mem (StoreVector mem src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10601 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10602 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10603 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10604 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10605 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10606 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10607 ins_pipe(fstoreD_mem_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10608 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10609 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10610 // Store Zero into vector in memory |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10611 instruct storeV8B_zero(memory mem, immI0 zero) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10612 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10613 match(Set mem (StoreVector mem (ReplicateB zero))); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10614 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10615 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10616 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10617 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10618 __ stx(G0, $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10619 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10620 ins_pipe(fstoreD_mem_zero); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10621 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10622 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10623 instruct storeV4S_zero(memory mem, immI0 zero) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10624 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10625 match(Set mem (StoreVector mem (ReplicateS zero))); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10626 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10627 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10628 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10629 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10630 __ stx(G0, $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10631 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10632 ins_pipe(fstoreD_mem_zero); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10633 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10634 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10635 instruct storeV2I_zero(memory mem, immI0 zero) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10636 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10637 match(Set mem (StoreVector mem (ReplicateI zero))); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10638 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10639 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10640 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10641 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10642 __ stx(G0, $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10643 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10644 ins_pipe(fstoreD_mem_zero); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10645 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10646 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10647 instruct storeV2F_zero(memory mem, immF0 zero) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10648 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10649 match(Set mem (StoreVector mem (ReplicateF zero))); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10650 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10651 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10652 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10653 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10654 __ stx(G0, $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10655 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10656 ins_pipe(fstoreD_mem_zero); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10657 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10658 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10659 // Replicate scalar to packed byte values into Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10660 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10661 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10662 match(Set dst (ReplicateB src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10663 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10664 format %{ "SLLX $src,56,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10665 "SRLX $tmp, 8,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10666 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10667 "SRLX $tmp,16,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10668 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10669 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10670 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10671 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10672 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10673 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10674 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10675 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10676 __ sllx(Rsrc, 56, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10677 __ srlx(Rtmp, 8, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10678 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10679 __ srlx(Rtmp, 16, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10680 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10681 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10682 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10683 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10684 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10685 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10686 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10687 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10688 // Replicate scalar to packed byte values into Double stack |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10689 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10690 predicate(n->as_Vector()->length() == 8 && UseVIS < 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10691 match(Set dst (ReplicateB src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10692 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10693 format %{ "SLLX $src,56,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10694 "SRLX $tmp, 8,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10695 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10696 "SRLX $tmp,16,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10697 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10698 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10699 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10700 "STX $tmp,$dst\t! regL to stkD" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10701 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10702 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10703 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10704 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10705 __ sllx(Rsrc, 56, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10706 __ srlx(Rtmp, 8, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10707 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10708 __ srlx(Rtmp, 16, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10709 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10710 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10711 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10712 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10713 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10714 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10715 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10716 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10717 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10718 // Replicate scalar constant to packed byte values in Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10719 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10720 predicate(n->as_Vector()->length() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10721 match(Set dst (ReplicateB con)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10722 effect(KILL tmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10723 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10724 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10725 // XXX This is a quick fix for 6833573. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10726 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10727 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10728 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10729 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10730 ins_pipe(loadConFD); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10731 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10732 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10733 // Replicate scalar to packed char/short values into Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10734 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10735 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10736 match(Set dst (ReplicateS src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10737 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10738 format %{ "SLLX $src,48,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10739 "SRLX $tmp,16,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10740 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10741 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10742 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10743 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10744 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10745 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10746 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10747 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10748 __ sllx(Rsrc, 48, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10749 __ srlx(Rtmp, 16, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10750 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10751 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10752 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10753 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10754 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10755 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10756 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10757 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10758 // Replicate scalar to packed char/short values into Double stack |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10759 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10760 predicate(n->as_Vector()->length() == 4 && UseVIS < 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10761 match(Set dst (ReplicateS src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10762 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10763 format %{ "SLLX $src,48,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10764 "SRLX $tmp,16,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10765 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10766 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10767 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10768 "STX $tmp,$dst\t! regL to stkD" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10769 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10770 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10771 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10772 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10773 __ sllx(Rsrc, 48, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10774 __ srlx(Rtmp, 16, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10775 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10776 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10777 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10778 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10779 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10780 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10781 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10782 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10783 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10784 // Replicate scalar constant to packed char/short values in Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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10785 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ |
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10786 predicate(n->as_Vector()->length() == 4); |
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10787 match(Set dst (ReplicateS con)); |
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10788 effect(KILL tmp); |
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10789 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} |
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10790 ins_encode %{ |
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10791 // XXX This is a quick fix for 6833573. |
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10792 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); |
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10793 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); |
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10794 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
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10795 %} |
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10796 ins_pipe(loadConFD); |
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10797 %} |
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10798 |
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10799 // Replicate scalar to packed int values into Double register |
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10800 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
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10801 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3); |
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10802 match(Set dst (ReplicateI src)); |
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10803 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
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10804 format %{ "SLLX $src,32,$tmp\n\t" |
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10805 "SRLX $tmp,32,$tmp2\n\t" |
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10806 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" |
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10807 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
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10808 ins_encode %{ |
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10809 Register Rsrc = $src$$Register; |
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10810 Register Rtmp = $tmp$$Register; |
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10811 Register Rtmp2 = $tmp2$$Register; |
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10812 __ sllx(Rsrc, 32, Rtmp); |
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10813 __ srlx(Rtmp, 32, Rtmp2); |
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10814 __ or3 (Rtmp, Rtmp2, Rtmp); |
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10815 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
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10816 %} |
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10817 ins_pipe(ialu_reg); |
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|
10818 %} |
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10819 |
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10820 // Replicate scalar to packed int values into Double stack |
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10821 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
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10822 predicate(n->as_Vector()->length() == 2 && UseVIS < 3); |
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10823 match(Set dst (ReplicateI src)); |
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10824 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
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10825 format %{ "SLLX $src,32,$tmp\n\t" |
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10826 "SRLX $tmp,32,$tmp2\n\t" |
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10827 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" |
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10828 "STX $tmp,$dst\t! regL to stkD" %} |
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10829 ins_encode %{ |
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10830 Register Rsrc = $src$$Register; |
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10831 Register Rtmp = $tmp$$Register; |
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10832 Register Rtmp2 = $tmp2$$Register; |
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10833 __ sllx(Rsrc, 32, Rtmp); |
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10834 __ srlx(Rtmp, 32, Rtmp2); |
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10835 __ or3 (Rtmp, Rtmp2, Rtmp); |
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10836 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
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10837 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
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|
10838 %} |
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|
10839 ins_pipe(ialu_reg); |
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|
10840 %} |
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|
10841 |
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|
10842 // Replicate scalar zero constant to packed int values in Double register |
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10843 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ |
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10844 predicate(n->as_Vector()->length() == 2); |
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|
10845 match(Set dst (ReplicateI con)); |
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|
10846 effect(KILL tmp); |
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|
10847 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} |
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|
10848 ins_encode %{ |
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|
10849 // XXX This is a quick fix for 6833573. |
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10850 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); |
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|
10851 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); |
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10852 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
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|
10853 %} |
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|
10854 ins_pipe(loadConFD); |
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|
10855 %} |
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|
10856 |
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|
10857 // Replicate scalar to packed float values into Double stack |
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|
10858 instruct Repl2F_stk(stackSlotD dst, regF src) %{ |
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|
10859 predicate(n->as_Vector()->length() == 2); |
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|
10860 match(Set dst (ReplicateF src)); |
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|
10861 ins_cost(MEMORY_REF_COST*2); |
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|
10862 format %{ "STF $src,$dst.hi\t! packed2F\n\t" |
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|
10863 "STF $src,$dst.lo" %} |
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|
10864 opcode(Assembler::stf_op3); |
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|
10865 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src)); |
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|
10866 ins_pipe(fstoreF_stk_reg); |
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|
10867 %} |
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|
10868 |
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changeset
|
10869 // Replicate scalar zero constant to packed float values in Double register |
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|
10870 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{ |
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|
10871 predicate(n->as_Vector()->length() == 2); |
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|
10872 match(Set dst (ReplicateF con)); |
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|
10873 effect(KILL tmp); |
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|
10874 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %} |
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|
10875 ins_encode %{ |
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|
10876 // XXX This is a quick fix for 6833573. |
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|
10877 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister); |
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|
10878 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register); |
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|
10879 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
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|
10880 %} |
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|
10881 ins_pipe(loadConFD); |
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|
10882 %} |
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|
10883 |
0 | 10884 //----------PEEPHOLE RULES----------------------------------------------------- |
10885 // These must follow all instruction definitions as they use the names | |
10886 // defined in the instructions definitions. | |
10887 // | |
605 | 10888 // peepmatch ( root_instr_name [preceding_instruction]* ); |
0 | 10889 // |
10890 // peepconstraint %{ | |
10891 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
10892 // [, ...] ); | |
10893 // // instruction numbers are zero-based using left to right order in peepmatch | |
10894 // | |
10895 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
10896 // // provide an instruction_number.operand_name for each operand that appears | |
10897 // // in the replacement instruction's match rule | |
10898 // | |
10899 // ---------VM FLAGS--------------------------------------------------------- | |
10900 // | |
10901 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
10902 // | |
10903 // Each peephole rule is given an identifying number starting with zero and | |
10904 // increasing by one in the order seen by the parser. An individual peephole | |
10905 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
10906 // on the command-line. | |
10907 // | |
10908 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
10909 // | |
10910 // Only match adjacent instructions in same basic block | |
10911 // Only equality constraints | |
10912 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
10913 // Only one replacement instruction | |
10914 // | |
10915 // ---------EXAMPLE---------------------------------------------------------- | |
10916 // | |
10917 // // pertinent parts of existing instructions in architecture description | |
10918 // instruct movI(eRegI dst, eRegI src) %{ | |
10919 // match(Set dst (CopyI src)); | |
10920 // %} | |
10921 // | |
10922 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
10923 // match(Set dst (AddI dst src)); | |
10924 // effect(KILL cr); | |
10925 // %} | |
10926 // | |
10927 // // Change (inc mov) to lea | |
10928 // peephole %{ | |
10929 // // increment preceeded by register-register move | |
10930 // peepmatch ( incI_eReg movI ); | |
10931 // // require that the destination register of the increment | |
10932 // // match the destination register of the move | |
10933 // peepconstraint ( 0.dst == 1.dst ); | |
10934 // // construct a replacement instruction that sets | |
10935 // // the destination to ( move's source register + one ) | |
10936 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
10937 // %} | |
10938 // | |
10939 | |
10940 // // Change load of spilled value to only a spill | |
10941 // instruct storeI(memory mem, eRegI src) %{ | |
10942 // match(Set mem (StoreI mem src)); | |
10943 // %} | |
10944 // | |
10945 // instruct loadI(eRegI dst, memory mem) %{ | |
10946 // match(Set dst (LoadI mem)); | |
10947 // %} | |
10948 // | |
10949 // peephole %{ | |
10950 // peepmatch ( loadI storeI ); | |
10951 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
10952 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
10953 // %} | |
10954 | |
10955 //----------SMARTSPILL RULES--------------------------------------------------- | |
10956 // These must follow all instruction definitions as they use the names | |
10957 // defined in the instructions definitions. | |
10958 // | |
10959 // SPARC will probably not have any of these rules due to RISC instruction set. | |
10960 | |
10961 //----------PIPELINE----------------------------------------------------------- | |
10962 // Rules which define the behavior of the target architectures pipeline. |