Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sparc.ad @ 3804:faa472957b38
7059034: Use movxtod/movdtox on T4
Summary: Use new VIS3 mov instructions on T4 for move data between general and float registers.
Reviewed-by: never, twisti
| author | kvn |
|---|---|
| date | Fri, 08 Jul 2011 09:38:48 -0700 |
| parents | 7e88bdae86ec |
| children | 3d42f82cd811 |
| rev | line source |
|---|---|
| 0 | 1 // |
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2 // Copyright (c) 1998, 2011, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // SPARC Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 register %{ | |
| 32 //----------Architecture Description Register Definitions---------------------- | |
| 33 // General Registers | |
| 34 // "reg_def" name ( register save type, C convention save type, | |
| 35 // ideal register type, encoding, vm name ); | |
| 36 // Register Save Types: | |
| 37 // | |
| 38 // NS = No-Save: The register allocator assumes that these registers | |
| 39 // can be used without saving upon entry to the method, & | |
| 40 // that they do not need to be saved at call sites. | |
| 41 // | |
| 42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 43 // can be used without saving upon entry to the method, | |
| 44 // but that they must be saved at call sites. | |
| 45 // | |
| 46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 47 // must be saved before using them upon entry to the | |
| 48 // method, but they do not need to be saved at call | |
| 49 // sites. | |
| 50 // | |
| 51 // AS = Always-Save: The register allocator assumes that these registers | |
| 52 // must be saved before using them upon entry to the | |
| 53 // method, & that they must be saved at call sites. | |
| 54 // | |
| 55 // Ideal Register Type is used to determine how to save & restore a | |
| 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 58 // | |
| 59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 60 | |
| 61 | |
| 62 // ---------------------------- | |
| 63 // Integer/Long Registers | |
| 64 // ---------------------------- | |
| 65 | |
| 66 // Need to expose the hi/lo aspect of 64-bit registers | |
| 67 // This register set is used for both the 64-bit build and | |
| 68 // the 32-bit build with 1-register longs. | |
| 69 | |
| 70 // Global Registers 0-7 | |
| 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
| 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
| 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
| 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
| 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
| 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
| 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
| 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
| 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
| 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
| 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
| 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
| 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
| 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
| 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
| 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
| 87 | |
| 88 // Output Registers 0-7 | |
| 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
| 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
| 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
| 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
| 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
| 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
| 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
| 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
| 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
| 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
| 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
| 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
| 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
| 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
| 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
| 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
| 105 | |
| 106 // Local Registers 0-7 | |
| 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
| 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
| 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
| 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
| 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
| 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
| 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
| 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
| 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
| 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
| 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
| 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
| 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
| 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
| 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
| 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
| 123 | |
| 124 // Input Registers 0-7 | |
| 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
| 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
| 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
| 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
| 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
| 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
| 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
| 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
| 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
| 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
| 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
| 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
| 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
| 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
| 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
| 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
| 141 | |
| 142 // ---------------------------- | |
| 143 // Float/Double Registers | |
| 144 // ---------------------------- | |
| 145 | |
| 146 // Float Registers | |
| 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
| 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
| 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
| 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
| 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
| 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
| 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
| 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
| 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
| 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
| 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
| 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
| 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
| 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
| 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
| 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
| 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
| 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
| 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
| 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
| 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
| 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
| 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
| 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
| 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
| 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
| 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
| 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
| 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
| 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
| 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
| 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
| 179 | |
| 180 // Double Registers | |
| 181 // The rules of ADL require that double registers be defined in pairs. | |
| 182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
| 183 // single float registers. In each pair, ADLC-assigned register numbers | |
| 184 // must be adjacent, with the lower number even. Finally, when the | |
| 185 // CPU stores such a register pair to memory, the word associated with | |
| 186 // the lower ADLC-assigned number must be stored to the lower address. | |
| 187 | |
| 188 // These definitions specify the actual bit encodings of the sparc | |
| 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
| 190 // wants 0-63, so we have to convert every time we want to use fp regs | |
| 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
| 605 | 192 // 255 is a flag meaning "don't go here". |
| 0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
| 194 // the place in the sparc stack crawler that asserts on the 255 is | |
| 195 // fixed up. | |
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196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
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197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
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198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
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199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
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200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
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201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
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202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
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203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
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204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
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205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
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206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
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207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
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208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
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209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
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210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
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211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
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212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
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213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
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214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
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215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
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216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
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217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
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218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
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219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
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220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
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221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
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222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
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223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
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224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
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225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
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226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
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227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
| 0 | 228 |
| 229 | |
| 230 // ---------------------------- | |
| 231 // Special Registers | |
| 232 // Condition Codes Flag Registers | |
| 233 // I tried to break out ICC and XCC but it's not very pretty. | |
| 234 // Every Sparc instruction which defs/kills one also kills the other. | |
| 235 // Hence every compare instruction which defs one kind of flags ends | |
| 236 // up needing a kill of the other. | |
| 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 238 | |
| 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
| 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
| 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
| 243 | |
| 244 // ---------------------------- | |
| 245 // Specify the enum values for the registers. These enums are only used by the | |
| 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
| 247 // for visibility to the rest of the vm. The order of this enum influences the | |
| 248 // register allocator so having the freedom to set this order and not be stuck | |
| 249 // with the order that is natural for the rest of the vm is worth it. | |
| 250 alloc_class chunk0( | |
| 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
| 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
| 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
| 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
| 255 | |
| 256 // Note that a register is not allocatable unless it is also mentioned | |
| 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
| 258 | |
| 259 alloc_class chunk1( | |
| 260 // The first registers listed here are those most likely to be used | |
| 261 // as temporaries. We move F0..F7 away from the front of the list, | |
| 262 // to reduce the likelihood of interferences with parameters and | |
| 263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
| 264 // since they are used for return values. | |
| 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
| 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
| 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
| 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
| 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
| 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
| 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
| 274 | |
| 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
| 276 | |
| 277 //----------Architecture Description Register Classes-------------------------- | |
| 278 // Several register classes are automatically defined based upon information in | |
| 279 // this architecture description. | |
| 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
| 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
| 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 283 // | |
| 284 | |
| 285 // G0 is not included in integer class since it has special meaning. | |
| 286 reg_class g0_reg(R_G0); | |
| 287 | |
| 288 // ---------------------------- | |
| 289 // Integer Register Classes | |
| 290 // ---------------------------- | |
| 291 // Exclusions from i_reg: | |
| 292 // R_G0: hardwired zero | |
| 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
| 294 // R_G6: reserved by Solaris ABI to tools | |
| 295 // R_G7: reserved by Solaris ABI to libthread | |
| 296 // R_O7: Used as a temp in many encodings | |
| 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 298 | |
| 299 // Class for all integer registers, except the G registers. This is used for | |
| 300 // encodings which use G registers as temps. The regular inputs to such | |
| 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
| 302 // will not put an input into a temp register. | |
| 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 304 | |
| 305 reg_class g1_regI(R_G1); | |
| 306 reg_class g3_regI(R_G3); | |
| 307 reg_class g4_regI(R_G4); | |
| 308 reg_class o0_regI(R_O0); | |
| 309 reg_class o7_regI(R_O7); | |
| 310 | |
| 311 // ---------------------------- | |
| 312 // Pointer Register Classes | |
| 313 // ---------------------------- | |
| 314 #ifdef _LP64 | |
| 315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
| 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 320 // Lock encodings use G3 and G4 internally | |
| 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
| 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 326 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
| 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
| 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 332 // We use it to save R_G2 across calls out of Java. | |
| 333 reg_class l7_regP(R_L7H,R_L7); | |
| 334 | |
| 335 // Other special pointer regs | |
| 336 reg_class g1_regP(R_G1H,R_G1); | |
| 337 reg_class g2_regP(R_G2H,R_G2); | |
| 338 reg_class g3_regP(R_G3H,R_G3); | |
| 339 reg_class g4_regP(R_G4H,R_G4); | |
| 340 reg_class g5_regP(R_G5H,R_G5); | |
| 341 reg_class i0_regP(R_I0H,R_I0); | |
| 342 reg_class o0_regP(R_O0H,R_O0); | |
| 343 reg_class o1_regP(R_O1H,R_O1); | |
| 344 reg_class o2_regP(R_O2H,R_O2); | |
| 345 reg_class o7_regP(R_O7H,R_O7); | |
| 346 | |
| 347 #else // _LP64 | |
| 348 // 32-bit build means 32-bit pointers means 1 register. | |
| 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
| 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 353 // Lock encodings use G3 and G4 internally | |
| 354 reg_class lock_ptr_reg(R_G1, R_G5, | |
| 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 359 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
| 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
| 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
| 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 365 // We use it to save R_G2 across calls out of Java. | |
| 366 reg_class l7_regP(R_L7); | |
| 367 | |
| 368 // Other special pointer regs | |
| 369 reg_class g1_regP(R_G1); | |
| 370 reg_class g2_regP(R_G2); | |
| 371 reg_class g3_regP(R_G3); | |
| 372 reg_class g4_regP(R_G4); | |
| 373 reg_class g5_regP(R_G5); | |
| 374 reg_class i0_regP(R_I0); | |
| 375 reg_class o0_regP(R_O0); | |
| 376 reg_class o1_regP(R_O1); | |
| 377 reg_class o2_regP(R_O2); | |
| 378 reg_class o7_regP(R_O7); | |
| 379 #endif // _LP64 | |
| 380 | |
| 381 | |
| 382 // ---------------------------- | |
| 383 // Long Register Classes | |
| 384 // ---------------------------- | |
| 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
| 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
| 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
| 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
| 389 #ifdef _LP64 | |
| 390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
| 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
| 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
| 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
| 394 #endif // _LP64 | |
| 395 ); | |
| 396 | |
| 397 reg_class g1_regL(R_G1H,R_G1); | |
|
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398 reg_class g3_regL(R_G3H,R_G3); |
| 0 | 399 reg_class o2_regL(R_O2H,R_O2); |
| 400 reg_class o7_regL(R_O7H,R_O7); | |
| 401 | |
| 402 // ---------------------------- | |
| 403 // Special Class for Condition Code Flags Register | |
| 404 reg_class int_flags(CCR); | |
| 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
| 406 reg_class float_flag0(FCC0); | |
| 407 | |
| 408 | |
| 409 // ---------------------------- | |
| 410 // Float Point Register Classes | |
| 411 // ---------------------------- | |
| 412 // Skip F30/F31, they are reserved for mem-mem copies | |
| 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
| 414 | |
| 415 // Paired floating point registers--they show up in the same order as the floats, | |
| 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
| 419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
| 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
| 422 ); | |
| 423 | |
| 424 // Paired floating point registers--they show up in the same order as the floats, | |
| 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
| 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 3804 | 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); |
| 0 | 429 %} |
| 430 | |
| 431 //----------DEFINITION BLOCK--------------------------------------------------- | |
| 432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
| 433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
| 434 // Format: | |
| 435 // int_def <name> ( <int_value>, <expression>); | |
| 436 // Generated Code in ad_<arch>.hpp | |
| 437 // #define <name> (<expression>) | |
| 438 // // value == <int_value> | |
| 439 // Generated code in ad_<arch>.cpp adlc_verification() | |
| 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
| 441 // | |
| 442 definitions %{ | |
| 443 // The default cost (of an ALU instruction). | |
| 444 int_def DEFAULT_COST ( 100, 100); | |
| 445 int_def HUGE_COST (1000000, 1000000); | |
| 446 | |
| 447 // Memory refs are twice as expensive as run-of-the-mill. | |
| 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
| 449 | |
| 450 // Branches are even more expensive. | |
| 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
| 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
| 453 %} | |
| 454 | |
| 455 | |
| 456 //----------SOURCE BLOCK------------------------------------------------------- | |
| 457 // This is a block of C++ code which provides values, functions, and | |
| 458 // definitions necessary in the rest of the architecture description | |
| 459 source_hpp %{ | |
| 460 // Must be visible to the DFA in dfa_sparc.cpp | |
| 461 extern bool can_branch_register( Node *bol, Node *cmp ); | |
| 462 | |
| 463 // Macros to extract hi & lo halves from a long pair. | |
| 464 // G0 is not part of any long pair, so assert on that. | |
| 605 | 465 // Prevents accidentally using G1 instead of G0. |
| 0 | 466 #define LONG_HI_REG(x) (x) |
| 467 #define LONG_LO_REG(x) (x) | |
| 468 | |
| 469 %} | |
| 470 | |
| 471 source %{ | |
| 472 #define __ _masm. | |
| 473 | |
|
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474 // Block initializing store |
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475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2 |
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476 |
| 0 | 477 // tertiary op of a LoadP or StoreP encoding |
| 478 #define REGP_OP true | |
| 479 | |
| 480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
| 481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
| 482 static Register reg_to_register_object(int register_encoding); | |
| 483 | |
| 484 // Used by the DFA in dfa_sparc.cpp. | |
| 485 // Check for being able to use a V9 branch-on-register. Requires a | |
| 486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
| 487 // extended. Doesn't work following an integer ADD, for example, because of | |
| 488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
| 489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
| 490 // replace them with zero, which could become sign-extension in a different OS | |
| 491 // release. There's no obvious reason why an interrupt will ever fill these | |
| 492 // bits with non-zero junk (the registers are reloaded with standard LD | |
| 493 // instructions which either zero-fill or sign-fill). | |
| 494 bool can_branch_register( Node *bol, Node *cmp ) { | |
| 495 if( !BranchOnRegister ) return false; | |
| 496 #ifdef _LP64 | |
| 497 if( cmp->Opcode() == Op_CmpP ) | |
| 498 return true; // No problems with pointer compares | |
| 499 #endif | |
| 500 if( cmp->Opcode() == Op_CmpL ) | |
| 501 return true; // No problems with long compares | |
| 502 | |
| 503 if( !SparcV9RegsHiBitsZero ) return false; | |
| 504 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
| 505 bol->as_Bool()->_test._test != BoolTest::eq ) | |
| 506 return false; | |
| 507 | |
| 508 // Check for comparing against a 'safe' value. Any operation which | |
| 509 // clears out the high word is safe. Thus, loads and certain shifts | |
| 510 // are safe, as are non-negative constants. Any operation which | |
| 511 // preserves zero bits in the high word is safe as long as each of its | |
| 512 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
| 513 // inputs are safe. At present, the only important case to recognize | |
| 514 // seems to be loads. Constants should fold away, and shifts & | |
| 515 // logicals can use the 'cc' forms. | |
| 516 Node *x = cmp->in(1); | |
| 517 if( x->is_Load() ) return true; | |
| 518 if( x->is_Phi() ) { | |
| 519 for( uint i = 1; i < x->req(); i++ ) | |
| 520 if( !x->in(i)->is_Load() ) | |
| 521 return false; | |
| 522 return true; | |
| 523 } | |
| 524 return false; | |
| 525 } | |
| 526 | |
| 527 // **************************************************************************** | |
| 528 | |
| 529 // REQUIRED FUNCTIONALITY | |
| 530 | |
| 531 // !!!!! Special hack to get all type of calls to specify the byte offset | |
| 532 // from the start of the call to the point where the return address | |
| 533 // will point. | |
| 534 // The "return address" is the address of the call instruction, plus 8. | |
| 535 | |
| 536 int MachCallStaticJavaNode::ret_addr_offset() { | |
| 1567 | 537 int offset = NativeCall::instruction_size; // call; delay slot |
| 538 if (_method_handle_invoke) | |
| 539 offset += 4; // restore SP | |
| 540 return offset; | |
| 0 | 541 } |
| 542 | |
| 543 int MachCallDynamicJavaNode::ret_addr_offset() { | |
| 544 int vtable_index = this->_vtable_index; | |
| 545 if (vtable_index < 0) { | |
| 546 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
| 547 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
| 548 return (NativeMovConstReg::instruction_size + | |
| 549 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
| 550 } else { | |
| 551 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 552 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); | |
| 553 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
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554 int klass_load_size; |
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555 if (UseCompressedOops) { |
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556 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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557 if (Universe::narrow_oop_base() == NULL) |
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558 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() |
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559 else |
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560 klass_load_size = 3*BytesPerInstWord; |
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561 } else { |
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562 klass_load_size = 1*BytesPerInstWord; |
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563 } |
| 0 | 564 if( Assembler::is_simm13(v_off) ) { |
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565 return klass_load_size + |
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566 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
| 0 | 567 NativeCall::instruction_size); // call; delay slot |
| 568 } else { | |
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569 return klass_load_size + |
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570 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
| 0 | 571 NativeCall::instruction_size); // call; delay slot |
| 572 } | |
| 573 } | |
| 574 } | |
| 575 | |
| 576 int MachCallRuntimeNode::ret_addr_offset() { | |
| 577 #ifdef _LP64 | |
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578 if (MacroAssembler::is_far_target(entry_point())) { |
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579 return NativeFarCall::instruction_size; |
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580 } else { |
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581 return NativeCall::instruction_size; |
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582 } |
| 0 | 583 #else |
| 584 return NativeCall::instruction_size; // call; delay slot | |
| 585 #endif | |
| 586 } | |
| 587 | |
| 588 // Indicate if the safepoint node needs the polling page as an input. | |
| 589 // Since Sparc does not have absolute addressing, it does. | |
| 590 bool SafePointNode::needs_polling_address_input() { | |
| 591 return true; | |
| 592 } | |
| 593 | |
| 594 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
| 595 void emit_break(CodeBuffer &cbuf) { | |
| 596 MacroAssembler _masm(&cbuf); | |
| 597 __ breakpoint_trap(); | |
| 598 } | |
| 599 | |
| 600 #ifndef PRODUCT | |
| 601 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 602 st->print("TA"); | |
| 603 } | |
| 604 #endif | |
| 605 | |
| 606 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 607 emit_break(cbuf); | |
| 608 } | |
| 609 | |
| 610 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
| 611 return MachNode::size(ra_); | |
| 612 } | |
| 613 | |
| 614 // Traceable jump | |
| 615 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
| 616 MacroAssembler _masm(&cbuf); | |
| 617 Register rdest = reg_to_register_object(jump_target); | |
| 618 __ JMP(rdest, 0); | |
| 619 __ delayed()->nop(); | |
| 620 } | |
| 621 | |
| 622 // Traceable jump and set exception pc | |
| 623 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
| 624 MacroAssembler _masm(&cbuf); | |
| 625 Register rdest = reg_to_register_object(jump_target); | |
| 626 __ JMP(rdest, 0); | |
| 627 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
| 628 } | |
| 629 | |
| 630 void emit_nop(CodeBuffer &cbuf) { | |
| 631 MacroAssembler _masm(&cbuf); | |
| 632 __ nop(); | |
| 633 } | |
| 634 | |
| 635 void emit_illtrap(CodeBuffer &cbuf) { | |
| 636 MacroAssembler _masm(&cbuf); | |
| 637 __ illtrap(0); | |
| 638 } | |
| 639 | |
| 640 | |
| 641 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 642 assert(n->rule() != loadUB_rule, ""); | |
| 643 | |
| 644 intptr_t offset = 0; | |
| 645 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
| 646 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
| 647 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
| 648 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
| 649 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 650 atype = atype->add_offset(offset); | |
| 651 assert(disp32 == offset, "wrong disp32"); | |
| 652 return atype->_offset; | |
| 653 } | |
| 654 | |
| 655 | |
| 656 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 657 assert(n->rule() != loadUB_rule, ""); | |
| 658 | |
| 659 intptr_t offset = 0; | |
| 660 Node* addr = n->in(2); | |
| 661 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 662 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
| 663 Node* a = addr->in(2/*AddPNode::Address*/); | |
| 664 Node* o = addr->in(3/*AddPNode::Offset*/); | |
| 665 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
| 666 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
| 667 assert(atype->isa_oop_ptr(), "still an oop"); | |
| 668 } | |
| 669 offset = atype->is_ptr()->_offset; | |
| 670 if (offset != Type::OffsetBot) offset += disp32; | |
| 671 return offset; | |
| 672 } | |
| 673 | |
| 2008 | 674 static inline jdouble replicate_immI(int con, int count, int width) { |
| 675 // Load a constant replicated "count" times with width "width" | |
| 676 int bit_width = width * 8; | |
| 677 jlong elt_val = con; | |
| 678 elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits | |
| 679 jlong val = elt_val; | |
| 680 for (int i = 0; i < count - 1; i++) { | |
| 681 val <<= bit_width; | |
| 682 val |= elt_val; | |
| 683 } | |
| 684 jdouble dval = *((jdouble*) &val); // coerce to double type | |
| 685 return dval; | |
| 686 } | |
| 687 | |
| 0 | 688 // Standard Sparc opcode form2 field breakdown |
| 689 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
| 690 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
| 691 int op = (f30 << 30) | | |
| 692 (f29 << 29) | | |
| 693 (f25 << 25) | | |
| 694 (f22 << 22) | | |
| 695 (f20 << 20) | | |
| 696 (f19 << 19) | | |
| 697 (f0 << 0); | |
| 1748 | 698 cbuf.insts()->emit_int32(op); |
| 0 | 699 } |
| 700 | |
| 701 // Standard Sparc opcode form2 field breakdown | |
| 702 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
| 703 f0 >>= 10; // Drop 10 bits | |
| 704 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
| 705 int op = (f30 << 30) | | |
| 706 (f25 << 25) | | |
| 707 (f22 << 22) | | |
| 708 (f0 << 0); | |
| 1748 | 709 cbuf.insts()->emit_int32(op); |
| 0 | 710 } |
| 711 | |
| 712 // Standard Sparc opcode form3 field breakdown | |
| 713 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
| 714 int op = (f30 << 30) | | |
| 715 (f25 << 25) | | |
| 716 (f19 << 19) | | |
| 717 (f14 << 14) | | |
| 718 (f5 << 5) | | |
| 719 (f0 << 0); | |
| 1748 | 720 cbuf.insts()->emit_int32(op); |
| 0 | 721 } |
| 722 | |
| 723 // Standard Sparc opcode form3 field breakdown | |
| 724 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
| 725 simm13 &= (1<<13)-1; // Mask to 13 bits | |
| 726 int op = (f30 << 30) | | |
| 727 (f25 << 25) | | |
| 728 (f19 << 19) | | |
| 729 (f14 << 14) | | |
| 730 (1 << 13) | // bit to indicate immediate-mode | |
| 731 (simm13<<0); | |
| 1748 | 732 cbuf.insts()->emit_int32(op); |
| 0 | 733 } |
| 734 | |
| 735 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
| 736 simm10 &= (1<<10)-1; // Mask to 10 bits | |
| 737 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
| 738 } | |
| 739 | |
| 740 #ifdef ASSERT | |
| 741 // Helper function for VerifyOops in emit_form3_mem_reg | |
| 742 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
| 743 warning("VerifyOops encountered unexpected instruction:"); | |
| 744 n->dump(2); | |
| 745 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
| 746 } | |
| 747 #endif | |
| 748 | |
| 749 | |
| 750 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
| 751 int src1_enc, int disp32, int src2_enc, int dst_enc) { | |
| 752 | |
| 753 #ifdef ASSERT | |
| 754 // The following code implements the +VerifyOops feature. | |
| 755 // It verifies oop values which are loaded into or stored out of | |
| 756 // the current method activation. +VerifyOops complements techniques | |
| 757 // like ScavengeALot, because it eagerly inspects oops in transit, | |
| 758 // as they enter or leave the stack, as opposed to ScavengeALot, | |
| 759 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
| 760 // For this reason, +VerifyOops can sometimes detect bugs very close | |
| 761 // to their point of creation. It can also serve as a cross-check | |
| 762 // on the validity of oop maps, when used toegether with ScavengeALot. | |
| 763 | |
| 764 // It would be good to verify oops at other points, especially | |
| 765 // when an oop is used as a base pointer for a load or store. | |
| 766 // This is presently difficult, because it is hard to know when | |
| 767 // a base address is biased or not. (If we had such information, | |
| 768 // it would be easy and useful to make a two-argument version of | |
| 769 // verify_oop which unbiases the base, and performs verification.) | |
| 770 | |
| 771 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
| 772 bool is_verified_oop_base = false; | |
| 773 bool is_verified_oop_load = false; | |
| 774 bool is_verified_oop_store = false; | |
| 775 int tmp_enc = -1; | |
| 776 if (VerifyOops && src1_enc != R_SP_enc) { | |
| 777 // classify the op, mainly for an assert check | |
| 778 int st_op = 0, ld_op = 0; | |
| 779 switch (primary) { | |
| 780 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
| 781 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
| 782 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
| 783 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
| 784 case Assembler::std_op3: st_op = Op_StoreL; break; | |
| 785 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
| 786 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
| 787 | |
| 788 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
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789 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
| 0 | 790 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
| 791 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
| 792 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
| 793 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
| 794 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
| 795 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
| 796 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
| 797 case Assembler::ldub_op3: ld_op = Op_LoadB; break; | |
| 798 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
| 799 | |
| 800 default: ShouldNotReachHere(); | |
| 801 } | |
| 802 if (tertiary == REGP_OP) { | |
| 803 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
| 804 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
| 805 else ShouldNotReachHere(); | |
| 806 if (st_op) { | |
| 807 // a store | |
| 808 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 809 Node* n2 = n->in(3); | |
| 810 if (n2 != NULL) { | |
| 811 const Type* t = n2->bottom_type(); | |
| 812 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 813 } | |
| 814 } else { | |
| 815 // a load | |
| 816 const Type* t = n->bottom_type(); | |
| 817 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 818 } | |
| 819 } | |
| 820 | |
| 821 if (ld_op) { | |
| 822 // a Load | |
| 823 // inputs are (0:control, 1:memory, 2:address) | |
| 824 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
| 825 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && | |
| 826 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
| 827 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
| 828 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
| 829 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
| 830 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
| 831 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
| 832 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
| 833 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
| 834 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
| 835 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
| 836 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
| 837 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
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838 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) && |
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839 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) && |
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840 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) && |
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841 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) && |
| 0 | 842 !(n->rule() == loadUB_rule)) { |
| 843 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
| 844 } | |
| 845 } else if (st_op) { | |
| 846 // a Store | |
| 847 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 848 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
| 849 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
| 850 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
| 851 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
| 852 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
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853 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) && |
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854 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) && |
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855 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) && |
| 0 | 856 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { |
| 857 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
| 858 } | |
| 859 } | |
| 860 | |
| 861 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
| 862 Node* addr = n->in(2); | |
| 863 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
| 864 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
| 865 if (atype != NULL) { | |
| 866 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
| 867 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
| 868 if (offset != offset_2) { | |
| 869 get_offset_from_base(n, atype, disp32); | |
| 870 get_offset_from_base_2(n, atype, disp32); | |
| 871 } | |
| 872 assert(offset == offset_2, "different offsets"); | |
| 873 if (offset == disp32) { | |
| 874 // we now know that src1 is a true oop pointer | |
| 875 is_verified_oop_base = true; | |
| 876 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
| 877 if( primary == Assembler::ldd_op3 ) { | |
| 878 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
| 879 } else { | |
| 880 tmp_enc = dst_enc; | |
| 881 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
| 882 assert(src1_enc != dst_enc, ""); | |
| 883 } | |
| 884 } | |
| 885 } | |
| 886 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
| 887 || offset == oopDesc::mark_offset_in_bytes())) { | |
| 888 // loading the mark should not be allowed either, but | |
| 889 // we don't check this since it conflicts with InlineObjectHash | |
| 890 // usage of LoadINode to get the mark. We could keep the | |
| 891 // check if we create a new LoadMarkNode | |
| 892 // but do not verify the object before its header is initialized | |
| 893 ShouldNotReachHere(); | |
| 894 } | |
| 895 } | |
| 896 } | |
| 897 } | |
| 898 } | |
| 899 #endif | |
| 900 | |
| 901 uint instr; | |
| 902 instr = (Assembler::ldst_op << 30) | |
| 903 | (dst_enc << 25) | |
| 904 | (primary << 19) | |
| 905 | (src1_enc << 14); | |
| 906 | |
| 907 uint index = src2_enc; | |
| 908 int disp = disp32; | |
| 909 | |
| 910 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
| 911 disp += STACK_BIAS; | |
| 912 | |
| 913 // We should have a compiler bailout here rather than a guarantee. | |
| 914 // Better yet would be some mechanism to handle variable-size matches correctly. | |
| 915 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
| 916 | |
| 917 if( disp == 0 ) { | |
| 918 // use reg-reg form | |
| 919 // bit 13 is already zero | |
| 920 instr |= index; | |
| 921 } else { | |
| 922 // use reg-imm form | |
| 923 instr |= 0x00002000; // set bit 13 to one | |
| 924 instr |= disp & 0x1FFF; | |
| 925 } | |
| 926 | |
| 1748 | 927 cbuf.insts()->emit_int32(instr); |
| 0 | 928 |
| 929 #ifdef ASSERT | |
| 930 { | |
| 931 MacroAssembler _masm(&cbuf); | |
| 932 if (is_verified_oop_base) { | |
| 933 __ verify_oop(reg_to_register_object(src1_enc)); | |
| 934 } | |
| 935 if (is_verified_oop_store) { | |
| 936 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 937 } | |
| 938 if (tmp_enc != -1) { | |
| 939 __ mov(O7, reg_to_register_object(tmp_enc)); | |
| 940 } | |
| 941 if (is_verified_oop_load) { | |
| 942 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 943 } | |
| 944 } | |
| 945 #endif | |
| 946 } | |
| 947 | |
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948 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) { |
| 0 | 949 // The method which records debug information at every safepoint |
| 950 // expects the call to be the first instruction in the snippet as | |
| 951 // it creates a PcDesc structure which tracks the offset of a call | |
| 952 // from the start of the codeBlob. This offset is computed as | |
| 953 // code_end() - code_begin() of the code which has been emitted | |
| 954 // so far. | |
| 955 // In this particular case we have skirted around the problem by | |
| 956 // putting the "mov" instruction in the delay slot but the problem | |
| 957 // may bite us again at some other point and a cleaner/generic | |
| 958 // solution using relocations would be needed. | |
| 959 MacroAssembler _masm(&cbuf); | |
| 960 __ set_inst_mark(); | |
| 961 | |
| 962 // We flush the current window just so that there is a valid stack copy | |
| 963 // the fact that the current window becomes active again instantly is | |
| 964 // not a problem there is nothing live in it. | |
| 965 | |
| 966 #ifdef ASSERT | |
| 967 int startpos = __ offset(); | |
| 968 #endif /* ASSERT */ | |
| 969 | |
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970 __ call((address)entry_point, rtype); |
| 0 | 971 |
| 972 if (preserve_g2) __ delayed()->mov(G2, L7); | |
| 973 else __ delayed()->nop(); | |
| 974 | |
| 975 if (preserve_g2) __ mov(L7, G2); | |
| 976 | |
| 977 #ifdef ASSERT | |
| 978 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
| 979 #ifdef _LP64 | |
| 980 // Trash argument dump slots. | |
| 981 __ set(0xb0b8ac0db0b8ac0d, G1); | |
| 982 __ mov(G1, G5); | |
| 983 __ stx(G1, SP, STACK_BIAS + 0x80); | |
| 984 __ stx(G1, SP, STACK_BIAS + 0x88); | |
| 985 __ stx(G1, SP, STACK_BIAS + 0x90); | |
| 986 __ stx(G1, SP, STACK_BIAS + 0x98); | |
| 987 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
| 988 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
| 989 #else // _LP64 | |
| 990 // this is also a native call, so smash the first 7 stack locations, | |
| 991 // and the various registers | |
| 992 | |
| 993 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
| 994 // while [SP+0x44..0x58] are the argument dump slots. | |
| 995 __ set((intptr_t)0xbaadf00d, G1); | |
| 996 __ mov(G1, G5); | |
| 997 __ sllx(G1, 32, G1); | |
| 998 __ or3(G1, G5, G1); | |
| 999 __ mov(G1, G5); | |
| 1000 __ stx(G1, SP, 0x40); | |
| 1001 __ stx(G1, SP, 0x48); | |
| 1002 __ stx(G1, SP, 0x50); | |
| 1003 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
| 1004 #endif // _LP64 | |
| 1005 } | |
| 1006 #endif /*ASSERT*/ | |
| 1007 } | |
| 1008 | |
| 1009 //============================================================================= | |
| 1010 // REQUIRED FUNCTIONALITY for encoding | |
| 1011 void emit_lo(CodeBuffer &cbuf, int val) { } | |
| 1012 void emit_hi(CodeBuffer &cbuf, int val) { } | |
| 1013 | |
| 1014 | |
| 1015 //============================================================================= | |
| 2008 | 1016 const bool Matcher::constant_table_absolute_addressing = false; |
| 1017 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask; | |
| 1018 | |
| 1019 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { | |
| 1020 Compile* C = ra_->C; | |
| 1021 Compile::ConstantTable& constant_table = C->constant_table(); | |
| 1022 MacroAssembler _masm(&cbuf); | |
| 1023 | |
| 1024 Register r = as_Register(ra_->get_encode(this)); | |
| 1025 CodeSection* cs = __ code()->consts(); | |
| 1026 int consts_size = cs->align_at_start(cs->size()); | |
| 1027 | |
| 1028 if (UseRDPCForConstantTableBase) { | |
| 1029 // For the following RDPC logic to work correctly the consts | |
| 1030 // section must be allocated right before the insts section. This | |
| 1031 // assert checks for that. The layout and the SECT_* constants | |
| 1032 // are defined in src/share/vm/asm/codeBuffer.hpp. | |
| 1033 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); | |
| 1034 int offset = __ offset(); | |
| 1035 int disp; | |
| 1036 | |
| 1037 // If the displacement from the current PC to the constant table | |
| 1038 // base fits into simm13 we set the constant table base to the | |
| 1039 // current PC. | |
| 1040 if (__ is_simm13(-(consts_size + offset))) { | |
| 1041 constant_table.set_table_base_offset(-(consts_size + offset)); | |
| 1042 disp = 0; | |
| 1043 } else { | |
| 1044 // If the offset of the top constant (last entry in the table) | |
| 1045 // fits into simm13 we set the constant table base to the actual | |
| 1046 // table base. | |
| 1047 if (__ is_simm13(constant_table.top_offset())) { | |
| 1048 constant_table.set_table_base_offset(0); | |
| 1049 disp = consts_size + offset; | |
| 1050 } else { | |
| 1051 // Otherwise we set the constant table base in the middle of the | |
| 1052 // constant table. | |
| 1053 int half_consts_size = consts_size / 2; | |
| 1054 assert(half_consts_size * 2 == consts_size, "sanity"); | |
| 1055 constant_table.set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement. | |
| 1056 disp = half_consts_size + offset; | |
| 1057 } | |
| 1058 } | |
| 1059 | |
| 1060 __ rdpc(r); | |
| 1061 | |
| 1062 if (disp != 0) { | |
| 1063 assert(r != O7, "need temporary"); | |
| 1064 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); | |
| 1065 } | |
| 1066 } | |
| 1067 else { | |
| 1068 // Materialize the constant table base. | |
| 1069 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); | |
| 1070 address baseaddr = cs->start() + -(constant_table.table_base_offset()); | |
| 1071 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); | |
| 1072 AddressLiteral base(baseaddr, rspec); | |
| 1073 __ set(base, r); | |
| 1074 } | |
| 1075 } | |
| 1076 | |
| 1077 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { | |
| 1078 if (UseRDPCForConstantTableBase) { | |
| 1079 // This is really the worst case but generally it's only 1 instruction. | |
|
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1080 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; |
| 2008 | 1081 } else { |
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1082 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; |
| 2008 | 1083 } |
| 1084 } | |
| 1085 | |
| 1086 #ifndef PRODUCT | |
| 1087 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 1088 char reg[128]; | |
| 1089 ra_->dump_register(this, reg); | |
| 1090 if (UseRDPCForConstantTableBase) { | |
| 1091 st->print("RDPC %s\t! constant table base", reg); | |
| 1092 } else { | |
| 1093 st->print("SET &constanttable,%s\t! constant table base", reg); | |
| 1094 } | |
| 1095 } | |
| 1096 #endif | |
| 1097 | |
| 1098 | |
| 1099 //============================================================================= | |
| 0 | 1100 |
| 1101 #ifndef PRODUCT | |
| 1102 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1103 Compile* C = ra_->C; | |
| 1104 | |
| 1105 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1106 st->print_cr("NOP"); st->print("\t"); | |
| 1107 } | |
| 1108 | |
| 1109 if( VerifyThread ) { | |
| 1110 st->print_cr("Verify_Thread"); st->print("\t"); | |
| 1111 } | |
| 1112 | |
| 1113 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1114 | |
| 1115 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1116 // We require that their callers must bang for them. But be careful, because | |
| 1117 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1118 // stack. But the stack safety zone should account for that. | |
| 1119 // See bugs 4446381, 4468289, 4497237. | |
| 1120 if (C->need_stack_bang(framesize)) { | |
| 1121 st->print_cr("! stack bang"); st->print("\t"); | |
| 1122 } | |
| 1123 | |
| 1124 if (Assembler::is_simm13(-framesize)) { | |
| 1125 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
| 1126 } else { | |
| 1127 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1128 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1129 st->print ("SAVE R_SP,R_G3,R_SP"); | |
| 1130 } | |
| 1131 | |
| 1132 } | |
| 1133 #endif | |
| 1134 | |
| 1135 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1136 Compile* C = ra_->C; | |
| 1137 MacroAssembler _masm(&cbuf); | |
| 1138 | |
| 1139 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1140 __ nop(); | |
| 1141 } | |
| 1142 | |
| 1143 __ verify_thread(); | |
| 1144 | |
| 1145 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1146 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
| 1147 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
| 1148 | |
| 1149 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1150 // We require that their callers must bang for them. But be careful, because | |
| 1151 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1152 // stack. But the stack safety zone should account for that. | |
| 1153 // See bugs 4446381, 4468289, 4497237. | |
| 1154 if (C->need_stack_bang(framesize)) { | |
| 1155 __ generate_stack_overflow_check(framesize); | |
| 1156 } | |
| 1157 | |
| 1158 if (Assembler::is_simm13(-framesize)) { | |
| 1159 __ save(SP, -framesize, SP); | |
| 1160 } else { | |
| 1161 __ sethi(-framesize & ~0x3ff, G3); | |
| 1162 __ add(G3, -framesize & 0x3ff, G3); | |
| 1163 __ save(SP, G3, SP); | |
| 1164 } | |
| 1165 C->set_frame_complete( __ offset() ); | |
| 1166 } | |
| 1167 | |
| 1168 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 1169 return MachNode::size(ra_); | |
| 1170 } | |
| 1171 | |
| 1172 int MachPrologNode::reloc() const { | |
| 1173 return 10; // a large enough number | |
| 1174 } | |
| 1175 | |
| 1176 //============================================================================= | |
| 1177 #ifndef PRODUCT | |
| 1178 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1179 Compile* C = ra_->C; | |
| 1180 | |
| 1181 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 1182 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
| 1183 #ifdef _LP64 | |
| 1184 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1185 #else | |
| 1186 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1187 #endif | |
| 1188 } | |
| 1189 | |
| 1190 if( do_polling() ) | |
| 1191 st->print("RET\n\t"); | |
| 1192 | |
| 1193 st->print("RESTORE"); | |
| 1194 } | |
| 1195 #endif | |
| 1196 | |
| 1197 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1198 MacroAssembler _masm(&cbuf); | |
| 1199 Compile* C = ra_->C; | |
| 1200 | |
| 1201 __ verify_thread(); | |
| 1202 | |
| 1203 // If this does safepoint polling, then do it here | |
| 1204 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 727 | 1205 AddressLiteral polling_page(os::get_polling_page()); |
| 1206 __ sethi(polling_page, L0); | |
| 0 | 1207 __ relocate(relocInfo::poll_return_type); |
| 1208 __ ld_ptr( L0, 0, G0 ); | |
| 1209 } | |
| 1210 | |
| 1211 // If this is a return, then stuff the restore in the delay slot | |
| 1212 if( do_polling() ) { | |
| 1213 __ ret(); | |
| 1214 __ delayed()->restore(); | |
| 1215 } else { | |
| 1216 __ restore(); | |
| 1217 } | |
| 1218 } | |
| 1219 | |
| 1220 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 1221 return MachNode::size(ra_); | |
| 1222 } | |
| 1223 | |
| 1224 int MachEpilogNode::reloc() const { | |
| 1225 return 16; // a large enough number | |
| 1226 } | |
| 1227 | |
| 1228 const Pipeline * MachEpilogNode::pipeline() const { | |
| 1229 return MachNode::pipeline_class(); | |
| 1230 } | |
| 1231 | |
| 1232 int MachEpilogNode::safepoint_offset() const { | |
| 1233 assert( do_polling(), "no return for this epilog node"); | |
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1234 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; |
| 0 | 1235 } |
| 1236 | |
| 1237 //============================================================================= | |
| 1238 | |
| 1239 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
| 1240 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
| 1241 static enum RC rc_class( OptoReg::Name reg ) { | |
| 1242 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 1243 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 1244 VMReg r = OptoReg::as_VMReg(reg); | |
| 1245 if (r->is_Register()) return rc_int; | |
| 1246 assert(r->is_FloatRegister(), "must be"); | |
| 1247 return rc_float; | |
| 1248 } | |
| 1249 | |
| 1250 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { | |
| 1251 if( cbuf ) { | |
| 1252 // Better yet would be some mechanism to handle variable-size matches correctly | |
| 1253 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
| 1254 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
| 1255 } else { | |
| 1256 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
| 1257 } | |
| 1258 } | |
| 1259 #ifndef PRODUCT | |
| 1260 else if( !do_size ) { | |
| 1261 if( size != 0 ) st->print("\n\t"); | |
| 1262 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | |
| 1263 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | |
| 1264 } | |
| 1265 #endif | |
| 1266 return size+4; | |
| 1267 } | |
| 1268 | |
| 1269 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
| 1270 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
| 1271 #ifndef PRODUCT | |
| 1272 else if( !do_size ) { | |
| 1273 if( size != 0 ) st->print("\n\t"); | |
| 1274 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
| 1275 } | |
| 1276 #endif | |
| 1277 return size+4; | |
| 1278 } | |
| 1279 | |
| 1280 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
| 1281 PhaseRegAlloc *ra_, | |
| 1282 bool do_size, | |
| 1283 outputStream* st ) const { | |
| 1284 // Get registers to move | |
| 1285 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1286 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1287 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 1288 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 1289 | |
| 1290 enum RC src_second_rc = rc_class(src_second); | |
| 1291 enum RC src_first_rc = rc_class(src_first); | |
| 1292 enum RC dst_second_rc = rc_class(dst_second); | |
| 1293 enum RC dst_first_rc = rc_class(dst_first); | |
| 1294 | |
| 1295 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 1296 | |
| 1297 // Generate spill code! | |
| 1298 int size = 0; | |
| 1299 | |
| 1300 if( src_first == dst_first && src_second == dst_second ) | |
| 1301 return size; // Self copy, no move | |
| 1302 | |
| 1303 // -------------------------------------- | |
| 1304 // Check for mem-mem move. Load into unused float registers and fall into | |
| 1305 // the float-store case. | |
| 1306 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1307 int offset = ra_->reg2offset(src_first); | |
| 1308 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1309 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
| 1310 src_second = OptoReg::Name(R_F31_num); | |
| 1311 src_second_rc = rc_float; | |
| 1312 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
| 1313 } else { | |
| 1314 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1315 } | |
| 1316 src_first = OptoReg::Name(R_F30_num); | |
| 1317 src_first_rc = rc_float; | |
| 1318 } | |
| 1319 | |
| 1320 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
| 1321 int offset = ra_->reg2offset(src_second); | |
| 1322 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
| 1323 src_second = OptoReg::Name(R_F31_num); | |
| 1324 src_second_rc = rc_float; | |
| 1325 } | |
| 1326 | |
| 1327 // -------------------------------------- | |
| 1328 // Check for float->int copy; requires a trip through memory | |
| 3804 | 1329 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { |
| 0 | 1330 int offset = frame::register_save_words*wordSize; |
| 3804 | 1331 if (cbuf) { |
| 0 | 1332 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); |
| 1333 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1334 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1335 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
| 1336 } | |
| 1337 #ifndef PRODUCT | |
| 3804 | 1338 else if (!do_size) { |
| 1339 if (size != 0) st->print("\n\t"); | |
| 0 | 1340 st->print( "SUB R_SP,16,R_SP\n"); |
| 1341 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1342 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1343 st->print("\tADD R_SP,16,R_SP\n"); | |
| 1344 } | |
| 1345 #endif | |
| 1346 size += 16; | |
| 1347 } | |
| 1348 | |
| 3804 | 1349 // Check for float->int copy on T4 |
| 1350 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { | |
| 1351 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1352 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
| 1353 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st); | |
| 1354 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st); | |
| 1355 } | |
| 1356 // Check for int->float copy on T4 | |
| 1357 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { | |
| 1358 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1359 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
| 1360 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st); | |
| 1361 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st); | |
| 1362 } | |
| 1363 | |
| 0 | 1364 // -------------------------------------- |
| 1365 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
| 1366 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
| 1367 // hardware does the flop for me. Doubles are always aligned, so no problem | |
| 1368 // there. Misaligned sources only come from native-long-returns (handled | |
| 1369 // special below). | |
| 1370 #ifndef _LP64 | |
| 1371 if( src_first_rc == rc_int && // source is already big-endian | |
| 1372 src_second_rc != rc_bad && // 64-bit move | |
| 1373 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
| 1374 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
| 1375 // Do the big-endian flop. | |
| 1376 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
| 1377 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
| 1378 } | |
| 1379 #endif | |
| 1380 | |
| 1381 // -------------------------------------- | |
| 1382 // Check for integer reg-reg copy | |
| 1383 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
| 1384 #ifndef _LP64 | |
| 1385 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
| 1386 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1387 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1388 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1389 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
| 1390 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
| 1391 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
| 1392 if( cbuf ) { | |
| 1393 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
| 1394 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
| 1395 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
| 1396 #ifndef PRODUCT | |
| 1397 } else if( !do_size ) { | |
| 1398 if( size != 0 ) st->print("\n\t"); | |
| 1399 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
| 1400 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
| 1401 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
| 1402 #endif | |
| 1403 } | |
| 1404 return size+12; | |
| 1405 } | |
| 1406 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
| 1407 // returning a long value in I0/I1 | |
| 1408 // a SpillCopy must be able to target a return instruction's reg_class | |
| 1409 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1410 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1411 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1412 OptoReg::Name tdest = dst_first; | |
| 1413 | |
| 1414 if (src_first == dst_first) { | |
| 1415 tdest = OptoReg::Name(R_O7_num); | |
| 1416 size += 4; | |
| 1417 } | |
| 1418 | |
| 1419 if( cbuf ) { | |
| 1420 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
| 1421 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
| 1422 // ShrL_reg_imm6 | |
| 1423 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
| 1424 // ShrR_reg_imm6 src, 0, dst | |
| 1425 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
| 1426 if (tdest != dst_first) { | |
| 1427 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
| 1428 } | |
| 1429 } | |
| 1430 #ifndef PRODUCT | |
| 1431 else if( !do_size ) { | |
| 1432 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
| 1433 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
| 1434 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
| 1435 if (tdest != dst_first) { | |
| 1436 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
| 1437 } | |
| 1438 } | |
| 1439 #endif // PRODUCT | |
| 1440 return size+8; | |
| 1441 } | |
| 1442 #endif // !_LP64 | |
| 1443 // Else normal reg-reg copy | |
| 1444 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
| 1445 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
| 1446 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
| 1447 // This moves an aligned adjacent pair. | |
| 1448 // See if we are done. | |
| 1449 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
| 1450 return size; | |
| 1451 } | |
| 1452 | |
| 1453 // Check for integer store | |
| 1454 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
| 1455 int offset = ra_->reg2offset(dst_first); | |
| 1456 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1457 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1458 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
| 1459 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
| 1460 } | |
| 1461 | |
| 1462 // Check for integer load | |
| 1463 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
| 1464 int offset = ra_->reg2offset(src_first); | |
| 1465 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1466 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1467 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
| 1468 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1469 } | |
| 1470 | |
| 1471 // Check for float reg-reg copy | |
| 1472 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1473 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1474 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1475 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
| 1476 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
| 1477 } | |
| 1478 | |
| 1479 // Check for float store | |
| 1480 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
| 1481 int offset = ra_->reg2offset(dst_first); | |
| 1482 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1483 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1484 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
| 1485 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1486 } | |
| 1487 | |
| 1488 // Check for float load | |
| 1489 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1490 int offset = ra_->reg2offset(src_first); | |
| 1491 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1492 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1493 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
| 1494 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1495 } | |
| 1496 | |
| 1497 // -------------------------------------------------------------------- | |
| 1498 // Check for hi bits still needing moving. Only happens for misaligned | |
| 1499 // arguments to native calls. | |
| 1500 if( src_second == dst_second ) | |
| 1501 return size; // Self copy; no move | |
| 1502 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1503 | |
| 1504 #ifndef _LP64 | |
| 1505 // In the LP64 build, all registers can be moved as aligned/adjacent | |
| 605 | 1506 // pairs, so there's never any need to move the high bits separately. |
| 0 | 1507 // The 32-bit builds have to deal with the 32-bit ABI which can force |
| 1508 // all sorts of silly alignment problems. | |
| 1509 | |
| 1510 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
| 1511 // 32-bits of a 64-bit register, but are needed in low bits of another | |
| 1512 // register (else it's a hi-bits-to-hi-bits copy which should have | |
| 1513 // happened already as part of a 64-bit move) | |
| 1514 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
| 1515 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
| 1516 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
| 1517 // Shift src_second down to dst_second's low bits. | |
| 1518 if( cbuf ) { | |
| 1519 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1520 #ifndef PRODUCT | |
| 1521 } else if( !do_size ) { | |
| 1522 if( size != 0 ) st->print("\n\t"); | |
| 1523 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
| 1524 #endif | |
| 1525 } | |
| 1526 return size+4; | |
| 1527 } | |
| 1528 | |
| 1529 // Check for high word integer store. Must down-shift the hi bits | |
| 1530 // into a temp register, then fall into the case of storing int bits. | |
| 1531 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
| 1532 // Shift src_second down to dst_second's low bits. | |
| 1533 if( cbuf ) { | |
| 1534 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1535 #ifndef PRODUCT | |
| 1536 } else if( !do_size ) { | |
| 1537 if( size != 0 ) st->print("\n\t"); | |
| 1538 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
| 1539 #endif | |
| 1540 } | |
| 1541 size+=4; | |
| 1542 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
| 1543 } | |
| 1544 | |
| 1545 // Check for high word integer load | |
| 1546 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
| 1547 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
| 1548 | |
| 1549 // Check for high word integer store | |
| 1550 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
| 1551 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
| 1552 | |
| 1553 // Check for high word float store | |
| 1554 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
| 1555 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
| 1556 | |
| 1557 #endif // !_LP64 | |
| 1558 | |
| 1559 Unimplemented(); | |
| 1560 } | |
| 1561 | |
| 1562 #ifndef PRODUCT | |
| 1563 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1564 implementation( NULL, ra_, false, st ); | |
| 1565 } | |
| 1566 #endif | |
| 1567 | |
| 1568 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1569 implementation( &cbuf, ra_, false, NULL ); | |
| 1570 } | |
| 1571 | |
| 1572 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1573 return implementation( NULL, ra_, true, NULL ); | |
| 1574 } | |
| 1575 | |
| 1576 //============================================================================= | |
| 1577 #ifndef PRODUCT | |
| 1578 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 1579 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
| 1580 } | |
| 1581 #endif | |
| 1582 | |
| 1583 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
| 1584 MacroAssembler _masm(&cbuf); | |
| 1585 for(int i = 0; i < _count; i += 1) { | |
| 1586 __ nop(); | |
| 1587 } | |
| 1588 } | |
| 1589 | |
| 1590 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
| 1591 return 4 * _count; | |
| 1592 } | |
| 1593 | |
| 1594 | |
| 1595 //============================================================================= | |
| 1596 #ifndef PRODUCT | |
| 1597 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1598 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1599 int reg = ra_->get_reg_first(this); | |
| 1600 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
| 1601 } | |
| 1602 #endif | |
| 1603 | |
| 1604 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1605 MacroAssembler _masm(&cbuf); | |
| 1606 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
| 1607 int reg = ra_->get_encode(this); | |
| 1608 | |
| 1609 if (Assembler::is_simm13(offset)) { | |
| 1610 __ add(SP, offset, reg_to_register_object(reg)); | |
| 1611 } else { | |
| 1612 __ set(offset, O7); | |
| 1613 __ add(SP, O7, reg_to_register_object(reg)); | |
| 1614 } | |
| 1615 } | |
| 1616 | |
| 1617 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1618 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
| 1619 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
| 1620 return ra_->C->scratch_emit_size(this); | |
| 1621 } | |
| 1622 | |
| 1623 //============================================================================= | |
| 1624 | |
| 1625 // emit call stub, compiled java to interpretor | |
| 1626 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
| 1627 | |
| 1628 // Stub is fixed up when the corresponding call is converted from calling | |
| 1629 // compiled code to calling interpreted code. | |
| 1630 // set (empty), G5 | |
| 1631 // jmp -1 | |
| 1632 | |
| 1748 | 1633 address mark = cbuf.insts_mark(); // get mark within main instrs section |
| 0 | 1634 |
| 1635 MacroAssembler _masm(&cbuf); | |
| 1636 | |
| 1637 address base = | |
| 1638 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1639 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1640 | |
| 1641 // static stub relocation stores the instruction address of the call | |
| 1642 __ relocate(static_stub_Relocation::spec(mark)); | |
| 1643 | |
| 1644 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); | |
| 1645 | |
| 1646 __ set_inst_mark(); | |
| 727 | 1647 AddressLiteral addrlit(-1); |
| 1648 __ JUMP(addrlit, G3, 0); | |
| 0 | 1649 |
| 1650 __ delayed()->nop(); | |
| 1651 | |
| 1652 // Update current stubs pointer and restore code_end. | |
| 1653 __ end_a_stub(); | |
| 1654 } | |
| 1655 | |
| 1656 // size of call stub, compiled java to interpretor | |
| 1657 uint size_java_to_interp() { | |
| 1658 // This doesn't need to be accurate but it must be larger or equal to | |
| 1659 // the real size of the stub. | |
| 1660 return (NativeMovConstReg::instruction_size + // sethi/setlo; | |
| 1661 NativeJump::instruction_size + // sethi; jmp; nop | |
| 1662 (TraceJumps ? 20 * BytesPerInstWord : 0) ); | |
| 1663 } | |
| 1664 // relocation entries for call stub, compiled java to interpretor | |
| 1665 uint reloc_java_to_interp() { | |
| 1666 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1667 } | |
| 1668 | |
| 1669 | |
| 1670 //============================================================================= | |
| 1671 #ifndef PRODUCT | |
| 1672 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1673 st->print_cr("\nUEP:"); | |
| 1674 #ifdef _LP64 | |
|
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1675 if (UseCompressedOops) { |
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1676 assert(Universe::heap() != NULL, "java heap should be initialized"); |
|
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1677 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
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1678 st->print_cr("\tSLL R_G5,3,R_G5"); |
|
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1679 if (Universe::narrow_oop_base() != NULL) |
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1680 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
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1681 } else { |
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1682 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
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1683 } |
| 0 | 1684 st->print_cr("\tCMP R_G5,R_G3" ); |
| 1685 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1686 #else // _LP64 | |
| 1687 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
| 1688 st->print_cr("\tCMP R_G5,R_G3" ); | |
| 1689 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1690 #endif // _LP64 | |
| 1691 } | |
| 1692 #endif | |
| 1693 | |
| 1694 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1695 MacroAssembler _masm(&cbuf); | |
| 1696 Label L; | |
| 1697 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 1698 Register temp_reg = G3; | |
| 1699 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
| 1700 | |
| 605 | 1701 // Load klass from receiver |
|
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1702 __ load_klass(O0, temp_reg); |
| 0 | 1703 // Compare against expected klass |
| 1704 __ cmp(temp_reg, G5_ic_reg); | |
| 1705 // Branch to miss code, checks xcc or icc depending | |
| 1706 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
| 1707 } | |
| 1708 | |
| 1709 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1710 return MachNode::size(ra_); | |
| 1711 } | |
| 1712 | |
| 1713 | |
| 1714 //============================================================================= | |
| 1715 | |
| 1716 uint size_exception_handler() { | |
| 1717 if (TraceJumps) { | |
| 1718 return (400); // just a guess | |
| 1719 } | |
| 1720 return ( NativeJump::instruction_size ); // sethi;jmp;nop | |
| 1721 } | |
| 1722 | |
| 1723 uint size_deopt_handler() { | |
| 1724 if (TraceJumps) { | |
| 1725 return (400); // just a guess | |
| 1726 } | |
| 1727 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore | |
| 1728 } | |
| 1729 | |
| 1730 // Emit exception handler code. | |
| 1731 int emit_exception_handler(CodeBuffer& cbuf) { | |
| 1732 Register temp_reg = G3; | |
| 1748 | 1733 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); |
| 0 | 1734 MacroAssembler _masm(&cbuf); |
| 1735 | |
| 1736 address base = | |
| 1737 __ start_a_stub(size_exception_handler()); | |
| 1738 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1739 | |
| 1740 int offset = __ offset(); | |
| 1741 | |
| 727 | 1742 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1743 __ delayed()->nop(); |
| 1744 | |
| 1745 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
| 1746 | |
| 1747 __ end_a_stub(); | |
| 1748 | |
| 1749 return offset; | |
| 1750 } | |
| 1751 | |
| 1752 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 1753 // Can't use any of the current frame's registers as we may have deopted | |
| 1754 // at a poll and everything (including G3) can be live. | |
| 1755 Register temp_reg = L0; | |
| 727 | 1756 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
| 0 | 1757 MacroAssembler _masm(&cbuf); |
| 1758 | |
| 1759 address base = | |
| 1760 __ start_a_stub(size_deopt_handler()); | |
| 1761 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1762 | |
| 1763 int offset = __ offset(); | |
| 1764 __ save_frame(0); | |
| 727 | 1765 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1766 __ delayed()->restore(); |
| 1767 | |
| 1768 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1769 | |
| 1770 __ end_a_stub(); | |
| 1771 return offset; | |
| 1772 | |
| 1773 } | |
| 1774 | |
| 1775 // Given a register encoding, produce a Integer Register object | |
| 1776 static Register reg_to_register_object(int register_encoding) { | |
| 1777 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
| 1778 return as_Register(register_encoding); | |
| 1779 } | |
| 1780 | |
| 1781 // Given a register encoding, produce a single-precision Float Register object | |
| 1782 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
| 1783 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
| 1784 return as_SingleFloatRegister(register_encoding); | |
| 1785 } | |
| 1786 | |
| 1787 // Given a register encoding, produce a double-precision Float Register object | |
| 1788 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
| 1789 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
| 1790 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
| 1791 return as_DoubleFloatRegister(register_encoding); | |
| 1792 } | |
| 1793 | |
|
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1794 const bool Matcher::match_rule_supported(int opcode) { |
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1795 if (!has_match_rule(opcode)) |
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1796 return false; |
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1797 |
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1798 switch (opcode) { |
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1799 case Op_CountLeadingZerosI: |
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1800 case Op_CountLeadingZerosL: |
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1801 case Op_CountTrailingZerosI: |
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1802 case Op_CountTrailingZerosL: |
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1803 if (!UsePopCountInstruction) |
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1804 return false; |
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1805 break; |
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1806 } |
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1807 |
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1808 return true; // Per default match rules are supported. |
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1809 } |
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1810 |
| 0 | 1811 int Matcher::regnum_to_fpu_offset(int regnum) { |
| 1812 return regnum - 32; // The FP registers are in the second chunk | |
| 1813 } | |
| 1814 | |
| 1815 #ifdef ASSERT | |
| 1816 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
| 1817 #endif | |
| 1818 | |
| 1819 // Vector width in bytes | |
| 1820 const uint Matcher::vector_width_in_bytes(void) { | |
| 1821 return 8; | |
| 1822 } | |
| 1823 | |
| 1824 // Vector ideal reg | |
| 1825 const uint Matcher::vector_ideal_reg(void) { | |
| 1826 return Op_RegD; | |
| 1827 } | |
| 1828 | |
| 1829 // USII supports fxtof through the whole range of number, USIII doesn't | |
| 1830 const bool Matcher::convL2FSupported(void) { | |
| 1831 return VM_Version::has_fast_fxtof(); | |
| 1832 } | |
| 1833 | |
| 1834 // Is this branch offset short enough that a short branch can be used? | |
| 1835 // | |
| 1836 // NOTE: If the platform does not provide any short branch variants, then | |
| 1837 // this method should return false for offset 0. | |
|
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1838 bool Matcher::is_short_branch_offset(int rule, int offset) { |
| 0 | 1839 return false; |
| 1840 } | |
| 1841 | |
| 1842 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1843 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1844 // Depends on optimizations in MacroAssembler::setx. | |
| 1845 int hi = (int)(value >> 32); | |
| 1846 int lo = (int)(value & ~0); | |
| 1847 return (hi == 0) || (hi == -1) || (lo == 0); | |
| 1848 } | |
| 1849 | |
| 1850 // No scaling for the parameter the ClearArray node. | |
| 1851 const bool Matcher::init_array_count_is_in_bytes = true; | |
| 1852 | |
| 1853 // Threshold size for cleararray. | |
| 1854 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1855 | |
| 1856 // Should the Matcher clone shifts on addressing modes, expecting them to | |
| 1857 // be subsumed into complex addressing expressions or compute them into | |
| 1858 // registers? True for Intel but false for most RISCs | |
| 1859 const bool Matcher::clone_shift_expressions = false; | |
| 1860 | |
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1861 // Do we need to mask the count passed to shift instructions or does |
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1862 // the cpu only look at the lower 5/6 bits anyway? |
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1863 const bool Matcher::need_masked_shift_count = false; |
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1864 |
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1865 bool Matcher::narrow_oop_use_complex_address() { |
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1866 NOT_LP64(ShouldNotCallThis()); |
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1867 assert(UseCompressedOops, "only for compressed oops code"); |
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1868 return false; |
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1869 } |
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1870 |
| 0 | 1871 // Is it better to copy float constants, or load them directly from memory? |
| 1872 // Intel can load a float constant from a direct address, requiring no | |
| 1873 // extra registers. Most RISCs will have to materialize an address into a | |
| 1874 // register first, so they would do better to copy the constant from stack. | |
| 1875 const bool Matcher::rematerialize_float_constants = false; | |
| 1876 | |
| 1877 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1878 // needed. Else we split the double into 2 integer pieces and move it | |
| 1879 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1880 // Java calling convention forces doubles to be aligned. | |
| 1881 #ifdef _LP64 | |
| 1882 const bool Matcher::misaligned_doubles_ok = true; | |
| 1883 #else | |
| 1884 const bool Matcher::misaligned_doubles_ok = false; | |
| 1885 #endif | |
| 1886 | |
| 1887 // No-op on SPARC. | |
| 1888 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1889 } | |
| 1890 | |
| 1891 // Advertise here if the CPU requires explicit rounding operations | |
| 1892 // to implement the UseStrictFP mode. | |
| 1893 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
| 1894 | |
|
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1895 // Are floats conerted to double when stored to stack during deoptimization? |
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1896 // Sparc does not handle callee-save floats. |
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1897 bool Matcher::float_in_double() { return false; } |
| 0 | 1898 |
| 1899 // Do ints take an entire long register or just half? | |
| 1900 // Note that we if-def off of _LP64. | |
| 1901 // The relevant question is how the int is callee-saved. In _LP64 | |
| 1902 // the whole long is written but de-opt'ing will have to extract | |
| 1903 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
| 1904 #ifdef _LP64 | |
| 1905 const bool Matcher::int_in_long = true; | |
| 1906 #else | |
| 1907 const bool Matcher::int_in_long = false; | |
| 1908 #endif | |
| 1909 | |
| 1910 // Return whether or not this register is ever used as an argument. This | |
| 1911 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1912 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1913 // arguments in those registers not be available to the callee. | |
| 1914 bool Matcher::can_be_java_arg( int reg ) { | |
| 1915 // Standard sparc 6 args in registers | |
| 1916 if( reg == R_I0_num || | |
| 1917 reg == R_I1_num || | |
| 1918 reg == R_I2_num || | |
| 1919 reg == R_I3_num || | |
| 1920 reg == R_I4_num || | |
| 1921 reg == R_I5_num ) return true; | |
| 1922 #ifdef _LP64 | |
| 1923 // 64-bit builds can pass 64-bit pointers and longs in | |
| 1924 // the high I registers | |
| 1925 if( reg == R_I0H_num || | |
| 1926 reg == R_I1H_num || | |
| 1927 reg == R_I2H_num || | |
| 1928 reg == R_I3H_num || | |
| 1929 reg == R_I4H_num || | |
| 1930 reg == R_I5H_num ) return true; | |
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1931 |
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1932 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
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1933 return true; |
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1934 } |
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1935 |
| 0 | 1936 #else |
| 1937 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
| 1938 // Longs cannot be passed in O regs, because O regs become I regs | |
| 1939 // after a 'save' and I regs get their high bits chopped off on | |
| 1940 // interrupt. | |
| 1941 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
| 1942 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
| 1943 #endif | |
| 1944 // A few float args in registers | |
| 1945 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
| 1946 | |
| 1947 return false; | |
| 1948 } | |
| 1949 | |
| 1950 bool Matcher::is_spillable_arg( int reg ) { | |
| 1951 return can_be_java_arg(reg); | |
| 1952 } | |
| 1953 | |
|
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1954 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
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1955 // Use hardware SDIVX instruction when it is |
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1956 // faster than a code which use multiply. |
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1957 return VM_Version::has_fast_idiv(); |
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1958 } |
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1959 |
| 0 | 1960 // Register for DIVI projection of divmodI |
| 1961 RegMask Matcher::divI_proj_mask() { | |
| 1962 ShouldNotReachHere(); | |
| 1963 return RegMask(); | |
| 1964 } | |
| 1965 | |
| 1966 // Register for MODI projection of divmodI | |
| 1967 RegMask Matcher::modI_proj_mask() { | |
| 1968 ShouldNotReachHere(); | |
| 1969 return RegMask(); | |
| 1970 } | |
| 1971 | |
| 1972 // Register for DIVL projection of divmodL | |
| 1973 RegMask Matcher::divL_proj_mask() { | |
| 1974 ShouldNotReachHere(); | |
| 1975 return RegMask(); | |
| 1976 } | |
| 1977 | |
| 1978 // Register for MODL projection of divmodL | |
| 1979 RegMask Matcher::modL_proj_mask() { | |
| 1980 ShouldNotReachHere(); | |
| 1981 return RegMask(); | |
| 1982 } | |
| 1983 | |
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1984 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
| 1567 | 1985 return L7_REGP_mask; |
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1986 } |
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1987 |
| 0 | 1988 %} |
| 1989 | |
| 1990 | |
| 1991 // The intptr_t operand types, defined by textual substitution. | |
| 1992 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
| 1993 #ifdef _LP64 | |
| 824 | 1994 #define immX immL |
| 1995 #define immX13 immL13 | |
| 1996 #define immX13m7 immL13m7 | |
| 1997 #define iRegX iRegL | |
| 1998 #define g1RegX g1RegL | |
| 0 | 1999 #else |
| 824 | 2000 #define immX immI |
| 2001 #define immX13 immI13 | |
| 2002 #define immX13m7 immI13m7 | |
| 2003 #define iRegX iRegI | |
| 2004 #define g1RegX g1RegI | |
| 0 | 2005 #endif |
| 2006 | |
| 2007 //----------ENCODING BLOCK----------------------------------------------------- | |
| 2008 // This block specifies the encoding classes used by the compiler to output | |
| 2009 // byte streams. Encoding classes are parameterized macros used by | |
| 2010 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 2011 // instruction. Operands specify their base encoding interface with the | |
| 2012 // interface keyword. There are currently supported four interfaces, | |
| 2013 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 2014 // operand to generate a function which returns its register number when | |
| 2015 // queried. CONST_INTER causes an operand to generate a function which | |
| 2016 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 2017 // operand to generate four functions which return the Base Register, the | |
| 2018 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 2019 // queried. COND_INTER causes an operand to generate six functions which | |
| 2020 // return the encoding code (ie - encoding bits for the instruction) | |
| 2021 // associated with each basic boolean condition for a conditional instruction. | |
| 2022 // | |
| 2023 // Instructions specify two basic values for encoding. Again, a function | |
| 2024 // is available to check if the constant displacement is an oop. They use the | |
| 2025 // ins_encode keyword to specify their encoding classes (which must be | |
| 2026 // a sequence of enc_class names, and their parameters, specified in | |
| 2027 // the encoding block), and they use the | |
| 2028 // opcode keyword to specify, in order, their primary, secondary, and | |
| 2029 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 2030 // needs for encoding need to be specified. | |
| 2031 encode %{ | |
| 2032 enc_class enc_untested %{ | |
| 2033 #ifdef ASSERT | |
| 2034 MacroAssembler _masm(&cbuf); | |
| 2035 __ untested("encoding"); | |
| 2036 #endif | |
| 2037 %} | |
| 2038 | |
| 2039 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
| 2040 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
| 2041 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | |
| 2042 %} | |
| 2043 | |
|
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2044 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
|
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2045 emit_form3_mem_reg(cbuf, this, $primary, -1, |
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2046 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
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2047 %} |
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2048 |
| 0 | 2049 enc_class form3_mem_prefetch_read( memory mem ) %{ |
|
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2050 emit_form3_mem_reg(cbuf, this, $primary, -1, |
| 0 | 2051 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
| 2052 %} | |
| 2053 | |
| 2054 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
|
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2055 emit_form3_mem_reg(cbuf, this, $primary, -1, |
| 0 | 2056 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
| 2057 %} | |
| 2058 | |
| 2059 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
| 2060 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
| 2061 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
| 2062 guarantee($mem$$index == R_G0_enc, "double index?"); | |
|
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2063 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
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2064 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
| 0 | 2065 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
| 2066 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
| 2067 %} | |
| 2068 | |
| 2069 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
| 2070 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
| 2071 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
| 2072 guarantee($mem$$index == R_G0_enc, "double index?"); | |
| 2073 // Load long with 2 instructions | |
|
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2074 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
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2075 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
| 0 | 2076 %} |
| 2077 | |
| 2078 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
| 2079 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
| 2080 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
|
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2081 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
| 0 | 2082 %} |
| 2083 | |
| 2084 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
| 2085 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2086 if( $rs2$$reg != $rd$$reg ) | |
| 2087 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 2088 %} | |
| 2089 | |
| 2090 // Target lo half of long | |
| 2091 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
| 2092 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2093 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
| 2094 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 2095 %} | |
| 2096 | |
| 2097 // Source lo half of long | |
| 2098 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
| 2099 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2100 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
| 2101 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
| 2102 %} | |
| 2103 | |
| 2104 // Target hi half of long | |
| 2105 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
| 2106 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
| 2107 %} | |
| 2108 | |
| 2109 // Source lo half of long, and leave it sign extended. | |
| 2110 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
| 2111 // Sign extend low half | |
| 2112 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
| 2113 %} | |
| 2114 | |
| 2115 // Source hi half of long, and leave it sign extended. | |
| 2116 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
| 2117 // Shift high half to low half | |
| 2118 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
| 2119 %} | |
| 2120 | |
| 2121 // Source hi half of long | |
| 2122 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
| 2123 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2124 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
| 2125 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
| 2126 %} | |
| 2127 | |
| 2128 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
| 2129 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
| 2130 %} | |
| 2131 | |
| 2132 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
| 2133 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
| 2134 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
| 2135 %} | |
| 2136 | |
| 2137 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
| 2138 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
| 2139 // clear if nothing else is happening | |
| 2140 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
| 2141 // blt,a,pn done | |
| 2142 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
| 2143 // mov dst,-1 in delay slot | |
| 2144 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2145 %} | |
| 2146 | |
| 2147 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
| 2148 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
| 2149 %} | |
| 2150 | |
| 2151 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
| 2152 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
| 2153 %} | |
| 2154 | |
| 2155 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
| 2156 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
| 2157 %} | |
| 2158 | |
| 2159 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
| 2160 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
| 2161 %} | |
| 2162 | |
| 2163 enc_class move_return_pc_to_o1() %{ | |
| 2164 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
| 2165 %} | |
| 2166 | |
| 2167 #ifdef _LP64 | |
| 2168 /* %%% merge with enc_to_bool */ | |
| 2169 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
| 2170 MacroAssembler _masm(&cbuf); | |
| 2171 | |
| 2172 Register src_reg = reg_to_register_object($src$$reg); | |
| 2173 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 2174 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
| 2175 %} | |
| 2176 #endif | |
| 2177 | |
| 2178 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
| 2179 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
| 2180 MacroAssembler _masm(&cbuf); | |
| 2181 | |
| 2182 Register p_reg = reg_to_register_object($p$$reg); | |
| 2183 Register q_reg = reg_to_register_object($q$$reg); | |
| 2184 Register y_reg = reg_to_register_object($y$$reg); | |
| 2185 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
| 2186 | |
| 2187 __ subcc( p_reg, q_reg, p_reg ); | |
| 2188 __ add ( p_reg, y_reg, tmp_reg ); | |
| 2189 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
| 2190 %} | |
| 2191 | |
| 2192 enc_class form_d2i_helper(regD src, regF dst) %{ | |
| 2193 // fcmp %fcc0,$src,$src | |
| 2194 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2195 // branch %fcc0 not-nan, predict taken | |
| 2196 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2197 // fdtoi $src,$dst | |
| 2198 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
| 2199 // fitos $dst,$dst (if nan) | |
| 2200 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2201 // clear $dst (if nan) | |
| 2202 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2203 // carry on here... | |
| 2204 %} | |
| 2205 | |
| 2206 enc_class form_d2l_helper(regD src, regD dst) %{ | |
| 2207 // fcmp %fcc0,$src,$src check for NAN | |
| 2208 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2209 // branch %fcc0 not-nan, predict taken | |
| 2210 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2211 // fdtox $src,$dst convert in delay slot | |
| 2212 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
| 2213 // fxtod $dst,$dst (if nan) | |
| 2214 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2215 // clear $dst (if nan) | |
| 2216 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2217 // carry on here... | |
| 2218 %} | |
| 2219 | |
| 2220 enc_class form_f2i_helper(regF src, regF dst) %{ | |
| 2221 // fcmps %fcc0,$src,$src | |
| 2222 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2223 // branch %fcc0 not-nan, predict taken | |
| 2224 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2225 // fstoi $src,$dst | |
| 2226 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
| 2227 // fitos $dst,$dst (if nan) | |
| 2228 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2229 // clear $dst (if nan) | |
| 2230 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2231 // carry on here... | |
| 2232 %} | |
| 2233 | |
| 2234 enc_class form_f2l_helper(regF src, regD dst) %{ | |
| 2235 // fcmps %fcc0,$src,$src | |
| 2236 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2237 // branch %fcc0 not-nan, predict taken | |
| 2238 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2239 // fstox $src,$dst | |
| 2240 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
| 2241 // fxtod $dst,$dst (if nan) | |
| 2242 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2243 // clear $dst (if nan) | |
| 2244 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2245 // carry on here... | |
| 2246 %} | |
| 2247 | |
| 2248 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2249 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2250 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2251 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2252 | |
| 2253 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2254 | |
| 2255 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2256 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2257 | |
| 2258 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
| 2259 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2260 %} | |
| 2261 | |
| 2262 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
| 2263 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2264 %} | |
| 2265 | |
| 2266 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
| 2267 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2268 %} | |
| 2269 | |
| 2270 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
| 2271 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2272 %} | |
| 2273 | |
| 2274 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
| 2275 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
| 2276 %} | |
| 2277 | |
| 2278 // Encloding class for traceable jumps | |
| 2279 enc_class form_jmpl(g3RegP dest) %{ | |
| 2280 emit_jmpl(cbuf, $dest$$reg); | |
| 2281 %} | |
| 2282 | |
| 2283 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
| 2284 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
| 2285 %} | |
| 2286 | |
| 2287 enc_class form2_nop() %{ | |
| 2288 emit_nop(cbuf); | |
| 2289 %} | |
| 2290 | |
| 2291 enc_class form2_illtrap() %{ | |
| 2292 emit_illtrap(cbuf); | |
| 2293 %} | |
| 2294 | |
| 2295 | |
| 2296 // Compare longs and convert into -1, 0, 1. | |
| 2297 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
| 2298 // CMP $src1,$src2 | |
| 2299 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
| 2300 // blt,a,pn done | |
| 2301 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
| 2302 // mov dst,-1 in delay slot | |
| 2303 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2304 // bgt,a,pn done | |
| 2305 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
| 2306 // mov dst,1 in delay slot | |
| 2307 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
| 2308 // CLR $dst | |
| 2309 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
| 2310 %} | |
| 2311 | |
| 2312 enc_class enc_PartialSubtypeCheck() %{ | |
| 2313 MacroAssembler _masm(&cbuf); | |
| 2314 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
| 2315 __ delayed()->nop(); | |
| 2316 %} | |
| 2317 | |
| 2318 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ | |
| 2319 MacroAssembler _masm(&cbuf); | |
| 2320 Label &L = *($labl$$label); | |
| 2321 Assembler::Predict predict_taken = | |
| 2322 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2323 | |
| 2324 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L); | |
| 2325 __ delayed()->nop(); | |
| 2326 %} | |
| 2327 | |
| 2328 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ | |
| 2329 MacroAssembler _masm(&cbuf); | |
| 2330 Label &L = *($labl$$label); | |
| 2331 Assembler::Predict predict_taken = | |
| 2332 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2333 | |
| 2334 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); | |
| 2335 __ delayed()->nop(); | |
| 2336 %} | |
| 2337 | |
| 2338 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ | |
| 2339 MacroAssembler _masm(&cbuf); | |
| 2340 Label &L = *($labl$$label); | |
| 2341 Assembler::Predict predict_taken = | |
| 2342 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2343 | |
| 2344 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); | |
| 2345 __ delayed()->nop(); | |
| 2346 %} | |
| 2347 | |
| 2348 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ | |
| 2349 MacroAssembler _masm(&cbuf); | |
| 2350 Label &L = *($labl$$label); | |
| 2351 Assembler::Predict predict_taken = | |
| 2352 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2353 | |
| 2354 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); | |
| 2355 __ delayed()->nop(); | |
| 2356 %} | |
| 2357 | |
| 2358 enc_class enc_ba( Label labl ) %{ | |
| 2359 MacroAssembler _masm(&cbuf); | |
| 2360 Label &L = *($labl$$label); | |
| 2361 __ ba(false, L); | |
| 2362 __ delayed()->nop(); | |
| 2363 %} | |
| 2364 | |
| 2365 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ | |
| 2366 MacroAssembler _masm(&cbuf); | |
| 2367 Label &L = *$labl$$label; | |
| 2368 Assembler::Predict predict_taken = | |
| 2369 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2370 | |
| 2371 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); | |
| 2372 __ delayed()->nop(); | |
| 2373 %} | |
| 2374 | |
| 2375 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
| 2376 int op = (Assembler::arith_op << 30) | | |
| 2377 ($dst$$reg << 25) | | |
| 2378 (Assembler::movcc_op3 << 19) | | |
| 2379 (1 << 18) | // cc2 bit for 'icc' | |
| 2380 ($cmp$$cmpcode << 14) | | |
| 2381 (0 << 13) | // select register move | |
| 2382 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
| 2383 ($src$$reg << 0); | |
| 1748 | 2384 cbuf.insts()->emit_int32(op); |
| 0 | 2385 %} |
| 2386 | |
| 2387 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
| 2388 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2389 int op = (Assembler::arith_op << 30) | | |
| 2390 ($dst$$reg << 25) | | |
| 2391 (Assembler::movcc_op3 << 19) | | |
| 2392 (1 << 18) | // cc2 bit for 'icc' | |
| 2393 ($cmp$$cmpcode << 14) | | |
| 2394 (1 << 13) | // select immediate move | |
| 2395 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
| 2396 (simm11 << 0); | |
| 1748 | 2397 cbuf.insts()->emit_int32(op); |
| 0 | 2398 %} |
| 2399 | |
| 2400 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
| 2401 int op = (Assembler::arith_op << 30) | | |
| 2402 ($dst$$reg << 25) | | |
| 2403 (Assembler::movcc_op3 << 19) | | |
| 2404 (0 << 18) | // cc2 bit for 'fccX' | |
| 2405 ($cmp$$cmpcode << 14) | | |
| 2406 (0 << 13) | // select register move | |
| 2407 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2408 ($src$$reg << 0); | |
| 1748 | 2409 cbuf.insts()->emit_int32(op); |
| 0 | 2410 %} |
| 2411 | |
| 2412 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
| 2413 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2414 int op = (Assembler::arith_op << 30) | | |
| 2415 ($dst$$reg << 25) | | |
| 2416 (Assembler::movcc_op3 << 19) | | |
| 2417 (0 << 18) | // cc2 bit for 'fccX' | |
| 2418 ($cmp$$cmpcode << 14) | | |
| 2419 (1 << 13) | // select immediate move | |
| 2420 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2421 (simm11 << 0); | |
| 1748 | 2422 cbuf.insts()->emit_int32(op); |
| 0 | 2423 %} |
| 2424 | |
| 2425 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
| 2426 int op = (Assembler::arith_op << 30) | | |
| 2427 ($dst$$reg << 25) | | |
| 2428 (Assembler::fpop2_op3 << 19) | | |
| 2429 (0 << 18) | | |
| 2430 ($cmp$$cmpcode << 14) | | |
| 2431 (1 << 13) | // select register move | |
| 2432 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
| 2433 ($primary << 5) | // select single, double or quad | |
| 2434 ($src$$reg << 0); | |
| 1748 | 2435 cbuf.insts()->emit_int32(op); |
| 0 | 2436 %} |
| 2437 | |
| 2438 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
| 2439 int op = (Assembler::arith_op << 30) | | |
| 2440 ($dst$$reg << 25) | | |
| 2441 (Assembler::fpop2_op3 << 19) | | |
| 2442 (0 << 18) | | |
| 2443 ($cmp$$cmpcode << 14) | | |
| 2444 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
| 2445 ($primary << 5) | // select single, double or quad | |
| 2446 ($src$$reg << 0); | |
| 1748 | 2447 cbuf.insts()->emit_int32(op); |
| 0 | 2448 %} |
| 2449 | |
| 2450 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
| 2451 // the condition comes from opcode-field instead of an argument. | |
| 2452 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
| 2453 int op = (Assembler::arith_op << 30) | | |
| 2454 ($dst$$reg << 25) | | |
| 2455 (Assembler::movcc_op3 << 19) | | |
| 2456 (1 << 18) | // cc2 bit for 'icc' | |
| 2457 ($primary << 14) | | |
| 2458 (0 << 13) | // select register move | |
| 2459 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2460 ($src$$reg << 0); | |
| 1748 | 2461 cbuf.insts()->emit_int32(op); |
| 0 | 2462 %} |
| 2463 | |
| 2464 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
| 2465 int op = (Assembler::arith_op << 30) | | |
| 2466 ($dst$$reg << 25) | | |
| 2467 (Assembler::movcc_op3 << 19) | | |
| 2468 (6 << 16) | // cc2 bit for 'xcc' | |
| 2469 ($primary << 14) | | |
| 2470 (0 << 13) | // select register move | |
| 2471 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2472 ($src$$reg << 0); | |
| 1748 | 2473 cbuf.insts()->emit_int32(op); |
| 0 | 2474 %} |
| 2475 | |
| 2476 enc_class Set13( immI13 src, iRegI rd ) %{ | |
| 2477 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
| 2478 %} | |
| 2479 | |
| 2480 enc_class SetHi22( immI src, iRegI rd ) %{ | |
| 2481 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
| 2482 %} | |
| 2483 | |
| 2484 enc_class Set32( immI src, iRegI rd ) %{ | |
| 2485 MacroAssembler _masm(&cbuf); | |
| 2486 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
| 2487 %} | |
| 2488 | |
| 2489 enc_class call_epilog %{ | |
| 2490 if( VerifyStackAtCalls ) { | |
| 2491 MacroAssembler _masm(&cbuf); | |
| 2492 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
| 2493 Register temp_reg = G3; | |
| 2494 __ add(SP, framesize, temp_reg); | |
| 2495 __ cmp(temp_reg, FP); | |
| 2496 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
| 2497 } | |
| 2498 %} | |
| 2499 | |
| 2500 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
| 2501 // to G1 so the register allocator will not have to deal with the misaligned register | |
| 2502 // pair. | |
| 2503 enc_class adjust_long_from_native_call %{ | |
| 2504 #ifndef _LP64 | |
| 2505 if (returns_long()) { | |
| 2506 // sllx O0,32,O0 | |
| 2507 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
| 2508 // srl O1,0,O1 | |
| 2509 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
| 2510 // or O0,O1,G1 | |
| 2511 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
| 2512 } | |
| 2513 #endif | |
| 2514 %} | |
| 2515 | |
| 2516 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
| 2517 // CALL directly to the runtime | |
| 2518 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
| 2519 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
|
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2520 /*preserve_g2=*/true); |
| 0 | 2521 %} |
| 2522 | |
| 1567 | 2523 enc_class preserve_SP %{ |
| 2524 MacroAssembler _masm(&cbuf); | |
| 2525 __ mov(SP, L7_mh_SP_save); | |
| 2526 %} | |
| 2527 | |
| 2528 enc_class restore_SP %{ | |
| 2529 MacroAssembler _masm(&cbuf); | |
| 2530 __ mov(L7_mh_SP_save, SP); | |
| 2531 %} | |
| 2532 | |
| 0 | 2533 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
| 2534 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2535 // who we intended to call. | |
| 2536 if ( !_method ) { | |
| 2537 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); | |
| 2538 } else if (_optimized_virtual) { | |
| 2539 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
| 2540 } else { | |
| 2541 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
| 2542 } | |
| 2543 if( _method ) { // Emit stub for static call | |
| 2544 emit_java_to_interp(cbuf); | |
| 2545 } | |
| 2546 %} | |
| 2547 | |
| 2548 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
| 2549 MacroAssembler _masm(&cbuf); | |
| 2550 __ set_inst_mark(); | |
| 2551 int vtable_index = this->_vtable_index; | |
| 2552 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
| 2553 if (vtable_index < 0) { | |
| 2554 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
| 2555 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
| 2556 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2557 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
| 2558 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
| 2559 // !!!!! | |
| 2560 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info | |
| 2561 // emit_call_dynamic_prologue( cbuf ); | |
| 2562 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); | |
| 2563 | |
| 2564 address virtual_call_oop_addr = __ inst_mark(); | |
| 2565 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2566 // who we intended to call. | |
| 2567 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); | |
| 2568 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); | |
| 2569 } else { | |
| 2570 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 2571 // Just go thru the vtable | |
| 2572 // get receiver klass (receiver already checked for non-null) | |
| 2573 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
| 2574 int off = __ offset(); | |
|
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2575 __ load_klass(O0, G3_scratch); |
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2576 int klass_load_size; |
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2577 if (UseCompressedOops) { |
|
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2578 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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2579 if (Universe::narrow_oop_base() == NULL) |
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2580 klass_load_size = 2*BytesPerInstWord; |
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2581 else |
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2582 klass_load_size = 3*BytesPerInstWord; |
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2583 } else { |
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2584 klass_load_size = 1*BytesPerInstWord; |
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2585 } |
| 0 | 2586 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
| 2587 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
| 2588 if( __ is_simm13(v_off) ) { | |
| 2589 __ ld_ptr(G3, v_off, G5_method); | |
| 2590 } else { | |
| 2591 // Generate 2 instructions | |
| 2592 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
| 2593 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
| 2594 // ld_ptr, set_hi, set | |
|
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2595 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
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2596 "Unexpected instruction size(s)"); |
| 0 | 2597 __ ld_ptr(G3, G5_method, G5_method); |
| 2598 } | |
| 2599 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
| 2600 // However it may very well end up in handle_wrong_method if the | |
| 2601 // method is abstract for the particular class. | |
| 2602 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); | |
| 2603 // jump to target (either compiled code or c2iadapter) | |
| 2604 __ jmpl(G3_scratch, G0, O7); | |
| 2605 __ delayed()->nop(); | |
| 2606 } | |
| 2607 %} | |
| 2608 | |
| 2609 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
| 2610 MacroAssembler _masm(&cbuf); | |
| 2611 | |
| 2612 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2613 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
| 2614 // we might be calling a C2I adapter which needs it. | |
| 2615 | |
| 2616 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
| 2617 // Load nmethod | |
| 2618 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); | |
| 2619 | |
| 2620 // CALL to compiled java, indirect the contents of G3 | |
| 2621 __ set_inst_mark(); | |
| 2622 __ callr(temp_reg, G0); | |
| 2623 __ delayed()->nop(); | |
| 2624 %} | |
| 2625 | |
| 2626 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
| 2627 MacroAssembler _masm(&cbuf); | |
| 2628 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2629 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2630 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2631 | |
| 2632 __ sra(Rdivisor, 0, Rdivisor); | |
| 2633 __ sra(Rdividend, 0, Rdividend); | |
| 2634 __ sdivx(Rdividend, Rdivisor, Rresult); | |
| 2635 %} | |
| 2636 | |
| 2637 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
| 2638 MacroAssembler _masm(&cbuf); | |
| 2639 | |
| 2640 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2641 int divisor = $imm$$constant; | |
| 2642 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2643 | |
| 2644 __ sra(Rdividend, 0, Rdividend); | |
| 2645 __ sdivx(Rdividend, divisor, Rresult); | |
| 2646 %} | |
| 2647 | |
| 2648 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 2649 MacroAssembler _masm(&cbuf); | |
| 2650 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
| 2651 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
| 2652 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2653 | |
| 2654 __ sra( Rsrc1, 0, Rsrc1 ); | |
| 2655 __ sra( Rsrc2, 0, Rsrc2 ); | |
| 2656 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
| 2657 __ srlx( Rdst, 32, Rdst ); | |
| 2658 %} | |
| 2659 | |
| 2660 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
| 2661 MacroAssembler _masm(&cbuf); | |
| 2662 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2663 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2664 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2665 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2666 | |
| 2667 assert(Rdividend != Rscratch, ""); | |
| 2668 assert(Rdivisor != Rscratch, ""); | |
| 2669 | |
| 2670 __ sra(Rdividend, 0, Rdividend); | |
| 2671 __ sra(Rdivisor, 0, Rdivisor); | |
| 2672 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
| 2673 __ mulx(Rscratch, Rdivisor, Rscratch); | |
| 2674 __ sub(Rdividend, Rscratch, Rresult); | |
| 2675 %} | |
| 2676 | |
| 2677 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
| 2678 MacroAssembler _masm(&cbuf); | |
| 2679 | |
| 2680 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2681 int divisor = $imm$$constant; | |
| 2682 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2683 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2684 | |
| 2685 assert(Rdividend != Rscratch, ""); | |
| 2686 | |
| 2687 __ sra(Rdividend, 0, Rdividend); | |
| 2688 __ sdivx(Rdividend, divisor, Rscratch); | |
| 2689 __ mulx(Rscratch, divisor, Rscratch); | |
| 2690 __ sub(Rdividend, Rscratch, Rresult); | |
| 2691 %} | |
| 2692 | |
| 2693 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
| 2694 MacroAssembler _masm(&cbuf); | |
| 2695 | |
| 2696 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2697 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2698 | |
| 2699 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2700 %} | |
| 2701 | |
| 2702 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
| 2703 MacroAssembler _masm(&cbuf); | |
| 2704 | |
| 2705 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2706 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2707 | |
| 2708 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2709 %} | |
| 2710 | |
| 2711 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
| 2712 MacroAssembler _masm(&cbuf); | |
| 2713 | |
| 2714 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2715 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2716 | |
| 2717 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2718 %} | |
| 2719 | |
| 2720 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
| 2721 MacroAssembler _masm(&cbuf); | |
| 2722 | |
| 2723 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2724 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2725 | |
| 2726 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2727 %} | |
| 2728 | |
| 2729 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
| 2730 MacroAssembler _masm(&cbuf); | |
| 2731 | |
| 2732 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2733 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2734 | |
| 2735 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2736 %} | |
| 2737 | |
| 2738 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
| 2739 MacroAssembler _masm(&cbuf); | |
| 2740 | |
| 2741 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2742 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2743 | |
| 2744 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2745 %} | |
| 2746 | |
| 2747 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
| 2748 MacroAssembler _masm(&cbuf); | |
| 2749 | |
| 2750 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2751 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2752 | |
| 2753 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2754 %} | |
| 2755 | |
| 2756 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2757 MacroAssembler _masm(&cbuf); | |
| 2758 | |
| 2759 Register Roop = reg_to_register_object($oop$$reg); | |
| 2760 Register Rbox = reg_to_register_object($box$$reg); | |
| 2761 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2762 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2763 | |
| 2764 assert(Roop != Rscratch, ""); | |
| 2765 assert(Roop != Rmark, ""); | |
| 2766 assert(Rbox != Rscratch, ""); | |
| 2767 assert(Rbox != Rmark, ""); | |
| 2768 | |
|
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2769 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2770 %} |
| 2771 | |
| 2772 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2773 MacroAssembler _masm(&cbuf); | |
| 2774 | |
| 2775 Register Roop = reg_to_register_object($oop$$reg); | |
| 2776 Register Rbox = reg_to_register_object($box$$reg); | |
| 2777 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2778 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2779 | |
| 2780 assert(Roop != Rscratch, ""); | |
| 2781 assert(Roop != Rmark, ""); | |
| 2782 assert(Rbox != Rscratch, ""); | |
| 2783 assert(Rbox != Rmark, ""); | |
| 2784 | |
|
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2785 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2786 %} |
| 2787 | |
| 2788 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
| 2789 MacroAssembler _masm(&cbuf); | |
| 2790 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2791 Register Rold = reg_to_register_object($old$$reg); | |
| 2792 Register Rnew = reg_to_register_object($new$$reg); | |
| 2793 | |
| 2794 // casx_under_lock picks 1 of 3 encodings: | |
| 2795 // For 32-bit pointers you get a 32-bit CAS | |
| 2796 // For 64-bit pointers you get a 64-bit CASX | |
|
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2797 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
| 0 | 2798 __ cmp( Rold, Rnew ); |
| 2799 %} | |
| 2800 | |
| 2801 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
| 2802 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2803 Register Rold = reg_to_register_object($old$$reg); | |
| 2804 Register Rnew = reg_to_register_object($new$$reg); | |
| 2805 | |
| 2806 MacroAssembler _masm(&cbuf); | |
| 2807 __ mov(Rnew, O7); | |
| 2808 __ casx(Rmem, Rold, O7); | |
| 2809 __ cmp( Rold, O7 ); | |
| 2810 %} | |
| 2811 | |
| 2812 // raw int cas, used for compareAndSwap | |
| 2813 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
| 2814 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2815 Register Rold = reg_to_register_object($old$$reg); | |
| 2816 Register Rnew = reg_to_register_object($new$$reg); | |
| 2817 | |
| 2818 MacroAssembler _masm(&cbuf); | |
| 2819 __ mov(Rnew, O7); | |
| 2820 __ cas(Rmem, Rold, O7); | |
| 2821 __ cmp( Rold, O7 ); | |
| 2822 %} | |
| 2823 | |
| 2824 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
| 2825 Register Rres = reg_to_register_object($res$$reg); | |
| 2826 | |
| 2827 MacroAssembler _masm(&cbuf); | |
| 2828 __ mov(1, Rres); | |
| 2829 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
| 2830 %} | |
| 2831 | |
| 2832 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
| 2833 Register Rres = reg_to_register_object($res$$reg); | |
| 2834 | |
| 2835 MacroAssembler _masm(&cbuf); | |
| 2836 __ mov(1, Rres); | |
| 2837 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
| 2838 %} | |
| 2839 | |
| 2840 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
| 2841 MacroAssembler _masm(&cbuf); | |
| 2842 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2843 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
| 2844 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
| 2845 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
| 2846 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
| 2847 | |
| 2848 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
| 2849 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
| 2850 %} | |
| 2851 | |
| 2852 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
| 2853 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ | |
| 2854 MacroAssembler _masm(&cbuf); | |
| 2855 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); | |
| 2856 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); | |
| 2857 Register base_pointer_arg = reg_to_register_object($base$$reg); | |
| 2858 | |
| 2859 Label loop; | |
| 2860 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
| 2861 | |
| 2862 // Loop and clear, walking backwards through the array. | |
| 2863 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
| 2864 __ bind(loop); | |
| 2865 __ deccc(nof_bytes_tmp, 8); | |
| 2866 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
| 2867 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
| 2868 // %%%% this mini-loop must not cross a cache boundary! | |
| 2869 %} | |
| 2870 | |
| 2871 | |
|
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2872 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
| 0 | 2873 Label Ldone, Lloop; |
| 2874 MacroAssembler _masm(&cbuf); | |
| 2875 | |
| 2876 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2877 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
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2878 Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
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2879 Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
| 0 | 2880 Register result_reg = reg_to_register_object($result$$reg); |
| 2881 | |
|
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2882 assert(result_reg != str1_reg && |
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2883 result_reg != str2_reg && |
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2884 result_reg != cnt1_reg && |
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2885 result_reg != cnt2_reg , |
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2886 "need different registers"); |
| 0 | 2887 |
| 2888 // Compute the minimum of the string lengths(str1_reg) and the | |
| 2889 // difference of the string lengths (stack) | |
| 2890 | |
| 2891 // See if the lengths are different, and calculate min in str1_reg. | |
| 2892 // Stash diff in O7 in case we need it for a tie-breaker. | |
| 2893 Label Lskip; | |
|
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2894 __ subcc(cnt1_reg, cnt2_reg, O7); |
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2895 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2896 __ br(Assembler::greater, true, Assembler::pt, Lskip); |
|
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2897 // cnt2 is shorter, so use its count: |
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2898 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2899 __ bind(Lskip); |
| 2900 | |
|
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2901 // reallocate cnt1_reg, cnt2_reg, result_reg |
| 0 | 2902 // Note: limit_reg holds the string length pre-scaled by 2 |
|
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2903 Register limit_reg = cnt1_reg; |
|
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2904 Register chr2_reg = cnt2_reg; |
| 0 | 2905 Register chr1_reg = result_reg; |
|
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2906 // str{12} are the base pointers |
| 0 | 2907 |
| 2908 // Is the minimum length zero? | |
| 2909 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
| 2910 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2911 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2912 | |
| 2913 // Load first characters | |
|
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2914 __ lduh(str1_reg, 0, chr1_reg); |
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2915 __ lduh(str2_reg, 0, chr2_reg); |
| 0 | 2916 |
| 2917 // Compare first characters | |
| 2918 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
| 2919 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2920 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2921 __ delayed()->nop(); | |
| 2922 | |
| 2923 { | |
| 2924 // Check after comparing first character to see if strings are equivalent | |
| 2925 Label LSkip2; | |
| 2926 // Check if the strings start at same location | |
|
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2927 __ cmp(str1_reg, str2_reg); |
| 0 | 2928 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
| 2929 __ delayed()->nop(); | |
| 2930 | |
| 2931 // Check if the length difference is zero (in O7) | |
| 2932 __ cmp(G0, O7); | |
| 2933 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2934 __ delayed()->mov(G0, result_reg); // result is zero | |
| 2935 | |
| 2936 // Strings might not be equal | |
| 2937 __ bind(LSkip2); | |
| 2938 } | |
| 2939 | |
| 2940 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); | |
| 2941 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2942 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2943 | |
|
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2944 // Shift str1_reg and str2_reg to the end of the arrays, negate limit |
|
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2945 __ add(str1_reg, limit_reg, str1_reg); |
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2946 __ add(str2_reg, limit_reg, str2_reg); |
| 0 | 2947 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
| 2948 | |
| 2949 // Compare the rest of the characters | |
|
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2950 __ lduh(str1_reg, limit_reg, chr1_reg); |
| 0 | 2951 __ bind(Lloop); |
|
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2952 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
|
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2953 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 0 | 2954 __ subcc(chr1_reg, chr2_reg, chr1_reg); |
| 2955 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2956 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2957 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
| 2958 // annul LDUH if branch is not taken to prevent access past end of string | |
| 2959 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
|
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2960 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 0 | 2961 |
| 2962 // If strings are equal up to min length, return the length difference. | |
| 2963 __ mov(O7, result_reg); | |
| 2964 | |
| 2965 // Otherwise, return the difference between the first mismatched chars. | |
| 2966 __ bind(Ldone); | |
| 2967 %} | |
| 2968 | |
|
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2969 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
|
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2970 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
| 681 | 2971 MacroAssembler _masm(&cbuf); |
| 2972 | |
| 2973 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2974 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
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2975 Register cnt_reg = reg_to_register_object($cnt$$reg); |
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2976 Register tmp1_reg = O7; |
| 681 | 2977 Register result_reg = reg_to_register_object($result$$reg); |
| 2978 | |
|
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2979 assert(result_reg != str1_reg && |
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2980 result_reg != str2_reg && |
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2981 result_reg != cnt_reg && |
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2982 result_reg != tmp1_reg , |
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2983 "need different registers"); |
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2984 |
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2985 __ cmp(str1_reg, str2_reg); //same char[] ? |
| 681 | 2986 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 2987 __ delayed()->add(G0, 1, result_reg); | |
| 2988 | |
|
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2989 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone); |
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2990 __ delayed()->add(G0, 1, result_reg); // count == 0 |
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2991 |
| 681 | 2992 //rename registers |
|
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2993 Register limit_reg = cnt_reg; |
| 681 | 2994 Register chr1_reg = result_reg; |
|
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2995 Register chr2_reg = tmp1_reg; |
| 681 | 2996 |
| 2997 //check for alignment and position the pointers to the ends | |
|
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2998 __ or3(str1_reg, str2_reg, chr1_reg); |
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2999 __ andcc(chr1_reg, 0x3, chr1_reg); |
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3000 // notZero means at least one not 4-byte aligned. |
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3001 // We could optimize the case when both arrays are not aligned |
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3002 // but it is not frequent case and it requires additional checks. |
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3003 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
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3004 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
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3005 |
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3006 // Compare char[] arrays aligned to 4 bytes. |
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3007 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
|
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3008 chr1_reg, chr2_reg, Ldone); |
| 681 | 3009 __ ba(false,Ldone); |
| 3010 __ delayed()->add(G0, 1, result_reg); | |
| 3011 | |
|
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3012 // char by char compare |
| 681 | 3013 __ bind(Lchar); |
|
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3014 __ add(str1_reg, limit_reg, str1_reg); |
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3015 __ add(str2_reg, limit_reg, str2_reg); |
| 681 | 3016 __ neg(limit_reg); //negate count |
| 3017 | |
|
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3018 __ lduh(str1_reg, limit_reg, chr1_reg); |
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3019 // Lchar_loop |
| 681 | 3020 __ bind(Lchar_loop); |
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3021 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 681 | 3022 __ cmp(chr1_reg, chr2_reg); |
| 3023 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
| 3024 __ delayed()->mov(G0, result_reg); //not equal | |
| 3025 __ inccc(limit_reg, sizeof(jchar)); | |
| 3026 // annul LDUH if branch is not taken to prevent access past end of string | |
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3027 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
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3028 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 681 | 3029 |
| 3030 __ add(G0, 1, result_reg); //equal | |
| 3031 | |
| 3032 __ bind(Ldone); | |
| 3033 %} | |
| 3034 | |
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3035 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
| 681 | 3036 Label Lvector, Ldone, Lloop; |
| 3037 MacroAssembler _masm(&cbuf); | |
| 3038 | |
| 3039 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
| 3040 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
| 3041 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
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3042 Register tmp2_reg = O7; |
| 681 | 3043 Register result_reg = reg_to_register_object($result$$reg); |
| 3044 | |
| 3045 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
| 3046 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
| 3047 | |
| 3048 // return true if the same array | |
| 3049 __ cmp(ary1_reg, ary2_reg); | |
| 1016 | 3050 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 681 | 3051 __ delayed()->add(G0, 1, result_reg); // equal |
| 3052 | |
| 3053 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
| 3054 __ delayed()->mov(G0, result_reg); // not equal | |
| 3055 | |
| 3056 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
| 3057 __ delayed()->mov(G0, result_reg); // not equal | |
| 3058 | |
| 3059 //load the lengths of arrays | |
| 727 | 3060 __ ld(Address(ary1_reg, length_offset), tmp1_reg); |
| 3061 __ ld(Address(ary2_reg, length_offset), tmp2_reg); | |
| 681 | 3062 |
| 3063 // return false if the two arrays are not equal length | |
| 3064 __ cmp(tmp1_reg, tmp2_reg); | |
| 3065 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
| 3066 __ delayed()->mov(G0, result_reg); // not equal | |
| 3067 | |
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3068 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone); |
| 681 | 3069 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
| 3070 | |
| 3071 // load array addresses | |
| 3072 __ add(ary1_reg, base_offset, ary1_reg); | |
| 3073 __ add(ary2_reg, base_offset, ary2_reg); | |
| 3074 | |
| 3075 // renaming registers | |
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3076 Register chr1_reg = result_reg; // for characters in ary1 |
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3077 Register chr2_reg = tmp2_reg; // for characters in ary2 |
| 681 | 3078 Register limit_reg = tmp1_reg; // length |
| 3079 | |
| 3080 // set byte count | |
| 3081 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
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3082 |
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3083 // Compare char[] arrays aligned to 4 bytes. |
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3084 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
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3085 chr1_reg, chr2_reg, Ldone); |
| 681 | 3086 __ add(G0, 1, result_reg); // equals |
| 3087 | |
| 3088 __ bind(Ldone); | |
| 3089 %} | |
| 3090 | |
| 0 | 3091 enc_class enc_rethrow() %{ |
| 1748 | 3092 cbuf.set_insts_mark(); |
| 0 | 3093 Register temp_reg = G3; |
| 727 | 3094 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
| 0 | 3095 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
| 3096 MacroAssembler _masm(&cbuf); | |
| 3097 #ifdef ASSERT | |
| 3098 __ save_frame(0); | |
| 727 | 3099 AddressLiteral last_rethrow_addrlit(&last_rethrow); |
| 3100 __ sethi(last_rethrow_addrlit, L1); | |
| 3101 Address addr(L1, last_rethrow_addrlit.low10()); | |
| 0 | 3102 __ get_pc(L2); |
| 3103 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to | |
| 727 | 3104 __ st_ptr(L2, addr); |
| 0 | 3105 __ restore(); |
| 3106 #endif | |
| 727 | 3107 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
| 0 | 3108 __ delayed()->nop(); |
| 3109 %} | |
| 3110 | |
| 3111 enc_class emit_mem_nop() %{ | |
| 3112 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
| 1748 | 3113 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); |
| 0 | 3114 %} |
| 3115 | |
| 3116 enc_class emit_fadd_nop() %{ | |
| 3117 // Generates the instruction FMOVS f31,f31 | |
| 1748 | 3118 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); |
| 0 | 3119 %} |
| 3120 | |
| 3121 enc_class emit_br_nop() %{ | |
| 3122 // Generates the instruction BPN,PN . | |
| 1748 | 3123 cbuf.insts()->emit_int32((unsigned int) 0x00400000); |
| 0 | 3124 %} |
| 3125 | |
| 3126 enc_class enc_membar_acquire %{ | |
| 3127 MacroAssembler _masm(&cbuf); | |
| 3128 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
| 3129 %} | |
| 3130 | |
| 3131 enc_class enc_membar_release %{ | |
| 3132 MacroAssembler _masm(&cbuf); | |
| 3133 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
| 3134 %} | |
| 3135 | |
| 3136 enc_class enc_membar_volatile %{ | |
| 3137 MacroAssembler _masm(&cbuf); | |
| 3138 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
| 3139 %} | |
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3140 |
| 0 | 3141 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ |
| 3142 MacroAssembler _masm(&cbuf); | |
| 3143 Register src_reg = reg_to_register_object($src$$reg); | |
| 3144 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3145 __ sllx(src_reg, 56, dst_reg); | |
| 3146 __ srlx(dst_reg, 8, O7); | |
| 3147 __ or3 (dst_reg, O7, dst_reg); | |
| 3148 __ srlx(dst_reg, 16, O7); | |
| 3149 __ or3 (dst_reg, O7, dst_reg); | |
| 3150 __ srlx(dst_reg, 32, O7); | |
| 3151 __ or3 (dst_reg, O7, dst_reg); | |
| 3152 %} | |
| 3153 | |
| 3154 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ | |
| 3155 MacroAssembler _masm(&cbuf); | |
| 3156 Register src_reg = reg_to_register_object($src$$reg); | |
| 3157 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3158 __ sll(src_reg, 24, dst_reg); | |
| 3159 __ srl(dst_reg, 8, O7); | |
| 3160 __ or3(dst_reg, O7, dst_reg); | |
| 3161 __ srl(dst_reg, 16, O7); | |
| 3162 __ or3(dst_reg, O7, dst_reg); | |
| 3163 %} | |
| 3164 | |
| 3165 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ | |
| 3166 MacroAssembler _masm(&cbuf); | |
| 3167 Register src_reg = reg_to_register_object($src$$reg); | |
| 3168 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3169 __ sllx(src_reg, 48, dst_reg); | |
| 3170 __ srlx(dst_reg, 16, O7); | |
| 3171 __ or3 (dst_reg, O7, dst_reg); | |
| 3172 __ srlx(dst_reg, 32, O7); | |
| 3173 __ or3 (dst_reg, O7, dst_reg); | |
| 3174 %} | |
| 3175 | |
| 3176 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ | |
| 3177 MacroAssembler _masm(&cbuf); | |
| 3178 Register src_reg = reg_to_register_object($src$$reg); | |
| 3179 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3180 __ sllx(src_reg, 32, dst_reg); | |
| 3181 __ srlx(dst_reg, 32, O7); | |
| 3182 __ or3 (dst_reg, O7, dst_reg); | |
| 3183 %} | |
| 3184 | |
| 3185 %} | |
| 3186 | |
| 3187 //----------FRAME-------------------------------------------------------------- | |
| 3188 // Definition of frame structure and management information. | |
| 3189 // | |
| 3190 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3191 // | (to get allocators register number | |
| 3192 // G Owned by | | v add VMRegImpl::stack0) | |
| 3193 // r CALLER | | | |
| 3194 // o | +--------+ pad to even-align allocators stack-slot | |
| 3195 // w V | pad0 | numbers; owned by CALLER | |
| 3196 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3197 // h ^ | in | 5 | |
| 3198 // | | args | 4 Holes in incoming args owned by SELF | |
| 3199 // | | | | 3 | |
| 3200 // | | +--------+ | |
| 3201 // V | | old out| Empty on Intel, window on Sparc | |
| 3202 // | old |preserve| Must be even aligned. | |
| 3203 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
| 3204 // | | in | 3 area for Intel ret address | |
| 3205 // Owned by |preserve| Empty on Sparc. | |
| 3206 // SELF +--------+ | |
| 3207 // | | pad2 | 2 pad to align old SP | |
| 3208 // | +--------+ 1 | |
| 3209 // | | locks | 0 | |
| 3210 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
| 3211 // | | pad1 | 11 pad to align new SP | |
| 3212 // | +--------+ | |
| 3213 // | | | 10 | |
| 3214 // | | spills | 9 spills | |
| 3215 // V | | 8 (pad0 slot for callee) | |
| 3216 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3217 // ^ | out | 7 | |
| 3218 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3219 // Owned by +--------+ | |
| 3220 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3221 // | new |preserve| Must be even-aligned. | |
| 3222 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3223 // | | | | |
| 3224 // | |
| 3225 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3226 // known from SELF's arguments and the Java calling convention. | |
| 3227 // Region 6-7 is determined per call site. | |
| 3228 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3229 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3230 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3231 // incoming area, as the Java calling convention is completely under | |
| 3232 // the control of the AD file. Doubles can be sorted and packed to | |
| 3233 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3234 // varargs C calling conventions. | |
| 3235 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3236 // even aligned with pad0 as needed. | |
| 3237 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3238 // region 6-11 is even aligned; it may be padded out more so that | |
| 3239 // the region from SP to FP meets the minimum stack alignment. | |
| 3240 | |
| 3241 frame %{ | |
| 3242 // What direction does stack grow in (assumed to be same for native & Java) | |
| 3243 stack_direction(TOWARDS_LOW); | |
| 3244 | |
| 3245 // These two registers define part of the calling convention | |
| 3246 // between compiled code and the interpreter. | |
| 3247 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C | |
| 3248 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter | |
| 3249 | |
| 3250 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3251 cisc_spilling_operand_name(indOffset); | |
| 3252 | |
| 3253 // Number of stack slots consumed by a Monitor enter | |
| 3254 #ifdef _LP64 | |
| 3255 sync_stack_slots(2); | |
| 3256 #else | |
| 3257 sync_stack_slots(1); | |
| 3258 #endif | |
| 3259 | |
| 3260 // Compiled code's Frame Pointer | |
| 3261 frame_pointer(R_SP); | |
| 3262 | |
| 3263 // Stack alignment requirement | |
| 3264 stack_alignment(StackAlignmentInBytes); | |
| 3265 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
| 3266 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
| 3267 | |
| 3268 // Number of stack slots between incoming argument block and the start of | |
| 3269 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3270 // EPILOG must remove this many slots. | |
| 3271 in_preserve_stack_slots(0); | |
| 3272 | |
| 3273 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3274 // for calls to C. Supports the var-args backing area for register parms. | |
| 3275 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
| 3276 #ifdef _LP64 | |
| 3277 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
| 3278 varargs_C_out_slots_killed(12); | |
| 3279 #else | |
| 3280 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
| 3281 varargs_C_out_slots_killed( 7); | |
| 3282 #endif | |
| 3283 | |
| 3284 // The after-PROLOG location of the return address. Location of | |
| 3285 // return address specifies a type (REG or STACK) and a number | |
| 3286 // representing the register number (i.e. - use a register name) or | |
| 3287 // stack slot. | |
| 3288 return_addr(REG R_I7); // Ret Addr is in register I7 | |
| 3289 | |
| 3290 // Body of function which returns an OptoRegs array locating | |
| 3291 // arguments either in registers or in stack slots for calling | |
| 3292 // java | |
| 3293 calling_convention %{ | |
| 3294 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
| 3295 | |
| 3296 %} | |
| 3297 | |
| 3298 // Body of function which returns an OptoRegs array locating | |
| 3299 // arguments either in registers or in stack slots for callin | |
| 3300 // C. | |
| 3301 c_calling_convention %{ | |
| 3302 // This is obviously always outgoing | |
| 3303 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 3304 %} | |
| 3305 | |
| 3306 // Location of native (C/C++) and interpreter return values. This is specified to | |
| 3307 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
| 3308 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
| 3309 // to and from the register pairs is done by the appropriate call and epilog | |
| 3310 // opcodes. This simplifies the register allocator. | |
| 3311 c_return_value %{ | |
| 3312 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3313 #ifdef _LP64 | |
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3314 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3315 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3316 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3317 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3318 #else // !_LP64 |
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3319 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3320 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
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3321 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3322 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
| 0 | 3323 #endif |
| 3324 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3325 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3326 %} | |
| 3327 | |
| 3328 // Location of compiled Java return values. Same as C | |
| 3329 return_value %{ | |
| 3330 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3331 #ifdef _LP64 | |
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3332 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3333 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3334 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3335 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3336 #else // !_LP64 |
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3337 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3338 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
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3339 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3340 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
| 0 | 3341 #endif |
| 3342 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3343 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3344 %} | |
| 3345 | |
| 3346 %} | |
| 3347 | |
| 3348 | |
| 3349 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3350 //----------Operand Attributes------------------------------------------------- | |
| 3351 op_attrib op_cost(1); // Required cost attribute | |
| 3352 | |
| 3353 //----------Instruction Attributes--------------------------------------------- | |
| 3354 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
| 3355 ins_attrib ins_size(32); // Required size attribute (in bits) | |
| 3356 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
| 3357 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 3358 // non-matching short branch variant of some | |
| 3359 // long branch? | |
| 3360 | |
| 3361 //----------OPERANDS----------------------------------------------------------- | |
| 3362 // Operand definitions must precede instruction definitions for correct parsing | |
| 3363 // in the ADLC because operands constitute user defined types which are used in | |
| 3364 // instruction definitions. | |
| 3365 | |
| 3366 //----------Simple Operands---------------------------------------------------- | |
| 3367 // Immediate Operands | |
| 3368 // Integer Immediate: 32-bit | |
| 3369 operand immI() %{ | |
| 3370 match(ConI); | |
| 3371 | |
| 3372 op_cost(0); | |
| 3373 // formats are generated automatically for constants and base registers | |
| 3374 format %{ %} | |
| 3375 interface(CONST_INTER); | |
| 3376 %} | |
| 3377 | |
| 824 | 3378 // Integer Immediate: 8-bit |
| 3379 operand immI8() %{ | |
| 3380 predicate(Assembler::is_simm(n->get_int(), 8)); | |
| 3381 match(ConI); | |
| 3382 op_cost(0); | |
| 3383 format %{ %} | |
| 3384 interface(CONST_INTER); | |
| 3385 %} | |
| 3386 | |
| 0 | 3387 // Integer Immediate: 13-bit |
| 3388 operand immI13() %{ | |
| 3389 predicate(Assembler::is_simm13(n->get_int())); | |
| 3390 match(ConI); | |
| 3391 op_cost(0); | |
| 3392 | |
| 3393 format %{ %} | |
| 3394 interface(CONST_INTER); | |
| 3395 %} | |
| 3396 | |
| 785 | 3397 // Integer Immediate: 13-bit minus 7 |
| 3398 operand immI13m7() %{ | |
| 3399 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); | |
| 3400 match(ConI); | |
| 3401 op_cost(0); | |
| 3402 | |
| 3403 format %{ %} | |
| 3404 interface(CONST_INTER); | |
| 3405 %} | |
| 3406 | |
| 824 | 3407 // Integer Immediate: 16-bit |
| 3408 operand immI16() %{ | |
| 3409 predicate(Assembler::is_simm(n->get_int(), 16)); | |
| 3410 match(ConI); | |
| 3411 op_cost(0); | |
| 3412 format %{ %} | |
| 3413 interface(CONST_INTER); | |
| 3414 %} | |
| 3415 | |
| 0 | 3416 // Unsigned (positive) Integer Immediate: 13-bit |
| 3417 operand immU13() %{ | |
| 3418 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | |
| 3419 match(ConI); | |
| 3420 op_cost(0); | |
| 3421 | |
| 3422 format %{ %} | |
| 3423 interface(CONST_INTER); | |
| 3424 %} | |
| 3425 | |
| 3426 // Integer Immediate: 6-bit | |
| 3427 operand immU6() %{ | |
| 3428 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
| 3429 match(ConI); | |
| 3430 op_cost(0); | |
| 3431 format %{ %} | |
| 3432 interface(CONST_INTER); | |
| 3433 %} | |
| 3434 | |
| 3435 // Integer Immediate: 11-bit | |
| 3436 operand immI11() %{ | |
| 3437 predicate(Assembler::is_simm(n->get_int(),11)); | |
| 3438 match(ConI); | |
| 3439 op_cost(0); | |
| 3440 format %{ %} | |
| 3441 interface(CONST_INTER); | |
| 3442 %} | |
| 3443 | |
| 3444 // Integer Immediate: 0-bit | |
| 3445 operand immI0() %{ | |
| 3446 predicate(n->get_int() == 0); | |
| 3447 match(ConI); | |
| 3448 op_cost(0); | |
| 3449 | |
| 3450 format %{ %} | |
| 3451 interface(CONST_INTER); | |
| 3452 %} | |
| 3453 | |
| 3454 // Integer Immediate: the value 10 | |
| 3455 operand immI10() %{ | |
| 3456 predicate(n->get_int() == 10); | |
| 3457 match(ConI); | |
| 3458 op_cost(0); | |
| 3459 | |
| 3460 format %{ %} | |
| 3461 interface(CONST_INTER); | |
| 3462 %} | |
| 3463 | |
| 3464 // Integer Immediate: the values 0-31 | |
| 3465 operand immU5() %{ | |
| 3466 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
| 3467 match(ConI); | |
| 3468 op_cost(0); | |
| 3469 | |
| 3470 format %{ %} | |
| 3471 interface(CONST_INTER); | |
| 3472 %} | |
| 3473 | |
| 3474 // Integer Immediate: the values 1-31 | |
| 3475 operand immI_1_31() %{ | |
| 3476 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
| 3477 match(ConI); | |
| 3478 op_cost(0); | |
| 3479 | |
| 3480 format %{ %} | |
| 3481 interface(CONST_INTER); | |
| 3482 %} | |
| 3483 | |
| 3484 // Integer Immediate: the values 32-63 | |
| 3485 operand immI_32_63() %{ | |
| 3486 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
| 3487 match(ConI); | |
| 3488 op_cost(0); | |
| 3489 | |
| 3490 format %{ %} | |
| 3491 interface(CONST_INTER); | |
| 3492 %} | |
| 3493 | |
| 785 | 3494 // Immediates for special shifts (sign extend) |
| 3495 | |
| 3496 // Integer Immediate: the value 16 | |
| 3497 operand immI_16() %{ | |
| 3498 predicate(n->get_int() == 16); | |
| 3499 match(ConI); | |
| 3500 op_cost(0); | |
| 3501 | |
| 3502 format %{ %} | |
| 3503 interface(CONST_INTER); | |
| 3504 %} | |
| 3505 | |
| 3506 // Integer Immediate: the value 24 | |
| 3507 operand immI_24() %{ | |
| 3508 predicate(n->get_int() == 24); | |
| 3509 match(ConI); | |
| 3510 op_cost(0); | |
| 3511 | |
| 3512 format %{ %} | |
| 3513 interface(CONST_INTER); | |
| 3514 %} | |
| 3515 | |
| 0 | 3516 // Integer Immediate: the value 255 |
| 3517 operand immI_255() %{ | |
| 3518 predicate( n->get_int() == 255 ); | |
| 3519 match(ConI); | |
| 3520 op_cost(0); | |
| 3521 | |
| 3522 format %{ %} | |
| 3523 interface(CONST_INTER); | |
| 3524 %} | |
| 3525 | |
| 785 | 3526 // Integer Immediate: the value 65535 |
| 3527 operand immI_65535() %{ | |
| 3528 predicate(n->get_int() == 65535); | |
| 3529 match(ConI); | |
| 3530 op_cost(0); | |
| 3531 | |
| 3532 format %{ %} | |
| 3533 interface(CONST_INTER); | |
| 3534 %} | |
| 3535 | |
| 0 | 3536 // Long Immediate: the value FF |
| 3537 operand immL_FF() %{ | |
| 3538 predicate( n->get_long() == 0xFFL ); | |
| 3539 match(ConL); | |
| 3540 op_cost(0); | |
| 3541 | |
| 3542 format %{ %} | |
| 3543 interface(CONST_INTER); | |
| 3544 %} | |
| 3545 | |
| 3546 // Long Immediate: the value FFFF | |
| 3547 operand immL_FFFF() %{ | |
| 3548 predicate( n->get_long() == 0xFFFFL ); | |
| 3549 match(ConL); | |
| 3550 op_cost(0); | |
| 3551 | |
| 3552 format %{ %} | |
| 3553 interface(CONST_INTER); | |
| 3554 %} | |
| 3555 | |
| 3556 // Pointer Immediate: 32 or 64-bit | |
| 3557 operand immP() %{ | |
| 3558 match(ConP); | |
| 3559 | |
| 3560 op_cost(5); | |
| 3561 // formats are generated automatically for constants and base registers | |
| 3562 format %{ %} | |
| 3563 interface(CONST_INTER); | |
| 3564 %} | |
| 3565 | |
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3566 #ifdef _LP64 |
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3567 // Pointer Immediate: 64-bit |
| 2008 | 3568 operand immP_set() %{ |
| 2080 | 3569 predicate(!VM_Version::is_niagara_plus()); |
| 2008 | 3570 match(ConP); |
| 3571 | |
| 3572 op_cost(5); | |
| 3573 // formats are generated automatically for constants and base registers | |
| 3574 format %{ %} | |
| 3575 interface(CONST_INTER); | |
| 3576 %} | |
| 3577 | |
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3578 // Pointer Immediate: 64-bit |
| 2008 | 3579 // From Niagara2 processors on a load should be better than materializing. |
| 3580 operand immP_load() %{ | |
| 2080 | 3581 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); |
| 2008 | 3582 match(ConP); |
| 3583 | |
| 3584 op_cost(5); | |
| 3585 // formats are generated automatically for constants and base registers | |
| 3586 format %{ %} | |
| 3587 interface(CONST_INTER); | |
| 3588 %} | |
| 3589 | |
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3590 // Pointer Immediate: 64-bit |
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3591 operand immP_no_oop_cheap() %{ |
| 2080 | 3592 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); |
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3593 match(ConP); |
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3594 |
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3595 op_cost(5); |
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3596 // formats are generated automatically for constants and base registers |
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3597 format %{ %} |
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3598 interface(CONST_INTER); |
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3599 %} |
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3600 #endif |
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3601 |
| 0 | 3602 operand immP13() %{ |
| 3603 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
| 3604 match(ConP); | |
| 3605 op_cost(0); | |
| 3606 | |
| 3607 format %{ %} | |
| 3608 interface(CONST_INTER); | |
| 3609 %} | |
| 3610 | |
| 3611 operand immP0() %{ | |
| 3612 predicate(n->get_ptr() == 0); | |
| 3613 match(ConP); | |
| 3614 op_cost(0); | |
| 3615 | |
| 3616 format %{ %} | |
| 3617 interface(CONST_INTER); | |
| 3618 %} | |
| 3619 | |
| 3620 operand immP_poll() %{ | |
| 3621 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
| 3622 match(ConP); | |
| 3623 | |
| 3624 // formats are generated automatically for constants and base registers | |
| 3625 format %{ %} | |
| 3626 interface(CONST_INTER); | |
| 3627 %} | |
| 3628 | |
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3629 // Pointer Immediate |
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3630 operand immN() |
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3631 %{ |
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3632 match(ConN); |
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3633 |
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3634 op_cost(10); |
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3635 format %{ %} |
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3636 interface(CONST_INTER); |
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3637 %} |
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3638 |
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3639 // NULL Pointer Immediate |
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3640 operand immN0() |
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3641 %{ |
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3642 predicate(n->get_narrowcon() == 0); |
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3643 match(ConN); |
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3644 |
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3645 op_cost(0); |
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3646 format %{ %} |
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3647 interface(CONST_INTER); |
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3648 %} |
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3649 |
| 0 | 3650 operand immL() %{ |
| 3651 match(ConL); | |
| 3652 op_cost(40); | |
| 3653 // formats are generated automatically for constants and base registers | |
| 3654 format %{ %} | |
| 3655 interface(CONST_INTER); | |
| 3656 %} | |
| 3657 | |
| 3658 operand immL0() %{ | |
| 3659 predicate(n->get_long() == 0L); | |
| 3660 match(ConL); | |
| 3661 op_cost(0); | |
| 3662 // formats are generated automatically for constants and base registers | |
| 3663 format %{ %} | |
| 3664 interface(CONST_INTER); | |
| 3665 %} | |
| 3666 | |
| 3667 // Long Immediate: 13-bit | |
| 3668 operand immL13() %{ | |
| 3669 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
| 3670 match(ConL); | |
| 3671 op_cost(0); | |
| 3672 | |
| 3673 format %{ %} | |
| 3674 interface(CONST_INTER); | |
| 3675 %} | |
| 3676 | |
| 785 | 3677 // Long Immediate: 13-bit minus 7 |
| 3678 operand immL13m7() %{ | |
| 3679 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); | |
| 3680 match(ConL); | |
| 3681 op_cost(0); | |
| 3682 | |
| 3683 format %{ %} | |
| 3684 interface(CONST_INTER); | |
| 3685 %} | |
| 3686 | |
| 0 | 3687 // Long Immediate: low 32-bit mask |
| 3688 operand immL_32bits() %{ | |
| 3689 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3690 match(ConL); | |
| 3691 op_cost(0); | |
| 3692 | |
| 3693 format %{ %} | |
| 3694 interface(CONST_INTER); | |
| 3695 %} | |
| 3696 | |
| 2008 | 3697 // Long Immediate: cheap (materialize in <= 3 instructions) |
| 3698 operand immL_cheap() %{ | |
| 2080 | 3699 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); |
| 2008 | 3700 match(ConL); |
| 3701 op_cost(0); | |
| 3702 | |
| 3703 format %{ %} | |
| 3704 interface(CONST_INTER); | |
| 3705 %} | |
| 3706 | |
| 3707 // Long Immediate: expensive (materialize in > 3 instructions) | |
| 3708 operand immL_expensive() %{ | |
| 2080 | 3709 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3); |
| 2008 | 3710 match(ConL); |
| 3711 op_cost(0); | |
| 3712 | |
| 3713 format %{ %} | |
| 3714 interface(CONST_INTER); | |
| 3715 %} | |
| 3716 | |
| 0 | 3717 // Double Immediate |
| 3718 operand immD() %{ | |
| 3719 match(ConD); | |
| 3720 | |
| 3721 op_cost(40); | |
| 3722 format %{ %} | |
| 3723 interface(CONST_INTER); | |
| 3724 %} | |
| 3725 | |
| 3726 operand immD0() %{ | |
| 3727 #ifdef _LP64 | |
| 3728 // on 64-bit architectures this comparision is faster | |
| 3729 predicate(jlong_cast(n->getd()) == 0); | |
| 3730 #else | |
| 3731 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
| 3732 #endif | |
| 3733 match(ConD); | |
| 3734 | |
| 3735 op_cost(0); | |
| 3736 format %{ %} | |
| 3737 interface(CONST_INTER); | |
| 3738 %} | |
| 3739 | |
| 3740 // Float Immediate | |
| 3741 operand immF() %{ | |
| 3742 match(ConF); | |
| 3743 | |
| 3744 op_cost(20); | |
| 3745 format %{ %} | |
| 3746 interface(CONST_INTER); | |
| 3747 %} | |
| 3748 | |
| 3749 // Float Immediate: 0 | |
| 3750 operand immF0() %{ | |
| 3751 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
| 3752 match(ConF); | |
| 3753 | |
| 3754 op_cost(0); | |
| 3755 format %{ %} | |
| 3756 interface(CONST_INTER); | |
| 3757 %} | |
| 3758 | |
| 3759 // Integer Register Operands | |
| 3760 // Integer Register | |
| 3761 operand iRegI() %{ | |
| 3762 constraint(ALLOC_IN_RC(int_reg)); | |
| 3763 match(RegI); | |
| 3764 | |
| 3765 match(notemp_iRegI); | |
| 3766 match(g1RegI); | |
| 3767 match(o0RegI); | |
| 3768 match(iRegIsafe); | |
| 3769 | |
| 3770 format %{ %} | |
| 3771 interface(REG_INTER); | |
| 3772 %} | |
| 3773 | |
| 3774 operand notemp_iRegI() %{ | |
| 3775 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
| 3776 match(RegI); | |
| 3777 | |
| 3778 match(o0RegI); | |
| 3779 | |
| 3780 format %{ %} | |
| 3781 interface(REG_INTER); | |
| 3782 %} | |
| 3783 | |
| 3784 operand o0RegI() %{ | |
| 3785 constraint(ALLOC_IN_RC(o0_regI)); | |
| 3786 match(iRegI); | |
| 3787 | |
| 3788 format %{ %} | |
| 3789 interface(REG_INTER); | |
| 3790 %} | |
| 3791 | |
| 3792 // Pointer Register | |
| 3793 operand iRegP() %{ | |
| 3794 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3795 match(RegP); | |
| 3796 | |
| 3797 match(lock_ptr_RegP); | |
| 3798 match(g1RegP); | |
| 3799 match(g2RegP); | |
| 3800 match(g3RegP); | |
| 3801 match(g4RegP); | |
| 3802 match(i0RegP); | |
| 3803 match(o0RegP); | |
| 3804 match(o1RegP); | |
| 3805 match(l7RegP); | |
| 3806 | |
| 3807 format %{ %} | |
| 3808 interface(REG_INTER); | |
| 3809 %} | |
| 3810 | |
| 3811 operand sp_ptr_RegP() %{ | |
| 3812 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 3813 match(RegP); | |
| 3814 match(iRegP); | |
| 3815 | |
| 3816 format %{ %} | |
| 3817 interface(REG_INTER); | |
| 3818 %} | |
| 3819 | |
| 3820 operand lock_ptr_RegP() %{ | |
| 3821 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
| 3822 match(RegP); | |
| 3823 match(i0RegP); | |
| 3824 match(o0RegP); | |
| 3825 match(o1RegP); | |
| 3826 match(l7RegP); | |
| 3827 | |
| 3828 format %{ %} | |
| 3829 interface(REG_INTER); | |
| 3830 %} | |
| 3831 | |
| 3832 operand g1RegP() %{ | |
| 3833 constraint(ALLOC_IN_RC(g1_regP)); | |
| 3834 match(iRegP); | |
| 3835 | |
| 3836 format %{ %} | |
| 3837 interface(REG_INTER); | |
| 3838 %} | |
| 3839 | |
| 3840 operand g2RegP() %{ | |
| 3841 constraint(ALLOC_IN_RC(g2_regP)); | |
| 3842 match(iRegP); | |
| 3843 | |
| 3844 format %{ %} | |
| 3845 interface(REG_INTER); | |
| 3846 %} | |
| 3847 | |
| 3848 operand g3RegP() %{ | |
| 3849 constraint(ALLOC_IN_RC(g3_regP)); | |
| 3850 match(iRegP); | |
| 3851 | |
| 3852 format %{ %} | |
| 3853 interface(REG_INTER); | |
| 3854 %} | |
| 3855 | |
| 3856 operand g1RegI() %{ | |
| 3857 constraint(ALLOC_IN_RC(g1_regI)); | |
| 3858 match(iRegI); | |
| 3859 | |
| 3860 format %{ %} | |
| 3861 interface(REG_INTER); | |
| 3862 %} | |
| 3863 | |
| 3864 operand g3RegI() %{ | |
| 3865 constraint(ALLOC_IN_RC(g3_regI)); | |
| 3866 match(iRegI); | |
| 3867 | |
| 3868 format %{ %} | |
| 3869 interface(REG_INTER); | |
| 3870 %} | |
| 3871 | |
| 3872 operand g4RegI() %{ | |
| 3873 constraint(ALLOC_IN_RC(g4_regI)); | |
| 3874 match(iRegI); | |
| 3875 | |
| 3876 format %{ %} | |
| 3877 interface(REG_INTER); | |
| 3878 %} | |
| 3879 | |
| 3880 operand g4RegP() %{ | |
| 3881 constraint(ALLOC_IN_RC(g4_regP)); | |
| 3882 match(iRegP); | |
| 3883 | |
| 3884 format %{ %} | |
| 3885 interface(REG_INTER); | |
| 3886 %} | |
| 3887 | |
| 3888 operand i0RegP() %{ | |
| 3889 constraint(ALLOC_IN_RC(i0_regP)); | |
| 3890 match(iRegP); | |
| 3891 | |
| 3892 format %{ %} | |
| 3893 interface(REG_INTER); | |
| 3894 %} | |
| 3895 | |
| 3896 operand o0RegP() %{ | |
| 3897 constraint(ALLOC_IN_RC(o0_regP)); | |
| 3898 match(iRegP); | |
| 3899 | |
| 3900 format %{ %} | |
| 3901 interface(REG_INTER); | |
| 3902 %} | |
| 3903 | |
| 3904 operand o1RegP() %{ | |
| 3905 constraint(ALLOC_IN_RC(o1_regP)); | |
| 3906 match(iRegP); | |
| 3907 | |
| 3908 format %{ %} | |
| 3909 interface(REG_INTER); | |
| 3910 %} | |
| 3911 | |
| 3912 operand o2RegP() %{ | |
| 3913 constraint(ALLOC_IN_RC(o2_regP)); | |
| 3914 match(iRegP); | |
| 3915 | |
| 3916 format %{ %} | |
| 3917 interface(REG_INTER); | |
| 3918 %} | |
| 3919 | |
| 3920 operand o7RegP() %{ | |
| 3921 constraint(ALLOC_IN_RC(o7_regP)); | |
| 3922 match(iRegP); | |
| 3923 | |
| 3924 format %{ %} | |
| 3925 interface(REG_INTER); | |
| 3926 %} | |
| 3927 | |
| 3928 operand l7RegP() %{ | |
| 3929 constraint(ALLOC_IN_RC(l7_regP)); | |
| 3930 match(iRegP); | |
| 3931 | |
| 3932 format %{ %} | |
| 3933 interface(REG_INTER); | |
| 3934 %} | |
| 3935 | |
| 3936 operand o7RegI() %{ | |
| 3937 constraint(ALLOC_IN_RC(o7_regI)); | |
| 3938 match(iRegI); | |
| 3939 | |
| 3940 format %{ %} | |
| 3941 interface(REG_INTER); | |
| 3942 %} | |
| 3943 | |
|
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3944 operand iRegN() %{ |
|
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3945 constraint(ALLOC_IN_RC(int_reg)); |
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3946 match(RegN); |
|
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3947 |
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3948 format %{ %} |
|
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3949 interface(REG_INTER); |
|
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3950 %} |
|
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3951 |
| 0 | 3952 // Long Register |
| 3953 operand iRegL() %{ | |
| 3954 constraint(ALLOC_IN_RC(long_reg)); | |
| 3955 match(RegL); | |
| 3956 | |
| 3957 format %{ %} | |
| 3958 interface(REG_INTER); | |
| 3959 %} | |
| 3960 | |
| 3961 operand o2RegL() %{ | |
| 3962 constraint(ALLOC_IN_RC(o2_regL)); | |
| 3963 match(iRegL); | |
| 3964 | |
| 3965 format %{ %} | |
| 3966 interface(REG_INTER); | |
| 3967 %} | |
| 3968 | |
| 3969 operand o7RegL() %{ | |
| 3970 constraint(ALLOC_IN_RC(o7_regL)); | |
| 3971 match(iRegL); | |
| 3972 | |
| 3973 format %{ %} | |
| 3974 interface(REG_INTER); | |
| 3975 %} | |
| 3976 | |
| 3977 operand g1RegL() %{ | |
| 3978 constraint(ALLOC_IN_RC(g1_regL)); | |
| 3979 match(iRegL); | |
| 3980 | |
| 3981 format %{ %} | |
| 3982 interface(REG_INTER); | |
| 3983 %} | |
| 3984 | |
|
420
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|
3985 operand g3RegL() %{ |
|
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3986 constraint(ALLOC_IN_RC(g3_regL)); |
|
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|
3987 match(iRegL); |
|
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|
3988 |
|
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|
3989 format %{ %} |
|
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|
3990 interface(REG_INTER); |
|
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|
3991 %} |
|
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|
3992 |
| 0 | 3993 // Int Register safe |
| 3994 // This is 64bit safe | |
| 3995 operand iRegIsafe() %{ | |
| 3996 constraint(ALLOC_IN_RC(long_reg)); | |
| 3997 | |
| 3998 match(iRegI); | |
| 3999 | |
| 4000 format %{ %} | |
| 4001 interface(REG_INTER); | |
| 4002 %} | |
| 4003 | |
| 4004 // Condition Code Flag Register | |
| 4005 operand flagsReg() %{ | |
| 4006 constraint(ALLOC_IN_RC(int_flags)); | |
| 4007 match(RegFlags); | |
| 4008 | |
| 4009 format %{ "ccr" %} // both ICC and XCC | |
| 4010 interface(REG_INTER); | |
| 4011 %} | |
| 4012 | |
| 4013 // Condition Code Register, unsigned comparisons. | |
| 4014 operand flagsRegU() %{ | |
| 4015 constraint(ALLOC_IN_RC(int_flags)); | |
| 4016 match(RegFlags); | |
| 4017 | |
| 4018 format %{ "icc_U" %} | |
| 4019 interface(REG_INTER); | |
| 4020 %} | |
| 4021 | |
| 4022 // Condition Code Register, pointer comparisons. | |
| 4023 operand flagsRegP() %{ | |
| 4024 constraint(ALLOC_IN_RC(int_flags)); | |
| 4025 match(RegFlags); | |
| 4026 | |
| 4027 #ifdef _LP64 | |
| 4028 format %{ "xcc_P" %} | |
| 4029 #else | |
| 4030 format %{ "icc_P" %} | |
| 4031 #endif | |
| 4032 interface(REG_INTER); | |
| 4033 %} | |
| 4034 | |
| 4035 // Condition Code Register, long comparisons. | |
| 4036 operand flagsRegL() %{ | |
| 4037 constraint(ALLOC_IN_RC(int_flags)); | |
| 4038 match(RegFlags); | |
| 4039 | |
| 4040 format %{ "xcc_L" %} | |
| 4041 interface(REG_INTER); | |
| 4042 %} | |
| 4043 | |
| 4044 // Condition Code Register, floating comparisons, unordered same as "less". | |
| 4045 operand flagsRegF() %{ | |
| 4046 constraint(ALLOC_IN_RC(float_flags)); | |
| 4047 match(RegFlags); | |
| 4048 match(flagsRegF0); | |
| 4049 | |
| 4050 format %{ %} | |
| 4051 interface(REG_INTER); | |
| 4052 %} | |
| 4053 | |
| 4054 operand flagsRegF0() %{ | |
| 4055 constraint(ALLOC_IN_RC(float_flag0)); | |
| 4056 match(RegFlags); | |
| 4057 | |
| 4058 format %{ %} | |
| 4059 interface(REG_INTER); | |
| 4060 %} | |
| 4061 | |
| 4062 | |
| 4063 // Condition Code Flag Register used by long compare | |
| 4064 operand flagsReg_long_LTGE() %{ | |
| 4065 constraint(ALLOC_IN_RC(int_flags)); | |
| 4066 match(RegFlags); | |
| 4067 format %{ "icc_LTGE" %} | |
| 4068 interface(REG_INTER); | |
| 4069 %} | |
| 4070 operand flagsReg_long_EQNE() %{ | |
| 4071 constraint(ALLOC_IN_RC(int_flags)); | |
| 4072 match(RegFlags); | |
| 4073 format %{ "icc_EQNE" %} | |
| 4074 interface(REG_INTER); | |
| 4075 %} | |
| 4076 operand flagsReg_long_LEGT() %{ | |
| 4077 constraint(ALLOC_IN_RC(int_flags)); | |
| 4078 match(RegFlags); | |
| 4079 format %{ "icc_LEGT" %} | |
| 4080 interface(REG_INTER); | |
| 4081 %} | |
| 4082 | |
| 4083 | |
| 4084 operand regD() %{ | |
| 4085 constraint(ALLOC_IN_RC(dflt_reg)); | |
| 4086 match(RegD); | |
| 4087 | |
| 551 | 4088 match(regD_low); |
| 4089 | |
| 0 | 4090 format %{ %} |
| 4091 interface(REG_INTER); | |
| 4092 %} | |
| 4093 | |
| 4094 operand regF() %{ | |
| 4095 constraint(ALLOC_IN_RC(sflt_reg)); | |
| 4096 match(RegF); | |
| 4097 | |
| 4098 format %{ %} | |
| 4099 interface(REG_INTER); | |
| 4100 %} | |
| 4101 | |
| 4102 operand regD_low() %{ | |
| 4103 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
| 551 | 4104 match(regD); |
| 0 | 4105 |
| 4106 format %{ %} | |
| 4107 interface(REG_INTER); | |
| 4108 %} | |
| 4109 | |
| 4110 // Special Registers | |
| 4111 | |
| 4112 // Method Register | |
| 4113 operand inline_cache_regP(iRegP reg) %{ | |
| 4114 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
| 4115 match(reg); | |
| 4116 format %{ %} | |
| 4117 interface(REG_INTER); | |
| 4118 %} | |
| 4119 | |
| 4120 operand interpreter_method_oop_regP(iRegP reg) %{ | |
| 4121 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
| 4122 match(reg); | |
| 4123 format %{ %} | |
| 4124 interface(REG_INTER); | |
| 4125 %} | |
| 4126 | |
| 4127 | |
| 4128 //----------Complex Operands--------------------------------------------------- | |
| 4129 // Indirect Memory Reference | |
| 4130 operand indirect(sp_ptr_RegP reg) %{ | |
| 4131 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4132 match(reg); | |
| 4133 | |
| 4134 op_cost(100); | |
| 4135 format %{ "[$reg]" %} | |
| 4136 interface(MEMORY_INTER) %{ | |
| 4137 base($reg); | |
| 4138 index(0x0); | |
| 4139 scale(0x0); | |
| 4140 disp(0x0); | |
| 4141 %} | |
| 4142 %} | |
| 4143 | |
| 785 | 4144 // Indirect with simm13 Offset |
| 0 | 4145 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
| 4146 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4147 match(AddP reg offset); | |
| 4148 | |
| 4149 op_cost(100); | |
| 4150 format %{ "[$reg + $offset]" %} | |
| 4151 interface(MEMORY_INTER) %{ | |
| 4152 base($reg); | |
| 4153 index(0x0); | |
| 4154 scale(0x0); | |
| 4155 disp($offset); | |
| 4156 %} | |
| 4157 %} | |
| 4158 | |
| 785 | 4159 // Indirect with simm13 Offset minus 7 |
| 4160 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ | |
| 4161 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4162 match(AddP reg offset); | |
| 4163 | |
| 4164 op_cost(100); | |
| 4165 format %{ "[$reg + $offset]" %} | |
| 4166 interface(MEMORY_INTER) %{ | |
| 4167 base($reg); | |
| 4168 index(0x0); | |
| 4169 scale(0x0); | |
| 4170 disp($offset); | |
| 4171 %} | |
| 4172 %} | |
| 4173 | |
| 0 | 4174 // Note: Intel has a swapped version also, like this: |
| 4175 //operand indOffsetX(iRegI reg, immP offset) %{ | |
| 4176 // constraint(ALLOC_IN_RC(int_reg)); | |
| 4177 // match(AddP offset reg); | |
| 4178 // | |
| 4179 // op_cost(100); | |
| 4180 // format %{ "[$reg + $offset]" %} | |
| 4181 // interface(MEMORY_INTER) %{ | |
| 4182 // base($reg); | |
| 4183 // index(0x0); | |
| 4184 // scale(0x0); | |
| 4185 // disp($offset); | |
| 4186 // %} | |
| 4187 //%} | |
| 4188 //// However, it doesn't make sense for SPARC, since | |
| 4189 // we have no particularly good way to embed oops in | |
| 4190 // single instructions. | |
| 4191 | |
| 4192 // Indirect with Register Index | |
| 4193 operand indIndex(iRegP addr, iRegX index) %{ | |
| 4194 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4195 match(AddP addr index); | |
| 4196 | |
| 4197 op_cost(100); | |
| 4198 format %{ "[$addr + $index]" %} | |
| 4199 interface(MEMORY_INTER) %{ | |
| 4200 base($addr); | |
| 4201 index($index); | |
| 4202 scale(0x0); | |
| 4203 disp(0x0); | |
| 4204 %} | |
| 4205 %} | |
| 4206 | |
| 4207 //----------Special Memory Operands-------------------------------------------- | |
| 4208 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4209 // values on the stack where a match requires a value to | |
| 4210 // flow through memory. | |
| 4211 operand stackSlotI(sRegI reg) %{ | |
| 4212 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4213 op_cost(100); | |
| 4214 //match(RegI); | |
| 4215 format %{ "[$reg]" %} | |
| 4216 interface(MEMORY_INTER) %{ | |
| 4217 base(0xE); // R_SP | |
| 4218 index(0x0); | |
| 4219 scale(0x0); | |
| 4220 disp($reg); // Stack Offset | |
| 4221 %} | |
| 4222 %} | |
| 4223 | |
| 4224 operand stackSlotP(sRegP reg) %{ | |
| 4225 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4226 op_cost(100); | |
| 4227 //match(RegP); | |
| 4228 format %{ "[$reg]" %} | |
| 4229 interface(MEMORY_INTER) %{ | |
| 4230 base(0xE); // R_SP | |
| 4231 index(0x0); | |
| 4232 scale(0x0); | |
| 4233 disp($reg); // Stack Offset | |
| 4234 %} | |
| 4235 %} | |
| 4236 | |
| 4237 operand stackSlotF(sRegF reg) %{ | |
| 4238 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4239 op_cost(100); | |
| 4240 //match(RegF); | |
| 4241 format %{ "[$reg]" %} | |
| 4242 interface(MEMORY_INTER) %{ | |
| 4243 base(0xE); // R_SP | |
| 4244 index(0x0); | |
| 4245 scale(0x0); | |
| 4246 disp($reg); // Stack Offset | |
| 4247 %} | |
| 4248 %} | |
| 4249 operand stackSlotD(sRegD reg) %{ | |
| 4250 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4251 op_cost(100); | |
| 4252 //match(RegD); | |
| 4253 format %{ "[$reg]" %} | |
| 4254 interface(MEMORY_INTER) %{ | |
| 4255 base(0xE); // R_SP | |
| 4256 index(0x0); | |
| 4257 scale(0x0); | |
| 4258 disp($reg); // Stack Offset | |
| 4259 %} | |
| 4260 %} | |
| 4261 operand stackSlotL(sRegL reg) %{ | |
| 4262 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4263 op_cost(100); | |
| 4264 //match(RegL); | |
| 4265 format %{ "[$reg]" %} | |
| 4266 interface(MEMORY_INTER) %{ | |
| 4267 base(0xE); // R_SP | |
| 4268 index(0x0); | |
| 4269 scale(0x0); | |
| 4270 disp($reg); // Stack Offset | |
| 4271 %} | |
| 4272 %} | |
| 4273 | |
| 4274 // Operands for expressing Control Flow | |
| 4275 // NOTE: Label is a predefined operand which should not be redefined in | |
| 4276 // the AD file. It is generically handled within the ADLC. | |
| 4277 | |
| 4278 //----------Conditional Branch Operands---------------------------------------- | |
| 4279 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4280 // the following set of codes: | |
| 4281 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4282 // | |
| 4283 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4284 // by the comparison instruction that sets a condition code flags register. | |
| 4285 // That result is represented by a flags operand whose subtype is appropriate | |
| 4286 // to the unsignedness (etc.) of the comparison. | |
| 4287 // | |
| 4288 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4289 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4290 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4291 | |
| 4292 operand cmpOp() %{ | |
| 4293 match(Bool); | |
| 4294 | |
| 4295 format %{ "" %} | |
| 4296 interface(COND_INTER) %{ | |
| 4297 equal(0x1); | |
| 4298 not_equal(0x9); | |
| 4299 less(0x3); | |
| 4300 greater_equal(0xB); | |
| 4301 less_equal(0x2); | |
| 4302 greater(0xA); | |
| 4303 %} | |
| 4304 %} | |
| 4305 | |
| 4306 // Comparison Op, unsigned | |
| 4307 operand cmpOpU() %{ | |
| 4308 match(Bool); | |
| 4309 | |
| 4310 format %{ "u" %} | |
| 4311 interface(COND_INTER) %{ | |
| 4312 equal(0x1); | |
| 4313 not_equal(0x9); | |
| 4314 less(0x5); | |
| 4315 greater_equal(0xD); | |
| 4316 less_equal(0x4); | |
| 4317 greater(0xC); | |
| 4318 %} | |
| 4319 %} | |
| 4320 | |
| 4321 // Comparison Op, pointer (same as unsigned) | |
| 4322 operand cmpOpP() %{ | |
| 4323 match(Bool); | |
| 4324 | |
| 4325 format %{ "p" %} | |
| 4326 interface(COND_INTER) %{ | |
| 4327 equal(0x1); | |
| 4328 not_equal(0x9); | |
| 4329 less(0x5); | |
| 4330 greater_equal(0xD); | |
| 4331 less_equal(0x4); | |
| 4332 greater(0xC); | |
| 4333 %} | |
| 4334 %} | |
| 4335 | |
| 4336 // Comparison Op, branch-register encoding | |
| 4337 operand cmpOp_reg() %{ | |
| 4338 match(Bool); | |
| 4339 | |
| 4340 format %{ "" %} | |
| 4341 interface(COND_INTER) %{ | |
| 4342 equal (0x1); | |
| 4343 not_equal (0x5); | |
| 4344 less (0x3); | |
| 4345 greater_equal(0x7); | |
| 4346 less_equal (0x2); | |
| 4347 greater (0x6); | |
| 4348 %} | |
| 4349 %} | |
| 4350 | |
| 4351 // Comparison Code, floating, unordered same as less | |
| 4352 operand cmpOpF() %{ | |
| 4353 match(Bool); | |
| 4354 | |
| 4355 format %{ "fl" %} | |
| 4356 interface(COND_INTER) %{ | |
| 4357 equal(0x9); | |
| 4358 not_equal(0x1); | |
| 4359 less(0x3); | |
| 4360 greater_equal(0xB); | |
| 4361 less_equal(0xE); | |
| 4362 greater(0x6); | |
| 4363 %} | |
| 4364 %} | |
| 4365 | |
| 4366 // Used by long compare | |
| 4367 operand cmpOp_commute() %{ | |
| 4368 match(Bool); | |
| 4369 | |
| 4370 format %{ "" %} | |
| 4371 interface(COND_INTER) %{ | |
| 4372 equal(0x1); | |
| 4373 not_equal(0x9); | |
| 4374 less(0xA); | |
| 4375 greater_equal(0x2); | |
| 4376 less_equal(0xB); | |
| 4377 greater(0x3); | |
| 4378 %} | |
| 4379 %} | |
| 4380 | |
| 4381 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4382 // Operand Classes are groups of operands that are used to simplify | |
| 605 | 4383 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4384 // instructions for every form of operand when the instruction accepts |
| 4385 // multiple operand types with the same basic encoding and format. The classic | |
| 4386 // case of this is memory operands. | |
| 4387 opclass memory( indirect, indOffset13, indIndex ); | |
|
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|
4388 opclass indIndexMemory( indIndex ); |
| 0 | 4389 |
| 4390 //----------PIPELINE----------------------------------------------------------- | |
| 4391 pipeline %{ | |
| 4392 | |
| 4393 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4394 attributes %{ | |
| 4395 fixed_size_instructions; // Fixed size instructions | |
| 4396 branch_has_delay_slot; // Branch has delay slot following | |
| 4397 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
| 4398 instruction_unit_size = 4; // An instruction is 4 bytes long | |
| 4399 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4400 instruction_fetch_units = 1; // of 16 bytes | |
| 4401 | |
| 4402 // List of nop instructions | |
| 4403 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
| 4404 %} | |
| 4405 | |
| 4406 //----------RESOURCES---------------------------------------------------------- | |
| 4407 // Resources are the functional units available to the machine | |
| 4408 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
| 4409 | |
| 4410 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4411 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4412 | |
| 4413 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
| 4414 | |
| 4415 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4416 // Pipeline Classes describe the stages in which input and output are | |
| 4417 // referenced by the hardware pipeline. | |
| 4418 | |
| 4419 // Integer ALU reg-reg operation | |
| 4420 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4421 single_instruction; | |
| 4422 dst : E(write); | |
| 4423 src1 : R(read); | |
| 4424 src2 : R(read); | |
| 4425 IALU : R; | |
| 4426 %} | |
| 4427 | |
| 4428 // Integer ALU reg-reg long operation | |
| 4429 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4430 instruction_count(2); | |
| 4431 dst : E(write); | |
| 4432 src1 : R(read); | |
| 4433 src2 : R(read); | |
| 4434 IALU : R; | |
| 4435 IALU : R; | |
| 4436 %} | |
| 4437 | |
| 4438 // Integer ALU reg-reg long dependent operation | |
| 4439 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
| 4440 instruction_count(1); multiple_bundles; | |
| 4441 dst : E(write); | |
| 4442 src1 : R(read); | |
| 4443 src2 : R(read); | |
| 4444 cr : E(write); | |
| 4445 IALU : R(2); | |
| 4446 %} | |
| 4447 | |
| 4448 // Integer ALU reg-imm operaion | |
| 4449 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4450 single_instruction; | |
| 4451 dst : E(write); | |
| 4452 src1 : R(read); | |
| 4453 IALU : R; | |
| 4454 %} | |
| 4455 | |
| 4456 // Integer ALU reg-reg operation with condition code | |
| 4457 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
| 4458 single_instruction; | |
| 4459 dst : E(write); | |
| 4460 cr : E(write); | |
| 4461 src1 : R(read); | |
| 4462 src2 : R(read); | |
| 4463 IALU : R; | |
| 4464 %} | |
| 4465 | |
| 4466 // Integer ALU reg-imm operation with condition code | |
| 4467 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
| 4468 single_instruction; | |
| 4469 dst : E(write); | |
| 4470 cr : E(write); | |
| 4471 src1 : R(read); | |
| 4472 IALU : R; | |
| 4473 %} | |
| 4474 | |
| 4475 // Integer ALU zero-reg operation | |
| 4476 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 4477 single_instruction; | |
| 4478 dst : E(write); | |
| 4479 src2 : R(read); | |
| 4480 IALU : R; | |
| 4481 %} | |
| 4482 | |
| 4483 // Integer ALU zero-reg operation with condition code only | |
| 4484 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
| 4485 single_instruction; | |
| 4486 cr : E(write); | |
| 4487 src : R(read); | |
| 4488 IALU : R; | |
| 4489 %} | |
| 4490 | |
| 4491 // Integer ALU reg-reg operation with condition code only | |
| 4492 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4493 single_instruction; | |
| 4494 cr : E(write); | |
| 4495 src1 : R(read); | |
| 4496 src2 : R(read); | |
| 4497 IALU : R; | |
| 4498 %} | |
| 4499 | |
| 4500 // Integer ALU reg-imm operation with condition code only | |
| 4501 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4502 single_instruction; | |
| 4503 cr : E(write); | |
| 4504 src1 : R(read); | |
| 4505 IALU : R; | |
| 4506 %} | |
| 4507 | |
| 4508 // Integer ALU reg-reg-zero operation with condition code only | |
| 4509 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
| 4510 single_instruction; | |
| 4511 cr : E(write); | |
| 4512 src1 : R(read); | |
| 4513 src2 : R(read); | |
| 4514 IALU : R; | |
| 4515 %} | |
| 4516 | |
| 4517 // Integer ALU reg-imm-zero operation with condition code only | |
| 4518 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
| 4519 single_instruction; | |
| 4520 cr : E(write); | |
| 4521 src1 : R(read); | |
| 4522 IALU : R; | |
| 4523 %} | |
| 4524 | |
| 4525 // Integer ALU reg-reg operation with condition code, src1 modified | |
| 4526 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4527 single_instruction; | |
| 4528 cr : E(write); | |
| 4529 src1 : E(write); | |
| 4530 src1 : R(read); | |
| 4531 src2 : R(read); | |
| 4532 IALU : R; | |
| 4533 %} | |
| 4534 | |
| 4535 // Integer ALU reg-imm operation with condition code, src1 modified | |
| 4536 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4537 single_instruction; | |
| 4538 cr : E(write); | |
| 4539 src1 : E(write); | |
| 4540 src1 : R(read); | |
| 4541 IALU : R; | |
| 4542 %} | |
| 4543 | |
| 4544 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
| 4545 multiple_bundles; | |
| 4546 dst : E(write)+4; | |
| 4547 cr : E(write); | |
| 4548 src1 : R(read); | |
| 4549 src2 : R(read); | |
| 4550 IALU : R(3); | |
| 4551 BR : R(2); | |
| 4552 %} | |
| 4553 | |
| 4554 // Integer ALU operation | |
| 4555 pipe_class ialu_none(iRegI dst) %{ | |
| 4556 single_instruction; | |
| 4557 dst : E(write); | |
| 4558 IALU : R; | |
| 4559 %} | |
| 4560 | |
| 4561 // Integer ALU reg operation | |
| 4562 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
| 4563 single_instruction; may_have_no_code; | |
| 4564 dst : E(write); | |
| 4565 src : R(read); | |
| 4566 IALU : R; | |
| 4567 %} | |
| 4568 | |
| 4569 // Integer ALU reg conditional operation | |
| 4570 // This instruction has a 1 cycle stall, and cannot execute | |
| 4571 // in the same cycle as the instruction setting the condition | |
| 4572 // code. We kludge this by pretending to read the condition code | |
| 4573 // 1 cycle earlier, and by marking the functional units as busy | |
| 4574 // for 2 cycles with the result available 1 cycle later than | |
| 4575 // is really the case. | |
| 4576 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
| 4577 single_instruction; | |
| 4578 op2_out : C(write); | |
| 4579 op1 : R(read); | |
| 4580 cr : R(read); // This is really E, with a 1 cycle stall | |
| 4581 BR : R(2); | |
| 4582 MS : R(2); | |
| 4583 %} | |
| 4584 | |
| 4585 #ifdef _LP64 | |
| 4586 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
| 4587 instruction_count(1); multiple_bundles; | |
| 4588 dst : C(write)+1; | |
| 4589 src : R(read)+1; | |
| 4590 IALU : R(1); | |
| 4591 BR : E(2); | |
| 4592 MS : E(2); | |
| 4593 %} | |
| 4594 #endif | |
| 4595 | |
| 4596 // Integer ALU reg operation | |
| 4597 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
| 4598 single_instruction; may_have_no_code; | |
| 4599 dst : E(write); | |
| 4600 src : R(read); | |
| 4601 IALU : R; | |
| 4602 %} | |
| 4603 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
| 4604 single_instruction; may_have_no_code; | |
| 4605 dst : E(write); | |
| 4606 src : R(read); | |
| 4607 IALU : R; | |
| 4608 %} | |
| 4609 | |
| 4610 // Two integer ALU reg operations | |
| 4611 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
| 4612 instruction_count(2); | |
| 4613 dst : E(write); | |
| 4614 src : R(read); | |
| 4615 A0 : R; | |
| 4616 A1 : R; | |
| 4617 %} | |
| 4618 | |
| 4619 // Two integer ALU reg operations | |
| 4620 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
| 4621 instruction_count(2); may_have_no_code; | |
| 4622 dst : E(write); | |
| 4623 src : R(read); | |
| 4624 A0 : R; | |
| 4625 A1 : R; | |
| 4626 %} | |
| 4627 | |
| 4628 // Integer ALU imm operation | |
| 4629 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
| 4630 single_instruction; | |
| 4631 dst : E(write); | |
| 4632 IALU : R; | |
| 4633 %} | |
| 4634 | |
| 4635 // Integer ALU reg-reg with carry operation | |
| 4636 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
| 4637 single_instruction; | |
| 4638 dst : E(write); | |
| 4639 src1 : R(read); | |
| 4640 src2 : R(read); | |
| 4641 IALU : R; | |
| 4642 %} | |
| 4643 | |
| 4644 // Integer ALU cc operation | |
| 4645 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
| 4646 single_instruction; | |
| 4647 dst : E(write); | |
| 4648 cc : R(read); | |
| 4649 IALU : R; | |
| 4650 %} | |
| 4651 | |
| 4652 // Integer ALU cc / second IALU operation | |
| 4653 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
| 4654 instruction_count(1); multiple_bundles; | |
| 4655 dst : E(write)+1; | |
| 4656 src : R(read); | |
| 4657 IALU : R; | |
| 4658 %} | |
| 4659 | |
| 4660 // Integer ALU cc / second IALU operation | |
| 4661 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
| 4662 instruction_count(1); multiple_bundles; | |
| 4663 dst : E(write)+1; | |
| 4664 p : R(read); | |
| 4665 q : R(read); | |
| 4666 IALU : R; | |
| 4667 %} | |
| 4668 | |
| 4669 // Integer ALU hi-lo-reg operation | |
| 4670 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
| 4671 instruction_count(1); multiple_bundles; | |
| 4672 dst : E(write)+1; | |
| 4673 IALU : R(2); | |
| 4674 %} | |
| 4675 | |
| 4676 // Float ALU hi-lo-reg operation (with temp) | |
| 4677 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
| 4678 instruction_count(1); multiple_bundles; | |
| 4679 dst : E(write)+1; | |
| 4680 IALU : R(2); | |
| 4681 %} | |
| 4682 | |
| 4683 // Long Constant | |
| 4684 pipe_class loadConL( iRegL dst, immL src ) %{ | |
| 4685 instruction_count(2); multiple_bundles; | |
| 4686 dst : E(write)+1; | |
| 4687 IALU : R(2); | |
| 4688 IALU : R(2); | |
| 4689 %} | |
| 4690 | |
| 4691 // Pointer Constant | |
| 4692 pipe_class loadConP( iRegP dst, immP src ) %{ | |
| 4693 instruction_count(0); multiple_bundles; | |
| 4694 fixed_latency(6); | |
| 4695 %} | |
| 4696 | |
| 4697 // Polling Address | |
| 4698 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
| 4699 #ifdef _LP64 | |
| 4700 instruction_count(0); multiple_bundles; | |
| 4701 fixed_latency(6); | |
| 4702 #else | |
| 4703 dst : E(write); | |
| 4704 IALU : R; | |
| 4705 #endif | |
| 4706 %} | |
| 4707 | |
| 4708 // Long Constant small | |
| 4709 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
| 4710 instruction_count(2); | |
| 4711 dst : E(write); | |
| 4712 IALU : R; | |
| 4713 IALU : R; | |
| 4714 %} | |
| 4715 | |
| 4716 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
| 4717 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
| 4718 instruction_count(1); multiple_bundles; | |
| 4719 src : R(read); | |
| 4720 dst : M(write)+1; | |
| 4721 IALU : R; | |
| 4722 MS : E; | |
| 4723 %} | |
| 4724 | |
| 4725 // Integer ALU nop operation | |
| 4726 pipe_class ialu_nop() %{ | |
| 4727 single_instruction; | |
| 4728 IALU : R; | |
| 4729 %} | |
| 4730 | |
| 4731 // Integer ALU nop operation | |
| 4732 pipe_class ialu_nop_A0() %{ | |
| 4733 single_instruction; | |
| 4734 A0 : R; | |
| 4735 %} | |
| 4736 | |
| 4737 // Integer ALU nop operation | |
| 4738 pipe_class ialu_nop_A1() %{ | |
| 4739 single_instruction; | |
| 4740 A1 : R; | |
| 4741 %} | |
| 4742 | |
| 4743 // Integer Multiply reg-reg operation | |
| 4744 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4745 single_instruction; | |
| 4746 dst : E(write); | |
| 4747 src1 : R(read); | |
| 4748 src2 : R(read); | |
| 4749 MS : R(5); | |
| 4750 %} | |
| 4751 | |
| 4752 // Integer Multiply reg-imm operation | |
| 4753 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4754 single_instruction; | |
| 4755 dst : E(write); | |
| 4756 src1 : R(read); | |
| 4757 MS : R(5); | |
| 4758 %} | |
| 4759 | |
| 4760 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4761 single_instruction; | |
| 4762 dst : E(write)+4; | |
| 4763 src1 : R(read); | |
| 4764 src2 : R(read); | |
| 4765 MS : R(6); | |
| 4766 %} | |
| 4767 | |
| 4768 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4769 single_instruction; | |
| 4770 dst : E(write)+4; | |
| 4771 src1 : R(read); | |
| 4772 MS : R(6); | |
| 4773 %} | |
| 4774 | |
| 4775 // Integer Divide reg-reg | |
| 4776 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
| 4777 instruction_count(1); multiple_bundles; | |
| 4778 dst : E(write); | |
| 4779 temp : E(write); | |
| 4780 src1 : R(read); | |
| 4781 src2 : R(read); | |
| 4782 temp : R(read); | |
| 4783 MS : R(38); | |
| 4784 %} | |
| 4785 | |
| 4786 // Integer Divide reg-imm | |
| 4787 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
| 4788 instruction_count(1); multiple_bundles; | |
| 4789 dst : E(write); | |
| 4790 temp : E(write); | |
| 4791 src1 : R(read); | |
| 4792 temp : R(read); | |
| 4793 MS : R(38); | |
| 4794 %} | |
| 4795 | |
| 4796 // Long Divide | |
| 4797 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4798 dst : E(write)+71; | |
| 4799 src1 : R(read); | |
| 4800 src2 : R(read)+1; | |
| 4801 MS : R(70); | |
| 4802 %} | |
| 4803 | |
| 4804 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4805 dst : E(write)+71; | |
| 4806 src1 : R(read); | |
| 4807 MS : R(70); | |
| 4808 %} | |
| 4809 | |
| 4810 // Floating Point Add Float | |
| 4811 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4812 single_instruction; | |
| 4813 dst : X(write); | |
| 4814 src1 : E(read); | |
| 4815 src2 : E(read); | |
| 4816 FA : R; | |
| 4817 %} | |
| 4818 | |
| 4819 // Floating Point Add Double | |
| 4820 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4821 single_instruction; | |
| 4822 dst : X(write); | |
| 4823 src1 : E(read); | |
| 4824 src2 : E(read); | |
| 4825 FA : R; | |
| 4826 %} | |
| 4827 | |
| 4828 // Floating Point Conditional Move based on integer flags | |
| 4829 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
| 4830 single_instruction; | |
| 4831 dst : X(write); | |
| 4832 src : E(read); | |
| 4833 cr : R(read); | |
| 4834 FA : R(2); | |
| 4835 BR : R(2); | |
| 4836 %} | |
| 4837 | |
| 4838 // Floating Point Conditional Move based on integer flags | |
| 4839 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
| 4840 single_instruction; | |
| 4841 dst : X(write); | |
| 4842 src : E(read); | |
| 4843 cr : R(read); | |
| 4844 FA : R(2); | |
| 4845 BR : R(2); | |
| 4846 %} | |
| 4847 | |
| 4848 // Floating Point Multiply Float | |
| 4849 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4850 single_instruction; | |
| 4851 dst : X(write); | |
| 4852 src1 : E(read); | |
| 4853 src2 : E(read); | |
| 4854 FM : R; | |
| 4855 %} | |
| 4856 | |
| 4857 // Floating Point Multiply Double | |
| 4858 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4859 single_instruction; | |
| 4860 dst : X(write); | |
| 4861 src1 : E(read); | |
| 4862 src2 : E(read); | |
| 4863 FM : R; | |
| 4864 %} | |
| 4865 | |
| 4866 // Floating Point Divide Float | |
| 4867 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4868 single_instruction; | |
| 4869 dst : X(write); | |
| 4870 src1 : E(read); | |
| 4871 src2 : E(read); | |
| 4872 FM : R; | |
| 4873 FDIV : C(14); | |
| 4874 %} | |
| 4875 | |
| 4876 // Floating Point Divide Double | |
| 4877 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4878 single_instruction; | |
| 4879 dst : X(write); | |
| 4880 src1 : E(read); | |
| 4881 src2 : E(read); | |
| 4882 FM : R; | |
| 4883 FDIV : C(17); | |
| 4884 %} | |
| 4885 | |
| 4886 // Floating Point Move/Negate/Abs Float | |
| 4887 pipe_class faddF_reg(regF dst, regF src) %{ | |
| 4888 single_instruction; | |
| 4889 dst : W(write); | |
| 4890 src : E(read); | |
| 4891 FA : R(1); | |
| 4892 %} | |
| 4893 | |
| 4894 // Floating Point Move/Negate/Abs Double | |
| 4895 pipe_class faddD_reg(regD dst, regD src) %{ | |
| 4896 single_instruction; | |
| 4897 dst : W(write); | |
| 4898 src : E(read); | |
| 4899 FA : R; | |
| 4900 %} | |
| 4901 | |
| 4902 // Floating Point Convert F->D | |
| 4903 pipe_class fcvtF2D(regD dst, regF src) %{ | |
| 4904 single_instruction; | |
| 4905 dst : X(write); | |
| 4906 src : E(read); | |
| 4907 FA : R; | |
| 4908 %} | |
| 4909 | |
| 4910 // Floating Point Convert I->D | |
| 4911 pipe_class fcvtI2D(regD dst, regF src) %{ | |
| 4912 single_instruction; | |
| 4913 dst : X(write); | |
| 4914 src : E(read); | |
| 4915 FA : R; | |
| 4916 %} | |
| 4917 | |
| 4918 // Floating Point Convert LHi->D | |
| 4919 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
| 4920 single_instruction; | |
| 4921 dst : X(write); | |
| 4922 src : E(read); | |
| 4923 FA : R; | |
| 4924 %} | |
| 4925 | |
| 4926 // Floating Point Convert L->D | |
| 4927 pipe_class fcvtL2D(regD dst, regF src) %{ | |
| 4928 single_instruction; | |
| 4929 dst : X(write); | |
| 4930 src : E(read); | |
| 4931 FA : R; | |
| 4932 %} | |
| 4933 | |
| 4934 // Floating Point Convert L->F | |
| 4935 pipe_class fcvtL2F(regD dst, regF src) %{ | |
| 4936 single_instruction; | |
| 4937 dst : X(write); | |
| 4938 src : E(read); | |
| 4939 FA : R; | |
| 4940 %} | |
| 4941 | |
| 4942 // Floating Point Convert D->F | |
| 4943 pipe_class fcvtD2F(regD dst, regF src) %{ | |
| 4944 single_instruction; | |
| 4945 dst : X(write); | |
| 4946 src : E(read); | |
| 4947 FA : R; | |
| 4948 %} | |
| 4949 | |
| 4950 // Floating Point Convert I->L | |
| 4951 pipe_class fcvtI2L(regD dst, regF src) %{ | |
| 4952 single_instruction; | |
| 4953 dst : X(write); | |
| 4954 src : E(read); | |
| 4955 FA : R; | |
| 4956 %} | |
| 4957 | |
| 4958 // Floating Point Convert D->F | |
| 4959 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
| 4960 instruction_count(1); multiple_bundles; | |
| 4961 dst : X(write)+6; | |
| 4962 src : E(read); | |
| 4963 FA : R; | |
| 4964 %} | |
| 4965 | |
| 4966 // Floating Point Convert D->L | |
| 4967 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
| 4968 instruction_count(1); multiple_bundles; | |
| 4969 dst : X(write)+6; | |
| 4970 src : E(read); | |
| 4971 FA : R; | |
| 4972 %} | |
| 4973 | |
| 4974 // Floating Point Convert F->I | |
| 4975 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
| 4976 instruction_count(1); multiple_bundles; | |
| 4977 dst : X(write)+6; | |
| 4978 src : E(read); | |
| 4979 FA : R; | |
| 4980 %} | |
| 4981 | |
| 4982 // Floating Point Convert F->L | |
| 4983 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
| 4984 instruction_count(1); multiple_bundles; | |
| 4985 dst : X(write)+6; | |
| 4986 src : E(read); | |
| 4987 FA : R; | |
| 4988 %} | |
| 4989 | |
| 4990 // Floating Point Convert I->F | |
| 4991 pipe_class fcvtI2F(regF dst, regF src) %{ | |
| 4992 single_instruction; | |
| 4993 dst : X(write); | |
| 4994 src : E(read); | |
| 4995 FA : R; | |
| 4996 %} | |
| 4997 | |
| 4998 // Floating Point Compare | |
| 4999 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
| 5000 single_instruction; | |
| 5001 cr : X(write); | |
| 5002 src1 : E(read); | |
| 5003 src2 : E(read); | |
| 5004 FA : R; | |
| 5005 %} | |
| 5006 | |
| 5007 // Floating Point Compare | |
| 5008 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
| 5009 single_instruction; | |
| 5010 cr : X(write); | |
| 5011 src1 : E(read); | |
| 5012 src2 : E(read); | |
| 5013 FA : R; | |
| 5014 %} | |
| 5015 | |
| 5016 // Floating Add Nop | |
| 5017 pipe_class fadd_nop() %{ | |
| 5018 single_instruction; | |
| 5019 FA : R; | |
| 5020 %} | |
| 5021 | |
| 5022 // Integer Store to Memory | |
| 5023 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
| 5024 single_instruction; | |
| 5025 mem : R(read); | |
| 5026 src : C(read); | |
| 5027 MS : R; | |
| 5028 %} | |
| 5029 | |
| 5030 // Integer Store to Memory | |
| 5031 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
| 5032 single_instruction; | |
| 5033 mem : R(read); | |
| 5034 src : C(read); | |
| 5035 MS : R; | |
| 5036 %} | |
| 5037 | |
| 5038 // Integer Store Zero to Memory | |
| 5039 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
| 5040 single_instruction; | |
| 5041 mem : R(read); | |
| 5042 MS : R; | |
| 5043 %} | |
| 5044 | |
| 5045 // Special Stack Slot Store | |
| 5046 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
| 5047 single_instruction; | |
| 5048 stkSlot : R(read); | |
| 5049 src : C(read); | |
| 5050 MS : R; | |
| 5051 %} | |
| 5052 | |
| 5053 // Special Stack Slot Store | |
| 5054 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
| 5055 instruction_count(2); multiple_bundles; | |
| 5056 stkSlot : R(read); | |
| 5057 src : C(read); | |
| 5058 MS : R(2); | |
| 5059 %} | |
| 5060 | |
| 5061 // Float Store | |
| 5062 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
| 5063 single_instruction; | |
| 5064 mem : R(read); | |
| 5065 src : C(read); | |
| 5066 MS : R; | |
| 5067 %} | |
| 5068 | |
| 5069 // Float Store | |
| 5070 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
| 5071 single_instruction; | |
| 5072 mem : R(read); | |
| 5073 MS : R; | |
| 5074 %} | |
| 5075 | |
| 5076 // Double Store | |
| 5077 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
| 5078 instruction_count(1); | |
| 5079 mem : R(read); | |
| 5080 src : C(read); | |
| 5081 MS : R; | |
| 5082 %} | |
| 5083 | |
| 5084 // Double Store | |
| 5085 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
| 5086 single_instruction; | |
| 5087 mem : R(read); | |
| 5088 MS : R; | |
| 5089 %} | |
| 5090 | |
| 5091 // Special Stack Slot Float Store | |
| 5092 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
| 5093 single_instruction; | |
| 5094 stkSlot : R(read); | |
| 5095 src : C(read); | |
| 5096 MS : R; | |
| 5097 %} | |
| 5098 | |
| 5099 // Special Stack Slot Double Store | |
| 5100 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
| 5101 single_instruction; | |
| 5102 stkSlot : R(read); | |
| 5103 src : C(read); | |
| 5104 MS : R; | |
| 5105 %} | |
| 5106 | |
| 5107 // Integer Load (when sign bit propagation not needed) | |
| 5108 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
| 5109 single_instruction; | |
| 5110 mem : R(read); | |
| 5111 dst : C(write); | |
| 5112 MS : R; | |
| 5113 %} | |
| 5114 | |
| 5115 // Integer Load from stack operand | |
| 5116 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
| 5117 single_instruction; | |
| 5118 mem : R(read); | |
| 5119 dst : C(write); | |
| 5120 MS : R; | |
| 5121 %} | |
| 5122 | |
| 5123 // Integer Load (when sign bit propagation or masking is needed) | |
| 5124 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
| 5125 single_instruction; | |
| 5126 mem : R(read); | |
| 5127 dst : M(write); | |
| 5128 MS : R; | |
| 5129 %} | |
| 5130 | |
| 5131 // Float Load | |
| 5132 pipe_class floadF_mem(regF dst, memory mem) %{ | |
| 5133 single_instruction; | |
| 5134 mem : R(read); | |
| 5135 dst : M(write); | |
| 5136 MS : R; | |
| 5137 %} | |
| 5138 | |
| 5139 // Float Load | |
| 5140 pipe_class floadD_mem(regD dst, memory mem) %{ | |
| 5141 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
| 5142 mem : R(read); | |
| 5143 dst : M(write); | |
| 5144 MS : R; | |
| 5145 %} | |
| 5146 | |
| 5147 // Float Load | |
| 5148 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
| 5149 single_instruction; | |
| 5150 stkSlot : R(read); | |
| 5151 dst : M(write); | |
| 5152 MS : R; | |
| 5153 %} | |
| 5154 | |
| 5155 // Float Load | |
| 5156 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
| 5157 single_instruction; | |
| 5158 stkSlot : R(read); | |
| 5159 dst : M(write); | |
| 5160 MS : R; | |
| 5161 %} | |
| 5162 | |
| 5163 // Memory Nop | |
| 5164 pipe_class mem_nop() %{ | |
| 5165 single_instruction; | |
| 5166 MS : R; | |
| 5167 %} | |
| 5168 | |
| 5169 pipe_class sethi(iRegP dst, immI src) %{ | |
| 5170 single_instruction; | |
| 5171 dst : E(write); | |
| 5172 IALU : R; | |
| 5173 %} | |
| 5174 | |
| 5175 pipe_class loadPollP(iRegP poll) %{ | |
| 5176 single_instruction; | |
| 5177 poll : R(read); | |
| 5178 MS : R; | |
| 5179 %} | |
| 5180 | |
| 5181 pipe_class br(Universe br, label labl) %{ | |
| 5182 single_instruction_with_delay_slot; | |
| 5183 BR : R; | |
| 5184 %} | |
| 5185 | |
| 5186 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
| 5187 single_instruction_with_delay_slot; | |
| 5188 cr : E(read); | |
| 5189 BR : R; | |
| 5190 %} | |
| 5191 | |
| 5192 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
| 5193 single_instruction_with_delay_slot; | |
| 5194 op1 : E(read); | |
| 5195 BR : R; | |
| 5196 MS : R; | |
| 5197 %} | |
| 5198 | |
| 5199 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ | |
| 5200 single_instruction_with_delay_slot; | |
| 5201 cr : E(read); | |
| 5202 BR : R; | |
| 5203 %} | |
| 5204 | |
| 5205 pipe_class br_nop() %{ | |
| 5206 single_instruction; | |
| 5207 BR : R; | |
| 5208 %} | |
| 5209 | |
| 5210 pipe_class simple_call(method meth) %{ | |
| 5211 instruction_count(2); multiple_bundles; force_serialization; | |
| 5212 fixed_latency(100); | |
| 5213 BR : R(1); | |
| 5214 MS : R(1); | |
| 5215 A0 : R(1); | |
| 5216 %} | |
| 5217 | |
| 5218 pipe_class compiled_call(method meth) %{ | |
| 5219 instruction_count(1); multiple_bundles; force_serialization; | |
| 5220 fixed_latency(100); | |
| 5221 MS : R(1); | |
| 5222 %} | |
| 5223 | |
| 5224 pipe_class call(method meth) %{ | |
| 5225 instruction_count(0); multiple_bundles; force_serialization; | |
| 5226 fixed_latency(100); | |
| 5227 %} | |
| 5228 | |
| 5229 pipe_class tail_call(Universe ignore, label labl) %{ | |
| 5230 single_instruction; has_delay_slot; | |
| 5231 fixed_latency(100); | |
| 5232 BR : R(1); | |
| 5233 MS : R(1); | |
| 5234 %} | |
| 5235 | |
| 5236 pipe_class ret(Universe ignore) %{ | |
| 5237 single_instruction; has_delay_slot; | |
| 5238 BR : R(1); | |
| 5239 MS : R(1); | |
| 5240 %} | |
| 5241 | |
| 5242 pipe_class ret_poll(g3RegP poll) %{ | |
| 5243 instruction_count(3); has_delay_slot; | |
| 5244 poll : E(read); | |
| 5245 MS : R; | |
| 5246 %} | |
| 5247 | |
| 5248 // The real do-nothing guy | |
| 5249 pipe_class empty( ) %{ | |
| 5250 instruction_count(0); | |
| 5251 %} | |
| 5252 | |
| 5253 pipe_class long_memory_op() %{ | |
| 5254 instruction_count(0); multiple_bundles; force_serialization; | |
| 5255 fixed_latency(25); | |
| 5256 MS : R(1); | |
| 5257 %} | |
| 5258 | |
| 5259 // Check-cast | |
| 5260 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
| 5261 array : R(read); | |
| 5262 match : R(read); | |
| 5263 IALU : R(2); | |
| 5264 BR : R(2); | |
| 5265 MS : R; | |
| 5266 %} | |
| 5267 | |
| 5268 // Convert FPU flags into +1,0,-1 | |
| 5269 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
| 5270 src1 : E(read); | |
| 5271 src2 : E(read); | |
| 5272 dst : E(write); | |
| 5273 FA : R; | |
| 5274 MS : R(2); | |
| 5275 BR : R(2); | |
| 5276 %} | |
| 5277 | |
| 5278 // Compare for p < q, and conditionally add y | |
| 5279 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
| 5280 p : E(read); | |
| 5281 q : E(read); | |
| 5282 y : E(read); | |
| 5283 IALU : R(3) | |
| 5284 %} | |
| 5285 | |
| 5286 // Perform a compare, then move conditionally in a branch delay slot. | |
| 5287 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
| 5288 src2 : E(read); | |
| 5289 srcdst : E(read); | |
| 5290 IALU : R; | |
| 5291 BR : R; | |
| 5292 %} | |
| 5293 | |
| 5294 // Define the class for the Nop node | |
| 5295 define %{ | |
| 5296 MachNop = ialu_nop; | |
| 5297 %} | |
| 5298 | |
| 5299 %} | |
| 5300 | |
| 5301 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5302 | |
| 5303 //------------Special Stack Slot instructions - no match rules----------------- | |
| 5304 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
| 5305 // No match rule to avoid chain rule match. | |
| 5306 effect(DEF dst, USE src); | |
| 5307 ins_cost(MEMORY_REF_COST); | |
| 5308 size(4); | |
| 5309 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
| 5310 opcode(Assembler::ldf_op3); | |
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5311 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5312 ins_pipe(floadF_stk); |
| 5313 %} | |
| 5314 | |
| 5315 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
| 5316 // No match rule to avoid chain rule match. | |
| 5317 effect(DEF dst, USE src); | |
| 5318 ins_cost(MEMORY_REF_COST); | |
| 5319 size(4); | |
| 5320 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
| 5321 opcode(Assembler::lddf_op3); | |
|
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5322 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5323 ins_pipe(floadD_stk); |
| 5324 %} | |
| 5325 | |
| 5326 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
| 5327 // No match rule to avoid chain rule match. | |
| 5328 effect(DEF dst, USE src); | |
| 5329 ins_cost(MEMORY_REF_COST); | |
| 5330 size(4); | |
| 5331 format %{ "STF $src,$dst\t! regF to stkI" %} | |
| 5332 opcode(Assembler::stf_op3); | |
|
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5333 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5334 ins_pipe(fstoreF_stk_reg); |
| 5335 %} | |
| 5336 | |
| 5337 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
| 5338 // No match rule to avoid chain rule match. | |
| 5339 effect(DEF dst, USE src); | |
| 5340 ins_cost(MEMORY_REF_COST); | |
| 5341 size(4); | |
| 5342 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
| 5343 opcode(Assembler::stdf_op3); | |
|
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5344 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5345 ins_pipe(fstoreD_stk_reg); |
| 5346 %} | |
| 5347 | |
| 5348 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
| 5349 effect(DEF dst, USE src); | |
| 5350 ins_cost(MEMORY_REF_COST*2); | |
| 5351 size(8); | |
| 5352 format %{ "STW $src,$dst.hi\t! long\n\t" | |
| 5353 "STW R_G0,$dst.lo" %} | |
| 5354 opcode(Assembler::stw_op3); | |
|
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5355 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
| 0 | 5356 ins_pipe(lstoreI_stk_reg); |
| 5357 %} | |
| 5358 | |
| 5359 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
| 5360 // No match rule to avoid chain rule match. | |
| 5361 effect(DEF dst, USE src); | |
| 5362 ins_cost(MEMORY_REF_COST); | |
| 5363 size(4); | |
| 5364 format %{ "STX $src,$dst\t! regL to stkD" %} | |
| 5365 opcode(Assembler::stx_op3); | |
|
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5366 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5367 ins_pipe(istore_stk_reg); |
| 5368 %} | |
| 5369 | |
| 5370 //---------- Chain stack slots between similar types -------- | |
| 5371 | |
| 5372 // Load integer from stack slot | |
| 5373 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
| 5374 match(Set dst src); | |
| 5375 ins_cost(MEMORY_REF_COST); | |
| 5376 | |
| 5377 size(4); | |
| 5378 format %{ "LDUW $src,$dst\t!stk" %} | |
| 5379 opcode(Assembler::lduw_op3); | |
|
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5380 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5381 ins_pipe(iload_mem); |
| 5382 %} | |
| 5383 | |
| 5384 // Store integer to stack slot | |
| 5385 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
| 5386 match(Set dst src); | |
| 5387 ins_cost(MEMORY_REF_COST); | |
| 5388 | |
| 5389 size(4); | |
| 5390 format %{ "STW $src,$dst\t!stk" %} | |
| 5391 opcode(Assembler::stw_op3); | |
|
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5392 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5393 ins_pipe(istore_mem_reg); |
| 5394 %} | |
| 5395 | |
| 5396 // Load long from stack slot | |
| 5397 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
| 5398 match(Set dst src); | |
| 5399 | |
| 5400 ins_cost(MEMORY_REF_COST); | |
| 5401 size(4); | |
| 5402 format %{ "LDX $src,$dst\t! long" %} | |
| 5403 opcode(Assembler::ldx_op3); | |
|
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5404 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5405 ins_pipe(iload_mem); |
| 5406 %} | |
| 5407 | |
| 5408 // Store long to stack slot | |
| 5409 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
| 5410 match(Set dst src); | |
| 5411 | |
| 5412 ins_cost(MEMORY_REF_COST); | |
| 5413 size(4); | |
| 5414 format %{ "STX $src,$dst\t! long" %} | |
| 5415 opcode(Assembler::stx_op3); | |
|
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5416 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5417 ins_pipe(istore_mem_reg); |
| 5418 %} | |
| 5419 | |
| 5420 #ifdef _LP64 | |
| 5421 // Load pointer from stack slot, 64-bit encoding | |
| 5422 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5423 match(Set dst src); | |
| 5424 ins_cost(MEMORY_REF_COST); | |
| 5425 size(4); | |
| 5426 format %{ "LDX $src,$dst\t!ptr" %} | |
| 5427 opcode(Assembler::ldx_op3); | |
|
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5428 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5429 ins_pipe(iload_mem); |
| 5430 %} | |
| 5431 | |
| 5432 // Store pointer to stack slot | |
| 5433 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5434 match(Set dst src); | |
| 5435 ins_cost(MEMORY_REF_COST); | |
| 5436 size(4); | |
| 5437 format %{ "STX $src,$dst\t!ptr" %} | |
| 5438 opcode(Assembler::stx_op3); | |
|
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5439 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5440 ins_pipe(istore_mem_reg); |
| 5441 %} | |
| 5442 #else // _LP64 | |
| 5443 // Load pointer from stack slot, 32-bit encoding | |
| 5444 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5445 match(Set dst src); | |
| 5446 ins_cost(MEMORY_REF_COST); | |
| 5447 format %{ "LDUW $src,$dst\t!ptr" %} | |
| 5448 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
|
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|
5449 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5450 ins_pipe(iload_mem); |
| 5451 %} | |
| 5452 | |
| 5453 // Store pointer to stack slot | |
| 5454 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5455 match(Set dst src); | |
| 5456 ins_cost(MEMORY_REF_COST); | |
| 5457 format %{ "STW $src,$dst\t!ptr" %} | |
| 5458 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
|
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|
5459 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5460 ins_pipe(istore_mem_reg); |
| 5461 %} | |
| 5462 #endif // _LP64 | |
| 5463 | |
| 5464 //------------Special Nop instructions for bundling - no match rules----------- | |
| 5465 // Nop using the A0 functional unit | |
| 5466 instruct Nop_A0() %{ | |
| 5467 ins_cost(0); | |
| 5468 | |
| 5469 format %{ "NOP ! Alu Pipeline" %} | |
| 5470 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5471 ins_encode( form2_nop() ); | |
| 5472 ins_pipe(ialu_nop_A0); | |
| 5473 %} | |
| 5474 | |
| 5475 // Nop using the A1 functional unit | |
| 5476 instruct Nop_A1( ) %{ | |
| 5477 ins_cost(0); | |
| 5478 | |
| 5479 format %{ "NOP ! Alu Pipeline" %} | |
| 5480 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5481 ins_encode( form2_nop() ); | |
| 5482 ins_pipe(ialu_nop_A1); | |
| 5483 %} | |
| 5484 | |
| 5485 // Nop using the memory functional unit | |
| 5486 instruct Nop_MS( ) %{ | |
| 5487 ins_cost(0); | |
| 5488 | |
| 5489 format %{ "NOP ! Memory Pipeline" %} | |
| 5490 ins_encode( emit_mem_nop ); | |
| 5491 ins_pipe(mem_nop); | |
| 5492 %} | |
| 5493 | |
| 5494 // Nop using the floating add functional unit | |
| 5495 instruct Nop_FA( ) %{ | |
| 5496 ins_cost(0); | |
| 5497 | |
| 5498 format %{ "NOP ! Floating Add Pipeline" %} | |
| 5499 ins_encode( emit_fadd_nop ); | |
| 5500 ins_pipe(fadd_nop); | |
| 5501 %} | |
| 5502 | |
| 5503 // Nop using the branch functional unit | |
| 5504 instruct Nop_BR( ) %{ | |
| 5505 ins_cost(0); | |
| 5506 | |
| 5507 format %{ "NOP ! Branch Pipeline" %} | |
| 5508 ins_encode( emit_br_nop ); | |
| 5509 ins_pipe(br_nop); | |
| 5510 %} | |
| 5511 | |
| 5512 //----------Load/Store/Move Instructions--------------------------------------- | |
| 5513 //----------Load Instructions-------------------------------------------------- | |
| 5514 // Load Byte (8bit signed) | |
| 5515 instruct loadB(iRegI dst, memory mem) %{ | |
| 5516 match(Set dst (LoadB mem)); | |
| 5517 ins_cost(MEMORY_REF_COST); | |
| 5518 | |
| 5519 size(4); | |
| 624 | 5520 format %{ "LDSB $mem,$dst\t! byte" %} |
| 727 | 5521 ins_encode %{ |
| 5522 __ ldsb($mem$$Address, $dst$$Register); | |
| 5523 %} | |
| 624 | 5524 ins_pipe(iload_mask_mem); |
| 5525 %} | |
| 5526 | |
| 5527 // Load Byte (8bit signed) into a Long Register | |
| 5528 instruct loadB2L(iRegL dst, memory mem) %{ | |
| 5529 match(Set dst (ConvI2L (LoadB mem))); | |
| 5530 ins_cost(MEMORY_REF_COST); | |
| 5531 | |
| 5532 size(4); | |
| 5533 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
| 727 | 5534 ins_encode %{ |
| 5535 __ ldsb($mem$$Address, $dst$$Register); | |
| 5536 %} | |
| 0 | 5537 ins_pipe(iload_mask_mem); |
| 5538 %} | |
| 5539 | |
| 624 | 5540 // Load Unsigned Byte (8bit UNsigned) into an int reg |
| 5541 instruct loadUB(iRegI dst, memory mem) %{ | |
| 5542 match(Set dst (LoadUB mem)); | |
| 0 | 5543 ins_cost(MEMORY_REF_COST); |
| 5544 | |
| 5545 size(4); | |
| 624 | 5546 format %{ "LDUB $mem,$dst\t! ubyte" %} |
| 727 | 5547 ins_encode %{ |
| 5548 __ ldub($mem$$Address, $dst$$Register); | |
| 5549 %} | |
| 824 | 5550 ins_pipe(iload_mem); |
| 624 | 5551 %} |
| 5552 | |
| 5553 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
| 5554 instruct loadUB2L(iRegL dst, memory mem) %{ | |
| 5555 match(Set dst (ConvI2L (LoadUB mem))); | |
| 5556 ins_cost(MEMORY_REF_COST); | |
| 5557 | |
| 5558 size(4); | |
| 5559 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
| 727 | 5560 ins_encode %{ |
| 5561 __ ldub($mem$$Address, $dst$$Register); | |
| 5562 %} | |
| 824 | 5563 ins_pipe(iload_mem); |
| 5564 %} | |
| 5565 | |
| 5566 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register | |
| 5567 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ | |
| 5568 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5569 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5570 | |
| 5571 size(2*4); | |
| 5572 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" | |
| 5573 "AND $dst,$mask,$dst" %} | |
| 5574 ins_encode %{ | |
| 5575 __ ldub($mem$$Address, $dst$$Register); | |
| 5576 __ and3($dst$$Register, $mask$$constant, $dst$$Register); | |
| 5577 %} | |
| 5578 ins_pipe(iload_mem); | |
| 0 | 5579 %} |
| 5580 | |
| 624 | 5581 // Load Short (16bit signed) |
| 5582 instruct loadS(iRegI dst, memory mem) %{ | |
| 5583 match(Set dst (LoadS mem)); | |
| 5584 ins_cost(MEMORY_REF_COST); | |
| 5585 | |
| 5586 size(4); | |
| 5587 format %{ "LDSH $mem,$dst\t! short" %} | |
| 727 | 5588 ins_encode %{ |
| 5589 __ ldsh($mem$$Address, $dst$$Register); | |
| 5590 %} | |
| 624 | 5591 ins_pipe(iload_mask_mem); |
| 5592 %} | |
| 5593 | |
| 785 | 5594 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 5595 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5596 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 5597 ins_cost(MEMORY_REF_COST); | |
| 5598 | |
| 5599 size(4); | |
| 5600 | |
| 5601 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} | |
| 5602 ins_encode %{ | |
| 5603 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5604 %} | |
| 5605 ins_pipe(iload_mask_mem); | |
| 5606 %} | |
| 5607 | |
| 624 | 5608 // Load Short (16bit signed) into a Long Register |
| 5609 instruct loadS2L(iRegL dst, memory mem) %{ | |
| 5610 match(Set dst (ConvI2L (LoadS mem))); | |
| 0 | 5611 ins_cost(MEMORY_REF_COST); |
| 5612 | |
| 5613 size(4); | |
| 624 | 5614 format %{ "LDSH $mem,$dst\t! short -> long" %} |
| 727 | 5615 ins_encode %{ |
| 5616 __ ldsh($mem$$Address, $dst$$Register); | |
| 5617 %} | |
| 624 | 5618 ins_pipe(iload_mask_mem); |
| 5619 %} | |
| 5620 | |
| 5621 // Load Unsigned Short/Char (16bit UNsigned) | |
| 5622 instruct loadUS(iRegI dst, memory mem) %{ | |
| 5623 match(Set dst (LoadUS mem)); | |
| 5624 ins_cost(MEMORY_REF_COST); | |
| 5625 | |
| 5626 size(4); | |
| 5627 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
| 727 | 5628 ins_encode %{ |
| 5629 __ lduh($mem$$Address, $dst$$Register); | |
| 5630 %} | |
| 824 | 5631 ins_pipe(iload_mem); |
| 0 | 5632 %} |
| 5633 | |
| 785 | 5634 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 5635 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5636 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 5637 ins_cost(MEMORY_REF_COST); | |
| 5638 | |
| 5639 size(4); | |
| 5640 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} | |
| 5641 ins_encode %{ | |
| 5642 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5643 %} | |
| 5644 ins_pipe(iload_mask_mem); | |
| 5645 %} | |
| 5646 | |
|
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551
diff
changeset
|
5647 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
| 624 | 5648 instruct loadUS2L(iRegL dst, memory mem) %{ |
| 5649 match(Set dst (ConvI2L (LoadUS mem))); | |
| 0 | 5650 ins_cost(MEMORY_REF_COST); |
| 5651 | |
| 5652 size(4); | |
| 624 | 5653 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
| 727 | 5654 ins_encode %{ |
| 5655 __ lduh($mem$$Address, $dst$$Register); | |
| 5656 %} | |
| 824 | 5657 ins_pipe(iload_mem); |
| 5658 %} | |
| 5659 | |
| 5660 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register | |
| 5661 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5662 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5663 ins_cost(MEMORY_REF_COST); | |
| 5664 | |
| 5665 size(4); | |
| 5666 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} | |
| 5667 ins_encode %{ | |
| 5668 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE | |
| 5669 %} | |
| 5670 ins_pipe(iload_mem); | |
| 5671 %} | |
| 5672 | |
| 5673 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register | |
| 5674 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
| 5675 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5676 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5677 | |
| 5678 size(2*4); | |
| 5679 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" | |
| 5680 "AND $dst,$mask,$dst" %} | |
| 5681 ins_encode %{ | |
| 5682 Register Rdst = $dst$$Register; | |
| 5683 __ lduh($mem$$Address, Rdst); | |
| 5684 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5685 %} | |
| 5686 ins_pipe(iload_mem); | |
| 5687 %} | |
| 5688 | |
| 5689 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register | |
| 5690 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | |
| 5691 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5692 effect(TEMP dst, TEMP tmp); | |
| 5693 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5694 | |
|
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1fbd5d696bf4
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diff
changeset
|
5695 size((3+1)*4); // set may use two instructions. |
| 824 | 5696 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
| 5697 "SET $mask,$tmp\n\t" | |
| 5698 "AND $dst,$tmp,$dst" %} | |
| 5699 ins_encode %{ | |
| 5700 Register Rdst = $dst$$Register; | |
| 5701 Register Rtmp = $tmp$$Register; | |
| 5702 __ lduh($mem$$Address, Rdst); | |
| 5703 __ set($mask$$constant, Rtmp); | |
| 5704 __ and3(Rdst, Rtmp, Rdst); | |
| 5705 %} | |
| 5706 ins_pipe(iload_mem); | |
| 0 | 5707 %} |
| 5708 | |
| 5709 // Load Integer | |
| 5710 instruct loadI(iRegI dst, memory mem) %{ | |
| 5711 match(Set dst (LoadI mem)); | |
| 5712 ins_cost(MEMORY_REF_COST); | |
| 624 | 5713 |
| 5714 size(4); | |
| 5715 format %{ "LDUW $mem,$dst\t! int" %} | |
| 727 | 5716 ins_encode %{ |
| 5717 __ lduw($mem$$Address, $dst$$Register); | |
| 5718 %} | |
| 624 | 5719 ins_pipe(iload_mem); |
| 5720 %} | |
| 5721 | |
| 785 | 5722 // Load Integer to Byte (8 bit signed) |
| 5723 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5724 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 5725 ins_cost(MEMORY_REF_COST); | |
| 5726 | |
| 5727 size(4); | |
| 5728 | |
| 5729 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} | |
| 5730 ins_encode %{ | |
| 5731 __ ldsb($mem$$Address, $dst$$Register, 3); | |
| 5732 %} | |
| 5733 ins_pipe(iload_mask_mem); | |
| 5734 %} | |
| 5735 | |
| 5736 // Load Integer to Unsigned Byte (8 bit UNsigned) | |
| 5737 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5738 match(Set dst (AndI (LoadI mem) mask)); | |
| 5739 ins_cost(MEMORY_REF_COST); | |
| 5740 | |
| 5741 size(4); | |
| 5742 | |
| 5743 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} | |
| 5744 ins_encode %{ | |
| 5745 __ ldub($mem$$Address, $dst$$Register, 3); | |
| 5746 %} | |
| 5747 ins_pipe(iload_mask_mem); | |
| 5748 %} | |
| 5749 | |
| 5750 // Load Integer to Short (16 bit signed) | |
| 5751 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ | |
| 5752 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 5753 ins_cost(MEMORY_REF_COST); | |
| 5754 | |
| 5755 size(4); | |
| 5756 | |
| 5757 format %{ "LDSH $mem+2,$dst\t! int -> short" %} | |
| 5758 ins_encode %{ | |
| 5759 __ ldsh($mem$$Address, $dst$$Register, 2); | |
| 5760 %} | |
| 5761 ins_pipe(iload_mask_mem); | |
| 5762 %} | |
| 5763 | |
| 5764 // Load Integer to Unsigned Short (16 bit UNsigned) | |
| 5765 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5766 match(Set dst (AndI (LoadI mem) mask)); | |
| 5767 ins_cost(MEMORY_REF_COST); | |
| 5768 | |
| 5769 size(4); | |
| 5770 | |
| 5771 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} | |
| 5772 ins_encode %{ | |
| 5773 __ lduh($mem$$Address, $dst$$Register, 2); | |
| 5774 %} | |
| 5775 ins_pipe(iload_mask_mem); | |
| 5776 %} | |
| 5777 | |
| 624 | 5778 // Load Integer into a Long Register |
| 5779 instruct loadI2L(iRegL dst, memory mem) %{ | |
| 5780 match(Set dst (ConvI2L (LoadI mem))); | |
| 5781 ins_cost(MEMORY_REF_COST); | |
| 5782 | |
| 5783 size(4); | |
| 5784 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
| 727 | 5785 ins_encode %{ |
| 5786 __ ldsw($mem$$Address, $dst$$Register); | |
| 5787 %} | |
| 824 | 5788 ins_pipe(iload_mask_mem); |
| 5789 %} | |
| 5790 | |
| 5791 // Load Integer with mask 0xFF into a Long Register | |
| 5792 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5793 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5794 ins_cost(MEMORY_REF_COST); | |
| 5795 | |
| 5796 size(4); | |
| 5797 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} | |
| 5798 ins_encode %{ | |
| 5799 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE | |
| 5800 %} | |
| 5801 ins_pipe(iload_mem); | |
| 5802 %} | |
| 5803 | |
| 5804 // Load Integer with mask 0xFFFF into a Long Register | |
| 5805 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5806 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5807 ins_cost(MEMORY_REF_COST); | |
| 5808 | |
| 5809 size(4); | |
| 5810 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} | |
| 5811 ins_encode %{ | |
| 5812 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | |
| 5813 %} | |
| 5814 ins_pipe(iload_mem); | |
| 5815 %} | |
| 5816 | |
| 5817 // Load Integer with a 13-bit mask into a Long Register | |
| 5818 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
| 5819 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5820 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5821 | |
| 5822 size(2*4); | |
| 5823 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" | |
| 5824 "AND $dst,$mask,$dst" %} | |
| 5825 ins_encode %{ | |
| 5826 Register Rdst = $dst$$Register; | |
| 5827 __ lduw($mem$$Address, Rdst); | |
| 5828 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5829 %} | |
| 5830 ins_pipe(iload_mem); | |
| 5831 %} | |
| 5832 | |
| 5833 // Load Integer with a 32-bit mask into a Long Register | |
| 5834 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ | |
| 5835 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5836 effect(TEMP dst, TEMP tmp); | |
| 5837 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5838 | |
|
951
1fbd5d696bf4
6875967: CTW fails with./generated/adfiles/ad_sparc.cpp:6711
twisti
parents:
824
diff
changeset
|
5839 size((3+1)*4); // set may use two instructions. |
| 824 | 5840 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" |
| 5841 "SET $mask,$tmp\n\t" | |
| 5842 "AND $dst,$tmp,$dst" %} | |
| 5843 ins_encode %{ | |
| 5844 Register Rdst = $dst$$Register; | |
| 5845 Register Rtmp = $tmp$$Register; | |
| 5846 __ lduw($mem$$Address, Rdst); | |
| 5847 __ set($mask$$constant, Rtmp); | |
| 5848 __ and3(Rdst, Rtmp, Rdst); | |
| 5849 %} | |
| 624 | 5850 ins_pipe(iload_mem); |
| 5851 %} | |
| 5852 | |
| 5853 // Load Unsigned Integer into a Long Register | |
| 5854 instruct loadUI2L(iRegL dst, memory mem) %{ | |
| 5855 match(Set dst (LoadUI2L mem)); | |
| 5856 ins_cost(MEMORY_REF_COST); | |
| 5857 | |
| 5858 size(4); | |
| 5859 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
| 727 | 5860 ins_encode %{ |
| 5861 __ lduw($mem$$Address, $dst$$Register); | |
| 5862 %} | |
| 0 | 5863 ins_pipe(iload_mem); |
| 5864 %} | |
| 5865 | |
| 5866 // Load Long - aligned | |
| 5867 instruct loadL(iRegL dst, memory mem ) %{ | |
| 5868 match(Set dst (LoadL mem)); | |
| 5869 ins_cost(MEMORY_REF_COST); | |
| 624 | 5870 |
| 0 | 5871 size(4); |
| 5872 format %{ "LDX $mem,$dst\t! long" %} | |
| 727 | 5873 ins_encode %{ |
| 5874 __ ldx($mem$$Address, $dst$$Register); | |
| 5875 %} | |
| 0 | 5876 ins_pipe(iload_mem); |
| 5877 %} | |
| 5878 | |
| 5879 // Load Long - UNaligned | |
| 5880 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
| 5881 match(Set dst (LoadL_unaligned mem)); | |
| 5882 effect(KILL tmp); | |
| 5883 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 5884 size(16); | |
| 5885 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
| 5886 "\tLDUW $mem ,$dst\n" | |
| 5887 "\tSLLX #32, $dst, $dst\n" | |
| 5888 "\tOR $dst, R_O7, $dst" %} | |
| 5889 opcode(Assembler::lduw_op3); | |
|
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5890 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
| 0 | 5891 ins_pipe(iload_mem); |
| 5892 %} | |
| 5893 | |
| 5894 // Load Aligned Packed Byte into a Double Register | |
| 5895 instruct loadA8B(regD dst, memory mem) %{ | |
| 5896 match(Set dst (Load8B mem)); | |
| 5897 ins_cost(MEMORY_REF_COST); | |
| 5898 size(4); | |
| 5899 format %{ "LDDF $mem,$dst\t! packed8B" %} | |
| 5900 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
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never
parents:
235
diff
changeset
|
5901 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5902 ins_pipe(floadD_mem); |
| 5903 %} | |
| 5904 | |
| 5905 // Load Aligned Packed Char into a Double Register | |
| 5906 instruct loadA4C(regD dst, memory mem) %{ | |
| 5907 match(Set dst (Load4C mem)); | |
| 5908 ins_cost(MEMORY_REF_COST); | |
| 5909 size(4); | |
| 5910 format %{ "LDDF $mem,$dst\t! packed4C" %} | |
| 5911 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5912 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5913 ins_pipe(floadD_mem); |
| 5914 %} | |
| 5915 | |
| 5916 // Load Aligned Packed Short into a Double Register | |
| 5917 instruct loadA4S(regD dst, memory mem) %{ | |
| 5918 match(Set dst (Load4S mem)); | |
| 5919 ins_cost(MEMORY_REF_COST); | |
| 5920 size(4); | |
| 5921 format %{ "LDDF $mem,$dst\t! packed4S" %} | |
| 5922 opcode(Assembler::lddf_op3); | |
|
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5923 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5924 ins_pipe(floadD_mem); |
| 5925 %} | |
| 5926 | |
| 5927 // Load Aligned Packed Int into a Double Register | |
| 5928 instruct loadA2I(regD dst, memory mem) %{ | |
| 5929 match(Set dst (Load2I mem)); | |
| 5930 ins_cost(MEMORY_REF_COST); | |
| 5931 size(4); | |
| 5932 format %{ "LDDF $mem,$dst\t! packed2I" %} | |
| 5933 opcode(Assembler::lddf_op3); | |
|
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5934 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5935 ins_pipe(floadD_mem); |
| 5936 %} | |
| 5937 | |
| 5938 // Load Range | |
| 5939 instruct loadRange(iRegI dst, memory mem) %{ | |
| 5940 match(Set dst (LoadRange mem)); | |
| 5941 ins_cost(MEMORY_REF_COST); | |
| 5942 | |
| 5943 size(4); | |
| 5944 format %{ "LDUW $mem,$dst\t! range" %} | |
| 5945 opcode(Assembler::lduw_op3); | |
|
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5946 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5947 ins_pipe(iload_mem); |
| 5948 %} | |
| 5949 | |
| 5950 // Load Integer into %f register (for fitos/fitod) | |
| 5951 instruct loadI_freg(regF dst, memory mem) %{ | |
| 5952 match(Set dst (LoadI mem)); | |
| 5953 ins_cost(MEMORY_REF_COST); | |
| 5954 size(4); | |
| 5955 | |
| 5956 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
| 5957 opcode(Assembler::ldf_op3); | |
|
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5958 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5959 ins_pipe(floadF_mem); |
| 5960 %} | |
| 5961 | |
| 5962 // Load Pointer | |
| 5963 instruct loadP(iRegP dst, memory mem) %{ | |
| 5964 match(Set dst (LoadP mem)); | |
| 5965 ins_cost(MEMORY_REF_COST); | |
| 5966 size(4); | |
| 5967 | |
| 5968 #ifndef _LP64 | |
| 5969 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 727 | 5970 ins_encode %{ |
| 5971 __ lduw($mem$$Address, $dst$$Register); | |
| 5972 %} | |
| 0 | 5973 #else |
| 5974 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 727 | 5975 ins_encode %{ |
| 5976 __ ldx($mem$$Address, $dst$$Register); | |
| 5977 %} | |
| 0 | 5978 #endif |
| 5979 ins_pipe(iload_mem); | |
| 5980 %} | |
| 5981 | |
|
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5982 // Load Compressed Pointer |
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5983 instruct loadN(iRegN dst, memory mem) %{ |
| 727 | 5984 match(Set dst (LoadN mem)); |
| 5985 ins_cost(MEMORY_REF_COST); | |
| 5986 size(4); | |
| 5987 | |
| 5988 format %{ "LDUW $mem,$dst\t! compressed ptr" %} | |
| 5989 ins_encode %{ | |
| 5990 __ lduw($mem$$Address, $dst$$Register); | |
| 5991 %} | |
| 5992 ins_pipe(iload_mem); | |
|
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5993 %} |
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5994 |
| 0 | 5995 // Load Klass Pointer |
| 5996 instruct loadKlass(iRegP dst, memory mem) %{ | |
| 5997 match(Set dst (LoadKlass mem)); | |
| 5998 ins_cost(MEMORY_REF_COST); | |
| 5999 size(4); | |
| 6000 | |
| 6001 #ifndef _LP64 | |
| 6002 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
| 727 | 6003 ins_encode %{ |
| 6004 __ lduw($mem$$Address, $dst$$Register); | |
| 6005 %} | |
| 0 | 6006 #else |
| 6007 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
| 727 | 6008 ins_encode %{ |
| 6009 __ ldx($mem$$Address, $dst$$Register); | |
| 6010 %} | |
| 0 | 6011 #endif |
| 6012 ins_pipe(iload_mem); | |
| 6013 %} | |
| 6014 | |
|
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6015 // Load narrow Klass Pointer |
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6016 instruct loadNKlass(iRegN dst, memory mem) %{ |
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6017 match(Set dst (LoadNKlass mem)); |
|
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6018 ins_cost(MEMORY_REF_COST); |
|
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6019 size(4); |
|
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6020 |
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6021 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
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6022 ins_encode %{ |
| 727 | 6023 __ lduw($mem$$Address, $dst$$Register); |
|
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6024 %} |
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6025 ins_pipe(iload_mem); |
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6026 %} |
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6027 |
| 0 | 6028 // Load Double |
| 6029 instruct loadD(regD dst, memory mem) %{ | |
| 6030 match(Set dst (LoadD mem)); | |
| 6031 ins_cost(MEMORY_REF_COST); | |
| 6032 | |
| 6033 size(4); | |
| 6034 format %{ "LDDF $mem,$dst" %} | |
| 6035 opcode(Assembler::lddf_op3); | |
|
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6036 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 6037 ins_pipe(floadD_mem); |
| 6038 %} | |
| 6039 | |
| 6040 // Load Double - UNaligned | |
| 6041 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
| 6042 match(Set dst (LoadD_unaligned mem)); | |
| 6043 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 6044 size(8); | |
| 6045 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
| 6046 "\tLDF $mem+4,$dst.lo\t!" %} | |
| 6047 opcode(Assembler::ldf_op3); | |
| 6048 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
| 6049 ins_pipe(iload_mem); | |
| 6050 %} | |
| 6051 | |
| 6052 // Load Float | |
| 6053 instruct loadF(regF dst, memory mem) %{ | |
| 6054 match(Set dst (LoadF mem)); | |
| 6055 ins_cost(MEMORY_REF_COST); | |
| 6056 | |
| 6057 size(4); | |
| 6058 format %{ "LDF $mem,$dst" %} | |
| 6059 opcode(Assembler::ldf_op3); | |
|
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6060 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 6061 ins_pipe(floadF_mem); |
| 6062 %} | |
| 6063 | |
| 6064 // Load Constant | |
| 6065 instruct loadConI( iRegI dst, immI src ) %{ | |
| 6066 match(Set dst src); | |
| 6067 ins_cost(DEFAULT_COST * 3/2); | |
| 6068 format %{ "SET $src,$dst" %} | |
| 6069 ins_encode( Set32(src, dst) ); | |
| 6070 ins_pipe(ialu_hi_lo_reg); | |
| 6071 %} | |
| 6072 | |
| 6073 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
| 6074 match(Set dst src); | |
| 6075 | |
| 6076 size(4); | |
| 6077 format %{ "MOV $src,$dst" %} | |
| 6078 ins_encode( Set13( src, dst ) ); | |
| 6079 ins_pipe(ialu_imm); | |
| 6080 %} | |
| 6081 | |
| 2008 | 6082 #ifndef _LP64 |
| 6083 instruct loadConP(iRegP dst, immP con) %{ | |
| 6084 match(Set dst con); | |
| 6085 ins_cost(DEFAULT_COST * 3/2); | |
| 6086 format %{ "SET $con,$dst\t!ptr" %} | |
| 6087 ins_encode %{ | |
| 6088 // [RGV] This next line should be generated from ADLC | |
| 6089 if (_opnds[1]->constant_is_oop()) { | |
| 6090 intptr_t val = $con$$constant; | |
| 6091 __ set_oop_constant((jobject) val, $dst$$Register); | |
| 6092 } else { // non-oop pointers, e.g. card mark base, heap top | |
| 6093 __ set($con$$constant, $dst$$Register); | |
| 6094 } | |
| 6095 %} | |
| 6096 ins_pipe(loadConP); | |
| 6097 %} | |
| 6098 #else | |
| 6099 instruct loadConP_set(iRegP dst, immP_set con) %{ | |
| 6100 match(Set dst con); | |
| 0 | 6101 ins_cost(DEFAULT_COST * 3/2); |
| 2008 | 6102 format %{ "SET $con,$dst\t! ptr" %} |
| 6103 ins_encode %{ | |
| 6104 // [RGV] This next line should be generated from ADLC | |
| 6105 if (_opnds[1]->constant_is_oop()) { | |
| 6106 intptr_t val = $con$$constant; | |
| 6107 __ set_oop_constant((jobject) val, $dst$$Register); | |
| 6108 } else { // non-oop pointers, e.g. card mark base, heap top | |
| 6109 __ set($con$$constant, $dst$$Register); | |
| 6110 } | |
| 6111 %} | |
| 0 | 6112 ins_pipe(loadConP); |
| 2008 | 6113 %} |
| 6114 | |
| 6115 instruct loadConP_load(iRegP dst, immP_load con) %{ | |
| 6116 match(Set dst con); | |
| 6117 ins_cost(MEMORY_REF_COST); | |
| 6118 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} | |
| 6119 ins_encode %{ | |
|
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6120 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
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6121 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); |
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6122 %} |
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6123 ins_pipe(loadConP); |
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6124 %} |
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6125 |
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6126 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ |
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6127 match(Set dst con); |
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6128 ins_cost(DEFAULT_COST * 3/2); |
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6129 format %{ "SET $con,$dst\t! non-oop ptr" %} |
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6130 ins_encode %{ |
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6131 __ set($con$$constant, $dst$$Register); |
| 2008 | 6132 %} |
| 6133 ins_pipe(loadConP); | |
| 6134 %} | |
| 6135 #endif // _LP64 | |
| 0 | 6136 |
| 6137 instruct loadConP0(iRegP dst, immP0 src) %{ | |
| 6138 match(Set dst src); | |
| 6139 | |
| 6140 size(4); | |
| 6141 format %{ "CLR $dst\t!ptr" %} | |
| 2008 | 6142 ins_encode %{ |
| 6143 __ clr($dst$$Register); | |
| 6144 %} | |
| 0 | 6145 ins_pipe(ialu_imm); |
| 6146 %} | |
| 6147 | |
| 6148 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
| 6149 match(Set dst src); | |
| 6150 ins_cost(DEFAULT_COST); | |
| 6151 format %{ "SET $src,$dst\t!ptr" %} | |
| 6152 ins_encode %{ | |
| 727 | 6153 AddressLiteral polling_page(os::get_polling_page()); |
| 6154 __ sethi(polling_page, reg_to_register_object($dst$$reg)); | |
| 0 | 6155 %} |
| 6156 ins_pipe(loadConP_poll); | |
| 6157 %} | |
| 6158 | |
|
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6159 instruct loadConN0(iRegN dst, immN0 src) %{ |
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6160 match(Set dst src); |
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6161 |
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6162 size(4); |
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6163 format %{ "CLR $dst\t! compressed NULL ptr" %} |
| 2008 | 6164 ins_encode %{ |
| 6165 __ clr($dst$$Register); | |
| 6166 %} | |
|
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6167 ins_pipe(ialu_imm); |
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6168 %} |
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6169 |
|
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6170 instruct loadConN(iRegN dst, immN src) %{ |
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6171 match(Set dst src); |
|
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6172 ins_cost(DEFAULT_COST * 3/2); |
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6173 format %{ "SET $src,$dst\t! compressed ptr" %} |
|
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6174 ins_encode %{ |
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6175 Register dst = $dst$$Register; |
|
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6176 __ set_narrow_oop((jobject)$src$$constant, dst); |
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6177 %} |
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6178 ins_pipe(ialu_hi_lo_reg); |
|
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6179 %} |
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6180 |
| 2008 | 6181 // Materialize long value (predicated by immL_cheap). |
| 6182 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ | |
| 6183 match(Set dst con); | |
| 0 | 6184 effect(KILL tmp); |
| 2008 | 6185 ins_cost(DEFAULT_COST * 3); |
| 6186 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} | |
| 6187 ins_encode %{ | |
| 6188 __ set64($con$$constant, $dst$$Register, $tmp$$Register); | |
| 6189 %} | |
| 6190 ins_pipe(loadConL); | |
| 6191 %} | |
| 6192 | |
| 6193 // Load long value from constant table (predicated by immL_expensive). | |
| 6194 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ | |
| 6195 match(Set dst con); | |
| 6196 ins_cost(MEMORY_REF_COST); | |
| 6197 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} | |
| 6198 ins_encode %{ | |
|
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6199 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
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|
6200 __ ldx($constanttablebase, con_offset, $dst$$Register); |
| 2008 | 6201 %} |
| 0 | 6202 ins_pipe(loadConL); |
| 6203 %} | |
| 6204 | |
| 6205 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
| 6206 match(Set dst src); | |
| 6207 ins_cost(DEFAULT_COST); | |
| 6208 size(4); | |
| 6209 format %{ "CLR $dst\t! long" %} | |
| 6210 ins_encode( Set13( src, dst ) ); | |
| 6211 ins_pipe(ialu_imm); | |
| 6212 %} | |
| 6213 | |
| 6214 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
| 6215 match(Set dst src); | |
| 6216 ins_cost(DEFAULT_COST * 2); | |
| 6217 | |
| 6218 size(4); | |
| 6219 format %{ "MOV $src,$dst\t! long" %} | |
| 6220 ins_encode( Set13( src, dst ) ); | |
| 6221 ins_pipe(ialu_imm); | |
| 6222 %} | |
| 6223 | |
|
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6224 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ |
| 2008 | 6225 match(Set dst con); |
|
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|
6226 effect(KILL tmp); |
| 2008 | 6227 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} |
| 727 | 6228 ins_encode %{ |
|
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7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6229 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6230 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); |
| 727 | 6231 %} |
| 0 | 6232 ins_pipe(loadConFD); |
| 6233 %} | |
| 6234 | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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2008
diff
changeset
|
6235 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ |
| 2008 | 6236 match(Set dst con); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6237 effect(KILL tmp); |
| 2008 | 6238 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} |
| 727 | 6239 ins_encode %{ |
|
732
fb4c18a2ec66
6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents:
727
diff
changeset
|
6240 // XXX This is a quick fix for 6833573. |
| 2008 | 6241 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6242 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6243 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 727 | 6244 %} |
| 0 | 6245 ins_pipe(loadConFD); |
| 6246 %} | |
| 6247 | |
| 6248 // Prefetch instructions. | |
| 6249 // Must be safe to execute with invalid address (cannot fault). | |
| 6250 | |
| 6251 instruct prefetchr( memory mem ) %{ | |
| 6252 match( PrefetchRead mem ); | |
| 6253 ins_cost(MEMORY_REF_COST); | |
| 6254 | |
| 6255 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
| 6256 opcode(Assembler::prefetch_op3); | |
| 6257 ins_encode( form3_mem_prefetch_read( mem ) ); | |
| 6258 ins_pipe(iload_mem); | |
| 6259 %} | |
| 6260 | |
| 6261 instruct prefetchw( memory mem ) %{ | |
|
1367
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6940726: Use BIS instruction for allocation prefetch on Sparc
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1274
diff
changeset
|
6262 predicate(AllocatePrefetchStyle != 3 ); |
| 0 | 6263 match( PrefetchWrite mem ); |
| 6264 ins_cost(MEMORY_REF_COST); | |
| 6265 | |
| 6266 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
| 6267 opcode(Assembler::prefetch_op3); | |
| 6268 ins_encode( form3_mem_prefetch_write( mem ) ); | |
| 6269 ins_pipe(iload_mem); | |
| 6270 %} | |
| 6271 | |
|
1367
9e321dcfa5b7
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parents:
1274
diff
changeset
|
6272 // Use BIS instruction to prefetch. |
|
9e321dcfa5b7
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kvn
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1274
diff
changeset
|
6273 instruct prefetchw_bis( memory mem ) %{ |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
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1274
diff
changeset
|
6274 predicate(AllocatePrefetchStyle == 3); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6275 match( PrefetchWrite mem ); |
|
9e321dcfa5b7
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1274
diff
changeset
|
6276 ins_cost(MEMORY_REF_COST); |
|
9e321dcfa5b7
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1274
diff
changeset
|
6277 |
|
9e321dcfa5b7
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1274
diff
changeset
|
6278 format %{ "STXA G0,$mem\t! // Block initializing store" %} |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6279 ins_encode %{ |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6280 Register base = as_Register($mem$$base); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
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diff
changeset
|
6281 int disp = $mem$$disp; |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6282 if (disp != 0) { |
|
9e321dcfa5b7
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kvn
parents:
1274
diff
changeset
|
6283 __ add(base, AllocatePrefetchStepSize, base); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6284 } |
|
9e321dcfa5b7
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kvn
parents:
1274
diff
changeset
|
6285 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
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1274
diff
changeset
|
6286 %} |
|
9e321dcfa5b7
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kvn
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1274
diff
changeset
|
6287 ins_pipe(istore_mem_reg); |
|
9e321dcfa5b7
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kvn
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1274
diff
changeset
|
6288 %} |
| 0 | 6289 |
| 6290 //----------Store Instructions------------------------------------------------- | |
| 6291 // Store Byte | |
| 6292 instruct storeB(memory mem, iRegI src) %{ | |
| 6293 match(Set mem (StoreB mem src)); | |
| 6294 ins_cost(MEMORY_REF_COST); | |
| 6295 | |
| 6296 size(4); | |
| 6297 format %{ "STB $src,$mem\t! byte" %} | |
| 6298 opcode(Assembler::stb_op3); | |
|
415
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235
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changeset
|
6299 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6300 ins_pipe(istore_mem_reg); |
| 6301 %} | |
| 6302 | |
| 6303 instruct storeB0(memory mem, immI0 src) %{ | |
| 6304 match(Set mem (StoreB mem src)); | |
| 6305 ins_cost(MEMORY_REF_COST); | |
| 6306 | |
| 6307 size(4); | |
| 6308 format %{ "STB $src,$mem\t! byte" %} | |
| 6309 opcode(Assembler::stb_op3); | |
|
415
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235
diff
changeset
|
6310 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6311 ins_pipe(istore_mem_zero); |
| 6312 %} | |
| 6313 | |
| 6314 instruct storeCM0(memory mem, immI0 src) %{ | |
| 6315 match(Set mem (StoreCM mem src)); | |
| 6316 ins_cost(MEMORY_REF_COST); | |
| 6317 | |
| 6318 size(4); | |
| 6319 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
| 6320 opcode(Assembler::stb_op3); | |
|
415
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235
diff
changeset
|
6321 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6322 ins_pipe(istore_mem_zero); |
| 6323 %} | |
| 6324 | |
| 6325 // Store Char/Short | |
| 6326 instruct storeC(memory mem, iRegI src) %{ | |
| 6327 match(Set mem (StoreC mem src)); | |
| 6328 ins_cost(MEMORY_REF_COST); | |
| 6329 | |
| 6330 size(4); | |
| 6331 format %{ "STH $src,$mem\t! short" %} | |
| 6332 opcode(Assembler::sth_op3); | |
|
415
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235
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|
6333 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6334 ins_pipe(istore_mem_reg); |
| 6335 %} | |
| 6336 | |
| 6337 instruct storeC0(memory mem, immI0 src) %{ | |
| 6338 match(Set mem (StoreC mem src)); | |
| 6339 ins_cost(MEMORY_REF_COST); | |
| 6340 | |
| 6341 size(4); | |
| 6342 format %{ "STH $src,$mem\t! short" %} | |
| 6343 opcode(Assembler::sth_op3); | |
|
415
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235
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|
6344 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6345 ins_pipe(istore_mem_zero); |
| 6346 %} | |
| 6347 | |
| 6348 // Store Integer | |
| 6349 instruct storeI(memory mem, iRegI src) %{ | |
| 6350 match(Set mem (StoreI mem src)); | |
| 6351 ins_cost(MEMORY_REF_COST); | |
| 6352 | |
| 6353 size(4); | |
| 6354 format %{ "STW $src,$mem" %} | |
| 6355 opcode(Assembler::stw_op3); | |
|
415
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235
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|
6356 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6357 ins_pipe(istore_mem_reg); |
| 6358 %} | |
| 6359 | |
| 6360 // Store Long | |
| 6361 instruct storeL(memory mem, iRegL src) %{ | |
| 6362 match(Set mem (StoreL mem src)); | |
| 6363 ins_cost(MEMORY_REF_COST); | |
| 6364 size(4); | |
| 6365 format %{ "STX $src,$mem\t! long" %} | |
| 6366 opcode(Assembler::stx_op3); | |
|
415
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235
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|
6367 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6368 ins_pipe(istore_mem_reg); |
| 6369 %} | |
| 6370 | |
| 6371 instruct storeI0(memory mem, immI0 src) %{ | |
| 6372 match(Set mem (StoreI mem src)); | |
| 6373 ins_cost(MEMORY_REF_COST); | |
| 6374 | |
| 6375 size(4); | |
| 6376 format %{ "STW $src,$mem" %} | |
| 6377 opcode(Assembler::stw_op3); | |
|
415
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235
diff
changeset
|
6378 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6379 ins_pipe(istore_mem_zero); |
| 6380 %} | |
| 6381 | |
| 6382 instruct storeL0(memory mem, immL0 src) %{ | |
| 6383 match(Set mem (StoreL mem src)); | |
| 6384 ins_cost(MEMORY_REF_COST); | |
| 6385 | |
| 6386 size(4); | |
| 6387 format %{ "STX $src,$mem" %} | |
| 6388 opcode(Assembler::stx_op3); | |
|
415
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235
diff
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|
6389 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6390 ins_pipe(istore_mem_zero); |
| 6391 %} | |
| 6392 | |
| 6393 // Store Integer from float register (used after fstoi) | |
| 6394 instruct storeI_Freg(memory mem, regF src) %{ | |
| 6395 match(Set mem (StoreI mem src)); | |
| 6396 ins_cost(MEMORY_REF_COST); | |
| 6397 | |
| 6398 size(4); | |
| 6399 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
| 6400 opcode(Assembler::stf_op3); | |
|
415
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|
6401 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6402 ins_pipe(fstoreF_mem_reg); |
| 6403 %} | |
| 6404 | |
| 6405 // Store Pointer | |
| 6406 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
| 6407 match(Set dst (StoreP dst src)); | |
| 6408 ins_cost(MEMORY_REF_COST); | |
| 6409 size(4); | |
| 6410 | |
| 6411 #ifndef _LP64 | |
| 6412 format %{ "STW $src,$dst\t! ptr" %} | |
| 6413 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6414 #else | |
| 6415 format %{ "STX $src,$dst\t! ptr" %} | |
| 6416 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6417 #endif | |
| 6418 ins_encode( form3_mem_reg( dst, src ) ); | |
| 6419 ins_pipe(istore_mem_spORreg); | |
| 6420 %} | |
| 6421 | |
| 6422 instruct storeP0(memory dst, immP0 src) %{ | |
| 6423 match(Set dst (StoreP dst src)); | |
| 6424 ins_cost(MEMORY_REF_COST); | |
| 6425 size(4); | |
| 6426 | |
| 6427 #ifndef _LP64 | |
| 6428 format %{ "STW $src,$dst\t! ptr" %} | |
| 6429 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6430 #else | |
| 6431 format %{ "STX $src,$dst\t! ptr" %} | |
| 6432 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6433 #endif | |
| 6434 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
| 6435 ins_pipe(istore_mem_zero); | |
| 6436 %} | |
| 6437 | |
|
113
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|
6438 // Store Compressed Pointer |
|
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|
6439 instruct storeN(memory dst, iRegN src) %{ |
|
ba764ed4b6f2
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diff
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|
6440 match(Set dst (StoreN dst src)); |
|
ba764ed4b6f2
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|
6441 ins_cost(MEMORY_REF_COST); |
|
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|
6442 size(4); |
|
ba764ed4b6f2
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diff
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|
6443 |
|
ba764ed4b6f2
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|
6444 format %{ "STW $src,$dst\t! compressed ptr" %} |
|
ba764ed4b6f2
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|
6445 ins_encode %{ |
|
ba764ed4b6f2
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diff
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|
6446 Register base = as_Register($dst$$base); |
|
ba764ed4b6f2
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|
6447 Register index = as_Register($dst$$index); |
|
ba764ed4b6f2
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|
6448 Register src = $src$$Register; |
|
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|
6449 if (index != G0) { |
|
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diff
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|
6450 __ stw(src, base, index); |
|
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|
6451 } else { |
|
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|
6452 __ stw(src, base, $dst$$disp); |
|
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|
6453 } |
|
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|
6454 %} |
|
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|
6455 ins_pipe(istore_mem_spORreg); |
|
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|
6456 %} |
|
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|
6457 |
|
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changeset
|
6458 instruct storeN0(memory dst, immN0 src) %{ |
|
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|
6459 match(Set dst (StoreN dst src)); |
|
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|
6460 ins_cost(MEMORY_REF_COST); |
|
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|
6461 size(4); |
|
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|
6462 |
|
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|
6463 format %{ "STW $src,$dst\t! compressed ptr" %} |
|
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|
6464 ins_encode %{ |
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|
6465 Register base = as_Register($dst$$base); |
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|
6466 Register index = as_Register($dst$$index); |
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|
6467 if (index != G0) { |
|
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|
6468 __ stw(0, base, index); |
|
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|
6469 } else { |
|
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|
6470 __ stw(0, base, $dst$$disp); |
|
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|
6471 } |
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|
6472 %} |
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|
6473 ins_pipe(istore_mem_zero); |
|
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|
6474 %} |
|
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|
6475 |
| 0 | 6476 // Store Double |
| 6477 instruct storeD( memory mem, regD src) %{ | |
| 6478 match(Set mem (StoreD mem src)); | |
| 6479 ins_cost(MEMORY_REF_COST); | |
| 6480 | |
| 6481 size(4); | |
| 6482 format %{ "STDF $src,$mem" %} | |
| 6483 opcode(Assembler::stdf_op3); | |
|
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|
6484 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6485 ins_pipe(fstoreD_mem_reg); |
| 6486 %} | |
| 6487 | |
| 6488 instruct storeD0( memory mem, immD0 src) %{ | |
| 6489 match(Set mem (StoreD mem src)); | |
| 6490 ins_cost(MEMORY_REF_COST); | |
| 6491 | |
| 6492 size(4); | |
| 6493 format %{ "STX $src,$mem" %} | |
| 6494 opcode(Assembler::stx_op3); | |
|
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|
6495 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6496 ins_pipe(fstoreD_mem_zero); |
| 6497 %} | |
| 6498 | |
| 6499 // Store Float | |
| 6500 instruct storeF( memory mem, regF src) %{ | |
| 6501 match(Set mem (StoreF mem src)); | |
| 6502 ins_cost(MEMORY_REF_COST); | |
| 6503 | |
| 6504 size(4); | |
| 6505 format %{ "STF $src,$mem" %} | |
| 6506 opcode(Assembler::stf_op3); | |
|
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|
6507 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6508 ins_pipe(fstoreF_mem_reg); |
| 6509 %} | |
| 6510 | |
| 6511 instruct storeF0( memory mem, immF0 src) %{ | |
| 6512 match(Set mem (StoreF mem src)); | |
| 6513 ins_cost(MEMORY_REF_COST); | |
| 6514 | |
| 6515 size(4); | |
| 6516 format %{ "STW $src,$mem\t! storeF0" %} | |
| 6517 opcode(Assembler::stw_op3); | |
|
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|
6518 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6519 ins_pipe(fstoreF_mem_zero); |
| 6520 %} | |
| 6521 | |
| 6522 // Store Aligned Packed Bytes in Double register to memory | |
| 6523 instruct storeA8B(memory mem, regD src) %{ | |
| 6524 match(Set mem (Store8B mem src)); | |
| 6525 ins_cost(MEMORY_REF_COST); | |
| 6526 size(4); | |
| 6527 format %{ "STDF $src,$mem\t! packed8B" %} | |
| 6528 opcode(Assembler::stdf_op3); | |
|
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|
6529 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6530 ins_pipe(fstoreD_mem_reg); |
| 6531 %} | |
| 6532 | |
|
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6533 // Convert oop pointer into compressed form |
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6534 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
|
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|
6535 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
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6536 match(Set dst (EncodeP src)); |
|
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6537 format %{ "encode_heap_oop $src, $dst" %} |
|
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6538 ins_encode %{ |
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6539 __ encode_heap_oop($src$$Register, $dst$$Register); |
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6540 %} |
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|
6541 ins_pipe(ialu_reg); |
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6542 %} |
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|
6543 |
|
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6544 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
|
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6545 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
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6546 match(Set dst (EncodeP src)); |
|
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6547 format %{ "encode_heap_oop_not_null $src, $dst" %} |
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|
6548 ins_encode %{ |
|
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|
6549 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
|
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6550 %} |
|
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|
6551 ins_pipe(ialu_reg); |
|
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|
6552 %} |
|
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|
6553 |
|
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6554 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
|
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6555 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
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6556 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
|
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6557 match(Set dst (DecodeN src)); |
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6558 format %{ "decode_heap_oop $src, $dst" %} |
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6559 ins_encode %{ |
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6560 __ decode_heap_oop($src$$Register, $dst$$Register); |
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6561 %} |
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|
6562 ins_pipe(ialu_reg); |
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6563 %} |
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|
6564 |
|
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|
6565 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
|
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|
6566 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
|
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|
6567 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
|
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6568 match(Set dst (DecodeN src)); |
|
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|
6569 format %{ "decode_heap_oop_not_null $src, $dst" %} |
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|
6570 ins_encode %{ |
|
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|
6571 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
|
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|
6572 %} |
|
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|
6573 ins_pipe(ialu_reg); |
|
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|
6574 %} |
|
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|
6575 |
|
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6576 |
| 0 | 6577 // Store Zero into Aligned Packed Bytes |
| 6578 instruct storeA8B0(memory mem, immI0 zero) %{ | |
| 6579 match(Set mem (Store8B mem zero)); | |
| 6580 ins_cost(MEMORY_REF_COST); | |
| 6581 size(4); | |
| 6582 format %{ "STX $zero,$mem\t! packed8B" %} | |
| 6583 opcode(Assembler::stx_op3); | |
|
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|
6584 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6585 ins_pipe(fstoreD_mem_zero); |
| 6586 %} | |
| 6587 | |
| 6588 // Store Aligned Packed Chars/Shorts in Double register to memory | |
| 6589 instruct storeA4C(memory mem, regD src) %{ | |
| 6590 match(Set mem (Store4C mem src)); | |
| 6591 ins_cost(MEMORY_REF_COST); | |
| 6592 size(4); | |
| 6593 format %{ "STDF $src,$mem\t! packed4C" %} | |
| 6594 opcode(Assembler::stdf_op3); | |
|
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|
6595 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6596 ins_pipe(fstoreD_mem_reg); |
| 6597 %} | |
| 6598 | |
| 6599 // Store Zero into Aligned Packed Chars/Shorts | |
| 6600 instruct storeA4C0(memory mem, immI0 zero) %{ | |
| 6601 match(Set mem (Store4C mem (Replicate4C zero))); | |
| 6602 ins_cost(MEMORY_REF_COST); | |
| 6603 size(4); | |
| 6604 format %{ "STX $zero,$mem\t! packed4C" %} | |
| 6605 opcode(Assembler::stx_op3); | |
|
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|
6606 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6607 ins_pipe(fstoreD_mem_zero); |
| 6608 %} | |
| 6609 | |
| 6610 // Store Aligned Packed Ints in Double register to memory | |
| 6611 instruct storeA2I(memory mem, regD src) %{ | |
| 6612 match(Set mem (Store2I mem src)); | |
| 6613 ins_cost(MEMORY_REF_COST); | |
| 6614 size(4); | |
| 6615 format %{ "STDF $src,$mem\t! packed2I" %} | |
| 6616 opcode(Assembler::stdf_op3); | |
|
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6617 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6618 ins_pipe(fstoreD_mem_reg); |
| 6619 %} | |
| 6620 | |
| 6621 // Store Zero into Aligned Packed Ints | |
| 6622 instruct storeA2I0(memory mem, immI0 zero) %{ | |
| 6623 match(Set mem (Store2I mem zero)); | |
| 6624 ins_cost(MEMORY_REF_COST); | |
| 6625 size(4); | |
| 6626 format %{ "STX $zero,$mem\t! packed2I" %} | |
| 6627 opcode(Assembler::stx_op3); | |
|
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|
6628 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6629 ins_pipe(fstoreD_mem_zero); |
| 6630 %} | |
| 6631 | |
| 6632 | |
| 6633 //----------MemBar Instructions----------------------------------------------- | |
| 6634 // Memory barrier flavors | |
| 6635 | |
| 6636 instruct membar_acquire() %{ | |
| 6637 match(MemBarAcquire); | |
| 6638 ins_cost(4*MEMORY_REF_COST); | |
| 6639 | |
| 6640 size(0); | |
| 6641 format %{ "MEMBAR-acquire" %} | |
| 6642 ins_encode( enc_membar_acquire ); | |
| 6643 ins_pipe(long_memory_op); | |
| 6644 %} | |
| 6645 | |
| 6646 instruct membar_acquire_lock() %{ | |
| 6647 match(MemBarAcquire); | |
| 6648 predicate(Matcher::prior_fast_lock(n)); | |
| 6649 ins_cost(0); | |
| 6650 | |
| 6651 size(0); | |
| 6652 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
| 6653 ins_encode( ); | |
| 6654 ins_pipe(empty); | |
| 6655 %} | |
| 6656 | |
| 6657 instruct membar_release() %{ | |
| 6658 match(MemBarRelease); | |
| 6659 ins_cost(4*MEMORY_REF_COST); | |
| 6660 | |
| 6661 size(0); | |
| 6662 format %{ "MEMBAR-release" %} | |
| 6663 ins_encode( enc_membar_release ); | |
| 6664 ins_pipe(long_memory_op); | |
| 6665 %} | |
| 6666 | |
| 6667 instruct membar_release_lock() %{ | |
| 6668 match(MemBarRelease); | |
| 6669 predicate(Matcher::post_fast_unlock(n)); | |
| 6670 ins_cost(0); | |
| 6671 | |
| 6672 size(0); | |
| 6673 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
| 6674 ins_encode( ); | |
| 6675 ins_pipe(empty); | |
| 6676 %} | |
| 6677 | |
| 6678 instruct membar_volatile() %{ | |
| 6679 match(MemBarVolatile); | |
| 6680 ins_cost(4*MEMORY_REF_COST); | |
| 6681 | |
| 6682 size(4); | |
| 6683 format %{ "MEMBAR-volatile" %} | |
| 6684 ins_encode( enc_membar_volatile ); | |
| 6685 ins_pipe(long_memory_op); | |
| 6686 %} | |
| 6687 | |
| 6688 instruct unnecessary_membar_volatile() %{ | |
| 6689 match(MemBarVolatile); | |
| 6690 predicate(Matcher::post_store_load_barrier(n)); | |
| 6691 ins_cost(0); | |
| 6692 | |
| 6693 size(0); | |
| 6694 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6695 ins_encode( ); | |
| 6696 ins_pipe(empty); | |
| 6697 %} | |
| 6698 | |
| 6699 //----------Register Move Instructions----------------------------------------- | |
| 6700 instruct roundDouble_nop(regD dst) %{ | |
| 6701 match(Set dst (RoundDouble dst)); | |
| 6702 ins_cost(0); | |
| 6703 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6704 ins_encode( ); | |
| 6705 ins_pipe(empty); | |
| 6706 %} | |
| 6707 | |
| 6708 | |
| 6709 instruct roundFloat_nop(regF dst) %{ | |
| 6710 match(Set dst (RoundFloat dst)); | |
| 6711 ins_cost(0); | |
| 6712 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6713 ins_encode( ); | |
| 6714 ins_pipe(empty); | |
| 6715 %} | |
| 6716 | |
| 6717 | |
| 6718 // Cast Index to Pointer for unsafe natives | |
| 6719 instruct castX2P(iRegX src, iRegP dst) %{ | |
| 6720 match(Set dst (CastX2P src)); | |
| 6721 | |
| 6722 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
| 6723 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6724 ins_pipe(ialu_reg); | |
| 6725 %} | |
| 6726 | |
| 6727 // Cast Pointer to Index for unsafe natives | |
| 6728 instruct castP2X(iRegP src, iRegX dst) %{ | |
| 6729 match(Set dst (CastP2X src)); | |
| 6730 | |
| 6731 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
| 6732 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6733 ins_pipe(ialu_reg); | |
| 6734 %} | |
| 6735 | |
| 6736 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
| 6737 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6738 match(Set stkSlot src); // chain rule | |
| 6739 ins_cost(MEMORY_REF_COST); | |
| 6740 format %{ "STDF $src,$stkSlot\t!stk" %} | |
| 6741 opcode(Assembler::stdf_op3); | |
|
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|
6742 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6743 ins_pipe(fstoreD_stk_reg); |
| 6744 %} | |
| 6745 | |
| 6746 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
| 6747 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6748 match(Set dst stkSlot); // chain rule | |
| 6749 ins_cost(MEMORY_REF_COST); | |
| 6750 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
| 6751 opcode(Assembler::lddf_op3); | |
|
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|
6752 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
| 0 | 6753 ins_pipe(floadD_stk); |
| 6754 %} | |
| 6755 | |
| 6756 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
| 6757 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6758 match(Set stkSlot src); // chain rule | |
| 6759 ins_cost(MEMORY_REF_COST); | |
| 6760 format %{ "STF $src,$stkSlot\t!stk" %} | |
| 6761 opcode(Assembler::stf_op3); | |
|
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|
6762 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6763 ins_pipe(fstoreF_stk_reg); |
| 6764 %} | |
| 6765 | |
| 6766 //----------Conditional Move--------------------------------------------------- | |
| 6767 // Conditional move | |
| 6768 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
| 6769 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6770 ins_cost(150); | |
| 6771 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6772 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6773 ins_pipe(ialu_reg); | |
| 6774 %} | |
| 6775 | |
| 6776 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
| 6777 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6778 ins_cost(140); | |
| 6779 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6780 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6781 ins_pipe(ialu_imm); | |
| 6782 %} | |
| 6783 | |
| 6784 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
| 6785 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6786 ins_cost(150); | |
| 6787 size(4); | |
| 6788 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6789 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6790 ins_pipe(ialu_reg); | |
| 6791 %} | |
| 6792 | |
| 6793 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
| 6794 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6795 ins_cost(140); | |
| 6796 size(4); | |
| 6797 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6798 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6799 ins_pipe(ialu_imm); | |
| 6800 %} | |
| 6801 | |
|
1160
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diff
changeset
|
6802 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
| 0 | 6803 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6804 ins_cost(150); | |
| 6805 size(4); | |
| 6806 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6807 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6808 ins_pipe(ialu_reg); | |
| 6809 %} | |
| 6810 | |
|
1160
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changeset
|
6811 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
| 0 | 6812 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6813 ins_cost(140); | |
| 6814 size(4); | |
| 6815 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6816 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6817 ins_pipe(ialu_imm); | |
| 6818 %} | |
| 6819 | |
| 6820 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
| 6821 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6822 ins_cost(150); | |
| 6823 size(4); | |
| 6824 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6825 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6826 ins_pipe(ialu_reg); | |
| 6827 %} | |
| 6828 | |
| 6829 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
| 6830 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6831 ins_cost(140); | |
| 6832 size(4); | |
| 6833 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6834 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6835 ins_pipe(ialu_imm); | |
| 6836 %} | |
| 6837 | |
|
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|
6838 // Conditional move for RegN. Only cmov(reg,reg). |
|
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|
6839 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
|
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|
6840 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
|
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|
6841 ins_cost(150); |
|
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|
6842 format %{ "MOV$cmp $pcc,$src,$dst" %} |
|
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|
6843 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
|
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changeset
|
6844 ins_pipe(ialu_reg); |
|
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|
6845 %} |
|
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|
6846 |
|
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changeset
|
6847 // This instruction also works with CmpN so we don't need cmovNN_reg. |
|
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|
6848 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
|
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changeset
|
6849 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
|
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changeset
|
6850 ins_cost(150); |
|
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parents:
163
diff
changeset
|
6851 size(4); |
|
c436414a719e
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parents:
163
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changeset
|
6852 format %{ "MOV$cmp $icc,$src,$dst" %} |
|
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163
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changeset
|
6853 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
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163
diff
changeset
|
6854 ins_pipe(ialu_reg); |
|
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parents:
163
diff
changeset
|
6855 %} |
|
c436414a719e
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parents:
163
diff
changeset
|
6856 |
|
1160
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changeset
|
6857 // This instruction also works with CmpN so we don't need cmovNN_reg. |
|
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changeset
|
6858 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ |
|
f24201449cac
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changeset
|
6859 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6860 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6861 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6862 format %{ "MOV$cmp $icc,$src,$dst" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6863 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6864 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6865 %} |
|
f24201449cac
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diff
changeset
|
6866 |
|
164
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parents:
163
diff
changeset
|
6867 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
|
c436414a719e
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163
diff
changeset
|
6868 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
|
c436414a719e
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parents:
163
diff
changeset
|
6869 ins_cost(150); |
|
c436414a719e
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parents:
163
diff
changeset
|
6870 size(4); |
|
c436414a719e
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parents:
163
diff
changeset
|
6871 format %{ "MOV$cmp $fcc,$src,$dst" %} |
|
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163
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changeset
|
6872 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
|
c436414a719e
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163
diff
changeset
|
6873 ins_pipe(ialu_reg); |
|
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163
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changeset
|
6874 %} |
|
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163
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changeset
|
6875 |
| 0 | 6876 // Conditional move |
| 6877 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
| 6878 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6879 ins_cost(150); | |
| 6880 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6881 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6882 ins_pipe(ialu_reg); | |
| 6883 %} | |
| 6884 | |
| 6885 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
| 6886 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6887 ins_cost(140); | |
| 6888 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6889 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6890 ins_pipe(ialu_imm); | |
| 6891 %} | |
| 6892 | |
|
164
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163
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changeset
|
6893 // This instruction also works with CmpN so we don't need cmovPN_reg. |
| 0 | 6894 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
| 6895 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6896 ins_cost(150); | |
| 6897 | |
| 6898 size(4); | |
| 6899 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6900 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6901 ins_pipe(ialu_reg); | |
| 6902 %} | |
| 6903 | |
|
1160
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diff
changeset
|
6904 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6905 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6906 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6907 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6908 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6909 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6910 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6911 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
6912 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6913 |
| 0 | 6914 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ |
| 6915 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6916 ins_cost(140); | |
| 6917 | |
| 6918 size(4); | |
| 6919 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6920 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6921 ins_pipe(ialu_imm); | |
| 6922 %} | |
| 6923 | |
|
1160
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changeset
|
6924 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6925 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6926 ins_cost(140); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6927 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6928 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6929 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
f24201449cac
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1137
diff
changeset
|
6930 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6931 ins_pipe(ialu_imm); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6932 %} |
|
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diff
changeset
|
6933 |
| 0 | 6934 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ |
| 6935 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6936 ins_cost(150); | |
| 6937 size(4); | |
| 6938 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6939 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6940 ins_pipe(ialu_imm); | |
| 6941 %} | |
| 6942 | |
| 6943 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
| 6944 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6945 ins_cost(140); | |
| 6946 size(4); | |
| 6947 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6948 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6949 ins_pipe(ialu_imm); | |
| 6950 %} | |
| 6951 | |
| 6952 // Conditional move | |
| 6953 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
| 6954 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
| 6955 ins_cost(150); | |
| 6956 opcode(0x101); | |
| 6957 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 6958 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6959 ins_pipe(int_conditional_float_move); | |
| 6960 %} | |
| 6961 | |
| 6962 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
| 6963 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
| 6964 ins_cost(150); | |
| 6965 | |
| 6966 size(4); | |
| 6967 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
| 6968 opcode(0x101); | |
| 6969 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6970 ins_pipe(int_conditional_float_move); | |
| 6971 %} | |
| 6972 | |
|
1160
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changeset
|
6973 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ |
|
f24201449cac
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changeset
|
6974 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
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diff
changeset
|
6975 ins_cost(150); |
|
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diff
changeset
|
6976 |
|
f24201449cac
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diff
changeset
|
6977 size(4); |
|
f24201449cac
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diff
changeset
|
6978 format %{ "FMOVS$cmp $icc,$src,$dst" %} |
|
f24201449cac
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diff
changeset
|
6979 opcode(0x101); |
|
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changeset
|
6980 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
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changeset
|
6981 ins_pipe(int_conditional_float_move); |
|
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diff
changeset
|
6982 %} |
|
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diff
changeset
|
6983 |
| 0 | 6984 // Conditional move, |
| 6985 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
| 6986 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
| 6987 ins_cost(150); | |
| 6988 size(4); | |
| 6989 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
| 6990 opcode(0x1); | |
| 6991 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 6992 ins_pipe(int_conditional_double_move); | |
| 6993 %} | |
| 6994 | |
| 6995 // Conditional move | |
| 6996 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
| 6997 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
| 6998 ins_cost(150); | |
| 6999 size(4); | |
| 7000 opcode(0x102); | |
| 7001 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 7002 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7003 ins_pipe(int_conditional_double_move); | |
| 7004 %} | |
| 7005 | |
| 7006 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
| 7007 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
| 7008 ins_cost(150); | |
| 7009 | |
| 7010 size(4); | |
| 7011 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
| 7012 opcode(0x102); | |
| 7013 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 7014 ins_pipe(int_conditional_double_move); | |
| 7015 %} | |
| 7016 | |
|
1160
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diff
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|
7017 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ |
|
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|
7018 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
|
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|
7019 ins_cost(150); |
|
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diff
changeset
|
7020 |
|
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diff
changeset
|
7021 size(4); |
|
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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|
7022 format %{ "FMOVD$cmp $icc,$src,$dst" %} |
|
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changeset
|
7023 opcode(0x102); |
|
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
7024 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
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changeset
|
7025 ins_pipe(int_conditional_double_move); |
|
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changeset
|
7026 %} |
|
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|
7027 |
| 0 | 7028 // Conditional move, |
| 7029 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
| 7030 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
| 7031 ins_cost(150); | |
| 7032 size(4); | |
| 7033 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
| 7034 opcode(0x2); | |
| 7035 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 7036 ins_pipe(int_conditional_double_move); | |
| 7037 %} | |
| 7038 | |
| 7039 // Conditional move | |
| 7040 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
| 7041 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 7042 ins_cost(150); | |
| 7043 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 7044 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7045 ins_pipe(ialu_reg); | |
| 7046 %} | |
| 7047 | |
| 7048 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
| 7049 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 7050 ins_cost(140); | |
| 7051 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 7052 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7053 ins_pipe(ialu_imm); | |
| 7054 %} | |
| 7055 | |
| 7056 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
| 7057 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
| 7058 ins_cost(150); | |
| 7059 | |
| 7060 size(4); | |
| 7061 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
| 7062 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 7063 ins_pipe(ialu_reg); | |
| 7064 %} | |
| 7065 | |
| 7066 | |
|
1160
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changeset
|
7067 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ |
|
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|
7068 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
|
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changeset
|
7069 ins_cost(150); |
|
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diff
changeset
|
7070 |
|
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diff
changeset
|
7071 size(4); |
|
f24201449cac
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changeset
|
7072 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
|
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|
7073 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
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changeset
|
7074 ins_pipe(ialu_reg); |
|
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changeset
|
7075 %} |
|
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changeset
|
7076 |
|
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|
7077 |
| 0 | 7078 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ |
| 7079 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
| 7080 ins_cost(150); | |
| 7081 | |
| 7082 size(4); | |
| 7083 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
| 7084 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 7085 ins_pipe(ialu_reg); | |
| 7086 %} | |
| 7087 | |
| 7088 | |
| 7089 | |
| 7090 //----------OS and Locking Instructions---------------------------------------- | |
| 7091 | |
| 7092 // This name is KNOWN by the ADLC and cannot be changed. | |
| 7093 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 7094 // for this guy. | |
| 7095 instruct tlsLoadP(g2RegP dst) %{ | |
| 7096 match(Set dst (ThreadLocal)); | |
| 7097 | |
| 7098 size(0); | |
| 7099 ins_cost(0); | |
| 7100 format %{ "# TLS is in G2" %} | |
| 7101 ins_encode( /*empty encoding*/ ); | |
| 7102 ins_pipe(ialu_none); | |
| 7103 %} | |
| 7104 | |
| 7105 instruct checkCastPP( iRegP dst ) %{ | |
| 7106 match(Set dst (CheckCastPP dst)); | |
| 7107 | |
| 7108 size(0); | |
| 7109 format %{ "# checkcastPP of $dst" %} | |
| 7110 ins_encode( /*empty encoding*/ ); | |
| 7111 ins_pipe(empty); | |
| 7112 %} | |
| 7113 | |
| 7114 | |
| 7115 instruct castPP( iRegP dst ) %{ | |
| 7116 match(Set dst (CastPP dst)); | |
| 7117 format %{ "# castPP of $dst" %} | |
| 7118 ins_encode( /*empty encoding*/ ); | |
| 7119 ins_pipe(empty); | |
| 7120 %} | |
| 7121 | |
| 7122 instruct castII( iRegI dst ) %{ | |
| 7123 match(Set dst (CastII dst)); | |
| 7124 format %{ "# castII of $dst" %} | |
| 7125 ins_encode( /*empty encoding*/ ); | |
| 7126 ins_cost(0); | |
| 7127 ins_pipe(empty); | |
| 7128 %} | |
| 7129 | |
| 7130 //----------Arithmetic Instructions-------------------------------------------- | |
| 7131 // Addition Instructions | |
| 7132 // Register Addition | |
| 7133 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7134 match(Set dst (AddI src1 src2)); | |
| 7135 | |
| 7136 size(4); | |
| 7137 format %{ "ADD $src1,$src2,$dst" %} | |
| 7138 ins_encode %{ | |
| 7139 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
| 7140 %} | |
| 7141 ins_pipe(ialu_reg_reg); | |
| 7142 %} | |
| 7143 | |
| 7144 // Immediate Addition | |
| 7145 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7146 match(Set dst (AddI src1 src2)); | |
| 7147 | |
| 7148 size(4); | |
| 7149 format %{ "ADD $src1,$src2,$dst" %} | |
| 7150 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7151 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7152 ins_pipe(ialu_reg_imm); | |
| 7153 %} | |
| 7154 | |
| 7155 // Pointer Register Addition | |
| 7156 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
| 7157 match(Set dst (AddP src1 src2)); | |
| 7158 | |
| 7159 size(4); | |
| 7160 format %{ "ADD $src1,$src2,$dst" %} | |
| 7161 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7162 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7163 ins_pipe(ialu_reg_reg); | |
| 7164 %} | |
| 7165 | |
| 7166 // Pointer Immediate Addition | |
| 7167 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
| 7168 match(Set dst (AddP src1 src2)); | |
| 7169 | |
| 7170 size(4); | |
| 7171 format %{ "ADD $src1,$src2,$dst" %} | |
| 7172 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7173 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7174 ins_pipe(ialu_reg_imm); | |
| 7175 %} | |
| 7176 | |
| 7177 // Long Addition | |
| 7178 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7179 match(Set dst (AddL src1 src2)); | |
| 7180 | |
| 7181 size(4); | |
| 7182 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
| 7183 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7184 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7185 ins_pipe(ialu_reg_reg); | |
| 7186 %} | |
| 7187 | |
| 7188 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7189 match(Set dst (AddL src1 con)); | |
| 7190 | |
| 7191 size(4); | |
| 7192 format %{ "ADD $src1,$con,$dst" %} | |
| 7193 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7194 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7195 ins_pipe(ialu_reg_imm); | |
| 7196 %} | |
| 7197 | |
| 7198 //----------Conditional_store-------------------------------------------------- | |
| 7199 // Conditional-store of the updated heap-top. | |
| 7200 // Used during allocation of the shared heap. | |
| 7201 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
| 7202 | |
| 7203 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
| 7204 instruct loadPLocked(iRegP dst, memory mem) %{ | |
| 7205 match(Set dst (LoadPLocked mem)); | |
| 7206 ins_cost(MEMORY_REF_COST); | |
| 7207 | |
| 7208 #ifndef _LP64 | |
| 7209 size(4); | |
| 7210 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 7211 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
| 7212 #else | |
| 7213 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 7214 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
| 7215 #endif | |
| 7216 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 7217 ins_pipe(iload_mem); | |
| 7218 %} | |
| 7219 | |
| 7220 // LoadL-locked. Same as a regular long load when used with a compare-swap | |
| 7221 instruct loadLLocked(iRegL dst, memory mem) %{ | |
| 7222 match(Set dst (LoadLLocked mem)); | |
| 7223 ins_cost(MEMORY_REF_COST); | |
| 7224 size(4); | |
| 7225 format %{ "LDX $mem,$dst\t! long" %} | |
| 7226 opcode(Assembler::ldx_op3); | |
|
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|
7227 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 7228 ins_pipe(iload_mem); |
| 7229 %} | |
| 7230 | |
| 7231 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
| 7232 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7233 effect( KILL newval ); | |
| 7234 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
| 7235 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
| 7236 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
| 7237 ins_pipe( long_memory_op ); | |
| 7238 %} | |
| 7239 | |
|
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|
7240 // Conditional-store of an int value. |
|
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|
7241 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
|
a1980da045cc
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|
7242 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
|
a1980da045cc
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|
7243 effect( KILL newval ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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changeset
|
7244 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
|
a1980da045cc
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changeset
|
7245 "CMP $oldval,$newval\t\t! See if we made progress" %} |
|
a1980da045cc
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changeset
|
7246 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7247 ins_pipe( long_memory_op ); |
| 7248 %} | |
| 7249 | |
|
420
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|
7250 // Conditional-store of a long value. |
|
a1980da045cc
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changeset
|
7251 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
|
a1980da045cc
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|
7252 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
|
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changeset
|
7253 effect( KILL newval ); |
|
a1980da045cc
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changeset
|
7254 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
|
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|
7255 "CMP $oldval,$newval\t\t! See if we made progress" %} |
|
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|
7256 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7257 ins_pipe( long_memory_op ); |
| 7258 %} | |
| 7259 | |
| 7260 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7261 | |
| 7262 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7263 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 7264 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7265 format %{ | |
| 7266 "MOV $newval,O7\n\t" | |
| 7267 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7268 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7269 "MOV 1,$res\n\t" | |
| 7270 "MOVne xcc,R_G0,$res" | |
| 7271 %} | |
| 7272 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
| 7273 enc_lflags_ne_to_boolean(res) ); | |
| 7274 ins_pipe( long_memory_op ); | |
| 7275 %} | |
| 7276 | |
| 7277 | |
| 7278 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7279 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 7280 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7281 format %{ | |
| 7282 "MOV $newval,O7\n\t" | |
| 7283 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7284 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7285 "MOV 1,$res\n\t" | |
| 7286 "MOVne icc,R_G0,$res" | |
| 7287 %} | |
| 7288 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
| 7289 enc_iflags_ne_to_boolean(res) ); | |
| 7290 ins_pipe( long_memory_op ); | |
| 7291 %} | |
| 7292 | |
| 7293 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7294 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 7295 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7296 format %{ | |
| 7297 "MOV $newval,O7\n\t" | |
|
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7298 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
| 0 | 7299 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
| 7300 "MOV 1,$res\n\t" | |
| 7301 "MOVne xcc,R_G0,$res" | |
| 7302 %} | |
|
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|
7303 #ifdef _LP64 |
| 0 | 7304 ins_encode( enc_casx(mem_ptr, oldval, newval), |
| 7305 enc_lflags_ne_to_boolean(res) ); | |
| 7306 #else | |
|
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|
7307 ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
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|
7308 enc_iflags_ne_to_boolean(res) ); |
|
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|
7309 #endif |
|
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|
7310 ins_pipe( long_memory_op ); |
|
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|
7311 %} |
|
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|
7312 |
|
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|
7313 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
|
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7314 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
|
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|
7315 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
| 0 | 7316 format %{ |
| 7317 "MOV $newval,O7\n\t" | |
| 7318 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7319 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7320 "MOV 1,$res\n\t" | |
| 7321 "MOVne icc,R_G0,$res" | |
| 7322 %} | |
|
181
823298b11afc
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165
diff
changeset
|
7323 ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
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parents:
165
diff
changeset
|
7324 enc_iflags_ne_to_boolean(res) ); |
| 0 | 7325 ins_pipe( long_memory_op ); |
| 7326 %} | |
| 7327 | |
| 7328 //--------------------- | |
| 7329 // Subtraction Instructions | |
| 7330 // Register Subtraction | |
| 7331 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7332 match(Set dst (SubI src1 src2)); | |
| 7333 | |
| 7334 size(4); | |
| 7335 format %{ "SUB $src1,$src2,$dst" %} | |
| 7336 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7337 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7338 ins_pipe(ialu_reg_reg); | |
| 7339 %} | |
| 7340 | |
| 7341 // Immediate Subtraction | |
| 7342 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7343 match(Set dst (SubI src1 src2)); | |
| 7344 | |
| 7345 size(4); | |
| 7346 format %{ "SUB $src1,$src2,$dst" %} | |
| 7347 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7348 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7349 ins_pipe(ialu_reg_imm); | |
| 7350 %} | |
| 7351 | |
| 7352 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 7353 match(Set dst (SubI zero src2)); | |
| 7354 | |
| 7355 size(4); | |
| 7356 format %{ "NEG $src2,$dst" %} | |
| 7357 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7358 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7359 ins_pipe(ialu_zero_reg); | |
| 7360 %} | |
| 7361 | |
| 7362 // Long subtraction | |
| 7363 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7364 match(Set dst (SubL src1 src2)); | |
| 7365 | |
| 7366 size(4); | |
| 7367 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7368 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7369 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7370 ins_pipe(ialu_reg_reg); | |
| 7371 %} | |
| 7372 | |
| 7373 // Immediate Subtraction | |
| 7374 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7375 match(Set dst (SubL src1 con)); | |
| 7376 | |
| 7377 size(4); | |
| 7378 format %{ "SUB $src1,$con,$dst\t! long" %} | |
| 7379 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7380 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7381 ins_pipe(ialu_reg_imm); | |
| 7382 %} | |
| 7383 | |
| 7384 // Long negation | |
| 7385 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
| 7386 match(Set dst (SubL zero src2)); | |
| 7387 | |
| 7388 size(4); | |
| 7389 format %{ "NEG $src2,$dst\t! long" %} | |
| 7390 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7391 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7392 ins_pipe(ialu_zero_reg); | |
| 7393 %} | |
| 7394 | |
| 7395 // Multiplication Instructions | |
| 7396 // Integer Multiplication | |
| 7397 // Register Multiplication | |
| 7398 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7399 match(Set dst (MulI src1 src2)); | |
| 7400 | |
| 7401 size(4); | |
| 7402 format %{ "MULX $src1,$src2,$dst" %} | |
| 7403 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7404 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7405 ins_pipe(imul_reg_reg); | |
| 7406 %} | |
| 7407 | |
| 7408 // Immediate Multiplication | |
| 7409 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7410 match(Set dst (MulI src1 src2)); | |
| 7411 | |
| 7412 size(4); | |
| 7413 format %{ "MULX $src1,$src2,$dst" %} | |
| 7414 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7415 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7416 ins_pipe(imul_reg_imm); | |
| 7417 %} | |
| 7418 | |
| 7419 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7420 match(Set dst (MulL src1 src2)); | |
| 7421 ins_cost(DEFAULT_COST * 5); | |
| 7422 size(4); | |
| 7423 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7424 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7425 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7426 ins_pipe(mulL_reg_reg); | |
| 7427 %} | |
| 7428 | |
| 7429 // Immediate Multiplication | |
| 7430 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7431 match(Set dst (MulL src1 src2)); | |
| 7432 ins_cost(DEFAULT_COST * 5); | |
| 7433 size(4); | |
| 7434 format %{ "MULX $src1,$src2,$dst" %} | |
| 7435 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7436 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7437 ins_pipe(mulL_reg_imm); | |
| 7438 %} | |
| 7439 | |
| 7440 // Integer Division | |
| 7441 // Register Division | |
| 7442 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 7443 match(Set dst (DivI src1 src2)); | |
| 7444 ins_cost((2+71)*DEFAULT_COST); | |
| 7445 | |
| 7446 format %{ "SRA $src2,0,$src2\n\t" | |
| 7447 "SRA $src1,0,$src1\n\t" | |
| 7448 "SDIVX $src1,$src2,$dst" %} | |
| 7449 ins_encode( idiv_reg( src1, src2, dst ) ); | |
| 7450 ins_pipe(sdiv_reg_reg); | |
| 7451 %} | |
| 7452 | |
| 7453 // Immediate Division | |
| 7454 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
| 7455 match(Set dst (DivI src1 src2)); | |
| 7456 ins_cost((2+71)*DEFAULT_COST); | |
| 7457 | |
| 7458 format %{ "SRA $src1,0,$src1\n\t" | |
| 7459 "SDIVX $src1,$src2,$dst" %} | |
| 7460 ins_encode( idiv_imm( src1, src2, dst ) ); | |
| 7461 ins_pipe(sdiv_reg_imm); | |
| 7462 %} | |
| 7463 | |
| 7464 //----------Div-By-10-Expansion------------------------------------------------ | |
| 7465 // Extract hi bits of a 32x32->64 bit multiply. | |
| 7466 // Expand rule only, not matched | |
| 7467 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
| 7468 effect( DEF dst, USE src1, USE src2 ); | |
| 7469 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
| 7470 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
| 7471 ins_encode( enc_mul_hi(dst,src1,src2)); | |
| 7472 ins_pipe(sdiv_reg_reg); | |
| 7473 %} | |
| 7474 | |
| 605 | 7475 // Magic constant, reciprocal of 10 |
| 0 | 7476 instruct loadConI_x66666667(iRegIsafe dst) %{ |
| 7477 effect( DEF dst ); | |
| 7478 | |
| 7479 size(8); | |
| 7480 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
| 7481 ins_encode( Set32(0x66666667, dst) ); | |
| 7482 ins_pipe(ialu_hi_lo_reg); | |
| 7483 %} | |
| 7484 | |
| 605 | 7485 // Register Shift Right Arithmetic Long by 32-63 |
| 0 | 7486 instruct sra_31( iRegI dst, iRegI src ) %{ |
| 7487 effect( DEF dst, USE src ); | |
| 7488 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
| 7489 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
| 7490 ins_pipe(ialu_reg_reg); | |
| 7491 %} | |
| 7492 | |
| 7493 // Arithmetic Shift Right by 8-bit immediate | |
| 7494 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
| 7495 effect( DEF dst, USE src ); | |
| 7496 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
| 7497 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7498 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
| 7499 ins_pipe(ialu_reg_imm); | |
| 7500 %} | |
| 7501 | |
| 7502 // Integer DIV with 10 | |
| 7503 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
| 7504 match(Set dst (DivI src div)); | |
| 7505 ins_cost((6+6)*DEFAULT_COST); | |
| 7506 expand %{ | |
| 7507 iRegIsafe tmp1; // Killed temps; | |
| 7508 iRegIsafe tmp2; // Killed temps; | |
| 7509 iRegI tmp3; // Killed temps; | |
| 7510 iRegI tmp4; // Killed temps; | |
| 7511 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
| 7512 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
| 7513 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
| 7514 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
| 7515 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
| 7516 %} | |
| 7517 %} | |
| 7518 | |
| 7519 // Register Long Division | |
| 7520 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7521 match(Set dst (DivL src1 src2)); | |
| 7522 ins_cost(DEFAULT_COST*71); | |
| 7523 size(4); | |
| 7524 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7525 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7526 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7527 ins_pipe(divL_reg_reg); | |
| 7528 %} | |
| 7529 | |
| 7530 // Register Long Division | |
| 7531 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7532 match(Set dst (DivL src1 src2)); | |
| 7533 ins_cost(DEFAULT_COST*71); | |
| 7534 size(4); | |
| 7535 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7536 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7537 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7538 ins_pipe(divL_reg_imm); | |
| 7539 %} | |
| 7540 | |
| 7541 // Integer Remainder | |
| 7542 // Register Remainder | |
| 7543 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7544 match(Set dst (ModI src1 src2)); | |
| 7545 effect( KILL ccr, KILL temp); | |
| 7546 | |
| 7547 format %{ "SREM $src1,$src2,$dst" %} | |
| 7548 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
| 7549 ins_pipe(sdiv_reg_reg); | |
| 7550 %} | |
| 7551 | |
| 7552 // Immediate Remainder | |
| 7553 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7554 match(Set dst (ModI src1 src2)); | |
| 7555 effect( KILL ccr, KILL temp); | |
| 7556 | |
| 7557 format %{ "SREM $src1,$src2,$dst" %} | |
| 7558 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
| 7559 ins_pipe(sdiv_reg_imm); | |
| 7560 %} | |
| 7561 | |
| 7562 // Register Long Remainder | |
| 7563 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7564 effect(DEF dst, USE src1, USE src2); | |
| 7565 size(4); | |
| 7566 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7567 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7568 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7569 ins_pipe(divL_reg_reg); | |
| 7570 %} | |
| 7571 | |
| 7572 // Register Long Division | |
| 7573 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7574 effect(DEF dst, USE src1, USE src2); | |
| 7575 size(4); | |
| 7576 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7577 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7578 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7579 ins_pipe(divL_reg_imm); | |
| 7580 %} | |
| 7581 | |
| 7582 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7583 effect(DEF dst, USE src1, USE src2); | |
| 7584 size(4); | |
| 7585 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7586 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7587 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7588 ins_pipe(mulL_reg_reg); | |
| 7589 %} | |
| 7590 | |
| 7591 // Immediate Multiplication | |
| 7592 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7593 effect(DEF dst, USE src1, USE src2); | |
| 7594 size(4); | |
| 7595 format %{ "MULX $src1,$src2,$dst" %} | |
| 7596 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7597 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7598 ins_pipe(mulL_reg_imm); | |
| 7599 %} | |
| 7600 | |
| 7601 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7602 effect(DEF dst, USE src1, USE src2); | |
| 7603 size(4); | |
| 7604 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7605 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7606 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7607 ins_pipe(ialu_reg_reg); | |
| 7608 %} | |
| 7609 | |
| 7610 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7611 effect(DEF dst, USE src1, USE src2); | |
| 7612 size(4); | |
| 7613 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7614 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7615 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7616 ins_pipe(ialu_reg_reg); | |
| 7617 %} | |
| 7618 | |
| 7619 // Register Long Remainder | |
| 7620 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7621 match(Set dst (ModL src1 src2)); | |
| 7622 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7623 expand %{ | |
| 7624 iRegL tmp1; | |
| 7625 iRegL tmp2; | |
| 7626 divL_reg_reg_1(tmp1, src1, src2); | |
| 7627 mulL_reg_reg_1(tmp2, tmp1, src2); | |
| 7628 subL_reg_reg_1(dst, src1, tmp2); | |
| 7629 %} | |
| 7630 %} | |
| 7631 | |
| 7632 // Register Long Remainder | |
| 7633 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7634 match(Set dst (ModL src1 src2)); | |
| 7635 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7636 expand %{ | |
| 7637 iRegL tmp1; | |
| 7638 iRegL tmp2; | |
| 7639 divL_reg_imm13_1(tmp1, src1, src2); | |
| 7640 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
| 7641 subL_reg_reg_2 (dst, src1, tmp2); | |
| 7642 %} | |
| 7643 %} | |
| 7644 | |
| 7645 // Integer Shift Instructions | |
| 7646 // Register Shift Left | |
| 7647 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7648 match(Set dst (LShiftI src1 src2)); | |
| 7649 | |
| 7650 size(4); | |
| 7651 format %{ "SLL $src1,$src2,$dst" %} | |
| 7652 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7653 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7654 ins_pipe(ialu_reg_reg); | |
| 7655 %} | |
| 7656 | |
| 7657 // Register Shift Left Immediate | |
| 7658 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7659 match(Set dst (LShiftI src1 src2)); | |
| 7660 | |
| 7661 size(4); | |
| 7662 format %{ "SLL $src1,$src2,$dst" %} | |
| 7663 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7664 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7665 ins_pipe(ialu_reg_imm); | |
| 7666 %} | |
| 7667 | |
| 7668 // Register Shift Left | |
| 7669 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7670 match(Set dst (LShiftL src1 src2)); | |
| 7671 | |
| 7672 size(4); | |
| 7673 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7674 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7675 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7676 ins_pipe(ialu_reg_reg); | |
| 7677 %} | |
| 7678 | |
| 7679 // Register Shift Left Immediate | |
| 7680 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7681 match(Set dst (LShiftL src1 src2)); | |
| 7682 | |
| 7683 size(4); | |
| 7684 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7685 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7686 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7687 ins_pipe(ialu_reg_imm); | |
| 7688 %} | |
| 7689 | |
| 7690 // Register Arithmetic Shift Right | |
| 7691 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7692 match(Set dst (RShiftI src1 src2)); | |
| 7693 size(4); | |
| 7694 format %{ "SRA $src1,$src2,$dst" %} | |
| 7695 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7696 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7697 ins_pipe(ialu_reg_reg); | |
| 7698 %} | |
| 7699 | |
| 7700 // Register Arithmetic Shift Right Immediate | |
| 7701 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7702 match(Set dst (RShiftI src1 src2)); | |
| 7703 | |
| 7704 size(4); | |
| 7705 format %{ "SRA $src1,$src2,$dst" %} | |
| 7706 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7707 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7708 ins_pipe(ialu_reg_imm); | |
| 7709 %} | |
| 7710 | |
| 7711 // Register Shift Right Arithmatic Long | |
| 7712 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7713 match(Set dst (RShiftL src1 src2)); | |
| 7714 | |
| 7715 size(4); | |
| 7716 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7717 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7718 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7719 ins_pipe(ialu_reg_reg); | |
| 7720 %} | |
| 7721 | |
| 7722 // Register Shift Left Immediate | |
| 7723 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7724 match(Set dst (RShiftL src1 src2)); | |
| 7725 | |
| 7726 size(4); | |
| 7727 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7728 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7729 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7730 ins_pipe(ialu_reg_imm); | |
| 7731 %} | |
| 7732 | |
| 7733 // Register Shift Right | |
| 7734 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7735 match(Set dst (URShiftI src1 src2)); | |
| 7736 | |
| 7737 size(4); | |
| 7738 format %{ "SRL $src1,$src2,$dst" %} | |
| 7739 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7740 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7741 ins_pipe(ialu_reg_reg); | |
| 7742 %} | |
| 7743 | |
| 7744 // Register Shift Right Immediate | |
| 7745 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7746 match(Set dst (URShiftI src1 src2)); | |
| 7747 | |
| 7748 size(4); | |
| 7749 format %{ "SRL $src1,$src2,$dst" %} | |
| 7750 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7751 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7752 ins_pipe(ialu_reg_imm); | |
| 7753 %} | |
| 7754 | |
| 7755 // Register Shift Right | |
| 7756 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7757 match(Set dst (URShiftL src1 src2)); | |
| 7758 | |
| 7759 size(4); | |
| 7760 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7761 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7762 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7763 ins_pipe(ialu_reg_reg); | |
| 7764 %} | |
| 7765 | |
| 7766 // Register Shift Right Immediate | |
| 7767 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7768 match(Set dst (URShiftL src1 src2)); | |
| 7769 | |
| 7770 size(4); | |
| 7771 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7772 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7773 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7774 ins_pipe(ialu_reg_imm); | |
| 7775 %} | |
| 7776 | |
| 7777 // Register Shift Right Immediate with a CastP2X | |
| 7778 #ifdef _LP64 | |
| 7779 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
| 7780 match(Set dst (URShiftL (CastP2X src1) src2)); | |
| 7781 size(4); | |
| 7782 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
| 7783 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7784 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7785 ins_pipe(ialu_reg_imm); | |
| 7786 %} | |
| 7787 #else | |
| 7788 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
| 7789 match(Set dst (URShiftI (CastP2X src1) src2)); | |
| 7790 size(4); | |
| 7791 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
| 7792 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7793 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7794 ins_pipe(ialu_reg_imm); | |
| 7795 %} | |
| 7796 #endif | |
| 7797 | |
| 7798 | |
| 7799 //----------Floating Point Arithmetic Instructions----------------------------- | |
| 7800 | |
| 7801 // Add float single precision | |
| 7802 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7803 match(Set dst (AddF src1 src2)); | |
| 7804 | |
| 7805 size(4); | |
| 7806 format %{ "FADDS $src1,$src2,$dst" %} | |
| 7807 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
| 7808 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7809 ins_pipe(faddF_reg_reg); | |
| 7810 %} | |
| 7811 | |
| 7812 // Add float double precision | |
| 7813 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7814 match(Set dst (AddD src1 src2)); | |
| 7815 | |
| 7816 size(4); | |
| 7817 format %{ "FADDD $src1,$src2,$dst" %} | |
| 7818 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 7819 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7820 ins_pipe(faddD_reg_reg); | |
| 7821 %} | |
| 7822 | |
| 7823 // Sub float single precision | |
| 7824 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7825 match(Set dst (SubF src1 src2)); | |
| 7826 | |
| 7827 size(4); | |
| 7828 format %{ "FSUBS $src1,$src2,$dst" %} | |
| 7829 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
| 7830 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7831 ins_pipe(faddF_reg_reg); | |
| 7832 %} | |
| 7833 | |
| 7834 // Sub float double precision | |
| 7835 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7836 match(Set dst (SubD src1 src2)); | |
| 7837 | |
| 7838 size(4); | |
| 7839 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 7840 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 7841 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7842 ins_pipe(faddD_reg_reg); | |
| 7843 %} | |
| 7844 | |
| 7845 // Mul float single precision | |
| 7846 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7847 match(Set dst (MulF src1 src2)); | |
| 7848 | |
| 7849 size(4); | |
| 7850 format %{ "FMULS $src1,$src2,$dst" %} | |
| 7851 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
| 7852 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7853 ins_pipe(fmulF_reg_reg); | |
| 7854 %} | |
| 7855 | |
| 7856 // Mul float double precision | |
| 7857 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7858 match(Set dst (MulD src1 src2)); | |
| 7859 | |
| 7860 size(4); | |
| 7861 format %{ "FMULD $src1,$src2,$dst" %} | |
| 7862 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 7863 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7864 ins_pipe(fmulD_reg_reg); | |
| 7865 %} | |
| 7866 | |
| 7867 // Div float single precision | |
| 7868 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7869 match(Set dst (DivF src1 src2)); | |
| 7870 | |
| 7871 size(4); | |
| 7872 format %{ "FDIVS $src1,$src2,$dst" %} | |
| 7873 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
| 7874 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7875 ins_pipe(fdivF_reg_reg); | |
| 7876 %} | |
| 7877 | |
| 7878 // Div float double precision | |
| 7879 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7880 match(Set dst (DivD src1 src2)); | |
| 7881 | |
| 7882 size(4); | |
| 7883 format %{ "FDIVD $src1,$src2,$dst" %} | |
| 7884 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
| 7885 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7886 ins_pipe(fdivD_reg_reg); | |
| 7887 %} | |
| 7888 | |
| 7889 // Absolute float double precision | |
| 7890 instruct absD_reg(regD dst, regD src) %{ | |
| 7891 match(Set dst (AbsD src)); | |
| 7892 | |
| 7893 format %{ "FABSd $src,$dst" %} | |
| 7894 ins_encode(fabsd(dst, src)); | |
| 7895 ins_pipe(faddD_reg); | |
| 7896 %} | |
| 7897 | |
| 7898 // Absolute float single precision | |
| 7899 instruct absF_reg(regF dst, regF src) %{ | |
| 7900 match(Set dst (AbsF src)); | |
| 7901 | |
| 7902 format %{ "FABSs $src,$dst" %} | |
| 7903 ins_encode(fabss(dst, src)); | |
| 7904 ins_pipe(faddF_reg); | |
| 7905 %} | |
| 7906 | |
| 7907 instruct negF_reg(regF dst, regF src) %{ | |
| 7908 match(Set dst (NegF src)); | |
| 7909 | |
| 7910 size(4); | |
| 7911 format %{ "FNEGs $src,$dst" %} | |
| 7912 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
| 7913 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
| 7914 ins_pipe(faddF_reg); | |
| 7915 %} | |
| 7916 | |
| 7917 instruct negD_reg(regD dst, regD src) %{ | |
| 7918 match(Set dst (NegD src)); | |
| 7919 | |
| 7920 format %{ "FNEGd $src,$dst" %} | |
| 7921 ins_encode(fnegd(dst, src)); | |
| 7922 ins_pipe(faddD_reg); | |
| 7923 %} | |
| 7924 | |
| 7925 // Sqrt float double precision | |
| 7926 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
| 7927 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 7928 | |
| 7929 size(4); | |
| 7930 format %{ "FSQRTS $src,$dst" %} | |
| 7931 ins_encode(fsqrts(dst, src)); | |
| 7932 ins_pipe(fdivF_reg_reg); | |
| 7933 %} | |
| 7934 | |
| 7935 // Sqrt float double precision | |
| 7936 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
| 7937 match(Set dst (SqrtD src)); | |
| 7938 | |
| 7939 size(4); | |
| 7940 format %{ "FSQRTD $src,$dst" %} | |
| 7941 ins_encode(fsqrtd(dst, src)); | |
| 7942 ins_pipe(fdivD_reg_reg); | |
| 7943 %} | |
| 7944 | |
| 7945 //----------Logical Instructions----------------------------------------------- | |
| 7946 // And Instructions | |
| 7947 // Register And | |
| 7948 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7949 match(Set dst (AndI src1 src2)); | |
| 7950 | |
| 7951 size(4); | |
| 7952 format %{ "AND $src1,$src2,$dst" %} | |
| 7953 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7954 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7955 ins_pipe(ialu_reg_reg); | |
| 7956 %} | |
| 7957 | |
| 7958 // Immediate And | |
| 7959 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7960 match(Set dst (AndI src1 src2)); | |
| 7961 | |
| 7962 size(4); | |
| 7963 format %{ "AND $src1,$src2,$dst" %} | |
| 7964 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7965 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7966 ins_pipe(ialu_reg_imm); | |
| 7967 %} | |
| 7968 | |
| 7969 // Register And Long | |
| 7970 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7971 match(Set dst (AndL src1 src2)); | |
| 7972 | |
| 7973 ins_cost(DEFAULT_COST); | |
| 7974 size(4); | |
| 7975 format %{ "AND $src1,$src2,$dst\t! long" %} | |
| 7976 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7977 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7978 ins_pipe(ialu_reg_reg); | |
| 7979 %} | |
| 7980 | |
| 7981 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7982 match(Set dst (AndL src1 con)); | |
| 7983 | |
| 7984 ins_cost(DEFAULT_COST); | |
| 7985 size(4); | |
| 7986 format %{ "AND $src1,$con,$dst\t! long" %} | |
| 7987 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7988 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7989 ins_pipe(ialu_reg_imm); | |
| 7990 %} | |
| 7991 | |
| 7992 // Or Instructions | |
| 7993 // Register Or | |
| 7994 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7995 match(Set dst (OrI src1 src2)); | |
| 7996 | |
| 7997 size(4); | |
| 7998 format %{ "OR $src1,$src2,$dst" %} | |
| 7999 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8000 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8001 ins_pipe(ialu_reg_reg); | |
| 8002 %} | |
| 8003 | |
| 8004 // Immediate Or | |
| 8005 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 8006 match(Set dst (OrI src1 src2)); | |
| 8007 | |
| 8008 size(4); | |
| 8009 format %{ "OR $src1,$src2,$dst" %} | |
| 8010 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8011 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 8012 ins_pipe(ialu_reg_imm); | |
| 8013 %} | |
| 8014 | |
| 8015 // Register Or Long | |
| 8016 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 8017 match(Set dst (OrL src1 src2)); | |
| 8018 | |
| 8019 ins_cost(DEFAULT_COST); | |
| 8020 size(4); | |
| 8021 format %{ "OR $src1,$src2,$dst\t! long" %} | |
| 8022 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8023 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8024 ins_pipe(ialu_reg_reg); | |
| 8025 %} | |
| 8026 | |
| 8027 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 8028 match(Set dst (OrL src1 con)); | |
| 8029 ins_cost(DEFAULT_COST*2); | |
| 8030 | |
| 8031 ins_cost(DEFAULT_COST); | |
| 8032 size(4); | |
| 8033 format %{ "OR $src1,$con,$dst\t! long" %} | |
| 8034 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8035 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 8036 ins_pipe(ialu_reg_imm); | |
| 8037 %} | |
| 8038 | |
|
420
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8039 #ifndef _LP64 |
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8040 |
|
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8041 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
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8042 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
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8043 match(Set dst (OrI src1 (CastP2X src2))); |
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8044 |
|
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8045 size(4); |
|
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8046 format %{ "OR $src1,$src2,$dst" %} |
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8047 opcode(Assembler::or_op3, Assembler::arith_op); |
|
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8048 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
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8049 ins_pipe(ialu_reg_reg); |
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8050 %} |
|
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8051 |
|
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8052 #else |
|
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8053 |
|
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8054 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
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8055 match(Set dst (OrL src1 (CastP2X src2))); |
|
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8056 |
|
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8057 ins_cost(DEFAULT_COST); |
|
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8058 size(4); |
|
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8059 format %{ "OR $src1,$src2,$dst\t! long" %} |
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8060 opcode(Assembler::or_op3, Assembler::arith_op); |
|
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8061 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
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8062 ins_pipe(ialu_reg_reg); |
|
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8063 %} |
|
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8064 |
|
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8065 #endif |
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8066 |
| 0 | 8067 // Xor Instructions |
| 8068 // Register Xor | |
| 8069 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 8070 match(Set dst (XorI src1 src2)); | |
| 8071 | |
| 8072 size(4); | |
| 8073 format %{ "XOR $src1,$src2,$dst" %} | |
| 8074 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8075 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8076 ins_pipe(ialu_reg_reg); | |
| 8077 %} | |
| 8078 | |
| 8079 // Immediate Xor | |
| 8080 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 8081 match(Set dst (XorI src1 src2)); | |
| 8082 | |
| 8083 size(4); | |
| 8084 format %{ "XOR $src1,$src2,$dst" %} | |
| 8085 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8086 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 8087 ins_pipe(ialu_reg_imm); | |
| 8088 %} | |
| 8089 | |
| 8090 // Register Xor Long | |
| 8091 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 8092 match(Set dst (XorL src1 src2)); | |
| 8093 | |
| 8094 ins_cost(DEFAULT_COST); | |
| 8095 size(4); | |
| 8096 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
| 8097 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8098 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8099 ins_pipe(ialu_reg_reg); | |
| 8100 %} | |
| 8101 | |
| 8102 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 8103 match(Set dst (XorL src1 con)); | |
| 8104 | |
| 8105 ins_cost(DEFAULT_COST); | |
| 8106 size(4); | |
| 8107 format %{ "XOR $src1,$con,$dst\t! long" %} | |
| 8108 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8109 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 8110 ins_pipe(ialu_reg_imm); | |
| 8111 %} | |
| 8112 | |
| 8113 //----------Convert to Boolean------------------------------------------------- | |
| 8114 // Nice hack for 32-bit tests but doesn't work for | |
| 8115 // 64-bit pointers. | |
| 8116 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
| 8117 match(Set dst (Conv2B src)); | |
| 8118 effect( KILL ccr ); | |
| 8119 ins_cost(DEFAULT_COST*2); | |
| 8120 format %{ "CMP R_G0,$src\n\t" | |
| 8121 "ADDX R_G0,0,$dst" %} | |
| 8122 ins_encode( enc_to_bool( src, dst ) ); | |
| 8123 ins_pipe(ialu_reg_ialu); | |
| 8124 %} | |
| 8125 | |
| 8126 #ifndef _LP64 | |
| 8127 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
| 8128 match(Set dst (Conv2B src)); | |
| 8129 effect( KILL ccr ); | |
| 8130 ins_cost(DEFAULT_COST*2); | |
| 8131 format %{ "CMP R_G0,$src\n\t" | |
| 8132 "ADDX R_G0,0,$dst" %} | |
| 8133 ins_encode( enc_to_bool( src, dst ) ); | |
| 8134 ins_pipe(ialu_reg_ialu); | |
| 8135 %} | |
| 8136 #else | |
| 8137 instruct convP2B( iRegI dst, iRegP src ) %{ | |
| 8138 match(Set dst (Conv2B src)); | |
| 8139 ins_cost(DEFAULT_COST*2); | |
| 8140 format %{ "MOV $src,$dst\n\t" | |
| 8141 "MOVRNZ $src,1,$dst" %} | |
| 8142 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
| 8143 ins_pipe(ialu_clr_and_mover); | |
| 8144 %} | |
| 8145 #endif | |
| 8146 | |
|
2254
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7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
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|
8147 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
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2121
diff
changeset
|
8148 match(Set dst (CmpLTMask src zero)); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
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|
8149 effect(KILL ccr); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8150 size(4); |
|
ab42c7e1cf83
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kvn
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2121
diff
changeset
|
8151 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} |
|
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7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8152 ins_encode %{ |
|
ab42c7e1cf83
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2121
diff
changeset
|
8153 __ sra($src$$Register, 31, $dst$$Register); |
|
ab42c7e1cf83
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|
8154 %} |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
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2121
diff
changeset
|
8155 ins_pipe(ialu_reg_imm); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
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2121
diff
changeset
|
8156 %} |
|
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2121
diff
changeset
|
8157 |
| 0 | 8158 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ |
| 8159 match(Set dst (CmpLTMask p q)); | |
| 8160 effect( KILL ccr ); | |
| 8161 ins_cost(DEFAULT_COST*4); | |
| 8162 format %{ "CMP $p,$q\n\t" | |
| 8163 "MOV #0,$dst\n\t" | |
| 8164 "BLT,a .+8\n\t" | |
| 8165 "MOV #-1,$dst" %} | |
| 8166 ins_encode( enc_ltmask(p,q,dst) ); | |
| 8167 ins_pipe(ialu_reg_reg_ialu); | |
| 8168 %} | |
| 8169 | |
| 8170 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
| 8171 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 8172 effect(KILL ccr, TEMP tmp); | |
| 8173 ins_cost(DEFAULT_COST*3); | |
| 8174 | |
| 8175 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
| 8176 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
|
2254
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7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8177 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} |
| 0 | 8178 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); |
| 8179 ins_pipe( cadd_cmpltmask ); | |
| 8180 %} | |
| 8181 | |
| 3804 | 8182 |
| 8183 //----------------------------------------------------------------- | |
| 8184 // Direct raw moves between float and general registers using VIS3. | |
| 8185 | |
| 8186 // ins_pipe(faddF_reg); | |
| 8187 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ | |
| 8188 predicate(UseVIS >= 3); | |
| 8189 match(Set dst (MoveF2I src)); | |
| 8190 | |
| 8191 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} | |
| 8192 ins_encode %{ | |
| 8193 __ movstouw($src$$FloatRegister, $dst$$Register); | |
| 8194 %} | |
| 8195 ins_pipe(ialu_reg_reg); | |
| 8196 %} | |
| 8197 | |
| 8198 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ | |
| 8199 predicate(UseVIS >= 3); | |
| 8200 match(Set dst (MoveI2F src)); | |
| 8201 | |
| 8202 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} | |
| 8203 ins_encode %{ | |
| 8204 __ movwtos($src$$Register, $dst$$FloatRegister); | |
| 8205 %} | |
| 0 | 8206 ins_pipe(ialu_reg_reg); |
| 8207 %} | |
| 8208 | |
| 3804 | 8209 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ |
| 8210 predicate(UseVIS >= 3); | |
| 8211 match(Set dst (MoveD2L src)); | |
| 8212 | |
| 8213 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} | |
| 8214 ins_encode %{ | |
| 8215 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); | |
| 8216 %} | |
| 0 | 8217 ins_pipe(ialu_reg_reg); |
| 8218 %} | |
| 8219 | |
| 3804 | 8220 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ |
| 8221 predicate(UseVIS >= 3); | |
| 8222 match(Set dst (MoveL2D src)); | |
| 8223 | |
| 8224 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} | |
| 8225 ins_encode %{ | |
| 8226 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); | |
| 8227 %} | |
| 0 | 8228 ins_pipe(ialu_reg_reg); |
| 8229 %} | |
| 8230 | |
| 3804 | 8231 |
| 8232 // Raw moves between float and general registers using stack. | |
| 8233 | |
| 0 | 8234 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ |
| 8235 match(Set dst (MoveF2I src)); | |
| 8236 effect(DEF dst, USE src); | |
| 8237 ins_cost(MEMORY_REF_COST); | |
| 8238 | |
| 8239 size(4); | |
| 8240 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
| 8241 opcode(Assembler::lduw_op3); | |
|
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|
8242 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8243 ins_pipe(iload_mem); |
| 8244 %} | |
| 8245 | |
| 8246 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 8247 match(Set dst (MoveI2F src)); | |
| 8248 effect(DEF dst, USE src); | |
| 8249 ins_cost(MEMORY_REF_COST); | |
| 8250 | |
| 8251 size(4); | |
| 8252 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
| 8253 opcode(Assembler::ldf_op3); | |
|
415
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235
diff
changeset
|
8254 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8255 ins_pipe(floadF_stk); |
| 8256 %} | |
| 8257 | |
| 8258 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
| 8259 match(Set dst (MoveD2L src)); | |
| 8260 effect(DEF dst, USE src); | |
| 8261 ins_cost(MEMORY_REF_COST); | |
| 8262 | |
| 8263 size(4); | |
| 8264 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
| 8265 opcode(Assembler::ldx_op3); | |
|
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235
diff
changeset
|
8266 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8267 ins_pipe(iload_mem); |
| 8268 %} | |
| 8269 | |
| 8270 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 8271 match(Set dst (MoveL2D src)); | |
| 8272 effect(DEF dst, USE src); | |
| 8273 ins_cost(MEMORY_REF_COST); | |
| 8274 | |
| 8275 size(4); | |
| 8276 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
| 8277 opcode(Assembler::lddf_op3); | |
|
415
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235
diff
changeset
|
8278 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8279 ins_pipe(floadD_stk); |
| 8280 %} | |
| 8281 | |
| 8282 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 8283 match(Set dst (MoveF2I src)); | |
| 8284 effect(DEF dst, USE src); | |
| 8285 ins_cost(MEMORY_REF_COST); | |
| 8286 | |
| 8287 size(4); | |
| 3804 | 8288 format %{ "STF $src,$dst\t! MoveF2I" %} |
| 0 | 8289 opcode(Assembler::stf_op3); |
|
415
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235
diff
changeset
|
8290 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8291 ins_pipe(fstoreF_stk_reg); |
| 8292 %} | |
| 8293 | |
| 8294 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
| 8295 match(Set dst (MoveI2F src)); | |
| 8296 effect(DEF dst, USE src); | |
| 8297 ins_cost(MEMORY_REF_COST); | |
| 8298 | |
| 8299 size(4); | |
| 3804 | 8300 format %{ "STW $src,$dst\t! MoveI2F" %} |
| 0 | 8301 opcode(Assembler::stw_op3); |
|
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|
8302 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8303 ins_pipe(istore_mem_reg); |
| 8304 %} | |
| 8305 | |
| 8306 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 8307 match(Set dst (MoveD2L src)); | |
| 8308 effect(DEF dst, USE src); | |
| 8309 ins_cost(MEMORY_REF_COST); | |
| 8310 | |
| 8311 size(4); | |
| 3804 | 8312 format %{ "STDF $src,$dst\t! MoveD2L" %} |
| 0 | 8313 opcode(Assembler::stdf_op3); |
|
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235
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|
8314 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8315 ins_pipe(fstoreD_stk_reg); |
| 8316 %} | |
| 8317 | |
| 8318 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
| 8319 match(Set dst (MoveL2D src)); | |
| 8320 effect(DEF dst, USE src); | |
| 8321 ins_cost(MEMORY_REF_COST); | |
| 8322 | |
| 8323 size(4); | |
| 3804 | 8324 format %{ "STX $src,$dst\t! MoveL2D" %} |
| 0 | 8325 opcode(Assembler::stx_op3); |
|
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235
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|
8326 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8327 ins_pipe(istore_mem_reg); |
| 8328 %} | |
| 8329 | |
| 8330 | |
| 3804 | 8331 //----------Arithmetic Conversion Instructions--------------------------------- |
| 8332 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 8333 | |
| 8334 instruct convD2F_reg(regF dst, regD src) %{ | |
| 8335 match(Set dst (ConvD2F src)); | |
| 8336 size(4); | |
| 8337 format %{ "FDTOS $src,$dst" %} | |
| 8338 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
| 8339 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
| 8340 ins_pipe(fcvtD2F); | |
| 8341 %} | |
| 8342 | |
| 8343 | |
| 8344 // Convert a double to an int in a float register. | |
| 8345 // If the double is a NAN, stuff a zero in instead. | |
| 8346 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
| 8347 effect(DEF dst, USE src, KILL fcc0); | |
| 8348 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8349 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8350 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8351 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8352 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8353 "skip:" %} | |
| 8354 ins_encode(form_d2i_helper(src,dst)); | |
| 8355 ins_pipe(fcvtD2I); | |
| 8356 %} | |
| 8357 | |
| 8358 instruct convD2I_stk(stackSlotI dst, regD src) %{ | |
| 8359 match(Set dst (ConvD2I src)); | |
| 8360 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8361 expand %{ | |
| 8362 regF tmp; | |
| 8363 convD2I_helper(tmp, src); | |
| 8364 regF_to_stkI(dst, tmp); | |
| 8365 %} | |
| 8366 %} | |
| 8367 | |
| 8368 instruct convD2I_reg(iRegI dst, regD src) %{ | |
| 8369 predicate(UseVIS >= 3); | |
| 8370 match(Set dst (ConvD2I src)); | |
| 8371 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8372 expand %{ | |
| 8373 regF tmp; | |
| 8374 convD2I_helper(tmp, src); | |
| 8375 MoveF2I_reg_reg(dst, tmp); | |
| 8376 %} | |
| 8377 %} | |
| 8378 | |
| 8379 | |
| 8380 // Convert a double to a long in a double register. | |
| 8381 // If the double is a NAN, stuff a zero in instead. | |
| 8382 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
| 8383 effect(DEF dst, USE src, KILL fcc0); | |
| 8384 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8385 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8386 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8387 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8388 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8389 "skip:" %} | |
| 8390 ins_encode(form_d2l_helper(src,dst)); | |
| 8391 ins_pipe(fcvtD2L); | |
| 8392 %} | |
| 8393 | |
| 8394 instruct convD2L_stk(stackSlotL dst, regD src) %{ | |
| 8395 match(Set dst (ConvD2L src)); | |
| 8396 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8397 expand %{ | |
| 8398 regD tmp; | |
| 8399 convD2L_helper(tmp, src); | |
| 8400 regD_to_stkL(dst, tmp); | |
| 8401 %} | |
| 8402 %} | |
| 8403 | |
| 8404 instruct convD2L_reg(iRegL dst, regD src) %{ | |
| 8405 predicate(UseVIS >= 3); | |
| 8406 match(Set dst (ConvD2L src)); | |
| 8407 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8408 expand %{ | |
| 8409 regD tmp; | |
| 8410 convD2L_helper(tmp, src); | |
| 8411 MoveD2L_reg_reg(dst, tmp); | |
| 8412 %} | |
| 8413 %} | |
| 8414 | |
| 8415 | |
| 8416 instruct convF2D_reg(regD dst, regF src) %{ | |
| 8417 match(Set dst (ConvF2D src)); | |
| 8418 format %{ "FSTOD $src,$dst" %} | |
| 8419 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
| 8420 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
| 8421 ins_pipe(fcvtF2D); | |
| 8422 %} | |
| 8423 | |
| 8424 | |
| 8425 // Convert a float to an int in a float register. | |
| 8426 // If the float is a NAN, stuff a zero in instead. | |
| 8427 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
| 8428 effect(DEF dst, USE src, KILL fcc0); | |
| 8429 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8430 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8431 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8432 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8433 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8434 "skip:" %} | |
| 8435 ins_encode(form_f2i_helper(src,dst)); | |
| 8436 ins_pipe(fcvtF2I); | |
| 8437 %} | |
| 8438 | |
| 8439 instruct convF2I_stk(stackSlotI dst, regF src) %{ | |
| 8440 match(Set dst (ConvF2I src)); | |
| 8441 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8442 expand %{ | |
| 8443 regF tmp; | |
| 8444 convF2I_helper(tmp, src); | |
| 8445 regF_to_stkI(dst, tmp); | |
| 8446 %} | |
| 8447 %} | |
| 8448 | |
| 8449 instruct convF2I_reg(iRegI dst, regF src) %{ | |
| 8450 predicate(UseVIS >= 3); | |
| 8451 match(Set dst (ConvF2I src)); | |
| 8452 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8453 expand %{ | |
| 8454 regF tmp; | |
| 8455 convF2I_helper(tmp, src); | |
| 8456 MoveF2I_reg_reg(dst, tmp); | |
| 8457 %} | |
| 8458 %} | |
| 8459 | |
| 8460 | |
| 8461 // Convert a float to a long in a float register. | |
| 8462 // If the float is a NAN, stuff a zero in instead. | |
| 8463 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
| 8464 effect(DEF dst, USE src, KILL fcc0); | |
| 8465 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8466 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8467 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8468 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8469 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8470 "skip:" %} | |
| 8471 ins_encode(form_f2l_helper(src,dst)); | |
| 8472 ins_pipe(fcvtF2L); | |
| 8473 %} | |
| 8474 | |
| 8475 instruct convF2L_stk(stackSlotL dst, regF src) %{ | |
| 8476 match(Set dst (ConvF2L src)); | |
| 8477 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8478 expand %{ | |
| 8479 regD tmp; | |
| 8480 convF2L_helper(tmp, src); | |
| 8481 regD_to_stkL(dst, tmp); | |
| 8482 %} | |
| 8483 %} | |
| 8484 | |
| 8485 instruct convF2L_reg(iRegL dst, regF src) %{ | |
| 8486 predicate(UseVIS >= 3); | |
| 8487 match(Set dst (ConvF2L src)); | |
| 8488 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8489 expand %{ | |
| 8490 regD tmp; | |
| 8491 convF2L_helper(tmp, src); | |
| 8492 MoveD2L_reg_reg(dst, tmp); | |
| 8493 %} | |
| 8494 %} | |
| 8495 | |
| 8496 | |
| 8497 instruct convI2D_helper(regD dst, regF tmp) %{ | |
| 8498 effect(USE tmp, DEF dst); | |
| 8499 format %{ "FITOD $tmp,$dst" %} | |
| 8500 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8501 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
| 8502 ins_pipe(fcvtI2D); | |
| 8503 %} | |
| 8504 | |
| 8505 instruct convI2D_stk(stackSlotI src, regD dst) %{ | |
| 8506 match(Set dst (ConvI2D src)); | |
| 8507 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8508 expand %{ | |
| 8509 regF tmp; | |
| 8510 stkI_to_regF(tmp, src); | |
| 8511 convI2D_helper(dst, tmp); | |
| 8512 %} | |
| 8513 %} | |
| 8514 | |
| 8515 instruct convI2D_reg(regD_low dst, iRegI src) %{ | |
| 8516 predicate(UseVIS >= 3); | |
| 8517 match(Set dst (ConvI2D src)); | |
| 8518 expand %{ | |
| 8519 regF tmp; | |
| 8520 MoveI2F_reg_reg(tmp, src); | |
| 8521 convI2D_helper(dst, tmp); | |
| 8522 %} | |
| 8523 %} | |
| 8524 | |
| 8525 instruct convI2D_mem(regD_low dst, memory mem) %{ | |
| 8526 match(Set dst (ConvI2D (LoadI mem))); | |
| 8527 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8528 size(8); | |
| 8529 format %{ "LDF $mem,$dst\n\t" | |
| 8530 "FITOD $dst,$dst" %} | |
| 8531 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
| 8532 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
| 8533 ins_pipe(floadF_mem); | |
| 8534 %} | |
| 8535 | |
| 8536 | |
| 8537 instruct convI2F_helper(regF dst, regF tmp) %{ | |
| 8538 effect(DEF dst, USE tmp); | |
| 8539 format %{ "FITOS $tmp,$dst" %} | |
| 8540 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
| 8541 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
| 8542 ins_pipe(fcvtI2F); | |
| 8543 %} | |
| 8544 | |
| 8545 instruct convI2F_stk(regF dst, stackSlotI src) %{ | |
| 8546 match(Set dst (ConvI2F src)); | |
| 8547 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8548 expand %{ | |
| 8549 regF tmp; | |
| 8550 stkI_to_regF(tmp,src); | |
| 8551 convI2F_helper(dst, tmp); | |
| 8552 %} | |
| 8553 %} | |
| 8554 | |
| 8555 instruct convI2F_reg(regF dst, iRegI src) %{ | |
| 8556 predicate(UseVIS >= 3); | |
| 8557 match(Set dst (ConvI2F src)); | |
| 8558 ins_cost(DEFAULT_COST); | |
| 8559 expand %{ | |
| 8560 regF tmp; | |
| 8561 MoveI2F_reg_reg(tmp, src); | |
| 8562 convI2F_helper(dst, tmp); | |
| 8563 %} | |
| 8564 %} | |
| 8565 | |
| 8566 instruct convI2F_mem( regF dst, memory mem ) %{ | |
| 8567 match(Set dst (ConvI2F (LoadI mem))); | |
| 8568 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8569 size(8); | |
| 8570 format %{ "LDF $mem,$dst\n\t" | |
| 8571 "FITOS $dst,$dst" %} | |
| 8572 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
| 8573 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
| 8574 ins_pipe(floadF_mem); | |
| 8575 %} | |
| 8576 | |
| 8577 | |
| 8578 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
| 8579 match(Set dst (ConvI2L src)); | |
| 8580 size(4); | |
| 8581 format %{ "SRA $src,0,$dst\t! int->long" %} | |
| 8582 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 8583 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8584 ins_pipe(ialu_reg_reg); | |
| 8585 %} | |
| 8586 | |
| 8587 // Zero-extend convert int to long | |
| 8588 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
| 8589 match(Set dst (AndL (ConvI2L src) mask) ); | |
| 8590 size(4); | |
| 8591 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
| 8592 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8593 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8594 ins_pipe(ialu_reg_reg); | |
| 8595 %} | |
| 8596 | |
| 8597 // Zero-extend long | |
| 8598 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
| 8599 match(Set dst (AndL src mask) ); | |
| 8600 size(4); | |
| 8601 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
| 8602 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8603 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8604 ins_pipe(ialu_reg_reg); | |
| 8605 %} | |
| 8606 | |
| 8607 | |
| 0 | 8608 //----------- |
| 8609 // Long to Double conversion using V8 opcodes. | |
| 8610 // Still useful because cheetah traps and becomes | |
| 8611 // amazingly slow for some common numbers. | |
| 8612 | |
| 8613 // Magic constant, 0x43300000 | |
| 8614 instruct loadConI_x43300000(iRegI dst) %{ | |
| 8615 effect(DEF dst); | |
| 8616 size(4); | |
| 8617 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
| 8618 ins_encode(SetHi22(0x43300000, dst)); | |
| 8619 ins_pipe(ialu_none); | |
| 8620 %} | |
| 8621 | |
| 8622 // Magic constant, 0x41f00000 | |
| 8623 instruct loadConI_x41f00000(iRegI dst) %{ | |
| 8624 effect(DEF dst); | |
| 8625 size(4); | |
| 8626 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
| 8627 ins_encode(SetHi22(0x41f00000, dst)); | |
| 8628 ins_pipe(ialu_none); | |
| 8629 %} | |
| 8630 | |
| 8631 // Construct a double from two float halves | |
| 8632 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
| 8633 effect(DEF dst, USE src1, USE src2); | |
| 8634 size(8); | |
| 8635 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
| 8636 "FMOVS $src2.lo,$dst.lo" %} | |
| 8637 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
| 8638 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
| 8639 ins_pipe(faddD_reg_reg); | |
| 8640 %} | |
| 8641 | |
| 8642 // Convert integer in high half of a double register (in the lower half of | |
| 8643 // the double register file) to double | |
| 8644 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
| 8645 effect(DEF dst, USE src); | |
| 8646 size(4); | |
| 8647 format %{ "FITOD $src,$dst" %} | |
| 8648 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8649 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
| 8650 ins_pipe(fcvtLHi2D); | |
| 8651 %} | |
| 8652 | |
| 8653 // Add float double precision | |
| 8654 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8655 effect(DEF dst, USE src1, USE src2); | |
| 8656 size(4); | |
| 8657 format %{ "FADDD $src1,$src2,$dst" %} | |
| 8658 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 8659 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8660 ins_pipe(faddD_reg_reg); | |
| 8661 %} | |
| 8662 | |
| 8663 // Sub float double precision | |
| 8664 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8665 effect(DEF dst, USE src1, USE src2); | |
| 8666 size(4); | |
| 8667 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 8668 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 8669 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8670 ins_pipe(faddD_reg_reg); | |
| 8671 %} | |
| 8672 | |
| 8673 // Mul float double precision | |
| 8674 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8675 effect(DEF dst, USE src1, USE src2); | |
| 8676 size(4); | |
| 8677 format %{ "FMULD $src1,$src2,$dst" %} | |
| 8678 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 8679 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8680 ins_pipe(fmulD_reg_reg); | |
| 8681 %} | |
| 8682 | |
| 8683 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
| 8684 match(Set dst (ConvL2D src)); | |
| 8685 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
| 8686 | |
| 8687 expand %{ | |
| 8688 regD_low tmpsrc; | |
| 8689 iRegI ix43300000; | |
| 8690 iRegI ix41f00000; | |
| 8691 stackSlotL lx43300000; | |
| 8692 stackSlotL lx41f00000; | |
| 8693 regD_low dx43300000; | |
| 8694 regD dx41f00000; | |
| 8695 regD tmp1; | |
| 8696 regD_low tmp2; | |
| 8697 regD tmp3; | |
| 8698 regD tmp4; | |
| 8699 | |
| 8700 stkL_to_regD(tmpsrc, src); | |
| 8701 | |
| 8702 loadConI_x43300000(ix43300000); | |
| 8703 loadConI_x41f00000(ix41f00000); | |
| 8704 regI_to_stkLHi(lx43300000, ix43300000); | |
| 8705 regI_to_stkLHi(lx41f00000, ix41f00000); | |
| 8706 stkL_to_regD(dx43300000, lx43300000); | |
| 8707 stkL_to_regD(dx41f00000, lx41f00000); | |
| 8708 | |
| 8709 convI2D_regDHi_regD(tmp1, tmpsrc); | |
| 8710 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
| 8711 subD_regD_regD(tmp3, tmp2, dx43300000); | |
| 8712 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
| 8713 addD_regD_regD(dst, tmp3, tmp4); | |
| 8714 %} | |
| 8715 %} | |
| 8716 | |
| 8717 // Long to Double conversion using fast fxtof | |
| 8718 instruct convL2D_helper(regD dst, regD tmp) %{ | |
| 8719 effect(DEF dst, USE tmp); | |
| 8720 size(4); | |
| 8721 format %{ "FXTOD $tmp,$dst" %} | |
| 8722 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
| 8723 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
| 8724 ins_pipe(fcvtL2D); | |
| 8725 %} | |
| 8726 | |
| 3804 | 8727 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ |
| 0 | 8728 predicate(VM_Version::has_fast_fxtof()); |
| 8729 match(Set dst (ConvL2D src)); | |
| 8730 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
| 8731 expand %{ | |
| 8732 regD tmp; | |
| 8733 stkL_to_regD(tmp, src); | |
| 8734 convL2D_helper(dst, tmp); | |
| 8735 %} | |
| 8736 %} | |
| 8737 | |
| 3804 | 8738 instruct convL2D_reg(regD dst, iRegL src) %{ |
| 8739 predicate(UseVIS >= 3); | |
| 8740 match(Set dst (ConvL2D src)); | |
| 8741 expand %{ | |
| 8742 regD tmp; | |
| 8743 MoveL2D_reg_reg(tmp, src); | |
| 8744 convL2D_helper(dst, tmp); | |
| 8745 %} | |
| 8746 %} | |
| 0 | 8747 |
| 8748 // Long to Float conversion using fast fxtof | |
| 8749 instruct convL2F_helper(regF dst, regD tmp) %{ | |
| 8750 effect(DEF dst, USE tmp); | |
| 8751 size(4); | |
| 8752 format %{ "FXTOS $tmp,$dst" %} | |
| 8753 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
| 8754 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
| 8755 ins_pipe(fcvtL2F); | |
| 8756 %} | |
| 8757 | |
| 3804 | 8758 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ |
| 0 | 8759 match(Set dst (ConvL2F src)); |
| 8760 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8761 expand %{ | |
| 8762 regD tmp; | |
| 8763 stkL_to_regD(tmp, src); | |
| 8764 convL2F_helper(dst, tmp); | |
| 8765 %} | |
| 8766 %} | |
| 3804 | 8767 |
| 8768 instruct convL2F_reg(regF dst, iRegL src) %{ | |
| 8769 predicate(UseVIS >= 3); | |
| 8770 match(Set dst (ConvL2F src)); | |
| 8771 ins_cost(DEFAULT_COST); | |
| 8772 expand %{ | |
| 8773 regD tmp; | |
| 8774 MoveL2D_reg_reg(tmp, src); | |
| 8775 convL2F_helper(dst, tmp); | |
| 8776 %} | |
| 8777 %} | |
| 8778 | |
| 0 | 8779 //----------- |
| 8780 | |
| 8781 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
| 8782 match(Set dst (ConvL2I src)); | |
| 8783 #ifndef _LP64 | |
| 8784 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
| 8785 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
| 8786 ins_pipe(ialu_move_reg_I_to_L); | |
| 8787 #else | |
| 8788 size(4); | |
| 8789 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
| 8790 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
| 8791 ins_pipe(ialu_reg); | |
| 8792 #endif | |
| 8793 %} | |
| 8794 | |
| 8795 // Register Shift Right Immediate | |
| 8796 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
| 8797 match(Set dst (ConvL2I (RShiftL src cnt))); | |
| 8798 | |
| 8799 size(4); | |
| 8800 format %{ "SRAX $src,$cnt,$dst" %} | |
| 8801 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 8802 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
| 8803 ins_pipe(ialu_reg_imm); | |
| 8804 %} | |
| 8805 | |
| 8806 // Replicate scalar to packed byte values in Double register | |
| 8807 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ | |
| 8808 effect(DEF dst, USE src); | |
| 8809 format %{ "SLLX $src,56,$dst\n\t" | |
| 8810 "SRLX $dst, 8,O7\n\t" | |
| 8811 "OR $dst,O7,$dst\n\t" | |
| 8812 "SRLX $dst,16,O7\n\t" | |
| 8813 "OR $dst,O7,$dst\n\t" | |
| 8814 "SRLX $dst,32,O7\n\t" | |
| 8815 "OR $dst,O7,$dst\t! replicate8B" %} | |
| 8816 ins_encode( enc_repl8b(src, dst)); | |
| 8817 ins_pipe(ialu_reg); | |
| 8818 %} | |
| 8819 | |
| 8820 // Replicate scalar to packed byte values in Double register | |
| 8821 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ | |
| 8822 match(Set dst (Replicate8B src)); | |
| 8823 expand %{ | |
| 8824 iRegL tmp; | |
| 8825 Repl8B_reg_helper(tmp, src); | |
| 8826 regL_to_stkD(dst, tmp); | |
| 8827 %} | |
| 8828 %} | |
| 8829 | |
| 8830 // Replicate scalar constant to packed byte values in Double register | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8831 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ |
| 2008 | 8832 match(Set dst (Replicate8B con)); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8833 effect(KILL tmp); |
| 2008 | 8834 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} |
| 8835 ins_encode %{ | |
| 8836 // XXX This is a quick fix for 6833573. | |
| 8837 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8838 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8839 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 2008 | 8840 %} |
| 0 | 8841 ins_pipe(loadConFD); |
| 8842 %} | |
| 8843 | |
| 8844 // Replicate scalar to packed char values into stack slot | |
| 8845 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ | |
| 8846 effect(DEF dst, USE src); | |
| 8847 format %{ "SLLX $src,48,$dst\n\t" | |
| 8848 "SRLX $dst,16,O7\n\t" | |
| 8849 "OR $dst,O7,$dst\n\t" | |
| 8850 "SRLX $dst,32,O7\n\t" | |
| 8851 "OR $dst,O7,$dst\t! replicate4C" %} | |
| 8852 ins_encode( enc_repl4s(src, dst) ); | |
| 8853 ins_pipe(ialu_reg); | |
| 8854 %} | |
| 8855 | |
| 8856 // Replicate scalar to packed char values into stack slot | |
| 8857 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ | |
| 8858 match(Set dst (Replicate4C src)); | |
| 8859 expand %{ | |
| 8860 iRegL tmp; | |
| 8861 Repl4C_reg_helper(tmp, src); | |
| 8862 regL_to_stkD(dst, tmp); | |
| 8863 %} | |
| 8864 %} | |
| 8865 | |
| 8866 // Replicate scalar constant to packed char values in Double register | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8867 instruct Repl4C_immI(regD dst, immI con, o7RegI tmp) %{ |
| 2008 | 8868 match(Set dst (Replicate4C con)); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8869 effect(KILL tmp); |
| 2008 | 8870 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %} |
| 8871 ins_encode %{ | |
| 8872 // XXX This is a quick fix for 6833573. | |
| 8873 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8874 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8875 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 2008 | 8876 %} |
| 0 | 8877 ins_pipe(loadConFD); |
| 8878 %} | |
| 8879 | |
| 8880 // Replicate scalar to packed short values into stack slot | |
| 8881 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ | |
| 8882 effect(DEF dst, USE src); | |
| 8883 format %{ "SLLX $src,48,$dst\n\t" | |
| 8884 "SRLX $dst,16,O7\n\t" | |
| 8885 "OR $dst,O7,$dst\n\t" | |
| 8886 "SRLX $dst,32,O7\n\t" | |
| 8887 "OR $dst,O7,$dst\t! replicate4S" %} | |
| 8888 ins_encode( enc_repl4s(src, dst) ); | |
| 8889 ins_pipe(ialu_reg); | |
| 8890 %} | |
| 8891 | |
| 8892 // Replicate scalar to packed short values into stack slot | |
| 8893 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ | |
| 8894 match(Set dst (Replicate4S src)); | |
| 8895 expand %{ | |
| 8896 iRegL tmp; | |
| 8897 Repl4S_reg_helper(tmp, src); | |
| 8898 regL_to_stkD(dst, tmp); | |
| 8899 %} | |
| 8900 %} | |
| 8901 | |
| 8902 // Replicate scalar constant to packed short values in Double register | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8903 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ |
| 2008 | 8904 match(Set dst (Replicate4S con)); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8905 effect(KILL tmp); |
| 2008 | 8906 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} |
| 8907 ins_encode %{ | |
| 8908 // XXX This is a quick fix for 6833573. | |
| 8909 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8910 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8911 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 2008 | 8912 %} |
| 0 | 8913 ins_pipe(loadConFD); |
| 8914 %} | |
| 8915 | |
| 8916 // Replicate scalar to packed int values in Double register | |
| 8917 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ | |
| 8918 effect(DEF dst, USE src); | |
| 8919 format %{ "SLLX $src,32,$dst\n\t" | |
| 8920 "SRLX $dst,32,O7\n\t" | |
| 8921 "OR $dst,O7,$dst\t! replicate2I" %} | |
| 8922 ins_encode( enc_repl2i(src, dst)); | |
| 8923 ins_pipe(ialu_reg); | |
| 8924 %} | |
| 8925 | |
| 8926 // Replicate scalar to packed int values in Double register | |
| 8927 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ | |
| 8928 match(Set dst (Replicate2I src)); | |
| 8929 expand %{ | |
| 8930 iRegL tmp; | |
| 8931 Repl2I_reg_helper(tmp, src); | |
| 8932 regL_to_stkD(dst, tmp); | |
| 8933 %} | |
| 8934 %} | |
| 8935 | |
| 8936 // Replicate scalar zero constant to packed int values in Double register | |
|
2012
5fe0781a8560
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diff
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|
8937 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ |
| 2008 | 8938 match(Set dst (Replicate2I con)); |
|
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|
8939 effect(KILL tmp); |
| 2008 | 8940 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} |
| 8941 ins_encode %{ | |
| 8942 // XXX This is a quick fix for 6833573. | |
| 8943 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); | |
|
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7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
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diff
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|
8944 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); |
|
5fe0781a8560
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|
8945 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 2008 | 8946 %} |
| 0 | 8947 ins_pipe(loadConFD); |
| 8948 %} | |
| 8949 | |
| 8950 //----------Control Flow Instructions------------------------------------------ | |
| 8951 // Compare Instructions | |
| 8952 // Compare Integers | |
| 8953 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
| 8954 match(Set icc (CmpI op1 op2)); | |
| 8955 effect( DEF icc, USE op1, USE op2 ); | |
| 8956 | |
| 8957 size(4); | |
| 8958 format %{ "CMP $op1,$op2" %} | |
| 8959 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8960 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8961 ins_pipe(ialu_cconly_reg_reg); | |
| 8962 %} | |
| 8963 | |
| 8964 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
| 8965 match(Set icc (CmpU op1 op2)); | |
| 8966 | |
| 8967 size(4); | |
| 8968 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 8969 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8970 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8971 ins_pipe(ialu_cconly_reg_reg); | |
| 8972 %} | |
| 8973 | |
| 8974 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
| 8975 match(Set icc (CmpI op1 op2)); | |
| 8976 effect( DEF icc, USE op1 ); | |
| 8977 | |
| 8978 size(4); | |
| 8979 format %{ "CMP $op1,$op2" %} | |
| 8980 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8981 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8982 ins_pipe(ialu_cconly_reg_imm); | |
| 8983 %} | |
| 8984 | |
| 8985 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
| 8986 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8987 | |
| 8988 size(4); | |
| 8989 format %{ "BTST $op2,$op1" %} | |
| 8990 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8991 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8992 ins_pipe(ialu_cconly_reg_reg_zero); | |
| 8993 %} | |
| 8994 | |
| 8995 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
| 8996 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8997 | |
| 8998 size(4); | |
| 8999 format %{ "BTST $op2,$op1" %} | |
| 9000 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 9001 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 9002 ins_pipe(ialu_cconly_reg_imm_zero); | |
| 9003 %} | |
| 9004 | |
| 9005 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
| 9006 match(Set xcc (CmpL op1 op2)); | |
| 9007 effect( DEF xcc, USE op1, USE op2 ); | |
| 9008 | |
| 9009 size(4); | |
| 9010 format %{ "CMP $op1,$op2\t\t! long" %} | |
| 9011 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 9012 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 9013 ins_pipe(ialu_cconly_reg_reg); | |
| 9014 %} | |
| 9015 | |
| 9016 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
| 9017 match(Set xcc (CmpL op1 con)); | |
| 9018 effect( DEF xcc, USE op1, USE con ); | |
| 9019 | |
| 9020 size(4); | |
| 9021 format %{ "CMP $op1,$con\t\t! long" %} | |
| 9022 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 9023 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 9024 ins_pipe(ialu_cconly_reg_reg); | |
| 9025 %} | |
| 9026 | |
| 9027 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
| 9028 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
| 9029 effect( DEF xcc, USE op1, USE op2 ); | |
| 9030 | |
| 9031 size(4); | |
| 9032 format %{ "BTST $op1,$op2\t\t! long" %} | |
| 9033 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 9034 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 9035 ins_pipe(ialu_cconly_reg_reg); | |
| 9036 %} | |
| 9037 | |
| 9038 // useful for checking the alignment of a pointer: | |
| 9039 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
| 9040 match(Set xcc (CmpL (AndL op1 con) zero)); | |
| 9041 effect( DEF xcc, USE op1, USE con ); | |
| 9042 | |
| 9043 size(4); | |
| 9044 format %{ "BTST $op1,$con\t\t! long" %} | |
| 9045 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 9046 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 9047 ins_pipe(ialu_cconly_reg_reg); | |
| 9048 %} | |
| 9049 | |
| 9050 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ | |
| 9051 match(Set icc (CmpU op1 op2)); | |
| 9052 | |
| 9053 size(4); | |
| 9054 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 9055 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 9056 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 9057 ins_pipe(ialu_cconly_reg_imm); | |
| 9058 %} | |
| 9059 | |
| 9060 // Compare Pointers | |
| 9061 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
| 9062 match(Set pcc (CmpP op1 op2)); | |
| 9063 | |
| 9064 size(4); | |
| 9065 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 9066 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 9067 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 9068 ins_pipe(ialu_cconly_reg_reg); | |
| 9069 %} | |
| 9070 | |
| 9071 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
| 9072 match(Set pcc (CmpP op1 op2)); | |
| 9073 | |
| 9074 size(4); | |
| 9075 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 9076 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 9077 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 9078 ins_pipe(ialu_cconly_reg_imm); | |
| 9079 %} | |
| 9080 | |
|
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9081 // Compare Narrow oops |
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9082 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
|
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9083 match(Set icc (CmpN op1 op2)); |
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9084 |
|
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|
9085 size(4); |
|
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9086 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
|
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9087 opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
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9088 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
|
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9089 ins_pipe(ialu_cconly_reg_reg); |
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9090 %} |
|
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9091 |
|
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9092 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
|
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9093 match(Set icc (CmpN op1 op2)); |
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9094 |
|
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|
9095 size(4); |
|
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9096 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
|
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9097 opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
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9098 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
|
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9099 ins_pipe(ialu_cconly_reg_imm); |
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9100 %} |
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9101 |
| 0 | 9102 //----------Max and Min-------------------------------------------------------- |
| 9103 // Min Instructions | |
| 9104 // Conditional move for min | |
| 9105 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 9106 effect( USE_DEF op2, USE op1, USE icc ); | |
| 9107 | |
| 9108 size(4); | |
| 9109 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
| 9110 opcode(Assembler::less); | |
| 9111 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 9112 ins_pipe(ialu_reg_flags); | |
| 9113 %} | |
| 9114 | |
| 9115 // Min Register with Register. | |
| 9116 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
| 9117 match(Set op2 (MinI op1 op2)); | |
| 9118 ins_cost(DEFAULT_COST*2); | |
| 9119 expand %{ | |
| 9120 flagsReg icc; | |
| 9121 compI_iReg(icc,op1,op2); | |
| 9122 cmovI_reg_lt(op2,op1,icc); | |
| 9123 %} | |
| 9124 %} | |
| 9125 | |
| 9126 // Max Instructions | |
| 9127 // Conditional move for max | |
| 9128 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 9129 effect( USE_DEF op2, USE op1, USE icc ); | |
| 9130 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
| 9131 opcode(Assembler::greater); | |
| 9132 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 9133 ins_pipe(ialu_reg_flags); | |
| 9134 %} | |
| 9135 | |
| 9136 // Max Register with Register | |
| 9137 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
| 9138 match(Set op2 (MaxI op1 op2)); | |
| 9139 ins_cost(DEFAULT_COST*2); | |
| 9140 expand %{ | |
| 9141 flagsReg icc; | |
| 9142 compI_iReg(icc,op1,op2); | |
| 9143 cmovI_reg_gt(op2,op1,icc); | |
| 9144 %} | |
| 9145 %} | |
| 9146 | |
| 9147 | |
| 9148 //----------Float Compares---------------------------------------------------- | |
| 9149 // Compare floating, generate condition code | |
| 9150 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
| 9151 match(Set fcc (CmpF src1 src2)); | |
| 9152 | |
| 9153 size(4); | |
| 9154 format %{ "FCMPs $fcc,$src1,$src2" %} | |
| 9155 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
| 9156 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
| 9157 ins_pipe(faddF_fcc_reg_reg_zero); | |
| 9158 %} | |
| 9159 | |
| 9160 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
| 9161 match(Set fcc (CmpD src1 src2)); | |
| 9162 | |
| 9163 size(4); | |
| 9164 format %{ "FCMPd $fcc,$src1,$src2" %} | |
| 9165 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
| 9166 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
| 9167 ins_pipe(faddD_fcc_reg_reg_zero); | |
| 9168 %} | |
| 9169 | |
| 9170 | |
| 9171 // Compare floating, generate -1,0,1 | |
| 9172 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
| 9173 match(Set dst (CmpF3 src1 src2)); | |
| 9174 effect(KILL fcc0); | |
| 9175 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 9176 format %{ "fcmpl $dst,$src1,$src2" %} | |
| 9177 // Primary = float | |
| 9178 opcode( true ); | |
| 9179 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 9180 ins_pipe( floating_cmp ); | |
| 9181 %} | |
| 9182 | |
| 9183 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
| 9184 match(Set dst (CmpD3 src1 src2)); | |
| 9185 effect(KILL fcc0); | |
| 9186 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 9187 format %{ "dcmpl $dst,$src1,$src2" %} | |
| 9188 // Primary = double (not float) | |
| 9189 opcode( false ); | |
| 9190 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 9191 ins_pipe( floating_cmp ); | |
| 9192 %} | |
| 9193 | |
| 9194 //----------Branches--------------------------------------------------------- | |
| 9195 // Jump | |
| 9196 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
| 9197 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
| 9198 match(Jump switch_val); | |
| 9199 | |
| 9200 ins_cost(350); | |
| 9201 | |
| 2008 | 9202 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" |
| 9203 "LD [O7 + $switch_val], O7\n\t" | |
| 0 | 9204 "JUMP O7" |
| 9205 %} | |
| 2008 | 9206 ins_encode %{ |
| 9207 // Calculate table address into a register. | |
| 9208 Register table_reg; | |
| 9209 Register label_reg = O7; | |
| 9210 if (constant_offset() == 0) { | |
| 9211 table_reg = $constanttablebase; | |
| 9212 } else { | |
| 9213 table_reg = O7; | |
|
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|
9214 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); |
|
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|
9215 __ add($constanttablebase, con_offset, table_reg); |
| 2008 | 9216 } |
| 9217 | |
| 9218 // Jump to base address + switch value | |
| 9219 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); | |
| 9220 __ jmp(label_reg, G0); | |
| 9221 __ delayed()->nop(); | |
| 9222 %} | |
| 0 | 9223 ins_pc_relative(1); |
| 9224 ins_pipe(ialu_reg_reg); | |
| 9225 %} | |
| 9226 | |
| 9227 // Direct Branch. Use V8 version with longer range. | |
| 9228 instruct branch(label labl) %{ | |
| 9229 match(Goto); | |
| 9230 effect(USE labl); | |
| 9231 | |
| 9232 size(8); | |
| 9233 ins_cost(BRANCH_COST); | |
| 9234 format %{ "BA $labl" %} | |
| 9235 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond | |
| 9236 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); | |
| 9237 ins_encode( enc_ba( labl ) ); | |
| 9238 ins_pc_relative(1); | |
| 9239 ins_pipe(br); | |
| 9240 %} | |
| 9241 | |
| 9242 // Conditional Direct Branch | |
| 9243 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 9244 match(If cmp icc); | |
| 9245 effect(USE labl); | |
| 9246 | |
| 9247 size(8); | |
| 9248 ins_cost(BRANCH_COST); | |
| 9249 format %{ "BP$cmp $icc,$labl" %} | |
| 9250 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9251 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9252 ins_pc_relative(1); | |
| 9253 ins_pipe(br_cc); | |
| 9254 %} | |
| 9255 | |
| 9256 // Branch-on-register tests all 64 bits. We assume that values | |
| 9257 // in 64-bit registers always remains zero or sign extended | |
| 9258 // unless our code munges the high bits. Interrupts can chop | |
| 9259 // the high order bits to zero or sign at any time. | |
| 9260 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
| 9261 match(If cmp (CmpI op1 zero)); | |
| 9262 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9263 effect(USE labl); | |
| 9264 | |
| 9265 size(8); | |
| 9266 ins_cost(BRANCH_COST); | |
| 9267 format %{ "BR$cmp $op1,$labl" %} | |
| 9268 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9269 ins_pc_relative(1); | |
| 9270 ins_pipe(br_reg); | |
| 9271 %} | |
| 9272 | |
| 9273 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
| 9274 match(If cmp (CmpP op1 null)); | |
| 9275 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9276 effect(USE labl); | |
| 9277 | |
| 9278 size(8); | |
| 9279 ins_cost(BRANCH_COST); | |
| 9280 format %{ "BR$cmp $op1,$labl" %} | |
| 9281 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9282 ins_pc_relative(1); | |
| 9283 ins_pipe(br_reg); | |
| 9284 %} | |
| 9285 | |
| 9286 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
| 9287 match(If cmp (CmpL op1 zero)); | |
| 9288 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9289 effect(USE labl); | |
| 9290 | |
| 9291 size(8); | |
| 9292 ins_cost(BRANCH_COST); | |
| 9293 format %{ "BR$cmp $op1,$labl" %} | |
| 9294 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9295 ins_pc_relative(1); | |
| 9296 ins_pipe(br_reg); | |
| 9297 %} | |
| 9298 | |
| 9299 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9300 match(If cmp icc); | |
| 9301 effect(USE labl); | |
| 9302 | |
| 9303 format %{ "BP$cmp $icc,$labl" %} | |
| 9304 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9305 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9306 ins_pc_relative(1); | |
| 9307 ins_pipe(br_cc); | |
| 9308 %} | |
| 9309 | |
| 9310 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
| 9311 match(If cmp pcc); | |
| 9312 effect(USE labl); | |
| 9313 | |
| 9314 size(8); | |
| 9315 ins_cost(BRANCH_COST); | |
| 9316 format %{ "BP$cmp $pcc,$labl" %} | |
| 9317 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9318 ins_encode( enc_bpx( labl, cmp, pcc ) ); | |
| 9319 ins_pc_relative(1); | |
| 9320 ins_pipe(br_cc); | |
| 9321 %} | |
| 9322 | |
| 9323 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
| 9324 match(If cmp fcc); | |
| 9325 effect(USE labl); | |
| 9326 | |
| 9327 size(8); | |
| 9328 ins_cost(BRANCH_COST); | |
| 9329 format %{ "FBP$cmp $fcc,$labl" %} | |
| 9330 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9331 ins_encode( enc_fbp( labl, cmp, fcc ) ); | |
| 9332 ins_pc_relative(1); | |
| 9333 ins_pipe(br_fcc); | |
| 9334 %} | |
| 9335 | |
| 9336 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 9337 match(CountedLoopEnd cmp icc); | |
| 9338 effect(USE labl); | |
| 9339 | |
| 9340 size(8); | |
| 9341 ins_cost(BRANCH_COST); | |
| 9342 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9343 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9344 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9345 ins_pc_relative(1); | |
| 9346 ins_pipe(br_cc); | |
| 9347 %} | |
| 9348 | |
| 9349 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9350 match(CountedLoopEnd cmp icc); | |
| 9351 effect(USE labl); | |
| 9352 | |
| 9353 size(8); | |
| 9354 ins_cost(BRANCH_COST); | |
| 9355 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9356 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9357 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9358 ins_pc_relative(1); | |
| 9359 ins_pipe(br_cc); | |
| 9360 %} | |
| 9361 | |
| 9362 // ============================================================================ | |
| 9363 // Long Compare | |
| 9364 // | |
| 9365 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 9366 // is tricky. The flavor of compare used depends on whether we are testing | |
| 9367 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 9368 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 9369 // the operands (yielding a GE test) and then negating; negate again for the | |
| 9370 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 9371 // NE test is negated from that. | |
| 9372 | |
| 9373 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 9374 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 9375 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 9376 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 9377 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 9378 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 9379 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 9380 // both forms beat the trinary form of long-compare and both are very useful | |
| 9381 // on Intel which has so few registers. | |
| 9382 | |
| 9383 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
| 9384 match(If cmp xcc); | |
| 9385 effect(USE labl); | |
| 9386 | |
| 9387 size(8); | |
| 9388 ins_cost(BRANCH_COST); | |
| 9389 format %{ "BP$cmp $xcc,$labl" %} | |
| 9390 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9391 ins_encode( enc_bpl( labl, cmp, xcc ) ); | |
| 9392 ins_pc_relative(1); | |
| 9393 ins_pipe(br_cc); | |
| 9394 %} | |
| 9395 | |
| 9396 // Manifest a CmpL3 result in an integer register. Very painful. | |
| 9397 // This is the test to avoid. | |
| 9398 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
| 9399 match(Set dst (CmpL3 src1 src2) ); | |
| 9400 effect( KILL ccr ); | |
| 9401 ins_cost(6*DEFAULT_COST); | |
| 9402 size(24); | |
| 9403 format %{ "CMP $src1,$src2\t\t! long\n" | |
| 9404 "\tBLT,a,pn done\n" | |
| 9405 "\tMOV -1,$dst\t! delay slot\n" | |
| 9406 "\tBGT,a,pn done\n" | |
| 9407 "\tMOV 1,$dst\t! delay slot\n" | |
| 9408 "\tCLR $dst\n" | |
| 9409 "done:" %} | |
| 9410 ins_encode( cmpl_flag(src1,src2,dst) ); | |
| 9411 ins_pipe(cmpL_reg); | |
| 9412 %} | |
| 9413 | |
| 9414 // Conditional move | |
| 9415 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
| 9416 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9417 ins_cost(150); | |
| 9418 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9419 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9420 ins_pipe(ialu_reg); | |
| 9421 %} | |
| 9422 | |
| 9423 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
| 9424 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9425 ins_cost(140); | |
| 9426 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9427 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9428 ins_pipe(ialu_imm); | |
| 9429 %} | |
| 9430 | |
| 9431 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
| 9432 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9433 ins_cost(150); | |
| 9434 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9435 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9436 ins_pipe(ialu_reg); | |
| 9437 %} | |
| 9438 | |
| 9439 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
| 9440 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9441 ins_cost(140); | |
| 9442 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9443 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9444 ins_pipe(ialu_imm); | |
| 9445 %} | |
| 9446 | |
|
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9447 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
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9448 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
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9449 ins_cost(150); |
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9450 format %{ "MOV$cmp $xcc,$src,$dst" %} |
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9451 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
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9452 ins_pipe(ialu_reg); |
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9453 %} |
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9454 |
| 0 | 9455 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
| 9456 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 9457 ins_cost(150); | |
| 9458 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9459 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9460 ins_pipe(ialu_reg); | |
| 9461 %} | |
| 9462 | |
| 9463 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
| 9464 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 9465 ins_cost(140); | |
| 9466 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9467 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9468 ins_pipe(ialu_imm); | |
| 9469 %} | |
| 9470 | |
| 9471 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
| 9472 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
| 9473 ins_cost(150); | |
| 9474 opcode(0x101); | |
| 9475 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
| 9476 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9477 ins_pipe(int_conditional_float_move); | |
| 9478 %} | |
| 9479 | |
| 9480 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
| 9481 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
| 9482 ins_cost(150); | |
| 9483 opcode(0x102); | |
| 9484 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
| 9485 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9486 ins_pipe(int_conditional_float_move); | |
| 9487 %} | |
| 9488 | |
| 9489 // ============================================================================ | |
| 9490 // Safepoint Instruction | |
| 9491 instruct safePoint_poll(iRegP poll) %{ | |
| 9492 match(SafePoint poll); | |
| 9493 effect(USE poll); | |
| 9494 | |
| 9495 size(4); | |
| 9496 #ifdef _LP64 | |
| 9497 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 9498 #else | |
| 9499 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 9500 #endif | |
| 9501 ins_encode %{ | |
| 9502 __ relocate(relocInfo::poll_type); | |
| 9503 __ ld_ptr($poll$$Register, 0, G0); | |
| 9504 %} | |
| 9505 ins_pipe(loadPollP); | |
| 9506 %} | |
| 9507 | |
| 9508 // ============================================================================ | |
| 9509 // Call Instructions | |
| 9510 // Call Java Static Instruction | |
| 9511 instruct CallStaticJavaDirect( method meth ) %{ | |
| 9512 match(CallStaticJava); | |
| 1567 | 9513 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
| 0 | 9514 effect(USE meth); |
| 9515 | |
| 9516 size(8); | |
| 9517 ins_cost(CALL_COST); | |
| 9518 format %{ "CALL,static ; NOP ==> " %} | |
| 9519 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
| 9520 ins_pc_relative(1); | |
| 9521 ins_pipe(simple_call); | |
| 9522 %} | |
| 9523 | |
| 1567 | 9524 // Call Java Static Instruction (method handle version) |
| 9525 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ | |
| 9526 match(CallStaticJava); | |
| 9527 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); | |
| 9528 effect(USE meth, KILL l7_mh_SP_save); | |
| 9529 | |
| 9530 size(8); | |
| 9531 ins_cost(CALL_COST); | |
| 9532 format %{ "CALL,static/MethodHandle" %} | |
| 9533 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); | |
| 9534 ins_pc_relative(1); | |
| 9535 ins_pipe(simple_call); | |
| 9536 %} | |
| 9537 | |
| 0 | 9538 // Call Java Dynamic Instruction |
| 9539 instruct CallDynamicJavaDirect( method meth ) %{ | |
| 9540 match(CallDynamicJava); | |
| 9541 effect(USE meth); | |
| 9542 | |
| 9543 ins_cost(CALL_COST); | |
| 9544 format %{ "SET (empty),R_G5\n\t" | |
| 9545 "CALL,dynamic ; NOP ==> " %} | |
| 9546 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
| 9547 ins_pc_relative(1); | |
| 9548 ins_pipe(call); | |
| 9549 %} | |
| 9550 | |
| 9551 // Call Runtime Instruction | |
| 9552 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
| 9553 match(CallRuntime); | |
| 9554 effect(USE meth, KILL l7); | |
| 9555 ins_cost(CALL_COST); | |
| 9556 format %{ "CALL,runtime" %} | |
| 9557 ins_encode( Java_To_Runtime( meth ), | |
| 9558 call_epilog, adjust_long_from_native_call ); | |
| 9559 ins_pc_relative(1); | |
| 9560 ins_pipe(simple_call); | |
| 9561 %} | |
| 9562 | |
| 9563 // Call runtime without safepoint - same as CallRuntime | |
| 9564 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
| 9565 match(CallLeaf); | |
| 9566 effect(USE meth, KILL l7); | |
| 9567 ins_cost(CALL_COST); | |
| 9568 format %{ "CALL,runtime leaf" %} | |
| 9569 ins_encode( Java_To_Runtime( meth ), | |
| 9570 call_epilog, | |
| 9571 adjust_long_from_native_call ); | |
| 9572 ins_pc_relative(1); | |
| 9573 ins_pipe(simple_call); | |
| 9574 %} | |
| 9575 | |
| 9576 // Call runtime without safepoint - same as CallLeaf | |
| 9577 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
| 9578 match(CallLeafNoFP); | |
| 9579 effect(USE meth, KILL l7); | |
| 9580 ins_cost(CALL_COST); | |
| 9581 format %{ "CALL,runtime leaf nofp" %} | |
| 9582 ins_encode( Java_To_Runtime( meth ), | |
| 9583 call_epilog, | |
| 9584 adjust_long_from_native_call ); | |
| 9585 ins_pc_relative(1); | |
| 9586 ins_pipe(simple_call); | |
| 9587 %} | |
| 9588 | |
| 9589 // Tail Call; Jump from runtime stub to Java code. | |
| 9590 // Also known as an 'interprocedural jump'. | |
| 9591 // Target of jump will eventually return to caller. | |
| 9592 // TailJump below removes the return address. | |
| 9593 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
| 9594 match(TailCall jump_target method_oop ); | |
| 9595 | |
| 9596 ins_cost(CALL_COST); | |
| 9597 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
| 9598 ins_encode(form_jmpl(jump_target)); | |
| 9599 ins_pipe(tail_call); | |
| 9600 %} | |
| 9601 | |
| 9602 | |
| 9603 // Return Instruction | |
| 9604 instruct Ret() %{ | |
| 9605 match(Return); | |
| 9606 | |
| 9607 // The epilogue node did the ret already. | |
| 9608 size(0); | |
| 9609 format %{ "! return" %} | |
| 9610 ins_encode(); | |
| 9611 ins_pipe(empty); | |
| 9612 %} | |
| 9613 | |
| 9614 | |
| 9615 // Tail Jump; remove the return address; jump to target. | |
| 9616 // TailCall above leaves the return address around. | |
| 9617 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
| 9618 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
| 9619 // "restore" before this instruction (in Epilogue), we need to materialize it | |
| 9620 // in %i0. | |
| 9621 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
| 9622 match( TailJump jump_target ex_oop ); | |
| 9623 ins_cost(CALL_COST); | |
| 9624 format %{ "! discard R_O7\n\t" | |
| 9625 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
| 9626 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
| 9627 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
| 9628 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
| 9629 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
| 9630 ins_pipe(tail_call); | |
| 9631 %} | |
| 9632 | |
| 9633 // Create exception oop: created by stack-crawling runtime code. | |
| 9634 // Created exception is now available to this handler, and is setup | |
| 9635 // just prior to jumping to this handler. No code emitted. | |
| 9636 instruct CreateException( o0RegP ex_oop ) | |
| 9637 %{ | |
| 9638 match(Set ex_oop (CreateEx)); | |
| 9639 ins_cost(0); | |
| 9640 | |
| 9641 size(0); | |
| 9642 // use the following format syntax | |
| 9643 format %{ "! exception oop is in R_O0; no code emitted" %} | |
| 9644 ins_encode(); | |
| 9645 ins_pipe(empty); | |
| 9646 %} | |
| 9647 | |
| 9648 | |
| 9649 // Rethrow exception: | |
| 9650 // The exception oop will come in the first argument position. | |
| 9651 // Then JUMP (not call) to the rethrow stub code. | |
| 9652 instruct RethrowException() | |
| 9653 %{ | |
| 9654 match(Rethrow); | |
| 9655 ins_cost(CALL_COST); | |
| 9656 | |
| 9657 // use the following format syntax | |
| 9658 format %{ "Jmp rethrow_stub" %} | |
| 9659 ins_encode(enc_rethrow); | |
| 9660 ins_pipe(tail_call); | |
| 9661 %} | |
| 9662 | |
| 9663 | |
| 9664 // Die now | |
| 9665 instruct ShouldNotReachHere( ) | |
| 9666 %{ | |
| 9667 match(Halt); | |
| 9668 ins_cost(CALL_COST); | |
| 9669 | |
| 9670 size(4); | |
| 9671 // Use the following format syntax | |
| 9672 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
| 9673 ins_encode( form2_illtrap() ); | |
| 9674 ins_pipe(tail_call); | |
| 9675 %} | |
| 9676 | |
| 9677 // ============================================================================ | |
| 9678 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 9679 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 9680 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 9681 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 9682 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
| 9683 match(Set index (PartialSubtypeCheck sub super)); | |
| 9684 effect( KILL pcc, KILL o7 ); | |
| 9685 ins_cost(DEFAULT_COST*10); | |
| 9686 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
| 9687 ins_encode( enc_PartialSubtypeCheck() ); | |
| 9688 ins_pipe(partial_subtype_check_pipe); | |
| 9689 %} | |
| 9690 | |
| 9691 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
| 9692 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 9693 effect( KILL idx, KILL o7 ); | |
| 9694 ins_cost(DEFAULT_COST*10); | |
| 9695 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
| 9696 ins_encode( enc_PartialSubtypeCheck() ); | |
| 9697 ins_pipe(partial_subtype_check_pipe); | |
| 9698 %} | |
| 9699 | |
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9700 |
| 0 | 9701 // ============================================================================ |
| 9702 // inlined locking and unlocking | |
| 9703 | |
| 9704 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
| 9705 match(Set pcc (FastLock object box)); | |
| 9706 | |
| 9707 effect(KILL scratch, TEMP scratch2); | |
| 9708 ins_cost(100); | |
| 9709 | |
| 9710 size(4*112); // conservative overestimation ... | |
| 9711 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
| 9712 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); | |
| 9713 ins_pipe(long_memory_op); | |
| 9714 %} | |
| 9715 | |
| 9716 | |
| 9717 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
| 9718 match(Set pcc (FastUnlock object box)); | |
| 9719 effect(KILL scratch, TEMP scratch2); | |
| 9720 ins_cost(100); | |
| 9721 | |
| 9722 size(4*120); // conservative overestimation ... | |
| 9723 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
| 9724 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); | |
| 9725 ins_pipe(long_memory_op); | |
| 9726 %} | |
| 9727 | |
| 9728 // Count and Base registers are fixed because the allocator cannot | |
| 9729 // kill unknown registers. The encodings are generic. | |
| 9730 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ | |
| 9731 match(Set dummy (ClearArray cnt base)); | |
| 9732 effect(TEMP temp, KILL ccr); | |
| 9733 ins_cost(300); | |
| 9734 format %{ "MOV $cnt,$temp\n" | |
| 9735 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
| 9736 " BRge loop\t\t! Clearing loop\n" | |
| 9737 " STX G0,[$base+$temp]\t! delay slot" %} | |
| 9738 ins_encode( enc_Clear_Array(cnt, base, temp) ); | |
| 9739 ins_pipe(long_memory_op); | |
| 9740 %} | |
| 9741 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9742 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9743 o7RegI tmp, flagsReg ccr) %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9744 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9745 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
| 0 | 9746 ins_cost(300); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9747 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9748 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
| 0 | 9749 ins_pipe(long_memory_op); |
| 9750 %} | |
| 9751 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9752 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9753 o7RegI tmp, flagsReg ccr) %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9754 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9755 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
| 681 | 9756 ins_cost(300); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9757 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9758 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
| 681 | 9759 ins_pipe(long_memory_op); |
| 9760 %} | |
| 9761 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9762 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9763 o7RegI tmp2, flagsReg ccr) %{ |
| 681 | 9764 match(Set result (AryEq ary1 ary2)); |
| 9765 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
| 9766 ins_cost(300); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9767 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
9768 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
| 681 | 9769 ins_pipe(long_memory_op); |
| 9770 %} | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9771 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9772 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9773 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9774 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9775 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9776 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9777 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9778 effect(TEMP dst, TEMP tmp, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9779 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9780 // x |= (x >> 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9781 // x |= (x >> 2); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9782 // x |= (x >> 4); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9783 // x |= (x >> 8); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9784 // x |= (x >> 16); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9785 // return (WORDBITS - popc(x)); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9786 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9787 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9788 "OR $dst,$tmp,$dst\n\t" |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9789 "SRL $dst,2,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9790 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9791 "SRL $dst,4,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9792 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9793 "SRL $dst,8,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9794 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9795 "SRL $dst,16,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9796 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9797 "POPC $dst,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9798 "MOV 32,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9799 "SUB $tmp,$dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9800 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9801 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9802 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9803 Register Rtmp = $tmp$$Register; |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9804 __ srl(Rsrc, 1, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9805 __ srl(Rsrc, 0, Rdst); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9806 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9807 __ srl(Rdst, 2, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9808 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9809 __ srl(Rdst, 4, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9810 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9811 __ srl(Rdst, 8, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9812 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9813 __ srl(Rdst, 16, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9814 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9815 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9816 __ mov(BitsPerInt, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9817 __ sub(Rtmp, Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9818 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9819 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9820 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9821 |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9822 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9823 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9824 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9825 effect(TEMP dst, TEMP tmp, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9826 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9827 // x |= (x >> 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9828 // x |= (x >> 2); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9829 // x |= (x >> 4); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9830 // x |= (x >> 8); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9831 // x |= (x >> 16); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9832 // x |= (x >> 32); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9833 // return (WORDBITS - popc(x)); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9834 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9835 "OR $src,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9836 "SRLX $dst,2,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9837 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9838 "SRLX $dst,4,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9839 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9840 "SRLX $dst,8,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9841 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9842 "SRLX $dst,16,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9843 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9844 "SRLX $dst,32,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9845 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9846 "POPC $dst,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9847 "MOV 64,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9848 "SUB $tmp,$dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9849 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9850 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9851 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9852 Register Rtmp = $tmp$$Register; |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9853 __ srlx(Rsrc, 1, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9854 __ or3( Rsrc, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9855 __ srlx(Rdst, 2, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9856 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9857 __ srlx(Rdst, 4, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9858 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9859 __ srlx(Rdst, 8, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9860 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9861 __ srlx(Rdst, 16, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9862 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9863 __ srlx(Rdst, 32, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
9864 __ or3( Rdst, Rtmp, Rdst); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9865 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9866 __ mov(BitsPerLong, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9867 __ sub(Rtmp, Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9868 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9869 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9870 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9871 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9872 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9873 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9874 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9875 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9876 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9877 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9878 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9879 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9880 "SRL $dst,R_G0,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9881 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9882 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9883 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9884 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9885 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9886 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9887 __ srl(Rdst, G0, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9888 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9889 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9890 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9891 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9892 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9893 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9894 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9895 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9896 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9897 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9898 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9899 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9900 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9901 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9902 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9903 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9904 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9905 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9906 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9907 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9908 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9909 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9910 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9911 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9912 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9913 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9914 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9915 instruct popCountI(iRegI dst, iRegI src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9916 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9917 match(Set dst (PopCountI src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9918 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9919 format %{ "POPC $src, $dst" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9920 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9921 __ popc($src$$Register, $dst$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9922 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9923 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9924 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9925 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9926 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9927 instruct popCountL(iRegI dst, iRegL src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9928 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9929 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9930 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9931 format %{ "POPC $src, $dst" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9932 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9933 __ popc($src$$Register, $dst$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9934 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9935 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9936 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9937 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9938 |
| 0 | 9939 // ============================================================================ |
| 9940 //------------Bytes reverse-------------------------------------------------- | |
| 9941 | |
| 9942 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
| 9943 match(Set dst (ReverseBytesI src)); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9944 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9945 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9946 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9947 // onto a stack slot. |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9948 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9949 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9950 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9951 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9952 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9953 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9954 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9955 ins_pipe( iload_mem ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9956 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9957 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9958 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9959 match(Set dst (ReverseBytesL src)); |
| 0 | 9960 |
| 9961 // Op cost is artificially doubled to make sure that load or store | |
| 9962 // instructions are preferred over this one which requires a spill | |
| 9963 // onto a stack slot. | |
| 9964 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9965 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9966 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9967 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9968 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9969 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
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|
9970 %} |
| 0 | 9971 ins_pipe( iload_mem ); |
| 9972 %} | |
| 9973 | |
|
1396
d7f654633cfe
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|
9974 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
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never
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diff
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|
9975 match(Set dst (ReverseBytesUS src)); |
|
d7f654633cfe
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parents:
1367
diff
changeset
|
9976 |
|
d7f654633cfe
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parents:
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diff
changeset
|
9977 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
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parents:
1367
diff
changeset
|
9978 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
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diff
changeset
|
9979 // onto a stack slot. |
|
d7f654633cfe
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diff
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|
9980 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
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|
9981 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
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diff
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|
9982 |
|
d7f654633cfe
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never
parents:
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diff
changeset
|
9983 ins_encode %{ |
|
d7f654633cfe
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diff
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|
9984 // the value was spilled as an int so bias the load |
|
d7f654633cfe
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|
9985 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
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|
9986 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
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diff
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|
9987 %} |
|
d7f654633cfe
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parents:
1367
diff
changeset
|
9988 ins_pipe( iload_mem ); |
|
d7f654633cfe
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parents:
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diff
changeset
|
9989 %} |
|
d7f654633cfe
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parents:
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diff
changeset
|
9990 |
|
d7f654633cfe
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diff
changeset
|
9991 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
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|
9992 match(Set dst (ReverseBytesS src)); |
| 0 | 9993 |
| 9994 // Op cost is artificially doubled to make sure that load or store | |
| 9995 // instructions are preferred over this one which requires a spill | |
| 9996 // onto a stack slot. | |
| 9997 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
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|
9998 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
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never
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1367
diff
changeset
|
9999 |
|
d7f654633cfe
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diff
changeset
|
10000 ins_encode %{ |
|
d7f654633cfe
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diff
changeset
|
10001 // the value was spilled as an int so bias the load |
|
d7f654633cfe
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never
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|
10002 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
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|
10003 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
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|
10004 %} |
| 0 | 10005 ins_pipe( iload_mem ); |
| 10006 %} | |
| 10007 | |
| 10008 // Load Integer reversed byte order | |
|
1396
d7f654633cfe
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|
10009 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ |
| 0 | 10010 match(Set dst (ReverseBytesI (LoadI src))); |
| 10011 | |
| 10012 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
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|
10013 size(4); |
| 0 | 10014 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
| 10015 | |
|
1396
d7f654633cfe
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|
10016 ins_encode %{ |
|
d7f654633cfe
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changeset
|
10017 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
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|
10018 %} |
| 0 | 10019 ins_pipe(iload_mem); |
| 10020 %} | |
| 10021 | |
| 10022 // Load Long - aligned and reversed | |
|
1396
d7f654633cfe
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never
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|
10023 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ |
| 0 | 10024 match(Set dst (ReverseBytesL (LoadL src))); |
| 10025 | |
|
1396
d7f654633cfe
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|
10026 ins_cost(MEMORY_REF_COST); |
|
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|
10027 size(4); |
| 0 | 10028 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
| 10029 | |
|
1396
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|
10030 ins_encode %{ |
|
d7f654633cfe
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diff
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|
10031 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
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|
10032 %} |
|
d7f654633cfe
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diff
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|
10033 ins_pipe(iload_mem); |
|
d7f654633cfe
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diff
changeset
|
10034 %} |
|
d7f654633cfe
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diff
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|
10035 |
|
d7f654633cfe
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diff
changeset
|
10036 // Load unsigned short / char reversed byte order |
|
d7f654633cfe
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never
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changeset
|
10037 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
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|
10038 match(Set dst (ReverseBytesUS (LoadUS src))); |
|
d7f654633cfe
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diff
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|
10039 |
|
d7f654633cfe
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|
10040 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
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diff
changeset
|
10041 size(4); |
|
d7f654633cfe
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changeset
|
10042 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
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diff
changeset
|
10043 |
|
d7f654633cfe
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diff
changeset
|
10044 ins_encode %{ |
|
d7f654633cfe
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|
10045 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
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diff
changeset
|
10046 %} |
|
d7f654633cfe
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diff
changeset
|
10047 ins_pipe(iload_mem); |
|
d7f654633cfe
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diff
changeset
|
10048 %} |
|
d7f654633cfe
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diff
changeset
|
10049 |
|
d7f654633cfe
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diff
changeset
|
10050 // Load short reversed byte order |
|
d7f654633cfe
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diff
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|
10051 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
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|
10052 match(Set dst (ReverseBytesS (LoadS src))); |
|
d7f654633cfe
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diff
changeset
|
10053 |
|
d7f654633cfe
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changeset
|
10054 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
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diff
changeset
|
10055 size(4); |
|
d7f654633cfe
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changeset
|
10056 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
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diff
changeset
|
10057 |
|
d7f654633cfe
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diff
changeset
|
10058 ins_encode %{ |
|
d7f654633cfe
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|
10059 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
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|
10060 %} |
| 0 | 10061 ins_pipe(iload_mem); |
| 10062 %} | |
| 10063 | |
| 10064 // Store Integer reversed byte order | |
|
1396
d7f654633cfe
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|
10065 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ |
| 0 | 10066 match(Set dst (StoreI dst (ReverseBytesI src))); |
| 10067 | |
| 10068 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
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changeset
|
10069 size(4); |
| 0 | 10070 format %{ "STWA $src, $dst\t!asi=primary_little" %} |
| 10071 | |
|
1396
d7f654633cfe
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|
10072 ins_encode %{ |
|
d7f654633cfe
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diff
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|
10073 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
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|
10074 %} |
| 0 | 10075 ins_pipe(istore_mem_reg); |
| 10076 %} | |
| 10077 | |
| 10078 // Store Long reversed byte order | |
|
1396
d7f654633cfe
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never
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|
10079 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ |
| 0 | 10080 match(Set dst (StoreL dst (ReverseBytesL src))); |
| 10081 | |
| 10082 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
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never
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changeset
|
10083 size(4); |
| 0 | 10084 format %{ "STXA $src, $dst\t!asi=primary_little" %} |
| 10085 | |
|
1396
d7f654633cfe
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never
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diff
changeset
|
10086 ins_encode %{ |
|
d7f654633cfe
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never
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diff
changeset
|
10087 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
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parents:
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diff
changeset
|
10088 %} |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
10089 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
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parents:
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diff
changeset
|
10090 %} |
|
d7f654633cfe
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never
parents:
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diff
changeset
|
10091 |
|
d7f654633cfe
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never
parents:
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diff
changeset
|
10092 // Store unsighed short/char reversed byte order |
|
d7f654633cfe
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never
parents:
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diff
changeset
|
10093 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
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never
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diff
changeset
|
10094 match(Set dst (StoreC dst (ReverseBytesUS src))); |
|
d7f654633cfe
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diff
changeset
|
10095 |
|
d7f654633cfe
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diff
changeset
|
10096 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
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diff
changeset
|
10097 size(4); |
|
d7f654633cfe
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diff
changeset
|
10098 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
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parents:
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diff
changeset
|
10099 |
|
d7f654633cfe
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diff
changeset
|
10100 ins_encode %{ |
|
d7f654633cfe
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diff
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|
10101 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
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|
10102 %} |
|
d7f654633cfe
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diff
changeset
|
10103 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
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diff
changeset
|
10104 %} |
|
d7f654633cfe
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diff
changeset
|
10105 |
|
d7f654633cfe
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diff
changeset
|
10106 // Store short reversed byte order |
|
d7f654633cfe
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never
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diff
changeset
|
10107 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
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never
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diff
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|
10108 match(Set dst (StoreC dst (ReverseBytesS src))); |
|
d7f654633cfe
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diff
changeset
|
10109 |
|
d7f654633cfe
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changeset
|
10110 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
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diff
changeset
|
10111 size(4); |
|
d7f654633cfe
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diff
changeset
|
10112 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
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never
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diff
changeset
|
10113 |
|
d7f654633cfe
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never
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diff
changeset
|
10114 ins_encode %{ |
|
d7f654633cfe
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never
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changeset
|
10115 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
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|
10116 %} |
| 0 | 10117 ins_pipe(istore_mem_reg); |
| 10118 %} | |
| 10119 | |
| 10120 //----------PEEPHOLE RULES----------------------------------------------------- | |
| 10121 // These must follow all instruction definitions as they use the names | |
| 10122 // defined in the instructions definitions. | |
| 10123 // | |
| 605 | 10124 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 10125 // |
| 10126 // peepconstraint %{ | |
| 10127 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 10128 // [, ...] ); | |
| 10129 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 10130 // | |
| 10131 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 10132 // // provide an instruction_number.operand_name for each operand that appears | |
| 10133 // // in the replacement instruction's match rule | |
| 10134 // | |
| 10135 // ---------VM FLAGS--------------------------------------------------------- | |
| 10136 // | |
| 10137 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 10138 // | |
| 10139 // Each peephole rule is given an identifying number starting with zero and | |
| 10140 // increasing by one in the order seen by the parser. An individual peephole | |
| 10141 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 10142 // on the command-line. | |
| 10143 // | |
| 10144 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 10145 // | |
| 10146 // Only match adjacent instructions in same basic block | |
| 10147 // Only equality constraints | |
| 10148 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 10149 // Only one replacement instruction | |
| 10150 // | |
| 10151 // ---------EXAMPLE---------------------------------------------------------- | |
| 10152 // | |
| 10153 // // pertinent parts of existing instructions in architecture description | |
| 10154 // instruct movI(eRegI dst, eRegI src) %{ | |
| 10155 // match(Set dst (CopyI src)); | |
| 10156 // %} | |
| 10157 // | |
| 10158 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 10159 // match(Set dst (AddI dst src)); | |
| 10160 // effect(KILL cr); | |
| 10161 // %} | |
| 10162 // | |
| 10163 // // Change (inc mov) to lea | |
| 10164 // peephole %{ | |
| 10165 // // increment preceeded by register-register move | |
| 10166 // peepmatch ( incI_eReg movI ); | |
| 10167 // // require that the destination register of the increment | |
| 10168 // // match the destination register of the move | |
| 10169 // peepconstraint ( 0.dst == 1.dst ); | |
| 10170 // // construct a replacement instruction that sets | |
| 10171 // // the destination to ( move's source register + one ) | |
| 10172 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
| 10173 // %} | |
| 10174 // | |
| 10175 | |
| 10176 // // Change load of spilled value to only a spill | |
| 10177 // instruct storeI(memory mem, eRegI src) %{ | |
| 10178 // match(Set mem (StoreI mem src)); | |
| 10179 // %} | |
| 10180 // | |
| 10181 // instruct loadI(eRegI dst, memory mem) %{ | |
| 10182 // match(Set dst (LoadI mem)); | |
| 10183 // %} | |
| 10184 // | |
| 10185 // peephole %{ | |
| 10186 // peepmatch ( loadI storeI ); | |
| 10187 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 10188 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 10189 // %} | |
| 10190 | |
| 10191 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 10192 // These must follow all instruction definitions as they use the names | |
| 10193 // defined in the instructions definitions. | |
| 10194 // | |
| 10195 // SPARC will probably not have any of these rules due to RISC instruction set. | |
| 10196 | |
| 10197 //----------PIPELINE----------------------------------------------------------- | |
| 10198 // Rules which define the behavior of the target architectures pipeline. |