Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sparc.ad @ 14440:41b780b43b74
8029015: PPC64 (part 216): opto: trap based null and range checks
Summary: On PPC64 use tdi instruction that does a compare and raises SIGTRAP for NULL and range checks.
Reviewed-by: kvn
| author | goetz |
|---|---|
| date | Wed, 27 Nov 2013 16:16:21 -0800 |
| parents | 50fdb38839eb |
| children | abec000618bf a9becfeecd1b |
| rev | line source |
|---|---|
| 0 | 1 // |
| 9154 | 2 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // SPARC Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 register %{ | |
| 32 //----------Architecture Description Register Definitions---------------------- | |
| 33 // General Registers | |
| 34 // "reg_def" name ( register save type, C convention save type, | |
| 35 // ideal register type, encoding, vm name ); | |
| 36 // Register Save Types: | |
| 37 // | |
| 38 // NS = No-Save: The register allocator assumes that these registers | |
| 39 // can be used without saving upon entry to the method, & | |
| 40 // that they do not need to be saved at call sites. | |
| 41 // | |
| 42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 43 // can be used without saving upon entry to the method, | |
| 44 // but that they must be saved at call sites. | |
| 45 // | |
| 46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 47 // must be saved before using them upon entry to the | |
| 48 // method, but they do not need to be saved at call | |
| 49 // sites. | |
| 50 // | |
| 51 // AS = Always-Save: The register allocator assumes that these registers | |
| 52 // must be saved before using them upon entry to the | |
| 53 // method, & that they must be saved at call sites. | |
| 54 // | |
| 55 // Ideal Register Type is used to determine how to save & restore a | |
| 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 58 // | |
| 59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 60 | |
| 61 | |
| 62 // ---------------------------- | |
| 63 // Integer/Long Registers | |
| 64 // ---------------------------- | |
| 65 | |
| 66 // Need to expose the hi/lo aspect of 64-bit registers | |
| 67 // This register set is used for both the 64-bit build and | |
| 68 // the 32-bit build with 1-register longs. | |
| 69 | |
| 70 // Global Registers 0-7 | |
| 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
| 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
| 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
| 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
| 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
| 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
| 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
| 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
| 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
| 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
| 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
| 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
| 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
| 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
| 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
| 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
| 87 | |
| 88 // Output Registers 0-7 | |
| 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
| 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
| 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
| 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
| 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
| 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
| 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
| 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
| 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
| 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
| 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
| 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
| 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
| 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
| 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
| 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
| 105 | |
| 106 // Local Registers 0-7 | |
| 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
| 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
| 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
| 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
| 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
| 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
| 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
| 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
| 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
| 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
| 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
| 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
| 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
| 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
| 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
| 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
| 123 | |
| 124 // Input Registers 0-7 | |
| 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
| 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
| 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
| 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
| 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
| 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
| 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
| 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
| 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
| 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
| 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
| 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
| 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
| 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
| 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
| 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
| 141 | |
| 142 // ---------------------------- | |
| 143 // Float/Double Registers | |
| 144 // ---------------------------- | |
| 145 | |
| 146 // Float Registers | |
| 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
| 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
| 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
| 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
| 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
| 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
| 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
| 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
| 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
| 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
| 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
| 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
| 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
| 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
| 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
| 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
| 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
| 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
| 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
| 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
| 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
| 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
| 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
| 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
| 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
| 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
| 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
| 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
| 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
| 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
| 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
| 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
| 179 | |
| 180 // Double Registers | |
| 181 // The rules of ADL require that double registers be defined in pairs. | |
| 182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
| 183 // single float registers. In each pair, ADLC-assigned register numbers | |
| 184 // must be adjacent, with the lower number even. Finally, when the | |
| 185 // CPU stores such a register pair to memory, the word associated with | |
| 186 // the lower ADLC-assigned number must be stored to the lower address. | |
| 187 | |
| 188 // These definitions specify the actual bit encodings of the sparc | |
| 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
| 190 // wants 0-63, so we have to convert every time we want to use fp regs | |
| 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
| 605 | 192 // 255 is a flag meaning "don't go here". |
| 0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
| 194 // the place in the sparc stack crawler that asserts on the 255 is | |
| 195 // fixed up. | |
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196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
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197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
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198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
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199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
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200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
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201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
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202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
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203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
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204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
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205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
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206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
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207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
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208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
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209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
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210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
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211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
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212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
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213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
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214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
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215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
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216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
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217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
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218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
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219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
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220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
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221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
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222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
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223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
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224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
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225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
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226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
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227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
| 0 | 228 |
| 229 | |
| 230 // ---------------------------- | |
| 231 // Special Registers | |
| 232 // Condition Codes Flag Registers | |
| 233 // I tried to break out ICC and XCC but it's not very pretty. | |
| 234 // Every Sparc instruction which defs/kills one also kills the other. | |
| 235 // Hence every compare instruction which defs one kind of flags ends | |
| 236 // up needing a kill of the other. | |
| 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 238 | |
| 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
| 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
| 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
| 243 | |
| 244 // ---------------------------- | |
| 245 // Specify the enum values for the registers. These enums are only used by the | |
| 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
| 247 // for visibility to the rest of the vm. The order of this enum influences the | |
| 248 // register allocator so having the freedom to set this order and not be stuck | |
| 249 // with the order that is natural for the rest of the vm is worth it. | |
| 250 alloc_class chunk0( | |
| 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
| 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
| 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
| 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
| 255 | |
| 256 // Note that a register is not allocatable unless it is also mentioned | |
| 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
| 258 | |
| 259 alloc_class chunk1( | |
| 260 // The first registers listed here are those most likely to be used | |
| 261 // as temporaries. We move F0..F7 away from the front of the list, | |
| 262 // to reduce the likelihood of interferences with parameters and | |
| 263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
| 264 // since they are used for return values. | |
| 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
| 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
| 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
| 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
| 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
| 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
| 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
| 274 | |
| 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
| 276 | |
| 277 //----------Architecture Description Register Classes-------------------------- | |
| 278 // Several register classes are automatically defined based upon information in | |
| 279 // this architecture description. | |
| 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
| 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
| 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 283 // | |
| 284 | |
| 285 // G0 is not included in integer class since it has special meaning. | |
| 286 reg_class g0_reg(R_G0); | |
| 287 | |
| 288 // ---------------------------- | |
| 289 // Integer Register Classes | |
| 290 // ---------------------------- | |
| 291 // Exclusions from i_reg: | |
| 292 // R_G0: hardwired zero | |
| 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
| 294 // R_G6: reserved by Solaris ABI to tools | |
| 295 // R_G7: reserved by Solaris ABI to libthread | |
| 296 // R_O7: Used as a temp in many encodings | |
| 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 298 | |
| 299 // Class for all integer registers, except the G registers. This is used for | |
| 300 // encodings which use G registers as temps. The regular inputs to such | |
| 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
| 302 // will not put an input into a temp register. | |
| 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 304 | |
| 305 reg_class g1_regI(R_G1); | |
| 306 reg_class g3_regI(R_G3); | |
| 307 reg_class g4_regI(R_G4); | |
| 308 reg_class o0_regI(R_O0); | |
| 309 reg_class o7_regI(R_O7); | |
| 310 | |
| 311 // ---------------------------- | |
| 312 // Pointer Register Classes | |
| 313 // ---------------------------- | |
| 314 #ifdef _LP64 | |
| 315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
| 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 320 // Lock encodings use G3 and G4 internally | |
| 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
| 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 326 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
| 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
| 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 332 // We use it to save R_G2 across calls out of Java. | |
| 333 reg_class l7_regP(R_L7H,R_L7); | |
| 334 | |
| 335 // Other special pointer regs | |
| 336 reg_class g1_regP(R_G1H,R_G1); | |
| 337 reg_class g2_regP(R_G2H,R_G2); | |
| 338 reg_class g3_regP(R_G3H,R_G3); | |
| 339 reg_class g4_regP(R_G4H,R_G4); | |
| 340 reg_class g5_regP(R_G5H,R_G5); | |
| 341 reg_class i0_regP(R_I0H,R_I0); | |
| 342 reg_class o0_regP(R_O0H,R_O0); | |
| 343 reg_class o1_regP(R_O1H,R_O1); | |
| 344 reg_class o2_regP(R_O2H,R_O2); | |
| 345 reg_class o7_regP(R_O7H,R_O7); | |
| 346 | |
| 347 #else // _LP64 | |
| 348 // 32-bit build means 32-bit pointers means 1 register. | |
| 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
| 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 353 // Lock encodings use G3 and G4 internally | |
| 354 reg_class lock_ptr_reg(R_G1, R_G5, | |
| 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 359 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
| 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
| 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
| 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 365 // We use it to save R_G2 across calls out of Java. | |
| 366 reg_class l7_regP(R_L7); | |
| 367 | |
| 368 // Other special pointer regs | |
| 369 reg_class g1_regP(R_G1); | |
| 370 reg_class g2_regP(R_G2); | |
| 371 reg_class g3_regP(R_G3); | |
| 372 reg_class g4_regP(R_G4); | |
| 373 reg_class g5_regP(R_G5); | |
| 374 reg_class i0_regP(R_I0); | |
| 375 reg_class o0_regP(R_O0); | |
| 376 reg_class o1_regP(R_O1); | |
| 377 reg_class o2_regP(R_O2); | |
| 378 reg_class o7_regP(R_O7); | |
| 379 #endif // _LP64 | |
| 380 | |
| 381 | |
| 382 // ---------------------------- | |
| 383 // Long Register Classes | |
| 384 // ---------------------------- | |
| 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
| 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
| 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
| 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
| 389 #ifdef _LP64 | |
| 390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
| 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
| 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
| 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
| 394 #endif // _LP64 | |
| 395 ); | |
| 396 | |
| 397 reg_class g1_regL(R_G1H,R_G1); | |
|
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398 reg_class g3_regL(R_G3H,R_G3); |
| 0 | 399 reg_class o2_regL(R_O2H,R_O2); |
| 400 reg_class o7_regL(R_O7H,R_O7); | |
| 401 | |
| 402 // ---------------------------- | |
| 403 // Special Class for Condition Code Flags Register | |
| 404 reg_class int_flags(CCR); | |
| 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
| 406 reg_class float_flag0(FCC0); | |
| 407 | |
| 408 | |
| 409 // ---------------------------- | |
| 410 // Float Point Register Classes | |
| 411 // ---------------------------- | |
| 412 // Skip F30/F31, they are reserved for mem-mem copies | |
| 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
| 414 | |
| 415 // Paired floating point registers--they show up in the same order as the floats, | |
| 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
| 419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
| 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
| 422 ); | |
| 423 | |
| 424 // Paired floating point registers--they show up in the same order as the floats, | |
| 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
| 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 3804 | 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); |
| 0 | 429 %} |
| 430 | |
| 431 //----------DEFINITION BLOCK--------------------------------------------------- | |
| 432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
| 433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
| 434 // Format: | |
| 435 // int_def <name> ( <int_value>, <expression>); | |
| 436 // Generated Code in ad_<arch>.hpp | |
| 437 // #define <name> (<expression>) | |
| 438 // // value == <int_value> | |
| 439 // Generated code in ad_<arch>.cpp adlc_verification() | |
| 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
| 441 // | |
| 442 definitions %{ | |
| 443 // The default cost (of an ALU instruction). | |
| 444 int_def DEFAULT_COST ( 100, 100); | |
| 445 int_def HUGE_COST (1000000, 1000000); | |
| 446 | |
| 447 // Memory refs are twice as expensive as run-of-the-mill. | |
| 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
| 449 | |
| 450 // Branches are even more expensive. | |
| 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
| 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
| 453 %} | |
| 454 | |
| 455 | |
| 456 //----------SOURCE BLOCK------------------------------------------------------- | |
| 457 // This is a block of C++ code which provides values, functions, and | |
| 458 // definitions necessary in the rest of the architecture description | |
| 459 source_hpp %{ | |
| 460 // Must be visible to the DFA in dfa_sparc.cpp | |
| 461 extern bool can_branch_register( Node *bol, Node *cmp ); | |
| 462 | |
| 3892 | 463 extern bool use_block_zeroing(Node* count); |
| 464 | |
| 0 | 465 // Macros to extract hi & lo halves from a long pair. |
| 466 // G0 is not part of any long pair, so assert on that. | |
| 605 | 467 // Prevents accidentally using G1 instead of G0. |
| 0 | 468 #define LONG_HI_REG(x) (x) |
| 469 #define LONG_LO_REG(x) (x) | |
| 470 | |
| 471 %} | |
| 472 | |
| 473 source %{ | |
| 474 #define __ _masm. | |
| 475 | |
| 476 // tertiary op of a LoadP or StoreP encoding | |
| 477 #define REGP_OP true | |
| 478 | |
| 479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
| 480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
| 481 static Register reg_to_register_object(int register_encoding); | |
| 482 | |
| 483 // Used by the DFA in dfa_sparc.cpp. | |
| 484 // Check for being able to use a V9 branch-on-register. Requires a | |
| 485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
| 486 // extended. Doesn't work following an integer ADD, for example, because of | |
| 487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
| 488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
| 489 // replace them with zero, which could become sign-extension in a different OS | |
| 490 // release. There's no obvious reason why an interrupt will ever fill these | |
| 491 // bits with non-zero junk (the registers are reloaded with standard LD | |
| 492 // instructions which either zero-fill or sign-fill). | |
| 493 bool can_branch_register( Node *bol, Node *cmp ) { | |
| 494 if( !BranchOnRegister ) return false; | |
| 495 #ifdef _LP64 | |
| 496 if( cmp->Opcode() == Op_CmpP ) | |
| 497 return true; // No problems with pointer compares | |
| 498 #endif | |
| 499 if( cmp->Opcode() == Op_CmpL ) | |
| 500 return true; // No problems with long compares | |
| 501 | |
| 502 if( !SparcV9RegsHiBitsZero ) return false; | |
| 503 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
| 504 bol->as_Bool()->_test._test != BoolTest::eq ) | |
| 505 return false; | |
| 506 | |
| 507 // Check for comparing against a 'safe' value. Any operation which | |
| 508 // clears out the high word is safe. Thus, loads and certain shifts | |
| 509 // are safe, as are non-negative constants. Any operation which | |
| 510 // preserves zero bits in the high word is safe as long as each of its | |
| 511 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
| 512 // inputs are safe. At present, the only important case to recognize | |
| 513 // seems to be loads. Constants should fold away, and shifts & | |
| 514 // logicals can use the 'cc' forms. | |
| 515 Node *x = cmp->in(1); | |
| 516 if( x->is_Load() ) return true; | |
| 517 if( x->is_Phi() ) { | |
| 518 for( uint i = 1; i < x->req(); i++ ) | |
| 519 if( !x->in(i)->is_Load() ) | |
| 520 return false; | |
| 521 return true; | |
| 522 } | |
| 523 return false; | |
| 524 } | |
| 525 | |
| 3892 | 526 bool use_block_zeroing(Node* count) { |
| 527 // Use BIS for zeroing if count is not constant | |
| 528 // or it is >= BlockZeroingLowLimit. | |
| 529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit); | |
| 530 } | |
| 531 | |
| 0 | 532 // **************************************************************************** |
| 533 | |
| 534 // REQUIRED FUNCTIONALITY | |
| 535 | |
| 536 // !!!!! Special hack to get all type of calls to specify the byte offset | |
| 537 // from the start of the call to the point where the return address | |
| 538 // will point. | |
| 539 // The "return address" is the address of the call instruction, plus 8. | |
| 540 | |
| 541 int MachCallStaticJavaNode::ret_addr_offset() { | |
| 1567 | 542 int offset = NativeCall::instruction_size; // call; delay slot |
| 543 if (_method_handle_invoke) | |
| 544 offset += 4; // restore SP | |
| 545 return offset; | |
| 0 | 546 } |
| 547 | |
| 548 int MachCallDynamicJavaNode::ret_addr_offset() { | |
| 549 int vtable_index = this->_vtable_index; | |
| 550 if (vtable_index < 0) { | |
| 551 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
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552 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
| 0 | 553 return (NativeMovConstReg::instruction_size + |
| 554 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
| 555 } else { | |
| 556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
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557 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
| 0 | 558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); |
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559 int klass_load_size; |
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560 if (UseCompressedClassPointers) { |
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561 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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562 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; |
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563 } else { |
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564 klass_load_size = 1*BytesPerInstWord; |
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565 } |
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566 if (Assembler::is_simm13(v_off)) { |
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567 return klass_load_size + |
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568 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
| 0 | 569 NativeCall::instruction_size); // call; delay slot |
| 570 } else { | |
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571 return klass_load_size + |
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572 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
| 0 | 573 NativeCall::instruction_size); // call; delay slot |
| 574 } | |
| 575 } | |
| 576 } | |
| 577 | |
| 578 int MachCallRuntimeNode::ret_addr_offset() { | |
| 579 #ifdef _LP64 | |
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580 if (MacroAssembler::is_far_target(entry_point())) { |
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581 return NativeFarCall::instruction_size; |
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582 } else { |
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583 return NativeCall::instruction_size; |
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584 } |
| 0 | 585 #else |
| 586 return NativeCall::instruction_size; // call; delay slot | |
| 587 #endif | |
| 588 } | |
| 589 | |
| 590 // Indicate if the safepoint node needs the polling page as an input. | |
| 591 // Since Sparc does not have absolute addressing, it does. | |
| 592 bool SafePointNode::needs_polling_address_input() { | |
| 593 return true; | |
| 594 } | |
| 595 | |
| 596 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
| 597 void emit_break(CodeBuffer &cbuf) { | |
| 598 MacroAssembler _masm(&cbuf); | |
| 599 __ breakpoint_trap(); | |
| 600 } | |
| 601 | |
| 602 #ifndef PRODUCT | |
| 603 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 604 st->print("TA"); | |
| 605 } | |
| 606 #endif | |
| 607 | |
| 608 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 609 emit_break(cbuf); | |
| 610 } | |
| 611 | |
| 612 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
| 613 return MachNode::size(ra_); | |
| 614 } | |
| 615 | |
| 616 // Traceable jump | |
| 617 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
| 618 MacroAssembler _masm(&cbuf); | |
| 619 Register rdest = reg_to_register_object(jump_target); | |
| 620 __ JMP(rdest, 0); | |
| 621 __ delayed()->nop(); | |
| 622 } | |
| 623 | |
| 624 // Traceable jump and set exception pc | |
| 625 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
| 626 MacroAssembler _masm(&cbuf); | |
| 627 Register rdest = reg_to_register_object(jump_target); | |
| 628 __ JMP(rdest, 0); | |
| 629 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
| 630 } | |
| 631 | |
| 632 void emit_nop(CodeBuffer &cbuf) { | |
| 633 MacroAssembler _masm(&cbuf); | |
| 634 __ nop(); | |
| 635 } | |
| 636 | |
| 637 void emit_illtrap(CodeBuffer &cbuf) { | |
| 638 MacroAssembler _masm(&cbuf); | |
| 639 __ illtrap(0); | |
| 640 } | |
| 641 | |
| 642 | |
| 643 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 644 assert(n->rule() != loadUB_rule, ""); | |
| 645 | |
| 646 intptr_t offset = 0; | |
| 647 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
| 648 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
| 649 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
| 650 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
| 651 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 652 atype = atype->add_offset(offset); | |
| 653 assert(disp32 == offset, "wrong disp32"); | |
| 654 return atype->_offset; | |
| 655 } | |
| 656 | |
| 657 | |
| 658 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 659 assert(n->rule() != loadUB_rule, ""); | |
| 660 | |
| 661 intptr_t offset = 0; | |
| 662 Node* addr = n->in(2); | |
| 663 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 664 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
| 665 Node* a = addr->in(2/*AddPNode::Address*/); | |
| 666 Node* o = addr->in(3/*AddPNode::Offset*/); | |
| 667 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
| 668 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
| 669 assert(atype->isa_oop_ptr(), "still an oop"); | |
| 670 } | |
| 671 offset = atype->is_ptr()->_offset; | |
| 672 if (offset != Type::OffsetBot) offset += disp32; | |
| 673 return offset; | |
| 674 } | |
| 675 | |
| 2008 | 676 static inline jdouble replicate_immI(int con, int count, int width) { |
| 677 // Load a constant replicated "count" times with width "width" | |
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678 assert(count*width == 8 && width <= 4, "sanity"); |
| 2008 | 679 int bit_width = width * 8; |
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680 jlong val = con; |
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681 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits |
| 2008 | 682 for (int i = 0; i < count - 1; i++) { |
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683 val |= (val << bit_width); |
| 2008 | 684 } |
| 685 jdouble dval = *((jdouble*) &val); // coerce to double type | |
| 686 return dval; | |
| 687 } | |
| 688 | |
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689 static inline jdouble replicate_immF(float con) { |
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690 // Replicate float con 2 times and pack into vector. |
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691 int val = *((int*)&con); |
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692 jlong lval = val; |
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693 lval = (lval << 32) | (lval & 0xFFFFFFFFl); |
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694 jdouble dval = *((jdouble*) &lval); // coerce to double type |
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695 return dval; |
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696 } |
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697 |
| 0 | 698 // Standard Sparc opcode form2 field breakdown |
| 699 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
| 700 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
| 701 int op = (f30 << 30) | | |
| 702 (f29 << 29) | | |
| 703 (f25 << 25) | | |
| 704 (f22 << 22) | | |
| 705 (f20 << 20) | | |
| 706 (f19 << 19) | | |
| 707 (f0 << 0); | |
| 1748 | 708 cbuf.insts()->emit_int32(op); |
| 0 | 709 } |
| 710 | |
| 711 // Standard Sparc opcode form2 field breakdown | |
| 712 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
| 713 f0 >>= 10; // Drop 10 bits | |
| 714 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
| 715 int op = (f30 << 30) | | |
| 716 (f25 << 25) | | |
| 717 (f22 << 22) | | |
| 718 (f0 << 0); | |
| 1748 | 719 cbuf.insts()->emit_int32(op); |
| 0 | 720 } |
| 721 | |
| 722 // Standard Sparc opcode form3 field breakdown | |
| 723 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
| 724 int op = (f30 << 30) | | |
| 725 (f25 << 25) | | |
| 726 (f19 << 19) | | |
| 727 (f14 << 14) | | |
| 728 (f5 << 5) | | |
| 729 (f0 << 0); | |
| 1748 | 730 cbuf.insts()->emit_int32(op); |
| 0 | 731 } |
| 732 | |
| 733 // Standard Sparc opcode form3 field breakdown | |
| 734 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
| 735 simm13 &= (1<<13)-1; // Mask to 13 bits | |
| 736 int op = (f30 << 30) | | |
| 737 (f25 << 25) | | |
| 738 (f19 << 19) | | |
| 739 (f14 << 14) | | |
| 740 (1 << 13) | // bit to indicate immediate-mode | |
| 741 (simm13<<0); | |
| 1748 | 742 cbuf.insts()->emit_int32(op); |
| 0 | 743 } |
| 744 | |
| 745 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
| 746 simm10 &= (1<<10)-1; // Mask to 10 bits | |
| 747 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
| 748 } | |
| 749 | |
| 750 #ifdef ASSERT | |
| 751 // Helper function for VerifyOops in emit_form3_mem_reg | |
| 752 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
| 753 warning("VerifyOops encountered unexpected instruction:"); | |
| 754 n->dump(2); | |
| 755 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
| 756 } | |
| 757 #endif | |
| 758 | |
| 759 | |
| 760 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
| 761 int src1_enc, int disp32, int src2_enc, int dst_enc) { | |
| 762 | |
| 763 #ifdef ASSERT | |
| 764 // The following code implements the +VerifyOops feature. | |
| 765 // It verifies oop values which are loaded into or stored out of | |
| 766 // the current method activation. +VerifyOops complements techniques | |
| 767 // like ScavengeALot, because it eagerly inspects oops in transit, | |
| 768 // as they enter or leave the stack, as opposed to ScavengeALot, | |
| 769 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
| 770 // For this reason, +VerifyOops can sometimes detect bugs very close | |
| 771 // to their point of creation. It can also serve as a cross-check | |
| 772 // on the validity of oop maps, when used toegether with ScavengeALot. | |
| 773 | |
| 774 // It would be good to verify oops at other points, especially | |
| 775 // when an oop is used as a base pointer for a load or store. | |
| 776 // This is presently difficult, because it is hard to know when | |
| 777 // a base address is biased or not. (If we had such information, | |
| 778 // it would be easy and useful to make a two-argument version of | |
| 779 // verify_oop which unbiases the base, and performs verification.) | |
| 780 | |
| 781 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
| 782 bool is_verified_oop_base = false; | |
| 783 bool is_verified_oop_load = false; | |
| 784 bool is_verified_oop_store = false; | |
| 785 int tmp_enc = -1; | |
| 786 if (VerifyOops && src1_enc != R_SP_enc) { | |
| 787 // classify the op, mainly for an assert check | |
| 788 int st_op = 0, ld_op = 0; | |
| 789 switch (primary) { | |
| 790 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
| 791 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
| 792 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
| 793 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
| 794 case Assembler::std_op3: st_op = Op_StoreL; break; | |
| 795 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
| 796 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
| 797 | |
| 798 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
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799 case Assembler::ldub_op3: ld_op = Op_LoadUB; break; |
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800 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
| 0 | 801 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
| 802 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
| 803 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
| 804 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
| 805 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
| 806 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
| 807 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
| 808 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
| 809 | |
| 810 default: ShouldNotReachHere(); | |
| 811 } | |
| 812 if (tertiary == REGP_OP) { | |
| 813 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
| 814 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
| 815 else ShouldNotReachHere(); | |
| 816 if (st_op) { | |
| 817 // a store | |
| 818 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 819 Node* n2 = n->in(3); | |
| 820 if (n2 != NULL) { | |
| 821 const Type* t = n2->bottom_type(); | |
| 822 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 823 } | |
| 824 } else { | |
| 825 // a load | |
| 826 const Type* t = n->bottom_type(); | |
| 827 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 828 } | |
| 829 } | |
| 830 | |
| 831 if (ld_op) { | |
| 832 // a Load | |
| 833 // inputs are (0:control, 1:memory, 2:address) | |
| 834 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
| 835 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
| 836 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
| 837 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
| 838 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
| 839 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
| 840 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
| 841 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
| 842 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
| 843 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
| 844 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
| 845 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
| 846 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
| 3898 | 847 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) && |
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848 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) && |
| 0 | 849 !(n->rule() == loadUB_rule)) { |
| 850 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
| 851 } | |
| 852 } else if (st_op) { | |
| 853 // a Store | |
| 854 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 855 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
| 856 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
| 857 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
| 858 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
| 859 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
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860 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) && |
| 0 | 861 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { |
| 862 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
| 863 } | |
| 864 } | |
| 865 | |
| 866 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
| 867 Node* addr = n->in(2); | |
| 868 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
| 869 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
| 870 if (atype != NULL) { | |
| 871 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
| 872 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
| 873 if (offset != offset_2) { | |
| 874 get_offset_from_base(n, atype, disp32); | |
| 875 get_offset_from_base_2(n, atype, disp32); | |
| 876 } | |
| 877 assert(offset == offset_2, "different offsets"); | |
| 878 if (offset == disp32) { | |
| 879 // we now know that src1 is a true oop pointer | |
| 880 is_verified_oop_base = true; | |
| 881 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
| 882 if( primary == Assembler::ldd_op3 ) { | |
| 883 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
| 884 } else { | |
| 885 tmp_enc = dst_enc; | |
| 886 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
| 887 assert(src1_enc != dst_enc, ""); | |
| 888 } | |
| 889 } | |
| 890 } | |
| 891 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
| 892 || offset == oopDesc::mark_offset_in_bytes())) { | |
| 893 // loading the mark should not be allowed either, but | |
| 894 // we don't check this since it conflicts with InlineObjectHash | |
| 895 // usage of LoadINode to get the mark. We could keep the | |
| 896 // check if we create a new LoadMarkNode | |
| 897 // but do not verify the object before its header is initialized | |
| 898 ShouldNotReachHere(); | |
| 899 } | |
| 900 } | |
| 901 } | |
| 902 } | |
| 903 } | |
| 904 #endif | |
| 905 | |
| 906 uint instr; | |
| 907 instr = (Assembler::ldst_op << 30) | |
| 908 | (dst_enc << 25) | |
| 909 | (primary << 19) | |
| 910 | (src1_enc << 14); | |
| 911 | |
| 912 uint index = src2_enc; | |
| 913 int disp = disp32; | |
| 914 | |
| 915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
| 916 disp += STACK_BIAS; | |
| 917 | |
| 918 // We should have a compiler bailout here rather than a guarantee. | |
| 919 // Better yet would be some mechanism to handle variable-size matches correctly. | |
| 920 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
| 921 | |
| 922 if( disp == 0 ) { | |
| 923 // use reg-reg form | |
| 924 // bit 13 is already zero | |
| 925 instr |= index; | |
| 926 } else { | |
| 927 // use reg-imm form | |
| 928 instr |= 0x00002000; // set bit 13 to one | |
| 929 instr |= disp & 0x1FFF; | |
| 930 } | |
| 931 | |
| 1748 | 932 cbuf.insts()->emit_int32(instr); |
| 0 | 933 |
| 934 #ifdef ASSERT | |
| 935 { | |
| 936 MacroAssembler _masm(&cbuf); | |
| 937 if (is_verified_oop_base) { | |
| 938 __ verify_oop(reg_to_register_object(src1_enc)); | |
| 939 } | |
| 940 if (is_verified_oop_store) { | |
| 941 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 942 } | |
| 943 if (tmp_enc != -1) { | |
| 944 __ mov(O7, reg_to_register_object(tmp_enc)); | |
| 945 } | |
| 946 if (is_verified_oop_load) { | |
| 947 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 948 } | |
| 949 } | |
| 950 #endif | |
| 951 } | |
| 952 | |
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953 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) { |
| 0 | 954 // The method which records debug information at every safepoint |
| 955 // expects the call to be the first instruction in the snippet as | |
| 956 // it creates a PcDesc structure which tracks the offset of a call | |
| 957 // from the start of the codeBlob. This offset is computed as | |
| 958 // code_end() - code_begin() of the code which has been emitted | |
| 959 // so far. | |
| 960 // In this particular case we have skirted around the problem by | |
| 961 // putting the "mov" instruction in the delay slot but the problem | |
| 962 // may bite us again at some other point and a cleaner/generic | |
| 963 // solution using relocations would be needed. | |
| 964 MacroAssembler _masm(&cbuf); | |
| 965 __ set_inst_mark(); | |
| 966 | |
| 967 // We flush the current window just so that there is a valid stack copy | |
| 968 // the fact that the current window becomes active again instantly is | |
| 969 // not a problem there is nothing live in it. | |
| 970 | |
| 971 #ifdef ASSERT | |
| 972 int startpos = __ offset(); | |
| 973 #endif /* ASSERT */ | |
| 974 | |
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975 __ call((address)entry_point, rtype); |
| 0 | 976 |
| 977 if (preserve_g2) __ delayed()->mov(G2, L7); | |
| 978 else __ delayed()->nop(); | |
| 979 | |
| 980 if (preserve_g2) __ mov(L7, G2); | |
| 981 | |
| 982 #ifdef ASSERT | |
| 983 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
| 984 #ifdef _LP64 | |
| 985 // Trash argument dump slots. | |
| 986 __ set(0xb0b8ac0db0b8ac0d, G1); | |
| 987 __ mov(G1, G5); | |
| 988 __ stx(G1, SP, STACK_BIAS + 0x80); | |
| 989 __ stx(G1, SP, STACK_BIAS + 0x88); | |
| 990 __ stx(G1, SP, STACK_BIAS + 0x90); | |
| 991 __ stx(G1, SP, STACK_BIAS + 0x98); | |
| 992 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
| 993 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
| 994 #else // _LP64 | |
| 995 // this is also a native call, so smash the first 7 stack locations, | |
| 996 // and the various registers | |
| 997 | |
| 998 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
| 999 // while [SP+0x44..0x58] are the argument dump slots. | |
| 1000 __ set((intptr_t)0xbaadf00d, G1); | |
| 1001 __ mov(G1, G5); | |
| 1002 __ sllx(G1, 32, G1); | |
| 1003 __ or3(G1, G5, G1); | |
| 1004 __ mov(G1, G5); | |
| 1005 __ stx(G1, SP, 0x40); | |
| 1006 __ stx(G1, SP, 0x48); | |
| 1007 __ stx(G1, SP, 0x50); | |
| 1008 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
| 1009 #endif // _LP64 | |
| 1010 } | |
| 1011 #endif /*ASSERT*/ | |
| 1012 } | |
| 1013 | |
| 1014 //============================================================================= | |
| 1015 // REQUIRED FUNCTIONALITY for encoding | |
| 1016 void emit_lo(CodeBuffer &cbuf, int val) { } | |
| 1017 void emit_hi(CodeBuffer &cbuf, int val) { } | |
| 1018 | |
| 1019 | |
| 1020 //============================================================================= | |
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1021 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask(); |
| 2008 | 1022 |
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1023 int Compile::ConstantTable::calculate_table_base_offset() const { |
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1024 if (UseRDPCForConstantTableBase) { |
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1025 // The table base offset might be less but then it fits into |
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1026 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit). |
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1027 return Assembler::min_simm13(); |
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1028 } else { |
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1029 int offset = -(size() / 2); |
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1030 if (!Assembler::is_simm13(offset)) { |
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1031 offset = Assembler::min_simm13(); |
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1032 } |
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1033 return offset; |
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1034 } |
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1035 } |
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1036 |
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1037 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } |
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1038 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { |
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1039 ShouldNotReachHere(); |
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1040 } |
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1041 |
| 2008 | 1042 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 1043 Compile* C = ra_->C; | |
| 1044 Compile::ConstantTable& constant_table = C->constant_table(); | |
| 1045 MacroAssembler _masm(&cbuf); | |
| 1046 | |
| 1047 Register r = as_Register(ra_->get_encode(this)); | |
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1048 CodeSection* consts_section = __ code()->consts(); |
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1049 int consts_size = consts_section->align_at_start(consts_section->size()); |
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1050 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); |
| 2008 | 1051 |
| 1052 if (UseRDPCForConstantTableBase) { | |
| 1053 // For the following RDPC logic to work correctly the consts | |
| 1054 // section must be allocated right before the insts section. This | |
| 1055 // assert checks for that. The layout and the SECT_* constants | |
| 1056 // are defined in src/share/vm/asm/codeBuffer.hpp. | |
| 1057 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); | |
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1058 int insts_offset = __ offset(); |
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1059 |
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1060 // Layout: |
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1061 // |
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1062 // |----------- consts section ------------|----------- insts section -----------... |
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1063 // |------ constant table -----|- padding -|------------------x---- |
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1064 // \ current PC (RDPC instruction) |
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1065 // |<------------- consts_size ----------->|<- insts_offset ->| |
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1066 // \ table base |
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1067 // The table base offset is later added to the load displacement |
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1068 // so it has to be negative. |
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1069 int table_base_offset = -(consts_size + insts_offset); |
| 2008 | 1070 int disp; |
| 1071 | |
| 1072 // If the displacement from the current PC to the constant table | |
| 1073 // base fits into simm13 we set the constant table base to the | |
| 1074 // current PC. | |
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1075 if (Assembler::is_simm13(table_base_offset)) { |
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1076 constant_table.set_table_base_offset(table_base_offset); |
| 2008 | 1077 disp = 0; |
| 1078 } else { | |
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1079 // Otherwise we set the constant table base offset to the |
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1080 // maximum negative displacement of load instructions to keep |
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1081 // the disp as small as possible: |
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1082 // |
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1083 // |<------------- consts_size ----------->|<- insts_offset ->| |
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1084 // |<--------- min_simm13 --------->|<-------- disp --------->| |
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1085 // \ table base |
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1086 table_base_offset = Assembler::min_simm13(); |
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1087 constant_table.set_table_base_offset(table_base_offset); |
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1088 disp = (consts_size + insts_offset) + table_base_offset; |
| 2008 | 1089 } |
| 1090 | |
| 1091 __ rdpc(r); | |
| 1092 | |
| 1093 if (disp != 0) { | |
| 1094 assert(r != O7, "need temporary"); | |
| 1095 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); | |
| 1096 } | |
| 1097 } | |
| 1098 else { | |
| 1099 // Materialize the constant table base. | |
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1100 address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); |
| 2008 | 1101 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); |
| 1102 AddressLiteral base(baseaddr, rspec); | |
| 1103 __ set(base, r); | |
| 1104 } | |
| 1105 } | |
| 1106 | |
| 1107 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { | |
| 1108 if (UseRDPCForConstantTableBase) { | |
| 1109 // This is really the worst case but generally it's only 1 instruction. | |
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1110 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; |
| 2008 | 1111 } else { |
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1112 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; |
| 2008 | 1113 } |
| 1114 } | |
| 1115 | |
| 1116 #ifndef PRODUCT | |
| 1117 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 1118 char reg[128]; | |
| 1119 ra_->dump_register(this, reg); | |
| 1120 if (UseRDPCForConstantTableBase) { | |
| 1121 st->print("RDPC %s\t! constant table base", reg); | |
| 1122 } else { | |
| 1123 st->print("SET &constanttable,%s\t! constant table base", reg); | |
| 1124 } | |
| 1125 } | |
| 1126 #endif | |
| 1127 | |
| 1128 | |
| 1129 //============================================================================= | |
| 0 | 1130 |
| 1131 #ifndef PRODUCT | |
| 1132 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1133 Compile* C = ra_->C; | |
| 1134 | |
| 1135 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1136 st->print_cr("NOP"); st->print("\t"); | |
| 1137 } | |
| 1138 | |
| 1139 if( VerifyThread ) { | |
| 1140 st->print_cr("Verify_Thread"); st->print("\t"); | |
| 1141 } | |
| 1142 | |
| 1143 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1144 | |
| 1145 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1146 // We require that their callers must bang for them. But be careful, because | |
| 1147 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1148 // stack. But the stack safety zone should account for that. | |
| 1149 // See bugs 4446381, 4468289, 4497237. | |
| 1150 if (C->need_stack_bang(framesize)) { | |
| 1151 st->print_cr("! stack bang"); st->print("\t"); | |
| 1152 } | |
| 1153 | |
| 1154 if (Assembler::is_simm13(-framesize)) { | |
| 1155 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
| 1156 } else { | |
| 1157 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1158 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1159 st->print ("SAVE R_SP,R_G3,R_SP"); | |
| 1160 } | |
| 1161 | |
| 1162 } | |
| 1163 #endif | |
| 1164 | |
| 1165 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1166 Compile* C = ra_->C; | |
| 1167 MacroAssembler _masm(&cbuf); | |
| 1168 | |
| 1169 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1170 __ nop(); | |
| 1171 } | |
| 1172 | |
| 1173 __ verify_thread(); | |
| 1174 | |
| 1175 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1176 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
| 1177 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
| 1178 | |
| 1179 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1180 // We require that their callers must bang for them. But be careful, because | |
| 1181 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1182 // stack. But the stack safety zone should account for that. | |
| 1183 // See bugs 4446381, 4468289, 4497237. | |
| 1184 if (C->need_stack_bang(framesize)) { | |
| 1185 __ generate_stack_overflow_check(framesize); | |
| 1186 } | |
| 1187 | |
| 1188 if (Assembler::is_simm13(-framesize)) { | |
| 1189 __ save(SP, -framesize, SP); | |
| 1190 } else { | |
| 1191 __ sethi(-framesize & ~0x3ff, G3); | |
| 1192 __ add(G3, -framesize & 0x3ff, G3); | |
| 1193 __ save(SP, G3, SP); | |
| 1194 } | |
| 1195 C->set_frame_complete( __ offset() ); | |
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1196 |
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1197 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) { |
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1198 // NOTE: We set the table base offset here because users might be |
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1199 // emitted before MachConstantBaseNode. |
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1200 Compile::ConstantTable& constant_table = C->constant_table(); |
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1201 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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1202 } |
| 0 | 1203 } |
| 1204 | |
| 1205 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 1206 return MachNode::size(ra_); | |
| 1207 } | |
| 1208 | |
| 1209 int MachPrologNode::reloc() const { | |
| 1210 return 10; // a large enough number | |
| 1211 } | |
| 1212 | |
| 1213 //============================================================================= | |
| 1214 #ifndef PRODUCT | |
| 1215 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1216 Compile* C = ra_->C; | |
| 1217 | |
| 1218 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 1219 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
| 1220 #ifdef _LP64 | |
| 1221 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1222 #else | |
| 1223 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1224 #endif | |
| 1225 } | |
| 1226 | |
| 1227 if( do_polling() ) | |
| 1228 st->print("RET\n\t"); | |
| 1229 | |
| 1230 st->print("RESTORE"); | |
| 1231 } | |
| 1232 #endif | |
| 1233 | |
| 1234 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1235 MacroAssembler _masm(&cbuf); | |
| 1236 Compile* C = ra_->C; | |
| 1237 | |
| 1238 __ verify_thread(); | |
| 1239 | |
| 1240 // If this does safepoint polling, then do it here | |
| 1241 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 727 | 1242 AddressLiteral polling_page(os::get_polling_page()); |
| 1243 __ sethi(polling_page, L0); | |
| 0 | 1244 __ relocate(relocInfo::poll_return_type); |
| 1245 __ ld_ptr( L0, 0, G0 ); | |
| 1246 } | |
| 1247 | |
| 1248 // If this is a return, then stuff the restore in the delay slot | |
| 1249 if( do_polling() ) { | |
| 1250 __ ret(); | |
| 1251 __ delayed()->restore(); | |
| 1252 } else { | |
| 1253 __ restore(); | |
| 1254 } | |
| 1255 } | |
| 1256 | |
| 1257 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 1258 return MachNode::size(ra_); | |
| 1259 } | |
| 1260 | |
| 1261 int MachEpilogNode::reloc() const { | |
| 1262 return 16; // a large enough number | |
| 1263 } | |
| 1264 | |
| 1265 const Pipeline * MachEpilogNode::pipeline() const { | |
| 1266 return MachNode::pipeline_class(); | |
| 1267 } | |
| 1268 | |
| 1269 int MachEpilogNode::safepoint_offset() const { | |
| 1270 assert( do_polling(), "no return for this epilog node"); | |
|
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7006044: materialize cheap non-oop pointers on 64-bit SPARC
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|
1271 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; |
| 0 | 1272 } |
| 1273 | |
| 1274 //============================================================================= | |
| 1275 | |
| 1276 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
| 1277 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
| 1278 static enum RC rc_class( OptoReg::Name reg ) { | |
| 1279 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 1280 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 1281 VMReg r = OptoReg::as_VMReg(reg); | |
| 1282 if (r->is_Register()) return rc_int; | |
| 1283 assert(r->is_FloatRegister(), "must be"); | |
| 1284 return rc_float; | |
| 1285 } | |
| 1286 | |
| 1287 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { | |
| 1288 if( cbuf ) { | |
| 1289 // Better yet would be some mechanism to handle variable-size matches correctly | |
| 1290 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
| 1291 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
| 1292 } else { | |
| 1293 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
| 1294 } | |
| 1295 } | |
| 1296 #ifndef PRODUCT | |
| 1297 else if( !do_size ) { | |
| 1298 if( size != 0 ) st->print("\n\t"); | |
| 1299 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | |
| 1300 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | |
| 1301 } | |
| 1302 #endif | |
| 1303 return size+4; | |
| 1304 } | |
| 1305 | |
| 1306 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
| 1307 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
| 1308 #ifndef PRODUCT | |
| 1309 else if( !do_size ) { | |
| 1310 if( size != 0 ) st->print("\n\t"); | |
| 1311 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
| 1312 } | |
| 1313 #endif | |
| 1314 return size+4; | |
| 1315 } | |
| 1316 | |
| 1317 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
| 1318 PhaseRegAlloc *ra_, | |
| 1319 bool do_size, | |
| 1320 outputStream* st ) const { | |
| 1321 // Get registers to move | |
| 1322 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1323 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1324 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 1325 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 1326 | |
| 1327 enum RC src_second_rc = rc_class(src_second); | |
| 1328 enum RC src_first_rc = rc_class(src_first); | |
| 1329 enum RC dst_second_rc = rc_class(dst_second); | |
| 1330 enum RC dst_first_rc = rc_class(dst_first); | |
| 1331 | |
| 1332 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 1333 | |
| 1334 // Generate spill code! | |
| 1335 int size = 0; | |
| 1336 | |
| 1337 if( src_first == dst_first && src_second == dst_second ) | |
| 1338 return size; // Self copy, no move | |
| 1339 | |
| 1340 // -------------------------------------- | |
| 1341 // Check for mem-mem move. Load into unused float registers and fall into | |
| 1342 // the float-store case. | |
| 1343 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1344 int offset = ra_->reg2offset(src_first); | |
| 1345 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1346 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
| 1347 src_second = OptoReg::Name(R_F31_num); | |
| 1348 src_second_rc = rc_float; | |
| 1349 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
| 1350 } else { | |
| 1351 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1352 } | |
| 1353 src_first = OptoReg::Name(R_F30_num); | |
| 1354 src_first_rc = rc_float; | |
| 1355 } | |
| 1356 | |
| 1357 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
| 1358 int offset = ra_->reg2offset(src_second); | |
| 1359 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
| 1360 src_second = OptoReg::Name(R_F31_num); | |
| 1361 src_second_rc = rc_float; | |
| 1362 } | |
| 1363 | |
| 1364 // -------------------------------------- | |
| 1365 // Check for float->int copy; requires a trip through memory | |
| 3804 | 1366 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { |
| 0 | 1367 int offset = frame::register_save_words*wordSize; |
| 3804 | 1368 if (cbuf) { |
| 0 | 1369 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); |
| 1370 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1371 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1372 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
| 1373 } | |
| 1374 #ifndef PRODUCT | |
| 3804 | 1375 else if (!do_size) { |
| 1376 if (size != 0) st->print("\n\t"); | |
| 0 | 1377 st->print( "SUB R_SP,16,R_SP\n"); |
| 1378 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1379 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1380 st->print("\tADD R_SP,16,R_SP\n"); | |
| 1381 } | |
| 1382 #endif | |
| 1383 size += 16; | |
| 1384 } | |
| 1385 | |
| 3804 | 1386 // Check for float->int copy on T4 |
| 1387 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { | |
| 1388 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1389 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
| 1390 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st); | |
| 1391 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st); | |
| 1392 } | |
| 1393 // Check for int->float copy on T4 | |
| 1394 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { | |
| 1395 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1396 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
| 1397 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st); | |
| 1398 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st); | |
| 1399 } | |
| 1400 | |
| 0 | 1401 // -------------------------------------- |
| 1402 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
| 1403 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
| 1404 // hardware does the flop for me. Doubles are always aligned, so no problem | |
| 1405 // there. Misaligned sources only come from native-long-returns (handled | |
| 1406 // special below). | |
| 1407 #ifndef _LP64 | |
| 1408 if( src_first_rc == rc_int && // source is already big-endian | |
| 1409 src_second_rc != rc_bad && // 64-bit move | |
| 1410 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
| 1411 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
| 1412 // Do the big-endian flop. | |
| 1413 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
| 1414 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
| 1415 } | |
| 1416 #endif | |
| 1417 | |
| 1418 // -------------------------------------- | |
| 1419 // Check for integer reg-reg copy | |
| 1420 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
| 1421 #ifndef _LP64 | |
| 1422 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
| 1423 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1424 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1425 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1426 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
| 1427 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
| 1428 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
| 1429 if( cbuf ) { | |
| 1430 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
| 1431 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
| 1432 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
| 1433 #ifndef PRODUCT | |
| 1434 } else if( !do_size ) { | |
| 1435 if( size != 0 ) st->print("\n\t"); | |
| 1436 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
| 1437 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
| 1438 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
| 1439 #endif | |
| 1440 } | |
| 1441 return size+12; | |
| 1442 } | |
| 1443 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
| 1444 // returning a long value in I0/I1 | |
| 1445 // a SpillCopy must be able to target a return instruction's reg_class | |
| 1446 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1447 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1448 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1449 OptoReg::Name tdest = dst_first; | |
| 1450 | |
| 1451 if (src_first == dst_first) { | |
| 1452 tdest = OptoReg::Name(R_O7_num); | |
| 1453 size += 4; | |
| 1454 } | |
| 1455 | |
| 1456 if( cbuf ) { | |
| 1457 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
| 1458 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
| 1459 // ShrL_reg_imm6 | |
| 1460 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
| 1461 // ShrR_reg_imm6 src, 0, dst | |
| 1462 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
| 1463 if (tdest != dst_first) { | |
| 1464 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
| 1465 } | |
| 1466 } | |
| 1467 #ifndef PRODUCT | |
| 1468 else if( !do_size ) { | |
| 1469 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
| 1470 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
| 1471 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
| 1472 if (tdest != dst_first) { | |
| 1473 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
| 1474 } | |
| 1475 } | |
| 1476 #endif // PRODUCT | |
| 1477 return size+8; | |
| 1478 } | |
| 1479 #endif // !_LP64 | |
| 1480 // Else normal reg-reg copy | |
| 1481 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
| 1482 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
| 1483 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
| 1484 // This moves an aligned adjacent pair. | |
| 1485 // See if we are done. | |
| 1486 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
| 1487 return size; | |
| 1488 } | |
| 1489 | |
| 1490 // Check for integer store | |
| 1491 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
| 1492 int offset = ra_->reg2offset(dst_first); | |
| 1493 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1494 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1495 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
| 1496 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
| 1497 } | |
| 1498 | |
| 1499 // Check for integer load | |
| 1500 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
| 1501 int offset = ra_->reg2offset(src_first); | |
| 1502 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1503 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1504 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
| 1505 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1506 } | |
| 1507 | |
| 1508 // Check for float reg-reg copy | |
| 1509 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1510 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1511 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1512 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
| 1513 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
| 1514 } | |
| 1515 | |
| 1516 // Check for float store | |
| 1517 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
| 1518 int offset = ra_->reg2offset(dst_first); | |
| 1519 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1520 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1521 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
| 1522 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1523 } | |
| 1524 | |
| 1525 // Check for float load | |
| 1526 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1527 int offset = ra_->reg2offset(src_first); | |
| 1528 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1529 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1530 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
| 1531 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1532 } | |
| 1533 | |
| 1534 // -------------------------------------------------------------------- | |
| 1535 // Check for hi bits still needing moving. Only happens for misaligned | |
| 1536 // arguments to native calls. | |
| 1537 if( src_second == dst_second ) | |
| 1538 return size; // Self copy; no move | |
| 1539 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1540 | |
| 1541 #ifndef _LP64 | |
| 1542 // In the LP64 build, all registers can be moved as aligned/adjacent | |
| 605 | 1543 // pairs, so there's never any need to move the high bits separately. |
| 0 | 1544 // The 32-bit builds have to deal with the 32-bit ABI which can force |
| 1545 // all sorts of silly alignment problems. | |
| 1546 | |
| 1547 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
| 1548 // 32-bits of a 64-bit register, but are needed in low bits of another | |
| 1549 // register (else it's a hi-bits-to-hi-bits copy which should have | |
| 1550 // happened already as part of a 64-bit move) | |
| 1551 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
| 1552 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
| 1553 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
| 1554 // Shift src_second down to dst_second's low bits. | |
| 1555 if( cbuf ) { | |
| 1556 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1557 #ifndef PRODUCT | |
| 1558 } else if( !do_size ) { | |
| 1559 if( size != 0 ) st->print("\n\t"); | |
| 1560 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
| 1561 #endif | |
| 1562 } | |
| 1563 return size+4; | |
| 1564 } | |
| 1565 | |
| 1566 // Check for high word integer store. Must down-shift the hi bits | |
| 1567 // into a temp register, then fall into the case of storing int bits. | |
| 1568 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
| 1569 // Shift src_second down to dst_second's low bits. | |
| 1570 if( cbuf ) { | |
| 1571 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1572 #ifndef PRODUCT | |
| 1573 } else if( !do_size ) { | |
| 1574 if( size != 0 ) st->print("\n\t"); | |
| 1575 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
| 1576 #endif | |
| 1577 } | |
| 1578 size+=4; | |
| 1579 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
| 1580 } | |
| 1581 | |
| 1582 // Check for high word integer load | |
| 1583 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
| 1584 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
| 1585 | |
| 1586 // Check for high word integer store | |
| 1587 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
| 1588 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
| 1589 | |
| 1590 // Check for high word float store | |
| 1591 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
| 1592 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
| 1593 | |
| 1594 #endif // !_LP64 | |
| 1595 | |
| 1596 Unimplemented(); | |
| 1597 } | |
| 1598 | |
| 1599 #ifndef PRODUCT | |
| 1600 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1601 implementation( NULL, ra_, false, st ); | |
| 1602 } | |
| 1603 #endif | |
| 1604 | |
| 1605 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1606 implementation( &cbuf, ra_, false, NULL ); | |
| 1607 } | |
| 1608 | |
| 1609 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1610 return implementation( NULL, ra_, true, NULL ); | |
| 1611 } | |
| 1612 | |
| 1613 //============================================================================= | |
| 1614 #ifndef PRODUCT | |
| 1615 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 1616 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
| 1617 } | |
| 1618 #endif | |
| 1619 | |
| 1620 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
| 1621 MacroAssembler _masm(&cbuf); | |
| 1622 for(int i = 0; i < _count; i += 1) { | |
| 1623 __ nop(); | |
| 1624 } | |
| 1625 } | |
| 1626 | |
| 1627 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
| 1628 return 4 * _count; | |
| 1629 } | |
| 1630 | |
| 1631 | |
| 1632 //============================================================================= | |
| 1633 #ifndef PRODUCT | |
| 1634 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1635 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1636 int reg = ra_->get_reg_first(this); | |
| 1637 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
| 1638 } | |
| 1639 #endif | |
| 1640 | |
| 1641 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1642 MacroAssembler _masm(&cbuf); | |
| 1643 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
| 1644 int reg = ra_->get_encode(this); | |
| 1645 | |
| 1646 if (Assembler::is_simm13(offset)) { | |
| 1647 __ add(SP, offset, reg_to_register_object(reg)); | |
| 1648 } else { | |
| 1649 __ set(offset, O7); | |
| 1650 __ add(SP, O7, reg_to_register_object(reg)); | |
| 1651 } | |
| 1652 } | |
| 1653 | |
| 1654 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1655 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
| 1656 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
| 1657 return ra_->C->scratch_emit_size(this); | |
| 1658 } | |
| 1659 | |
| 1660 //============================================================================= | |
| 1661 #ifndef PRODUCT | |
| 1662 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1663 st->print_cr("\nUEP:"); | |
| 1664 #ifdef _LP64 | |
|
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1665 if (UseCompressedClassPointers) { |
|
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1666 assert(Universe::heap() != NULL, "java heap should be initialized"); |
|
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1667 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
|
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1668 if (Universe::narrow_klass_base() != 0) { |
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1669 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base"); |
|
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1670 if (Universe::narrow_klass_shift() != 0) { |
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1671 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); |
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1672 } |
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1673 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
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1674 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base"); |
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1675 } else { |
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1676 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); |
|
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1677 } |
|
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1678 } else { |
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1679 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
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1680 } |
| 0 | 1681 st->print_cr("\tCMP R_G5,R_G3" ); |
| 1682 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1683 #else // _LP64 | |
| 1684 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
| 1685 st->print_cr("\tCMP R_G5,R_G3" ); | |
| 1686 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1687 #endif // _LP64 | |
| 1688 } | |
| 1689 #endif | |
| 1690 | |
| 1691 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1692 MacroAssembler _masm(&cbuf); | |
| 1693 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 1694 Register temp_reg = G3; | |
| 1695 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
| 1696 | |
| 605 | 1697 // Load klass from receiver |
|
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1698 __ load_klass(O0, temp_reg); |
| 0 | 1699 // Compare against expected klass |
| 1700 __ cmp(temp_reg, G5_ic_reg); | |
| 1701 // Branch to miss code, checks xcc or icc depending | |
| 1702 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
| 1703 } | |
| 1704 | |
| 1705 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1706 return MachNode::size(ra_); | |
| 1707 } | |
| 1708 | |
| 1709 | |
| 1710 //============================================================================= | |
| 1711 | |
| 1712 uint size_exception_handler() { | |
| 1713 if (TraceJumps) { | |
| 1714 return (400); // just a guess | |
| 1715 } | |
| 1716 return ( NativeJump::instruction_size ); // sethi;jmp;nop | |
| 1717 } | |
| 1718 | |
| 1719 uint size_deopt_handler() { | |
| 1720 if (TraceJumps) { | |
| 1721 return (400); // just a guess | |
| 1722 } | |
| 1723 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore | |
| 1724 } | |
| 1725 | |
| 1726 // Emit exception handler code. | |
| 1727 int emit_exception_handler(CodeBuffer& cbuf) { | |
| 1728 Register temp_reg = G3; | |
| 1748 | 1729 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); |
| 0 | 1730 MacroAssembler _masm(&cbuf); |
| 1731 | |
| 1732 address base = | |
| 1733 __ start_a_stub(size_exception_handler()); | |
| 1734 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1735 | |
| 1736 int offset = __ offset(); | |
| 1737 | |
| 727 | 1738 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1739 __ delayed()->nop(); |
| 1740 | |
| 1741 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
| 1742 | |
| 1743 __ end_a_stub(); | |
| 1744 | |
| 1745 return offset; | |
| 1746 } | |
| 1747 | |
| 1748 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 1749 // Can't use any of the current frame's registers as we may have deopted | |
| 1750 // at a poll and everything (including G3) can be live. | |
| 1751 Register temp_reg = L0; | |
| 727 | 1752 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
| 0 | 1753 MacroAssembler _masm(&cbuf); |
| 1754 | |
| 1755 address base = | |
| 1756 __ start_a_stub(size_deopt_handler()); | |
| 1757 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1758 | |
| 1759 int offset = __ offset(); | |
| 1760 __ save_frame(0); | |
| 727 | 1761 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1762 __ delayed()->restore(); |
| 1763 | |
| 1764 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1765 | |
| 1766 __ end_a_stub(); | |
| 1767 return offset; | |
| 1768 | |
| 1769 } | |
| 1770 | |
| 1771 // Given a register encoding, produce a Integer Register object | |
| 1772 static Register reg_to_register_object(int register_encoding) { | |
| 1773 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
| 1774 return as_Register(register_encoding); | |
| 1775 } | |
| 1776 | |
| 1777 // Given a register encoding, produce a single-precision Float Register object | |
| 1778 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
| 1779 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
| 1780 return as_SingleFloatRegister(register_encoding); | |
| 1781 } | |
| 1782 | |
| 1783 // Given a register encoding, produce a double-precision Float Register object | |
| 1784 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
| 1785 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
| 1786 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
| 1787 return as_DoubleFloatRegister(register_encoding); | |
| 1788 } | |
| 1789 | |
|
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1790 const bool Matcher::match_rule_supported(int opcode) { |
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1791 if (!has_match_rule(opcode)) |
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1792 return false; |
|
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1793 |
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1794 switch (opcode) { |
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1795 case Op_CountLeadingZerosI: |
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1796 case Op_CountLeadingZerosL: |
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1797 case Op_CountTrailingZerosI: |
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1798 case Op_CountTrailingZerosL: |
|
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1799 case Op_PopCountI: |
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1800 case Op_PopCountL: |
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1801 if (!UsePopCountInstruction) |
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1802 return false; |
|
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1803 case Op_CompareAndSwapL: |
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1804 #ifdef _LP64 |
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1805 case Op_CompareAndSwapP: |
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1806 #endif |
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1807 if (!VM_Version::supports_cx8()) |
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1808 return false; |
|
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1809 break; |
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1810 } |
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1811 |
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1812 return true; // Per default match rules are supported. |
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1813 } |
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1814 |
| 0 | 1815 int Matcher::regnum_to_fpu_offset(int regnum) { |
| 1816 return regnum - 32; // The FP registers are in the second chunk | |
| 1817 } | |
| 1818 | |
| 1819 #ifdef ASSERT | |
| 1820 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
| 1821 #endif | |
| 1822 | |
| 1823 // Vector width in bytes | |
|
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1824 const int Matcher::vector_width_in_bytes(BasicType bt) { |
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1825 assert(MaxVectorSize == 8, ""); |
| 0 | 1826 return 8; |
| 1827 } | |
| 1828 | |
| 1829 // Vector ideal reg | |
|
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1830 const int Matcher::vector_ideal_reg(int size) { |
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1831 assert(MaxVectorSize == 8, ""); |
| 0 | 1832 return Op_RegD; |
| 1833 } | |
| 1834 | |
| 6823 | 1835 const int Matcher::vector_shift_count_ideal_reg(int size) { |
| 1836 fatal("vector shift is not supported"); | |
| 1837 return Node::NotAMachineReg; | |
| 1838 } | |
| 1839 | |
|
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1840 // Limits on vector size (number of elements) loaded into vector. |
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1841 const int Matcher::max_vector_size(const BasicType bt) { |
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1842 assert(is_java_primitive(bt), "only primitive type vectors"); |
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1843 return vector_width_in_bytes(bt)/type2aelembytes(bt); |
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1844 } |
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1845 |
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1846 const int Matcher::min_vector_size(const BasicType bt) { |
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1847 return max_vector_size(bt); // Same as max. |
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1848 } |
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1849 |
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1850 // SPARC doesn't support misaligned vectors store/load. |
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1851 const bool Matcher::misaligned_vectors_ok() { |
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1852 return false; |
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1853 } |
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1854 |
| 0 | 1855 // USII supports fxtof through the whole range of number, USIII doesn't |
| 1856 const bool Matcher::convL2FSupported(void) { | |
| 1857 return VM_Version::has_fast_fxtof(); | |
| 1858 } | |
| 1859 | |
| 1860 // Is this branch offset short enough that a short branch can be used? | |
| 1861 // | |
| 1862 // NOTE: If the platform does not provide any short branch variants, then | |
| 1863 // this method should return false for offset 0. | |
| 3851 | 1864 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1865 // The passed offset is relative to address of the branch. | |
| 1866 // Don't need to adjust the offset. | |
|
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1867 return UseCBCond && Assembler::is_simm12(offset); |
| 0 | 1868 } |
| 1869 | |
| 1870 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1871 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1872 // Depends on optimizations in MacroAssembler::setx. | |
| 1873 int hi = (int)(value >> 32); | |
| 1874 int lo = (int)(value & ~0); | |
| 1875 return (hi == 0) || (hi == -1) || (lo == 0); | |
| 1876 } | |
| 1877 | |
| 1878 // No scaling for the parameter the ClearArray node. | |
| 1879 const bool Matcher::init_array_count_is_in_bytes = true; | |
| 1880 | |
| 1881 // Threshold size for cleararray. | |
| 1882 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1883 | |
| 4047 | 1884 // No additional cost for CMOVL. |
| 1885 const int Matcher::long_cmove_cost() { return 0; } | |
| 1886 | |
| 1887 // CMOVF/CMOVD are expensive on T4 and on SPARC64. | |
| 1888 const int Matcher::float_cmove_cost() { | |
| 1889 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; | |
| 1890 } | |
| 1891 | |
|
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1892 // Does the CPU require late expand (see block.cpp for description of late expand)? |
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1893 const bool Matcher::require_postalloc_expand = false; |
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1894 |
| 0 | 1895 // Should the Matcher clone shifts on addressing modes, expecting them to |
| 1896 // be subsumed into complex addressing expressions or compute them into | |
| 1897 // registers? True for Intel but false for most RISCs | |
| 1898 const bool Matcher::clone_shift_expressions = false; | |
| 1899 | |
|
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1900 // Do we need to mask the count passed to shift instructions or does |
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1901 // the cpu only look at the lower 5/6 bits anyway? |
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1902 const bool Matcher::need_masked_shift_count = false; |
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1903 |
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1904 bool Matcher::narrow_oop_use_complex_address() { |
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1905 NOT_LP64(ShouldNotCallThis()); |
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1906 assert(UseCompressedOops, "only for compressed oops code"); |
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1907 return false; |
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1908 } |
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1909 |
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1910 bool Matcher::narrow_klass_use_complex_address() { |
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1911 NOT_LP64(ShouldNotCallThis()); |
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1912 assert(UseCompressedClassPointers, "only for compressed klass code"); |
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1913 return false; |
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1914 } |
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1915 |
| 0 | 1916 // Is it better to copy float constants, or load them directly from memory? |
| 1917 // Intel can load a float constant from a direct address, requiring no | |
| 1918 // extra registers. Most RISCs will have to materialize an address into a | |
| 1919 // register first, so they would do better to copy the constant from stack. | |
| 1920 const bool Matcher::rematerialize_float_constants = false; | |
| 1921 | |
| 1922 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1923 // needed. Else we split the double into 2 integer pieces and move it | |
| 1924 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1925 // Java calling convention forces doubles to be aligned. | |
| 1926 #ifdef _LP64 | |
| 1927 const bool Matcher::misaligned_doubles_ok = true; | |
| 1928 #else | |
| 1929 const bool Matcher::misaligned_doubles_ok = false; | |
| 1930 #endif | |
| 1931 | |
| 1932 // No-op on SPARC. | |
| 1933 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1934 } | |
| 1935 | |
| 1936 // Advertise here if the CPU requires explicit rounding operations | |
| 1937 // to implement the UseStrictFP mode. | |
| 1938 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
| 1939 | |
|
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1940 // Are floats conerted to double when stored to stack during deoptimization? |
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1941 // Sparc does not handle callee-save floats. |
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1942 bool Matcher::float_in_double() { return false; } |
| 0 | 1943 |
| 1944 // Do ints take an entire long register or just half? | |
| 1945 // Note that we if-def off of _LP64. | |
| 1946 // The relevant question is how the int is callee-saved. In _LP64 | |
| 1947 // the whole long is written but de-opt'ing will have to extract | |
| 1948 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
| 1949 #ifdef _LP64 | |
| 1950 const bool Matcher::int_in_long = true; | |
| 1951 #else | |
| 1952 const bool Matcher::int_in_long = false; | |
| 1953 #endif | |
| 1954 | |
| 1955 // Return whether or not this register is ever used as an argument. This | |
| 1956 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1957 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1958 // arguments in those registers not be available to the callee. | |
| 1959 bool Matcher::can_be_java_arg( int reg ) { | |
| 1960 // Standard sparc 6 args in registers | |
| 1961 if( reg == R_I0_num || | |
| 1962 reg == R_I1_num || | |
| 1963 reg == R_I2_num || | |
| 1964 reg == R_I3_num || | |
| 1965 reg == R_I4_num || | |
| 1966 reg == R_I5_num ) return true; | |
| 1967 #ifdef _LP64 | |
| 1968 // 64-bit builds can pass 64-bit pointers and longs in | |
| 1969 // the high I registers | |
| 1970 if( reg == R_I0H_num || | |
| 1971 reg == R_I1H_num || | |
| 1972 reg == R_I2H_num || | |
| 1973 reg == R_I3H_num || | |
| 1974 reg == R_I4H_num || | |
| 1975 reg == R_I5H_num ) return true; | |
|
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1976 |
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1977 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
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1978 return true; |
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1979 } |
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1980 |
| 0 | 1981 #else |
| 1982 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
| 1983 // Longs cannot be passed in O regs, because O regs become I regs | |
| 1984 // after a 'save' and I regs get their high bits chopped off on | |
| 1985 // interrupt. | |
| 1986 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
| 1987 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
| 1988 #endif | |
| 1989 // A few float args in registers | |
| 1990 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
| 1991 | |
| 1992 return false; | |
| 1993 } | |
| 1994 | |
| 1995 bool Matcher::is_spillable_arg( int reg ) { | |
| 1996 return can_be_java_arg(reg); | |
| 1997 } | |
| 1998 | |
|
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1999 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
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2000 // Use hardware SDIVX instruction when it is |
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2001 // faster than a code which use multiply. |
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2002 return VM_Version::has_fast_idiv(); |
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2003 } |
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2004 |
| 0 | 2005 // Register for DIVI projection of divmodI |
| 2006 RegMask Matcher::divI_proj_mask() { | |
| 2007 ShouldNotReachHere(); | |
| 2008 return RegMask(); | |
| 2009 } | |
| 2010 | |
| 2011 // Register for MODI projection of divmodI | |
| 2012 RegMask Matcher::modI_proj_mask() { | |
| 2013 ShouldNotReachHere(); | |
| 2014 return RegMask(); | |
| 2015 } | |
| 2016 | |
| 2017 // Register for DIVL projection of divmodL | |
| 2018 RegMask Matcher::divL_proj_mask() { | |
| 2019 ShouldNotReachHere(); | |
| 2020 return RegMask(); | |
| 2021 } | |
| 2022 | |
| 2023 // Register for MODL projection of divmodL | |
| 2024 RegMask Matcher::modL_proj_mask() { | |
| 2025 ShouldNotReachHere(); | |
| 2026 return RegMask(); | |
| 2027 } | |
| 2028 | |
|
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2029 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
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2030 return L7_REGP_mask(); |
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2031 } |
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2032 |
| 12323 | 2033 const RegMask Matcher::mathExactI_result_proj_mask() { |
| 2034 return G1_REGI_mask(); | |
| 2035 } | |
| 2036 | |
|
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2037 const RegMask Matcher::mathExactL_result_proj_mask() { |
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2038 return G1_REGL_mask(); |
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2039 } |
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2040 |
| 12323 | 2041 const RegMask Matcher::mathExactI_flags_proj_mask() { |
| 2042 return INT_FLAGS_mask(); | |
| 2043 } | |
| 2044 | |
| 2045 | |
| 0 | 2046 %} |
| 2047 | |
| 2048 | |
| 2049 // The intptr_t operand types, defined by textual substitution. | |
| 2050 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
| 2051 #ifdef _LP64 | |
| 824 | 2052 #define immX immL |
| 2053 #define immX13 immL13 | |
| 2054 #define immX13m7 immL13m7 | |
| 2055 #define iRegX iRegL | |
| 2056 #define g1RegX g1RegL | |
| 0 | 2057 #else |
| 824 | 2058 #define immX immI |
| 2059 #define immX13 immI13 | |
| 2060 #define immX13m7 immI13m7 | |
| 2061 #define iRegX iRegI | |
| 2062 #define g1RegX g1RegI | |
| 0 | 2063 #endif |
| 2064 | |
| 2065 //----------ENCODING BLOCK----------------------------------------------------- | |
| 2066 // This block specifies the encoding classes used by the compiler to output | |
| 2067 // byte streams. Encoding classes are parameterized macros used by | |
| 2068 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 2069 // instruction. Operands specify their base encoding interface with the | |
| 2070 // interface keyword. There are currently supported four interfaces, | |
| 2071 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 2072 // operand to generate a function which returns its register number when | |
| 2073 // queried. CONST_INTER causes an operand to generate a function which | |
| 2074 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 2075 // operand to generate four functions which return the Base Register, the | |
| 2076 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 2077 // queried. COND_INTER causes an operand to generate six functions which | |
| 2078 // return the encoding code (ie - encoding bits for the instruction) | |
| 2079 // associated with each basic boolean condition for a conditional instruction. | |
| 2080 // | |
| 2081 // Instructions specify two basic values for encoding. Again, a function | |
| 2082 // is available to check if the constant displacement is an oop. They use the | |
| 2083 // ins_encode keyword to specify their encoding classes (which must be | |
| 2084 // a sequence of enc_class names, and their parameters, specified in | |
| 2085 // the encoding block), and they use the | |
| 2086 // opcode keyword to specify, in order, their primary, secondary, and | |
| 2087 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 2088 // needs for encoding need to be specified. | |
| 2089 encode %{ | |
| 2090 enc_class enc_untested %{ | |
| 2091 #ifdef ASSERT | |
| 2092 MacroAssembler _masm(&cbuf); | |
| 2093 __ untested("encoding"); | |
| 2094 #endif | |
| 2095 %} | |
| 2096 | |
| 2097 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
| 2098 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
| 2099 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | |
| 2100 %} | |
| 2101 | |
|
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2102 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
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2103 emit_form3_mem_reg(cbuf, this, $primary, -1, |
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2104 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
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2105 %} |
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2106 |
| 0 | 2107 enc_class form3_mem_prefetch_read( memory mem ) %{ |
|
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2108 emit_form3_mem_reg(cbuf, this, $primary, -1, |
| 0 | 2109 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
| 2110 %} | |
| 2111 | |
| 2112 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
|
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2113 emit_form3_mem_reg(cbuf, this, $primary, -1, |
| 0 | 2114 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
| 2115 %} | |
| 2116 | |
| 2117 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
|
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2118 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
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2119 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
| 0 | 2120 guarantee($mem$$index == R_G0_enc, "double index?"); |
|
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2121 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
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2122 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
| 0 | 2123 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
| 2124 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
| 2125 %} | |
| 2126 | |
| 2127 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
|
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2128 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
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2129 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
| 0 | 2130 guarantee($mem$$index == R_G0_enc, "double index?"); |
| 2131 // Load long with 2 instructions | |
|
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2132 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
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2133 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
| 0 | 2134 %} |
| 2135 | |
| 2136 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
| 2137 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
| 2138 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
|
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2139 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
| 0 | 2140 %} |
| 2141 | |
| 2142 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
| 2143 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2144 if( $rs2$$reg != $rd$$reg ) | |
| 2145 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 2146 %} | |
| 2147 | |
| 2148 // Target lo half of long | |
| 2149 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
| 2150 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2151 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
| 2152 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 2153 %} | |
| 2154 | |
| 2155 // Source lo half of long | |
| 2156 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
| 2157 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2158 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
| 2159 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
| 2160 %} | |
| 2161 | |
| 2162 // Target hi half of long | |
| 2163 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
| 2164 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
| 2165 %} | |
| 2166 | |
| 2167 // Source lo half of long, and leave it sign extended. | |
| 2168 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
| 2169 // Sign extend low half | |
| 2170 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
| 2171 %} | |
| 2172 | |
| 2173 // Source hi half of long, and leave it sign extended. | |
| 2174 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
| 2175 // Shift high half to low half | |
| 2176 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
| 2177 %} | |
| 2178 | |
| 2179 // Source hi half of long | |
| 2180 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
| 2181 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2182 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
| 2183 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
| 2184 %} | |
| 2185 | |
| 2186 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
| 2187 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
| 2188 %} | |
| 2189 | |
| 2190 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
| 2191 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
| 2192 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
| 2193 %} | |
| 2194 | |
| 2195 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
| 2196 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
| 2197 // clear if nothing else is happening | |
| 2198 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
| 2199 // blt,a,pn done | |
| 2200 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
| 2201 // mov dst,-1 in delay slot | |
| 2202 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2203 %} | |
| 2204 | |
| 2205 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
| 2206 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
| 2207 %} | |
| 2208 | |
| 2209 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
| 2210 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
| 2211 %} | |
| 2212 | |
| 2213 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
| 2214 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
| 2215 %} | |
| 2216 | |
| 2217 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
| 2218 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
| 2219 %} | |
| 2220 | |
| 2221 enc_class move_return_pc_to_o1() %{ | |
| 2222 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
| 2223 %} | |
| 2224 | |
| 2225 #ifdef _LP64 | |
| 2226 /* %%% merge with enc_to_bool */ | |
| 2227 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
| 2228 MacroAssembler _masm(&cbuf); | |
| 2229 | |
| 2230 Register src_reg = reg_to_register_object($src$$reg); | |
| 2231 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 2232 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
| 2233 %} | |
| 2234 #endif | |
| 2235 | |
| 2236 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
| 2237 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
| 2238 MacroAssembler _masm(&cbuf); | |
| 2239 | |
| 2240 Register p_reg = reg_to_register_object($p$$reg); | |
| 2241 Register q_reg = reg_to_register_object($q$$reg); | |
| 2242 Register y_reg = reg_to_register_object($y$$reg); | |
| 2243 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
| 2244 | |
| 2245 __ subcc( p_reg, q_reg, p_reg ); | |
| 2246 __ add ( p_reg, y_reg, tmp_reg ); | |
| 2247 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
| 2248 %} | |
| 2249 | |
| 2250 enc_class form_d2i_helper(regD src, regF dst) %{ | |
| 2251 // fcmp %fcc0,$src,$src | |
| 2252 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2253 // branch %fcc0 not-nan, predict taken | |
| 2254 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2255 // fdtoi $src,$dst | |
| 2256 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
| 2257 // fitos $dst,$dst (if nan) | |
| 2258 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2259 // clear $dst (if nan) | |
| 2260 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2261 // carry on here... | |
| 2262 %} | |
| 2263 | |
| 2264 enc_class form_d2l_helper(regD src, regD dst) %{ | |
| 2265 // fcmp %fcc0,$src,$src check for NAN | |
| 2266 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2267 // branch %fcc0 not-nan, predict taken | |
| 2268 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2269 // fdtox $src,$dst convert in delay slot | |
| 2270 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
| 2271 // fxtod $dst,$dst (if nan) | |
| 2272 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2273 // clear $dst (if nan) | |
| 2274 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2275 // carry on here... | |
| 2276 %} | |
| 2277 | |
| 2278 enc_class form_f2i_helper(regF src, regF dst) %{ | |
| 2279 // fcmps %fcc0,$src,$src | |
| 2280 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2281 // branch %fcc0 not-nan, predict taken | |
| 2282 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2283 // fstoi $src,$dst | |
| 2284 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
| 2285 // fitos $dst,$dst (if nan) | |
| 2286 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2287 // clear $dst (if nan) | |
| 2288 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2289 // carry on here... | |
| 2290 %} | |
| 2291 | |
| 2292 enc_class form_f2l_helper(regF src, regD dst) %{ | |
| 2293 // fcmps %fcc0,$src,$src | |
| 2294 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2295 // branch %fcc0 not-nan, predict taken | |
| 2296 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2297 // fstox $src,$dst | |
| 2298 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
| 2299 // fxtod $dst,$dst (if nan) | |
| 2300 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2301 // clear $dst (if nan) | |
| 2302 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2303 // carry on here... | |
| 2304 %} | |
| 2305 | |
| 2306 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2307 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2308 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2309 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2310 | |
| 2311 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2312 | |
| 2313 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2314 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2315 | |
| 2316 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
| 2317 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2318 %} | |
| 2319 | |
| 2320 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
| 2321 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2322 %} | |
| 2323 | |
| 2324 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
| 2325 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2326 %} | |
| 2327 | |
| 2328 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
| 2329 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2330 %} | |
| 2331 | |
| 2332 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
| 2333 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
| 2334 %} | |
| 2335 | |
| 2336 // Encloding class for traceable jumps | |
| 2337 enc_class form_jmpl(g3RegP dest) %{ | |
| 2338 emit_jmpl(cbuf, $dest$$reg); | |
| 2339 %} | |
| 2340 | |
| 2341 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
| 2342 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
| 2343 %} | |
| 2344 | |
| 2345 enc_class form2_nop() %{ | |
| 2346 emit_nop(cbuf); | |
| 2347 %} | |
| 2348 | |
| 2349 enc_class form2_illtrap() %{ | |
| 2350 emit_illtrap(cbuf); | |
| 2351 %} | |
| 2352 | |
| 2353 | |
| 2354 // Compare longs and convert into -1, 0, 1. | |
| 2355 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
| 2356 // CMP $src1,$src2 | |
| 2357 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
| 2358 // blt,a,pn done | |
| 2359 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
| 2360 // mov dst,-1 in delay slot | |
| 2361 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2362 // bgt,a,pn done | |
| 2363 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
| 2364 // mov dst,1 in delay slot | |
| 2365 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
| 2366 // CLR $dst | |
| 2367 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
| 2368 %} | |
| 2369 | |
| 2370 enc_class enc_PartialSubtypeCheck() %{ | |
| 2371 MacroAssembler _masm(&cbuf); | |
| 2372 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
| 2373 __ delayed()->nop(); | |
| 2374 %} | |
| 2375 | |
| 3839 | 2376 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ |
| 0 | 2377 MacroAssembler _masm(&cbuf); |
| 3839 | 2378 Label* L = $labl$$label; |
| 0 | 2379 Assembler::Predict predict_taken = |
| 3839 | 2380 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
| 2381 | |
| 2382 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 0 | 2383 __ delayed()->nop(); |
| 2384 %} | |
| 2385 | |
| 3839 | 2386 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ |
| 0 | 2387 MacroAssembler _masm(&cbuf); |
| 3839 | 2388 Label* L = $labl$$label; |
| 0 | 2389 Assembler::Predict predict_taken = |
| 3839 | 2390 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
| 2391 | |
| 2392 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); | |
| 0 | 2393 __ delayed()->nop(); |
| 2394 %} | |
| 2395 | |
| 2396 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
| 2397 int op = (Assembler::arith_op << 30) | | |
| 2398 ($dst$$reg << 25) | | |
| 2399 (Assembler::movcc_op3 << 19) | | |
| 2400 (1 << 18) | // cc2 bit for 'icc' | |
| 2401 ($cmp$$cmpcode << 14) | | |
| 2402 (0 << 13) | // select register move | |
| 2403 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
| 2404 ($src$$reg << 0); | |
| 1748 | 2405 cbuf.insts()->emit_int32(op); |
| 0 | 2406 %} |
| 2407 | |
| 2408 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
| 2409 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2410 int op = (Assembler::arith_op << 30) | | |
| 2411 ($dst$$reg << 25) | | |
| 2412 (Assembler::movcc_op3 << 19) | | |
| 2413 (1 << 18) | // cc2 bit for 'icc' | |
| 2414 ($cmp$$cmpcode << 14) | | |
| 2415 (1 << 13) | // select immediate move | |
| 2416 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
| 2417 (simm11 << 0); | |
| 1748 | 2418 cbuf.insts()->emit_int32(op); |
| 0 | 2419 %} |
| 2420 | |
| 2421 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
| 2422 int op = (Assembler::arith_op << 30) | | |
| 2423 ($dst$$reg << 25) | | |
| 2424 (Assembler::movcc_op3 << 19) | | |
| 2425 (0 << 18) | // cc2 bit for 'fccX' | |
| 2426 ($cmp$$cmpcode << 14) | | |
| 2427 (0 << 13) | // select register move | |
| 2428 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2429 ($src$$reg << 0); | |
| 1748 | 2430 cbuf.insts()->emit_int32(op); |
| 0 | 2431 %} |
| 2432 | |
| 2433 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
| 2434 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2435 int op = (Assembler::arith_op << 30) | | |
| 2436 ($dst$$reg << 25) | | |
| 2437 (Assembler::movcc_op3 << 19) | | |
| 2438 (0 << 18) | // cc2 bit for 'fccX' | |
| 2439 ($cmp$$cmpcode << 14) | | |
| 2440 (1 << 13) | // select immediate move | |
| 2441 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2442 (simm11 << 0); | |
| 1748 | 2443 cbuf.insts()->emit_int32(op); |
| 0 | 2444 %} |
| 2445 | |
| 2446 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
| 2447 int op = (Assembler::arith_op << 30) | | |
| 2448 ($dst$$reg << 25) | | |
| 2449 (Assembler::fpop2_op3 << 19) | | |
| 2450 (0 << 18) | | |
| 2451 ($cmp$$cmpcode << 14) | | |
| 2452 (1 << 13) | // select register move | |
| 2453 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
| 2454 ($primary << 5) | // select single, double or quad | |
| 2455 ($src$$reg << 0); | |
| 1748 | 2456 cbuf.insts()->emit_int32(op); |
| 0 | 2457 %} |
| 2458 | |
| 2459 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
| 2460 int op = (Assembler::arith_op << 30) | | |
| 2461 ($dst$$reg << 25) | | |
| 2462 (Assembler::fpop2_op3 << 19) | | |
| 2463 (0 << 18) | | |
| 2464 ($cmp$$cmpcode << 14) | | |
| 2465 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
| 2466 ($primary << 5) | // select single, double or quad | |
| 2467 ($src$$reg << 0); | |
| 1748 | 2468 cbuf.insts()->emit_int32(op); |
| 0 | 2469 %} |
| 2470 | |
| 2471 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
| 2472 // the condition comes from opcode-field instead of an argument. | |
| 2473 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
| 2474 int op = (Assembler::arith_op << 30) | | |
| 2475 ($dst$$reg << 25) | | |
| 2476 (Assembler::movcc_op3 << 19) | | |
| 2477 (1 << 18) | // cc2 bit for 'icc' | |
| 2478 ($primary << 14) | | |
| 2479 (0 << 13) | // select register move | |
| 2480 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2481 ($src$$reg << 0); | |
| 1748 | 2482 cbuf.insts()->emit_int32(op); |
| 0 | 2483 %} |
| 2484 | |
| 2485 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
| 2486 int op = (Assembler::arith_op << 30) | | |
| 2487 ($dst$$reg << 25) | | |
| 2488 (Assembler::movcc_op3 << 19) | | |
| 2489 (6 << 16) | // cc2 bit for 'xcc' | |
| 2490 ($primary << 14) | | |
| 2491 (0 << 13) | // select register move | |
| 2492 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2493 ($src$$reg << 0); | |
| 1748 | 2494 cbuf.insts()->emit_int32(op); |
| 0 | 2495 %} |
| 2496 | |
| 2497 enc_class Set13( immI13 src, iRegI rd ) %{ | |
| 2498 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
| 2499 %} | |
| 2500 | |
| 2501 enc_class SetHi22( immI src, iRegI rd ) %{ | |
| 2502 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
| 2503 %} | |
| 2504 | |
| 2505 enc_class Set32( immI src, iRegI rd ) %{ | |
| 2506 MacroAssembler _masm(&cbuf); | |
| 2507 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
| 2508 %} | |
| 2509 | |
| 2510 enc_class call_epilog %{ | |
| 2511 if( VerifyStackAtCalls ) { | |
| 2512 MacroAssembler _masm(&cbuf); | |
| 2513 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
| 2514 Register temp_reg = G3; | |
| 2515 __ add(SP, framesize, temp_reg); | |
| 2516 __ cmp(temp_reg, FP); | |
| 2517 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
| 2518 } | |
| 2519 %} | |
| 2520 | |
| 2521 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
| 2522 // to G1 so the register allocator will not have to deal with the misaligned register | |
| 2523 // pair. | |
| 2524 enc_class adjust_long_from_native_call %{ | |
| 2525 #ifndef _LP64 | |
| 2526 if (returns_long()) { | |
| 2527 // sllx O0,32,O0 | |
| 2528 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
| 2529 // srl O1,0,O1 | |
| 2530 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
| 2531 // or O0,O1,G1 | |
| 2532 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
| 2533 } | |
| 2534 #endif | |
| 2535 %} | |
| 2536 | |
| 2537 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
| 2538 // CALL directly to the runtime | |
| 2539 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
| 2540 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
|
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2541 /*preserve_g2=*/true); |
| 0 | 2542 %} |
| 2543 | |
| 1567 | 2544 enc_class preserve_SP %{ |
| 2545 MacroAssembler _masm(&cbuf); | |
| 2546 __ mov(SP, L7_mh_SP_save); | |
| 2547 %} | |
| 2548 | |
| 2549 enc_class restore_SP %{ | |
| 2550 MacroAssembler _masm(&cbuf); | |
| 2551 __ mov(L7_mh_SP_save, SP); | |
| 2552 %} | |
| 2553 | |
| 0 | 2554 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
| 2555 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2556 // who we intended to call. | |
|
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2557 if (!_method) { |
| 0 | 2558 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); |
| 2559 } else if (_optimized_virtual) { | |
| 2560 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
| 2561 } else { | |
| 2562 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
| 2563 } | |
|
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2564 if (_method) { // Emit stub for static call. |
|
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2565 CompiledStaticCall::emit_to_interp_stub(cbuf); |
| 0 | 2566 } |
| 2567 %} | |
| 2568 | |
| 2569 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
| 2570 MacroAssembler _masm(&cbuf); | |
| 2571 __ set_inst_mark(); | |
| 2572 int vtable_index = this->_vtable_index; | |
| 2573 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
| 2574 if (vtable_index < 0) { | |
| 2575 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
|
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2576 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
| 0 | 2577 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); |
| 2578 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
| 2579 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
|
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2580 __ ic_call((address)$meth$$method); |
| 0 | 2581 } else { |
| 2582 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 2583 // Just go thru the vtable | |
| 2584 // get receiver klass (receiver already checked for non-null) | |
| 2585 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
| 2586 int off = __ offset(); | |
|
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2587 __ load_klass(O0, G3_scratch); |
|
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2588 int klass_load_size; |
|
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2589 if (UseCompressedClassPointers) { |
|
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2590 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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2591 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; |
|
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2592 } else { |
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2593 klass_load_size = 1*BytesPerInstWord; |
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2594 } |
|
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2595 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
| 0 | 2596 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); |
|
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|
2597 if (Assembler::is_simm13(v_off)) { |
| 0 | 2598 __ ld_ptr(G3, v_off, G5_method); |
| 2599 } else { | |
| 2600 // Generate 2 instructions | |
| 2601 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
| 2602 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
| 2603 // ld_ptr, set_hi, set | |
|
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2604 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
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2605 "Unexpected instruction size(s)"); |
| 0 | 2606 __ ld_ptr(G3, G5_method, G5_method); |
| 2607 } | |
| 2608 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
| 2609 // However it may very well end up in handle_wrong_method if the | |
| 2610 // method is abstract for the particular class. | |
|
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|
2611 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch); |
| 0 | 2612 // jump to target (either compiled code or c2iadapter) |
| 2613 __ jmpl(G3_scratch, G0, O7); | |
| 2614 __ delayed()->nop(); | |
| 2615 } | |
| 2616 %} | |
| 2617 | |
| 2618 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
| 2619 MacroAssembler _masm(&cbuf); | |
| 2620 | |
| 2621 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2622 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
| 2623 // we might be calling a C2I adapter which needs it. | |
| 2624 | |
| 2625 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
| 2626 // Load nmethod | |
|
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2627 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg); |
| 0 | 2628 |
| 2629 // CALL to compiled java, indirect the contents of G3 | |
| 2630 __ set_inst_mark(); | |
| 2631 __ callr(temp_reg, G0); | |
| 2632 __ delayed()->nop(); | |
| 2633 %} | |
| 2634 | |
| 2635 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
| 2636 MacroAssembler _masm(&cbuf); | |
| 2637 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2638 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2639 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2640 | |
| 2641 __ sra(Rdivisor, 0, Rdivisor); | |
| 2642 __ sra(Rdividend, 0, Rdividend); | |
| 2643 __ sdivx(Rdividend, Rdivisor, Rresult); | |
| 2644 %} | |
| 2645 | |
| 2646 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
| 2647 MacroAssembler _masm(&cbuf); | |
| 2648 | |
| 2649 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2650 int divisor = $imm$$constant; | |
| 2651 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2652 | |
| 2653 __ sra(Rdividend, 0, Rdividend); | |
| 2654 __ sdivx(Rdividend, divisor, Rresult); | |
| 2655 %} | |
| 2656 | |
| 2657 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 2658 MacroAssembler _masm(&cbuf); | |
| 2659 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
| 2660 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
| 2661 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2662 | |
| 2663 __ sra( Rsrc1, 0, Rsrc1 ); | |
| 2664 __ sra( Rsrc2, 0, Rsrc2 ); | |
| 2665 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
| 2666 __ srlx( Rdst, 32, Rdst ); | |
| 2667 %} | |
| 2668 | |
| 2669 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
| 2670 MacroAssembler _masm(&cbuf); | |
| 2671 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2672 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2673 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2674 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2675 | |
| 2676 assert(Rdividend != Rscratch, ""); | |
| 2677 assert(Rdivisor != Rscratch, ""); | |
| 2678 | |
| 2679 __ sra(Rdividend, 0, Rdividend); | |
| 2680 __ sra(Rdivisor, 0, Rdivisor); | |
| 2681 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
| 2682 __ mulx(Rscratch, Rdivisor, Rscratch); | |
| 2683 __ sub(Rdividend, Rscratch, Rresult); | |
| 2684 %} | |
| 2685 | |
| 2686 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
| 2687 MacroAssembler _masm(&cbuf); | |
| 2688 | |
| 2689 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2690 int divisor = $imm$$constant; | |
| 2691 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2692 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2693 | |
| 2694 assert(Rdividend != Rscratch, ""); | |
| 2695 | |
| 2696 __ sra(Rdividend, 0, Rdividend); | |
| 2697 __ sdivx(Rdividend, divisor, Rscratch); | |
| 2698 __ mulx(Rscratch, divisor, Rscratch); | |
| 2699 __ sub(Rdividend, Rscratch, Rresult); | |
| 2700 %} | |
| 2701 | |
| 2702 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
| 2703 MacroAssembler _masm(&cbuf); | |
| 2704 | |
| 2705 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2706 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2707 | |
| 2708 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2709 %} | |
| 2710 | |
| 2711 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
| 2712 MacroAssembler _masm(&cbuf); | |
| 2713 | |
| 2714 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2715 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2716 | |
| 2717 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2718 %} | |
| 2719 | |
| 2720 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
| 2721 MacroAssembler _masm(&cbuf); | |
| 2722 | |
| 2723 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2724 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2725 | |
| 2726 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2727 %} | |
| 2728 | |
| 2729 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
| 2730 MacroAssembler _masm(&cbuf); | |
| 2731 | |
| 2732 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2733 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2734 | |
| 2735 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2736 %} | |
| 2737 | |
| 2738 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
| 2739 MacroAssembler _masm(&cbuf); | |
| 2740 | |
| 2741 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2742 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2743 | |
| 2744 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2745 %} | |
| 2746 | |
| 2747 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
| 2748 MacroAssembler _masm(&cbuf); | |
| 2749 | |
| 2750 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2751 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2752 | |
| 2753 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2754 %} | |
| 2755 | |
| 2756 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
| 2757 MacroAssembler _masm(&cbuf); | |
| 2758 | |
| 2759 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2760 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2761 | |
| 2762 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2763 %} | |
| 2764 | |
| 2765 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2766 MacroAssembler _masm(&cbuf); | |
| 2767 | |
| 2768 Register Roop = reg_to_register_object($oop$$reg); | |
| 2769 Register Rbox = reg_to_register_object($box$$reg); | |
| 2770 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2771 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2772 | |
| 2773 assert(Roop != Rscratch, ""); | |
| 2774 assert(Roop != Rmark, ""); | |
| 2775 assert(Rbox != Rscratch, ""); | |
| 2776 assert(Rbox != Rmark, ""); | |
| 2777 | |
|
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|
2778 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2779 %} |
| 2780 | |
| 2781 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2782 MacroAssembler _masm(&cbuf); | |
| 2783 | |
| 2784 Register Roop = reg_to_register_object($oop$$reg); | |
| 2785 Register Rbox = reg_to_register_object($box$$reg); | |
| 2786 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2787 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2788 | |
| 2789 assert(Roop != Rscratch, ""); | |
| 2790 assert(Roop != Rmark, ""); | |
| 2791 assert(Rbox != Rscratch, ""); | |
| 2792 assert(Rbox != Rmark, ""); | |
| 2793 | |
|
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|
2794 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2795 %} |
| 2796 | |
| 2797 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
| 2798 MacroAssembler _masm(&cbuf); | |
| 2799 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2800 Register Rold = reg_to_register_object($old$$reg); | |
| 2801 Register Rnew = reg_to_register_object($new$$reg); | |
| 2802 | |
| 10997 | 2803 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
| 0 | 2804 __ cmp( Rold, Rnew ); |
| 2805 %} | |
| 2806 | |
| 2807 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
| 2808 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2809 Register Rold = reg_to_register_object($old$$reg); | |
| 2810 Register Rnew = reg_to_register_object($new$$reg); | |
| 2811 | |
| 2812 MacroAssembler _masm(&cbuf); | |
| 2813 __ mov(Rnew, O7); | |
| 2814 __ casx(Rmem, Rold, O7); | |
| 2815 __ cmp( Rold, O7 ); | |
| 2816 %} | |
| 2817 | |
| 2818 // raw int cas, used for compareAndSwap | |
| 2819 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
| 2820 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2821 Register Rold = reg_to_register_object($old$$reg); | |
| 2822 Register Rnew = reg_to_register_object($new$$reg); | |
| 2823 | |
| 2824 MacroAssembler _masm(&cbuf); | |
| 2825 __ mov(Rnew, O7); | |
| 2826 __ cas(Rmem, Rold, O7); | |
| 2827 __ cmp( Rold, O7 ); | |
| 2828 %} | |
| 2829 | |
| 2830 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
| 2831 Register Rres = reg_to_register_object($res$$reg); | |
| 2832 | |
| 2833 MacroAssembler _masm(&cbuf); | |
| 2834 __ mov(1, Rres); | |
| 2835 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
| 2836 %} | |
| 2837 | |
| 2838 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
| 2839 Register Rres = reg_to_register_object($res$$reg); | |
| 2840 | |
| 2841 MacroAssembler _masm(&cbuf); | |
| 2842 __ mov(1, Rres); | |
| 2843 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
| 2844 %} | |
| 2845 | |
| 2846 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
| 2847 MacroAssembler _masm(&cbuf); | |
| 2848 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2849 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
| 2850 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
| 2851 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
| 2852 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
| 2853 | |
| 2854 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
| 2855 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
| 2856 %} | |
| 2857 | |
| 2858 | |
|
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2859 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
| 0 | 2860 Label Ldone, Lloop; |
| 2861 MacroAssembler _masm(&cbuf); | |
| 2862 | |
| 2863 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2864 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
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2865 Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
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2866 Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
| 0 | 2867 Register result_reg = reg_to_register_object($result$$reg); |
| 2868 | |
|
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2869 assert(result_reg != str1_reg && |
|
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2870 result_reg != str2_reg && |
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2871 result_reg != cnt1_reg && |
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|
2872 result_reg != cnt2_reg , |
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2873 "need different registers"); |
| 0 | 2874 |
| 2875 // Compute the minimum of the string lengths(str1_reg) and the | |
| 2876 // difference of the string lengths (stack) | |
| 2877 | |
| 2878 // See if the lengths are different, and calculate min in str1_reg. | |
| 2879 // Stash diff in O7 in case we need it for a tie-breaker. | |
| 2880 Label Lskip; | |
|
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2881 __ subcc(cnt1_reg, cnt2_reg, O7); |
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2882 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2883 __ br(Assembler::greater, true, Assembler::pt, Lskip); |
|
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2884 // cnt2 is shorter, so use its count: |
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2885 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2886 __ bind(Lskip); |
| 2887 | |
|
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2888 // reallocate cnt1_reg, cnt2_reg, result_reg |
| 0 | 2889 // Note: limit_reg holds the string length pre-scaled by 2 |
|
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2890 Register limit_reg = cnt1_reg; |
|
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2891 Register chr2_reg = cnt2_reg; |
| 0 | 2892 Register chr1_reg = result_reg; |
|
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2893 // str{12} are the base pointers |
| 0 | 2894 |
| 2895 // Is the minimum length zero? | |
| 2896 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
| 2897 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2898 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2899 | |
| 2900 // Load first characters | |
|
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2901 __ lduh(str1_reg, 0, chr1_reg); |
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|
2902 __ lduh(str2_reg, 0, chr2_reg); |
| 0 | 2903 |
| 2904 // Compare first characters | |
| 2905 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
| 2906 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2907 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2908 __ delayed()->nop(); | |
| 2909 | |
| 2910 { | |
| 2911 // Check after comparing first character to see if strings are equivalent | |
| 2912 Label LSkip2; | |
| 2913 // Check if the strings start at same location | |
|
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2914 __ cmp(str1_reg, str2_reg); |
| 0 | 2915 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
| 2916 __ delayed()->nop(); | |
| 2917 | |
| 2918 // Check if the length difference is zero (in O7) | |
| 2919 __ cmp(G0, O7); | |
| 2920 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2921 __ delayed()->mov(G0, result_reg); // result is zero | |
| 2922 | |
| 2923 // Strings might not be equal | |
| 2924 __ bind(LSkip2); | |
| 2925 } | |
| 2926 | |
|
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2927 // We have no guarantee that on 64 bit the higher half of limit_reg is 0 |
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2928 __ signx(limit_reg); |
|
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|
2929 |
| 0 | 2930 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); |
| 2931 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2932 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2933 | |
|
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2934 // Shift str1_reg and str2_reg to the end of the arrays, negate limit |
|
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2935 __ add(str1_reg, limit_reg, str1_reg); |
|
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|
2936 __ add(str2_reg, limit_reg, str2_reg); |
| 0 | 2937 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
| 2938 | |
| 2939 // Compare the rest of the characters | |
|
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|
2940 __ lduh(str1_reg, limit_reg, chr1_reg); |
| 0 | 2941 __ bind(Lloop); |
|
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2942 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
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|
2943 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 0 | 2944 __ subcc(chr1_reg, chr2_reg, chr1_reg); |
| 2945 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2946 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2947 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
| 2948 // annul LDUH if branch is not taken to prevent access past end of string | |
| 2949 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
|
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|
2950 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 0 | 2951 |
| 2952 // If strings are equal up to min length, return the length difference. | |
| 2953 __ mov(O7, result_reg); | |
| 2954 | |
| 2955 // Otherwise, return the difference between the first mismatched chars. | |
| 2956 __ bind(Ldone); | |
| 2957 %} | |
| 2958 | |
|
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2959 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
|
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2960 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
| 681 | 2961 MacroAssembler _masm(&cbuf); |
| 2962 | |
| 2963 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2964 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
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2965 Register cnt_reg = reg_to_register_object($cnt$$reg); |
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|
2966 Register tmp1_reg = O7; |
| 681 | 2967 Register result_reg = reg_to_register_object($result$$reg); |
| 2968 | |
|
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2969 assert(result_reg != str1_reg && |
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|
2970 result_reg != str2_reg && |
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|
2971 result_reg != cnt_reg && |
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|
2972 result_reg != tmp1_reg , |
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|
2973 "need different registers"); |
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2974 |
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|
2975 __ cmp(str1_reg, str2_reg); //same char[] ? |
| 681 | 2976 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 2977 __ delayed()->add(G0, 1, result_reg); | |
| 2978 | |
| 3839 | 2979 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn); |
|
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2980 __ delayed()->add(G0, 1, result_reg); // count == 0 |
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|
2981 |
| 681 | 2982 //rename registers |
|
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|
2983 Register limit_reg = cnt_reg; |
| 681 | 2984 Register chr1_reg = result_reg; |
|
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|
2985 Register chr2_reg = tmp1_reg; |
| 681 | 2986 |
|
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2987 // We have no guarantee that on 64 bit the higher half of limit_reg is 0 |
|
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|
2988 __ signx(limit_reg); |
|
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|
2989 |
| 681 | 2990 //check for alignment and position the pointers to the ends |
|
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|
2991 __ or3(str1_reg, str2_reg, chr1_reg); |
|
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|
2992 __ andcc(chr1_reg, 0x3, chr1_reg); |
|
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|
2993 // notZero means at least one not 4-byte aligned. |
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|
2994 // We could optimize the case when both arrays are not aligned |
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|
2995 // but it is not frequent case and it requires additional checks. |
|
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|
2996 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
|
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2997 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
|
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|
2998 |
|
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|
2999 // Compare char[] arrays aligned to 4 bytes. |
|
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|
3000 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
|
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|
3001 chr1_reg, chr2_reg, Ldone); |
| 3839 | 3002 __ ba(Ldone); |
| 681 | 3003 __ delayed()->add(G0, 1, result_reg); |
| 3004 | |
|
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|
3005 // char by char compare |
| 681 | 3006 __ bind(Lchar); |
|
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|
3007 __ add(str1_reg, limit_reg, str1_reg); |
|
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|
3008 __ add(str2_reg, limit_reg, str2_reg); |
| 681 | 3009 __ neg(limit_reg); //negate count |
| 3010 | |
|
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|
3011 __ lduh(str1_reg, limit_reg, chr1_reg); |
|
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|
3012 // Lchar_loop |
| 681 | 3013 __ bind(Lchar_loop); |
|
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|
3014 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 681 | 3015 __ cmp(chr1_reg, chr2_reg); |
| 3016 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
| 3017 __ delayed()->mov(G0, result_reg); //not equal | |
| 3018 __ inccc(limit_reg, sizeof(jchar)); | |
| 3019 // annul LDUH if branch is not taken to prevent access past end of string | |
|
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|
3020 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
|
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|
3021 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 681 | 3022 |
| 3023 __ add(G0, 1, result_reg); //equal | |
| 3024 | |
| 3025 __ bind(Ldone); | |
| 3026 %} | |
| 3027 | |
|
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|
3028 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
| 681 | 3029 Label Lvector, Ldone, Lloop; |
| 3030 MacroAssembler _masm(&cbuf); | |
| 3031 | |
| 3032 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
| 3033 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
| 3034 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
|
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|
3035 Register tmp2_reg = O7; |
| 681 | 3036 Register result_reg = reg_to_register_object($result$$reg); |
| 3037 | |
| 3038 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
| 3039 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
| 3040 | |
| 3041 // return true if the same array | |
| 3042 __ cmp(ary1_reg, ary2_reg); | |
| 1016 | 3043 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 681 | 3044 __ delayed()->add(G0, 1, result_reg); // equal |
| 3045 | |
| 3046 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
| 3047 __ delayed()->mov(G0, result_reg); // not equal | |
| 3048 | |
| 3049 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
| 3050 __ delayed()->mov(G0, result_reg); // not equal | |
| 3051 | |
| 3052 //load the lengths of arrays | |
| 727 | 3053 __ ld(Address(ary1_reg, length_offset), tmp1_reg); |
| 3054 __ ld(Address(ary2_reg, length_offset), tmp2_reg); | |
| 681 | 3055 |
| 3056 // return false if the two arrays are not equal length | |
| 3057 __ cmp(tmp1_reg, tmp2_reg); | |
| 3058 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
| 3059 __ delayed()->mov(G0, result_reg); // not equal | |
| 3060 | |
| 3839 | 3061 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn); |
| 681 | 3062 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
| 3063 | |
| 3064 // load array addresses | |
| 3065 __ add(ary1_reg, base_offset, ary1_reg); | |
| 3066 __ add(ary2_reg, base_offset, ary2_reg); | |
| 3067 | |
| 3068 // renaming registers | |
|
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|
3069 Register chr1_reg = result_reg; // for characters in ary1 |
|
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|
3070 Register chr2_reg = tmp2_reg; // for characters in ary2 |
| 681 | 3071 Register limit_reg = tmp1_reg; // length |
| 3072 | |
| 3073 // set byte count | |
| 3074 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
|
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|
3075 |
|
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|
3076 // Compare char[] arrays aligned to 4 bytes. |
|
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|
3077 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
|
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|
3078 chr1_reg, chr2_reg, Ldone); |
| 681 | 3079 __ add(G0, 1, result_reg); // equals |
| 3080 | |
| 3081 __ bind(Ldone); | |
| 3082 %} | |
| 3083 | |
| 0 | 3084 enc_class enc_rethrow() %{ |
| 1748 | 3085 cbuf.set_insts_mark(); |
| 0 | 3086 Register temp_reg = G3; |
| 727 | 3087 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
| 0 | 3088 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
| 3089 MacroAssembler _masm(&cbuf); | |
| 3090 #ifdef ASSERT | |
| 3091 __ save_frame(0); | |
| 727 | 3092 AddressLiteral last_rethrow_addrlit(&last_rethrow); |
| 3093 __ sethi(last_rethrow_addrlit, L1); | |
| 3094 Address addr(L1, last_rethrow_addrlit.low10()); | |
| 10997 | 3095 __ rdpc(L2); |
| 0 | 3096 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to |
| 727 | 3097 __ st_ptr(L2, addr); |
| 0 | 3098 __ restore(); |
| 3099 #endif | |
| 727 | 3100 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
| 0 | 3101 __ delayed()->nop(); |
| 3102 %} | |
| 3103 | |
| 3104 enc_class emit_mem_nop() %{ | |
| 3105 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
| 1748 | 3106 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); |
| 0 | 3107 %} |
| 3108 | |
| 3109 enc_class emit_fadd_nop() %{ | |
| 3110 // Generates the instruction FMOVS f31,f31 | |
| 1748 | 3111 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); |
| 0 | 3112 %} |
| 3113 | |
| 3114 enc_class emit_br_nop() %{ | |
| 3115 // Generates the instruction BPN,PN . | |
| 1748 | 3116 cbuf.insts()->emit_int32((unsigned int) 0x00400000); |
| 0 | 3117 %} |
| 3118 | |
| 3119 enc_class enc_membar_acquire %{ | |
| 3120 MacroAssembler _masm(&cbuf); | |
| 3121 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
| 3122 %} | |
| 3123 | |
| 3124 enc_class enc_membar_release %{ | |
| 3125 MacroAssembler _masm(&cbuf); | |
| 3126 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
| 3127 %} | |
| 3128 | |
| 3129 enc_class enc_membar_volatile %{ | |
| 3130 MacroAssembler _masm(&cbuf); | |
| 3131 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
| 3132 %} | |
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3133 |
| 0 | 3134 %} |
| 3135 | |
| 3136 //----------FRAME-------------------------------------------------------------- | |
| 3137 // Definition of frame structure and management information. | |
| 3138 // | |
| 3139 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3140 // | (to get allocators register number | |
| 3141 // G Owned by | | v add VMRegImpl::stack0) | |
| 3142 // r CALLER | | | |
| 3143 // o | +--------+ pad to even-align allocators stack-slot | |
| 3144 // w V | pad0 | numbers; owned by CALLER | |
| 3145 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3146 // h ^ | in | 5 | |
| 3147 // | | args | 4 Holes in incoming args owned by SELF | |
| 3148 // | | | | 3 | |
| 3149 // | | +--------+ | |
| 3150 // V | | old out| Empty on Intel, window on Sparc | |
| 3151 // | old |preserve| Must be even aligned. | |
| 3152 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
| 3153 // | | in | 3 area for Intel ret address | |
| 3154 // Owned by |preserve| Empty on Sparc. | |
| 3155 // SELF +--------+ | |
| 3156 // | | pad2 | 2 pad to align old SP | |
| 3157 // | +--------+ 1 | |
| 3158 // | | locks | 0 | |
| 3159 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
| 3160 // | | pad1 | 11 pad to align new SP | |
| 3161 // | +--------+ | |
| 3162 // | | | 10 | |
| 3163 // | | spills | 9 spills | |
| 3164 // V | | 8 (pad0 slot for callee) | |
| 3165 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3166 // ^ | out | 7 | |
| 3167 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3168 // Owned by +--------+ | |
| 3169 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3170 // | new |preserve| Must be even-aligned. | |
| 3171 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3172 // | | | | |
| 3173 // | |
| 3174 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3175 // known from SELF's arguments and the Java calling convention. | |
| 3176 // Region 6-7 is determined per call site. | |
| 3177 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3178 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3179 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3180 // incoming area, as the Java calling convention is completely under | |
| 3181 // the control of the AD file. Doubles can be sorted and packed to | |
| 3182 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3183 // varargs C calling conventions. | |
| 3184 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3185 // even aligned with pad0 as needed. | |
| 3186 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3187 // region 6-11 is even aligned; it may be padded out more so that | |
| 3188 // the region from SP to FP meets the minimum stack alignment. | |
| 3189 | |
| 3190 frame %{ | |
| 3191 // What direction does stack grow in (assumed to be same for native & Java) | |
| 3192 stack_direction(TOWARDS_LOW); | |
| 3193 | |
| 3194 // These two registers define part of the calling convention | |
| 3195 // between compiled code and the interpreter. | |
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3196 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C |
| 0 | 3197 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter |
| 3198 | |
| 3199 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3200 cisc_spilling_operand_name(indOffset); | |
| 3201 | |
| 3202 // Number of stack slots consumed by a Monitor enter | |
| 3203 #ifdef _LP64 | |
| 3204 sync_stack_slots(2); | |
| 3205 #else | |
| 3206 sync_stack_slots(1); | |
| 3207 #endif | |
| 3208 | |
| 3209 // Compiled code's Frame Pointer | |
| 3210 frame_pointer(R_SP); | |
| 3211 | |
| 3212 // Stack alignment requirement | |
| 3213 stack_alignment(StackAlignmentInBytes); | |
| 3214 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
| 3215 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
| 3216 | |
| 3217 // Number of stack slots between incoming argument block and the start of | |
| 3218 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3219 // EPILOG must remove this many slots. | |
| 3220 in_preserve_stack_slots(0); | |
| 3221 | |
| 3222 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3223 // for calls to C. Supports the var-args backing area for register parms. | |
| 3224 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
| 3225 #ifdef _LP64 | |
| 3226 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
| 3227 varargs_C_out_slots_killed(12); | |
| 3228 #else | |
| 3229 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
| 3230 varargs_C_out_slots_killed( 7); | |
| 3231 #endif | |
| 3232 | |
| 3233 // The after-PROLOG location of the return address. Location of | |
| 3234 // return address specifies a type (REG or STACK) and a number | |
| 3235 // representing the register number (i.e. - use a register name) or | |
| 3236 // stack slot. | |
| 3237 return_addr(REG R_I7); // Ret Addr is in register I7 | |
| 3238 | |
| 3239 // Body of function which returns an OptoRegs array locating | |
| 3240 // arguments either in registers or in stack slots for calling | |
| 3241 // java | |
| 3242 calling_convention %{ | |
| 3243 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
| 3244 | |
| 3245 %} | |
| 3246 | |
| 3247 // Body of function which returns an OptoRegs array locating | |
| 3248 // arguments either in registers or in stack slots for callin | |
| 3249 // C. | |
| 3250 c_calling_convention %{ | |
| 3251 // This is obviously always outgoing | |
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3252 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); |
| 0 | 3253 %} |
| 3254 | |
| 3255 // Location of native (C/C++) and interpreter return values. This is specified to | |
| 3256 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
| 3257 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
| 3258 // to and from the register pairs is done by the appropriate call and epilog | |
| 3259 // opcodes. This simplifies the register allocator. | |
| 3260 c_return_value %{ | |
| 3261 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3262 #ifdef _LP64 | |
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3263 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3264 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3265 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3266 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3267 #else // !_LP64 |
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3268 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3269 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
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3270 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3271 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
| 0 | 3272 #endif |
| 3273 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3274 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3275 %} | |
| 3276 | |
| 3277 // Location of compiled Java return values. Same as C | |
| 3278 return_value %{ | |
| 3279 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3280 #ifdef _LP64 | |
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3281 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3282 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3283 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3284 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3285 #else // !_LP64 |
|
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3286 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3287 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
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3288 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3289 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
| 0 | 3290 #endif |
| 3291 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3292 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3293 %} | |
| 3294 | |
| 3295 %} | |
| 3296 | |
| 3297 | |
| 3298 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3299 //----------Operand Attributes------------------------------------------------- | |
| 3300 op_attrib op_cost(1); // Required cost attribute | |
| 3301 | |
| 3302 //----------Instruction Attributes--------------------------------------------- | |
| 3303 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
| 3842 | 3304 ins_attrib ins_size(32); // Required size attribute (in bits) |
| 3851 | 3305 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back |
| 3842 | 3306 ins_attrib ins_short_branch(0); // Required flag: is this instruction a |
| 3307 // non-matching short branch variant of some | |
| 0 | 3308 // long branch? |
| 3309 | |
| 3310 //----------OPERANDS----------------------------------------------------------- | |
| 3311 // Operand definitions must precede instruction definitions for correct parsing | |
| 3312 // in the ADLC because operands constitute user defined types which are used in | |
| 3313 // instruction definitions. | |
| 3314 | |
| 3315 //----------Simple Operands---------------------------------------------------- | |
| 3316 // Immediate Operands | |
| 3317 // Integer Immediate: 32-bit | |
| 3318 operand immI() %{ | |
| 3319 match(ConI); | |
| 3320 | |
| 3321 op_cost(0); | |
| 3322 // formats are generated automatically for constants and base registers | |
| 3323 format %{ %} | |
| 3324 interface(CONST_INTER); | |
| 3325 %} | |
| 3326 | |
| 824 | 3327 // Integer Immediate: 8-bit |
| 3328 operand immI8() %{ | |
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3329 predicate(Assembler::is_simm8(n->get_int())); |
| 824 | 3330 match(ConI); |
| 3331 op_cost(0); | |
| 3332 format %{ %} | |
| 3333 interface(CONST_INTER); | |
| 3334 %} | |
| 3335 | |
| 0 | 3336 // Integer Immediate: 13-bit |
| 3337 operand immI13() %{ | |
| 3338 predicate(Assembler::is_simm13(n->get_int())); | |
| 3339 match(ConI); | |
| 3340 op_cost(0); | |
| 3341 | |
| 3342 format %{ %} | |
| 3343 interface(CONST_INTER); | |
| 3344 %} | |
| 3345 | |
| 785 | 3346 // Integer Immediate: 13-bit minus 7 |
| 3347 operand immI13m7() %{ | |
| 3348 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); | |
| 3349 match(ConI); | |
| 3350 op_cost(0); | |
| 3351 | |
| 3352 format %{ %} | |
| 3353 interface(CONST_INTER); | |
| 3354 %} | |
| 3355 | |
| 824 | 3356 // Integer Immediate: 16-bit |
| 3357 operand immI16() %{ | |
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3358 predicate(Assembler::is_simm16(n->get_int())); |
| 824 | 3359 match(ConI); |
| 3360 op_cost(0); | |
| 3361 format %{ %} | |
| 3362 interface(CONST_INTER); | |
| 3363 %} | |
| 3364 | |
| 0 | 3365 // Unsigned (positive) Integer Immediate: 13-bit |
| 3366 operand immU13() %{ | |
| 3367 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | |
| 3368 match(ConI); | |
| 3369 op_cost(0); | |
| 3370 | |
| 3371 format %{ %} | |
| 3372 interface(CONST_INTER); | |
| 3373 %} | |
| 3374 | |
| 3375 // Integer Immediate: 6-bit | |
| 3376 operand immU6() %{ | |
| 3377 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
| 3378 match(ConI); | |
| 3379 op_cost(0); | |
| 3380 format %{ %} | |
| 3381 interface(CONST_INTER); | |
| 3382 %} | |
| 3383 | |
| 3384 // Integer Immediate: 11-bit | |
| 3385 operand immI11() %{ | |
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3386 predicate(Assembler::is_simm11(n->get_int())); |
| 0 | 3387 match(ConI); |
| 3388 op_cost(0); | |
| 3389 format %{ %} | |
| 3390 interface(CONST_INTER); | |
| 3391 %} | |
| 3392 | |
| 3851 | 3393 // Integer Immediate: 5-bit |
| 3394 operand immI5() %{ | |
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3395 predicate(Assembler::is_simm5(n->get_int())); |
| 3851 | 3396 match(ConI); |
| 3397 op_cost(0); | |
| 3398 format %{ %} | |
| 3399 interface(CONST_INTER); | |
| 3400 %} | |
| 3401 | |
| 0 | 3402 // Integer Immediate: 0-bit |
| 3403 operand immI0() %{ | |
| 3404 predicate(n->get_int() == 0); | |
| 3405 match(ConI); | |
| 3406 op_cost(0); | |
| 3407 | |
| 3408 format %{ %} | |
| 3409 interface(CONST_INTER); | |
| 3410 %} | |
| 3411 | |
| 3412 // Integer Immediate: the value 10 | |
| 3413 operand immI10() %{ | |
| 3414 predicate(n->get_int() == 10); | |
| 3415 match(ConI); | |
| 3416 op_cost(0); | |
| 3417 | |
| 3418 format %{ %} | |
| 3419 interface(CONST_INTER); | |
| 3420 %} | |
| 3421 | |
| 3422 // Integer Immediate: the values 0-31 | |
| 3423 operand immU5() %{ | |
| 3424 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
| 3425 match(ConI); | |
| 3426 op_cost(0); | |
| 3427 | |
| 3428 format %{ %} | |
| 3429 interface(CONST_INTER); | |
| 3430 %} | |
| 3431 | |
| 3432 // Integer Immediate: the values 1-31 | |
| 3433 operand immI_1_31() %{ | |
| 3434 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
| 3435 match(ConI); | |
| 3436 op_cost(0); | |
| 3437 | |
| 3438 format %{ %} | |
| 3439 interface(CONST_INTER); | |
| 3440 %} | |
| 3441 | |
| 3442 // Integer Immediate: the values 32-63 | |
| 3443 operand immI_32_63() %{ | |
| 3444 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
| 3445 match(ConI); | |
| 3446 op_cost(0); | |
| 3447 | |
| 3448 format %{ %} | |
| 3449 interface(CONST_INTER); | |
| 3450 %} | |
| 3451 | |
| 785 | 3452 // Immediates for special shifts (sign extend) |
| 3453 | |
| 3454 // Integer Immediate: the value 16 | |
| 3455 operand immI_16() %{ | |
| 3456 predicate(n->get_int() == 16); | |
| 3457 match(ConI); | |
| 3458 op_cost(0); | |
| 3459 | |
| 3460 format %{ %} | |
| 3461 interface(CONST_INTER); | |
| 3462 %} | |
| 3463 | |
| 3464 // Integer Immediate: the value 24 | |
| 3465 operand immI_24() %{ | |
| 3466 predicate(n->get_int() == 24); | |
| 3467 match(ConI); | |
| 3468 op_cost(0); | |
| 3469 | |
| 3470 format %{ %} | |
| 3471 interface(CONST_INTER); | |
| 3472 %} | |
| 3473 | |
| 0 | 3474 // Integer Immediate: the value 255 |
| 3475 operand immI_255() %{ | |
| 3476 predicate( n->get_int() == 255 ); | |
| 3477 match(ConI); | |
| 3478 op_cost(0); | |
| 3479 | |
| 3480 format %{ %} | |
| 3481 interface(CONST_INTER); | |
| 3482 %} | |
| 3483 | |
| 785 | 3484 // Integer Immediate: the value 65535 |
| 3485 operand immI_65535() %{ | |
| 3486 predicate(n->get_int() == 65535); | |
| 3487 match(ConI); | |
| 3488 op_cost(0); | |
| 3489 | |
| 3490 format %{ %} | |
| 3491 interface(CONST_INTER); | |
| 3492 %} | |
| 3493 | |
| 0 | 3494 // Long Immediate: the value FF |
| 3495 operand immL_FF() %{ | |
| 3496 predicate( n->get_long() == 0xFFL ); | |
| 3497 match(ConL); | |
| 3498 op_cost(0); | |
| 3499 | |
| 3500 format %{ %} | |
| 3501 interface(CONST_INTER); | |
| 3502 %} | |
| 3503 | |
| 3504 // Long Immediate: the value FFFF | |
| 3505 operand immL_FFFF() %{ | |
| 3506 predicate( n->get_long() == 0xFFFFL ); | |
| 3507 match(ConL); | |
| 3508 op_cost(0); | |
| 3509 | |
| 3510 format %{ %} | |
| 3511 interface(CONST_INTER); | |
| 3512 %} | |
| 3513 | |
| 3514 // Pointer Immediate: 32 or 64-bit | |
| 3515 operand immP() %{ | |
| 3516 match(ConP); | |
| 3517 | |
| 3518 op_cost(5); | |
| 3519 // formats are generated automatically for constants and base registers | |
| 3520 format %{ %} | |
| 3521 interface(CONST_INTER); | |
| 3522 %} | |
| 3523 | |
|
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3524 #ifdef _LP64 |
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3525 // Pointer Immediate: 64-bit |
| 2008 | 3526 operand immP_set() %{ |
| 2080 | 3527 predicate(!VM_Version::is_niagara_plus()); |
| 2008 | 3528 match(ConP); |
| 3529 | |
| 3530 op_cost(5); | |
| 3531 // formats are generated automatically for constants and base registers | |
| 3532 format %{ %} | |
| 3533 interface(CONST_INTER); | |
| 3534 %} | |
| 3535 | |
|
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3536 // Pointer Immediate: 64-bit |
| 2008 | 3537 // From Niagara2 processors on a load should be better than materializing. |
| 3538 operand immP_load() %{ | |
| 2080 | 3539 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); |
| 2008 | 3540 match(ConP); |
| 3541 | |
| 3542 op_cost(5); | |
| 3543 // formats are generated automatically for constants and base registers | |
| 3544 format %{ %} | |
| 3545 interface(CONST_INTER); | |
| 3546 %} | |
| 3547 | |
|
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3548 // Pointer Immediate: 64-bit |
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3549 operand immP_no_oop_cheap() %{ |
| 2080 | 3550 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); |
|
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3551 match(ConP); |
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3552 |
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3553 op_cost(5); |
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3554 // formats are generated automatically for constants and base registers |
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3555 format %{ %} |
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3556 interface(CONST_INTER); |
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3557 %} |
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3558 #endif |
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3559 |
| 0 | 3560 operand immP13() %{ |
| 3561 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
| 3562 match(ConP); | |
| 3563 op_cost(0); | |
| 3564 | |
| 3565 format %{ %} | |
| 3566 interface(CONST_INTER); | |
| 3567 %} | |
| 3568 | |
| 3569 operand immP0() %{ | |
| 3570 predicate(n->get_ptr() == 0); | |
| 3571 match(ConP); | |
| 3572 op_cost(0); | |
| 3573 | |
| 3574 format %{ %} | |
| 3575 interface(CONST_INTER); | |
| 3576 %} | |
| 3577 | |
| 3578 operand immP_poll() %{ | |
| 3579 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
| 3580 match(ConP); | |
| 3581 | |
| 3582 // formats are generated automatically for constants and base registers | |
| 3583 format %{ %} | |
| 3584 interface(CONST_INTER); | |
| 3585 %} | |
| 3586 | |
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3587 // Pointer Immediate |
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3588 operand immN() |
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3589 %{ |
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3590 match(ConN); |
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3591 |
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3592 op_cost(10); |
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3593 format %{ %} |
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3594 interface(CONST_INTER); |
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3595 %} |
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3596 |
|
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3597 operand immNKlass() |
|
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|
3598 %{ |
|
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|
3599 match(ConNKlass); |
|
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|
3600 |
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|
3601 op_cost(10); |
|
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3602 format %{ %} |
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|
3603 interface(CONST_INTER); |
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3604 %} |
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3605 |
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3606 // NULL Pointer Immediate |
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3607 operand immN0() |
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3608 %{ |
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3609 predicate(n->get_narrowcon() == 0); |
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3610 match(ConN); |
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3611 |
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3612 op_cost(0); |
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3613 format %{ %} |
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3614 interface(CONST_INTER); |
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3615 %} |
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3616 |
| 0 | 3617 operand immL() %{ |
| 3618 match(ConL); | |
| 3619 op_cost(40); | |
| 3620 // formats are generated automatically for constants and base registers | |
| 3621 format %{ %} | |
| 3622 interface(CONST_INTER); | |
| 3623 %} | |
| 3624 | |
| 3625 operand immL0() %{ | |
| 3626 predicate(n->get_long() == 0L); | |
| 3627 match(ConL); | |
| 3628 op_cost(0); | |
| 3629 // formats are generated automatically for constants and base registers | |
| 3630 format %{ %} | |
| 3631 interface(CONST_INTER); | |
| 3632 %} | |
| 3633 | |
| 3851 | 3634 // Integer Immediate: 5-bit |
| 3635 operand immL5() %{ | |
|
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3636 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long())); |
| 3851 | 3637 match(ConL); |
| 3638 op_cost(0); | |
| 3639 format %{ %} | |
| 3640 interface(CONST_INTER); | |
| 3641 %} | |
| 3642 | |
| 0 | 3643 // Long Immediate: 13-bit |
| 3644 operand immL13() %{ | |
| 3645 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
| 3646 match(ConL); | |
| 3647 op_cost(0); | |
| 3648 | |
| 3649 format %{ %} | |
| 3650 interface(CONST_INTER); | |
| 3651 %} | |
| 3652 | |
| 785 | 3653 // Long Immediate: 13-bit minus 7 |
| 3654 operand immL13m7() %{ | |
| 3655 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); | |
| 3656 match(ConL); | |
| 3657 op_cost(0); | |
| 3658 | |
| 3659 format %{ %} | |
| 3660 interface(CONST_INTER); | |
| 3661 %} | |
| 3662 | |
| 0 | 3663 // Long Immediate: low 32-bit mask |
| 3664 operand immL_32bits() %{ | |
| 3665 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3666 match(ConL); | |
| 3667 op_cost(0); | |
| 3668 | |
| 3669 format %{ %} | |
| 3670 interface(CONST_INTER); | |
| 3671 %} | |
| 3672 | |
| 2008 | 3673 // Long Immediate: cheap (materialize in <= 3 instructions) |
| 3674 operand immL_cheap() %{ | |
| 2080 | 3675 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); |
| 2008 | 3676 match(ConL); |
| 3677 op_cost(0); | |
| 3678 | |
| 3679 format %{ %} | |
| 3680 interface(CONST_INTER); | |
| 3681 %} | |
| 3682 | |
| 3683 // Long Immediate: expensive (materialize in > 3 instructions) | |
| 3684 operand immL_expensive() %{ | |
| 2080 | 3685 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3); |
| 2008 | 3686 match(ConL); |
| 3687 op_cost(0); | |
| 3688 | |
| 3689 format %{ %} | |
| 3690 interface(CONST_INTER); | |
| 3691 %} | |
| 3692 | |
| 0 | 3693 // Double Immediate |
| 3694 operand immD() %{ | |
| 3695 match(ConD); | |
| 3696 | |
| 3697 op_cost(40); | |
| 3698 format %{ %} | |
| 3699 interface(CONST_INTER); | |
| 3700 %} | |
| 3701 | |
| 3702 operand immD0() %{ | |
| 3703 #ifdef _LP64 | |
| 3704 // on 64-bit architectures this comparision is faster | |
| 3705 predicate(jlong_cast(n->getd()) == 0); | |
| 3706 #else | |
| 3707 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
| 3708 #endif | |
| 3709 match(ConD); | |
| 3710 | |
| 3711 op_cost(0); | |
| 3712 format %{ %} | |
| 3713 interface(CONST_INTER); | |
| 3714 %} | |
| 3715 | |
| 3716 // Float Immediate | |
| 3717 operand immF() %{ | |
| 3718 match(ConF); | |
| 3719 | |
| 3720 op_cost(20); | |
| 3721 format %{ %} | |
| 3722 interface(CONST_INTER); | |
| 3723 %} | |
| 3724 | |
| 3725 // Float Immediate: 0 | |
| 3726 operand immF0() %{ | |
| 3727 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
| 3728 match(ConF); | |
| 3729 | |
| 3730 op_cost(0); | |
| 3731 format %{ %} | |
| 3732 interface(CONST_INTER); | |
| 3733 %} | |
| 3734 | |
| 3735 // Integer Register Operands | |
| 3736 // Integer Register | |
| 3737 operand iRegI() %{ | |
| 3738 constraint(ALLOC_IN_RC(int_reg)); | |
| 3739 match(RegI); | |
| 3740 | |
| 3741 match(notemp_iRegI); | |
| 3742 match(g1RegI); | |
| 3743 match(o0RegI); | |
| 3744 match(iRegIsafe); | |
| 3745 | |
| 3746 format %{ %} | |
| 3747 interface(REG_INTER); | |
| 3748 %} | |
| 3749 | |
| 3750 operand notemp_iRegI() %{ | |
| 3751 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
| 3752 match(RegI); | |
| 3753 | |
| 3754 match(o0RegI); | |
| 3755 | |
| 3756 format %{ %} | |
| 3757 interface(REG_INTER); | |
| 3758 %} | |
| 3759 | |
| 3760 operand o0RegI() %{ | |
| 3761 constraint(ALLOC_IN_RC(o0_regI)); | |
| 3762 match(iRegI); | |
| 3763 | |
| 3764 format %{ %} | |
| 3765 interface(REG_INTER); | |
| 3766 %} | |
| 3767 | |
| 3768 // Pointer Register | |
| 3769 operand iRegP() %{ | |
| 3770 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3771 match(RegP); | |
| 3772 | |
| 3773 match(lock_ptr_RegP); | |
| 3774 match(g1RegP); | |
| 3775 match(g2RegP); | |
| 3776 match(g3RegP); | |
| 3777 match(g4RegP); | |
| 3778 match(i0RegP); | |
| 3779 match(o0RegP); | |
| 3780 match(o1RegP); | |
| 3781 match(l7RegP); | |
| 3782 | |
| 3783 format %{ %} | |
| 3784 interface(REG_INTER); | |
| 3785 %} | |
| 3786 | |
| 3787 operand sp_ptr_RegP() %{ | |
| 3788 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 3789 match(RegP); | |
| 3790 match(iRegP); | |
| 3791 | |
| 3792 format %{ %} | |
| 3793 interface(REG_INTER); | |
| 3794 %} | |
| 3795 | |
| 3796 operand lock_ptr_RegP() %{ | |
| 3797 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
| 3798 match(RegP); | |
| 3799 match(i0RegP); | |
| 3800 match(o0RegP); | |
| 3801 match(o1RegP); | |
| 3802 match(l7RegP); | |
| 3803 | |
| 3804 format %{ %} | |
| 3805 interface(REG_INTER); | |
| 3806 %} | |
| 3807 | |
| 3808 operand g1RegP() %{ | |
| 3809 constraint(ALLOC_IN_RC(g1_regP)); | |
| 3810 match(iRegP); | |
| 3811 | |
| 3812 format %{ %} | |
| 3813 interface(REG_INTER); | |
| 3814 %} | |
| 3815 | |
| 3816 operand g2RegP() %{ | |
| 3817 constraint(ALLOC_IN_RC(g2_regP)); | |
| 3818 match(iRegP); | |
| 3819 | |
| 3820 format %{ %} | |
| 3821 interface(REG_INTER); | |
| 3822 %} | |
| 3823 | |
| 3824 operand g3RegP() %{ | |
| 3825 constraint(ALLOC_IN_RC(g3_regP)); | |
| 3826 match(iRegP); | |
| 3827 | |
| 3828 format %{ %} | |
| 3829 interface(REG_INTER); | |
| 3830 %} | |
| 3831 | |
| 3832 operand g1RegI() %{ | |
| 3833 constraint(ALLOC_IN_RC(g1_regI)); | |
| 3834 match(iRegI); | |
| 3835 | |
| 3836 format %{ %} | |
| 3837 interface(REG_INTER); | |
| 3838 %} | |
| 3839 | |
| 3840 operand g3RegI() %{ | |
| 3841 constraint(ALLOC_IN_RC(g3_regI)); | |
| 3842 match(iRegI); | |
| 3843 | |
| 3844 format %{ %} | |
| 3845 interface(REG_INTER); | |
| 3846 %} | |
| 3847 | |
| 3848 operand g4RegI() %{ | |
| 3849 constraint(ALLOC_IN_RC(g4_regI)); | |
| 3850 match(iRegI); | |
| 3851 | |
| 3852 format %{ %} | |
| 3853 interface(REG_INTER); | |
| 3854 %} | |
| 3855 | |
| 3856 operand g4RegP() %{ | |
| 3857 constraint(ALLOC_IN_RC(g4_regP)); | |
| 3858 match(iRegP); | |
| 3859 | |
| 3860 format %{ %} | |
| 3861 interface(REG_INTER); | |
| 3862 %} | |
| 3863 | |
| 3864 operand i0RegP() %{ | |
| 3865 constraint(ALLOC_IN_RC(i0_regP)); | |
| 3866 match(iRegP); | |
| 3867 | |
| 3868 format %{ %} | |
| 3869 interface(REG_INTER); | |
| 3870 %} | |
| 3871 | |
| 3872 operand o0RegP() %{ | |
| 3873 constraint(ALLOC_IN_RC(o0_regP)); | |
| 3874 match(iRegP); | |
| 3875 | |
| 3876 format %{ %} | |
| 3877 interface(REG_INTER); | |
| 3878 %} | |
| 3879 | |
| 3880 operand o1RegP() %{ | |
| 3881 constraint(ALLOC_IN_RC(o1_regP)); | |
| 3882 match(iRegP); | |
| 3883 | |
| 3884 format %{ %} | |
| 3885 interface(REG_INTER); | |
| 3886 %} | |
| 3887 | |
| 3888 operand o2RegP() %{ | |
| 3889 constraint(ALLOC_IN_RC(o2_regP)); | |
| 3890 match(iRegP); | |
| 3891 | |
| 3892 format %{ %} | |
| 3893 interface(REG_INTER); | |
| 3894 %} | |
| 3895 | |
| 3896 operand o7RegP() %{ | |
| 3897 constraint(ALLOC_IN_RC(o7_regP)); | |
| 3898 match(iRegP); | |
| 3899 | |
| 3900 format %{ %} | |
| 3901 interface(REG_INTER); | |
| 3902 %} | |
| 3903 | |
| 3904 operand l7RegP() %{ | |
| 3905 constraint(ALLOC_IN_RC(l7_regP)); | |
| 3906 match(iRegP); | |
| 3907 | |
| 3908 format %{ %} | |
| 3909 interface(REG_INTER); | |
| 3910 %} | |
| 3911 | |
| 3912 operand o7RegI() %{ | |
| 3913 constraint(ALLOC_IN_RC(o7_regI)); | |
| 3914 match(iRegI); | |
| 3915 | |
| 3916 format %{ %} | |
| 3917 interface(REG_INTER); | |
| 3918 %} | |
| 3919 | |
|
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3920 operand iRegN() %{ |
|
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3921 constraint(ALLOC_IN_RC(int_reg)); |
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3922 match(RegN); |
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3923 |
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3924 format %{ %} |
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3925 interface(REG_INTER); |
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3926 %} |
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3927 |
| 0 | 3928 // Long Register |
| 3929 operand iRegL() %{ | |
| 3930 constraint(ALLOC_IN_RC(long_reg)); | |
| 3931 match(RegL); | |
| 3932 | |
| 3933 format %{ %} | |
| 3934 interface(REG_INTER); | |
| 3935 %} | |
| 3936 | |
| 3937 operand o2RegL() %{ | |
| 3938 constraint(ALLOC_IN_RC(o2_regL)); | |
| 3939 match(iRegL); | |
| 3940 | |
| 3941 format %{ %} | |
| 3942 interface(REG_INTER); | |
| 3943 %} | |
| 3944 | |
| 3945 operand o7RegL() %{ | |
| 3946 constraint(ALLOC_IN_RC(o7_regL)); | |
| 3947 match(iRegL); | |
| 3948 | |
| 3949 format %{ %} | |
| 3950 interface(REG_INTER); | |
| 3951 %} | |
| 3952 | |
| 3953 operand g1RegL() %{ | |
| 3954 constraint(ALLOC_IN_RC(g1_regL)); | |
| 3955 match(iRegL); | |
| 3956 | |
| 3957 format %{ %} | |
| 3958 interface(REG_INTER); | |
| 3959 %} | |
| 3960 | |
|
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3961 operand g3RegL() %{ |
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3962 constraint(ALLOC_IN_RC(g3_regL)); |
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3963 match(iRegL); |
|
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3964 |
|
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3965 format %{ %} |
|
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3966 interface(REG_INTER); |
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3967 %} |
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3968 |
| 0 | 3969 // Int Register safe |
| 3970 // This is 64bit safe | |
| 3971 operand iRegIsafe() %{ | |
| 3972 constraint(ALLOC_IN_RC(long_reg)); | |
| 3973 | |
| 3974 match(iRegI); | |
| 3975 | |
| 3976 format %{ %} | |
| 3977 interface(REG_INTER); | |
| 3978 %} | |
| 3979 | |
| 3980 // Condition Code Flag Register | |
| 3981 operand flagsReg() %{ | |
| 3982 constraint(ALLOC_IN_RC(int_flags)); | |
| 3983 match(RegFlags); | |
| 3984 | |
| 3985 format %{ "ccr" %} // both ICC and XCC | |
| 3986 interface(REG_INTER); | |
| 3987 %} | |
| 3988 | |
| 3989 // Condition Code Register, unsigned comparisons. | |
| 3990 operand flagsRegU() %{ | |
| 3991 constraint(ALLOC_IN_RC(int_flags)); | |
| 3992 match(RegFlags); | |
| 3993 | |
| 3994 format %{ "icc_U" %} | |
| 3995 interface(REG_INTER); | |
| 3996 %} | |
| 3997 | |
| 3998 // Condition Code Register, pointer comparisons. | |
| 3999 operand flagsRegP() %{ | |
| 4000 constraint(ALLOC_IN_RC(int_flags)); | |
| 4001 match(RegFlags); | |
| 4002 | |
| 4003 #ifdef _LP64 | |
| 4004 format %{ "xcc_P" %} | |
| 4005 #else | |
| 4006 format %{ "icc_P" %} | |
| 4007 #endif | |
| 4008 interface(REG_INTER); | |
| 4009 %} | |
| 4010 | |
| 4011 // Condition Code Register, long comparisons. | |
| 4012 operand flagsRegL() %{ | |
| 4013 constraint(ALLOC_IN_RC(int_flags)); | |
| 4014 match(RegFlags); | |
| 4015 | |
| 4016 format %{ "xcc_L" %} | |
| 4017 interface(REG_INTER); | |
| 4018 %} | |
| 4019 | |
| 4020 // Condition Code Register, floating comparisons, unordered same as "less". | |
| 4021 operand flagsRegF() %{ | |
| 4022 constraint(ALLOC_IN_RC(float_flags)); | |
| 4023 match(RegFlags); | |
| 4024 match(flagsRegF0); | |
| 4025 | |
| 4026 format %{ %} | |
| 4027 interface(REG_INTER); | |
| 4028 %} | |
| 4029 | |
| 4030 operand flagsRegF0() %{ | |
| 4031 constraint(ALLOC_IN_RC(float_flag0)); | |
| 4032 match(RegFlags); | |
| 4033 | |
| 4034 format %{ %} | |
| 4035 interface(REG_INTER); | |
| 4036 %} | |
| 4037 | |
| 4038 | |
| 4039 // Condition Code Flag Register used by long compare | |
| 4040 operand flagsReg_long_LTGE() %{ | |
| 4041 constraint(ALLOC_IN_RC(int_flags)); | |
| 4042 match(RegFlags); | |
| 4043 format %{ "icc_LTGE" %} | |
| 4044 interface(REG_INTER); | |
| 4045 %} | |
| 4046 operand flagsReg_long_EQNE() %{ | |
| 4047 constraint(ALLOC_IN_RC(int_flags)); | |
| 4048 match(RegFlags); | |
| 4049 format %{ "icc_EQNE" %} | |
| 4050 interface(REG_INTER); | |
| 4051 %} | |
| 4052 operand flagsReg_long_LEGT() %{ | |
| 4053 constraint(ALLOC_IN_RC(int_flags)); | |
| 4054 match(RegFlags); | |
| 4055 format %{ "icc_LEGT" %} | |
| 4056 interface(REG_INTER); | |
| 4057 %} | |
| 4058 | |
| 4059 | |
| 4060 operand regD() %{ | |
| 4061 constraint(ALLOC_IN_RC(dflt_reg)); | |
| 4062 match(RegD); | |
| 4063 | |
| 551 | 4064 match(regD_low); |
| 4065 | |
| 0 | 4066 format %{ %} |
| 4067 interface(REG_INTER); | |
| 4068 %} | |
| 4069 | |
| 4070 operand regF() %{ | |
| 4071 constraint(ALLOC_IN_RC(sflt_reg)); | |
| 4072 match(RegF); | |
| 4073 | |
| 4074 format %{ %} | |
| 4075 interface(REG_INTER); | |
| 4076 %} | |
| 4077 | |
| 4078 operand regD_low() %{ | |
| 4079 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
| 551 | 4080 match(regD); |
| 0 | 4081 |
| 4082 format %{ %} | |
| 4083 interface(REG_INTER); | |
| 4084 %} | |
| 4085 | |
| 4086 // Special Registers | |
| 4087 | |
| 4088 // Method Register | |
| 4089 operand inline_cache_regP(iRegP reg) %{ | |
| 4090 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
| 4091 match(reg); | |
| 4092 format %{ %} | |
| 4093 interface(REG_INTER); | |
| 4094 %} | |
| 4095 | |
| 4096 operand interpreter_method_oop_regP(iRegP reg) %{ | |
| 4097 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
| 4098 match(reg); | |
| 4099 format %{ %} | |
| 4100 interface(REG_INTER); | |
| 4101 %} | |
| 4102 | |
| 4103 | |
| 4104 //----------Complex Operands--------------------------------------------------- | |
| 4105 // Indirect Memory Reference | |
| 4106 operand indirect(sp_ptr_RegP reg) %{ | |
| 4107 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4108 match(reg); | |
| 4109 | |
| 4110 op_cost(100); | |
| 4111 format %{ "[$reg]" %} | |
| 4112 interface(MEMORY_INTER) %{ | |
| 4113 base($reg); | |
| 4114 index(0x0); | |
| 4115 scale(0x0); | |
| 4116 disp(0x0); | |
| 4117 %} | |
| 4118 %} | |
| 4119 | |
| 785 | 4120 // Indirect with simm13 Offset |
| 0 | 4121 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
| 4122 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4123 match(AddP reg offset); | |
| 4124 | |
| 4125 op_cost(100); | |
| 4126 format %{ "[$reg + $offset]" %} | |
| 4127 interface(MEMORY_INTER) %{ | |
| 4128 base($reg); | |
| 4129 index(0x0); | |
| 4130 scale(0x0); | |
| 4131 disp($offset); | |
| 4132 %} | |
| 4133 %} | |
| 4134 | |
| 785 | 4135 // Indirect with simm13 Offset minus 7 |
| 4136 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ | |
| 4137 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4138 match(AddP reg offset); | |
| 4139 | |
| 4140 op_cost(100); | |
| 4141 format %{ "[$reg + $offset]" %} | |
| 4142 interface(MEMORY_INTER) %{ | |
| 4143 base($reg); | |
| 4144 index(0x0); | |
| 4145 scale(0x0); | |
| 4146 disp($offset); | |
| 4147 %} | |
| 4148 %} | |
| 4149 | |
| 0 | 4150 // Note: Intel has a swapped version also, like this: |
| 4151 //operand indOffsetX(iRegI reg, immP offset) %{ | |
| 4152 // constraint(ALLOC_IN_RC(int_reg)); | |
| 4153 // match(AddP offset reg); | |
| 4154 // | |
| 4155 // op_cost(100); | |
| 4156 // format %{ "[$reg + $offset]" %} | |
| 4157 // interface(MEMORY_INTER) %{ | |
| 4158 // base($reg); | |
| 4159 // index(0x0); | |
| 4160 // scale(0x0); | |
| 4161 // disp($offset); | |
| 4162 // %} | |
| 4163 //%} | |
| 4164 //// However, it doesn't make sense for SPARC, since | |
| 4165 // we have no particularly good way to embed oops in | |
| 4166 // single instructions. | |
| 4167 | |
| 4168 // Indirect with Register Index | |
| 4169 operand indIndex(iRegP addr, iRegX index) %{ | |
| 4170 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4171 match(AddP addr index); | |
| 4172 | |
| 4173 op_cost(100); | |
| 4174 format %{ "[$addr + $index]" %} | |
| 4175 interface(MEMORY_INTER) %{ | |
| 4176 base($addr); | |
| 4177 index($index); | |
| 4178 scale(0x0); | |
| 4179 disp(0x0); | |
| 4180 %} | |
| 4181 %} | |
| 4182 | |
| 4183 //----------Special Memory Operands-------------------------------------------- | |
| 4184 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4185 // values on the stack where a match requires a value to | |
| 4186 // flow through memory. | |
| 4187 operand stackSlotI(sRegI reg) %{ | |
| 4188 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4189 op_cost(100); | |
| 4190 //match(RegI); | |
| 4191 format %{ "[$reg]" %} | |
| 4192 interface(MEMORY_INTER) %{ | |
| 4193 base(0xE); // R_SP | |
| 4194 index(0x0); | |
| 4195 scale(0x0); | |
| 4196 disp($reg); // Stack Offset | |
| 4197 %} | |
| 4198 %} | |
| 4199 | |
| 4200 operand stackSlotP(sRegP reg) %{ | |
| 4201 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4202 op_cost(100); | |
| 4203 //match(RegP); | |
| 4204 format %{ "[$reg]" %} | |
| 4205 interface(MEMORY_INTER) %{ | |
| 4206 base(0xE); // R_SP | |
| 4207 index(0x0); | |
| 4208 scale(0x0); | |
| 4209 disp($reg); // Stack Offset | |
| 4210 %} | |
| 4211 %} | |
| 4212 | |
| 4213 operand stackSlotF(sRegF reg) %{ | |
| 4214 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4215 op_cost(100); | |
| 4216 //match(RegF); | |
| 4217 format %{ "[$reg]" %} | |
| 4218 interface(MEMORY_INTER) %{ | |
| 4219 base(0xE); // R_SP | |
| 4220 index(0x0); | |
| 4221 scale(0x0); | |
| 4222 disp($reg); // Stack Offset | |
| 4223 %} | |
| 4224 %} | |
| 4225 operand stackSlotD(sRegD reg) %{ | |
| 4226 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4227 op_cost(100); | |
| 4228 //match(RegD); | |
| 4229 format %{ "[$reg]" %} | |
| 4230 interface(MEMORY_INTER) %{ | |
| 4231 base(0xE); // R_SP | |
| 4232 index(0x0); | |
| 4233 scale(0x0); | |
| 4234 disp($reg); // Stack Offset | |
| 4235 %} | |
| 4236 %} | |
| 4237 operand stackSlotL(sRegL reg) %{ | |
| 4238 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4239 op_cost(100); | |
| 4240 //match(RegL); | |
| 4241 format %{ "[$reg]" %} | |
| 4242 interface(MEMORY_INTER) %{ | |
| 4243 base(0xE); // R_SP | |
| 4244 index(0x0); | |
| 4245 scale(0x0); | |
| 4246 disp($reg); // Stack Offset | |
| 4247 %} | |
| 4248 %} | |
| 4249 | |
| 4250 // Operands for expressing Control Flow | |
| 4251 // NOTE: Label is a predefined operand which should not be redefined in | |
| 4252 // the AD file. It is generically handled within the ADLC. | |
| 4253 | |
| 4254 //----------Conditional Branch Operands---------------------------------------- | |
| 4255 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4256 // the following set of codes: | |
| 4257 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4258 // | |
| 4259 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4260 // by the comparison instruction that sets a condition code flags register. | |
| 4261 // That result is represented by a flags operand whose subtype is appropriate | |
| 4262 // to the unsignedness (etc.) of the comparison. | |
| 4263 // | |
| 4264 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4265 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4266 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4267 | |
| 4268 operand cmpOp() %{ | |
| 4269 match(Bool); | |
| 4270 | |
| 4271 format %{ "" %} | |
| 4272 interface(COND_INTER) %{ | |
| 4273 equal(0x1); | |
| 4274 not_equal(0x9); | |
| 4275 less(0x3); | |
| 4276 greater_equal(0xB); | |
| 4277 less_equal(0x2); | |
| 4278 greater(0xA); | |
| 12323 | 4279 overflow(0x7); |
| 4280 no_overflow(0xF); | |
| 0 | 4281 %} |
| 4282 %} | |
| 4283 | |
| 4284 // Comparison Op, unsigned | |
| 4285 operand cmpOpU() %{ | |
| 4286 match(Bool); | |
| 12323 | 4287 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
| 4288 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
| 0 | 4289 |
| 4290 format %{ "u" %} | |
| 4291 interface(COND_INTER) %{ | |
| 4292 equal(0x1); | |
| 4293 not_equal(0x9); | |
| 4294 less(0x5); | |
| 4295 greater_equal(0xD); | |
| 4296 less_equal(0x4); | |
| 4297 greater(0xC); | |
| 12323 | 4298 overflow(0x7); |
| 4299 no_overflow(0xF); | |
| 0 | 4300 %} |
| 4301 %} | |
| 4302 | |
| 4303 // Comparison Op, pointer (same as unsigned) | |
| 4304 operand cmpOpP() %{ | |
| 4305 match(Bool); | |
| 12323 | 4306 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
| 4307 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
| 0 | 4308 |
| 4309 format %{ "p" %} | |
| 4310 interface(COND_INTER) %{ | |
| 4311 equal(0x1); | |
| 4312 not_equal(0x9); | |
| 4313 less(0x5); | |
| 4314 greater_equal(0xD); | |
| 4315 less_equal(0x4); | |
| 4316 greater(0xC); | |
| 12323 | 4317 overflow(0x7); |
| 4318 no_overflow(0xF); | |
| 0 | 4319 %} |
| 4320 %} | |
| 4321 | |
| 4322 // Comparison Op, branch-register encoding | |
| 4323 operand cmpOp_reg() %{ | |
| 4324 match(Bool); | |
| 12323 | 4325 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
| 4326 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
| 0 | 4327 |
| 4328 format %{ "" %} | |
| 4329 interface(COND_INTER) %{ | |
| 4330 equal (0x1); | |
| 4331 not_equal (0x5); | |
| 4332 less (0x3); | |
| 4333 greater_equal(0x7); | |
| 4334 less_equal (0x2); | |
| 4335 greater (0x6); | |
| 12323 | 4336 overflow(0x7); // not supported |
| 4337 no_overflow(0xF); // not supported | |
| 0 | 4338 %} |
| 4339 %} | |
| 4340 | |
| 4341 // Comparison Code, floating, unordered same as less | |
| 4342 operand cmpOpF() %{ | |
| 4343 match(Bool); | |
| 12323 | 4344 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
| 4345 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
| 0 | 4346 |
| 4347 format %{ "fl" %} | |
| 4348 interface(COND_INTER) %{ | |
| 4349 equal(0x9); | |
| 4350 not_equal(0x1); | |
| 4351 less(0x3); | |
| 4352 greater_equal(0xB); | |
| 4353 less_equal(0xE); | |
| 4354 greater(0x6); | |
| 12323 | 4355 |
| 4356 overflow(0x7); // not supported | |
| 4357 no_overflow(0xF); // not supported | |
| 0 | 4358 %} |
| 4359 %} | |
| 4360 | |
| 4361 // Used by long compare | |
| 4362 operand cmpOp_commute() %{ | |
| 4363 match(Bool); | |
| 12323 | 4364 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
| 4365 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
| 0 | 4366 |
| 4367 format %{ "" %} | |
| 4368 interface(COND_INTER) %{ | |
| 4369 equal(0x1); | |
| 4370 not_equal(0x9); | |
| 4371 less(0xA); | |
| 4372 greater_equal(0x2); | |
| 4373 less_equal(0xB); | |
| 4374 greater(0x3); | |
| 12323 | 4375 overflow(0x7); |
| 4376 no_overflow(0xF); | |
| 0 | 4377 %} |
| 4378 %} | |
| 4379 | |
| 4380 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4381 // Operand Classes are groups of operands that are used to simplify | |
| 605 | 4382 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4383 // instructions for every form of operand when the instruction accepts |
| 4384 // multiple operand types with the same basic encoding and format. The classic | |
| 4385 // case of this is memory operands. | |
| 4386 opclass memory( indirect, indOffset13, indIndex ); | |
|
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4387 opclass indIndexMemory( indIndex ); |
| 0 | 4388 |
| 4389 //----------PIPELINE----------------------------------------------------------- | |
| 4390 pipeline %{ | |
| 4391 | |
| 4392 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4393 attributes %{ | |
| 4394 fixed_size_instructions; // Fixed size instructions | |
| 4395 branch_has_delay_slot; // Branch has delay slot following | |
| 4396 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
| 4397 instruction_unit_size = 4; // An instruction is 4 bytes long | |
| 4398 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4399 instruction_fetch_units = 1; // of 16 bytes | |
| 4400 | |
| 4401 // List of nop instructions | |
| 4402 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
| 4403 %} | |
| 4404 | |
| 4405 //----------RESOURCES---------------------------------------------------------- | |
| 4406 // Resources are the functional units available to the machine | |
| 4407 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
| 4408 | |
| 4409 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4410 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4411 | |
| 4412 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
| 4413 | |
| 4414 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4415 // Pipeline Classes describe the stages in which input and output are | |
| 4416 // referenced by the hardware pipeline. | |
| 4417 | |
| 4418 // Integer ALU reg-reg operation | |
| 4419 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4420 single_instruction; | |
| 4421 dst : E(write); | |
| 4422 src1 : R(read); | |
| 4423 src2 : R(read); | |
| 4424 IALU : R; | |
| 4425 %} | |
| 4426 | |
| 4427 // Integer ALU reg-reg long operation | |
| 4428 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4429 instruction_count(2); | |
| 4430 dst : E(write); | |
| 4431 src1 : R(read); | |
| 4432 src2 : R(read); | |
| 4433 IALU : R; | |
| 4434 IALU : R; | |
| 4435 %} | |
| 4436 | |
| 4437 // Integer ALU reg-reg long dependent operation | |
| 4438 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
| 4439 instruction_count(1); multiple_bundles; | |
| 4440 dst : E(write); | |
| 4441 src1 : R(read); | |
| 4442 src2 : R(read); | |
| 4443 cr : E(write); | |
| 4444 IALU : R(2); | |
| 4445 %} | |
| 4446 | |
| 4447 // Integer ALU reg-imm operaion | |
| 4448 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4449 single_instruction; | |
| 4450 dst : E(write); | |
| 4451 src1 : R(read); | |
| 4452 IALU : R; | |
| 4453 %} | |
| 4454 | |
| 4455 // Integer ALU reg-reg operation with condition code | |
| 4456 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
| 4457 single_instruction; | |
| 4458 dst : E(write); | |
| 4459 cr : E(write); | |
| 4460 src1 : R(read); | |
| 4461 src2 : R(read); | |
| 4462 IALU : R; | |
| 4463 %} | |
| 4464 | |
| 4465 // Integer ALU reg-imm operation with condition code | |
| 4466 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
| 4467 single_instruction; | |
| 4468 dst : E(write); | |
| 4469 cr : E(write); | |
| 4470 src1 : R(read); | |
| 4471 IALU : R; | |
| 4472 %} | |
| 4473 | |
| 4474 // Integer ALU zero-reg operation | |
| 4475 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 4476 single_instruction; | |
| 4477 dst : E(write); | |
| 4478 src2 : R(read); | |
| 4479 IALU : R; | |
| 4480 %} | |
| 4481 | |
| 4482 // Integer ALU zero-reg operation with condition code only | |
| 4483 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
| 4484 single_instruction; | |
| 4485 cr : E(write); | |
| 4486 src : R(read); | |
| 4487 IALU : R; | |
| 4488 %} | |
| 4489 | |
| 4490 // Integer ALU reg-reg operation with condition code only | |
| 4491 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4492 single_instruction; | |
| 4493 cr : E(write); | |
| 4494 src1 : R(read); | |
| 4495 src2 : R(read); | |
| 4496 IALU : R; | |
| 4497 %} | |
| 4498 | |
| 4499 // Integer ALU reg-imm operation with condition code only | |
| 4500 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4501 single_instruction; | |
| 4502 cr : E(write); | |
| 4503 src1 : R(read); | |
| 4504 IALU : R; | |
| 4505 %} | |
| 4506 | |
| 4507 // Integer ALU reg-reg-zero operation with condition code only | |
| 4508 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
| 4509 single_instruction; | |
| 4510 cr : E(write); | |
| 4511 src1 : R(read); | |
| 4512 src2 : R(read); | |
| 4513 IALU : R; | |
| 4514 %} | |
| 4515 | |
| 4516 // Integer ALU reg-imm-zero operation with condition code only | |
| 4517 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
| 4518 single_instruction; | |
| 4519 cr : E(write); | |
| 4520 src1 : R(read); | |
| 4521 IALU : R; | |
| 4522 %} | |
| 4523 | |
| 4524 // Integer ALU reg-reg operation with condition code, src1 modified | |
| 4525 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4526 single_instruction; | |
| 4527 cr : E(write); | |
| 4528 src1 : E(write); | |
| 4529 src1 : R(read); | |
| 4530 src2 : R(read); | |
| 4531 IALU : R; | |
| 4532 %} | |
| 4533 | |
| 4534 // Integer ALU reg-imm operation with condition code, src1 modified | |
| 4535 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4536 single_instruction; | |
| 4537 cr : E(write); | |
| 4538 src1 : E(write); | |
| 4539 src1 : R(read); | |
| 4540 IALU : R; | |
| 4541 %} | |
| 4542 | |
| 4543 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
| 4544 multiple_bundles; | |
| 4545 dst : E(write)+4; | |
| 4546 cr : E(write); | |
| 4547 src1 : R(read); | |
| 4548 src2 : R(read); | |
| 4549 IALU : R(3); | |
| 4550 BR : R(2); | |
| 4551 %} | |
| 4552 | |
| 4553 // Integer ALU operation | |
| 4554 pipe_class ialu_none(iRegI dst) %{ | |
| 4555 single_instruction; | |
| 4556 dst : E(write); | |
| 4557 IALU : R; | |
| 4558 %} | |
| 4559 | |
| 4560 // Integer ALU reg operation | |
| 4561 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
| 4562 single_instruction; may_have_no_code; | |
| 4563 dst : E(write); | |
| 4564 src : R(read); | |
| 4565 IALU : R; | |
| 4566 %} | |
| 4567 | |
| 4568 // Integer ALU reg conditional operation | |
| 4569 // This instruction has a 1 cycle stall, and cannot execute | |
| 4570 // in the same cycle as the instruction setting the condition | |
| 4571 // code. We kludge this by pretending to read the condition code | |
| 4572 // 1 cycle earlier, and by marking the functional units as busy | |
| 4573 // for 2 cycles with the result available 1 cycle later than | |
| 4574 // is really the case. | |
| 4575 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
| 4576 single_instruction; | |
| 4577 op2_out : C(write); | |
| 4578 op1 : R(read); | |
| 4579 cr : R(read); // This is really E, with a 1 cycle stall | |
| 4580 BR : R(2); | |
| 4581 MS : R(2); | |
| 4582 %} | |
| 4583 | |
| 4584 #ifdef _LP64 | |
| 4585 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
| 4586 instruction_count(1); multiple_bundles; | |
| 4587 dst : C(write)+1; | |
| 4588 src : R(read)+1; | |
| 4589 IALU : R(1); | |
| 4590 BR : E(2); | |
| 4591 MS : E(2); | |
| 4592 %} | |
| 4593 #endif | |
| 4594 | |
| 4595 // Integer ALU reg operation | |
| 4596 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
| 4597 single_instruction; may_have_no_code; | |
| 4598 dst : E(write); | |
| 4599 src : R(read); | |
| 4600 IALU : R; | |
| 4601 %} | |
| 4602 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
| 4603 single_instruction; may_have_no_code; | |
| 4604 dst : E(write); | |
| 4605 src : R(read); | |
| 4606 IALU : R; | |
| 4607 %} | |
| 4608 | |
| 4609 // Two integer ALU reg operations | |
| 4610 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
| 4611 instruction_count(2); | |
| 4612 dst : E(write); | |
| 4613 src : R(read); | |
| 4614 A0 : R; | |
| 4615 A1 : R; | |
| 4616 %} | |
| 4617 | |
| 4618 // Two integer ALU reg operations | |
| 4619 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
| 4620 instruction_count(2); may_have_no_code; | |
| 4621 dst : E(write); | |
| 4622 src : R(read); | |
| 4623 A0 : R; | |
| 4624 A1 : R; | |
| 4625 %} | |
| 4626 | |
| 4627 // Integer ALU imm operation | |
| 4628 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
| 4629 single_instruction; | |
| 4630 dst : E(write); | |
| 4631 IALU : R; | |
| 4632 %} | |
| 4633 | |
| 4634 // Integer ALU reg-reg with carry operation | |
| 4635 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
| 4636 single_instruction; | |
| 4637 dst : E(write); | |
| 4638 src1 : R(read); | |
| 4639 src2 : R(read); | |
| 4640 IALU : R; | |
| 4641 %} | |
| 4642 | |
| 4643 // Integer ALU cc operation | |
| 4644 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
| 4645 single_instruction; | |
| 4646 dst : E(write); | |
| 4647 cc : R(read); | |
| 4648 IALU : R; | |
| 4649 %} | |
| 4650 | |
| 4651 // Integer ALU cc / second IALU operation | |
| 4652 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
| 4653 instruction_count(1); multiple_bundles; | |
| 4654 dst : E(write)+1; | |
| 4655 src : R(read); | |
| 4656 IALU : R; | |
| 4657 %} | |
| 4658 | |
| 4659 // Integer ALU cc / second IALU operation | |
| 4660 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
| 4661 instruction_count(1); multiple_bundles; | |
| 4662 dst : E(write)+1; | |
| 4663 p : R(read); | |
| 4664 q : R(read); | |
| 4665 IALU : R; | |
| 4666 %} | |
| 4667 | |
| 4668 // Integer ALU hi-lo-reg operation | |
| 4669 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
| 4670 instruction_count(1); multiple_bundles; | |
| 4671 dst : E(write)+1; | |
| 4672 IALU : R(2); | |
| 4673 %} | |
| 4674 | |
| 4675 // Float ALU hi-lo-reg operation (with temp) | |
| 4676 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
| 4677 instruction_count(1); multiple_bundles; | |
| 4678 dst : E(write)+1; | |
| 4679 IALU : R(2); | |
| 4680 %} | |
| 4681 | |
| 4682 // Long Constant | |
| 4683 pipe_class loadConL( iRegL dst, immL src ) %{ | |
| 4684 instruction_count(2); multiple_bundles; | |
| 4685 dst : E(write)+1; | |
| 4686 IALU : R(2); | |
| 4687 IALU : R(2); | |
| 4688 %} | |
| 4689 | |
| 4690 // Pointer Constant | |
| 4691 pipe_class loadConP( iRegP dst, immP src ) %{ | |
| 4692 instruction_count(0); multiple_bundles; | |
| 4693 fixed_latency(6); | |
| 4694 %} | |
| 4695 | |
| 4696 // Polling Address | |
| 4697 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
| 4698 #ifdef _LP64 | |
| 4699 instruction_count(0); multiple_bundles; | |
| 4700 fixed_latency(6); | |
| 4701 #else | |
| 4702 dst : E(write); | |
| 4703 IALU : R; | |
| 4704 #endif | |
| 4705 %} | |
| 4706 | |
| 4707 // Long Constant small | |
| 4708 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
| 4709 instruction_count(2); | |
| 4710 dst : E(write); | |
| 4711 IALU : R; | |
| 4712 IALU : R; | |
| 4713 %} | |
| 4714 | |
| 4715 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
| 4716 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
| 4717 instruction_count(1); multiple_bundles; | |
| 4718 src : R(read); | |
| 4719 dst : M(write)+1; | |
| 4720 IALU : R; | |
| 4721 MS : E; | |
| 4722 %} | |
| 4723 | |
| 4724 // Integer ALU nop operation | |
| 4725 pipe_class ialu_nop() %{ | |
| 4726 single_instruction; | |
| 4727 IALU : R; | |
| 4728 %} | |
| 4729 | |
| 4730 // Integer ALU nop operation | |
| 4731 pipe_class ialu_nop_A0() %{ | |
| 4732 single_instruction; | |
| 4733 A0 : R; | |
| 4734 %} | |
| 4735 | |
| 4736 // Integer ALU nop operation | |
| 4737 pipe_class ialu_nop_A1() %{ | |
| 4738 single_instruction; | |
| 4739 A1 : R; | |
| 4740 %} | |
| 4741 | |
| 4742 // Integer Multiply reg-reg operation | |
| 4743 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4744 single_instruction; | |
| 4745 dst : E(write); | |
| 4746 src1 : R(read); | |
| 4747 src2 : R(read); | |
| 4748 MS : R(5); | |
| 4749 %} | |
| 4750 | |
| 4751 // Integer Multiply reg-imm operation | |
| 4752 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4753 single_instruction; | |
| 4754 dst : E(write); | |
| 4755 src1 : R(read); | |
| 4756 MS : R(5); | |
| 4757 %} | |
| 4758 | |
| 4759 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4760 single_instruction; | |
| 4761 dst : E(write)+4; | |
| 4762 src1 : R(read); | |
| 4763 src2 : R(read); | |
| 4764 MS : R(6); | |
| 4765 %} | |
| 4766 | |
| 4767 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4768 single_instruction; | |
| 4769 dst : E(write)+4; | |
| 4770 src1 : R(read); | |
| 4771 MS : R(6); | |
| 4772 %} | |
| 4773 | |
| 4774 // Integer Divide reg-reg | |
| 4775 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
| 4776 instruction_count(1); multiple_bundles; | |
| 4777 dst : E(write); | |
| 4778 temp : E(write); | |
| 4779 src1 : R(read); | |
| 4780 src2 : R(read); | |
| 4781 temp : R(read); | |
| 4782 MS : R(38); | |
| 4783 %} | |
| 4784 | |
| 4785 // Integer Divide reg-imm | |
| 4786 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
| 4787 instruction_count(1); multiple_bundles; | |
| 4788 dst : E(write); | |
| 4789 temp : E(write); | |
| 4790 src1 : R(read); | |
| 4791 temp : R(read); | |
| 4792 MS : R(38); | |
| 4793 %} | |
| 4794 | |
| 4795 // Long Divide | |
| 4796 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4797 dst : E(write)+71; | |
| 4798 src1 : R(read); | |
| 4799 src2 : R(read)+1; | |
| 4800 MS : R(70); | |
| 4801 %} | |
| 4802 | |
| 4803 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4804 dst : E(write)+71; | |
| 4805 src1 : R(read); | |
| 4806 MS : R(70); | |
| 4807 %} | |
| 4808 | |
| 4809 // Floating Point Add Float | |
| 4810 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4811 single_instruction; | |
| 4812 dst : X(write); | |
| 4813 src1 : E(read); | |
| 4814 src2 : E(read); | |
| 4815 FA : R; | |
| 4816 %} | |
| 4817 | |
| 4818 // Floating Point Add Double | |
| 4819 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4820 single_instruction; | |
| 4821 dst : X(write); | |
| 4822 src1 : E(read); | |
| 4823 src2 : E(read); | |
| 4824 FA : R; | |
| 4825 %} | |
| 4826 | |
| 4827 // Floating Point Conditional Move based on integer flags | |
| 4828 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
| 4829 single_instruction; | |
| 4830 dst : X(write); | |
| 4831 src : E(read); | |
| 4832 cr : R(read); | |
| 4833 FA : R(2); | |
| 4834 BR : R(2); | |
| 4835 %} | |
| 4836 | |
| 4837 // Floating Point Conditional Move based on integer flags | |
| 4838 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
| 4839 single_instruction; | |
| 4840 dst : X(write); | |
| 4841 src : E(read); | |
| 4842 cr : R(read); | |
| 4843 FA : R(2); | |
| 4844 BR : R(2); | |
| 4845 %} | |
| 4846 | |
| 4847 // Floating Point Multiply Float | |
| 4848 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4849 single_instruction; | |
| 4850 dst : X(write); | |
| 4851 src1 : E(read); | |
| 4852 src2 : E(read); | |
| 4853 FM : R; | |
| 4854 %} | |
| 4855 | |
| 4856 // Floating Point Multiply Double | |
| 4857 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4858 single_instruction; | |
| 4859 dst : X(write); | |
| 4860 src1 : E(read); | |
| 4861 src2 : E(read); | |
| 4862 FM : R; | |
| 4863 %} | |
| 4864 | |
| 4865 // Floating Point Divide Float | |
| 4866 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4867 single_instruction; | |
| 4868 dst : X(write); | |
| 4869 src1 : E(read); | |
| 4870 src2 : E(read); | |
| 4871 FM : R; | |
| 4872 FDIV : C(14); | |
| 4873 %} | |
| 4874 | |
| 4875 // Floating Point Divide Double | |
| 4876 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4877 single_instruction; | |
| 4878 dst : X(write); | |
| 4879 src1 : E(read); | |
| 4880 src2 : E(read); | |
| 4881 FM : R; | |
| 4882 FDIV : C(17); | |
| 4883 %} | |
| 4884 | |
| 4885 // Floating Point Move/Negate/Abs Float | |
| 4886 pipe_class faddF_reg(regF dst, regF src) %{ | |
| 4887 single_instruction; | |
| 4888 dst : W(write); | |
| 4889 src : E(read); | |
| 4890 FA : R(1); | |
| 4891 %} | |
| 4892 | |
| 4893 // Floating Point Move/Negate/Abs Double | |
| 4894 pipe_class faddD_reg(regD dst, regD src) %{ | |
| 4895 single_instruction; | |
| 4896 dst : W(write); | |
| 4897 src : E(read); | |
| 4898 FA : R; | |
| 4899 %} | |
| 4900 | |
| 4901 // Floating Point Convert F->D | |
| 4902 pipe_class fcvtF2D(regD dst, regF src) %{ | |
| 4903 single_instruction; | |
| 4904 dst : X(write); | |
| 4905 src : E(read); | |
| 4906 FA : R; | |
| 4907 %} | |
| 4908 | |
| 4909 // Floating Point Convert I->D | |
| 4910 pipe_class fcvtI2D(regD dst, regF src) %{ | |
| 4911 single_instruction; | |
| 4912 dst : X(write); | |
| 4913 src : E(read); | |
| 4914 FA : R; | |
| 4915 %} | |
| 4916 | |
| 4917 // Floating Point Convert LHi->D | |
| 4918 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
| 4919 single_instruction; | |
| 4920 dst : X(write); | |
| 4921 src : E(read); | |
| 4922 FA : R; | |
| 4923 %} | |
| 4924 | |
| 4925 // Floating Point Convert L->D | |
| 4926 pipe_class fcvtL2D(regD dst, regF src) %{ | |
| 4927 single_instruction; | |
| 4928 dst : X(write); | |
| 4929 src : E(read); | |
| 4930 FA : R; | |
| 4931 %} | |
| 4932 | |
| 4933 // Floating Point Convert L->F | |
| 4934 pipe_class fcvtL2F(regD dst, regF src) %{ | |
| 4935 single_instruction; | |
| 4936 dst : X(write); | |
| 4937 src : E(read); | |
| 4938 FA : R; | |
| 4939 %} | |
| 4940 | |
| 4941 // Floating Point Convert D->F | |
| 4942 pipe_class fcvtD2F(regD dst, regF src) %{ | |
| 4943 single_instruction; | |
| 4944 dst : X(write); | |
| 4945 src : E(read); | |
| 4946 FA : R; | |
| 4947 %} | |
| 4948 | |
| 4949 // Floating Point Convert I->L | |
| 4950 pipe_class fcvtI2L(regD dst, regF src) %{ | |
| 4951 single_instruction; | |
| 4952 dst : X(write); | |
| 4953 src : E(read); | |
| 4954 FA : R; | |
| 4955 %} | |
| 4956 | |
| 4957 // Floating Point Convert D->F | |
| 4958 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
| 4959 instruction_count(1); multiple_bundles; | |
| 4960 dst : X(write)+6; | |
| 4961 src : E(read); | |
| 4962 FA : R; | |
| 4963 %} | |
| 4964 | |
| 4965 // Floating Point Convert D->L | |
| 4966 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
| 4967 instruction_count(1); multiple_bundles; | |
| 4968 dst : X(write)+6; | |
| 4969 src : E(read); | |
| 4970 FA : R; | |
| 4971 %} | |
| 4972 | |
| 4973 // Floating Point Convert F->I | |
| 4974 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
| 4975 instruction_count(1); multiple_bundles; | |
| 4976 dst : X(write)+6; | |
| 4977 src : E(read); | |
| 4978 FA : R; | |
| 4979 %} | |
| 4980 | |
| 4981 // Floating Point Convert F->L | |
| 4982 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
| 4983 instruction_count(1); multiple_bundles; | |
| 4984 dst : X(write)+6; | |
| 4985 src : E(read); | |
| 4986 FA : R; | |
| 4987 %} | |
| 4988 | |
| 4989 // Floating Point Convert I->F | |
| 4990 pipe_class fcvtI2F(regF dst, regF src) %{ | |
| 4991 single_instruction; | |
| 4992 dst : X(write); | |
| 4993 src : E(read); | |
| 4994 FA : R; | |
| 4995 %} | |
| 4996 | |
| 4997 // Floating Point Compare | |
| 4998 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
| 4999 single_instruction; | |
| 5000 cr : X(write); | |
| 5001 src1 : E(read); | |
| 5002 src2 : E(read); | |
| 5003 FA : R; | |
| 5004 %} | |
| 5005 | |
| 5006 // Floating Point Compare | |
| 5007 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
| 5008 single_instruction; | |
| 5009 cr : X(write); | |
| 5010 src1 : E(read); | |
| 5011 src2 : E(read); | |
| 5012 FA : R; | |
| 5013 %} | |
| 5014 | |
| 5015 // Floating Add Nop | |
| 5016 pipe_class fadd_nop() %{ | |
| 5017 single_instruction; | |
| 5018 FA : R; | |
| 5019 %} | |
| 5020 | |
| 5021 // Integer Store to Memory | |
| 5022 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
| 5023 single_instruction; | |
| 5024 mem : R(read); | |
| 5025 src : C(read); | |
| 5026 MS : R; | |
| 5027 %} | |
| 5028 | |
| 5029 // Integer Store to Memory | |
| 5030 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
| 5031 single_instruction; | |
| 5032 mem : R(read); | |
| 5033 src : C(read); | |
| 5034 MS : R; | |
| 5035 %} | |
| 5036 | |
| 5037 // Integer Store Zero to Memory | |
| 5038 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
| 5039 single_instruction; | |
| 5040 mem : R(read); | |
| 5041 MS : R; | |
| 5042 %} | |
| 5043 | |
| 5044 // Special Stack Slot Store | |
| 5045 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
| 5046 single_instruction; | |
| 5047 stkSlot : R(read); | |
| 5048 src : C(read); | |
| 5049 MS : R; | |
| 5050 %} | |
| 5051 | |
| 5052 // Special Stack Slot Store | |
| 5053 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
| 5054 instruction_count(2); multiple_bundles; | |
| 5055 stkSlot : R(read); | |
| 5056 src : C(read); | |
| 5057 MS : R(2); | |
| 5058 %} | |
| 5059 | |
| 5060 // Float Store | |
| 5061 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
| 5062 single_instruction; | |
| 5063 mem : R(read); | |
| 5064 src : C(read); | |
| 5065 MS : R; | |
| 5066 %} | |
| 5067 | |
| 5068 // Float Store | |
| 5069 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
| 5070 single_instruction; | |
| 5071 mem : R(read); | |
| 5072 MS : R; | |
| 5073 %} | |
| 5074 | |
| 5075 // Double Store | |
| 5076 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
| 5077 instruction_count(1); | |
| 5078 mem : R(read); | |
| 5079 src : C(read); | |
| 5080 MS : R; | |
| 5081 %} | |
| 5082 | |
| 5083 // Double Store | |
| 5084 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
| 5085 single_instruction; | |
| 5086 mem : R(read); | |
| 5087 MS : R; | |
| 5088 %} | |
| 5089 | |
| 5090 // Special Stack Slot Float Store | |
| 5091 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
| 5092 single_instruction; | |
| 5093 stkSlot : R(read); | |
| 5094 src : C(read); | |
| 5095 MS : R; | |
| 5096 %} | |
| 5097 | |
| 5098 // Special Stack Slot Double Store | |
| 5099 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
| 5100 single_instruction; | |
| 5101 stkSlot : R(read); | |
| 5102 src : C(read); | |
| 5103 MS : R; | |
| 5104 %} | |
| 5105 | |
| 5106 // Integer Load (when sign bit propagation not needed) | |
| 5107 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
| 5108 single_instruction; | |
| 5109 mem : R(read); | |
| 5110 dst : C(write); | |
| 5111 MS : R; | |
| 5112 %} | |
| 5113 | |
| 5114 // Integer Load from stack operand | |
| 5115 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
| 5116 single_instruction; | |
| 5117 mem : R(read); | |
| 5118 dst : C(write); | |
| 5119 MS : R; | |
| 5120 %} | |
| 5121 | |
| 5122 // Integer Load (when sign bit propagation or masking is needed) | |
| 5123 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
| 5124 single_instruction; | |
| 5125 mem : R(read); | |
| 5126 dst : M(write); | |
| 5127 MS : R; | |
| 5128 %} | |
| 5129 | |
| 5130 // Float Load | |
| 5131 pipe_class floadF_mem(regF dst, memory mem) %{ | |
| 5132 single_instruction; | |
| 5133 mem : R(read); | |
| 5134 dst : M(write); | |
| 5135 MS : R; | |
| 5136 %} | |
| 5137 | |
| 5138 // Float Load | |
| 5139 pipe_class floadD_mem(regD dst, memory mem) %{ | |
| 5140 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
| 5141 mem : R(read); | |
| 5142 dst : M(write); | |
| 5143 MS : R; | |
| 5144 %} | |
| 5145 | |
| 5146 // Float Load | |
| 5147 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
| 5148 single_instruction; | |
| 5149 stkSlot : R(read); | |
| 5150 dst : M(write); | |
| 5151 MS : R; | |
| 5152 %} | |
| 5153 | |
| 5154 // Float Load | |
| 5155 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
| 5156 single_instruction; | |
| 5157 stkSlot : R(read); | |
| 5158 dst : M(write); | |
| 5159 MS : R; | |
| 5160 %} | |
| 5161 | |
| 5162 // Memory Nop | |
| 5163 pipe_class mem_nop() %{ | |
| 5164 single_instruction; | |
| 5165 MS : R; | |
| 5166 %} | |
| 5167 | |
| 5168 pipe_class sethi(iRegP dst, immI src) %{ | |
| 5169 single_instruction; | |
| 5170 dst : E(write); | |
| 5171 IALU : R; | |
| 5172 %} | |
| 5173 | |
| 5174 pipe_class loadPollP(iRegP poll) %{ | |
| 5175 single_instruction; | |
| 5176 poll : R(read); | |
| 5177 MS : R; | |
| 5178 %} | |
| 5179 | |
| 5180 pipe_class br(Universe br, label labl) %{ | |
| 5181 single_instruction_with_delay_slot; | |
| 5182 BR : R; | |
| 5183 %} | |
| 5184 | |
| 5185 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
| 5186 single_instruction_with_delay_slot; | |
| 5187 cr : E(read); | |
| 5188 BR : R; | |
| 5189 %} | |
| 5190 | |
| 5191 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
| 5192 single_instruction_with_delay_slot; | |
| 5193 op1 : E(read); | |
| 5194 BR : R; | |
| 5195 MS : R; | |
| 5196 %} | |
| 5197 | |
| 3851 | 5198 // Compare and branch |
| 5199 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ | |
| 5200 instruction_count(2); has_delay_slot; | |
| 5201 cr : E(write); | |
| 5202 src1 : R(read); | |
| 5203 src2 : R(read); | |
| 5204 IALU : R; | |
| 5205 BR : R; | |
| 5206 %} | |
| 5207 | |
| 5208 // Compare and branch | |
| 5209 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ | |
| 5210 instruction_count(2); has_delay_slot; | |
| 5211 cr : E(write); | |
| 5212 src1 : R(read); | |
| 5213 IALU : R; | |
| 5214 BR : R; | |
| 5215 %} | |
| 5216 | |
| 5217 // Compare and branch using cbcond | |
| 5218 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ | |
| 5219 single_instruction; | |
| 5220 src1 : E(read); | |
| 5221 src2 : E(read); | |
| 5222 IALU : R; | |
| 5223 BR : R; | |
| 5224 %} | |
| 5225 | |
| 5226 // Compare and branch using cbcond | |
| 5227 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ | |
| 5228 single_instruction; | |
| 5229 src1 : E(read); | |
| 5230 IALU : R; | |
| 5231 BR : R; | |
| 5232 %} | |
| 5233 | |
| 0 | 5234 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ |
| 5235 single_instruction_with_delay_slot; | |
| 5236 cr : E(read); | |
| 5237 BR : R; | |
| 5238 %} | |
| 5239 | |
| 5240 pipe_class br_nop() %{ | |
| 5241 single_instruction; | |
| 5242 BR : R; | |
| 5243 %} | |
| 5244 | |
| 5245 pipe_class simple_call(method meth) %{ | |
| 5246 instruction_count(2); multiple_bundles; force_serialization; | |
| 5247 fixed_latency(100); | |
| 5248 BR : R(1); | |
| 5249 MS : R(1); | |
| 5250 A0 : R(1); | |
| 5251 %} | |
| 5252 | |
| 5253 pipe_class compiled_call(method meth) %{ | |
| 5254 instruction_count(1); multiple_bundles; force_serialization; | |
| 5255 fixed_latency(100); | |
| 5256 MS : R(1); | |
| 5257 %} | |
| 5258 | |
| 5259 pipe_class call(method meth) %{ | |
| 5260 instruction_count(0); multiple_bundles; force_serialization; | |
| 5261 fixed_latency(100); | |
| 5262 %} | |
| 5263 | |
| 5264 pipe_class tail_call(Universe ignore, label labl) %{ | |
| 5265 single_instruction; has_delay_slot; | |
| 5266 fixed_latency(100); | |
| 5267 BR : R(1); | |
| 5268 MS : R(1); | |
| 5269 %} | |
| 5270 | |
| 5271 pipe_class ret(Universe ignore) %{ | |
| 5272 single_instruction; has_delay_slot; | |
| 5273 BR : R(1); | |
| 5274 MS : R(1); | |
| 5275 %} | |
| 5276 | |
| 5277 pipe_class ret_poll(g3RegP poll) %{ | |
| 5278 instruction_count(3); has_delay_slot; | |
| 5279 poll : E(read); | |
| 5280 MS : R; | |
| 5281 %} | |
| 5282 | |
| 5283 // The real do-nothing guy | |
| 5284 pipe_class empty( ) %{ | |
| 5285 instruction_count(0); | |
| 5286 %} | |
| 5287 | |
| 5288 pipe_class long_memory_op() %{ | |
| 5289 instruction_count(0); multiple_bundles; force_serialization; | |
| 5290 fixed_latency(25); | |
| 5291 MS : R(1); | |
| 5292 %} | |
| 5293 | |
| 5294 // Check-cast | |
| 5295 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
| 5296 array : R(read); | |
| 5297 match : R(read); | |
| 5298 IALU : R(2); | |
| 5299 BR : R(2); | |
| 5300 MS : R; | |
| 5301 %} | |
| 5302 | |
| 5303 // Convert FPU flags into +1,0,-1 | |
| 5304 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
| 5305 src1 : E(read); | |
| 5306 src2 : E(read); | |
| 5307 dst : E(write); | |
| 5308 FA : R; | |
| 5309 MS : R(2); | |
| 5310 BR : R(2); | |
| 5311 %} | |
| 5312 | |
| 5313 // Compare for p < q, and conditionally add y | |
| 5314 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
| 5315 p : E(read); | |
| 5316 q : E(read); | |
| 5317 y : E(read); | |
| 5318 IALU : R(3) | |
| 5319 %} | |
| 5320 | |
| 5321 // Perform a compare, then move conditionally in a branch delay slot. | |
| 5322 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
| 5323 src2 : E(read); | |
| 5324 srcdst : E(read); | |
| 5325 IALU : R; | |
| 5326 BR : R; | |
| 5327 %} | |
| 5328 | |
| 5329 // Define the class for the Nop node | |
| 5330 define %{ | |
| 5331 MachNop = ialu_nop; | |
| 5332 %} | |
| 5333 | |
| 5334 %} | |
| 5335 | |
| 5336 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5337 | |
| 5338 //------------Special Stack Slot instructions - no match rules----------------- | |
| 5339 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
| 5340 // No match rule to avoid chain rule match. | |
| 5341 effect(DEF dst, USE src); | |
| 5342 ins_cost(MEMORY_REF_COST); | |
| 5343 size(4); | |
| 5344 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
| 5345 opcode(Assembler::ldf_op3); | |
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5346 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5347 ins_pipe(floadF_stk); |
| 5348 %} | |
| 5349 | |
| 5350 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
| 5351 // No match rule to avoid chain rule match. | |
| 5352 effect(DEF dst, USE src); | |
| 5353 ins_cost(MEMORY_REF_COST); | |
| 5354 size(4); | |
| 5355 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
| 5356 opcode(Assembler::lddf_op3); | |
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5357 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5358 ins_pipe(floadD_stk); |
| 5359 %} | |
| 5360 | |
| 5361 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
| 5362 // No match rule to avoid chain rule match. | |
| 5363 effect(DEF dst, USE src); | |
| 5364 ins_cost(MEMORY_REF_COST); | |
| 5365 size(4); | |
| 5366 format %{ "STF $src,$dst\t! regF to stkI" %} | |
| 5367 opcode(Assembler::stf_op3); | |
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5368 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5369 ins_pipe(fstoreF_stk_reg); |
| 5370 %} | |
| 5371 | |
| 5372 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
| 5373 // No match rule to avoid chain rule match. | |
| 5374 effect(DEF dst, USE src); | |
| 5375 ins_cost(MEMORY_REF_COST); | |
| 5376 size(4); | |
| 5377 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
| 5378 opcode(Assembler::stdf_op3); | |
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5379 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5380 ins_pipe(fstoreD_stk_reg); |
| 5381 %} | |
| 5382 | |
| 5383 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
| 5384 effect(DEF dst, USE src); | |
| 5385 ins_cost(MEMORY_REF_COST*2); | |
| 5386 size(8); | |
| 5387 format %{ "STW $src,$dst.hi\t! long\n\t" | |
| 5388 "STW R_G0,$dst.lo" %} | |
| 5389 opcode(Assembler::stw_op3); | |
|
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5390 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
| 0 | 5391 ins_pipe(lstoreI_stk_reg); |
| 5392 %} | |
| 5393 | |
| 5394 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
| 5395 // No match rule to avoid chain rule match. | |
| 5396 effect(DEF dst, USE src); | |
| 5397 ins_cost(MEMORY_REF_COST); | |
| 5398 size(4); | |
| 5399 format %{ "STX $src,$dst\t! regL to stkD" %} | |
| 5400 opcode(Assembler::stx_op3); | |
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5401 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5402 ins_pipe(istore_stk_reg); |
| 5403 %} | |
| 5404 | |
| 5405 //---------- Chain stack slots between similar types -------- | |
| 5406 | |
| 5407 // Load integer from stack slot | |
| 5408 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
| 5409 match(Set dst src); | |
| 5410 ins_cost(MEMORY_REF_COST); | |
| 5411 | |
| 5412 size(4); | |
| 5413 format %{ "LDUW $src,$dst\t!stk" %} | |
| 5414 opcode(Assembler::lduw_op3); | |
|
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5415 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5416 ins_pipe(iload_mem); |
| 5417 %} | |
| 5418 | |
| 5419 // Store integer to stack slot | |
| 5420 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
| 5421 match(Set dst src); | |
| 5422 ins_cost(MEMORY_REF_COST); | |
| 5423 | |
| 5424 size(4); | |
| 5425 format %{ "STW $src,$dst\t!stk" %} | |
| 5426 opcode(Assembler::stw_op3); | |
|
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5427 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5428 ins_pipe(istore_mem_reg); |
| 5429 %} | |
| 5430 | |
| 5431 // Load long from stack slot | |
| 5432 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
| 5433 match(Set dst src); | |
| 5434 | |
| 5435 ins_cost(MEMORY_REF_COST); | |
| 5436 size(4); | |
| 5437 format %{ "LDX $src,$dst\t! long" %} | |
| 5438 opcode(Assembler::ldx_op3); | |
|
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5439 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5440 ins_pipe(iload_mem); |
| 5441 %} | |
| 5442 | |
| 5443 // Store long to stack slot | |
| 5444 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
| 5445 match(Set dst src); | |
| 5446 | |
| 5447 ins_cost(MEMORY_REF_COST); | |
| 5448 size(4); | |
| 5449 format %{ "STX $src,$dst\t! long" %} | |
| 5450 opcode(Assembler::stx_op3); | |
|
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5451 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5452 ins_pipe(istore_mem_reg); |
| 5453 %} | |
| 5454 | |
| 5455 #ifdef _LP64 | |
| 5456 // Load pointer from stack slot, 64-bit encoding | |
| 5457 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5458 match(Set dst src); | |
| 5459 ins_cost(MEMORY_REF_COST); | |
| 5460 size(4); | |
| 5461 format %{ "LDX $src,$dst\t!ptr" %} | |
| 5462 opcode(Assembler::ldx_op3); | |
|
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5463 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5464 ins_pipe(iload_mem); |
| 5465 %} | |
| 5466 | |
| 5467 // Store pointer to stack slot | |
| 5468 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5469 match(Set dst src); | |
| 5470 ins_cost(MEMORY_REF_COST); | |
| 5471 size(4); | |
| 5472 format %{ "STX $src,$dst\t!ptr" %} | |
| 5473 opcode(Assembler::stx_op3); | |
|
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5474 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5475 ins_pipe(istore_mem_reg); |
| 5476 %} | |
| 5477 #else // _LP64 | |
| 5478 // Load pointer from stack slot, 32-bit encoding | |
| 5479 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5480 match(Set dst src); | |
| 5481 ins_cost(MEMORY_REF_COST); | |
| 5482 format %{ "LDUW $src,$dst\t!ptr" %} | |
| 5483 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
|
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5484 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5485 ins_pipe(iload_mem); |
| 5486 %} | |
| 5487 | |
| 5488 // Store pointer to stack slot | |
| 5489 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5490 match(Set dst src); | |
| 5491 ins_cost(MEMORY_REF_COST); | |
| 5492 format %{ "STW $src,$dst\t!ptr" %} | |
| 5493 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
|
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5494 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5495 ins_pipe(istore_mem_reg); |
| 5496 %} | |
| 5497 #endif // _LP64 | |
| 5498 | |
| 5499 //------------Special Nop instructions for bundling - no match rules----------- | |
| 5500 // Nop using the A0 functional unit | |
| 5501 instruct Nop_A0() %{ | |
| 5502 ins_cost(0); | |
| 5503 | |
| 5504 format %{ "NOP ! Alu Pipeline" %} | |
| 5505 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5506 ins_encode( form2_nop() ); | |
| 5507 ins_pipe(ialu_nop_A0); | |
| 5508 %} | |
| 5509 | |
| 5510 // Nop using the A1 functional unit | |
| 5511 instruct Nop_A1( ) %{ | |
| 5512 ins_cost(0); | |
| 5513 | |
| 5514 format %{ "NOP ! Alu Pipeline" %} | |
| 5515 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5516 ins_encode( form2_nop() ); | |
| 5517 ins_pipe(ialu_nop_A1); | |
| 5518 %} | |
| 5519 | |
| 5520 // Nop using the memory functional unit | |
| 5521 instruct Nop_MS( ) %{ | |
| 5522 ins_cost(0); | |
| 5523 | |
| 5524 format %{ "NOP ! Memory Pipeline" %} | |
| 5525 ins_encode( emit_mem_nop ); | |
| 5526 ins_pipe(mem_nop); | |
| 5527 %} | |
| 5528 | |
| 5529 // Nop using the floating add functional unit | |
| 5530 instruct Nop_FA( ) %{ | |
| 5531 ins_cost(0); | |
| 5532 | |
| 5533 format %{ "NOP ! Floating Add Pipeline" %} | |
| 5534 ins_encode( emit_fadd_nop ); | |
| 5535 ins_pipe(fadd_nop); | |
| 5536 %} | |
| 5537 | |
| 5538 // Nop using the branch functional unit | |
| 5539 instruct Nop_BR( ) %{ | |
| 5540 ins_cost(0); | |
| 5541 | |
| 5542 format %{ "NOP ! Branch Pipeline" %} | |
| 5543 ins_encode( emit_br_nop ); | |
| 5544 ins_pipe(br_nop); | |
| 5545 %} | |
| 5546 | |
| 5547 //----------Load/Store/Move Instructions--------------------------------------- | |
| 5548 //----------Load Instructions-------------------------------------------------- | |
| 5549 // Load Byte (8bit signed) | |
| 5550 instruct loadB(iRegI dst, memory mem) %{ | |
| 5551 match(Set dst (LoadB mem)); | |
| 5552 ins_cost(MEMORY_REF_COST); | |
| 5553 | |
| 5554 size(4); | |
| 624 | 5555 format %{ "LDSB $mem,$dst\t! byte" %} |
| 727 | 5556 ins_encode %{ |
| 5557 __ ldsb($mem$$Address, $dst$$Register); | |
| 5558 %} | |
| 624 | 5559 ins_pipe(iload_mask_mem); |
| 5560 %} | |
| 5561 | |
| 5562 // Load Byte (8bit signed) into a Long Register | |
| 5563 instruct loadB2L(iRegL dst, memory mem) %{ | |
| 5564 match(Set dst (ConvI2L (LoadB mem))); | |
| 5565 ins_cost(MEMORY_REF_COST); | |
| 5566 | |
| 5567 size(4); | |
| 5568 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
| 727 | 5569 ins_encode %{ |
| 5570 __ ldsb($mem$$Address, $dst$$Register); | |
| 5571 %} | |
| 0 | 5572 ins_pipe(iload_mask_mem); |
| 5573 %} | |
| 5574 | |
| 624 | 5575 // Load Unsigned Byte (8bit UNsigned) into an int reg |
| 5576 instruct loadUB(iRegI dst, memory mem) %{ | |
| 5577 match(Set dst (LoadUB mem)); | |
| 0 | 5578 ins_cost(MEMORY_REF_COST); |
| 5579 | |
| 5580 size(4); | |
| 624 | 5581 format %{ "LDUB $mem,$dst\t! ubyte" %} |
| 727 | 5582 ins_encode %{ |
| 5583 __ ldub($mem$$Address, $dst$$Register); | |
| 5584 %} | |
| 824 | 5585 ins_pipe(iload_mem); |
| 624 | 5586 %} |
| 5587 | |
| 5588 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
| 5589 instruct loadUB2L(iRegL dst, memory mem) %{ | |
| 5590 match(Set dst (ConvI2L (LoadUB mem))); | |
| 5591 ins_cost(MEMORY_REF_COST); | |
| 5592 | |
| 5593 size(4); | |
| 5594 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
| 727 | 5595 ins_encode %{ |
| 5596 __ ldub($mem$$Address, $dst$$Register); | |
| 5597 %} | |
| 824 | 5598 ins_pipe(iload_mem); |
| 5599 %} | |
| 5600 | |
| 5601 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register | |
| 5602 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ | |
| 5603 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5604 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5605 | |
| 5606 size(2*4); | |
| 5607 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" | |
| 5608 "AND $dst,$mask,$dst" %} | |
| 5609 ins_encode %{ | |
| 5610 __ ldub($mem$$Address, $dst$$Register); | |
| 5611 __ and3($dst$$Register, $mask$$constant, $dst$$Register); | |
| 5612 %} | |
| 5613 ins_pipe(iload_mem); | |
| 0 | 5614 %} |
| 5615 | |
| 624 | 5616 // Load Short (16bit signed) |
| 5617 instruct loadS(iRegI dst, memory mem) %{ | |
| 5618 match(Set dst (LoadS mem)); | |
| 5619 ins_cost(MEMORY_REF_COST); | |
| 5620 | |
| 5621 size(4); | |
| 5622 format %{ "LDSH $mem,$dst\t! short" %} | |
| 727 | 5623 ins_encode %{ |
| 5624 __ ldsh($mem$$Address, $dst$$Register); | |
| 5625 %} | |
| 624 | 5626 ins_pipe(iload_mask_mem); |
| 5627 %} | |
| 5628 | |
| 785 | 5629 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 5630 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5631 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 5632 ins_cost(MEMORY_REF_COST); | |
| 5633 | |
| 5634 size(4); | |
| 5635 | |
| 5636 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} | |
| 5637 ins_encode %{ | |
| 5638 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5639 %} | |
| 5640 ins_pipe(iload_mask_mem); | |
| 5641 %} | |
| 5642 | |
| 624 | 5643 // Load Short (16bit signed) into a Long Register |
| 5644 instruct loadS2L(iRegL dst, memory mem) %{ | |
| 5645 match(Set dst (ConvI2L (LoadS mem))); | |
| 0 | 5646 ins_cost(MEMORY_REF_COST); |
| 5647 | |
| 5648 size(4); | |
| 624 | 5649 format %{ "LDSH $mem,$dst\t! short -> long" %} |
| 727 | 5650 ins_encode %{ |
| 5651 __ ldsh($mem$$Address, $dst$$Register); | |
| 5652 %} | |
| 624 | 5653 ins_pipe(iload_mask_mem); |
| 5654 %} | |
| 5655 | |
| 5656 // Load Unsigned Short/Char (16bit UNsigned) | |
| 5657 instruct loadUS(iRegI dst, memory mem) %{ | |
| 5658 match(Set dst (LoadUS mem)); | |
| 5659 ins_cost(MEMORY_REF_COST); | |
| 5660 | |
| 5661 size(4); | |
| 5662 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
| 727 | 5663 ins_encode %{ |
| 5664 __ lduh($mem$$Address, $dst$$Register); | |
| 5665 %} | |
| 824 | 5666 ins_pipe(iload_mem); |
| 0 | 5667 %} |
| 5668 | |
| 785 | 5669 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 5670 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5671 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 5672 ins_cost(MEMORY_REF_COST); | |
| 5673 | |
| 5674 size(4); | |
| 5675 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} | |
| 5676 ins_encode %{ | |
| 5677 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5678 %} | |
| 5679 ins_pipe(iload_mask_mem); | |
| 5680 %} | |
| 5681 | |
|
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551
diff
changeset
|
5682 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
| 624 | 5683 instruct loadUS2L(iRegL dst, memory mem) %{ |
| 5684 match(Set dst (ConvI2L (LoadUS mem))); | |
| 0 | 5685 ins_cost(MEMORY_REF_COST); |
| 5686 | |
| 5687 size(4); | |
| 624 | 5688 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
| 727 | 5689 ins_encode %{ |
| 5690 __ lduh($mem$$Address, $dst$$Register); | |
| 5691 %} | |
| 824 | 5692 ins_pipe(iload_mem); |
| 5693 %} | |
| 5694 | |
| 5695 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register | |
| 5696 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5697 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5698 ins_cost(MEMORY_REF_COST); | |
| 5699 | |
| 5700 size(4); | |
| 5701 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} | |
| 5702 ins_encode %{ | |
| 5703 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE | |
| 5704 %} | |
| 5705 ins_pipe(iload_mem); | |
| 5706 %} | |
| 5707 | |
| 5708 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register | |
| 5709 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
| 5710 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5711 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5712 | |
| 5713 size(2*4); | |
| 5714 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" | |
| 5715 "AND $dst,$mask,$dst" %} | |
| 5716 ins_encode %{ | |
| 5717 Register Rdst = $dst$$Register; | |
| 5718 __ lduh($mem$$Address, Rdst); | |
| 5719 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5720 %} | |
| 5721 ins_pipe(iload_mem); | |
| 5722 %} | |
| 5723 | |
| 5724 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register | |
| 5725 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | |
| 5726 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5727 effect(TEMP dst, TEMP tmp); | |
| 5728 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5729 | |
|
951
1fbd5d696bf4
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twisti
parents:
824
diff
changeset
|
5730 size((3+1)*4); // set may use two instructions. |
| 824 | 5731 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
| 5732 "SET $mask,$tmp\n\t" | |
| 5733 "AND $dst,$tmp,$dst" %} | |
| 5734 ins_encode %{ | |
| 5735 Register Rdst = $dst$$Register; | |
| 5736 Register Rtmp = $tmp$$Register; | |
| 5737 __ lduh($mem$$Address, Rdst); | |
| 5738 __ set($mask$$constant, Rtmp); | |
| 5739 __ and3(Rdst, Rtmp, Rdst); | |
| 5740 %} | |
| 5741 ins_pipe(iload_mem); | |
| 0 | 5742 %} |
| 5743 | |
| 5744 // Load Integer | |
| 5745 instruct loadI(iRegI dst, memory mem) %{ | |
| 5746 match(Set dst (LoadI mem)); | |
| 5747 ins_cost(MEMORY_REF_COST); | |
| 624 | 5748 |
| 5749 size(4); | |
| 5750 format %{ "LDUW $mem,$dst\t! int" %} | |
| 727 | 5751 ins_encode %{ |
| 5752 __ lduw($mem$$Address, $dst$$Register); | |
| 5753 %} | |
| 624 | 5754 ins_pipe(iload_mem); |
| 5755 %} | |
| 5756 | |
| 785 | 5757 // Load Integer to Byte (8 bit signed) |
| 5758 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5759 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 5760 ins_cost(MEMORY_REF_COST); | |
| 5761 | |
| 5762 size(4); | |
| 5763 | |
| 5764 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} | |
| 5765 ins_encode %{ | |
| 5766 __ ldsb($mem$$Address, $dst$$Register, 3); | |
| 5767 %} | |
| 5768 ins_pipe(iload_mask_mem); | |
| 5769 %} | |
| 5770 | |
| 5771 // Load Integer to Unsigned Byte (8 bit UNsigned) | |
| 5772 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5773 match(Set dst (AndI (LoadI mem) mask)); | |
| 5774 ins_cost(MEMORY_REF_COST); | |
| 5775 | |
| 5776 size(4); | |
| 5777 | |
| 5778 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} | |
| 5779 ins_encode %{ | |
| 5780 __ ldub($mem$$Address, $dst$$Register, 3); | |
| 5781 %} | |
| 5782 ins_pipe(iload_mask_mem); | |
| 5783 %} | |
| 5784 | |
| 5785 // Load Integer to Short (16 bit signed) | |
| 5786 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ | |
| 5787 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 5788 ins_cost(MEMORY_REF_COST); | |
| 5789 | |
| 5790 size(4); | |
| 5791 | |
| 5792 format %{ "LDSH $mem+2,$dst\t! int -> short" %} | |
| 5793 ins_encode %{ | |
| 5794 __ ldsh($mem$$Address, $dst$$Register, 2); | |
| 5795 %} | |
| 5796 ins_pipe(iload_mask_mem); | |
| 5797 %} | |
| 5798 | |
| 5799 // Load Integer to Unsigned Short (16 bit UNsigned) | |
| 5800 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5801 match(Set dst (AndI (LoadI mem) mask)); | |
| 5802 ins_cost(MEMORY_REF_COST); | |
| 5803 | |
| 5804 size(4); | |
| 5805 | |
| 5806 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} | |
| 5807 ins_encode %{ | |
| 5808 __ lduh($mem$$Address, $dst$$Register, 2); | |
| 5809 %} | |
| 5810 ins_pipe(iload_mask_mem); | |
| 5811 %} | |
| 5812 | |
| 624 | 5813 // Load Integer into a Long Register |
| 5814 instruct loadI2L(iRegL dst, memory mem) %{ | |
| 5815 match(Set dst (ConvI2L (LoadI mem))); | |
| 5816 ins_cost(MEMORY_REF_COST); | |
| 5817 | |
| 5818 size(4); | |
| 5819 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
| 727 | 5820 ins_encode %{ |
| 5821 __ ldsw($mem$$Address, $dst$$Register); | |
| 5822 %} | |
| 824 | 5823 ins_pipe(iload_mask_mem); |
| 5824 %} | |
| 5825 | |
| 5826 // Load Integer with mask 0xFF into a Long Register | |
| 5827 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5828 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5829 ins_cost(MEMORY_REF_COST); | |
| 5830 | |
| 5831 size(4); | |
| 5832 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} | |
| 5833 ins_encode %{ | |
| 5834 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE | |
| 5835 %} | |
| 5836 ins_pipe(iload_mem); | |
| 5837 %} | |
| 5838 | |
| 5839 // Load Integer with mask 0xFFFF into a Long Register | |
| 5840 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5841 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5842 ins_cost(MEMORY_REF_COST); | |
| 5843 | |
| 5844 size(4); | |
| 5845 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} | |
| 5846 ins_encode %{ | |
| 5847 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | |
| 5848 %} | |
| 5849 ins_pipe(iload_mem); | |
| 5850 %} | |
| 5851 | |
| 5852 // Load Integer with a 13-bit mask into a Long Register | |
| 5853 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
| 5854 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5855 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5856 | |
| 5857 size(2*4); | |
| 5858 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" | |
| 5859 "AND $dst,$mask,$dst" %} | |
| 5860 ins_encode %{ | |
| 5861 Register Rdst = $dst$$Register; | |
| 5862 __ lduw($mem$$Address, Rdst); | |
| 5863 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5864 %} | |
| 5865 ins_pipe(iload_mem); | |
| 5866 %} | |
| 5867 | |
| 5868 // Load Integer with a 32-bit mask into a Long Register | |
| 5869 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ | |
| 5870 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5871 effect(TEMP dst, TEMP tmp); | |
| 5872 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5873 | |
|
951
1fbd5d696bf4
6875967: CTW fails with./generated/adfiles/ad_sparc.cpp:6711
twisti
parents:
824
diff
changeset
|
5874 size((3+1)*4); // set may use two instructions. |
| 824 | 5875 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" |
| 5876 "SET $mask,$tmp\n\t" | |
| 5877 "AND $dst,$tmp,$dst" %} | |
| 5878 ins_encode %{ | |
| 5879 Register Rdst = $dst$$Register; | |
| 5880 Register Rtmp = $tmp$$Register; | |
| 5881 __ lduw($mem$$Address, Rdst); | |
| 5882 __ set($mask$$constant, Rtmp); | |
| 5883 __ and3(Rdst, Rtmp, Rdst); | |
| 5884 %} | |
| 624 | 5885 ins_pipe(iload_mem); |
| 5886 %} | |
| 5887 | |
| 5888 // Load Unsigned Integer into a Long Register | |
| 6849 | 5889 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{ |
| 5890 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
| 624 | 5891 ins_cost(MEMORY_REF_COST); |
| 5892 | |
| 5893 size(4); | |
| 5894 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
| 727 | 5895 ins_encode %{ |
| 5896 __ lduw($mem$$Address, $dst$$Register); | |
| 5897 %} | |
| 0 | 5898 ins_pipe(iload_mem); |
| 5899 %} | |
| 5900 | |
| 5901 // Load Long - aligned | |
| 5902 instruct loadL(iRegL dst, memory mem ) %{ | |
| 5903 match(Set dst (LoadL mem)); | |
| 5904 ins_cost(MEMORY_REF_COST); | |
| 624 | 5905 |
| 0 | 5906 size(4); |
| 5907 format %{ "LDX $mem,$dst\t! long" %} | |
| 727 | 5908 ins_encode %{ |
| 5909 __ ldx($mem$$Address, $dst$$Register); | |
| 5910 %} | |
| 0 | 5911 ins_pipe(iload_mem); |
| 5912 %} | |
| 5913 | |
| 5914 // Load Long - UNaligned | |
| 5915 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
| 5916 match(Set dst (LoadL_unaligned mem)); | |
| 5917 effect(KILL tmp); | |
| 5918 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 5919 size(16); | |
| 5920 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
| 5921 "\tLDUW $mem ,$dst\n" | |
| 5922 "\tSLLX #32, $dst, $dst\n" | |
| 5923 "\tOR $dst, R_O7, $dst" %} | |
| 5924 opcode(Assembler::lduw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5925 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
| 0 | 5926 ins_pipe(iload_mem); |
| 5927 %} | |
| 5928 | |
| 5929 // Load Range | |
| 5930 instruct loadRange(iRegI dst, memory mem) %{ | |
| 5931 match(Set dst (LoadRange mem)); | |
| 5932 ins_cost(MEMORY_REF_COST); | |
| 5933 | |
| 5934 size(4); | |
| 5935 format %{ "LDUW $mem,$dst\t! range" %} | |
| 5936 opcode(Assembler::lduw_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
235
diff
changeset
|
5937 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5938 ins_pipe(iload_mem); |
| 5939 %} | |
| 5940 | |
| 5941 // Load Integer into %f register (for fitos/fitod) | |
| 5942 instruct loadI_freg(regF dst, memory mem) %{ | |
| 5943 match(Set dst (LoadI mem)); | |
| 5944 ins_cost(MEMORY_REF_COST); | |
| 5945 size(4); | |
| 5946 | |
| 5947 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
| 5948 opcode(Assembler::ldf_op3); | |
|
415
4d9884b01ba6
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parents:
235
diff
changeset
|
5949 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5950 ins_pipe(floadF_mem); |
| 5951 %} | |
| 5952 | |
| 5953 // Load Pointer | |
| 5954 instruct loadP(iRegP dst, memory mem) %{ | |
| 5955 match(Set dst (LoadP mem)); | |
| 5956 ins_cost(MEMORY_REF_COST); | |
| 5957 size(4); | |
| 5958 | |
| 5959 #ifndef _LP64 | |
| 5960 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 727 | 5961 ins_encode %{ |
| 5962 __ lduw($mem$$Address, $dst$$Register); | |
| 5963 %} | |
| 0 | 5964 #else |
| 5965 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 727 | 5966 ins_encode %{ |
| 5967 __ ldx($mem$$Address, $dst$$Register); | |
| 5968 %} | |
| 0 | 5969 #endif |
| 5970 ins_pipe(iload_mem); | |
| 5971 %} | |
| 5972 | |
|
113
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coleenp
parents:
81
diff
changeset
|
5973 // Load Compressed Pointer |
|
ba764ed4b6f2
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parents:
81
diff
changeset
|
5974 instruct loadN(iRegN dst, memory mem) %{ |
| 727 | 5975 match(Set dst (LoadN mem)); |
| 5976 ins_cost(MEMORY_REF_COST); | |
| 5977 size(4); | |
| 5978 | |
| 5979 format %{ "LDUW $mem,$dst\t! compressed ptr" %} | |
| 5980 ins_encode %{ | |
| 5981 __ lduw($mem$$Address, $dst$$Register); | |
| 5982 %} | |
| 5983 ins_pipe(iload_mem); | |
|
113
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81
diff
changeset
|
5984 %} |
|
ba764ed4b6f2
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81
diff
changeset
|
5985 |
| 0 | 5986 // Load Klass Pointer |
| 5987 instruct loadKlass(iRegP dst, memory mem) %{ | |
| 5988 match(Set dst (LoadKlass mem)); | |
| 5989 ins_cost(MEMORY_REF_COST); | |
| 5990 size(4); | |
| 5991 | |
| 5992 #ifndef _LP64 | |
| 5993 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
| 727 | 5994 ins_encode %{ |
| 5995 __ lduw($mem$$Address, $dst$$Register); | |
| 5996 %} | |
| 0 | 5997 #else |
| 5998 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
| 727 | 5999 ins_encode %{ |
| 6000 __ ldx($mem$$Address, $dst$$Register); | |
| 6001 %} | |
| 0 | 6002 #endif |
| 6003 ins_pipe(iload_mem); | |
| 6004 %} | |
| 6005 | |
|
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6006 // Load narrow Klass Pointer |
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6007 instruct loadNKlass(iRegN dst, memory mem) %{ |
|
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6008 match(Set dst (LoadNKlass mem)); |
|
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6009 ins_cost(MEMORY_REF_COST); |
|
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6010 size(4); |
|
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|
6011 |
|
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|
6012 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
|
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6013 ins_encode %{ |
| 727 | 6014 __ lduw($mem$$Address, $dst$$Register); |
|
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|
6015 %} |
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|
6016 ins_pipe(iload_mem); |
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6017 %} |
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6018 |
| 0 | 6019 // Load Double |
| 6020 instruct loadD(regD dst, memory mem) %{ | |
| 6021 match(Set dst (LoadD mem)); | |
| 6022 ins_cost(MEMORY_REF_COST); | |
| 6023 | |
| 6024 size(4); | |
| 6025 format %{ "LDDF $mem,$dst" %} | |
| 6026 opcode(Assembler::lddf_op3); | |
|
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6027 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 6028 ins_pipe(floadD_mem); |
| 6029 %} | |
| 6030 | |
| 6031 // Load Double - UNaligned | |
| 6032 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
| 6033 match(Set dst (LoadD_unaligned mem)); | |
| 6034 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 6035 size(8); | |
| 6036 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
| 6037 "\tLDF $mem+4,$dst.lo\t!" %} | |
| 6038 opcode(Assembler::ldf_op3); | |
| 6039 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
| 6040 ins_pipe(iload_mem); | |
| 6041 %} | |
| 6042 | |
| 6043 // Load Float | |
| 6044 instruct loadF(regF dst, memory mem) %{ | |
| 6045 match(Set dst (LoadF mem)); | |
| 6046 ins_cost(MEMORY_REF_COST); | |
| 6047 | |
| 6048 size(4); | |
| 6049 format %{ "LDF $mem,$dst" %} | |
| 6050 opcode(Assembler::ldf_op3); | |
|
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6051 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 6052 ins_pipe(floadF_mem); |
| 6053 %} | |
| 6054 | |
| 6055 // Load Constant | |
| 6056 instruct loadConI( iRegI dst, immI src ) %{ | |
| 6057 match(Set dst src); | |
| 6058 ins_cost(DEFAULT_COST * 3/2); | |
| 6059 format %{ "SET $src,$dst" %} | |
| 6060 ins_encode( Set32(src, dst) ); | |
| 6061 ins_pipe(ialu_hi_lo_reg); | |
| 6062 %} | |
| 6063 | |
| 6064 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
| 6065 match(Set dst src); | |
| 6066 | |
| 6067 size(4); | |
| 6068 format %{ "MOV $src,$dst" %} | |
| 6069 ins_encode( Set13( src, dst ) ); | |
| 6070 ins_pipe(ialu_imm); | |
| 6071 %} | |
| 6072 | |
| 2008 | 6073 #ifndef _LP64 |
| 6074 instruct loadConP(iRegP dst, immP con) %{ | |
| 6075 match(Set dst con); | |
| 6076 ins_cost(DEFAULT_COST * 3/2); | |
| 6077 format %{ "SET $con,$dst\t!ptr" %} | |
| 6078 ins_encode %{ | |
|
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|
6079 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); |
| 2008 | 6080 intptr_t val = $con$$constant; |
|
6725
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|
6081 if (constant_reloc == relocInfo::oop_type) { |
| 2008 | 6082 __ set_oop_constant((jobject) val, $dst$$Register); |
|
6725
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|
6083 } else if (constant_reloc == relocInfo::metadata_type) { |
|
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|
6084 __ set_metadata_constant((Metadata*)val, $dst$$Register); |
| 2008 | 6085 } else { // non-oop pointers, e.g. card mark base, heap top |
|
6725
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|
6086 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); |
|
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|
6087 __ set(val, $dst$$Register); |
| 2008 | 6088 } |
| 6089 %} | |
| 6090 ins_pipe(loadConP); | |
| 6091 %} | |
| 6092 #else | |
| 6093 instruct loadConP_set(iRegP dst, immP_set con) %{ | |
| 6094 match(Set dst con); | |
| 0 | 6095 ins_cost(DEFAULT_COST * 3/2); |
| 2008 | 6096 format %{ "SET $con,$dst\t! ptr" %} |
| 6097 ins_encode %{ | |
|
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|
6098 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); |
| 2008 | 6099 intptr_t val = $con$$constant; |
|
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|
6100 if (constant_reloc == relocInfo::oop_type) { |
| 2008 | 6101 __ set_oop_constant((jobject) val, $dst$$Register); |
|
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|
6102 } else if (constant_reloc == relocInfo::metadata_type) { |
|
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|
6103 __ set_metadata_constant((Metadata*)val, $dst$$Register); |
| 2008 | 6104 } else { // non-oop pointers, e.g. card mark base, heap top |
|
6725
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|
6105 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); |
|
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|
6106 __ set(val, $dst$$Register); |
| 2008 | 6107 } |
| 6108 %} | |
| 0 | 6109 ins_pipe(loadConP); |
| 2008 | 6110 %} |
| 6111 | |
| 6112 instruct loadConP_load(iRegP dst, immP_load con) %{ | |
| 6113 match(Set dst con); | |
| 6114 ins_cost(MEMORY_REF_COST); | |
| 6115 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} | |
| 6116 ins_encode %{ | |
|
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|
6117 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
|
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|
6118 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); |
|
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|
6119 %} |
|
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|
6120 ins_pipe(loadConP); |
|
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|
6121 %} |
|
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|
6122 |
|
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|
6123 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ |
|
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|
6124 match(Set dst con); |
|
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|
6125 ins_cost(DEFAULT_COST * 3/2); |
|
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|
6126 format %{ "SET $con,$dst\t! non-oop ptr" %} |
|
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|
6127 ins_encode %{ |
|
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|
6128 __ set($con$$constant, $dst$$Register); |
| 2008 | 6129 %} |
| 6130 ins_pipe(loadConP); | |
| 6131 %} | |
| 6132 #endif // _LP64 | |
| 0 | 6133 |
| 6134 instruct loadConP0(iRegP dst, immP0 src) %{ | |
| 6135 match(Set dst src); | |
| 6136 | |
| 6137 size(4); | |
| 6138 format %{ "CLR $dst\t!ptr" %} | |
| 2008 | 6139 ins_encode %{ |
| 6140 __ clr($dst$$Register); | |
| 6141 %} | |
| 0 | 6142 ins_pipe(ialu_imm); |
| 6143 %} | |
| 6144 | |
| 6145 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
| 6146 match(Set dst src); | |
| 6147 ins_cost(DEFAULT_COST); | |
| 6148 format %{ "SET $src,$dst\t!ptr" %} | |
| 6149 ins_encode %{ | |
| 727 | 6150 AddressLiteral polling_page(os::get_polling_page()); |
| 6151 __ sethi(polling_page, reg_to_register_object($dst$$reg)); | |
| 0 | 6152 %} |
| 6153 ins_pipe(loadConP_poll); | |
| 6154 %} | |
| 6155 | |
|
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6156 instruct loadConN0(iRegN dst, immN0 src) %{ |
|
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|
6157 match(Set dst src); |
|
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|
6158 |
|
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|
6159 size(4); |
|
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|
6160 format %{ "CLR $dst\t! compressed NULL ptr" %} |
| 2008 | 6161 ins_encode %{ |
| 6162 __ clr($dst$$Register); | |
| 6163 %} | |
|
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|
6164 ins_pipe(ialu_imm); |
|
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|
6165 %} |
|
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|
6166 |
|
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|
6167 instruct loadConN(iRegN dst, immN src) %{ |
|
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|
6168 match(Set dst src); |
|
164
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|
6169 ins_cost(DEFAULT_COST * 3/2); |
|
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|
6170 format %{ "SET $src,$dst\t! compressed ptr" %} |
|
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|
6171 ins_encode %{ |
|
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|
6172 Register dst = $dst$$Register; |
|
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|
6173 __ set_narrow_oop((jobject)$src$$constant, dst); |
|
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|
6174 %} |
|
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|
6175 ins_pipe(ialu_hi_lo_reg); |
|
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|
6176 %} |
|
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|
6177 |
|
6848
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6823
diff
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|
6178 instruct loadConNKlass(iRegN dst, immNKlass src) %{ |
|
8e47bac5643a
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6823
diff
changeset
|
6179 match(Set dst src); |
|
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|
6180 ins_cost(DEFAULT_COST * 3/2); |
|
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diff
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|
6181 format %{ "SET $src,$dst\t! compressed klass ptr" %} |
|
8e47bac5643a
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roland
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6823
diff
changeset
|
6182 ins_encode %{ |
|
8e47bac5643a
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6823
diff
changeset
|
6183 Register dst = $dst$$Register; |
|
8e47bac5643a
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6823
diff
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|
6184 __ set_narrow_klass((Klass*)$src$$constant, dst); |
|
8e47bac5643a
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6823
diff
changeset
|
6185 %} |
|
8e47bac5643a
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6823
diff
changeset
|
6186 ins_pipe(ialu_hi_lo_reg); |
|
8e47bac5643a
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6823
diff
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|
6187 %} |
|
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|
6188 |
| 2008 | 6189 // Materialize long value (predicated by immL_cheap). |
| 6190 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ | |
| 6191 match(Set dst con); | |
| 0 | 6192 effect(KILL tmp); |
| 2008 | 6193 ins_cost(DEFAULT_COST * 3); |
| 6194 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} | |
| 6195 ins_encode %{ | |
| 6196 __ set64($con$$constant, $dst$$Register, $tmp$$Register); | |
| 6197 %} | |
| 6198 ins_pipe(loadConL); | |
| 6199 %} | |
| 6200 | |
| 6201 // Load long value from constant table (predicated by immL_expensive). | |
| 6202 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ | |
| 6203 match(Set dst con); | |
| 6204 ins_cost(MEMORY_REF_COST); | |
| 6205 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} | |
| 6206 ins_encode %{ | |
|
2012
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2008
diff
changeset
|
6207 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
|
5fe0781a8560
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2008
diff
changeset
|
6208 __ ldx($constanttablebase, con_offset, $dst$$Register); |
| 2008 | 6209 %} |
| 0 | 6210 ins_pipe(loadConL); |
| 6211 %} | |
| 6212 | |
| 6213 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
| 6214 match(Set dst src); | |
| 6215 ins_cost(DEFAULT_COST); | |
| 6216 size(4); | |
| 6217 format %{ "CLR $dst\t! long" %} | |
| 6218 ins_encode( Set13( src, dst ) ); | |
| 6219 ins_pipe(ialu_imm); | |
| 6220 %} | |
| 6221 | |
| 6222 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
| 6223 match(Set dst src); | |
| 6224 ins_cost(DEFAULT_COST * 2); | |
| 6225 | |
| 6226 size(4); | |
| 6227 format %{ "MOV $src,$dst\t! long" %} | |
| 6228 ins_encode( Set13( src, dst ) ); | |
| 6229 ins_pipe(ialu_imm); | |
| 6230 %} | |
| 6231 | |
|
2012
5fe0781a8560
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2008
diff
changeset
|
6232 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ |
| 2008 | 6233 match(Set dst con); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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2008
diff
changeset
|
6234 effect(KILL tmp); |
| 2008 | 6235 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} |
| 727 | 6236 ins_encode %{ |
|
2012
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7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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2008
diff
changeset
|
6237 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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2008
diff
changeset
|
6238 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); |
| 727 | 6239 %} |
| 0 | 6240 ins_pipe(loadConFD); |
| 6241 %} | |
| 6242 | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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2008
diff
changeset
|
6243 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ |
| 2008 | 6244 match(Set dst con); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
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2008
diff
changeset
|
6245 effect(KILL tmp); |
| 2008 | 6246 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} |
| 727 | 6247 ins_encode %{ |
|
732
fb4c18a2ec66
6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents:
727
diff
changeset
|
6248 // XXX This is a quick fix for 6833573. |
| 2008 | 6249 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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2008
diff
changeset
|
6250 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
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2008
diff
changeset
|
6251 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 727 | 6252 %} |
| 0 | 6253 ins_pipe(loadConFD); |
| 6254 %} | |
| 6255 | |
| 6256 // Prefetch instructions. | |
| 6257 // Must be safe to execute with invalid address (cannot fault). | |
| 6258 | |
| 6259 instruct prefetchr( memory mem ) %{ | |
| 6260 match( PrefetchRead mem ); | |
| 6261 ins_cost(MEMORY_REF_COST); | |
| 3854 | 6262 size(4); |
| 0 | 6263 |
| 6264 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
| 6265 opcode(Assembler::prefetch_op3); | |
| 6266 ins_encode( form3_mem_prefetch_read( mem ) ); | |
| 6267 ins_pipe(iload_mem); | |
| 6268 %} | |
| 6269 | |
| 6270 instruct prefetchw( memory mem ) %{ | |
| 6271 match( PrefetchWrite mem ); | |
| 6272 ins_cost(MEMORY_REF_COST); | |
| 3854 | 6273 size(4); |
| 0 | 6274 |
| 6275 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
| 6276 opcode(Assembler::prefetch_op3); | |
| 6277 ins_encode( form3_mem_prefetch_write( mem ) ); | |
| 6278 ins_pipe(iload_mem); | |
| 6279 %} | |
| 6280 | |
| 3854 | 6281 // Prefetch instructions for allocation. |
| 6282 | |
| 6283 instruct prefetchAlloc( memory mem ) %{ | |
| 6284 predicate(AllocatePrefetchInstr == 0); | |
| 6285 match( PrefetchAllocation mem ); | |
| 6286 ins_cost(MEMORY_REF_COST); | |
| 6287 size(4); | |
| 6288 | |
| 6289 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %} | |
| 6290 opcode(Assembler::prefetch_op3); | |
| 6291 ins_encode( form3_mem_prefetch_write( mem ) ); | |
| 6292 ins_pipe(iload_mem); | |
| 6293 %} | |
| 6294 | |
| 6295 // Use BIS instruction to prefetch for allocation. | |
| 6296 // Could fault, need space at the end of TLAB. | |
| 6297 instruct prefetchAlloc_bis( iRegP dst ) %{ | |
| 6298 predicate(AllocatePrefetchInstr == 1); | |
| 6299 match( PrefetchAllocation dst ); | |
| 6300 ins_cost(MEMORY_REF_COST); | |
| 6301 size(4); | |
| 6302 | |
| 6303 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %} | |
| 6304 ins_encode %{ | |
| 6305 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); | |
|
1367
9e321dcfa5b7
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1274
diff
changeset
|
6306 %} |
|
9e321dcfa5b7
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1274
diff
changeset
|
6307 ins_pipe(istore_mem_reg); |
|
9e321dcfa5b7
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1274
diff
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|
6308 %} |
| 0 | 6309 |
| 3854 | 6310 // Next code is used for finding next cache line address to prefetch. |
| 6311 #ifndef _LP64 | |
| 6312 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{ | |
| 6313 match(Set dst (CastX2P (AndI (CastP2X src) mask))); | |
| 6314 ins_cost(DEFAULT_COST); | |
| 6315 size(4); | |
| 6316 | |
| 6317 format %{ "AND $src,$mask,$dst\t! next cache line address" %} | |
| 6318 ins_encode %{ | |
| 6319 __ and3($src$$Register, $mask$$constant, $dst$$Register); | |
| 6320 %} | |
| 6321 ins_pipe(ialu_reg_imm); | |
| 6322 %} | |
| 6323 #else | |
| 6324 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{ | |
| 6325 match(Set dst (CastX2P (AndL (CastP2X src) mask))); | |
| 6326 ins_cost(DEFAULT_COST); | |
| 6327 size(4); | |
| 6328 | |
| 6329 format %{ "AND $src,$mask,$dst\t! next cache line address" %} | |
| 6330 ins_encode %{ | |
| 6331 __ and3($src$$Register, $mask$$constant, $dst$$Register); | |
| 6332 %} | |
| 6333 ins_pipe(ialu_reg_imm); | |
| 6334 %} | |
| 6335 #endif | |
| 6336 | |
| 0 | 6337 //----------Store Instructions------------------------------------------------- |
| 6338 // Store Byte | |
| 6339 instruct storeB(memory mem, iRegI src) %{ | |
| 6340 match(Set mem (StoreB mem src)); | |
| 6341 ins_cost(MEMORY_REF_COST); | |
| 6342 | |
| 6343 size(4); | |
| 6344 format %{ "STB $src,$mem\t! byte" %} | |
| 6345 opcode(Assembler::stb_op3); | |
|
415
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235
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|
6346 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6347 ins_pipe(istore_mem_reg); |
| 6348 %} | |
| 6349 | |
| 6350 instruct storeB0(memory mem, immI0 src) %{ | |
| 6351 match(Set mem (StoreB mem src)); | |
| 6352 ins_cost(MEMORY_REF_COST); | |
| 6353 | |
| 6354 size(4); | |
| 6355 format %{ "STB $src,$mem\t! byte" %} | |
| 6356 opcode(Assembler::stb_op3); | |
|
415
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235
diff
changeset
|
6357 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6358 ins_pipe(istore_mem_zero); |
| 6359 %} | |
| 6360 | |
| 6361 instruct storeCM0(memory mem, immI0 src) %{ | |
| 6362 match(Set mem (StoreCM mem src)); | |
| 6363 ins_cost(MEMORY_REF_COST); | |
| 6364 | |
| 6365 size(4); | |
| 6366 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
| 6367 opcode(Assembler::stb_op3); | |
|
415
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parents:
235
diff
changeset
|
6368 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6369 ins_pipe(istore_mem_zero); |
| 6370 %} | |
| 6371 | |
| 6372 // Store Char/Short | |
| 6373 instruct storeC(memory mem, iRegI src) %{ | |
| 6374 match(Set mem (StoreC mem src)); | |
| 6375 ins_cost(MEMORY_REF_COST); | |
| 6376 | |
| 6377 size(4); | |
| 6378 format %{ "STH $src,$mem\t! short" %} | |
| 6379 opcode(Assembler::sth_op3); | |
|
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
235
diff
changeset
|
6380 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6381 ins_pipe(istore_mem_reg); |
| 6382 %} | |
| 6383 | |
| 6384 instruct storeC0(memory mem, immI0 src) %{ | |
| 6385 match(Set mem (StoreC mem src)); | |
| 6386 ins_cost(MEMORY_REF_COST); | |
| 6387 | |
| 6388 size(4); | |
| 6389 format %{ "STH $src,$mem\t! short" %} | |
| 6390 opcode(Assembler::sth_op3); | |
|
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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235
diff
changeset
|
6391 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6392 ins_pipe(istore_mem_zero); |
| 6393 %} | |
| 6394 | |
| 6395 // Store Integer | |
| 6396 instruct storeI(memory mem, iRegI src) %{ | |
| 6397 match(Set mem (StoreI mem src)); | |
| 6398 ins_cost(MEMORY_REF_COST); | |
| 6399 | |
| 6400 size(4); | |
| 6401 format %{ "STW $src,$mem" %} | |
| 6402 opcode(Assembler::stw_op3); | |
|
415
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235
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|
6403 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6404 ins_pipe(istore_mem_reg); |
| 6405 %} | |
| 6406 | |
| 6407 // Store Long | |
| 6408 instruct storeL(memory mem, iRegL src) %{ | |
| 6409 match(Set mem (StoreL mem src)); | |
| 6410 ins_cost(MEMORY_REF_COST); | |
| 6411 size(4); | |
| 6412 format %{ "STX $src,$mem\t! long" %} | |
| 6413 opcode(Assembler::stx_op3); | |
|
415
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parents:
235
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|
6414 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6415 ins_pipe(istore_mem_reg); |
| 6416 %} | |
| 6417 | |
| 6418 instruct storeI0(memory mem, immI0 src) %{ | |
| 6419 match(Set mem (StoreI mem src)); | |
| 6420 ins_cost(MEMORY_REF_COST); | |
| 6421 | |
| 6422 size(4); | |
| 6423 format %{ "STW $src,$mem" %} | |
| 6424 opcode(Assembler::stw_op3); | |
|
415
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never
parents:
235
diff
changeset
|
6425 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6426 ins_pipe(istore_mem_zero); |
| 6427 %} | |
| 6428 | |
| 6429 instruct storeL0(memory mem, immL0 src) %{ | |
| 6430 match(Set mem (StoreL mem src)); | |
| 6431 ins_cost(MEMORY_REF_COST); | |
| 6432 | |
| 6433 size(4); | |
| 6434 format %{ "STX $src,$mem" %} | |
| 6435 opcode(Assembler::stx_op3); | |
|
415
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parents:
235
diff
changeset
|
6436 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6437 ins_pipe(istore_mem_zero); |
| 6438 %} | |
| 6439 | |
| 6440 // Store Integer from float register (used after fstoi) | |
| 6441 instruct storeI_Freg(memory mem, regF src) %{ | |
| 6442 match(Set mem (StoreI mem src)); | |
| 6443 ins_cost(MEMORY_REF_COST); | |
| 6444 | |
| 6445 size(4); | |
| 6446 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
| 6447 opcode(Assembler::stf_op3); | |
|
415
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235
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|
6448 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6449 ins_pipe(fstoreF_mem_reg); |
| 6450 %} | |
| 6451 | |
| 6452 // Store Pointer | |
| 6453 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
| 6454 match(Set dst (StoreP dst src)); | |
| 6455 ins_cost(MEMORY_REF_COST); | |
| 6456 size(4); | |
| 6457 | |
| 6458 #ifndef _LP64 | |
| 6459 format %{ "STW $src,$dst\t! ptr" %} | |
| 6460 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6461 #else | |
| 6462 format %{ "STX $src,$dst\t! ptr" %} | |
| 6463 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6464 #endif | |
| 6465 ins_encode( form3_mem_reg( dst, src ) ); | |
| 6466 ins_pipe(istore_mem_spORreg); | |
| 6467 %} | |
| 6468 | |
| 6469 instruct storeP0(memory dst, immP0 src) %{ | |
| 6470 match(Set dst (StoreP dst src)); | |
| 6471 ins_cost(MEMORY_REF_COST); | |
| 6472 size(4); | |
| 6473 | |
| 6474 #ifndef _LP64 | |
| 6475 format %{ "STW $src,$dst\t! ptr" %} | |
| 6476 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6477 #else | |
| 6478 format %{ "STX $src,$dst\t! ptr" %} | |
| 6479 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6480 #endif | |
| 6481 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
| 6482 ins_pipe(istore_mem_zero); | |
| 6483 %} | |
| 6484 | |
|
113
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|
6485 // Store Compressed Pointer |
|
ba764ed4b6f2
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81
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|
6486 instruct storeN(memory dst, iRegN src) %{ |
|
ba764ed4b6f2
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81
diff
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|
6487 match(Set dst (StoreN dst src)); |
|
ba764ed4b6f2
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81
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|
6488 ins_cost(MEMORY_REF_COST); |
|
ba764ed4b6f2
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81
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|
6489 size(4); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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81
diff
changeset
|
6490 |
|
ba764ed4b6f2
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81
diff
changeset
|
6491 format %{ "STW $src,$dst\t! compressed ptr" %} |
|
ba764ed4b6f2
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coleenp
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81
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changeset
|
6492 ins_encode %{ |
|
ba764ed4b6f2
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coleenp
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81
diff
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|
6493 Register base = as_Register($dst$$base); |
|
ba764ed4b6f2
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81
diff
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|
6494 Register index = as_Register($dst$$index); |
|
ba764ed4b6f2
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81
diff
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|
6495 Register src = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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81
diff
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|
6496 if (index != G0) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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81
diff
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|
6497 __ stw(src, base, index); |
|
ba764ed4b6f2
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|
6498 } else { |
|
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diff
changeset
|
6499 __ stw(src, base, $dst$$disp); |
|
ba764ed4b6f2
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|
6500 } |
|
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|
6501 %} |
|
ba764ed4b6f2
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|
6502 ins_pipe(istore_mem_spORreg); |
|
ba764ed4b6f2
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|
6503 %} |
|
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|
6504 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
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6823
diff
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|
6505 instruct storeNKlass(memory dst, iRegN src) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
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6823
diff
changeset
|
6506 match(Set dst (StoreNKlass dst src)); |
|
8e47bac5643a
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diff
changeset
|
6507 ins_cost(MEMORY_REF_COST); |
|
8e47bac5643a
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roland
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diff
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|
6508 size(4); |
|
8e47bac5643a
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diff
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|
6509 |
|
8e47bac5643a
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diff
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|
6510 format %{ "STW $src,$dst\t! compressed klass ptr" %} |
|
8e47bac5643a
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diff
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|
6511 ins_encode %{ |
|
8e47bac5643a
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diff
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|
6512 Register base = as_Register($dst$$base); |
|
8e47bac5643a
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diff
changeset
|
6513 Register index = as_Register($dst$$index); |
|
8e47bac5643a
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diff
changeset
|
6514 Register src = $src$$Register; |
|
8e47bac5643a
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6823
diff
changeset
|
6515 if (index != G0) { |
|
8e47bac5643a
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6823
diff
changeset
|
6516 __ stw(src, base, index); |
|
8e47bac5643a
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diff
changeset
|
6517 } else { |
|
8e47bac5643a
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diff
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|
6518 __ stw(src, base, $dst$$disp); |
|
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6823
diff
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|
6519 } |
|
8e47bac5643a
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diff
changeset
|
6520 %} |
|
8e47bac5643a
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diff
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|
6521 ins_pipe(istore_mem_spORreg); |
|
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diff
changeset
|
6522 %} |
|
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|
6523 |
|
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6524 instruct storeN0(memory dst, immN0 src) %{ |
|
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6525 match(Set dst (StoreN dst src)); |
|
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|
6526 ins_cost(MEMORY_REF_COST); |
|
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|
6527 size(4); |
|
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|
6528 |
|
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changeset
|
6529 format %{ "STW $src,$dst\t! compressed ptr" %} |
|
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|
6530 ins_encode %{ |
|
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|
6531 Register base = as_Register($dst$$base); |
|
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changeset
|
6532 Register index = as_Register($dst$$index); |
|
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6533 if (index != G0) { |
|
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|
6534 __ stw(0, base, index); |
|
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|
6535 } else { |
|
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|
6536 __ stw(0, base, $dst$$disp); |
|
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|
6537 } |
|
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|
6538 %} |
|
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|
6539 ins_pipe(istore_mem_zero); |
|
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|
6540 %} |
|
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|
6541 |
| 0 | 6542 // Store Double |
| 6543 instruct storeD( memory mem, regD src) %{ | |
| 6544 match(Set mem (StoreD mem src)); | |
| 6545 ins_cost(MEMORY_REF_COST); | |
| 6546 | |
| 6547 size(4); | |
| 6548 format %{ "STDF $src,$mem" %} | |
| 6549 opcode(Assembler::stdf_op3); | |
|
415
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|
6550 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6551 ins_pipe(fstoreD_mem_reg); |
| 6552 %} | |
| 6553 | |
| 6554 instruct storeD0( memory mem, immD0 src) %{ | |
| 6555 match(Set mem (StoreD mem src)); | |
| 6556 ins_cost(MEMORY_REF_COST); | |
| 6557 | |
| 6558 size(4); | |
| 6559 format %{ "STX $src,$mem" %} | |
| 6560 opcode(Assembler::stx_op3); | |
|
415
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|
6561 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6562 ins_pipe(fstoreD_mem_zero); |
| 6563 %} | |
| 6564 | |
| 6565 // Store Float | |
| 6566 instruct storeF( memory mem, regF src) %{ | |
| 6567 match(Set mem (StoreF mem src)); | |
| 6568 ins_cost(MEMORY_REF_COST); | |
| 6569 | |
| 6570 size(4); | |
| 6571 format %{ "STF $src,$mem" %} | |
| 6572 opcode(Assembler::stf_op3); | |
|
415
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|
6573 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6574 ins_pipe(fstoreF_mem_reg); |
| 6575 %} | |
| 6576 | |
| 6577 instruct storeF0( memory mem, immF0 src) %{ | |
| 6578 match(Set mem (StoreF mem src)); | |
| 6579 ins_cost(MEMORY_REF_COST); | |
| 6580 | |
| 6581 size(4); | |
| 6582 format %{ "STW $src,$mem\t! storeF0" %} | |
| 6583 opcode(Assembler::stw_op3); | |
|
415
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|
6584 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6585 ins_pipe(fstoreF_mem_zero); |
| 6586 %} | |
| 6587 | |
|
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|
6588 // Convert oop pointer into compressed form |
|
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|
6589 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
|
221
1e026f8da827
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|
6590 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
113
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|
6591 match(Set dst (EncodeP src)); |
|
124
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|
6592 format %{ "encode_heap_oop $src, $dst" %} |
|
113
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|
6593 ins_encode %{ |
|
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|
6594 __ encode_heap_oop($src$$Register, $dst$$Register); |
|
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|
6595 %} |
|
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|
6596 ins_pipe(ialu_reg); |
|
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|
6597 %} |
|
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|
6598 |
|
124
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|
6599 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
|
221
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|
6600 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
124
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|
6601 match(Set dst (EncodeP src)); |
|
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|
6602 format %{ "encode_heap_oop_not_null $src, $dst" %} |
|
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|
6603 ins_encode %{ |
|
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|
6604 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
|
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|
6605 %} |
|
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|
6606 ins_pipe(ialu_reg); |
|
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|
6607 %} |
|
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|
6608 |
|
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|
6609 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
|
182
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|
6610 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
|
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|
6611 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
|
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|
6612 match(Set dst (DecodeN src)); |
|
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|
6613 format %{ "decode_heap_oop $src, $dst" %} |
|
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|
6614 ins_encode %{ |
|
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|
6615 __ decode_heap_oop($src$$Register, $dst$$Register); |
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|
6616 %} |
|
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|
6617 ins_pipe(ialu_reg); |
|
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|
6618 %} |
|
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|
6619 |
|
124
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|
6620 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
|
182
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|
6621 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
|
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|
6622 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
|
124
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|
6623 match(Set dst (DecodeN src)); |
|
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|
6624 format %{ "decode_heap_oop_not_null $src, $dst" %} |
|
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|
6625 ins_encode %{ |
|
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|
6626 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
|
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|
6627 %} |
|
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changeset
|
6628 ins_pipe(ialu_reg); |
|
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|
6629 %} |
|
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|
6630 |
|
6848
8e47bac5643a
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6823
diff
changeset
|
6631 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{ |
|
8e47bac5643a
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roland
parents:
6823
diff
changeset
|
6632 match(Set dst (EncodePKlass src)); |
|
8e47bac5643a
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6823
diff
changeset
|
6633 format %{ "encode_klass_not_null $src, $dst" %} |
|
8e47bac5643a
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6823
diff
changeset
|
6634 ins_encode %{ |
|
8e47bac5643a
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6823
diff
changeset
|
6635 __ encode_klass_not_null($src$$Register, $dst$$Register); |
|
8e47bac5643a
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roland
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6823
diff
changeset
|
6636 %} |
|
8e47bac5643a
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roland
parents:
6823
diff
changeset
|
6637 ins_pipe(ialu_reg); |
|
8e47bac5643a
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roland
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6823
diff
changeset
|
6638 %} |
|
8e47bac5643a
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roland
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6823
diff
changeset
|
6639 |
|
8e47bac5643a
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roland
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6823
diff
changeset
|
6640 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6641 match(Set dst (DecodeNKlass src)); |
|
8e47bac5643a
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roland
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6823
diff
changeset
|
6642 format %{ "decode_klass_not_null $src, $dst" %} |
|
8e47bac5643a
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roland
parents:
6823
diff
changeset
|
6643 ins_encode %{ |
|
8e47bac5643a
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roland
parents:
6823
diff
changeset
|
6644 __ decode_klass_not_null($src$$Register, $dst$$Register); |
|
8e47bac5643a
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roland
parents:
6823
diff
changeset
|
6645 %} |
|
8e47bac5643a
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roland
parents:
6823
diff
changeset
|
6646 ins_pipe(ialu_reg); |
|
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diff
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|
6647 %} |
|
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|
6648 |
| 0 | 6649 //----------MemBar Instructions----------------------------------------------- |
| 6650 // Memory barrier flavors | |
| 6651 | |
| 6652 instruct membar_acquire() %{ | |
| 6653 match(MemBarAcquire); | |
|
14439
50fdb38839eb
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
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14435
diff
changeset
|
6654 match(LoadFence); |
| 0 | 6655 ins_cost(4*MEMORY_REF_COST); |
| 6656 | |
| 6657 size(0); | |
| 6658 format %{ "MEMBAR-acquire" %} | |
| 6659 ins_encode( enc_membar_acquire ); | |
| 6660 ins_pipe(long_memory_op); | |
| 6661 %} | |
| 6662 | |
| 6663 instruct membar_acquire_lock() %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
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3842
diff
changeset
|
6664 match(MemBarAcquireLock); |
| 0 | 6665 ins_cost(0); |
| 6666 | |
| 6667 size(0); | |
| 6668 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
| 6669 ins_encode( ); | |
| 6670 ins_pipe(empty); | |
| 6671 %} | |
| 6672 | |
| 6673 instruct membar_release() %{ | |
| 6674 match(MemBarRelease); | |
|
14439
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14435
diff
changeset
|
6675 match(StoreFence); |
| 0 | 6676 ins_cost(4*MEMORY_REF_COST); |
| 6677 | |
| 6678 size(0); | |
| 6679 format %{ "MEMBAR-release" %} | |
| 6680 ins_encode( enc_membar_release ); | |
| 6681 ins_pipe(long_memory_op); | |
| 6682 %} | |
| 6683 | |
| 6684 instruct membar_release_lock() %{ | |
|
3849
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diff
changeset
|
6685 match(MemBarReleaseLock); |
| 0 | 6686 ins_cost(0); |
| 6687 | |
| 6688 size(0); | |
| 6689 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
| 6690 ins_encode( ); | |
| 6691 ins_pipe(empty); | |
| 6692 %} | |
| 6693 | |
| 6694 instruct membar_volatile() %{ | |
| 6695 match(MemBarVolatile); | |
| 6696 ins_cost(4*MEMORY_REF_COST); | |
| 6697 | |
| 6698 size(4); | |
| 6699 format %{ "MEMBAR-volatile" %} | |
| 6700 ins_encode( enc_membar_volatile ); | |
| 6701 ins_pipe(long_memory_op); | |
| 6702 %} | |
| 6703 | |
| 6704 instruct unnecessary_membar_volatile() %{ | |
| 6705 match(MemBarVolatile); | |
| 6706 predicate(Matcher::post_store_load_barrier(n)); | |
| 6707 ins_cost(0); | |
| 6708 | |
| 6709 size(0); | |
| 6710 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6711 ins_encode( ); | |
| 6712 ins_pipe(empty); | |
| 6713 %} | |
| 6714 | |
|
4763
1dc233a8c7fe
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4121
diff
changeset
|
6715 instruct membar_storestore() %{ |
|
1dc233a8c7fe
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roland
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4121
diff
changeset
|
6716 match(MemBarStoreStore); |
|
1dc233a8c7fe
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4121
diff
changeset
|
6717 ins_cost(0); |
|
1dc233a8c7fe
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4121
diff
changeset
|
6718 |
|
1dc233a8c7fe
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roland
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4121
diff
changeset
|
6719 size(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
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4121
diff
changeset
|
6720 format %{ "!MEMBAR-storestore (empty encoding)" %} |
|
1dc233a8c7fe
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roland
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4121
diff
changeset
|
6721 ins_encode( ); |
|
1dc233a8c7fe
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roland
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4121
diff
changeset
|
6722 ins_pipe(empty); |
|
1dc233a8c7fe
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roland
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4121
diff
changeset
|
6723 %} |
|
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diff
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|
6724 |
| 0 | 6725 //----------Register Move Instructions----------------------------------------- |
| 6726 instruct roundDouble_nop(regD dst) %{ | |
| 6727 match(Set dst (RoundDouble dst)); | |
| 6728 ins_cost(0); | |
| 6729 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6730 ins_encode( ); | |
| 6731 ins_pipe(empty); | |
| 6732 %} | |
| 6733 | |
| 6734 | |
| 6735 instruct roundFloat_nop(regF dst) %{ | |
| 6736 match(Set dst (RoundFloat dst)); | |
| 6737 ins_cost(0); | |
| 6738 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6739 ins_encode( ); | |
| 6740 ins_pipe(empty); | |
| 6741 %} | |
| 6742 | |
| 6743 | |
| 6744 // Cast Index to Pointer for unsafe natives | |
| 6745 instruct castX2P(iRegX src, iRegP dst) %{ | |
| 6746 match(Set dst (CastX2P src)); | |
| 6747 | |
| 6748 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
| 6749 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6750 ins_pipe(ialu_reg); | |
| 6751 %} | |
| 6752 | |
| 6753 // Cast Pointer to Index for unsafe natives | |
| 6754 instruct castP2X(iRegP src, iRegX dst) %{ | |
| 6755 match(Set dst (CastP2X src)); | |
| 6756 | |
| 6757 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
| 6758 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6759 ins_pipe(ialu_reg); | |
| 6760 %} | |
| 6761 | |
| 6762 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
| 6763 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6764 match(Set stkSlot src); // chain rule | |
| 6765 ins_cost(MEMORY_REF_COST); | |
| 6766 format %{ "STDF $src,$stkSlot\t!stk" %} | |
| 6767 opcode(Assembler::stdf_op3); | |
|
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|
6768 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6769 ins_pipe(fstoreD_stk_reg); |
| 6770 %} | |
| 6771 | |
| 6772 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
| 6773 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6774 match(Set dst stkSlot); // chain rule | |
| 6775 ins_cost(MEMORY_REF_COST); | |
| 6776 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
| 6777 opcode(Assembler::lddf_op3); | |
|
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|
6778 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
| 0 | 6779 ins_pipe(floadD_stk); |
| 6780 %} | |
| 6781 | |
| 6782 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
| 6783 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6784 match(Set stkSlot src); // chain rule | |
| 6785 ins_cost(MEMORY_REF_COST); | |
| 6786 format %{ "STF $src,$stkSlot\t!stk" %} | |
| 6787 opcode(Assembler::stf_op3); | |
|
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|
6788 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6789 ins_pipe(fstoreF_stk_reg); |
| 6790 %} | |
| 6791 | |
| 6792 //----------Conditional Move--------------------------------------------------- | |
| 6793 // Conditional move | |
| 6794 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
| 6795 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6796 ins_cost(150); | |
| 6797 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6798 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6799 ins_pipe(ialu_reg); | |
| 6800 %} | |
| 6801 | |
| 6802 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
| 6803 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6804 ins_cost(140); | |
| 6805 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6806 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6807 ins_pipe(ialu_imm); | |
| 6808 %} | |
| 6809 | |
| 6810 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
| 6811 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6812 ins_cost(150); | |
| 6813 size(4); | |
| 6814 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6815 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6816 ins_pipe(ialu_reg); | |
| 6817 %} | |
| 6818 | |
| 6819 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
| 6820 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6821 ins_cost(140); | |
| 6822 size(4); | |
| 6823 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6824 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6825 ins_pipe(ialu_imm); | |
| 6826 %} | |
| 6827 | |
|
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|
6828 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
| 0 | 6829 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6830 ins_cost(150); | |
| 6831 size(4); | |
| 6832 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6833 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6834 ins_pipe(ialu_reg); | |
| 6835 %} | |
| 6836 | |
|
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|
6837 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
| 0 | 6838 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6839 ins_cost(140); | |
| 6840 size(4); | |
| 6841 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6842 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6843 ins_pipe(ialu_imm); | |
| 6844 %} | |
| 6845 | |
| 6846 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
| 6847 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6848 ins_cost(150); | |
| 6849 size(4); | |
| 6850 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6851 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6852 ins_pipe(ialu_reg); | |
| 6853 %} | |
| 6854 | |
| 6855 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
| 6856 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6857 ins_cost(140); | |
| 6858 size(4); | |
| 6859 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6860 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6861 ins_pipe(ialu_imm); | |
| 6862 %} | |
| 6863 | |
|
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|
6864 // Conditional move for RegN. Only cmov(reg,reg). |
|
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|
6865 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
|
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|
6866 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
|
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|
6867 ins_cost(150); |
|
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|
6868 format %{ "MOV$cmp $pcc,$src,$dst" %} |
|
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|
6869 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
|
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|
6870 ins_pipe(ialu_reg); |
|
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|
6871 %} |
|
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|
6872 |
|
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changeset
|
6873 // This instruction also works with CmpN so we don't need cmovNN_reg. |
|
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|
6874 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
|
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changeset
|
6875 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
|
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|
6876 ins_cost(150); |
|
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changeset
|
6877 size(4); |
|
c436414a719e
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changeset
|
6878 format %{ "MOV$cmp $icc,$src,$dst" %} |
|
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changeset
|
6879 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
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changeset
|
6880 ins_pipe(ialu_reg); |
|
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changeset
|
6881 %} |
|
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163
diff
changeset
|
6882 |
|
1160
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changeset
|
6883 // This instruction also works with CmpN so we don't need cmovNN_reg. |
|
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changeset
|
6884 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ |
|
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changeset
|
6885 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
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diff
changeset
|
6886 ins_cost(150); |
|
f24201449cac
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diff
changeset
|
6887 size(4); |
|
f24201449cac
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changeset
|
6888 format %{ "MOV$cmp $icc,$src,$dst" %} |
|
f24201449cac
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1137
diff
changeset
|
6889 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6890 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6891 %} |
|
f24201449cac
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diff
changeset
|
6892 |
|
164
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163
diff
changeset
|
6893 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
|
c436414a719e
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163
diff
changeset
|
6894 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
|
c436414a719e
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163
diff
changeset
|
6895 ins_cost(150); |
|
c436414a719e
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parents:
163
diff
changeset
|
6896 size(4); |
|
c436414a719e
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parents:
163
diff
changeset
|
6897 format %{ "MOV$cmp $fcc,$src,$dst" %} |
|
c436414a719e
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kvn
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163
diff
changeset
|
6898 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
|
c436414a719e
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163
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changeset
|
6899 ins_pipe(ialu_reg); |
|
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changeset
|
6900 %} |
|
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|
6901 |
| 0 | 6902 // Conditional move |
| 6903 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
| 6904 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6905 ins_cost(150); | |
| 6906 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6907 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6908 ins_pipe(ialu_reg); | |
| 6909 %} | |
| 6910 | |
| 6911 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
| 6912 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6913 ins_cost(140); | |
| 6914 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6915 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6916 ins_pipe(ialu_imm); | |
| 6917 %} | |
| 6918 | |
|
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changeset
|
6919 // This instruction also works with CmpN so we don't need cmovPN_reg. |
| 0 | 6920 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
| 6921 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6922 ins_cost(150); | |
| 6923 | |
| 6924 size(4); | |
| 6925 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6926 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6927 ins_pipe(ialu_reg); | |
| 6928 %} | |
| 6929 | |
|
1160
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changeset
|
6930 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6931 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
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1137
diff
changeset
|
6932 ins_cost(150); |
|
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1137
diff
changeset
|
6933 |
|
f24201449cac
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changeset
|
6934 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
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changeset
|
6935 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
f24201449cac
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1137
diff
changeset
|
6936 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
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changeset
|
6937 ins_pipe(ialu_reg); |
|
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changeset
|
6938 %} |
|
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|
6939 |
| 0 | 6940 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ |
| 6941 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6942 ins_cost(140); | |
| 6943 | |
| 6944 size(4); | |
| 6945 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6946 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6947 ins_pipe(ialu_imm); | |
| 6948 %} | |
| 6949 | |
|
1160
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changeset
|
6950 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ |
|
f24201449cac
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|
6951 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
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diff
changeset
|
6952 ins_cost(140); |
|
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changeset
|
6953 |
|
f24201449cac
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diff
changeset
|
6954 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6955 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
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diff
changeset
|
6956 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
|
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changeset
|
6957 ins_pipe(ialu_imm); |
|
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changeset
|
6958 %} |
|
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|
6959 |
| 0 | 6960 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ |
| 6961 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6962 ins_cost(150); | |
| 6963 size(4); | |
| 6964 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6965 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6966 ins_pipe(ialu_imm); | |
| 6967 %} | |
| 6968 | |
| 6969 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
| 6970 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6971 ins_cost(140); | |
| 6972 size(4); | |
| 6973 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6974 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6975 ins_pipe(ialu_imm); | |
| 6976 %} | |
| 6977 | |
| 6978 // Conditional move | |
| 6979 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
| 6980 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
| 6981 ins_cost(150); | |
| 6982 opcode(0x101); | |
| 6983 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 6984 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6985 ins_pipe(int_conditional_float_move); | |
| 6986 %} | |
| 6987 | |
| 6988 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
| 6989 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
| 6990 ins_cost(150); | |
| 6991 | |
| 6992 size(4); | |
| 6993 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
| 6994 opcode(0x101); | |
| 6995 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6996 ins_pipe(int_conditional_float_move); | |
| 6997 %} | |
| 6998 | |
|
1160
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|
6999 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ |
|
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changeset
|
7000 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7001 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7002 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7003 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7004 format %{ "FMOVS$cmp $icc,$src,$dst" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7005 opcode(0x101); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7006 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7007 ins_pipe(int_conditional_float_move); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7008 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7009 |
| 0 | 7010 // Conditional move, |
| 7011 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
| 7012 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
| 7013 ins_cost(150); | |
| 7014 size(4); | |
| 7015 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
| 7016 opcode(0x1); | |
| 7017 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 7018 ins_pipe(int_conditional_double_move); | |
| 7019 %} | |
| 7020 | |
| 7021 // Conditional move | |
| 7022 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
| 7023 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
| 7024 ins_cost(150); | |
| 7025 size(4); | |
| 7026 opcode(0x102); | |
| 7027 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 7028 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7029 ins_pipe(int_conditional_double_move); | |
| 7030 %} | |
| 7031 | |
| 7032 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
| 7033 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
| 7034 ins_cost(150); | |
| 7035 | |
| 7036 size(4); | |
| 7037 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
| 7038 opcode(0x102); | |
| 7039 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 7040 ins_pipe(int_conditional_double_move); | |
| 7041 %} | |
| 7042 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7043 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7044 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7045 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7046 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7047 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7048 format %{ "FMOVD$cmp $icc,$src,$dst" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7049 opcode(0x102); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7050 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7051 ins_pipe(int_conditional_double_move); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7052 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7053 |
| 0 | 7054 // Conditional move, |
| 7055 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
| 7056 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
| 7057 ins_cost(150); | |
| 7058 size(4); | |
| 7059 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
| 7060 opcode(0x2); | |
| 7061 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 7062 ins_pipe(int_conditional_double_move); | |
| 7063 %} | |
| 7064 | |
| 7065 // Conditional move | |
| 7066 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
| 7067 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 7068 ins_cost(150); | |
| 7069 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 7070 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7071 ins_pipe(ialu_reg); | |
| 7072 %} | |
| 7073 | |
| 7074 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
| 7075 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 7076 ins_cost(140); | |
| 7077 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 7078 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7079 ins_pipe(ialu_imm); | |
| 7080 %} | |
| 7081 | |
| 7082 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
| 7083 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
| 7084 ins_cost(150); | |
| 7085 | |
| 7086 size(4); | |
| 7087 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
| 7088 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 7089 ins_pipe(ialu_reg); | |
| 7090 %} | |
| 7091 | |
| 7092 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7093 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7094 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7095 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7096 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7097 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7098 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7099 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7100 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7101 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7102 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7103 |
| 0 | 7104 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ |
| 7105 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
| 7106 ins_cost(150); | |
| 7107 | |
| 7108 size(4); | |
| 7109 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
| 7110 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 7111 ins_pipe(ialu_reg); | |
| 7112 %} | |
| 7113 | |
| 7114 | |
| 7115 | |
| 7116 //----------OS and Locking Instructions---------------------------------------- | |
| 7117 | |
| 7118 // This name is KNOWN by the ADLC and cannot be changed. | |
| 7119 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 7120 // for this guy. | |
| 7121 instruct tlsLoadP(g2RegP dst) %{ | |
| 7122 match(Set dst (ThreadLocal)); | |
| 7123 | |
| 7124 size(0); | |
| 7125 ins_cost(0); | |
| 7126 format %{ "# TLS is in G2" %} | |
| 7127 ins_encode( /*empty encoding*/ ); | |
| 7128 ins_pipe(ialu_none); | |
| 7129 %} | |
| 7130 | |
| 7131 instruct checkCastPP( iRegP dst ) %{ | |
| 7132 match(Set dst (CheckCastPP dst)); | |
| 7133 | |
| 7134 size(0); | |
| 7135 format %{ "# checkcastPP of $dst" %} | |
| 7136 ins_encode( /*empty encoding*/ ); | |
| 7137 ins_pipe(empty); | |
| 7138 %} | |
| 7139 | |
| 7140 | |
| 7141 instruct castPP( iRegP dst ) %{ | |
| 7142 match(Set dst (CastPP dst)); | |
| 7143 format %{ "# castPP of $dst" %} | |
| 7144 ins_encode( /*empty encoding*/ ); | |
| 7145 ins_pipe(empty); | |
| 7146 %} | |
| 7147 | |
| 7148 instruct castII( iRegI dst ) %{ | |
| 7149 match(Set dst (CastII dst)); | |
| 7150 format %{ "# castII of $dst" %} | |
| 7151 ins_encode( /*empty encoding*/ ); | |
| 7152 ins_cost(0); | |
| 7153 ins_pipe(empty); | |
| 7154 %} | |
| 7155 | |
| 7156 //----------Arithmetic Instructions-------------------------------------------- | |
| 7157 // Addition Instructions | |
| 7158 // Register Addition | |
| 7159 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7160 match(Set dst (AddI src1 src2)); | |
| 7161 | |
| 7162 size(4); | |
| 7163 format %{ "ADD $src1,$src2,$dst" %} | |
| 7164 ins_encode %{ | |
| 7165 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
| 7166 %} | |
| 7167 ins_pipe(ialu_reg_reg); | |
| 7168 %} | |
| 7169 | |
| 7170 // Immediate Addition | |
| 7171 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7172 match(Set dst (AddI src1 src2)); | |
| 7173 | |
| 7174 size(4); | |
| 7175 format %{ "ADD $src1,$src2,$dst" %} | |
| 7176 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7177 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7178 ins_pipe(ialu_reg_imm); | |
| 7179 %} | |
| 7180 | |
| 7181 // Pointer Register Addition | |
| 7182 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
| 7183 match(Set dst (AddP src1 src2)); | |
| 7184 | |
| 7185 size(4); | |
| 7186 format %{ "ADD $src1,$src2,$dst" %} | |
| 7187 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7188 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7189 ins_pipe(ialu_reg_reg); | |
| 7190 %} | |
| 7191 | |
| 7192 // Pointer Immediate Addition | |
| 7193 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
| 7194 match(Set dst (AddP src1 src2)); | |
| 7195 | |
| 7196 size(4); | |
| 7197 format %{ "ADD $src1,$src2,$dst" %} | |
| 7198 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7199 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7200 ins_pipe(ialu_reg_imm); | |
| 7201 %} | |
| 7202 | |
| 7203 // Long Addition | |
| 7204 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7205 match(Set dst (AddL src1 src2)); | |
| 7206 | |
| 7207 size(4); | |
| 7208 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
| 7209 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7210 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7211 ins_pipe(ialu_reg_reg); | |
| 7212 %} | |
| 7213 | |
| 7214 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7215 match(Set dst (AddL src1 con)); | |
| 7216 | |
| 7217 size(4); | |
| 7218 format %{ "ADD $src1,$con,$dst" %} | |
| 7219 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7220 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7221 ins_pipe(ialu_reg_imm); | |
| 7222 %} | |
| 7223 | |
| 7224 //----------Conditional_store-------------------------------------------------- | |
| 7225 // Conditional-store of the updated heap-top. | |
| 7226 // Used during allocation of the shared heap. | |
| 7227 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
| 7228 | |
| 7229 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
| 7230 instruct loadPLocked(iRegP dst, memory mem) %{ | |
| 7231 match(Set dst (LoadPLocked mem)); | |
| 7232 ins_cost(MEMORY_REF_COST); | |
| 7233 | |
| 7234 #ifndef _LP64 | |
| 7235 size(4); | |
| 7236 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 7237 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
| 7238 #else | |
| 7239 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 7240 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
| 7241 #endif | |
| 7242 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 7243 ins_pipe(iload_mem); | |
| 7244 %} | |
| 7245 | |
| 7246 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
| 7247 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7248 effect( KILL newval ); | |
| 7249 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
| 7250 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
| 7251 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
| 7252 ins_pipe( long_memory_op ); | |
| 7253 %} | |
| 7254 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7255 // Conditional-store of an int value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7256 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7257 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7258 effect( KILL newval ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7259 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7260 "CMP $oldval,$newval\t\t! See if we made progress" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7261 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7262 ins_pipe( long_memory_op ); |
| 7263 %} | |
| 7264 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7265 // Conditional-store of a long value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7266 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7267 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7268 effect( KILL newval ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
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415
diff
changeset
|
7269 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
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415
diff
changeset
|
7270 "CMP $oldval,$newval\t\t! See if we made progress" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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415
diff
changeset
|
7271 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7272 ins_pipe( long_memory_op ); |
| 7273 %} | |
| 7274 | |
| 7275 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7276 | |
| 7277 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7278 predicate(VM_Version::supports_cx8()); |
| 0 | 7279 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
| 7280 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7281 format %{ | |
| 7282 "MOV $newval,O7\n\t" | |
| 7283 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7284 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7285 "MOV 1,$res\n\t" | |
| 7286 "MOVne xcc,R_G0,$res" | |
| 7287 %} | |
| 7288 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
| 7289 enc_lflags_ne_to_boolean(res) ); | |
| 7290 ins_pipe( long_memory_op ); | |
| 7291 %} | |
| 7292 | |
| 7293 | |
| 7294 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7295 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 7296 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7297 format %{ | |
| 7298 "MOV $newval,O7\n\t" | |
| 7299 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7300 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7301 "MOV 1,$res\n\t" | |
| 7302 "MOVne icc,R_G0,$res" | |
| 7303 %} | |
| 7304 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
| 7305 enc_iflags_ne_to_boolean(res) ); | |
| 7306 ins_pipe( long_memory_op ); | |
| 7307 %} | |
| 7308 | |
| 7309 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7310 #ifdef _LP64 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7311 predicate(VM_Version::supports_cx8()); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7312 #endif |
| 0 | 7313 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
| 7314 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7315 format %{ | |
| 7316 "MOV $newval,O7\n\t" | |
|
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|
7317 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
| 0 | 7318 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
| 7319 "MOV 1,$res\n\t" | |
| 7320 "MOVne xcc,R_G0,$res" | |
| 7321 %} | |
|
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|
7322 #ifdef _LP64 |
| 0 | 7323 ins_encode( enc_casx(mem_ptr, oldval, newval), |
| 7324 enc_lflags_ne_to_boolean(res) ); | |
| 7325 #else | |
|
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|
7326 ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
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|
7327 enc_iflags_ne_to_boolean(res) ); |
|
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|
7328 #endif |
|
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|
7329 ins_pipe( long_memory_op ); |
|
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|
7330 %} |
|
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|
7331 |
|
181
823298b11afc
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parents:
165
diff
changeset
|
7332 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
|
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|
7333 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
|
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165
diff
changeset
|
7334 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
| 0 | 7335 format %{ |
| 7336 "MOV $newval,O7\n\t" | |
| 7337 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7338 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7339 "MOV 1,$res\n\t" | |
| 7340 "MOVne icc,R_G0,$res" | |
| 7341 %} | |
|
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parents:
165
diff
changeset
|
7342 ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
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|
7343 enc_iflags_ne_to_boolean(res) ); |
| 0 | 7344 ins_pipe( long_memory_op ); |
| 7345 %} | |
| 7346 | |
|
6795
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diff
changeset
|
7347 instruct xchgI( memory mem, iRegI newval) %{ |
|
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|
7348 match(Set newval (GetAndSetI mem newval)); |
|
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|
7349 format %{ "SWAP [$mem],$newval" %} |
|
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|
7350 size(4); |
|
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|
7351 ins_encode %{ |
|
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diff
changeset
|
7352 __ swap($mem$$Address, $newval$$Register); |
|
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|
7353 %} |
|
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changeset
|
7354 ins_pipe( long_memory_op ); |
|
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parents:
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diff
changeset
|
7355 %} |
|
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|
7356 |
|
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changeset
|
7357 #ifndef _LP64 |
|
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diff
changeset
|
7358 instruct xchgP( memory mem, iRegP newval) %{ |
|
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|
7359 match(Set newval (GetAndSetP mem newval)); |
|
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|
7360 format %{ "SWAP [$mem],$newval" %} |
|
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|
7361 size(4); |
|
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|
7362 ins_encode %{ |
|
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changeset
|
7363 __ swap($mem$$Address, $newval$$Register); |
|
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|
7364 %} |
|
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|
7365 ins_pipe( long_memory_op ); |
|
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|
7366 %} |
|
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|
7367 #endif |
|
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|
7368 |
|
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changeset
|
7369 instruct xchgN( memory mem, iRegN newval) %{ |
|
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|
7370 match(Set newval (GetAndSetN mem newval)); |
|
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|
7371 format %{ "SWAP [$mem],$newval" %} |
|
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|
7372 size(4); |
|
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|
7373 ins_encode %{ |
|
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|
7374 __ swap($mem$$Address, $newval$$Register); |
|
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|
7375 %} |
|
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|
7376 ins_pipe( long_memory_op ); |
|
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|
7377 %} |
|
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|
7378 |
| 0 | 7379 //--------------------- |
| 7380 // Subtraction Instructions | |
| 7381 // Register Subtraction | |
| 7382 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7383 match(Set dst (SubI src1 src2)); | |
| 7384 | |
| 7385 size(4); | |
| 7386 format %{ "SUB $src1,$src2,$dst" %} | |
| 7387 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7388 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7389 ins_pipe(ialu_reg_reg); | |
| 7390 %} | |
| 7391 | |
| 7392 // Immediate Subtraction | |
| 7393 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7394 match(Set dst (SubI src1 src2)); | |
| 7395 | |
| 7396 size(4); | |
| 7397 format %{ "SUB $src1,$src2,$dst" %} | |
| 7398 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7399 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7400 ins_pipe(ialu_reg_imm); | |
| 7401 %} | |
| 7402 | |
| 7403 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 7404 match(Set dst (SubI zero src2)); | |
| 7405 | |
| 7406 size(4); | |
| 7407 format %{ "NEG $src2,$dst" %} | |
| 7408 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7409 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7410 ins_pipe(ialu_zero_reg); | |
| 7411 %} | |
| 7412 | |
| 7413 // Long subtraction | |
| 7414 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7415 match(Set dst (SubL src1 src2)); | |
| 7416 | |
| 7417 size(4); | |
| 7418 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7419 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7420 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7421 ins_pipe(ialu_reg_reg); | |
| 7422 %} | |
| 7423 | |
| 7424 // Immediate Subtraction | |
| 7425 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7426 match(Set dst (SubL src1 con)); | |
| 7427 | |
| 7428 size(4); | |
| 7429 format %{ "SUB $src1,$con,$dst\t! long" %} | |
| 7430 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7431 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7432 ins_pipe(ialu_reg_imm); | |
| 7433 %} | |
| 7434 | |
| 7435 // Long negation | |
| 7436 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
| 7437 match(Set dst (SubL zero src2)); | |
| 7438 | |
| 7439 size(4); | |
| 7440 format %{ "NEG $src2,$dst\t! long" %} | |
| 7441 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7442 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7443 ins_pipe(ialu_zero_reg); | |
| 7444 %} | |
| 7445 | |
| 7446 // Multiplication Instructions | |
| 7447 // Integer Multiplication | |
| 7448 // Register Multiplication | |
| 7449 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7450 match(Set dst (MulI src1 src2)); | |
| 7451 | |
| 7452 size(4); | |
| 7453 format %{ "MULX $src1,$src2,$dst" %} | |
| 7454 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7455 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7456 ins_pipe(imul_reg_reg); | |
| 7457 %} | |
| 7458 | |
| 7459 // Immediate Multiplication | |
| 7460 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7461 match(Set dst (MulI src1 src2)); | |
| 7462 | |
| 7463 size(4); | |
| 7464 format %{ "MULX $src1,$src2,$dst" %} | |
| 7465 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7466 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7467 ins_pipe(imul_reg_imm); | |
| 7468 %} | |
| 7469 | |
| 7470 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7471 match(Set dst (MulL src1 src2)); | |
| 7472 ins_cost(DEFAULT_COST * 5); | |
| 7473 size(4); | |
| 7474 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7475 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7476 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7477 ins_pipe(mulL_reg_reg); | |
| 7478 %} | |
| 7479 | |
| 7480 // Immediate Multiplication | |
| 7481 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7482 match(Set dst (MulL src1 src2)); | |
| 7483 ins_cost(DEFAULT_COST * 5); | |
| 7484 size(4); | |
| 7485 format %{ "MULX $src1,$src2,$dst" %} | |
| 7486 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7487 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7488 ins_pipe(mulL_reg_imm); | |
| 7489 %} | |
| 7490 | |
| 7491 // Integer Division | |
| 7492 // Register Division | |
| 7493 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 7494 match(Set dst (DivI src1 src2)); | |
| 7495 ins_cost((2+71)*DEFAULT_COST); | |
| 7496 | |
| 7497 format %{ "SRA $src2,0,$src2\n\t" | |
| 7498 "SRA $src1,0,$src1\n\t" | |
| 7499 "SDIVX $src1,$src2,$dst" %} | |
| 7500 ins_encode( idiv_reg( src1, src2, dst ) ); | |
| 7501 ins_pipe(sdiv_reg_reg); | |
| 7502 %} | |
| 7503 | |
| 7504 // Immediate Division | |
| 7505 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
| 7506 match(Set dst (DivI src1 src2)); | |
| 7507 ins_cost((2+71)*DEFAULT_COST); | |
| 7508 | |
| 7509 format %{ "SRA $src1,0,$src1\n\t" | |
| 7510 "SDIVX $src1,$src2,$dst" %} | |
| 7511 ins_encode( idiv_imm( src1, src2, dst ) ); | |
| 7512 ins_pipe(sdiv_reg_imm); | |
| 7513 %} | |
| 7514 | |
| 7515 //----------Div-By-10-Expansion------------------------------------------------ | |
| 7516 // Extract hi bits of a 32x32->64 bit multiply. | |
| 7517 // Expand rule only, not matched | |
| 7518 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
| 7519 effect( DEF dst, USE src1, USE src2 ); | |
| 7520 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
| 7521 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
| 7522 ins_encode( enc_mul_hi(dst,src1,src2)); | |
| 7523 ins_pipe(sdiv_reg_reg); | |
| 7524 %} | |
| 7525 | |
| 605 | 7526 // Magic constant, reciprocal of 10 |
| 0 | 7527 instruct loadConI_x66666667(iRegIsafe dst) %{ |
| 7528 effect( DEF dst ); | |
| 7529 | |
| 7530 size(8); | |
| 7531 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
| 7532 ins_encode( Set32(0x66666667, dst) ); | |
| 7533 ins_pipe(ialu_hi_lo_reg); | |
| 7534 %} | |
| 7535 | |
| 605 | 7536 // Register Shift Right Arithmetic Long by 32-63 |
| 0 | 7537 instruct sra_31( iRegI dst, iRegI src ) %{ |
| 7538 effect( DEF dst, USE src ); | |
| 7539 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
| 7540 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
| 7541 ins_pipe(ialu_reg_reg); | |
| 7542 %} | |
| 7543 | |
| 7544 // Arithmetic Shift Right by 8-bit immediate | |
| 7545 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
| 7546 effect( DEF dst, USE src ); | |
| 7547 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
| 7548 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7549 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
| 7550 ins_pipe(ialu_reg_imm); | |
| 7551 %} | |
| 7552 | |
| 7553 // Integer DIV with 10 | |
| 7554 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
| 7555 match(Set dst (DivI src div)); | |
| 7556 ins_cost((6+6)*DEFAULT_COST); | |
| 7557 expand %{ | |
| 7558 iRegIsafe tmp1; // Killed temps; | |
| 7559 iRegIsafe tmp2; // Killed temps; | |
| 7560 iRegI tmp3; // Killed temps; | |
| 7561 iRegI tmp4; // Killed temps; | |
| 7562 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
| 7563 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
| 7564 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
| 7565 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
| 7566 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
| 7567 %} | |
| 7568 %} | |
| 7569 | |
| 7570 // Register Long Division | |
| 7571 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7572 match(Set dst (DivL src1 src2)); | |
| 7573 ins_cost(DEFAULT_COST*71); | |
| 7574 size(4); | |
| 7575 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7576 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7577 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7578 ins_pipe(divL_reg_reg); | |
| 7579 %} | |
| 7580 | |
| 7581 // Register Long Division | |
| 7582 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7583 match(Set dst (DivL src1 src2)); | |
| 7584 ins_cost(DEFAULT_COST*71); | |
| 7585 size(4); | |
| 7586 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7587 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7588 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7589 ins_pipe(divL_reg_imm); | |
| 7590 %} | |
| 7591 | |
| 7592 // Integer Remainder | |
| 7593 // Register Remainder | |
| 7594 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7595 match(Set dst (ModI src1 src2)); | |
| 7596 effect( KILL ccr, KILL temp); | |
| 7597 | |
| 7598 format %{ "SREM $src1,$src2,$dst" %} | |
| 7599 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
| 7600 ins_pipe(sdiv_reg_reg); | |
| 7601 %} | |
| 7602 | |
| 7603 // Immediate Remainder | |
| 7604 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7605 match(Set dst (ModI src1 src2)); | |
| 7606 effect( KILL ccr, KILL temp); | |
| 7607 | |
| 7608 format %{ "SREM $src1,$src2,$dst" %} | |
| 7609 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
| 7610 ins_pipe(sdiv_reg_imm); | |
| 7611 %} | |
| 7612 | |
| 7613 // Register Long Remainder | |
| 7614 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7615 effect(DEF dst, USE src1, USE src2); | |
| 7616 size(4); | |
| 7617 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7618 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7619 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7620 ins_pipe(divL_reg_reg); | |
| 7621 %} | |
| 7622 | |
| 7623 // Register Long Division | |
| 7624 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7625 effect(DEF dst, USE src1, USE src2); | |
| 7626 size(4); | |
| 7627 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7628 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7629 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7630 ins_pipe(divL_reg_imm); | |
| 7631 %} | |
| 7632 | |
| 7633 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7634 effect(DEF dst, USE src1, USE src2); | |
| 7635 size(4); | |
| 7636 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7637 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7638 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7639 ins_pipe(mulL_reg_reg); | |
| 7640 %} | |
| 7641 | |
| 7642 // Immediate Multiplication | |
| 7643 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7644 effect(DEF dst, USE src1, USE src2); | |
| 7645 size(4); | |
| 7646 format %{ "MULX $src1,$src2,$dst" %} | |
| 7647 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7648 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7649 ins_pipe(mulL_reg_imm); | |
| 7650 %} | |
| 7651 | |
| 7652 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7653 effect(DEF dst, USE src1, USE src2); | |
| 7654 size(4); | |
| 7655 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7656 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7657 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7658 ins_pipe(ialu_reg_reg); | |
| 7659 %} | |
| 7660 | |
| 7661 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7662 effect(DEF dst, USE src1, USE src2); | |
| 7663 size(4); | |
| 7664 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7665 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7666 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7667 ins_pipe(ialu_reg_reg); | |
| 7668 %} | |
| 7669 | |
| 7670 // Register Long Remainder | |
| 7671 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7672 match(Set dst (ModL src1 src2)); | |
| 7673 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7674 expand %{ | |
| 7675 iRegL tmp1; | |
| 7676 iRegL tmp2; | |
| 7677 divL_reg_reg_1(tmp1, src1, src2); | |
| 7678 mulL_reg_reg_1(tmp2, tmp1, src2); | |
| 7679 subL_reg_reg_1(dst, src1, tmp2); | |
| 7680 %} | |
| 7681 %} | |
| 7682 | |
| 7683 // Register Long Remainder | |
| 7684 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7685 match(Set dst (ModL src1 src2)); | |
| 7686 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7687 expand %{ | |
| 7688 iRegL tmp1; | |
| 7689 iRegL tmp2; | |
| 7690 divL_reg_imm13_1(tmp1, src1, src2); | |
| 7691 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
| 7692 subL_reg_reg_2 (dst, src1, tmp2); | |
| 7693 %} | |
| 7694 %} | |
| 7695 | |
| 7696 // Integer Shift Instructions | |
| 7697 // Register Shift Left | |
| 7698 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7699 match(Set dst (LShiftI src1 src2)); | |
| 7700 | |
| 7701 size(4); | |
| 7702 format %{ "SLL $src1,$src2,$dst" %} | |
| 7703 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7704 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7705 ins_pipe(ialu_reg_reg); | |
| 7706 %} | |
| 7707 | |
| 7708 // Register Shift Left Immediate | |
| 7709 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7710 match(Set dst (LShiftI src1 src2)); | |
| 7711 | |
| 7712 size(4); | |
| 7713 format %{ "SLL $src1,$src2,$dst" %} | |
| 7714 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7715 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7716 ins_pipe(ialu_reg_imm); | |
| 7717 %} | |
| 7718 | |
| 7719 // Register Shift Left | |
| 7720 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7721 match(Set dst (LShiftL src1 src2)); | |
| 7722 | |
| 7723 size(4); | |
| 7724 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7725 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7726 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7727 ins_pipe(ialu_reg_reg); | |
| 7728 %} | |
| 7729 | |
| 7730 // Register Shift Left Immediate | |
| 7731 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7732 match(Set dst (LShiftL src1 src2)); | |
| 7733 | |
| 7734 size(4); | |
| 7735 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7736 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7737 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7738 ins_pipe(ialu_reg_imm); | |
| 7739 %} | |
| 7740 | |
| 7741 // Register Arithmetic Shift Right | |
| 7742 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7743 match(Set dst (RShiftI src1 src2)); | |
| 7744 size(4); | |
| 7745 format %{ "SRA $src1,$src2,$dst" %} | |
| 7746 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7747 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7748 ins_pipe(ialu_reg_reg); | |
| 7749 %} | |
| 7750 | |
| 7751 // Register Arithmetic Shift Right Immediate | |
| 7752 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7753 match(Set dst (RShiftI src1 src2)); | |
| 7754 | |
| 7755 size(4); | |
| 7756 format %{ "SRA $src1,$src2,$dst" %} | |
| 7757 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7758 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7759 ins_pipe(ialu_reg_imm); | |
| 7760 %} | |
| 7761 | |
| 7762 // Register Shift Right Arithmatic Long | |
| 7763 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7764 match(Set dst (RShiftL src1 src2)); | |
| 7765 | |
| 7766 size(4); | |
| 7767 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7768 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7769 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7770 ins_pipe(ialu_reg_reg); | |
| 7771 %} | |
| 7772 | |
| 7773 // Register Shift Left Immediate | |
| 7774 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7775 match(Set dst (RShiftL src1 src2)); | |
| 7776 | |
| 7777 size(4); | |
| 7778 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7779 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7780 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7781 ins_pipe(ialu_reg_imm); | |
| 7782 %} | |
| 7783 | |
| 7784 // Register Shift Right | |
| 7785 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7786 match(Set dst (URShiftI src1 src2)); | |
| 7787 | |
| 7788 size(4); | |
| 7789 format %{ "SRL $src1,$src2,$dst" %} | |
| 7790 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7791 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7792 ins_pipe(ialu_reg_reg); | |
| 7793 %} | |
| 7794 | |
| 7795 // Register Shift Right Immediate | |
| 7796 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7797 match(Set dst (URShiftI src1 src2)); | |
| 7798 | |
| 7799 size(4); | |
| 7800 format %{ "SRL $src1,$src2,$dst" %} | |
| 7801 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7802 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7803 ins_pipe(ialu_reg_imm); | |
| 7804 %} | |
| 7805 | |
| 7806 // Register Shift Right | |
| 7807 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7808 match(Set dst (URShiftL src1 src2)); | |
| 7809 | |
| 7810 size(4); | |
| 7811 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7812 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7813 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7814 ins_pipe(ialu_reg_reg); | |
| 7815 %} | |
| 7816 | |
| 7817 // Register Shift Right Immediate | |
| 7818 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7819 match(Set dst (URShiftL src1 src2)); | |
| 7820 | |
| 7821 size(4); | |
| 7822 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7823 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7824 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7825 ins_pipe(ialu_reg_imm); | |
| 7826 %} | |
| 7827 | |
| 7828 // Register Shift Right Immediate with a CastP2X | |
| 7829 #ifdef _LP64 | |
| 7830 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
| 7831 match(Set dst (URShiftL (CastP2X src1) src2)); | |
| 7832 size(4); | |
| 7833 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
| 7834 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7835 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7836 ins_pipe(ialu_reg_imm); | |
| 7837 %} | |
| 7838 #else | |
| 7839 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
| 7840 match(Set dst (URShiftI (CastP2X src1) src2)); | |
| 7841 size(4); | |
| 7842 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
| 7843 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7844 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7845 ins_pipe(ialu_reg_imm); | |
| 7846 %} | |
| 7847 #endif | |
| 7848 | |
| 7849 | |
| 7850 //----------Floating Point Arithmetic Instructions----------------------------- | |
| 7851 | |
| 7852 // Add float single precision | |
| 7853 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7854 match(Set dst (AddF src1 src2)); | |
| 7855 | |
| 7856 size(4); | |
| 7857 format %{ "FADDS $src1,$src2,$dst" %} | |
| 7858 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
| 7859 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7860 ins_pipe(faddF_reg_reg); | |
| 7861 %} | |
| 7862 | |
| 7863 // Add float double precision | |
| 7864 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7865 match(Set dst (AddD src1 src2)); | |
| 7866 | |
| 7867 size(4); | |
| 7868 format %{ "FADDD $src1,$src2,$dst" %} | |
| 7869 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 7870 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7871 ins_pipe(faddD_reg_reg); | |
| 7872 %} | |
| 7873 | |
| 7874 // Sub float single precision | |
| 7875 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7876 match(Set dst (SubF src1 src2)); | |
| 7877 | |
| 7878 size(4); | |
| 7879 format %{ "FSUBS $src1,$src2,$dst" %} | |
| 7880 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
| 7881 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7882 ins_pipe(faddF_reg_reg); | |
| 7883 %} | |
| 7884 | |
| 7885 // Sub float double precision | |
| 7886 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7887 match(Set dst (SubD src1 src2)); | |
| 7888 | |
| 7889 size(4); | |
| 7890 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 7891 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 7892 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7893 ins_pipe(faddD_reg_reg); | |
| 7894 %} | |
| 7895 | |
| 7896 // Mul float single precision | |
| 7897 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7898 match(Set dst (MulF src1 src2)); | |
| 7899 | |
| 7900 size(4); | |
| 7901 format %{ "FMULS $src1,$src2,$dst" %} | |
| 7902 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
| 7903 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7904 ins_pipe(fmulF_reg_reg); | |
| 7905 %} | |
| 7906 | |
| 7907 // Mul float double precision | |
| 7908 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7909 match(Set dst (MulD src1 src2)); | |
| 7910 | |
| 7911 size(4); | |
| 7912 format %{ "FMULD $src1,$src2,$dst" %} | |
| 7913 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 7914 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7915 ins_pipe(fmulD_reg_reg); | |
| 7916 %} | |
| 7917 | |
| 7918 // Div float single precision | |
| 7919 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7920 match(Set dst (DivF src1 src2)); | |
| 7921 | |
| 7922 size(4); | |
| 7923 format %{ "FDIVS $src1,$src2,$dst" %} | |
| 7924 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
| 7925 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7926 ins_pipe(fdivF_reg_reg); | |
| 7927 %} | |
| 7928 | |
| 7929 // Div float double precision | |
| 7930 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7931 match(Set dst (DivD src1 src2)); | |
| 7932 | |
| 7933 size(4); | |
| 7934 format %{ "FDIVD $src1,$src2,$dst" %} | |
| 7935 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
| 7936 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7937 ins_pipe(fdivD_reg_reg); | |
| 7938 %} | |
| 7939 | |
| 7940 // Absolute float double precision | |
| 7941 instruct absD_reg(regD dst, regD src) %{ | |
| 7942 match(Set dst (AbsD src)); | |
| 7943 | |
| 7944 format %{ "FABSd $src,$dst" %} | |
| 7945 ins_encode(fabsd(dst, src)); | |
| 7946 ins_pipe(faddD_reg); | |
| 7947 %} | |
| 7948 | |
| 7949 // Absolute float single precision | |
| 7950 instruct absF_reg(regF dst, regF src) %{ | |
| 7951 match(Set dst (AbsF src)); | |
| 7952 | |
| 7953 format %{ "FABSs $src,$dst" %} | |
| 7954 ins_encode(fabss(dst, src)); | |
| 7955 ins_pipe(faddF_reg); | |
| 7956 %} | |
| 7957 | |
| 7958 instruct negF_reg(regF dst, regF src) %{ | |
| 7959 match(Set dst (NegF src)); | |
| 7960 | |
| 7961 size(4); | |
| 7962 format %{ "FNEGs $src,$dst" %} | |
| 7963 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
| 7964 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
| 7965 ins_pipe(faddF_reg); | |
| 7966 %} | |
| 7967 | |
| 7968 instruct negD_reg(regD dst, regD src) %{ | |
| 7969 match(Set dst (NegD src)); | |
| 7970 | |
| 7971 format %{ "FNEGd $src,$dst" %} | |
| 7972 ins_encode(fnegd(dst, src)); | |
| 7973 ins_pipe(faddD_reg); | |
| 7974 %} | |
| 7975 | |
| 7976 // Sqrt float double precision | |
| 7977 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
| 7978 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 7979 | |
| 7980 size(4); | |
| 7981 format %{ "FSQRTS $src,$dst" %} | |
| 7982 ins_encode(fsqrts(dst, src)); | |
| 7983 ins_pipe(fdivF_reg_reg); | |
| 7984 %} | |
| 7985 | |
| 7986 // Sqrt float double precision | |
| 7987 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
| 7988 match(Set dst (SqrtD src)); | |
| 7989 | |
| 7990 size(4); | |
| 7991 format %{ "FSQRTD $src,$dst" %} | |
| 7992 ins_encode(fsqrtd(dst, src)); | |
| 7993 ins_pipe(fdivD_reg_reg); | |
| 7994 %} | |
| 7995 | |
| 7996 //----------Logical Instructions----------------------------------------------- | |
| 7997 // And Instructions | |
| 7998 // Register And | |
| 7999 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 8000 match(Set dst (AndI src1 src2)); | |
| 8001 | |
| 8002 size(4); | |
| 8003 format %{ "AND $src1,$src2,$dst" %} | |
| 8004 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 8005 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8006 ins_pipe(ialu_reg_reg); | |
| 8007 %} | |
| 8008 | |
| 8009 // Immediate And | |
| 8010 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 8011 match(Set dst (AndI src1 src2)); | |
| 8012 | |
| 8013 size(4); | |
| 8014 format %{ "AND $src1,$src2,$dst" %} | |
| 8015 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 8016 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 8017 ins_pipe(ialu_reg_imm); | |
| 8018 %} | |
| 8019 | |
| 8020 // Register And Long | |
| 8021 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 8022 match(Set dst (AndL src1 src2)); | |
| 8023 | |
| 8024 ins_cost(DEFAULT_COST); | |
| 8025 size(4); | |
| 8026 format %{ "AND $src1,$src2,$dst\t! long" %} | |
| 8027 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 8028 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8029 ins_pipe(ialu_reg_reg); | |
| 8030 %} | |
| 8031 | |
| 8032 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 8033 match(Set dst (AndL src1 con)); | |
| 8034 | |
| 8035 ins_cost(DEFAULT_COST); | |
| 8036 size(4); | |
| 8037 format %{ "AND $src1,$con,$dst\t! long" %} | |
| 8038 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 8039 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 8040 ins_pipe(ialu_reg_imm); | |
| 8041 %} | |
| 8042 | |
| 8043 // Or Instructions | |
| 8044 // Register Or | |
| 8045 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 8046 match(Set dst (OrI src1 src2)); | |
| 8047 | |
| 8048 size(4); | |
| 8049 format %{ "OR $src1,$src2,$dst" %} | |
| 8050 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8051 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8052 ins_pipe(ialu_reg_reg); | |
| 8053 %} | |
| 8054 | |
| 8055 // Immediate Or | |
| 8056 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 8057 match(Set dst (OrI src1 src2)); | |
| 8058 | |
| 8059 size(4); | |
| 8060 format %{ "OR $src1,$src2,$dst" %} | |
| 8061 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8062 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 8063 ins_pipe(ialu_reg_imm); | |
| 8064 %} | |
| 8065 | |
| 8066 // Register Or Long | |
| 8067 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 8068 match(Set dst (OrL src1 src2)); | |
| 8069 | |
| 8070 ins_cost(DEFAULT_COST); | |
| 8071 size(4); | |
| 8072 format %{ "OR $src1,$src2,$dst\t! long" %} | |
| 8073 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8074 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8075 ins_pipe(ialu_reg_reg); | |
| 8076 %} | |
| 8077 | |
| 8078 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 8079 match(Set dst (OrL src1 con)); | |
| 8080 ins_cost(DEFAULT_COST*2); | |
| 8081 | |
| 8082 ins_cost(DEFAULT_COST); | |
| 8083 size(4); | |
| 8084 format %{ "OR $src1,$con,$dst\t! long" %} | |
| 8085 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8086 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 8087 ins_pipe(ialu_reg_imm); | |
| 8088 %} | |
| 8089 | |
|
420
a1980da045cc
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|
8090 #ifndef _LP64 |
|
a1980da045cc
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|
8091 |
|
a1980da045cc
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diff
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|
8092 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
|
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|
8093 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
|
a1980da045cc
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diff
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|
8094 match(Set dst (OrI src1 (CastP2X src2))); |
|
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diff
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|
8095 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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diff
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|
8096 size(4); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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diff
changeset
|
8097 format %{ "OR $src1,$src2,$dst" %} |
|
a1980da045cc
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|
8098 opcode(Assembler::or_op3, Assembler::arith_op); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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diff
changeset
|
8099 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
a1980da045cc
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diff
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|
8100 ins_pipe(ialu_reg_reg); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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diff
changeset
|
8101 %} |
|
a1980da045cc
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changeset
|
8102 |
|
a1980da045cc
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diff
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|
8103 #else |
|
a1980da045cc
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diff
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|
8104 |
|
a1980da045cc
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|
8105 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
|
a1980da045cc
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|
8106 match(Set dst (OrL src1 (CastP2X src2))); |
|
a1980da045cc
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|
8107 |
|
a1980da045cc
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|
8108 ins_cost(DEFAULT_COST); |
|
a1980da045cc
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diff
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|
8109 size(4); |
|
a1980da045cc
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|
8110 format %{ "OR $src1,$src2,$dst\t! long" %} |
|
a1980da045cc
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diff
changeset
|
8111 opcode(Assembler::or_op3, Assembler::arith_op); |
|
a1980da045cc
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|
8112 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
a1980da045cc
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|
8113 ins_pipe(ialu_reg_reg); |
|
a1980da045cc
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|
8114 %} |
|
a1980da045cc
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|
8115 |
|
a1980da045cc
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|
8116 #endif |
|
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|
8117 |
| 0 | 8118 // Xor Instructions |
| 8119 // Register Xor | |
| 8120 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 8121 match(Set dst (XorI src1 src2)); | |
| 8122 | |
| 8123 size(4); | |
| 8124 format %{ "XOR $src1,$src2,$dst" %} | |
| 8125 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8126 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8127 ins_pipe(ialu_reg_reg); | |
| 8128 %} | |
| 8129 | |
| 8130 // Immediate Xor | |
| 8131 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 8132 match(Set dst (XorI src1 src2)); | |
| 8133 | |
| 8134 size(4); | |
| 8135 format %{ "XOR $src1,$src2,$dst" %} | |
| 8136 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8137 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 8138 ins_pipe(ialu_reg_imm); | |
| 8139 %} | |
| 8140 | |
| 8141 // Register Xor Long | |
| 8142 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 8143 match(Set dst (XorL src1 src2)); | |
| 8144 | |
| 8145 ins_cost(DEFAULT_COST); | |
| 8146 size(4); | |
| 8147 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
| 8148 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8149 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8150 ins_pipe(ialu_reg_reg); | |
| 8151 %} | |
| 8152 | |
| 8153 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 8154 match(Set dst (XorL src1 con)); | |
| 8155 | |
| 8156 ins_cost(DEFAULT_COST); | |
| 8157 size(4); | |
| 8158 format %{ "XOR $src1,$con,$dst\t! long" %} | |
| 8159 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8160 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 8161 ins_pipe(ialu_reg_imm); | |
| 8162 %} | |
| 8163 | |
| 8164 //----------Convert to Boolean------------------------------------------------- | |
| 8165 // Nice hack for 32-bit tests but doesn't work for | |
| 8166 // 64-bit pointers. | |
| 8167 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
| 8168 match(Set dst (Conv2B src)); | |
| 8169 effect( KILL ccr ); | |
| 8170 ins_cost(DEFAULT_COST*2); | |
| 8171 format %{ "CMP R_G0,$src\n\t" | |
| 8172 "ADDX R_G0,0,$dst" %} | |
| 8173 ins_encode( enc_to_bool( src, dst ) ); | |
| 8174 ins_pipe(ialu_reg_ialu); | |
| 8175 %} | |
| 8176 | |
| 8177 #ifndef _LP64 | |
| 8178 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
| 8179 match(Set dst (Conv2B src)); | |
| 8180 effect( KILL ccr ); | |
| 8181 ins_cost(DEFAULT_COST*2); | |
| 8182 format %{ "CMP R_G0,$src\n\t" | |
| 8183 "ADDX R_G0,0,$dst" %} | |
| 8184 ins_encode( enc_to_bool( src, dst ) ); | |
| 8185 ins_pipe(ialu_reg_ialu); | |
| 8186 %} | |
| 8187 #else | |
| 8188 instruct convP2B( iRegI dst, iRegP src ) %{ | |
| 8189 match(Set dst (Conv2B src)); | |
| 8190 ins_cost(DEFAULT_COST*2); | |
| 8191 format %{ "MOV $src,$dst\n\t" | |
| 8192 "MOVRNZ $src,1,$dst" %} | |
| 8193 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
| 8194 ins_pipe(ialu_clr_and_mover); | |
| 8195 %} | |
| 8196 #endif | |
| 8197 | |
|
2254
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|
8198 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ |
|
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diff
changeset
|
8199 match(Set dst (CmpLTMask src zero)); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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diff
changeset
|
8200 effect(KILL ccr); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8201 size(4); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8202 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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diff
changeset
|
8203 ins_encode %{ |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8204 __ sra($src$$Register, 31, $dst$$Register); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8205 %} |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
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2121
diff
changeset
|
8206 ins_pipe(ialu_reg_imm); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
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2121
diff
changeset
|
8207 %} |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
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2121
diff
changeset
|
8208 |
| 0 | 8209 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ |
| 8210 match(Set dst (CmpLTMask p q)); | |
| 8211 effect( KILL ccr ); | |
| 8212 ins_cost(DEFAULT_COST*4); | |
| 8213 format %{ "CMP $p,$q\n\t" | |
| 8214 "MOV #0,$dst\n\t" | |
| 8215 "BLT,a .+8\n\t" | |
| 8216 "MOV #-1,$dst" %} | |
| 8217 ins_encode( enc_ltmask(p,q,dst) ); | |
| 8218 ins_pipe(ialu_reg_reg_ialu); | |
| 8219 %} | |
| 8220 | |
| 8221 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
| 8222 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 8223 effect(KILL ccr, TEMP tmp); | |
| 8224 ins_cost(DEFAULT_COST*3); | |
| 8225 | |
| 8226 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
| 8227 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
|
2254
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7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
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2121
diff
changeset
|
8228 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} |
| 9154 | 8229 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp)); |
| 8230 ins_pipe(cadd_cmpltmask); | |
| 8231 %} | |
| 8232 | |
| 8233 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{ | |
| 8234 match(Set p (AndI (CmpLTMask p q) y)); | |
| 8235 effect(KILL ccr); | |
| 8236 ins_cost(DEFAULT_COST*3); | |
| 8237 | |
| 8238 format %{ "CMP $p,$q\n\t" | |
| 8239 "MOV $y,$p\n\t" | |
| 8240 "MOVge G0,$p" %} | |
| 8241 ins_encode %{ | |
| 8242 __ cmp($p$$Register, $q$$Register); | |
| 8243 __ mov($y$$Register, $p$$Register); | |
| 8244 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register); | |
| 8245 %} | |
| 8246 ins_pipe(ialu_reg_reg_ialu); | |
| 8247 %} | |
| 3804 | 8248 |
| 8249 //----------------------------------------------------------------- | |
| 8250 // Direct raw moves between float and general registers using VIS3. | |
| 8251 | |
| 8252 // ins_pipe(faddF_reg); | |
| 8253 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ | |
| 8254 predicate(UseVIS >= 3); | |
| 8255 match(Set dst (MoveF2I src)); | |
| 8256 | |
| 8257 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} | |
| 8258 ins_encode %{ | |
| 8259 __ movstouw($src$$FloatRegister, $dst$$Register); | |
| 8260 %} | |
| 8261 ins_pipe(ialu_reg_reg); | |
| 8262 %} | |
| 8263 | |
| 8264 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ | |
| 8265 predicate(UseVIS >= 3); | |
| 8266 match(Set dst (MoveI2F src)); | |
| 8267 | |
| 8268 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} | |
| 8269 ins_encode %{ | |
| 8270 __ movwtos($src$$Register, $dst$$FloatRegister); | |
| 8271 %} | |
| 0 | 8272 ins_pipe(ialu_reg_reg); |
| 8273 %} | |
| 8274 | |
| 3804 | 8275 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ |
| 8276 predicate(UseVIS >= 3); | |
| 8277 match(Set dst (MoveD2L src)); | |
| 8278 | |
| 8279 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} | |
| 8280 ins_encode %{ | |
| 8281 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); | |
| 8282 %} | |
| 0 | 8283 ins_pipe(ialu_reg_reg); |
| 8284 %} | |
| 8285 | |
| 3804 | 8286 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ |
| 8287 predicate(UseVIS >= 3); | |
| 8288 match(Set dst (MoveL2D src)); | |
| 8289 | |
| 8290 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} | |
| 8291 ins_encode %{ | |
| 8292 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); | |
| 8293 %} | |
| 0 | 8294 ins_pipe(ialu_reg_reg); |
| 8295 %} | |
| 8296 | |
| 3804 | 8297 |
| 8298 // Raw moves between float and general registers using stack. | |
| 8299 | |
| 0 | 8300 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ |
| 8301 match(Set dst (MoveF2I src)); | |
| 8302 effect(DEF dst, USE src); | |
| 8303 ins_cost(MEMORY_REF_COST); | |
| 8304 | |
| 8305 size(4); | |
| 8306 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
| 8307 opcode(Assembler::lduw_op3); | |
|
415
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changeset
|
8308 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8309 ins_pipe(iload_mem); |
| 8310 %} | |
| 8311 | |
| 8312 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 8313 match(Set dst (MoveI2F src)); | |
| 8314 effect(DEF dst, USE src); | |
| 8315 ins_cost(MEMORY_REF_COST); | |
| 8316 | |
| 8317 size(4); | |
| 8318 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
| 8319 opcode(Assembler::ldf_op3); | |
|
415
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235
diff
changeset
|
8320 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8321 ins_pipe(floadF_stk); |
| 8322 %} | |
| 8323 | |
| 8324 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
| 8325 match(Set dst (MoveD2L src)); | |
| 8326 effect(DEF dst, USE src); | |
| 8327 ins_cost(MEMORY_REF_COST); | |
| 8328 | |
| 8329 size(4); | |
| 8330 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
| 8331 opcode(Assembler::ldx_op3); | |
|
415
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235
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changeset
|
8332 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8333 ins_pipe(iload_mem); |
| 8334 %} | |
| 8335 | |
| 8336 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 8337 match(Set dst (MoveL2D src)); | |
| 8338 effect(DEF dst, USE src); | |
| 8339 ins_cost(MEMORY_REF_COST); | |
| 8340 | |
| 8341 size(4); | |
| 8342 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
| 8343 opcode(Assembler::lddf_op3); | |
|
415
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235
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changeset
|
8344 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8345 ins_pipe(floadD_stk); |
| 8346 %} | |
| 8347 | |
| 8348 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 8349 match(Set dst (MoveF2I src)); | |
| 8350 effect(DEF dst, USE src); | |
| 8351 ins_cost(MEMORY_REF_COST); | |
| 8352 | |
| 8353 size(4); | |
| 3804 | 8354 format %{ "STF $src,$dst\t! MoveF2I" %} |
| 0 | 8355 opcode(Assembler::stf_op3); |
|
415
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235
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changeset
|
8356 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8357 ins_pipe(fstoreF_stk_reg); |
| 8358 %} | |
| 8359 | |
| 8360 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
| 8361 match(Set dst (MoveI2F src)); | |
| 8362 effect(DEF dst, USE src); | |
| 8363 ins_cost(MEMORY_REF_COST); | |
| 8364 | |
| 8365 size(4); | |
| 3804 | 8366 format %{ "STW $src,$dst\t! MoveI2F" %} |
| 0 | 8367 opcode(Assembler::stw_op3); |
|
415
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235
diff
changeset
|
8368 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8369 ins_pipe(istore_mem_reg); |
| 8370 %} | |
| 8371 | |
| 8372 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 8373 match(Set dst (MoveD2L src)); | |
| 8374 effect(DEF dst, USE src); | |
| 8375 ins_cost(MEMORY_REF_COST); | |
| 8376 | |
| 8377 size(4); | |
| 3804 | 8378 format %{ "STDF $src,$dst\t! MoveD2L" %} |
| 0 | 8379 opcode(Assembler::stdf_op3); |
|
415
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never
parents:
235
diff
changeset
|
8380 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8381 ins_pipe(fstoreD_stk_reg); |
| 8382 %} | |
| 8383 | |
| 8384 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
| 8385 match(Set dst (MoveL2D src)); | |
| 8386 effect(DEF dst, USE src); | |
| 8387 ins_cost(MEMORY_REF_COST); | |
| 8388 | |
| 8389 size(4); | |
| 3804 | 8390 format %{ "STX $src,$dst\t! MoveL2D" %} |
| 0 | 8391 opcode(Assembler::stx_op3); |
|
415
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never
parents:
235
diff
changeset
|
8392 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8393 ins_pipe(istore_mem_reg); |
| 8394 %} | |
| 8395 | |
| 8396 | |
| 3804 | 8397 //----------Arithmetic Conversion Instructions--------------------------------- |
| 8398 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 8399 | |
| 8400 instruct convD2F_reg(regF dst, regD src) %{ | |
| 8401 match(Set dst (ConvD2F src)); | |
| 8402 size(4); | |
| 8403 format %{ "FDTOS $src,$dst" %} | |
| 8404 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
| 8405 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
| 8406 ins_pipe(fcvtD2F); | |
| 8407 %} | |
| 8408 | |
| 8409 | |
| 8410 // Convert a double to an int in a float register. | |
| 8411 // If the double is a NAN, stuff a zero in instead. | |
| 8412 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
| 8413 effect(DEF dst, USE src, KILL fcc0); | |
| 8414 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8415 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8416 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8417 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8418 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8419 "skip:" %} | |
| 8420 ins_encode(form_d2i_helper(src,dst)); | |
| 8421 ins_pipe(fcvtD2I); | |
| 8422 %} | |
| 8423 | |
| 8424 instruct convD2I_stk(stackSlotI dst, regD src) %{ | |
| 8425 match(Set dst (ConvD2I src)); | |
| 8426 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8427 expand %{ | |
| 8428 regF tmp; | |
| 8429 convD2I_helper(tmp, src); | |
| 8430 regF_to_stkI(dst, tmp); | |
| 8431 %} | |
| 8432 %} | |
| 8433 | |
| 8434 instruct convD2I_reg(iRegI dst, regD src) %{ | |
| 8435 predicate(UseVIS >= 3); | |
| 8436 match(Set dst (ConvD2I src)); | |
| 8437 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8438 expand %{ | |
| 8439 regF tmp; | |
| 8440 convD2I_helper(tmp, src); | |
| 8441 MoveF2I_reg_reg(dst, tmp); | |
| 8442 %} | |
| 8443 %} | |
| 8444 | |
| 8445 | |
| 8446 // Convert a double to a long in a double register. | |
| 8447 // If the double is a NAN, stuff a zero in instead. | |
| 8448 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
| 8449 effect(DEF dst, USE src, KILL fcc0); | |
| 8450 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8451 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8452 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8453 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8454 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8455 "skip:" %} | |
| 8456 ins_encode(form_d2l_helper(src,dst)); | |
| 8457 ins_pipe(fcvtD2L); | |
| 8458 %} | |
| 8459 | |
| 8460 instruct convD2L_stk(stackSlotL dst, regD src) %{ | |
| 8461 match(Set dst (ConvD2L src)); | |
| 8462 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8463 expand %{ | |
| 8464 regD tmp; | |
| 8465 convD2L_helper(tmp, src); | |
| 8466 regD_to_stkL(dst, tmp); | |
| 8467 %} | |
| 8468 %} | |
| 8469 | |
| 8470 instruct convD2L_reg(iRegL dst, regD src) %{ | |
| 8471 predicate(UseVIS >= 3); | |
| 8472 match(Set dst (ConvD2L src)); | |
| 8473 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8474 expand %{ | |
| 8475 regD tmp; | |
| 8476 convD2L_helper(tmp, src); | |
| 8477 MoveD2L_reg_reg(dst, tmp); | |
| 8478 %} | |
| 8479 %} | |
| 8480 | |
| 8481 | |
| 8482 instruct convF2D_reg(regD dst, regF src) %{ | |
| 8483 match(Set dst (ConvF2D src)); | |
| 8484 format %{ "FSTOD $src,$dst" %} | |
| 8485 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
| 8486 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
| 8487 ins_pipe(fcvtF2D); | |
| 8488 %} | |
| 8489 | |
| 8490 | |
| 8491 // Convert a float to an int in a float register. | |
| 8492 // If the float is a NAN, stuff a zero in instead. | |
| 8493 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
| 8494 effect(DEF dst, USE src, KILL fcc0); | |
| 8495 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8496 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8497 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8498 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8499 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8500 "skip:" %} | |
| 8501 ins_encode(form_f2i_helper(src,dst)); | |
| 8502 ins_pipe(fcvtF2I); | |
| 8503 %} | |
| 8504 | |
| 8505 instruct convF2I_stk(stackSlotI dst, regF src) %{ | |
| 8506 match(Set dst (ConvF2I src)); | |
| 8507 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8508 expand %{ | |
| 8509 regF tmp; | |
| 8510 convF2I_helper(tmp, src); | |
| 8511 regF_to_stkI(dst, tmp); | |
| 8512 %} | |
| 8513 %} | |
| 8514 | |
| 8515 instruct convF2I_reg(iRegI dst, regF src) %{ | |
| 8516 predicate(UseVIS >= 3); | |
| 8517 match(Set dst (ConvF2I src)); | |
| 8518 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8519 expand %{ | |
| 8520 regF tmp; | |
| 8521 convF2I_helper(tmp, src); | |
| 8522 MoveF2I_reg_reg(dst, tmp); | |
| 8523 %} | |
| 8524 %} | |
| 8525 | |
| 8526 | |
| 8527 // Convert a float to a long in a float register. | |
| 8528 // If the float is a NAN, stuff a zero in instead. | |
| 8529 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
| 8530 effect(DEF dst, USE src, KILL fcc0); | |
| 8531 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8532 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8533 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8534 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8535 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8536 "skip:" %} | |
| 8537 ins_encode(form_f2l_helper(src,dst)); | |
| 8538 ins_pipe(fcvtF2L); | |
| 8539 %} | |
| 8540 | |
| 8541 instruct convF2L_stk(stackSlotL dst, regF src) %{ | |
| 8542 match(Set dst (ConvF2L src)); | |
| 8543 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8544 expand %{ | |
| 8545 regD tmp; | |
| 8546 convF2L_helper(tmp, src); | |
| 8547 regD_to_stkL(dst, tmp); | |
| 8548 %} | |
| 8549 %} | |
| 8550 | |
| 8551 instruct convF2L_reg(iRegL dst, regF src) %{ | |
| 8552 predicate(UseVIS >= 3); | |
| 8553 match(Set dst (ConvF2L src)); | |
| 8554 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8555 expand %{ | |
| 8556 regD tmp; | |
| 8557 convF2L_helper(tmp, src); | |
| 8558 MoveD2L_reg_reg(dst, tmp); | |
| 8559 %} | |
| 8560 %} | |
| 8561 | |
| 8562 | |
| 8563 instruct convI2D_helper(regD dst, regF tmp) %{ | |
| 8564 effect(USE tmp, DEF dst); | |
| 8565 format %{ "FITOD $tmp,$dst" %} | |
| 8566 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8567 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
| 8568 ins_pipe(fcvtI2D); | |
| 8569 %} | |
| 8570 | |
| 8571 instruct convI2D_stk(stackSlotI src, regD dst) %{ | |
| 8572 match(Set dst (ConvI2D src)); | |
| 8573 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8574 expand %{ | |
| 8575 regF tmp; | |
| 8576 stkI_to_regF(tmp, src); | |
| 8577 convI2D_helper(dst, tmp); | |
| 8578 %} | |
| 8579 %} | |
| 8580 | |
| 8581 instruct convI2D_reg(regD_low dst, iRegI src) %{ | |
| 8582 predicate(UseVIS >= 3); | |
| 8583 match(Set dst (ConvI2D src)); | |
| 8584 expand %{ | |
| 8585 regF tmp; | |
| 8586 MoveI2F_reg_reg(tmp, src); | |
| 8587 convI2D_helper(dst, tmp); | |
| 8588 %} | |
| 8589 %} | |
| 8590 | |
| 8591 instruct convI2D_mem(regD_low dst, memory mem) %{ | |
| 8592 match(Set dst (ConvI2D (LoadI mem))); | |
| 8593 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8594 size(8); | |
| 8595 format %{ "LDF $mem,$dst\n\t" | |
| 8596 "FITOD $dst,$dst" %} | |
| 8597 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
| 8598 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
| 8599 ins_pipe(floadF_mem); | |
| 8600 %} | |
| 8601 | |
| 8602 | |
| 8603 instruct convI2F_helper(regF dst, regF tmp) %{ | |
| 8604 effect(DEF dst, USE tmp); | |
| 8605 format %{ "FITOS $tmp,$dst" %} | |
| 8606 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
| 8607 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
| 8608 ins_pipe(fcvtI2F); | |
| 8609 %} | |
| 8610 | |
| 8611 instruct convI2F_stk(regF dst, stackSlotI src) %{ | |
| 8612 match(Set dst (ConvI2F src)); | |
| 8613 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8614 expand %{ | |
| 8615 regF tmp; | |
| 8616 stkI_to_regF(tmp,src); | |
| 8617 convI2F_helper(dst, tmp); | |
| 8618 %} | |
| 8619 %} | |
| 8620 | |
| 8621 instruct convI2F_reg(regF dst, iRegI src) %{ | |
| 8622 predicate(UseVIS >= 3); | |
| 8623 match(Set dst (ConvI2F src)); | |
| 8624 ins_cost(DEFAULT_COST); | |
| 8625 expand %{ | |
| 8626 regF tmp; | |
| 8627 MoveI2F_reg_reg(tmp, src); | |
| 8628 convI2F_helper(dst, tmp); | |
| 8629 %} | |
| 8630 %} | |
| 8631 | |
| 8632 instruct convI2F_mem( regF dst, memory mem ) %{ | |
| 8633 match(Set dst (ConvI2F (LoadI mem))); | |
| 8634 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8635 size(8); | |
| 8636 format %{ "LDF $mem,$dst\n\t" | |
| 8637 "FITOS $dst,$dst" %} | |
| 8638 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
| 8639 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
| 8640 ins_pipe(floadF_mem); | |
| 8641 %} | |
| 8642 | |
| 8643 | |
| 8644 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
| 8645 match(Set dst (ConvI2L src)); | |
| 8646 size(4); | |
| 8647 format %{ "SRA $src,0,$dst\t! int->long" %} | |
| 8648 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 8649 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8650 ins_pipe(ialu_reg_reg); | |
| 8651 %} | |
| 8652 | |
| 8653 // Zero-extend convert int to long | |
| 8654 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
| 8655 match(Set dst (AndL (ConvI2L src) mask) ); | |
| 8656 size(4); | |
| 8657 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
| 8658 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8659 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8660 ins_pipe(ialu_reg_reg); | |
| 8661 %} | |
| 8662 | |
| 8663 // Zero-extend long | |
| 8664 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
| 8665 match(Set dst (AndL src mask) ); | |
| 8666 size(4); | |
| 8667 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
| 8668 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8669 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8670 ins_pipe(ialu_reg_reg); | |
| 8671 %} | |
| 8672 | |
| 8673 | |
| 0 | 8674 //----------- |
| 8675 // Long to Double conversion using V8 opcodes. | |
| 8676 // Still useful because cheetah traps and becomes | |
| 8677 // amazingly slow for some common numbers. | |
| 8678 | |
| 8679 // Magic constant, 0x43300000 | |
| 8680 instruct loadConI_x43300000(iRegI dst) %{ | |
| 8681 effect(DEF dst); | |
| 8682 size(4); | |
| 8683 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
| 8684 ins_encode(SetHi22(0x43300000, dst)); | |
| 8685 ins_pipe(ialu_none); | |
| 8686 %} | |
| 8687 | |
| 8688 // Magic constant, 0x41f00000 | |
| 8689 instruct loadConI_x41f00000(iRegI dst) %{ | |
| 8690 effect(DEF dst); | |
| 8691 size(4); | |
| 8692 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
| 8693 ins_encode(SetHi22(0x41f00000, dst)); | |
| 8694 ins_pipe(ialu_none); | |
| 8695 %} | |
| 8696 | |
| 8697 // Construct a double from two float halves | |
| 8698 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
| 8699 effect(DEF dst, USE src1, USE src2); | |
| 8700 size(8); | |
| 8701 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
| 8702 "FMOVS $src2.lo,$dst.lo" %} | |
| 8703 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
| 8704 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
| 8705 ins_pipe(faddD_reg_reg); | |
| 8706 %} | |
| 8707 | |
| 8708 // Convert integer in high half of a double register (in the lower half of | |
| 8709 // the double register file) to double | |
| 8710 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
| 8711 effect(DEF dst, USE src); | |
| 8712 size(4); | |
| 8713 format %{ "FITOD $src,$dst" %} | |
| 8714 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8715 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
| 8716 ins_pipe(fcvtLHi2D); | |
| 8717 %} | |
| 8718 | |
| 8719 // Add float double precision | |
| 8720 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8721 effect(DEF dst, USE src1, USE src2); | |
| 8722 size(4); | |
| 8723 format %{ "FADDD $src1,$src2,$dst" %} | |
| 8724 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 8725 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8726 ins_pipe(faddD_reg_reg); | |
| 8727 %} | |
| 8728 | |
| 8729 // Sub float double precision | |
| 8730 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8731 effect(DEF dst, USE src1, USE src2); | |
| 8732 size(4); | |
| 8733 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 8734 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 8735 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8736 ins_pipe(faddD_reg_reg); | |
| 8737 %} | |
| 8738 | |
| 8739 // Mul float double precision | |
| 8740 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8741 effect(DEF dst, USE src1, USE src2); | |
| 8742 size(4); | |
| 8743 format %{ "FMULD $src1,$src2,$dst" %} | |
| 8744 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 8745 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8746 ins_pipe(fmulD_reg_reg); | |
| 8747 %} | |
| 8748 | |
| 8749 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
| 8750 match(Set dst (ConvL2D src)); | |
| 8751 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
| 8752 | |
| 8753 expand %{ | |
| 8754 regD_low tmpsrc; | |
| 8755 iRegI ix43300000; | |
| 8756 iRegI ix41f00000; | |
| 8757 stackSlotL lx43300000; | |
| 8758 stackSlotL lx41f00000; | |
| 8759 regD_low dx43300000; | |
| 8760 regD dx41f00000; | |
| 8761 regD tmp1; | |
| 8762 regD_low tmp2; | |
| 8763 regD tmp3; | |
| 8764 regD tmp4; | |
| 8765 | |
| 8766 stkL_to_regD(tmpsrc, src); | |
| 8767 | |
| 8768 loadConI_x43300000(ix43300000); | |
| 8769 loadConI_x41f00000(ix41f00000); | |
| 8770 regI_to_stkLHi(lx43300000, ix43300000); | |
| 8771 regI_to_stkLHi(lx41f00000, ix41f00000); | |
| 8772 stkL_to_regD(dx43300000, lx43300000); | |
| 8773 stkL_to_regD(dx41f00000, lx41f00000); | |
| 8774 | |
| 8775 convI2D_regDHi_regD(tmp1, tmpsrc); | |
| 8776 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
| 8777 subD_regD_regD(tmp3, tmp2, dx43300000); | |
| 8778 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
| 8779 addD_regD_regD(dst, tmp3, tmp4); | |
| 8780 %} | |
| 8781 %} | |
| 8782 | |
| 8783 // Long to Double conversion using fast fxtof | |
| 8784 instruct convL2D_helper(regD dst, regD tmp) %{ | |
| 8785 effect(DEF dst, USE tmp); | |
| 8786 size(4); | |
| 8787 format %{ "FXTOD $tmp,$dst" %} | |
| 8788 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
| 8789 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
| 8790 ins_pipe(fcvtL2D); | |
| 8791 %} | |
| 8792 | |
| 3804 | 8793 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ |
| 0 | 8794 predicate(VM_Version::has_fast_fxtof()); |
| 8795 match(Set dst (ConvL2D src)); | |
| 8796 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
| 8797 expand %{ | |
| 8798 regD tmp; | |
| 8799 stkL_to_regD(tmp, src); | |
| 8800 convL2D_helper(dst, tmp); | |
| 8801 %} | |
| 8802 %} | |
| 8803 | |
| 3804 | 8804 instruct convL2D_reg(regD dst, iRegL src) %{ |
| 8805 predicate(UseVIS >= 3); | |
| 8806 match(Set dst (ConvL2D src)); | |
| 8807 expand %{ | |
| 8808 regD tmp; | |
| 8809 MoveL2D_reg_reg(tmp, src); | |
| 8810 convL2D_helper(dst, tmp); | |
| 8811 %} | |
| 8812 %} | |
| 0 | 8813 |
| 8814 // Long to Float conversion using fast fxtof | |
| 8815 instruct convL2F_helper(regF dst, regD tmp) %{ | |
| 8816 effect(DEF dst, USE tmp); | |
| 8817 size(4); | |
| 8818 format %{ "FXTOS $tmp,$dst" %} | |
| 8819 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
| 8820 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
| 8821 ins_pipe(fcvtL2F); | |
| 8822 %} | |
| 8823 | |
| 3804 | 8824 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ |
| 0 | 8825 match(Set dst (ConvL2F src)); |
| 8826 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8827 expand %{ | |
| 8828 regD tmp; | |
| 8829 stkL_to_regD(tmp, src); | |
| 8830 convL2F_helper(dst, tmp); | |
| 8831 %} | |
| 8832 %} | |
| 3804 | 8833 |
| 8834 instruct convL2F_reg(regF dst, iRegL src) %{ | |
| 8835 predicate(UseVIS >= 3); | |
| 8836 match(Set dst (ConvL2F src)); | |
| 8837 ins_cost(DEFAULT_COST); | |
| 8838 expand %{ | |
| 8839 regD tmp; | |
| 8840 MoveL2D_reg_reg(tmp, src); | |
| 8841 convL2F_helper(dst, tmp); | |
| 8842 %} | |
| 8843 %} | |
| 8844 | |
| 0 | 8845 //----------- |
| 8846 | |
| 8847 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
| 8848 match(Set dst (ConvL2I src)); | |
| 8849 #ifndef _LP64 | |
| 8850 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
| 8851 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
| 8852 ins_pipe(ialu_move_reg_I_to_L); | |
| 8853 #else | |
| 8854 size(4); | |
| 8855 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
| 8856 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
| 8857 ins_pipe(ialu_reg); | |
| 8858 #endif | |
| 8859 %} | |
| 8860 | |
| 8861 // Register Shift Right Immediate | |
| 8862 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
| 8863 match(Set dst (ConvL2I (RShiftL src cnt))); | |
| 8864 | |
| 8865 size(4); | |
| 8866 format %{ "SRAX $src,$cnt,$dst" %} | |
| 8867 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 8868 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
| 8869 ins_pipe(ialu_reg_imm); | |
| 8870 %} | |
| 8871 | |
| 8872 //----------Control Flow Instructions------------------------------------------ | |
| 8873 // Compare Instructions | |
| 8874 // Compare Integers | |
| 8875 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
| 8876 match(Set icc (CmpI op1 op2)); | |
| 8877 effect( DEF icc, USE op1, USE op2 ); | |
| 8878 | |
| 8879 size(4); | |
| 8880 format %{ "CMP $op1,$op2" %} | |
| 8881 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8882 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8883 ins_pipe(ialu_cconly_reg_reg); | |
| 8884 %} | |
| 8885 | |
| 8886 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
| 8887 match(Set icc (CmpU op1 op2)); | |
| 8888 | |
| 8889 size(4); | |
| 8890 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 8891 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8892 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8893 ins_pipe(ialu_cconly_reg_reg); | |
| 8894 %} | |
| 8895 | |
| 8896 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
| 8897 match(Set icc (CmpI op1 op2)); | |
| 8898 effect( DEF icc, USE op1 ); | |
| 8899 | |
| 8900 size(4); | |
| 8901 format %{ "CMP $op1,$op2" %} | |
| 8902 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8903 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8904 ins_pipe(ialu_cconly_reg_imm); | |
| 8905 %} | |
| 8906 | |
| 8907 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
| 8908 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8909 | |
| 8910 size(4); | |
| 8911 format %{ "BTST $op2,$op1" %} | |
| 8912 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8913 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8914 ins_pipe(ialu_cconly_reg_reg_zero); | |
| 8915 %} | |
| 8916 | |
| 8917 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
| 8918 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8919 | |
| 8920 size(4); | |
| 8921 format %{ "BTST $op2,$op1" %} | |
| 8922 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8923 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8924 ins_pipe(ialu_cconly_reg_imm_zero); | |
| 8925 %} | |
| 8926 | |
| 8927 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
| 8928 match(Set xcc (CmpL op1 op2)); | |
| 8929 effect( DEF xcc, USE op1, USE op2 ); | |
| 8930 | |
| 8931 size(4); | |
| 8932 format %{ "CMP $op1,$op2\t\t! long" %} | |
| 8933 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8934 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8935 ins_pipe(ialu_cconly_reg_reg); | |
| 8936 %} | |
| 8937 | |
| 8938 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
| 8939 match(Set xcc (CmpL op1 con)); | |
| 8940 effect( DEF xcc, USE op1, USE con ); | |
| 8941 | |
| 8942 size(4); | |
| 8943 format %{ "CMP $op1,$con\t\t! long" %} | |
| 8944 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8945 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 8946 ins_pipe(ialu_cconly_reg_reg); | |
| 8947 %} | |
| 8948 | |
| 8949 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
| 8950 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
| 8951 effect( DEF xcc, USE op1, USE op2 ); | |
| 8952 | |
| 8953 size(4); | |
| 8954 format %{ "BTST $op1,$op2\t\t! long" %} | |
| 8955 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8956 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8957 ins_pipe(ialu_cconly_reg_reg); | |
| 8958 %} | |
| 8959 | |
| 8960 // useful for checking the alignment of a pointer: | |
| 8961 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
| 8962 match(Set xcc (CmpL (AndL op1 con) zero)); | |
| 8963 effect( DEF xcc, USE op1, USE con ); | |
| 8964 | |
| 8965 size(4); | |
| 8966 format %{ "BTST $op1,$con\t\t! long" %} | |
| 8967 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8968 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 8969 ins_pipe(ialu_cconly_reg_reg); | |
| 8970 %} | |
| 8971 | |
| 8972 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ | |
| 8973 match(Set icc (CmpU op1 op2)); | |
| 8974 | |
| 8975 size(4); | |
| 8976 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 8977 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8978 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8979 ins_pipe(ialu_cconly_reg_imm); | |
| 8980 %} | |
| 8981 | |
| 8982 // Compare Pointers | |
| 8983 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
| 8984 match(Set pcc (CmpP op1 op2)); | |
| 8985 | |
| 8986 size(4); | |
| 8987 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 8988 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8989 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8990 ins_pipe(ialu_cconly_reg_reg); | |
| 8991 %} | |
| 8992 | |
| 8993 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
| 8994 match(Set pcc (CmpP op1 op2)); | |
| 8995 | |
| 8996 size(4); | |
| 8997 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 8998 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8999 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 9000 ins_pipe(ialu_cconly_reg_imm); | |
| 9001 %} | |
| 9002 | |
|
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9003 // Compare Narrow oops |
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9004 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
|
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9005 match(Set icc (CmpN op1 op2)); |
|
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9006 |
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9007 size(4); |
|
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9008 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
|
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9009 opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
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9010 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
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9011 ins_pipe(ialu_cconly_reg_reg); |
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9012 %} |
|
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9013 |
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9014 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
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9015 match(Set icc (CmpN op1 op2)); |
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9016 |
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9017 size(4); |
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9018 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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9019 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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9020 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
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9021 ins_pipe(ialu_cconly_reg_imm); |
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9022 %} |
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9023 |
| 0 | 9024 //----------Max and Min-------------------------------------------------------- |
| 9025 // Min Instructions | |
| 9026 // Conditional move for min | |
| 9027 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 9028 effect( USE_DEF op2, USE op1, USE icc ); | |
| 9029 | |
| 9030 size(4); | |
| 9031 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
| 9032 opcode(Assembler::less); | |
| 9033 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 9034 ins_pipe(ialu_reg_flags); | |
| 9035 %} | |
| 9036 | |
| 9037 // Min Register with Register. | |
| 9038 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
| 9039 match(Set op2 (MinI op1 op2)); | |
| 9040 ins_cost(DEFAULT_COST*2); | |
| 9041 expand %{ | |
| 9042 flagsReg icc; | |
| 9043 compI_iReg(icc,op1,op2); | |
| 9044 cmovI_reg_lt(op2,op1,icc); | |
| 9045 %} | |
| 9046 %} | |
| 9047 | |
| 9048 // Max Instructions | |
| 9049 // Conditional move for max | |
| 9050 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 9051 effect( USE_DEF op2, USE op1, USE icc ); | |
| 9052 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
| 9053 opcode(Assembler::greater); | |
| 9054 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 9055 ins_pipe(ialu_reg_flags); | |
| 9056 %} | |
| 9057 | |
| 9058 // Max Register with Register | |
| 9059 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
| 9060 match(Set op2 (MaxI op1 op2)); | |
| 9061 ins_cost(DEFAULT_COST*2); | |
| 9062 expand %{ | |
| 9063 flagsReg icc; | |
| 9064 compI_iReg(icc,op1,op2); | |
| 9065 cmovI_reg_gt(op2,op1,icc); | |
| 9066 %} | |
| 9067 %} | |
| 9068 | |
| 9069 | |
| 9070 //----------Float Compares---------------------------------------------------- | |
| 9071 // Compare floating, generate condition code | |
| 9072 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
| 9073 match(Set fcc (CmpF src1 src2)); | |
| 9074 | |
| 9075 size(4); | |
| 9076 format %{ "FCMPs $fcc,$src1,$src2" %} | |
| 9077 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
| 9078 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
| 9079 ins_pipe(faddF_fcc_reg_reg_zero); | |
| 9080 %} | |
| 9081 | |
| 9082 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
| 9083 match(Set fcc (CmpD src1 src2)); | |
| 9084 | |
| 9085 size(4); | |
| 9086 format %{ "FCMPd $fcc,$src1,$src2" %} | |
| 9087 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
| 9088 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
| 9089 ins_pipe(faddD_fcc_reg_reg_zero); | |
| 9090 %} | |
| 9091 | |
| 9092 | |
| 9093 // Compare floating, generate -1,0,1 | |
| 9094 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
| 9095 match(Set dst (CmpF3 src1 src2)); | |
| 9096 effect(KILL fcc0); | |
| 9097 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 9098 format %{ "fcmpl $dst,$src1,$src2" %} | |
| 9099 // Primary = float | |
| 9100 opcode( true ); | |
| 9101 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 9102 ins_pipe( floating_cmp ); | |
| 9103 %} | |
| 9104 | |
| 9105 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
| 9106 match(Set dst (CmpD3 src1 src2)); | |
| 9107 effect(KILL fcc0); | |
| 9108 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 9109 format %{ "dcmpl $dst,$src1,$src2" %} | |
| 9110 // Primary = double (not float) | |
| 9111 opcode( false ); | |
| 9112 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 9113 ins_pipe( floating_cmp ); | |
| 9114 %} | |
| 9115 | |
| 9116 //----------Branches--------------------------------------------------------- | |
| 9117 // Jump | |
| 9118 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
| 9119 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
| 9120 match(Jump switch_val); | |
|
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9121 effect(TEMP table); |
| 0 | 9122 |
| 9123 ins_cost(350); | |
| 9124 | |
| 2008 | 9125 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" |
| 9126 "LD [O7 + $switch_val], O7\n\t" | |
|
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9127 "JUMP O7" %} |
| 2008 | 9128 ins_encode %{ |
| 9129 // Calculate table address into a register. | |
| 9130 Register table_reg; | |
| 9131 Register label_reg = O7; | |
|
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9132 // If we are calculating the size of this instruction don't trust |
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9133 // zero offsets because they might change when |
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9134 // MachConstantBaseNode decides to optimize the constant table |
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9135 // base. |
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9136 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) { |
| 2008 | 9137 table_reg = $constanttablebase; |
| 9138 } else { | |
| 9139 table_reg = O7; | |
|
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9140 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); |
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9141 __ add($constanttablebase, con_offset, table_reg); |
| 2008 | 9142 } |
| 9143 | |
| 9144 // Jump to base address + switch value | |
| 9145 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); | |
| 9146 __ jmp(label_reg, G0); | |
| 9147 __ delayed()->nop(); | |
| 9148 %} | |
| 0 | 9149 ins_pipe(ialu_reg_reg); |
| 9150 %} | |
| 9151 | |
| 9152 // Direct Branch. Use V8 version with longer range. | |
| 9153 instruct branch(label labl) %{ | |
| 9154 match(Goto); | |
| 9155 effect(USE labl); | |
| 9156 | |
| 9157 size(8); | |
| 9158 ins_cost(BRANCH_COST); | |
| 9159 format %{ "BA $labl" %} | |
| 3839 | 9160 ins_encode %{ |
| 9161 Label* L = $labl$$label; | |
| 9162 __ ba(*L); | |
| 9163 __ delayed()->nop(); | |
| 9164 %} | |
| 0 | 9165 ins_pipe(br); |
| 9166 %} | |
| 9167 | |
| 3851 | 9168 // Direct Branch, short with no delay slot |
| 9169 instruct branch_short(label labl) %{ | |
| 9170 match(Goto); | |
| 9171 predicate(UseCBCond); | |
| 9172 effect(USE labl); | |
| 9173 | |
| 9174 size(4); | |
| 9175 ins_cost(BRANCH_COST); | |
| 9176 format %{ "BA $labl\t! short branch" %} | |
|
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9177 ins_encode %{ |
| 3851 | 9178 Label* L = $labl$$label; |
| 9179 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9180 __ ba_short(*L); | |
| 9181 %} | |
| 9182 ins_short_branch(1); | |
| 9183 ins_avoid_back_to_back(1); | |
| 9184 ins_pipe(cbcond_reg_imm); | |
| 9185 %} | |
| 9186 | |
| 0 | 9187 // Conditional Direct Branch |
| 9188 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 9189 match(If cmp icc); | |
| 9190 effect(USE labl); | |
| 9191 | |
| 9192 size(8); | |
| 9193 ins_cost(BRANCH_COST); | |
| 9194 format %{ "BP$cmp $icc,$labl" %} | |
| 9195 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9196 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9197 ins_pipe(br_cc); | |
| 9198 %} | |
| 9199 | |
| 9200 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9201 match(If cmp icc); | |
| 9202 effect(USE labl); | |
| 9203 | |
| 3851 | 9204 ins_cost(BRANCH_COST); |
| 0 | 9205 format %{ "BP$cmp $icc,$labl" %} |
| 9206 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9207 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9208 ins_pipe(br_cc); | |
| 9209 %} | |
| 9210 | |
| 9211 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
| 9212 match(If cmp pcc); | |
| 9213 effect(USE labl); | |
| 9214 | |
| 9215 size(8); | |
| 9216 ins_cost(BRANCH_COST); | |
| 9217 format %{ "BP$cmp $pcc,$labl" %} | |
| 3839 | 9218 ins_encode %{ |
| 9219 Label* L = $labl$$label; | |
| 9220 Assembler::Predict predict_taken = | |
| 9221 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9222 | |
| 9223 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
| 9224 __ delayed()->nop(); | |
| 9225 %} | |
| 0 | 9226 ins_pipe(br_cc); |
| 9227 %} | |
| 9228 | |
| 9229 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
| 9230 match(If cmp fcc); | |
| 9231 effect(USE labl); | |
| 9232 | |
| 9233 size(8); | |
| 9234 ins_cost(BRANCH_COST); | |
| 9235 format %{ "FBP$cmp $fcc,$labl" %} | |
| 3839 | 9236 ins_encode %{ |
| 9237 Label* L = $labl$$label; | |
| 9238 Assembler::Predict predict_taken = | |
| 9239 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9240 | |
| 9241 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); | |
| 9242 __ delayed()->nop(); | |
| 9243 %} | |
| 0 | 9244 ins_pipe(br_fcc); |
| 9245 %} | |
| 9246 | |
| 9247 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 9248 match(CountedLoopEnd cmp icc); | |
| 9249 effect(USE labl); | |
| 9250 | |
| 9251 size(8); | |
| 9252 ins_cost(BRANCH_COST); | |
| 9253 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9254 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9255 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9256 ins_pipe(br_cc); | |
| 9257 %} | |
| 9258 | |
| 9259 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9260 match(CountedLoopEnd cmp icc); | |
| 9261 effect(USE labl); | |
| 9262 | |
| 9263 size(8); | |
| 9264 ins_cost(BRANCH_COST); | |
| 9265 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9266 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9267 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9268 ins_pipe(br_cc); | |
| 9269 %} | |
| 9270 | |
| 3851 | 9271 // Compare and branch instructions |
| 9272 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
| 9273 match(If cmp (CmpI op1 op2)); | |
| 9274 effect(USE labl, KILL icc); | |
| 9275 | |
| 9276 size(12); | |
| 9277 ins_cost(BRANCH_COST); | |
| 9278 format %{ "CMP $op1,$op2\t! int\n\t" | |
| 9279 "BP$cmp $labl" %} | |
| 9280 ins_encode %{ | |
| 9281 Label* L = $labl$$label; | |
| 9282 Assembler::Predict predict_taken = | |
| 9283 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9284 __ cmp($op1$$Register, $op2$$Register); | |
| 9285 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9286 __ delayed()->nop(); | |
| 9287 %} | |
| 9288 ins_pipe(cmp_br_reg_reg); | |
| 9289 %} | |
| 9290 | |
| 9291 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
| 9292 match(If cmp (CmpI op1 op2)); | |
| 9293 effect(USE labl, KILL icc); | |
| 9294 | |
| 9295 size(12); | |
| 9296 ins_cost(BRANCH_COST); | |
| 9297 format %{ "CMP $op1,$op2\t! int\n\t" | |
| 9298 "BP$cmp $labl" %} | |
| 9299 ins_encode %{ | |
| 9300 Label* L = $labl$$label; | |
| 9301 Assembler::Predict predict_taken = | |
| 9302 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9303 __ cmp($op1$$Register, $op2$$constant); | |
| 9304 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9305 __ delayed()->nop(); | |
| 9306 %} | |
| 9307 ins_pipe(cmp_br_reg_imm); | |
| 9308 %} | |
| 9309 | |
| 9310 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
| 9311 match(If cmp (CmpU op1 op2)); | |
| 9312 effect(USE labl, KILL icc); | |
| 9313 | |
| 9314 size(12); | |
| 9315 ins_cost(BRANCH_COST); | |
| 9316 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
| 9317 "BP$cmp $labl" %} | |
| 9318 ins_encode %{ | |
| 9319 Label* L = $labl$$label; | |
| 9320 Assembler::Predict predict_taken = | |
| 9321 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9322 __ cmp($op1$$Register, $op2$$Register); | |
| 9323 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9324 __ delayed()->nop(); | |
| 9325 %} | |
| 9326 ins_pipe(cmp_br_reg_reg); | |
| 9327 %} | |
| 9328 | |
| 9329 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
| 9330 match(If cmp (CmpU op1 op2)); | |
| 9331 effect(USE labl, KILL icc); | |
| 9332 | |
| 9333 size(12); | |
| 9334 ins_cost(BRANCH_COST); | |
| 9335 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
| 9336 "BP$cmp $labl" %} | |
| 9337 ins_encode %{ | |
| 9338 Label* L = $labl$$label; | |
| 9339 Assembler::Predict predict_taken = | |
| 9340 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9341 __ cmp($op1$$Register, $op2$$constant); | |
| 9342 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9343 __ delayed()->nop(); | |
| 9344 %} | |
| 9345 ins_pipe(cmp_br_reg_imm); | |
| 9346 %} | |
| 9347 | |
| 9348 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
| 9349 match(If cmp (CmpL op1 op2)); | |
| 9350 effect(USE labl, KILL xcc); | |
| 9351 | |
| 9352 size(12); | |
| 9353 ins_cost(BRANCH_COST); | |
| 9354 format %{ "CMP $op1,$op2\t! long\n\t" | |
| 9355 "BP$cmp $labl" %} | |
| 9356 ins_encode %{ | |
| 9357 Label* L = $labl$$label; | |
| 9358 Assembler::Predict predict_taken = | |
| 9359 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9360 __ cmp($op1$$Register, $op2$$Register); | |
| 9361 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
| 9362 __ delayed()->nop(); | |
| 9363 %} | |
| 9364 ins_pipe(cmp_br_reg_reg); | |
| 9365 %} | |
| 9366 | |
| 9367 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
| 9368 match(If cmp (CmpL op1 op2)); | |
| 9369 effect(USE labl, KILL xcc); | |
| 9370 | |
| 9371 size(12); | |
| 9372 ins_cost(BRANCH_COST); | |
| 9373 format %{ "CMP $op1,$op2\t! long\n\t" | |
| 9374 "BP$cmp $labl" %} | |
| 9375 ins_encode %{ | |
| 9376 Label* L = $labl$$label; | |
| 9377 Assembler::Predict predict_taken = | |
| 9378 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9379 __ cmp($op1$$Register, $op2$$constant); | |
| 9380 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
| 9381 __ delayed()->nop(); | |
| 9382 %} | |
| 9383 ins_pipe(cmp_br_reg_imm); | |
| 9384 %} | |
| 9385 | |
| 9386 // Compare Pointers and branch | |
| 9387 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
| 9388 match(If cmp (CmpP op1 op2)); | |
| 9389 effect(USE labl, KILL pcc); | |
| 9390 | |
| 9391 size(12); | |
| 9392 ins_cost(BRANCH_COST); | |
| 9393 format %{ "CMP $op1,$op2\t! ptr\n\t" | |
| 9394 "B$cmp $labl" %} | |
| 9395 ins_encode %{ | |
| 9396 Label* L = $labl$$label; | |
| 9397 Assembler::Predict predict_taken = | |
| 9398 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9399 __ cmp($op1$$Register, $op2$$Register); | |
| 9400 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
| 9401 __ delayed()->nop(); | |
| 9402 %} | |
| 9403 ins_pipe(cmp_br_reg_reg); | |
| 9404 %} | |
| 9405 | |
| 9406 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
| 9407 match(If cmp (CmpP op1 null)); | |
| 9408 effect(USE labl, KILL pcc); | |
| 9409 | |
| 9410 size(12); | |
| 9411 ins_cost(BRANCH_COST); | |
| 9412 format %{ "CMP $op1,0\t! ptr\n\t" | |
| 9413 "B$cmp $labl" %} | |
| 9414 ins_encode %{ | |
| 9415 Label* L = $labl$$label; | |
| 9416 Assembler::Predict predict_taken = | |
| 9417 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9418 __ cmp($op1$$Register, G0); | |
| 9419 // bpr() is not used here since it has shorter distance. | |
| 9420 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
| 9421 __ delayed()->nop(); | |
| 9422 %} | |
| 9423 ins_pipe(cmp_br_reg_reg); | |
| 9424 %} | |
| 9425 | |
| 9426 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
| 9427 match(If cmp (CmpN op1 op2)); | |
| 9428 effect(USE labl, KILL icc); | |
| 9429 | |
| 9430 size(12); | |
| 9431 ins_cost(BRANCH_COST); | |
| 9432 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" | |
| 9433 "BP$cmp $labl" %} | |
| 9434 ins_encode %{ | |
| 9435 Label* L = $labl$$label; | |
| 9436 Assembler::Predict predict_taken = | |
| 9437 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9438 __ cmp($op1$$Register, $op2$$Register); | |
| 9439 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9440 __ delayed()->nop(); | |
| 9441 %} | |
| 9442 ins_pipe(cmp_br_reg_reg); | |
| 9443 %} | |
| 9444 | |
| 9445 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
| 9446 match(If cmp (CmpN op1 null)); | |
| 9447 effect(USE labl, KILL icc); | |
| 9448 | |
| 9449 size(12); | |
| 9450 ins_cost(BRANCH_COST); | |
| 9451 format %{ "CMP $op1,0\t! compressed ptr\n\t" | |
| 9452 "BP$cmp $labl" %} | |
| 9453 ins_encode %{ | |
| 9454 Label* L = $labl$$label; | |
| 9455 Assembler::Predict predict_taken = | |
| 9456 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9457 __ cmp($op1$$Register, G0); | |
| 9458 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9459 __ delayed()->nop(); | |
| 9460 %} | |
| 9461 ins_pipe(cmp_br_reg_reg); | |
| 9462 %} | |
| 9463 | |
| 9464 // Loop back branch | |
| 9465 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
| 9466 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
| 9467 effect(USE labl, KILL icc); | |
| 9468 | |
| 9469 size(12); | |
| 9470 ins_cost(BRANCH_COST); | |
| 9471 format %{ "CMP $op1,$op2\t! int\n\t" | |
| 9472 "BP$cmp $labl\t! Loop end" %} | |
| 9473 ins_encode %{ | |
| 9474 Label* L = $labl$$label; | |
| 9475 Assembler::Predict predict_taken = | |
| 9476 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9477 __ cmp($op1$$Register, $op2$$Register); | |
| 9478 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9479 __ delayed()->nop(); | |
| 9480 %} | |
| 9481 ins_pipe(cmp_br_reg_reg); | |
| 9482 %} | |
| 9483 | |
| 9484 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
| 9485 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
| 9486 effect(USE labl, KILL icc); | |
| 9487 | |
| 9488 size(12); | |
| 9489 ins_cost(BRANCH_COST); | |
| 9490 format %{ "CMP $op1,$op2\t! int\n\t" | |
| 9491 "BP$cmp $labl\t! Loop end" %} | |
| 9492 ins_encode %{ | |
| 9493 Label* L = $labl$$label; | |
| 9494 Assembler::Predict predict_taken = | |
| 9495 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9496 __ cmp($op1$$Register, $op2$$constant); | |
| 9497 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9498 __ delayed()->nop(); | |
| 9499 %} | |
| 9500 ins_pipe(cmp_br_reg_imm); | |
| 9501 %} | |
| 9502 | |
| 9503 // Short compare and branch instructions | |
| 9504 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
| 9505 match(If cmp (CmpI op1 op2)); | |
| 9506 predicate(UseCBCond); | |
| 9507 effect(USE labl, KILL icc); | |
| 9508 | |
| 9509 size(4); | |
| 9510 ins_cost(BRANCH_COST); | |
| 9511 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
| 9512 ins_encode %{ | |
| 9513 Label* L = $labl$$label; | |
| 9514 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9515 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
| 9516 %} | |
| 9517 ins_short_branch(1); | |
| 9518 ins_avoid_back_to_back(1); | |
| 9519 ins_pipe(cbcond_reg_reg); | |
| 9520 %} | |
| 9521 | |
| 9522 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
| 9523 match(If cmp (CmpI op1 op2)); | |
| 9524 predicate(UseCBCond); | |
| 9525 effect(USE labl, KILL icc); | |
| 9526 | |
| 9527 size(4); | |
| 9528 ins_cost(BRANCH_COST); | |
| 9529 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
| 9530 ins_encode %{ | |
| 9531 Label* L = $labl$$label; | |
| 9532 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9533 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
| 9534 %} | |
| 9535 ins_short_branch(1); | |
| 9536 ins_avoid_back_to_back(1); | |
| 9537 ins_pipe(cbcond_reg_imm); | |
| 9538 %} | |
| 9539 | |
| 9540 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
| 9541 match(If cmp (CmpU op1 op2)); | |
| 9542 predicate(UseCBCond); | |
| 9543 effect(USE labl, KILL icc); | |
| 9544 | |
| 9545 size(4); | |
| 9546 ins_cost(BRANCH_COST); | |
| 9547 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
| 9548 ins_encode %{ | |
| 9549 Label* L = $labl$$label; | |
| 9550 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9551 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
| 9552 %} | |
| 9553 ins_short_branch(1); | |
| 9554 ins_avoid_back_to_back(1); | |
| 9555 ins_pipe(cbcond_reg_reg); | |
| 9556 %} | |
| 9557 | |
| 9558 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
| 9559 match(If cmp (CmpU op1 op2)); | |
| 9560 predicate(UseCBCond); | |
| 9561 effect(USE labl, KILL icc); | |
| 9562 | |
| 9563 size(4); | |
| 9564 ins_cost(BRANCH_COST); | |
| 9565 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
| 9566 ins_encode %{ | |
| 9567 Label* L = $labl$$label; | |
| 9568 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9569 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
| 9570 %} | |
| 9571 ins_short_branch(1); | |
| 9572 ins_avoid_back_to_back(1); | |
| 9573 ins_pipe(cbcond_reg_imm); | |
| 9574 %} | |
| 9575 | |
| 9576 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
| 9577 match(If cmp (CmpL op1 op2)); | |
| 9578 predicate(UseCBCond); | |
| 9579 effect(USE labl, KILL xcc); | |
| 9580 | |
| 9581 size(4); | |
| 9582 ins_cost(BRANCH_COST); | |
| 9583 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
| 9584 ins_encode %{ | |
| 9585 Label* L = $labl$$label; | |
| 9586 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9587 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); | |
| 9588 %} | |
| 9589 ins_short_branch(1); | |
| 9590 ins_avoid_back_to_back(1); | |
| 9591 ins_pipe(cbcond_reg_reg); | |
| 9592 %} | |
| 9593 | |
| 9594 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
| 9595 match(If cmp (CmpL op1 op2)); | |
| 9596 predicate(UseCBCond); | |
| 9597 effect(USE labl, KILL xcc); | |
| 9598 | |
| 9599 size(4); | |
| 9600 ins_cost(BRANCH_COST); | |
| 9601 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
| 9602 ins_encode %{ | |
| 9603 Label* L = $labl$$label; | |
| 9604 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9605 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); | |
| 9606 %} | |
| 9607 ins_short_branch(1); | |
| 9608 ins_avoid_back_to_back(1); | |
| 9609 ins_pipe(cbcond_reg_imm); | |
| 9610 %} | |
| 9611 | |
| 9612 // Compare Pointers and branch | |
| 9613 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
| 9614 match(If cmp (CmpP op1 op2)); | |
| 9615 predicate(UseCBCond); | |
| 9616 effect(USE labl, KILL pcc); | |
| 9617 | |
| 9618 size(4); | |
| 9619 ins_cost(BRANCH_COST); | |
| 9620 #ifdef _LP64 | |
| 9621 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} | |
| 9622 #else | |
| 9623 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %} | |
| 9624 #endif | |
| 9625 ins_encode %{ | |
| 9626 Label* L = $labl$$label; | |
| 9627 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9628 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); | |
| 9629 %} | |
| 9630 ins_short_branch(1); | |
| 9631 ins_avoid_back_to_back(1); | |
| 9632 ins_pipe(cbcond_reg_reg); | |
| 9633 %} | |
| 9634 | |
| 9635 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
| 9636 match(If cmp (CmpP op1 null)); | |
| 9637 predicate(UseCBCond); | |
| 9638 effect(USE labl, KILL pcc); | |
| 9639 | |
| 9640 size(4); | |
| 9641 ins_cost(BRANCH_COST); | |
| 9642 #ifdef _LP64 | |
| 9643 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} | |
| 9644 #else | |
| 9645 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %} | |
| 9646 #endif | |
| 9647 ins_encode %{ | |
| 9648 Label* L = $labl$$label; | |
| 9649 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9650 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); | |
| 9651 %} | |
| 9652 ins_short_branch(1); | |
| 9653 ins_avoid_back_to_back(1); | |
| 9654 ins_pipe(cbcond_reg_reg); | |
| 9655 %} | |
| 9656 | |
| 9657 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
| 9658 match(If cmp (CmpN op1 op2)); | |
| 9659 predicate(UseCBCond); | |
| 9660 effect(USE labl, KILL icc); | |
| 9661 | |
| 9662 size(4); | |
| 9663 ins_cost(BRANCH_COST); | |
| 9664 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %} | |
| 9665 ins_encode %{ | |
| 9666 Label* L = $labl$$label; | |
| 9667 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9668 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
| 9669 %} | |
| 9670 ins_short_branch(1); | |
| 9671 ins_avoid_back_to_back(1); | |
| 9672 ins_pipe(cbcond_reg_reg); | |
| 9673 %} | |
| 9674 | |
| 9675 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
| 9676 match(If cmp (CmpN op1 null)); | |
| 9677 predicate(UseCBCond); | |
| 9678 effect(USE labl, KILL icc); | |
| 9679 | |
| 9680 size(4); | |
| 9681 ins_cost(BRANCH_COST); | |
| 9682 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} | |
| 9683 ins_encode %{ | |
| 9684 Label* L = $labl$$label; | |
| 9685 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9686 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); | |
| 9687 %} | |
| 9688 ins_short_branch(1); | |
| 9689 ins_avoid_back_to_back(1); | |
| 9690 ins_pipe(cbcond_reg_reg); | |
| 9691 %} | |
| 9692 | |
| 9693 // Loop back branch | |
| 9694 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
| 9695 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
| 9696 predicate(UseCBCond); | |
| 9697 effect(USE labl, KILL icc); | |
| 9698 | |
| 9699 size(4); | |
| 9700 ins_cost(BRANCH_COST); | |
| 9701 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
| 9702 ins_encode %{ | |
| 9703 Label* L = $labl$$label; | |
| 9704 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9705 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
| 9706 %} | |
| 9707 ins_short_branch(1); | |
| 9708 ins_avoid_back_to_back(1); | |
| 9709 ins_pipe(cbcond_reg_reg); | |
| 9710 %} | |
| 9711 | |
| 9712 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
| 9713 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
| 9714 predicate(UseCBCond); | |
| 9715 effect(USE labl, KILL icc); | |
| 9716 | |
| 9717 size(4); | |
| 9718 ins_cost(BRANCH_COST); | |
| 9719 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
| 9720 ins_encode %{ | |
| 9721 Label* L = $labl$$label; | |
| 9722 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9723 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
| 9724 %} | |
| 9725 ins_short_branch(1); | |
| 9726 ins_avoid_back_to_back(1); | |
| 9727 ins_pipe(cbcond_reg_imm); | |
| 9728 %} | |
| 9729 | |
| 9730 // Branch-on-register tests all 64 bits. We assume that values | |
| 9731 // in 64-bit registers always remains zero or sign extended | |
| 9732 // unless our code munges the high bits. Interrupts can chop | |
| 9733 // the high order bits to zero or sign at any time. | |
| 9734 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
| 9735 match(If cmp (CmpI op1 zero)); | |
| 9736 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9737 effect(USE labl); | |
| 9738 | |
| 9739 size(8); | |
| 9740 ins_cost(BRANCH_COST); | |
| 9741 format %{ "BR$cmp $op1,$labl" %} | |
| 9742 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9743 ins_pipe(br_reg); | |
| 9744 %} | |
| 9745 | |
| 9746 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
| 9747 match(If cmp (CmpP op1 null)); | |
| 9748 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9749 effect(USE labl); | |
| 9750 | |
| 9751 size(8); | |
| 9752 ins_cost(BRANCH_COST); | |
| 9753 format %{ "BR$cmp $op1,$labl" %} | |
| 9754 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9755 ins_pipe(br_reg); | |
| 9756 %} | |
| 9757 | |
| 9758 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
| 9759 match(If cmp (CmpL op1 zero)); | |
| 9760 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9761 effect(USE labl); | |
| 9762 | |
| 9763 size(8); | |
| 9764 ins_cost(BRANCH_COST); | |
| 9765 format %{ "BR$cmp $op1,$labl" %} | |
| 9766 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9767 ins_pipe(br_reg); | |
| 9768 %} | |
| 9769 | |
| 9770 | |
| 0 | 9771 // ============================================================================ |
| 9772 // Long Compare | |
| 9773 // | |
| 9774 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 9775 // is tricky. The flavor of compare used depends on whether we are testing | |
| 9776 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 9777 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 9778 // the operands (yielding a GE test) and then negating; negate again for the | |
| 9779 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 9780 // NE test is negated from that. | |
| 9781 | |
| 9782 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 9783 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 9784 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 9785 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 9786 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 9787 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 9788 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 9789 // both forms beat the trinary form of long-compare and both are very useful | |
| 9790 // on Intel which has so few registers. | |
| 9791 | |
| 9792 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
| 9793 match(If cmp xcc); | |
| 9794 effect(USE labl); | |
| 9795 | |
| 9796 size(8); | |
| 9797 ins_cost(BRANCH_COST); | |
| 9798 format %{ "BP$cmp $xcc,$labl" %} | |
| 3839 | 9799 ins_encode %{ |
| 9800 Label* L = $labl$$label; | |
| 9801 Assembler::Predict predict_taken = | |
| 9802 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9803 | |
| 9804 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
| 9805 __ delayed()->nop(); | |
| 9806 %} | |
| 0 | 9807 ins_pipe(br_cc); |
| 9808 %} | |
| 9809 | |
| 9810 // Manifest a CmpL3 result in an integer register. Very painful. | |
| 9811 // This is the test to avoid. | |
| 9812 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
| 9813 match(Set dst (CmpL3 src1 src2) ); | |
| 9814 effect( KILL ccr ); | |
| 9815 ins_cost(6*DEFAULT_COST); | |
| 9816 size(24); | |
| 9817 format %{ "CMP $src1,$src2\t\t! long\n" | |
| 9818 "\tBLT,a,pn done\n" | |
| 9819 "\tMOV -1,$dst\t! delay slot\n" | |
| 9820 "\tBGT,a,pn done\n" | |
| 9821 "\tMOV 1,$dst\t! delay slot\n" | |
| 9822 "\tCLR $dst\n" | |
| 9823 "done:" %} | |
| 9824 ins_encode( cmpl_flag(src1,src2,dst) ); | |
| 9825 ins_pipe(cmpL_reg); | |
| 9826 %} | |
| 9827 | |
| 9828 // Conditional move | |
| 9829 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
| 9830 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9831 ins_cost(150); | |
| 9832 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9833 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9834 ins_pipe(ialu_reg); | |
| 9835 %} | |
| 9836 | |
| 9837 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
| 9838 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9839 ins_cost(140); | |
| 9840 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9841 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9842 ins_pipe(ialu_imm); | |
| 9843 %} | |
| 9844 | |
| 9845 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
| 9846 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9847 ins_cost(150); | |
| 9848 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9849 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9850 ins_pipe(ialu_reg); | |
| 9851 %} | |
| 9852 | |
| 9853 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
| 9854 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9855 ins_cost(140); | |
| 9856 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9857 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9858 ins_pipe(ialu_imm); | |
| 9859 %} | |
| 9860 | |
|
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9861 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
|
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9862 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
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9863 ins_cost(150); |
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9864 format %{ "MOV$cmp $xcc,$src,$dst" %} |
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9865 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
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9866 ins_pipe(ialu_reg); |
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9867 %} |
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9868 |
| 0 | 9869 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
| 9870 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 9871 ins_cost(150); | |
| 9872 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9873 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9874 ins_pipe(ialu_reg); | |
| 9875 %} | |
| 9876 | |
| 9877 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
| 9878 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 9879 ins_cost(140); | |
| 9880 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9881 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9882 ins_pipe(ialu_imm); | |
| 9883 %} | |
| 9884 | |
| 9885 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
| 9886 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
| 9887 ins_cost(150); | |
| 9888 opcode(0x101); | |
| 9889 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
| 9890 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9891 ins_pipe(int_conditional_float_move); | |
| 9892 %} | |
| 9893 | |
| 9894 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
| 9895 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
| 9896 ins_cost(150); | |
| 9897 opcode(0x102); | |
| 9898 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
| 9899 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9900 ins_pipe(int_conditional_float_move); | |
| 9901 %} | |
| 9902 | |
| 9903 // ============================================================================ | |
| 9904 // Safepoint Instruction | |
| 9905 instruct safePoint_poll(iRegP poll) %{ | |
| 9906 match(SafePoint poll); | |
| 9907 effect(USE poll); | |
| 9908 | |
| 9909 size(4); | |
| 9910 #ifdef _LP64 | |
| 9911 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 9912 #else | |
| 9913 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 9914 #endif | |
| 9915 ins_encode %{ | |
| 9916 __ relocate(relocInfo::poll_type); | |
| 9917 __ ld_ptr($poll$$Register, 0, G0); | |
| 9918 %} | |
| 9919 ins_pipe(loadPollP); | |
| 9920 %} | |
| 9921 | |
| 9922 // ============================================================================ | |
| 9923 // Call Instructions | |
| 9924 // Call Java Static Instruction | |
| 9925 instruct CallStaticJavaDirect( method meth ) %{ | |
| 9926 match(CallStaticJava); | |
| 1567 | 9927 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
| 0 | 9928 effect(USE meth); |
| 9929 | |
| 9930 size(8); | |
| 9931 ins_cost(CALL_COST); | |
| 9932 format %{ "CALL,static ; NOP ==> " %} | |
| 9933 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
| 9934 ins_pipe(simple_call); | |
| 9935 %} | |
| 9936 | |
| 1567 | 9937 // Call Java Static Instruction (method handle version) |
| 9938 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ | |
| 9939 match(CallStaticJava); | |
| 9940 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); | |
| 9941 effect(USE meth, KILL l7_mh_SP_save); | |
| 9942 | |
|
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9943 size(16); |
| 1567 | 9944 ins_cost(CALL_COST); |
| 9945 format %{ "CALL,static/MethodHandle" %} | |
| 9946 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); | |
| 9947 ins_pipe(simple_call); | |
| 9948 %} | |
| 9949 | |
| 0 | 9950 // Call Java Dynamic Instruction |
| 9951 instruct CallDynamicJavaDirect( method meth ) %{ | |
| 9952 match(CallDynamicJava); | |
| 9953 effect(USE meth); | |
| 9954 | |
| 9955 ins_cost(CALL_COST); | |
| 9956 format %{ "SET (empty),R_G5\n\t" | |
| 9957 "CALL,dynamic ; NOP ==> " %} | |
| 9958 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
| 9959 ins_pipe(call); | |
| 9960 %} | |
| 9961 | |
| 9962 // Call Runtime Instruction | |
| 9963 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
| 9964 match(CallRuntime); | |
| 9965 effect(USE meth, KILL l7); | |
| 9966 ins_cost(CALL_COST); | |
| 9967 format %{ "CALL,runtime" %} | |
| 9968 ins_encode( Java_To_Runtime( meth ), | |
| 9969 call_epilog, adjust_long_from_native_call ); | |
| 9970 ins_pipe(simple_call); | |
| 9971 %} | |
| 9972 | |
| 9973 // Call runtime without safepoint - same as CallRuntime | |
| 9974 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
| 9975 match(CallLeaf); | |
| 9976 effect(USE meth, KILL l7); | |
| 9977 ins_cost(CALL_COST); | |
| 9978 format %{ "CALL,runtime leaf" %} | |
| 9979 ins_encode( Java_To_Runtime( meth ), | |
| 9980 call_epilog, | |
| 9981 adjust_long_from_native_call ); | |
| 9982 ins_pipe(simple_call); | |
| 9983 %} | |
| 9984 | |
| 9985 // Call runtime without safepoint - same as CallLeaf | |
| 9986 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
| 9987 match(CallLeafNoFP); | |
| 9988 effect(USE meth, KILL l7); | |
| 9989 ins_cost(CALL_COST); | |
| 9990 format %{ "CALL,runtime leaf nofp" %} | |
| 9991 ins_encode( Java_To_Runtime( meth ), | |
| 9992 call_epilog, | |
| 9993 adjust_long_from_native_call ); | |
| 9994 ins_pipe(simple_call); | |
| 9995 %} | |
| 9996 | |
| 9997 // Tail Call; Jump from runtime stub to Java code. | |
| 9998 // Also known as an 'interprocedural jump'. | |
| 9999 // Target of jump will eventually return to caller. | |
| 10000 // TailJump below removes the return address. | |
| 10001 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
| 10002 match(TailCall jump_target method_oop ); | |
| 10003 | |
| 10004 ins_cost(CALL_COST); | |
| 10005 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
| 10006 ins_encode(form_jmpl(jump_target)); | |
| 10007 ins_pipe(tail_call); | |
| 10008 %} | |
| 10009 | |
| 10010 | |
| 10011 // Return Instruction | |
| 10012 instruct Ret() %{ | |
| 10013 match(Return); | |
| 10014 | |
| 10015 // The epilogue node did the ret already. | |
| 10016 size(0); | |
| 10017 format %{ "! return" %} | |
| 10018 ins_encode(); | |
| 10019 ins_pipe(empty); | |
| 10020 %} | |
| 10021 | |
| 10022 | |
| 10023 // Tail Jump; remove the return address; jump to target. | |
| 10024 // TailCall above leaves the return address around. | |
| 10025 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
| 10026 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
| 10027 // "restore" before this instruction (in Epilogue), we need to materialize it | |
| 10028 // in %i0. | |
| 10029 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
| 10030 match( TailJump jump_target ex_oop ); | |
| 10031 ins_cost(CALL_COST); | |
| 10032 format %{ "! discard R_O7\n\t" | |
| 10033 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
| 10034 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
| 10035 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
| 10036 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
| 10037 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
| 10038 ins_pipe(tail_call); | |
| 10039 %} | |
| 10040 | |
| 10041 // Create exception oop: created by stack-crawling runtime code. | |
| 10042 // Created exception is now available to this handler, and is setup | |
| 10043 // just prior to jumping to this handler. No code emitted. | |
| 10044 instruct CreateException( o0RegP ex_oop ) | |
| 10045 %{ | |
| 10046 match(Set ex_oop (CreateEx)); | |
| 10047 ins_cost(0); | |
| 10048 | |
| 10049 size(0); | |
| 10050 // use the following format syntax | |
| 10051 format %{ "! exception oop is in R_O0; no code emitted" %} | |
| 10052 ins_encode(); | |
| 10053 ins_pipe(empty); | |
| 10054 %} | |
| 10055 | |
| 10056 | |
| 10057 // Rethrow exception: | |
| 10058 // The exception oop will come in the first argument position. | |
| 10059 // Then JUMP (not call) to the rethrow stub code. | |
| 10060 instruct RethrowException() | |
| 10061 %{ | |
| 10062 match(Rethrow); | |
| 10063 ins_cost(CALL_COST); | |
| 10064 | |
| 10065 // use the following format syntax | |
| 10066 format %{ "Jmp rethrow_stub" %} | |
| 10067 ins_encode(enc_rethrow); | |
| 10068 ins_pipe(tail_call); | |
| 10069 %} | |
| 10070 | |
| 10071 | |
| 10072 // Die now | |
| 10073 instruct ShouldNotReachHere( ) | |
| 10074 %{ | |
| 10075 match(Halt); | |
| 10076 ins_cost(CALL_COST); | |
| 10077 | |
| 10078 size(4); | |
| 10079 // Use the following format syntax | |
| 10080 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
| 10081 ins_encode( form2_illtrap() ); | |
| 10082 ins_pipe(tail_call); | |
| 10083 %} | |
| 10084 | |
| 10085 // ============================================================================ | |
| 10086 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 10087 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 10088 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 10089 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 10090 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
| 10091 match(Set index (PartialSubtypeCheck sub super)); | |
| 10092 effect( KILL pcc, KILL o7 ); | |
| 10093 ins_cost(DEFAULT_COST*10); | |
| 10094 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
| 10095 ins_encode( enc_PartialSubtypeCheck() ); | |
| 10096 ins_pipe(partial_subtype_check_pipe); | |
| 10097 %} | |
| 10098 | |
| 10099 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
| 10100 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 10101 effect( KILL idx, KILL o7 ); | |
| 10102 ins_cost(DEFAULT_COST*10); | |
| 10103 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
| 10104 ins_encode( enc_PartialSubtypeCheck() ); | |
| 10105 ins_pipe(partial_subtype_check_pipe); | |
| 10106 %} | |
| 10107 | |
|
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10108 |
| 0 | 10109 // ============================================================================ |
| 10110 // inlined locking and unlocking | |
| 10111 | |
| 4777 | 10112 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ |
| 0 | 10113 match(Set pcc (FastLock object box)); |
| 10114 | |
| 4777 | 10115 effect(TEMP scratch2, USE_KILL box, KILL scratch); |
| 0 | 10116 ins_cost(100); |
| 10117 | |
| 4777 | 10118 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} |
| 0 | 10119 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); |
| 10120 ins_pipe(long_memory_op); | |
| 10121 %} | |
| 10122 | |
| 10123 | |
| 4777 | 10124 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ |
| 0 | 10125 match(Set pcc (FastUnlock object box)); |
| 4777 | 10126 effect(TEMP scratch2, USE_KILL box, KILL scratch); |
| 0 | 10127 ins_cost(100); |
| 10128 | |
| 4777 | 10129 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} |
| 0 | 10130 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); |
| 10131 ins_pipe(long_memory_op); | |
| 10132 %} | |
| 10133 | |
| 3892 | 10134 // The encodings are generic. |
| 0 | 10135 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ |
| 3892 | 10136 predicate(!use_block_zeroing(n->in(2)) ); |
| 0 | 10137 match(Set dummy (ClearArray cnt base)); |
| 10138 effect(TEMP temp, KILL ccr); | |
| 10139 ins_cost(300); | |
| 10140 format %{ "MOV $cnt,$temp\n" | |
| 10141 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
| 10142 " BRge loop\t\t! Clearing loop\n" | |
| 10143 " STX G0,[$base+$temp]\t! delay slot" %} | |
| 3892 | 10144 |
| 10145 ins_encode %{ | |
| 10146 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
| 10147 Register nof_bytes_arg = $cnt$$Register; | |
| 10148 Register nof_bytes_tmp = $temp$$Register; | |
| 10149 Register base_pointer_arg = $base$$Register; | |
| 10150 | |
| 10151 Label loop; | |
| 10152 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
| 10153 | |
| 10154 // Loop and clear, walking backwards through the array. | |
| 10155 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
| 10156 __ bind(loop); | |
| 10157 __ deccc(nof_bytes_tmp, 8); | |
| 10158 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
| 10159 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
| 10160 // %%%% this mini-loop must not cross a cache boundary! | |
| 10161 %} | |
| 10162 ins_pipe(long_memory_op); | |
| 10163 %} | |
| 10164 | |
| 10165 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{ | |
| 10166 predicate(use_block_zeroing(n->in(2))); | |
| 10167 match(Set dummy (ClearArray cnt base)); | |
| 10168 effect(USE_KILL cnt, USE_KILL base, KILL ccr); | |
| 10169 ins_cost(300); | |
| 10170 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} | |
| 10171 | |
| 10172 ins_encode %{ | |
| 10173 | |
| 10174 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); | |
| 10175 Register to = $base$$Register; | |
| 10176 Register count = $cnt$$Register; | |
| 10177 | |
| 10178 Label Ldone; | |
| 10179 __ nop(); // Separate short branches | |
| 10180 // Use BIS for zeroing (temp is not used). | |
| 10181 __ bis_zeroing(to, count, G0, Ldone); | |
| 10182 __ bind(Ldone); | |
| 10183 | |
| 10184 %} | |
| 10185 ins_pipe(long_memory_op); | |
| 10186 %} | |
| 10187 | |
| 10188 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{ | |
| 10189 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit)); | |
| 10190 match(Set dummy (ClearArray cnt base)); | |
| 10191 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr); | |
| 10192 ins_cost(300); | |
| 10193 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} | |
| 10194 | |
| 10195 ins_encode %{ | |
| 10196 | |
| 10197 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); | |
| 10198 Register to = $base$$Register; | |
| 10199 Register count = $cnt$$Register; | |
| 10200 Register temp = $tmp$$Register; | |
| 10201 | |
| 10202 Label Ldone; | |
| 10203 __ nop(); // Separate short branches | |
| 10204 // Use BIS for zeroing | |
| 10205 __ bis_zeroing(to, count, temp, Ldone); | |
| 10206 __ bind(Ldone); | |
| 10207 | |
| 10208 %} | |
| 0 | 10209 ins_pipe(long_memory_op); |
| 10210 %} | |
| 10211 | |
|
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10212 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
|
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|
10213 o7RegI tmp, flagsReg ccr) %{ |
|
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|
10214 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
|
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|
10215 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
| 0 | 10216 ins_cost(300); |
|
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|
10217 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
|
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|
10218 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
| 0 | 10219 ins_pipe(long_memory_op); |
| 10220 %} | |
| 10221 | |
|
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|
10222 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
|
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|
10223 o7RegI tmp, flagsReg ccr) %{ |
|
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|
10224 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
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|
10225 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
| 681 | 10226 ins_cost(300); |
|
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|
10227 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
|
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|
10228 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
| 681 | 10229 ins_pipe(long_memory_op); |
| 10230 %} | |
| 10231 | |
|
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|
10232 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
|
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|
10233 o7RegI tmp2, flagsReg ccr) %{ |
| 681 | 10234 match(Set result (AryEq ary1 ary2)); |
| 10235 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
| 10236 ins_cost(300); | |
|
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|
10237 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
|
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|
10238 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
| 681 | 10239 ins_pipe(long_memory_op); |
| 10240 %} | |
|
643
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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|
10241 |
|
775
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|
10242 |
|
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|
10243 //---------- Zeros Count Instructions ------------------------------------------ |
|
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|
10244 |
|
7426
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|
10245 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
|
775
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|
10246 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
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|
10247 match(Set dst (CountLeadingZerosI src)); |
|
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10248 effect(TEMP dst, TEMP tmp, KILL cr); |
|
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|
10249 |
|
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|
10250 // x |= (x >> 1); |
|
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|
10251 // x |= (x >> 2); |
|
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|
10252 // x |= (x >> 4); |
|
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|
10253 // x |= (x >> 8); |
|
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|
10254 // x |= (x >> 16); |
|
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|
10255 // return (WORDBITS - popc(x)); |
|
1041
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|
10256 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
|
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|
10257 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
|
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|
10258 "OR $dst,$tmp,$dst\n\t" |
|
775
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|
10259 "SRL $dst,2,$tmp\n\t" |
|
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|
10260 "OR $dst,$tmp,$dst\n\t" |
|
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|
10261 "SRL $dst,4,$tmp\n\t" |
|
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|
10262 "OR $dst,$tmp,$dst\n\t" |
|
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|
10263 "SRL $dst,8,$tmp\n\t" |
|
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|
10264 "OR $dst,$tmp,$dst\n\t" |
|
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|
10265 "SRL $dst,16,$tmp\n\t" |
|
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|
10266 "OR $dst,$tmp,$dst\n\t" |
|
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|
10267 "POPC $dst,$dst\n\t" |
|
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|
10268 "MOV 32,$tmp\n\t" |
|
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|
10269 "SUB $tmp,$dst,$dst" %} |
|
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|
10270 ins_encode %{ |
|
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|
10271 Register Rdst = $dst$$Register; |
|
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|
10272 Register Rsrc = $src$$Register; |
|
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|
10273 Register Rtmp = $tmp$$Register; |
|
1915
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|
10274 __ srl(Rsrc, 1, Rtmp); |
|
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|
10275 __ srl(Rsrc, 0, Rdst); |
|
1041
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|
10276 __ or3(Rdst, Rtmp, Rdst); |
|
1915
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|
10277 __ srl(Rdst, 2, Rtmp); |
|
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10278 __ or3(Rdst, Rtmp, Rdst); |
|
1915
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|
10279 __ srl(Rdst, 4, Rtmp); |
|
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10280 __ or3(Rdst, Rtmp, Rdst); |
|
1915
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|
10281 __ srl(Rdst, 8, Rtmp); |
|
775
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|
10282 __ or3(Rdst, Rtmp, Rdst); |
|
1915
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|
10283 __ srl(Rdst, 16, Rtmp); |
|
775
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|
10284 __ or3(Rdst, Rtmp, Rdst); |
|
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|
10285 __ popc(Rdst, Rdst); |
|
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|
10286 __ mov(BitsPerInt, Rtmp); |
|
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10287 __ sub(Rtmp, Rdst, Rdst); |
|
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|
10288 %} |
|
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|
10289 ins_pipe(ialu_reg); |
|
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|
10290 %} |
|
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|
10291 |
|
1915
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changeset
|
10292 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
|
775
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|
10293 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
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|
10294 match(Set dst (CountLeadingZerosL src)); |
|
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|
10295 effect(TEMP dst, TEMP tmp, KILL cr); |
|
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|
10296 |
|
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|
10297 // x |= (x >> 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10298 // x |= (x >> 2); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10299 // x |= (x >> 4); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10300 // x |= (x >> 8); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10301 // x |= (x >> 16); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10302 // x |= (x >> 32); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10303 // return (WORDBITS - popc(x)); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10304 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10305 "OR $src,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10306 "SRLX $dst,2,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10307 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10308 "SRLX $dst,4,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10309 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10310 "SRLX $dst,8,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10311 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10312 "SRLX $dst,16,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10313 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10314 "SRLX $dst,32,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10315 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10316 "POPC $dst,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10317 "MOV 64,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10318 "SUB $tmp,$dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10319 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10320 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10321 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10322 Register Rtmp = $tmp$$Register; |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10323 __ srlx(Rsrc, 1, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10324 __ or3( Rsrc, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10325 __ srlx(Rdst, 2, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10326 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10327 __ srlx(Rdst, 4, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10328 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10329 __ srlx(Rdst, 8, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10330 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10331 __ srlx(Rdst, 16, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10332 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10333 __ srlx(Rdst, 32, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10334 __ or3( Rdst, Rtmp, Rdst); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10335 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10336 __ mov(BitsPerLong, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10337 __ sub(Rtmp, Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10338 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10339 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10340 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10341 |
|
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10342 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10343 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10344 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10345 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10346 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10347 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10348 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10349 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10350 "SRL $dst,R_G0,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10351 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10352 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10353 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10354 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10355 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10356 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10357 __ srl(Rdst, G0, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10358 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10359 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10360 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10361 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10362 |
|
4003
4bac06a82bc3
7100757: The BitSet.nextSetBit() produces incorrect result in 32bit VM on Sparc
kvn
parents:
3898
diff
changeset
|
10363 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10364 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10365 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10366 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10367 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10368 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10369 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10370 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10371 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10372 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10373 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10374 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10375 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10376 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10377 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10378 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10379 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10380 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10381 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10382 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10383 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10384 |
|
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10385 instruct popCountI(iRegIsafe dst, iRegI src) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10386 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10387 match(Set dst (PopCountI src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10388 |
|
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10389 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t" |
|
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10390 "POPC $dst, $dst" %} |
|
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10391 ins_encode %{ |
|
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10392 __ srl($src$$Register, G0, $dst$$Register); |
|
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10393 __ popc($dst$$Register, $dst$$Register); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10394 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10395 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10396 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10397 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10398 // Note: Long.bitCount(long) returns an int. |
|
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10399 instruct popCountL(iRegIsafe dst, iRegL src) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10400 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10401 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10402 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10403 format %{ "POPC $src, $dst" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10404 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10405 __ popc($src$$Register, $dst$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10406 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10407 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10408 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10409 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10410 |
| 0 | 10411 // ============================================================================ |
| 10412 //------------Bytes reverse-------------------------------------------------- | |
| 10413 | |
| 10414 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
| 10415 match(Set dst (ReverseBytesI src)); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10416 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10417 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10418 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10419 // onto a stack slot. |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10420 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10421 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10422 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10423 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10424 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10425 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10426 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10427 ins_pipe( iload_mem ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10428 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10429 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10430 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10431 match(Set dst (ReverseBytesL src)); |
| 0 | 10432 |
| 10433 // Op cost is artificially doubled to make sure that load or store | |
| 10434 // instructions are preferred over this one which requires a spill | |
| 10435 // onto a stack slot. | |
| 10436 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10437 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10438 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10439 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10440 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10441 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10442 %} |
| 0 | 10443 ins_pipe( iload_mem ); |
| 10444 %} | |
| 10445 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10446 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10447 match(Set dst (ReverseBytesUS src)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10448 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10449 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10450 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10451 // onto a stack slot. |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10452 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10453 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10454 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10455 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10456 // the value was spilled as an int so bias the load |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10457 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10458 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10459 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10460 ins_pipe( iload_mem ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10461 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10462 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10463 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10464 match(Set dst (ReverseBytesS src)); |
| 0 | 10465 |
| 10466 // Op cost is artificially doubled to make sure that load or store | |
| 10467 // instructions are preferred over this one which requires a spill | |
| 10468 // onto a stack slot. | |
| 10469 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10470 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10471 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10472 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10473 // the value was spilled as an int so bias the load |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10474 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10475 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10476 %} |
| 0 | 10477 ins_pipe( iload_mem ); |
| 10478 %} | |
| 10479 | |
| 10480 // Load Integer reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10481 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ |
| 0 | 10482 match(Set dst (ReverseBytesI (LoadI src))); |
| 10483 | |
| 10484 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10485 size(4); |
| 0 | 10486 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
| 10487 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10488 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10489 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10490 %} |
| 0 | 10491 ins_pipe(iload_mem); |
| 10492 %} | |
| 10493 | |
| 10494 // Load Long - aligned and reversed | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10495 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ |
| 0 | 10496 match(Set dst (ReverseBytesL (LoadL src))); |
| 10497 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10498 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10499 size(4); |
| 0 | 10500 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
| 10501 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10502 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10503 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10504 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10505 ins_pipe(iload_mem); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10506 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10507 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10508 // Load unsigned short / char reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10509 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10510 match(Set dst (ReverseBytesUS (LoadUS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10511 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10512 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10513 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10514 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10515 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10516 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10517 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10518 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10519 ins_pipe(iload_mem); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10520 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10521 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10522 // Load short reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10523 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10524 match(Set dst (ReverseBytesS (LoadS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10525 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10526 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10527 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10528 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10529 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10530 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10531 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10532 %} |
| 0 | 10533 ins_pipe(iload_mem); |
| 10534 %} | |
| 10535 | |
| 10536 // Store Integer reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10537 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ |
| 0 | 10538 match(Set dst (StoreI dst (ReverseBytesI src))); |
| 10539 | |
| 10540 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10541 size(4); |
| 0 | 10542 format %{ "STWA $src, $dst\t!asi=primary_little" %} |
| 10543 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10544 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10545 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10546 %} |
| 0 | 10547 ins_pipe(istore_mem_reg); |
| 10548 %} | |
| 10549 | |
| 10550 // Store Long reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10551 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ |
| 0 | 10552 match(Set dst (StoreL dst (ReverseBytesL src))); |
| 10553 | |
| 10554 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10555 size(4); |
| 0 | 10556 format %{ "STXA $src, $dst\t!asi=primary_little" %} |
| 10557 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10558 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10559 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10560 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10561 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10562 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10563 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10564 // Store unsighed short/char reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10565 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10566 match(Set dst (StoreC dst (ReverseBytesUS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10567 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10568 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10569 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10570 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10571 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10572 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10573 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10574 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10575 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10576 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10577 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10578 // Store short reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10579 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10580 match(Set dst (StoreC dst (ReverseBytesS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10581 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10582 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10583 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10584 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10585 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10586 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10587 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10588 %} |
| 0 | 10589 ins_pipe(istore_mem_reg); |
| 10590 %} | |
| 10591 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10592 // ====================VECTOR INSTRUCTIONS===================================== |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10593 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10594 // Load Aligned Packed values into a Double Register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10595 instruct loadV8(regD dst, memory mem) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10596 predicate(n->as_LoadVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10597 match(Set dst (LoadVector mem)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10598 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10599 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10600 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10601 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10602 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10603 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10604 ins_pipe(floadD_mem); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10605 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10606 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10607 // Store Vector in Double register to memory |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10608 instruct storeV8(memory mem, regD src) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10609 predicate(n->as_StoreVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10610 match(Set mem (StoreVector mem src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10611 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10612 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10613 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10614 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10615 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10616 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10617 ins_pipe(fstoreD_mem_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10618 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10619 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10620 // Store Zero into vector in memory |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10621 instruct storeV8B_zero(memory mem, immI0 zero) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10622 predicate(n->as_StoreVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10623 match(Set mem (StoreVector mem (ReplicateB zero))); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10624 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10625 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10626 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10627 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10628 __ stx(G0, $mem$$Address); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10629 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10630 ins_pipe(fstoreD_mem_zero); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10631 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10632 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10633 instruct storeV4S_zero(memory mem, immI0 zero) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10634 predicate(n->as_StoreVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10635 match(Set mem (StoreVector mem (ReplicateS zero))); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10636 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10637 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10638 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10639 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10640 __ stx(G0, $mem$$Address); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10641 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10642 ins_pipe(fstoreD_mem_zero); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10643 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10644 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10645 instruct storeV2I_zero(memory mem, immI0 zero) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10646 predicate(n->as_StoreVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10647 match(Set mem (StoreVector mem (ReplicateI zero))); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10648 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10649 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10650 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10651 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10652 __ stx(G0, $mem$$Address); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10653 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10654 ins_pipe(fstoreD_mem_zero); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10655 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10656 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10657 instruct storeV2F_zero(memory mem, immF0 zero) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10658 predicate(n->as_StoreVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10659 match(Set mem (StoreVector mem (ReplicateF zero))); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10660 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10661 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10662 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10663 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10664 __ stx(G0, $mem$$Address); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10665 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10666 ins_pipe(fstoreD_mem_zero); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10667 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10668 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10669 // Replicate scalar to packed byte values into Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10670 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10671 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10672 match(Set dst (ReplicateB src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10673 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10674 format %{ "SLLX $src,56,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10675 "SRLX $tmp, 8,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10676 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10677 "SRLX $tmp,16,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10678 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10679 "SRLX $tmp,32,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10680 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10681 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10682 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10683 Register Rsrc = $src$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10684 Register Rtmp = $tmp$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10685 Register Rtmp2 = $tmp2$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10686 __ sllx(Rsrc, 56, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10687 __ srlx(Rtmp, 8, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10688 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10689 __ srlx(Rtmp, 16, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10690 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10691 __ srlx(Rtmp, 32, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10692 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10693 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10694 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10695 ins_pipe(ialu_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10696 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10697 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10698 // Replicate scalar to packed byte values into Double stack |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10699 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10700 predicate(n->as_Vector()->length() == 8 && UseVIS < 3); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10701 match(Set dst (ReplicateB src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10702 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10703 format %{ "SLLX $src,56,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10704 "SRLX $tmp, 8,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10705 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10706 "SRLX $tmp,16,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10707 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10708 "SRLX $tmp,32,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10709 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10710 "STX $tmp,$dst\t! regL to stkD" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10711 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10712 Register Rsrc = $src$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10713 Register Rtmp = $tmp$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10714 Register Rtmp2 = $tmp2$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10715 __ sllx(Rsrc, 56, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10716 __ srlx(Rtmp, 8, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10717 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10718 __ srlx(Rtmp, 16, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10719 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10720 __ srlx(Rtmp, 32, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10721 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10722 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10723 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10724 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10725 ins_pipe(ialu_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10726 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10727 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10728 // Replicate scalar constant to packed byte values in Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10729 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10730 predicate(n->as_Vector()->length() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10731 match(Set dst (ReplicateB con)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10732 effect(KILL tmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10733 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10734 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10735 // XXX This is a quick fix for 6833573. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10736 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10737 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10738 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10739 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10740 ins_pipe(loadConFD); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10741 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10742 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10743 // Replicate scalar to packed char/short values into Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10744 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10745 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10746 match(Set dst (ReplicateS src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10747 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10748 format %{ "SLLX $src,48,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10749 "SRLX $tmp,16,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10750 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10751 "SRLX $tmp,32,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10752 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10753 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10754 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10755 Register Rsrc = $src$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10756 Register Rtmp = $tmp$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10757 Register Rtmp2 = $tmp2$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10758 __ sllx(Rsrc, 48, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10759 __ srlx(Rtmp, 16, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10760 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10761 __ srlx(Rtmp, 32, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10762 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10763 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10764 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10765 ins_pipe(ialu_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10766 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10767 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10768 // Replicate scalar to packed char/short values into Double stack |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10769 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10770 predicate(n->as_Vector()->length() == 4 && UseVIS < 3); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10771 match(Set dst (ReplicateS src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10772 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10773 format %{ "SLLX $src,48,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10774 "SRLX $tmp,16,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10775 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10776 "SRLX $tmp,32,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10777 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10778 "STX $tmp,$dst\t! regL to stkD" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10779 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10780 Register Rsrc = $src$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10781 Register Rtmp = $tmp$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10782 Register Rtmp2 = $tmp2$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10783 __ sllx(Rsrc, 48, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10784 __ srlx(Rtmp, 16, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10785 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10786 __ srlx(Rtmp, 32, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10787 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10788 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10789 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10790 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10791 ins_pipe(ialu_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10792 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10793 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10794 // Replicate scalar constant to packed char/short values in Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10795 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10796 predicate(n->as_Vector()->length() == 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10797 match(Set dst (ReplicateS con)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10798 effect(KILL tmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10799 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10800 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10801 // XXX This is a quick fix for 6833573. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10802 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10803 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10804 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10805 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10806 ins_pipe(loadConFD); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10807 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10808 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10809 // Replicate scalar to packed int values into Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10810 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
8c92982cbbc4
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10811 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3); |
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10812 match(Set dst (ReplicateI src)); |
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10813 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
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10814 format %{ "SLLX $src,32,$tmp\n\t" |
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10815 "SRLX $tmp,32,$tmp2\n\t" |
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10816 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" |
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10817 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
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10818 ins_encode %{ |
|
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10819 Register Rsrc = $src$$Register; |
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10820 Register Rtmp = $tmp$$Register; |
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10821 Register Rtmp2 = $tmp2$$Register; |
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10822 __ sllx(Rsrc, 32, Rtmp); |
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10823 __ srlx(Rtmp, 32, Rtmp2); |
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10824 __ or3 (Rtmp, Rtmp2, Rtmp); |
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10825 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
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10826 %} |
|
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10827 ins_pipe(ialu_reg); |
|
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10828 %} |
|
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10829 |
|
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10830 // Replicate scalar to packed int values into Double stack |
|
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10831 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
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10832 predicate(n->as_Vector()->length() == 2 && UseVIS < 3); |
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10833 match(Set dst (ReplicateI src)); |
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10834 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
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10835 format %{ "SLLX $src,32,$tmp\n\t" |
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10836 "SRLX $tmp,32,$tmp2\n\t" |
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10837 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" |
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10838 "STX $tmp,$dst\t! regL to stkD" %} |
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10839 ins_encode %{ |
|
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10840 Register Rsrc = $src$$Register; |
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10841 Register Rtmp = $tmp$$Register; |
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10842 Register Rtmp2 = $tmp2$$Register; |
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10843 __ sllx(Rsrc, 32, Rtmp); |
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10844 __ srlx(Rtmp, 32, Rtmp2); |
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10845 __ or3 (Rtmp, Rtmp2, Rtmp); |
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10846 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
|
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10847 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
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10848 %} |
|
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10849 ins_pipe(ialu_reg); |
|
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10850 %} |
|
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|
10851 |
|
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10852 // Replicate scalar zero constant to packed int values in Double register |
|
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10853 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ |
|
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10854 predicate(n->as_Vector()->length() == 2); |
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10855 match(Set dst (ReplicateI con)); |
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10856 effect(KILL tmp); |
|
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10857 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} |
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|
10858 ins_encode %{ |
|
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|
10859 // XXX This is a quick fix for 6833573. |
|
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10860 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); |
|
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10861 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); |
|
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10862 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
|
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|
10863 %} |
|
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|
10864 ins_pipe(loadConFD); |
|
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|
10865 %} |
|
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|
10866 |
|
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|
10867 // Replicate scalar to packed float values into Double stack |
|
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10868 instruct Repl2F_stk(stackSlotD dst, regF src) %{ |
|
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|
10869 predicate(n->as_Vector()->length() == 2); |
|
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10870 match(Set dst (ReplicateF src)); |
|
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|
10871 ins_cost(MEMORY_REF_COST*2); |
|
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10872 format %{ "STF $src,$dst.hi\t! packed2F\n\t" |
|
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10873 "STF $src,$dst.lo" %} |
|
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|
10874 opcode(Assembler::stf_op3); |
|
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10875 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src)); |
|
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|
10876 ins_pipe(fstoreF_stk_reg); |
|
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|
10877 %} |
|
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|
10878 |
|
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|
10879 // Replicate scalar zero constant to packed float values in Double register |
|
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|
10880 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{ |
|
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|
10881 predicate(n->as_Vector()->length() == 2); |
|
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10882 match(Set dst (ReplicateF con)); |
|
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|
10883 effect(KILL tmp); |
|
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|
10884 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %} |
|
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|
10885 ins_encode %{ |
|
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|
10886 // XXX This is a quick fix for 6833573. |
|
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|
10887 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister); |
|
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10888 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register); |
|
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10889 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
|
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|
10890 %} |
|
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|
10891 ins_pipe(loadConFD); |
|
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|
10892 %} |
|
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|
10893 |
| 0 | 10894 //----------PEEPHOLE RULES----------------------------------------------------- |
| 10895 // These must follow all instruction definitions as they use the names | |
| 10896 // defined in the instructions definitions. | |
| 10897 // | |
| 605 | 10898 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 10899 // |
| 10900 // peepconstraint %{ | |
| 10901 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 10902 // [, ...] ); | |
| 10903 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 10904 // | |
| 10905 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 10906 // // provide an instruction_number.operand_name for each operand that appears | |
| 10907 // // in the replacement instruction's match rule | |
| 10908 // | |
| 10909 // ---------VM FLAGS--------------------------------------------------------- | |
| 10910 // | |
| 10911 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 10912 // | |
| 10913 // Each peephole rule is given an identifying number starting with zero and | |
| 10914 // increasing by one in the order seen by the parser. An individual peephole | |
| 10915 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 10916 // on the command-line. | |
| 10917 // | |
| 10918 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 10919 // | |
| 10920 // Only match adjacent instructions in same basic block | |
| 10921 // Only equality constraints | |
| 10922 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 10923 // Only one replacement instruction | |
| 10924 // | |
| 10925 // ---------EXAMPLE---------------------------------------------------------- | |
| 10926 // | |
| 10927 // // pertinent parts of existing instructions in architecture description | |
| 10928 // instruct movI(eRegI dst, eRegI src) %{ | |
| 10929 // match(Set dst (CopyI src)); | |
| 10930 // %} | |
| 10931 // | |
| 10932 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 10933 // match(Set dst (AddI dst src)); | |
| 10934 // effect(KILL cr); | |
| 10935 // %} | |
| 10936 // | |
| 10937 // // Change (inc mov) to lea | |
| 10938 // peephole %{ | |
| 10939 // // increment preceeded by register-register move | |
| 10940 // peepmatch ( incI_eReg movI ); | |
| 10941 // // require that the destination register of the increment | |
| 10942 // // match the destination register of the move | |
| 10943 // peepconstraint ( 0.dst == 1.dst ); | |
| 10944 // // construct a replacement instruction that sets | |
| 10945 // // the destination to ( move's source register + one ) | |
| 10946 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
| 10947 // %} | |
| 10948 // | |
| 10949 | |
| 10950 // // Change load of spilled value to only a spill | |
| 10951 // instruct storeI(memory mem, eRegI src) %{ | |
| 10952 // match(Set mem (StoreI mem src)); | |
| 10953 // %} | |
| 10954 // | |
| 10955 // instruct loadI(eRegI dst, memory mem) %{ | |
| 10956 // match(Set dst (LoadI mem)); | |
| 10957 // %} | |
| 10958 // | |
| 10959 // peephole %{ | |
| 10960 // peepmatch ( loadI storeI ); | |
| 10961 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 10962 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 10963 // %} | |
| 10964 | |
| 10965 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 10966 // These must follow all instruction definitions as they use the names | |
| 10967 // defined in the instructions definitions. | |
| 10968 // | |
| 10969 // SPARC will probably not have any of these rules due to RISC instruction set. | |
| 10970 | |
| 10971 //----------PIPELINE----------------------------------------------------------- | |
| 10972 // Rules which define the behavior of the target architectures pipeline. |