Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sparc.ad @ 17810:62c54fcc0a35
Merge
| author | kvn |
|---|---|
| date | Tue, 25 Mar 2014 17:07:36 -0700 |
| parents | a433eb716ce1 085b304a1cc5 |
| children | 17b2fbdb6637 |
| rev | line source |
|---|---|
| 0 | 1 // |
| 9154 | 2 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // SPARC Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 register %{ | |
| 32 //----------Architecture Description Register Definitions---------------------- | |
| 33 // General Registers | |
| 34 // "reg_def" name ( register save type, C convention save type, | |
| 35 // ideal register type, encoding, vm name ); | |
| 36 // Register Save Types: | |
| 37 // | |
| 38 // NS = No-Save: The register allocator assumes that these registers | |
| 39 // can be used without saving upon entry to the method, & | |
| 40 // that they do not need to be saved at call sites. | |
| 41 // | |
| 42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 43 // can be used without saving upon entry to the method, | |
| 44 // but that they must be saved at call sites. | |
| 45 // | |
| 46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 47 // must be saved before using them upon entry to the | |
| 48 // method, but they do not need to be saved at call | |
| 49 // sites. | |
| 50 // | |
| 51 // AS = Always-Save: The register allocator assumes that these registers | |
| 52 // must be saved before using them upon entry to the | |
| 53 // method, & that they must be saved at call sites. | |
| 54 // | |
| 55 // Ideal Register Type is used to determine how to save & restore a | |
| 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 58 // | |
| 59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 60 | |
| 61 | |
| 62 // ---------------------------- | |
| 63 // Integer/Long Registers | |
| 64 // ---------------------------- | |
| 65 | |
| 66 // Need to expose the hi/lo aspect of 64-bit registers | |
| 67 // This register set is used for both the 64-bit build and | |
| 68 // the 32-bit build with 1-register longs. | |
| 69 | |
| 70 // Global Registers 0-7 | |
| 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
| 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
| 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
| 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
| 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
| 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
| 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
| 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
| 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
| 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
| 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
| 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
| 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
| 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
| 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
| 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
| 87 | |
| 88 // Output Registers 0-7 | |
| 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
| 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
| 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
| 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
| 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
| 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
| 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
| 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
| 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
| 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
| 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
| 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
| 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
| 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
| 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
| 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
| 105 | |
| 106 // Local Registers 0-7 | |
| 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
| 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
| 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
| 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
| 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
| 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
| 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
| 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
| 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
| 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
| 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
| 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
| 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
| 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
| 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
| 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
| 123 | |
| 124 // Input Registers 0-7 | |
| 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
| 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
| 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
| 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
| 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
| 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
| 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
| 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
| 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
| 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
| 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
| 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
| 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
| 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
| 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
| 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
| 141 | |
| 142 // ---------------------------- | |
| 143 // Float/Double Registers | |
| 144 // ---------------------------- | |
| 145 | |
| 146 // Float Registers | |
| 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
| 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
| 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
| 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
| 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
| 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
| 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
| 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
| 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
| 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
| 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
| 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
| 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
| 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
| 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
| 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
| 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
| 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
| 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
| 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
| 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
| 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
| 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
| 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
| 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
| 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
| 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
| 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
| 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
| 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
| 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
| 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
| 179 | |
| 180 // Double Registers | |
| 181 // The rules of ADL require that double registers be defined in pairs. | |
| 182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
| 183 // single float registers. In each pair, ADLC-assigned register numbers | |
| 184 // must be adjacent, with the lower number even. Finally, when the | |
| 185 // CPU stores such a register pair to memory, the word associated with | |
| 186 // the lower ADLC-assigned number must be stored to the lower address. | |
| 187 | |
| 188 // These definitions specify the actual bit encodings of the sparc | |
| 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
| 190 // wants 0-63, so we have to convert every time we want to use fp regs | |
| 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
| 605 | 192 // 255 is a flag meaning "don't go here". |
| 0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
| 194 // the place in the sparc stack crawler that asserts on the 255 is | |
| 195 // fixed up. | |
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196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
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197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
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198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
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199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
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200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
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201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
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202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
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203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
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204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
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205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
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206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
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207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
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208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
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209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
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210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
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211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
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212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
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213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
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214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
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215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
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216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
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217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
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218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
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219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
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220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
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221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
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222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
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223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
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224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
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225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
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226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
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227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
| 0 | 228 |
| 229 | |
| 230 // ---------------------------- | |
| 231 // Special Registers | |
| 232 // Condition Codes Flag Registers | |
| 233 // I tried to break out ICC and XCC but it's not very pretty. | |
| 234 // Every Sparc instruction which defs/kills one also kills the other. | |
| 235 // Hence every compare instruction which defs one kind of flags ends | |
| 236 // up needing a kill of the other. | |
| 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 238 | |
| 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
| 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
| 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
| 243 | |
| 244 // ---------------------------- | |
| 245 // Specify the enum values for the registers. These enums are only used by the | |
| 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
| 247 // for visibility to the rest of the vm. The order of this enum influences the | |
| 248 // register allocator so having the freedom to set this order and not be stuck | |
| 249 // with the order that is natural for the rest of the vm is worth it. | |
| 250 alloc_class chunk0( | |
| 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
| 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
| 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
| 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
| 255 | |
| 256 // Note that a register is not allocatable unless it is also mentioned | |
| 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
| 258 | |
| 259 alloc_class chunk1( | |
| 260 // The first registers listed here are those most likely to be used | |
| 261 // as temporaries. We move F0..F7 away from the front of the list, | |
| 262 // to reduce the likelihood of interferences with parameters and | |
| 263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
| 264 // since they are used for return values. | |
| 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
| 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
| 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
| 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
| 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
| 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
| 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
| 274 | |
| 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
| 276 | |
| 277 //----------Architecture Description Register Classes-------------------------- | |
| 278 // Several register classes are automatically defined based upon information in | |
| 279 // this architecture description. | |
| 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
| 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
| 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 283 // | |
| 284 | |
| 285 // G0 is not included in integer class since it has special meaning. | |
| 286 reg_class g0_reg(R_G0); | |
| 287 | |
| 288 // ---------------------------- | |
| 289 // Integer Register Classes | |
| 290 // ---------------------------- | |
| 291 // Exclusions from i_reg: | |
| 292 // R_G0: hardwired zero | |
| 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
| 294 // R_G6: reserved by Solaris ABI to tools | |
| 295 // R_G7: reserved by Solaris ABI to libthread | |
| 296 // R_O7: Used as a temp in many encodings | |
| 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 298 | |
| 299 // Class for all integer registers, except the G registers. This is used for | |
| 300 // encodings which use G registers as temps. The regular inputs to such | |
| 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
| 302 // will not put an input into a temp register. | |
| 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 304 | |
| 305 reg_class g1_regI(R_G1); | |
| 306 reg_class g3_regI(R_G3); | |
| 307 reg_class g4_regI(R_G4); | |
| 308 reg_class o0_regI(R_O0); | |
| 309 reg_class o7_regI(R_O7); | |
| 310 | |
| 311 // ---------------------------- | |
| 312 // Pointer Register Classes | |
| 313 // ---------------------------- | |
| 314 #ifdef _LP64 | |
| 315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
| 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 320 // Lock encodings use G3 and G4 internally | |
| 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
| 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 326 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
| 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
| 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 332 // We use it to save R_G2 across calls out of Java. | |
| 333 reg_class l7_regP(R_L7H,R_L7); | |
| 334 | |
| 335 // Other special pointer regs | |
| 336 reg_class g1_regP(R_G1H,R_G1); | |
| 337 reg_class g2_regP(R_G2H,R_G2); | |
| 338 reg_class g3_regP(R_G3H,R_G3); | |
| 339 reg_class g4_regP(R_G4H,R_G4); | |
| 340 reg_class g5_regP(R_G5H,R_G5); | |
| 341 reg_class i0_regP(R_I0H,R_I0); | |
| 342 reg_class o0_regP(R_O0H,R_O0); | |
| 343 reg_class o1_regP(R_O1H,R_O1); | |
| 344 reg_class o2_regP(R_O2H,R_O2); | |
| 345 reg_class o7_regP(R_O7H,R_O7); | |
| 346 | |
| 347 #else // _LP64 | |
| 348 // 32-bit build means 32-bit pointers means 1 register. | |
| 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
| 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 353 // Lock encodings use G3 and G4 internally | |
| 354 reg_class lock_ptr_reg(R_G1, R_G5, | |
| 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 359 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
| 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
| 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
| 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 365 // We use it to save R_G2 across calls out of Java. | |
| 366 reg_class l7_regP(R_L7); | |
| 367 | |
| 368 // Other special pointer regs | |
| 369 reg_class g1_regP(R_G1); | |
| 370 reg_class g2_regP(R_G2); | |
| 371 reg_class g3_regP(R_G3); | |
| 372 reg_class g4_regP(R_G4); | |
| 373 reg_class g5_regP(R_G5); | |
| 374 reg_class i0_regP(R_I0); | |
| 375 reg_class o0_regP(R_O0); | |
| 376 reg_class o1_regP(R_O1); | |
| 377 reg_class o2_regP(R_O2); | |
| 378 reg_class o7_regP(R_O7); | |
| 379 #endif // _LP64 | |
| 380 | |
| 381 | |
| 382 // ---------------------------- | |
| 383 // Long Register Classes | |
| 384 // ---------------------------- | |
| 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
| 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
| 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
| 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
| 389 #ifdef _LP64 | |
| 390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
| 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
| 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
| 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
| 394 #endif // _LP64 | |
| 395 ); | |
| 396 | |
| 397 reg_class g1_regL(R_G1H,R_G1); | |
|
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398 reg_class g3_regL(R_G3H,R_G3); |
| 0 | 399 reg_class o2_regL(R_O2H,R_O2); |
| 400 reg_class o7_regL(R_O7H,R_O7); | |
| 401 | |
| 402 // ---------------------------- | |
| 403 // Special Class for Condition Code Flags Register | |
| 404 reg_class int_flags(CCR); | |
| 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
| 406 reg_class float_flag0(FCC0); | |
| 407 | |
| 408 | |
| 409 // ---------------------------- | |
| 410 // Float Point Register Classes | |
| 411 // ---------------------------- | |
| 412 // Skip F30/F31, they are reserved for mem-mem copies | |
| 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
| 414 | |
| 415 // Paired floating point registers--they show up in the same order as the floats, | |
| 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
| 419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
| 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
| 422 ); | |
| 423 | |
| 424 // Paired floating point registers--they show up in the same order as the floats, | |
| 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
| 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 3804 | 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); |
| 0 | 429 %} |
| 430 | |
| 431 //----------DEFINITION BLOCK--------------------------------------------------- | |
| 432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
| 433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
| 434 // Format: | |
| 435 // int_def <name> ( <int_value>, <expression>); | |
| 436 // Generated Code in ad_<arch>.hpp | |
| 437 // #define <name> (<expression>) | |
| 438 // // value == <int_value> | |
| 439 // Generated code in ad_<arch>.cpp adlc_verification() | |
| 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
| 441 // | |
| 442 definitions %{ | |
| 443 // The default cost (of an ALU instruction). | |
| 444 int_def DEFAULT_COST ( 100, 100); | |
| 445 int_def HUGE_COST (1000000, 1000000); | |
| 446 | |
| 447 // Memory refs are twice as expensive as run-of-the-mill. | |
| 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
| 449 | |
| 450 // Branches are even more expensive. | |
| 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
| 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
| 453 %} | |
| 454 | |
| 455 | |
| 456 //----------SOURCE BLOCK------------------------------------------------------- | |
| 457 // This is a block of C++ code which provides values, functions, and | |
| 458 // definitions necessary in the rest of the architecture description | |
| 459 source_hpp %{ | |
|
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460 // Header information of the source block. |
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461 // Method declarations/definitions which are used outside |
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462 // the ad-scope can conveniently be defined here. |
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463 // |
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464 // To keep related declarations/definitions/uses close together, |
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465 // we switch between source %{ }% and source_hpp %{ }% freely as needed. |
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466 |
| 0 | 467 // Must be visible to the DFA in dfa_sparc.cpp |
| 468 extern bool can_branch_register( Node *bol, Node *cmp ); | |
| 469 | |
| 3892 | 470 extern bool use_block_zeroing(Node* count); |
| 471 | |
| 0 | 472 // Macros to extract hi & lo halves from a long pair. |
| 473 // G0 is not part of any long pair, so assert on that. | |
| 605 | 474 // Prevents accidentally using G1 instead of G0. |
| 0 | 475 #define LONG_HI_REG(x) (x) |
| 476 #define LONG_LO_REG(x) (x) | |
| 477 | |
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478 class CallStubImpl { |
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479 |
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480 //-------------------------------------------------------------- |
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481 //---< Used for optimization in Compile::Shorten_branches >--- |
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482 //-------------------------------------------------------------- |
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483 |
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484 public: |
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485 // Size of call trampoline stub. |
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486 static uint size_call_trampoline() { |
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487 return 0; // no call trampolines on this platform |
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488 } |
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489 |
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490 // number of relocations needed by a call trampoline stub |
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491 static uint reloc_call_trampoline() { |
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492 return 0; // no call trampolines on this platform |
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493 } |
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494 }; |
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495 |
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496 class HandlerImpl { |
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497 |
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498 public: |
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499 |
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500 static int emit_exception_handler(CodeBuffer &cbuf); |
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501 static int emit_deopt_handler(CodeBuffer& cbuf); |
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502 |
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503 static uint size_exception_handler() { |
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504 if (TraceJumps) { |
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505 return (400); // just a guess |
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506 } |
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507 return ( NativeJump::instruction_size ); // sethi;jmp;nop |
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508 } |
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509 |
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510 static uint size_deopt_handler() { |
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511 if (TraceJumps) { |
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512 return (400); // just a guess |
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513 } |
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514 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore |
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515 } |
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516 }; |
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517 |
| 0 | 518 %} |
| 519 | |
| 520 source %{ | |
| 521 #define __ _masm. | |
| 522 | |
| 523 // tertiary op of a LoadP or StoreP encoding | |
| 524 #define REGP_OP true | |
| 525 | |
| 526 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
| 527 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
| 528 static Register reg_to_register_object(int register_encoding); | |
| 529 | |
| 530 // Used by the DFA in dfa_sparc.cpp. | |
| 531 // Check for being able to use a V9 branch-on-register. Requires a | |
| 532 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
| 533 // extended. Doesn't work following an integer ADD, for example, because of | |
| 534 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
| 535 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
| 536 // replace them with zero, which could become sign-extension in a different OS | |
| 537 // release. There's no obvious reason why an interrupt will ever fill these | |
| 538 // bits with non-zero junk (the registers are reloaded with standard LD | |
| 539 // instructions which either zero-fill or sign-fill). | |
| 540 bool can_branch_register( Node *bol, Node *cmp ) { | |
| 541 if( !BranchOnRegister ) return false; | |
| 542 #ifdef _LP64 | |
| 543 if( cmp->Opcode() == Op_CmpP ) | |
| 544 return true; // No problems with pointer compares | |
| 545 #endif | |
| 546 if( cmp->Opcode() == Op_CmpL ) | |
| 547 return true; // No problems with long compares | |
| 548 | |
| 549 if( !SparcV9RegsHiBitsZero ) return false; | |
| 550 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
| 551 bol->as_Bool()->_test._test != BoolTest::eq ) | |
| 552 return false; | |
| 553 | |
| 554 // Check for comparing against a 'safe' value. Any operation which | |
| 555 // clears out the high word is safe. Thus, loads and certain shifts | |
| 556 // are safe, as are non-negative constants. Any operation which | |
| 557 // preserves zero bits in the high word is safe as long as each of its | |
| 558 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
| 559 // inputs are safe. At present, the only important case to recognize | |
| 560 // seems to be loads. Constants should fold away, and shifts & | |
| 561 // logicals can use the 'cc' forms. | |
| 562 Node *x = cmp->in(1); | |
| 563 if( x->is_Load() ) return true; | |
| 564 if( x->is_Phi() ) { | |
| 565 for( uint i = 1; i < x->req(); i++ ) | |
| 566 if( !x->in(i)->is_Load() ) | |
| 567 return false; | |
| 568 return true; | |
| 569 } | |
| 570 return false; | |
| 571 } | |
| 572 | |
| 3892 | 573 bool use_block_zeroing(Node* count) { |
| 574 // Use BIS for zeroing if count is not constant | |
| 575 // or it is >= BlockZeroingLowLimit. | |
| 576 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit); | |
| 577 } | |
| 578 | |
| 0 | 579 // **************************************************************************** |
| 580 | |
| 581 // REQUIRED FUNCTIONALITY | |
| 582 | |
| 583 // !!!!! Special hack to get all type of calls to specify the byte offset | |
| 584 // from the start of the call to the point where the return address | |
| 585 // will point. | |
| 586 // The "return address" is the address of the call instruction, plus 8. | |
| 587 | |
| 588 int MachCallStaticJavaNode::ret_addr_offset() { | |
| 1567 | 589 int offset = NativeCall::instruction_size; // call; delay slot |
| 590 if (_method_handle_invoke) | |
| 591 offset += 4; // restore SP | |
| 592 return offset; | |
| 0 | 593 } |
| 594 | |
| 595 int MachCallDynamicJavaNode::ret_addr_offset() { | |
| 596 int vtable_index = this->_vtable_index; | |
| 597 if (vtable_index < 0) { | |
| 598 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
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599 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
| 0 | 600 return (NativeMovConstReg::instruction_size + |
| 601 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
| 602 } else { | |
| 603 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
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604 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
| 0 | 605 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); |
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606 int klass_load_size; |
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607 if (UseCompressedClassPointers) { |
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608 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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609 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; |
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610 } else { |
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611 klass_load_size = 1*BytesPerInstWord; |
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612 } |
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613 if (Assembler::is_simm13(v_off)) { |
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614 return klass_load_size + |
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615 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
| 0 | 616 NativeCall::instruction_size); // call; delay slot |
| 617 } else { | |
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618 return klass_load_size + |
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619 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
| 0 | 620 NativeCall::instruction_size); // call; delay slot |
| 621 } | |
| 622 } | |
| 623 } | |
| 624 | |
| 625 int MachCallRuntimeNode::ret_addr_offset() { | |
| 626 #ifdef _LP64 | |
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627 if (MacroAssembler::is_far_target(entry_point())) { |
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628 return NativeFarCall::instruction_size; |
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629 } else { |
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630 return NativeCall::instruction_size; |
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631 } |
| 0 | 632 #else |
| 633 return NativeCall::instruction_size; // call; delay slot | |
| 634 #endif | |
| 635 } | |
| 636 | |
| 637 // Indicate if the safepoint node needs the polling page as an input. | |
| 638 // Since Sparc does not have absolute addressing, it does. | |
| 639 bool SafePointNode::needs_polling_address_input() { | |
| 640 return true; | |
| 641 } | |
| 642 | |
| 643 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
| 644 void emit_break(CodeBuffer &cbuf) { | |
| 645 MacroAssembler _masm(&cbuf); | |
| 646 __ breakpoint_trap(); | |
| 647 } | |
| 648 | |
| 649 #ifndef PRODUCT | |
| 650 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 651 st->print("TA"); | |
| 652 } | |
| 653 #endif | |
| 654 | |
| 655 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 656 emit_break(cbuf); | |
| 657 } | |
| 658 | |
| 659 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
| 660 return MachNode::size(ra_); | |
| 661 } | |
| 662 | |
| 663 // Traceable jump | |
| 664 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
| 665 MacroAssembler _masm(&cbuf); | |
| 666 Register rdest = reg_to_register_object(jump_target); | |
| 667 __ JMP(rdest, 0); | |
| 668 __ delayed()->nop(); | |
| 669 } | |
| 670 | |
| 671 // Traceable jump and set exception pc | |
| 672 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
| 673 MacroAssembler _masm(&cbuf); | |
| 674 Register rdest = reg_to_register_object(jump_target); | |
| 675 __ JMP(rdest, 0); | |
| 676 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
| 677 } | |
| 678 | |
| 679 void emit_nop(CodeBuffer &cbuf) { | |
| 680 MacroAssembler _masm(&cbuf); | |
| 681 __ nop(); | |
| 682 } | |
| 683 | |
| 684 void emit_illtrap(CodeBuffer &cbuf) { | |
| 685 MacroAssembler _masm(&cbuf); | |
| 686 __ illtrap(0); | |
| 687 } | |
| 688 | |
| 689 | |
| 690 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 691 assert(n->rule() != loadUB_rule, ""); | |
| 692 | |
| 693 intptr_t offset = 0; | |
| 694 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
| 695 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
| 696 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
| 697 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
| 698 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 699 atype = atype->add_offset(offset); | |
| 700 assert(disp32 == offset, "wrong disp32"); | |
| 701 return atype->_offset; | |
| 702 } | |
| 703 | |
| 704 | |
| 705 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 706 assert(n->rule() != loadUB_rule, ""); | |
| 707 | |
| 708 intptr_t offset = 0; | |
| 709 Node* addr = n->in(2); | |
| 710 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 711 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
| 712 Node* a = addr->in(2/*AddPNode::Address*/); | |
| 713 Node* o = addr->in(3/*AddPNode::Offset*/); | |
| 714 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
| 715 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
| 716 assert(atype->isa_oop_ptr(), "still an oop"); | |
| 717 } | |
| 718 offset = atype->is_ptr()->_offset; | |
| 719 if (offset != Type::OffsetBot) offset += disp32; | |
| 720 return offset; | |
| 721 } | |
| 722 | |
| 2008 | 723 static inline jdouble replicate_immI(int con, int count, int width) { |
| 724 // Load a constant replicated "count" times with width "width" | |
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725 assert(count*width == 8 && width <= 4, "sanity"); |
| 2008 | 726 int bit_width = width * 8; |
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727 jlong val = con; |
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728 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits |
| 2008 | 729 for (int i = 0; i < count - 1; i++) { |
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730 val |= (val << bit_width); |
| 2008 | 731 } |
| 732 jdouble dval = *((jdouble*) &val); // coerce to double type | |
| 733 return dval; | |
| 734 } | |
| 735 | |
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736 static inline jdouble replicate_immF(float con) { |
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737 // Replicate float con 2 times and pack into vector. |
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738 int val = *((int*)&con); |
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739 jlong lval = val; |
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740 lval = (lval << 32) | (lval & 0xFFFFFFFFl); |
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741 jdouble dval = *((jdouble*) &lval); // coerce to double type |
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742 return dval; |
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743 } |
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744 |
| 0 | 745 // Standard Sparc opcode form2 field breakdown |
| 746 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
| 747 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
| 748 int op = (f30 << 30) | | |
| 749 (f29 << 29) | | |
| 750 (f25 << 25) | | |
| 751 (f22 << 22) | | |
| 752 (f20 << 20) | | |
| 753 (f19 << 19) | | |
| 754 (f0 << 0); | |
| 1748 | 755 cbuf.insts()->emit_int32(op); |
| 0 | 756 } |
| 757 | |
| 758 // Standard Sparc opcode form2 field breakdown | |
| 759 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
| 760 f0 >>= 10; // Drop 10 bits | |
| 761 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
| 762 int op = (f30 << 30) | | |
| 763 (f25 << 25) | | |
| 764 (f22 << 22) | | |
| 765 (f0 << 0); | |
| 1748 | 766 cbuf.insts()->emit_int32(op); |
| 0 | 767 } |
| 768 | |
| 769 // Standard Sparc opcode form3 field breakdown | |
| 770 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
| 771 int op = (f30 << 30) | | |
| 772 (f25 << 25) | | |
| 773 (f19 << 19) | | |
| 774 (f14 << 14) | | |
| 775 (f5 << 5) | | |
| 776 (f0 << 0); | |
| 1748 | 777 cbuf.insts()->emit_int32(op); |
| 0 | 778 } |
| 779 | |
| 780 // Standard Sparc opcode form3 field breakdown | |
| 781 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
| 782 simm13 &= (1<<13)-1; // Mask to 13 bits | |
| 783 int op = (f30 << 30) | | |
| 784 (f25 << 25) | | |
| 785 (f19 << 19) | | |
| 786 (f14 << 14) | | |
| 787 (1 << 13) | // bit to indicate immediate-mode | |
| 788 (simm13<<0); | |
| 1748 | 789 cbuf.insts()->emit_int32(op); |
| 0 | 790 } |
| 791 | |
| 792 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
| 793 simm10 &= (1<<10)-1; // Mask to 10 bits | |
| 794 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
| 795 } | |
| 796 | |
| 797 #ifdef ASSERT | |
| 798 // Helper function for VerifyOops in emit_form3_mem_reg | |
| 799 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
| 800 warning("VerifyOops encountered unexpected instruction:"); | |
| 801 n->dump(2); | |
| 802 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
| 803 } | |
| 804 #endif | |
| 805 | |
| 806 | |
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807 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary, |
| 0 | 808 int src1_enc, int disp32, int src2_enc, int dst_enc) { |
| 809 | |
| 810 #ifdef ASSERT | |
| 811 // The following code implements the +VerifyOops feature. | |
| 812 // It verifies oop values which are loaded into or stored out of | |
| 813 // the current method activation. +VerifyOops complements techniques | |
| 814 // like ScavengeALot, because it eagerly inspects oops in transit, | |
| 815 // as they enter or leave the stack, as opposed to ScavengeALot, | |
| 816 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
| 817 // For this reason, +VerifyOops can sometimes detect bugs very close | |
| 818 // to their point of creation. It can also serve as a cross-check | |
| 819 // on the validity of oop maps, when used toegether with ScavengeALot. | |
| 820 | |
| 821 // It would be good to verify oops at other points, especially | |
| 822 // when an oop is used as a base pointer for a load or store. | |
| 823 // This is presently difficult, because it is hard to know when | |
| 824 // a base address is biased or not. (If we had such information, | |
| 825 // it would be easy and useful to make a two-argument version of | |
| 826 // verify_oop which unbiases the base, and performs verification.) | |
| 827 | |
| 828 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
| 829 bool is_verified_oop_base = false; | |
| 830 bool is_verified_oop_load = false; | |
| 831 bool is_verified_oop_store = false; | |
| 832 int tmp_enc = -1; | |
| 833 if (VerifyOops && src1_enc != R_SP_enc) { | |
| 834 // classify the op, mainly for an assert check | |
| 835 int st_op = 0, ld_op = 0; | |
| 836 switch (primary) { | |
| 837 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
| 838 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
| 839 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
| 840 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
| 841 case Assembler::std_op3: st_op = Op_StoreL; break; | |
| 842 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
| 843 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
| 844 | |
| 845 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
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846 case Assembler::ldub_op3: ld_op = Op_LoadUB; break; |
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847 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
| 0 | 848 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
| 849 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
| 850 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
| 851 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
| 852 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
| 853 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
| 854 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
| 855 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
| 856 | |
| 857 default: ShouldNotReachHere(); | |
| 858 } | |
| 859 if (tertiary == REGP_OP) { | |
| 860 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
| 861 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
| 862 else ShouldNotReachHere(); | |
| 863 if (st_op) { | |
| 864 // a store | |
| 865 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 866 Node* n2 = n->in(3); | |
| 867 if (n2 != NULL) { | |
| 868 const Type* t = n2->bottom_type(); | |
| 869 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 870 } | |
| 871 } else { | |
| 872 // a load | |
| 873 const Type* t = n->bottom_type(); | |
| 874 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 875 } | |
| 876 } | |
| 877 | |
| 878 if (ld_op) { | |
| 879 // a Load | |
| 880 // inputs are (0:control, 1:memory, 2:address) | |
| 881 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
| 882 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
| 883 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
| 884 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
| 885 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
| 886 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
| 887 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
| 888 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
| 889 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
| 890 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
| 891 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
| 892 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
| 893 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
| 3898 | 894 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) && |
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895 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) && |
| 0 | 896 !(n->rule() == loadUB_rule)) { |
| 897 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
| 898 } | |
| 899 } else if (st_op) { | |
| 900 // a Store | |
| 901 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 902 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
| 903 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
| 904 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
| 905 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
| 906 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
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907 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) && |
| 0 | 908 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { |
| 909 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
| 910 } | |
| 911 } | |
| 912 | |
| 913 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
| 914 Node* addr = n->in(2); | |
| 915 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
| 916 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
| 917 if (atype != NULL) { | |
| 918 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
| 919 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
| 920 if (offset != offset_2) { | |
| 921 get_offset_from_base(n, atype, disp32); | |
| 922 get_offset_from_base_2(n, atype, disp32); | |
| 923 } | |
| 924 assert(offset == offset_2, "different offsets"); | |
| 925 if (offset == disp32) { | |
| 926 // we now know that src1 is a true oop pointer | |
| 927 is_verified_oop_base = true; | |
| 928 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
| 929 if( primary == Assembler::ldd_op3 ) { | |
| 930 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
| 931 } else { | |
| 932 tmp_enc = dst_enc; | |
| 933 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
| 934 assert(src1_enc != dst_enc, ""); | |
| 935 } | |
| 936 } | |
| 937 } | |
| 938 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
| 939 || offset == oopDesc::mark_offset_in_bytes())) { | |
| 940 // loading the mark should not be allowed either, but | |
| 941 // we don't check this since it conflicts with InlineObjectHash | |
| 942 // usage of LoadINode to get the mark. We could keep the | |
| 943 // check if we create a new LoadMarkNode | |
| 944 // but do not verify the object before its header is initialized | |
| 945 ShouldNotReachHere(); | |
| 946 } | |
| 947 } | |
| 948 } | |
| 949 } | |
| 950 } | |
| 951 #endif | |
| 952 | |
| 953 uint instr; | |
| 954 instr = (Assembler::ldst_op << 30) | |
| 955 | (dst_enc << 25) | |
| 956 | (primary << 19) | |
| 957 | (src1_enc << 14); | |
| 958 | |
| 959 uint index = src2_enc; | |
| 960 int disp = disp32; | |
| 961 | |
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962 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) { |
| 0 | 963 disp += STACK_BIAS; |
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964 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not |
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965 if (!Assembler::is_simm13(disp)) { |
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966 ra->C->record_method_not_compilable("unable to handle large constant offsets"); |
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967 return; |
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968 } |
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969 } |
| 0 | 970 |
| 971 // We should have a compiler bailout here rather than a guarantee. | |
| 972 // Better yet would be some mechanism to handle variable-size matches correctly. | |
| 973 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
| 974 | |
| 975 if( disp == 0 ) { | |
| 976 // use reg-reg form | |
| 977 // bit 13 is already zero | |
| 978 instr |= index; | |
| 979 } else { | |
| 980 // use reg-imm form | |
| 981 instr |= 0x00002000; // set bit 13 to one | |
| 982 instr |= disp & 0x1FFF; | |
| 983 } | |
| 984 | |
| 1748 | 985 cbuf.insts()->emit_int32(instr); |
| 0 | 986 |
| 987 #ifdef ASSERT | |
| 988 { | |
| 989 MacroAssembler _masm(&cbuf); | |
| 990 if (is_verified_oop_base) { | |
| 991 __ verify_oop(reg_to_register_object(src1_enc)); | |
| 992 } | |
| 993 if (is_verified_oop_store) { | |
| 994 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 995 } | |
| 996 if (tmp_enc != -1) { | |
| 997 __ mov(O7, reg_to_register_object(tmp_enc)); | |
| 998 } | |
| 999 if (is_verified_oop_load) { | |
| 1000 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 1001 } | |
| 1002 } | |
| 1003 #endif | |
| 1004 } | |
| 1005 | |
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1006 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) { |
| 0 | 1007 // The method which records debug information at every safepoint |
| 1008 // expects the call to be the first instruction in the snippet as | |
| 1009 // it creates a PcDesc structure which tracks the offset of a call | |
| 1010 // from the start of the codeBlob. This offset is computed as | |
| 1011 // code_end() - code_begin() of the code which has been emitted | |
| 1012 // so far. | |
| 1013 // In this particular case we have skirted around the problem by | |
| 1014 // putting the "mov" instruction in the delay slot but the problem | |
| 1015 // may bite us again at some other point and a cleaner/generic | |
| 1016 // solution using relocations would be needed. | |
| 1017 MacroAssembler _masm(&cbuf); | |
| 1018 __ set_inst_mark(); | |
| 1019 | |
| 1020 // We flush the current window just so that there is a valid stack copy | |
| 1021 // the fact that the current window becomes active again instantly is | |
| 1022 // not a problem there is nothing live in it. | |
| 1023 | |
| 1024 #ifdef ASSERT | |
| 1025 int startpos = __ offset(); | |
| 1026 #endif /* ASSERT */ | |
| 1027 | |
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1028 __ call((address)entry_point, rtype); |
| 0 | 1029 |
| 1030 if (preserve_g2) __ delayed()->mov(G2, L7); | |
| 1031 else __ delayed()->nop(); | |
| 1032 | |
| 1033 if (preserve_g2) __ mov(L7, G2); | |
| 1034 | |
| 1035 #ifdef ASSERT | |
| 1036 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
| 1037 #ifdef _LP64 | |
| 1038 // Trash argument dump slots. | |
| 1039 __ set(0xb0b8ac0db0b8ac0d, G1); | |
| 1040 __ mov(G1, G5); | |
| 1041 __ stx(G1, SP, STACK_BIAS + 0x80); | |
| 1042 __ stx(G1, SP, STACK_BIAS + 0x88); | |
| 1043 __ stx(G1, SP, STACK_BIAS + 0x90); | |
| 1044 __ stx(G1, SP, STACK_BIAS + 0x98); | |
| 1045 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
| 1046 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
| 1047 #else // _LP64 | |
| 1048 // this is also a native call, so smash the first 7 stack locations, | |
| 1049 // and the various registers | |
| 1050 | |
| 1051 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
| 1052 // while [SP+0x44..0x58] are the argument dump slots. | |
| 1053 __ set((intptr_t)0xbaadf00d, G1); | |
| 1054 __ mov(G1, G5); | |
| 1055 __ sllx(G1, 32, G1); | |
| 1056 __ or3(G1, G5, G1); | |
| 1057 __ mov(G1, G5); | |
| 1058 __ stx(G1, SP, 0x40); | |
| 1059 __ stx(G1, SP, 0x48); | |
| 1060 __ stx(G1, SP, 0x50); | |
| 1061 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
| 1062 #endif // _LP64 | |
| 1063 } | |
| 1064 #endif /*ASSERT*/ | |
| 1065 } | |
| 1066 | |
| 1067 //============================================================================= | |
| 1068 // REQUIRED FUNCTIONALITY for encoding | |
| 1069 void emit_lo(CodeBuffer &cbuf, int val) { } | |
| 1070 void emit_hi(CodeBuffer &cbuf, int val) { } | |
| 1071 | |
| 1072 | |
| 1073 //============================================================================= | |
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1074 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask(); |
| 2008 | 1075 |
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1076 int Compile::ConstantTable::calculate_table_base_offset() const { |
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1077 if (UseRDPCForConstantTableBase) { |
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1078 // The table base offset might be less but then it fits into |
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1079 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit). |
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1080 return Assembler::min_simm13(); |
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1081 } else { |
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1082 int offset = -(size() / 2); |
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1083 if (!Assembler::is_simm13(offset)) { |
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1084 offset = Assembler::min_simm13(); |
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1085 } |
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1086 return offset; |
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1087 } |
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1088 } |
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1089 |
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1090 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } |
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1091 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { |
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1092 ShouldNotReachHere(); |
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1093 } |
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1094 |
| 2008 | 1095 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 1096 Compile* C = ra_->C; | |
| 1097 Compile::ConstantTable& constant_table = C->constant_table(); | |
| 1098 MacroAssembler _masm(&cbuf); | |
| 1099 | |
| 1100 Register r = as_Register(ra_->get_encode(this)); | |
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1101 CodeSection* consts_section = __ code()->consts(); |
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1102 int consts_size = consts_section->align_at_start(consts_section->size()); |
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1103 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); |
| 2008 | 1104 |
| 1105 if (UseRDPCForConstantTableBase) { | |
| 1106 // For the following RDPC logic to work correctly the consts | |
| 1107 // section must be allocated right before the insts section. This | |
| 1108 // assert checks for that. The layout and the SECT_* constants | |
| 1109 // are defined in src/share/vm/asm/codeBuffer.hpp. | |
| 1110 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); | |
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1111 int insts_offset = __ offset(); |
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1112 |
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1113 // Layout: |
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1114 // |
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1115 // |----------- consts section ------------|----------- insts section -----------... |
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1116 // |------ constant table -----|- padding -|------------------x---- |
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1117 // \ current PC (RDPC instruction) |
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1118 // |<------------- consts_size ----------->|<- insts_offset ->| |
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1119 // \ table base |
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1120 // The table base offset is later added to the load displacement |
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1121 // so it has to be negative. |
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1122 int table_base_offset = -(consts_size + insts_offset); |
| 2008 | 1123 int disp; |
| 1124 | |
| 1125 // If the displacement from the current PC to the constant table | |
| 1126 // base fits into simm13 we set the constant table base to the | |
| 1127 // current PC. | |
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1128 if (Assembler::is_simm13(table_base_offset)) { |
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1129 constant_table.set_table_base_offset(table_base_offset); |
| 2008 | 1130 disp = 0; |
| 1131 } else { | |
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1132 // Otherwise we set the constant table base offset to the |
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1133 // maximum negative displacement of load instructions to keep |
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1134 // the disp as small as possible: |
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1135 // |
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1136 // |<------------- consts_size ----------->|<- insts_offset ->| |
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1137 // |<--------- min_simm13 --------->|<-------- disp --------->| |
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1138 // \ table base |
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1139 table_base_offset = Assembler::min_simm13(); |
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1140 constant_table.set_table_base_offset(table_base_offset); |
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1141 disp = (consts_size + insts_offset) + table_base_offset; |
| 2008 | 1142 } |
| 1143 | |
| 1144 __ rdpc(r); | |
| 1145 | |
| 1146 if (disp != 0) { | |
| 1147 assert(r != O7, "need temporary"); | |
| 1148 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); | |
| 1149 } | |
| 1150 } | |
| 1151 else { | |
| 1152 // Materialize the constant table base. | |
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1153 address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); |
| 2008 | 1154 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); |
| 1155 AddressLiteral base(baseaddr, rspec); | |
| 1156 __ set(base, r); | |
| 1157 } | |
| 1158 } | |
| 1159 | |
| 1160 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { | |
| 1161 if (UseRDPCForConstantTableBase) { | |
| 1162 // This is really the worst case but generally it's only 1 instruction. | |
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1163 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; |
| 2008 | 1164 } else { |
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1165 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; |
| 2008 | 1166 } |
| 1167 } | |
| 1168 | |
| 1169 #ifndef PRODUCT | |
| 1170 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 1171 char reg[128]; | |
| 1172 ra_->dump_register(this, reg); | |
| 1173 if (UseRDPCForConstantTableBase) { | |
| 1174 st->print("RDPC %s\t! constant table base", reg); | |
| 1175 } else { | |
| 1176 st->print("SET &constanttable,%s\t! constant table base", reg); | |
| 1177 } | |
| 1178 } | |
| 1179 #endif | |
| 1180 | |
| 1181 | |
| 1182 //============================================================================= | |
| 0 | 1183 |
| 1184 #ifndef PRODUCT | |
| 1185 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1186 Compile* C = ra_->C; | |
| 1187 | |
| 1188 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1189 st->print_cr("NOP"); st->print("\t"); | |
| 1190 } | |
| 1191 | |
| 1192 if( VerifyThread ) { | |
| 1193 st->print_cr("Verify_Thread"); st->print("\t"); | |
| 1194 } | |
| 1195 | |
| 1196 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1197 | |
| 1198 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1199 // We require that their callers must bang for them. But be careful, because | |
| 1200 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1201 // stack. But the stack safety zone should account for that. | |
| 1202 // See bugs 4446381, 4468289, 4497237. | |
| 1203 if (C->need_stack_bang(framesize)) { | |
| 1204 st->print_cr("! stack bang"); st->print("\t"); | |
| 1205 } | |
| 1206 | |
| 1207 if (Assembler::is_simm13(-framesize)) { | |
| 1208 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
| 1209 } else { | |
| 1210 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1211 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1212 st->print ("SAVE R_SP,R_G3,R_SP"); | |
| 1213 } | |
| 1214 | |
| 1215 } | |
| 1216 #endif | |
| 1217 | |
| 1218 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1219 Compile* C = ra_->C; | |
| 1220 MacroAssembler _masm(&cbuf); | |
| 1221 | |
| 1222 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1223 __ nop(); | |
| 1224 } | |
| 1225 | |
| 1226 __ verify_thread(); | |
| 1227 | |
| 1228 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1229 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
| 1230 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
| 1231 | |
| 1232 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1233 // We require that their callers must bang for them. But be careful, because | |
| 1234 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1235 // stack. But the stack safety zone should account for that. | |
| 1236 // See bugs 4446381, 4468289, 4497237. | |
| 1237 if (C->need_stack_bang(framesize)) { | |
| 1238 __ generate_stack_overflow_check(framesize); | |
| 1239 } | |
| 1240 | |
| 1241 if (Assembler::is_simm13(-framesize)) { | |
| 1242 __ save(SP, -framesize, SP); | |
| 1243 } else { | |
| 1244 __ sethi(-framesize & ~0x3ff, G3); | |
| 1245 __ add(G3, -framesize & 0x3ff, G3); | |
| 1246 __ save(SP, G3, SP); | |
| 1247 } | |
| 1248 C->set_frame_complete( __ offset() ); | |
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1249 |
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1250 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) { |
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1251 // NOTE: We set the table base offset here because users might be |
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1252 // emitted before MachConstantBaseNode. |
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1253 Compile::ConstantTable& constant_table = C->constant_table(); |
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1254 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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1255 } |
| 0 | 1256 } |
| 1257 | |
| 1258 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 1259 return MachNode::size(ra_); | |
| 1260 } | |
| 1261 | |
| 1262 int MachPrologNode::reloc() const { | |
| 1263 return 10; // a large enough number | |
| 1264 } | |
| 1265 | |
| 1266 //============================================================================= | |
| 1267 #ifndef PRODUCT | |
| 1268 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1269 Compile* C = ra_->C; | |
| 1270 | |
| 1271 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 1272 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
| 1273 #ifdef _LP64 | |
| 1274 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1275 #else | |
| 1276 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1277 #endif | |
| 1278 } | |
| 1279 | |
| 1280 if( do_polling() ) | |
| 1281 st->print("RET\n\t"); | |
| 1282 | |
| 1283 st->print("RESTORE"); | |
| 1284 } | |
| 1285 #endif | |
| 1286 | |
| 1287 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1288 MacroAssembler _masm(&cbuf); | |
| 1289 Compile* C = ra_->C; | |
| 1290 | |
| 1291 __ verify_thread(); | |
| 1292 | |
| 1293 // If this does safepoint polling, then do it here | |
| 1294 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 727 | 1295 AddressLiteral polling_page(os::get_polling_page()); |
| 1296 __ sethi(polling_page, L0); | |
| 0 | 1297 __ relocate(relocInfo::poll_return_type); |
| 1298 __ ld_ptr( L0, 0, G0 ); | |
| 1299 } | |
| 1300 | |
| 1301 // If this is a return, then stuff the restore in the delay slot | |
| 1302 if( do_polling() ) { | |
| 1303 __ ret(); | |
| 1304 __ delayed()->restore(); | |
| 1305 } else { | |
| 1306 __ restore(); | |
| 1307 } | |
| 1308 } | |
| 1309 | |
| 1310 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 1311 return MachNode::size(ra_); | |
| 1312 } | |
| 1313 | |
| 1314 int MachEpilogNode::reloc() const { | |
| 1315 return 16; // a large enough number | |
| 1316 } | |
| 1317 | |
| 1318 const Pipeline * MachEpilogNode::pipeline() const { | |
| 1319 return MachNode::pipeline_class(); | |
| 1320 } | |
| 1321 | |
| 1322 int MachEpilogNode::safepoint_offset() const { | |
| 1323 assert( do_polling(), "no return for this epilog node"); | |
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1324 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; |
| 0 | 1325 } |
| 1326 | |
| 1327 //============================================================================= | |
| 1328 | |
| 1329 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
| 1330 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
| 1331 static enum RC rc_class( OptoReg::Name reg ) { | |
| 1332 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 1333 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 1334 VMReg r = OptoReg::as_VMReg(reg); | |
| 1335 if (r->is_Register()) return rc_int; | |
| 1336 assert(r->is_FloatRegister(), "must be"); | |
| 1337 return rc_float; | |
| 1338 } | |
| 1339 | |
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1340 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { |
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1341 if (cbuf) { |
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1342 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); |
| 0 | 1343 } |
| 1344 #ifndef PRODUCT | |
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1345 else if (!do_size) { |
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1346 if (size != 0) st->print("\n\t"); |
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1347 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); |
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1348 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); |
| 0 | 1349 } |
| 1350 #endif | |
| 1351 return size+4; | |
| 1352 } | |
| 1353 | |
| 1354 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
| 1355 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
| 1356 #ifndef PRODUCT | |
| 1357 else if( !do_size ) { | |
| 1358 if( size != 0 ) st->print("\n\t"); | |
| 1359 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
| 1360 } | |
| 1361 #endif | |
| 1362 return size+4; | |
| 1363 } | |
| 1364 | |
| 1365 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
| 1366 PhaseRegAlloc *ra_, | |
| 1367 bool do_size, | |
| 1368 outputStream* st ) const { | |
| 1369 // Get registers to move | |
| 1370 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1371 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1372 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 1373 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 1374 | |
| 1375 enum RC src_second_rc = rc_class(src_second); | |
| 1376 enum RC src_first_rc = rc_class(src_first); | |
| 1377 enum RC dst_second_rc = rc_class(dst_second); | |
| 1378 enum RC dst_first_rc = rc_class(dst_first); | |
| 1379 | |
| 1380 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 1381 | |
| 1382 // Generate spill code! | |
| 1383 int size = 0; | |
| 1384 | |
| 1385 if( src_first == dst_first && src_second == dst_second ) | |
| 1386 return size; // Self copy, no move | |
| 1387 | |
| 1388 // -------------------------------------- | |
| 1389 // Check for mem-mem move. Load into unused float registers and fall into | |
| 1390 // the float-store case. | |
| 1391 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1392 int offset = ra_->reg2offset(src_first); | |
| 1393 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1394 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
| 1395 src_second = OptoReg::Name(R_F31_num); | |
| 1396 src_second_rc = rc_float; | |
| 1397 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
| 1398 } else { | |
| 1399 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1400 } | |
| 1401 src_first = OptoReg::Name(R_F30_num); | |
| 1402 src_first_rc = rc_float; | |
| 1403 } | |
| 1404 | |
| 1405 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
| 1406 int offset = ra_->reg2offset(src_second); | |
| 1407 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
| 1408 src_second = OptoReg::Name(R_F31_num); | |
| 1409 src_second_rc = rc_float; | |
| 1410 } | |
| 1411 | |
| 1412 // -------------------------------------- | |
| 1413 // Check for float->int copy; requires a trip through memory | |
| 3804 | 1414 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { |
| 0 | 1415 int offset = frame::register_save_words*wordSize; |
| 3804 | 1416 if (cbuf) { |
| 0 | 1417 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); |
| 1418 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1419 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1420 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
| 1421 } | |
| 1422 #ifndef PRODUCT | |
| 3804 | 1423 else if (!do_size) { |
| 1424 if (size != 0) st->print("\n\t"); | |
| 0 | 1425 st->print( "SUB R_SP,16,R_SP\n"); |
| 1426 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1427 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1428 st->print("\tADD R_SP,16,R_SP\n"); | |
| 1429 } | |
| 1430 #endif | |
| 1431 size += 16; | |
| 1432 } | |
| 1433 | |
| 3804 | 1434 // Check for float->int copy on T4 |
| 1435 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { | |
| 1436 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1437 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
| 1438 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st); | |
| 1439 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st); | |
| 1440 } | |
| 1441 // Check for int->float copy on T4 | |
| 1442 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { | |
| 1443 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1444 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
| 1445 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st); | |
| 1446 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st); | |
| 1447 } | |
| 1448 | |
| 0 | 1449 // -------------------------------------- |
| 1450 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
| 1451 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
| 1452 // hardware does the flop for me. Doubles are always aligned, so no problem | |
| 1453 // there. Misaligned sources only come from native-long-returns (handled | |
| 1454 // special below). | |
| 1455 #ifndef _LP64 | |
| 1456 if( src_first_rc == rc_int && // source is already big-endian | |
| 1457 src_second_rc != rc_bad && // 64-bit move | |
| 1458 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
| 1459 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
| 1460 // Do the big-endian flop. | |
| 1461 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
| 1462 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
| 1463 } | |
| 1464 #endif | |
| 1465 | |
| 1466 // -------------------------------------- | |
| 1467 // Check for integer reg-reg copy | |
| 1468 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
| 1469 #ifndef _LP64 | |
| 1470 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
| 1471 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1472 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1473 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1474 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
| 1475 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
| 1476 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
| 1477 if( cbuf ) { | |
| 1478 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
| 1479 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
| 1480 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
| 1481 #ifndef PRODUCT | |
| 1482 } else if( !do_size ) { | |
| 1483 if( size != 0 ) st->print("\n\t"); | |
| 1484 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
| 1485 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
| 1486 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
| 1487 #endif | |
| 1488 } | |
| 1489 return size+12; | |
| 1490 } | |
| 1491 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
| 1492 // returning a long value in I0/I1 | |
| 1493 // a SpillCopy must be able to target a return instruction's reg_class | |
| 1494 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1495 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1496 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1497 OptoReg::Name tdest = dst_first; | |
| 1498 | |
| 1499 if (src_first == dst_first) { | |
| 1500 tdest = OptoReg::Name(R_O7_num); | |
| 1501 size += 4; | |
| 1502 } | |
| 1503 | |
| 1504 if( cbuf ) { | |
| 1505 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
| 1506 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
| 1507 // ShrL_reg_imm6 | |
| 1508 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
| 1509 // ShrR_reg_imm6 src, 0, dst | |
| 1510 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
| 1511 if (tdest != dst_first) { | |
| 1512 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
| 1513 } | |
| 1514 } | |
| 1515 #ifndef PRODUCT | |
| 1516 else if( !do_size ) { | |
| 1517 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
| 1518 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
| 1519 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
| 1520 if (tdest != dst_first) { | |
| 1521 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
| 1522 } | |
| 1523 } | |
| 1524 #endif // PRODUCT | |
| 1525 return size+8; | |
| 1526 } | |
| 1527 #endif // !_LP64 | |
| 1528 // Else normal reg-reg copy | |
| 1529 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
| 1530 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
| 1531 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
| 1532 // This moves an aligned adjacent pair. | |
| 1533 // See if we are done. | |
| 1534 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
| 1535 return size; | |
| 1536 } | |
| 1537 | |
| 1538 // Check for integer store | |
| 1539 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
| 1540 int offset = ra_->reg2offset(dst_first); | |
| 1541 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1542 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1543 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
| 1544 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
| 1545 } | |
| 1546 | |
| 1547 // Check for integer load | |
| 1548 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
| 1549 int offset = ra_->reg2offset(src_first); | |
| 1550 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1551 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1552 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
| 1553 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1554 } | |
| 1555 | |
| 1556 // Check for float reg-reg copy | |
| 1557 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1558 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1559 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1560 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
| 1561 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
| 1562 } | |
| 1563 | |
| 1564 // Check for float store | |
| 1565 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
| 1566 int offset = ra_->reg2offset(dst_first); | |
| 1567 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1568 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1569 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
| 1570 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1571 } | |
| 1572 | |
| 1573 // Check for float load | |
| 1574 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1575 int offset = ra_->reg2offset(src_first); | |
| 1576 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1577 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1578 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
| 1579 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1580 } | |
| 1581 | |
| 1582 // -------------------------------------------------------------------- | |
| 1583 // Check for hi bits still needing moving. Only happens for misaligned | |
| 1584 // arguments to native calls. | |
| 1585 if( src_second == dst_second ) | |
| 1586 return size; // Self copy; no move | |
| 1587 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1588 | |
| 1589 #ifndef _LP64 | |
| 1590 // In the LP64 build, all registers can be moved as aligned/adjacent | |
| 605 | 1591 // pairs, so there's never any need to move the high bits separately. |
| 0 | 1592 // The 32-bit builds have to deal with the 32-bit ABI which can force |
| 1593 // all sorts of silly alignment problems. | |
| 1594 | |
| 1595 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
| 1596 // 32-bits of a 64-bit register, but are needed in low bits of another | |
| 1597 // register (else it's a hi-bits-to-hi-bits copy which should have | |
| 1598 // happened already as part of a 64-bit move) | |
| 1599 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
| 1600 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
| 1601 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
| 1602 // Shift src_second down to dst_second's low bits. | |
| 1603 if( cbuf ) { | |
| 1604 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1605 #ifndef PRODUCT | |
| 1606 } else if( !do_size ) { | |
| 1607 if( size != 0 ) st->print("\n\t"); | |
| 1608 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
| 1609 #endif | |
| 1610 } | |
| 1611 return size+4; | |
| 1612 } | |
| 1613 | |
| 1614 // Check for high word integer store. Must down-shift the hi bits | |
| 1615 // into a temp register, then fall into the case of storing int bits. | |
| 1616 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
| 1617 // Shift src_second down to dst_second's low bits. | |
| 1618 if( cbuf ) { | |
| 1619 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1620 #ifndef PRODUCT | |
| 1621 } else if( !do_size ) { | |
| 1622 if( size != 0 ) st->print("\n\t"); | |
| 1623 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
| 1624 #endif | |
| 1625 } | |
| 1626 size+=4; | |
| 1627 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
| 1628 } | |
| 1629 | |
| 1630 // Check for high word integer load | |
| 1631 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
| 1632 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
| 1633 | |
| 1634 // Check for high word integer store | |
| 1635 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
| 1636 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
| 1637 | |
| 1638 // Check for high word float store | |
| 1639 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
| 1640 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
| 1641 | |
| 1642 #endif // !_LP64 | |
| 1643 | |
| 1644 Unimplemented(); | |
| 1645 } | |
| 1646 | |
| 1647 #ifndef PRODUCT | |
| 1648 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1649 implementation( NULL, ra_, false, st ); | |
| 1650 } | |
| 1651 #endif | |
| 1652 | |
| 1653 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1654 implementation( &cbuf, ra_, false, NULL ); | |
| 1655 } | |
| 1656 | |
| 1657 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1658 return implementation( NULL, ra_, true, NULL ); | |
| 1659 } | |
| 1660 | |
| 1661 //============================================================================= | |
| 1662 #ifndef PRODUCT | |
| 1663 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 1664 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
| 1665 } | |
| 1666 #endif | |
| 1667 | |
| 1668 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
| 1669 MacroAssembler _masm(&cbuf); | |
| 1670 for(int i = 0; i < _count; i += 1) { | |
| 1671 __ nop(); | |
| 1672 } | |
| 1673 } | |
| 1674 | |
| 1675 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
| 1676 return 4 * _count; | |
| 1677 } | |
| 1678 | |
| 1679 | |
| 1680 //============================================================================= | |
| 1681 #ifndef PRODUCT | |
| 1682 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1683 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1684 int reg = ra_->get_reg_first(this); | |
| 1685 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
| 1686 } | |
| 1687 #endif | |
| 1688 | |
| 1689 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1690 MacroAssembler _masm(&cbuf); | |
| 1691 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
| 1692 int reg = ra_->get_encode(this); | |
| 1693 | |
| 1694 if (Assembler::is_simm13(offset)) { | |
| 1695 __ add(SP, offset, reg_to_register_object(reg)); | |
| 1696 } else { | |
| 1697 __ set(offset, O7); | |
| 1698 __ add(SP, O7, reg_to_register_object(reg)); | |
| 1699 } | |
| 1700 } | |
| 1701 | |
| 1702 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1703 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
| 1704 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
| 1705 return ra_->C->scratch_emit_size(this); | |
| 1706 } | |
| 1707 | |
| 1708 //============================================================================= | |
| 1709 #ifndef PRODUCT | |
| 1710 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1711 st->print_cr("\nUEP:"); | |
| 1712 #ifdef _LP64 | |
|
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1713 if (UseCompressedClassPointers) { |
|
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1714 assert(Universe::heap() != NULL, "java heap should be initialized"); |
|
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1715 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
|
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1716 if (Universe::narrow_klass_base() != 0) { |
|
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1717 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base"); |
|
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1718 if (Universe::narrow_klass_shift() != 0) { |
|
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1719 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); |
|
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1720 } |
|
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1721 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
|
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1722 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base"); |
|
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1723 } else { |
|
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1724 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); |
|
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1725 } |
|
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1726 } else { |
|
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1727 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
|
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1728 } |
| 0 | 1729 st->print_cr("\tCMP R_G5,R_G3" ); |
| 1730 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1731 #else // _LP64 | |
| 1732 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
| 1733 st->print_cr("\tCMP R_G5,R_G3" ); | |
| 1734 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1735 #endif // _LP64 | |
| 1736 } | |
| 1737 #endif | |
| 1738 | |
| 1739 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1740 MacroAssembler _masm(&cbuf); | |
| 1741 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 1742 Register temp_reg = G3; | |
| 1743 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
| 1744 | |
| 605 | 1745 // Load klass from receiver |
|
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1746 __ load_klass(O0, temp_reg); |
| 0 | 1747 // Compare against expected klass |
| 1748 __ cmp(temp_reg, G5_ic_reg); | |
| 1749 // Branch to miss code, checks xcc or icc depending | |
| 1750 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
| 1751 } | |
| 1752 | |
| 1753 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1754 return MachNode::size(ra_); | |
| 1755 } | |
| 1756 | |
| 1757 | |
| 1758 //============================================================================= | |
| 1759 | |
| 1760 | |
| 1761 // Emit exception handler code. | |
|
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1762 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) { |
| 0 | 1763 Register temp_reg = G3; |
| 1748 | 1764 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); |
| 0 | 1765 MacroAssembler _masm(&cbuf); |
| 1766 | |
| 1767 address base = | |
| 1768 __ start_a_stub(size_exception_handler()); | |
| 1769 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1770 | |
| 1771 int offset = __ offset(); | |
| 1772 | |
| 727 | 1773 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1774 __ delayed()->nop(); |
| 1775 | |
| 1776 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
| 1777 | |
| 1778 __ end_a_stub(); | |
| 1779 | |
| 1780 return offset; | |
| 1781 } | |
| 1782 | |
|
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1783 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { |
| 0 | 1784 // Can't use any of the current frame's registers as we may have deopted |
| 1785 // at a poll and everything (including G3) can be live. | |
| 1786 Register temp_reg = L0; | |
| 727 | 1787 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
| 0 | 1788 MacroAssembler _masm(&cbuf); |
| 1789 | |
| 1790 address base = | |
| 1791 __ start_a_stub(size_deopt_handler()); | |
| 1792 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1793 | |
| 1794 int offset = __ offset(); | |
| 1795 __ save_frame(0); | |
| 727 | 1796 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1797 __ delayed()->restore(); |
| 1798 | |
| 1799 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1800 | |
| 1801 __ end_a_stub(); | |
| 1802 return offset; | |
| 1803 | |
| 1804 } | |
| 1805 | |
| 1806 // Given a register encoding, produce a Integer Register object | |
| 1807 static Register reg_to_register_object(int register_encoding) { | |
| 1808 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
| 1809 return as_Register(register_encoding); | |
| 1810 } | |
| 1811 | |
| 1812 // Given a register encoding, produce a single-precision Float Register object | |
| 1813 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
| 1814 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
| 1815 return as_SingleFloatRegister(register_encoding); | |
| 1816 } | |
| 1817 | |
| 1818 // Given a register encoding, produce a double-precision Float Register object | |
| 1819 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
| 1820 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
| 1821 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
| 1822 return as_DoubleFloatRegister(register_encoding); | |
| 1823 } | |
| 1824 | |
|
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1825 const bool Matcher::match_rule_supported(int opcode) { |
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1826 if (!has_match_rule(opcode)) |
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1827 return false; |
|
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1828 |
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1829 switch (opcode) { |
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1830 case Op_CountLeadingZerosI: |
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1831 case Op_CountLeadingZerosL: |
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1832 case Op_CountTrailingZerosI: |
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1833 case Op_CountTrailingZerosL: |
|
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1834 case Op_PopCountI: |
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1835 case Op_PopCountL: |
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1836 if (!UsePopCountInstruction) |
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1837 return false; |
|
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1838 case Op_CompareAndSwapL: |
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1839 #ifdef _LP64 |
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1840 case Op_CompareAndSwapP: |
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1841 #endif |
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1842 if (!VM_Version::supports_cx8()) |
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1843 return false; |
|
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1844 break; |
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1845 } |
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1846 |
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1847 return true; // Per default match rules are supported. |
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1848 } |
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1849 |
| 0 | 1850 int Matcher::regnum_to_fpu_offset(int regnum) { |
| 1851 return regnum - 32; // The FP registers are in the second chunk | |
| 1852 } | |
| 1853 | |
| 1854 #ifdef ASSERT | |
| 1855 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
| 1856 #endif | |
| 1857 | |
| 1858 // Vector width in bytes | |
|
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1859 const int Matcher::vector_width_in_bytes(BasicType bt) { |
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1860 assert(MaxVectorSize == 8, ""); |
| 0 | 1861 return 8; |
| 1862 } | |
| 1863 | |
| 1864 // Vector ideal reg | |
|
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1865 const int Matcher::vector_ideal_reg(int size) { |
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1866 assert(MaxVectorSize == 8, ""); |
| 0 | 1867 return Op_RegD; |
| 1868 } | |
| 1869 | |
| 6823 | 1870 const int Matcher::vector_shift_count_ideal_reg(int size) { |
| 1871 fatal("vector shift is not supported"); | |
| 1872 return Node::NotAMachineReg; | |
| 1873 } | |
| 1874 | |
|
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1875 // Limits on vector size (number of elements) loaded into vector. |
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1876 const int Matcher::max_vector_size(const BasicType bt) { |
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1877 assert(is_java_primitive(bt), "only primitive type vectors"); |
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1878 return vector_width_in_bytes(bt)/type2aelembytes(bt); |
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1879 } |
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1880 |
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1881 const int Matcher::min_vector_size(const BasicType bt) { |
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1882 return max_vector_size(bt); // Same as max. |
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1883 } |
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1884 |
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1885 // SPARC doesn't support misaligned vectors store/load. |
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1886 const bool Matcher::misaligned_vectors_ok() { |
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1887 return false; |
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1888 } |
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1889 |
| 17670 | 1890 // Current (2013) SPARC platforms need to read original key |
| 1891 // to construct decryption expanded key | |
| 1892 const bool Matcher::pass_original_key_for_aes() { | |
| 1893 return true; | |
| 1894 } | |
| 1895 | |
| 0 | 1896 // USII supports fxtof through the whole range of number, USIII doesn't |
| 1897 const bool Matcher::convL2FSupported(void) { | |
| 1898 return VM_Version::has_fast_fxtof(); | |
| 1899 } | |
| 1900 | |
| 1901 // Is this branch offset short enough that a short branch can be used? | |
| 1902 // | |
| 1903 // NOTE: If the platform does not provide any short branch variants, then | |
| 1904 // this method should return false for offset 0. | |
| 3851 | 1905 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1906 // The passed offset is relative to address of the branch. | |
| 1907 // Don't need to adjust the offset. | |
|
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1908 return UseCBCond && Assembler::is_simm12(offset); |
| 0 | 1909 } |
| 1910 | |
| 1911 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1912 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1913 // Depends on optimizations in MacroAssembler::setx. | |
| 1914 int hi = (int)(value >> 32); | |
| 1915 int lo = (int)(value & ~0); | |
| 1916 return (hi == 0) || (hi == -1) || (lo == 0); | |
| 1917 } | |
| 1918 | |
| 1919 // No scaling for the parameter the ClearArray node. | |
| 1920 const bool Matcher::init_array_count_is_in_bytes = true; | |
| 1921 | |
| 1922 // Threshold size for cleararray. | |
| 1923 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1924 | |
| 4047 | 1925 // No additional cost for CMOVL. |
| 1926 const int Matcher::long_cmove_cost() { return 0; } | |
| 1927 | |
| 1928 // CMOVF/CMOVD are expensive on T4 and on SPARC64. | |
| 1929 const int Matcher::float_cmove_cost() { | |
| 1930 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; | |
| 1931 } | |
| 1932 | |
|
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1933 // Does the CPU require late expand (see block.cpp for description of late expand)? |
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1934 const bool Matcher::require_postalloc_expand = false; |
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1935 |
| 0 | 1936 // Should the Matcher clone shifts on addressing modes, expecting them to |
| 1937 // be subsumed into complex addressing expressions or compute them into | |
| 1938 // registers? True for Intel but false for most RISCs | |
| 1939 const bool Matcher::clone_shift_expressions = false; | |
| 1940 | |
|
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1941 // Do we need to mask the count passed to shift instructions or does |
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1942 // the cpu only look at the lower 5/6 bits anyway? |
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1943 const bool Matcher::need_masked_shift_count = false; |
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1944 |
|
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1945 bool Matcher::narrow_oop_use_complex_address() { |
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1946 NOT_LP64(ShouldNotCallThis()); |
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1947 assert(UseCompressedOops, "only for compressed oops code"); |
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1948 return false; |
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1949 } |
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1950 |
|
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1951 bool Matcher::narrow_klass_use_complex_address() { |
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1952 NOT_LP64(ShouldNotCallThis()); |
|
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1953 assert(UseCompressedClassPointers, "only for compressed klass code"); |
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1954 return false; |
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1955 } |
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1956 |
| 0 | 1957 // Is it better to copy float constants, or load them directly from memory? |
| 1958 // Intel can load a float constant from a direct address, requiring no | |
| 1959 // extra registers. Most RISCs will have to materialize an address into a | |
| 1960 // register first, so they would do better to copy the constant from stack. | |
| 1961 const bool Matcher::rematerialize_float_constants = false; | |
| 1962 | |
| 1963 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1964 // needed. Else we split the double into 2 integer pieces and move it | |
| 1965 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1966 // Java calling convention forces doubles to be aligned. | |
| 1967 #ifdef _LP64 | |
| 1968 const bool Matcher::misaligned_doubles_ok = true; | |
| 1969 #else | |
| 1970 const bool Matcher::misaligned_doubles_ok = false; | |
| 1971 #endif | |
| 1972 | |
| 1973 // No-op on SPARC. | |
| 1974 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1975 } | |
| 1976 | |
| 1977 // Advertise here if the CPU requires explicit rounding operations | |
| 1978 // to implement the UseStrictFP mode. | |
| 1979 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
| 1980 | |
|
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1981 // Are floats conerted to double when stored to stack during deoptimization? |
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1982 // Sparc does not handle callee-save floats. |
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1983 bool Matcher::float_in_double() { return false; } |
| 0 | 1984 |
| 1985 // Do ints take an entire long register or just half? | |
| 1986 // Note that we if-def off of _LP64. | |
| 1987 // The relevant question is how the int is callee-saved. In _LP64 | |
| 1988 // the whole long is written but de-opt'ing will have to extract | |
| 1989 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
| 1990 #ifdef _LP64 | |
| 1991 const bool Matcher::int_in_long = true; | |
| 1992 #else | |
| 1993 const bool Matcher::int_in_long = false; | |
| 1994 #endif | |
| 1995 | |
| 1996 // Return whether or not this register is ever used as an argument. This | |
| 1997 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1998 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1999 // arguments in those registers not be available to the callee. | |
| 2000 bool Matcher::can_be_java_arg( int reg ) { | |
| 2001 // Standard sparc 6 args in registers | |
| 2002 if( reg == R_I0_num || | |
| 2003 reg == R_I1_num || | |
| 2004 reg == R_I2_num || | |
| 2005 reg == R_I3_num || | |
| 2006 reg == R_I4_num || | |
| 2007 reg == R_I5_num ) return true; | |
| 2008 #ifdef _LP64 | |
| 2009 // 64-bit builds can pass 64-bit pointers and longs in | |
| 2010 // the high I registers | |
| 2011 if( reg == R_I0H_num || | |
| 2012 reg == R_I1H_num || | |
| 2013 reg == R_I2H_num || | |
| 2014 reg == R_I3H_num || | |
| 2015 reg == R_I4H_num || | |
| 2016 reg == R_I5H_num ) return true; | |
|
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2017 |
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2018 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
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2019 return true; |
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2020 } |
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2021 |
| 0 | 2022 #else |
| 2023 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
| 2024 // Longs cannot be passed in O regs, because O regs become I regs | |
| 2025 // after a 'save' and I regs get their high bits chopped off on | |
| 2026 // interrupt. | |
| 2027 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
| 2028 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
| 2029 #endif | |
| 2030 // A few float args in registers | |
| 2031 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
| 2032 | |
| 2033 return false; | |
| 2034 } | |
| 2035 | |
| 2036 bool Matcher::is_spillable_arg( int reg ) { | |
| 2037 return can_be_java_arg(reg); | |
| 2038 } | |
| 2039 | |
|
1914
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2040 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
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2041 // Use hardware SDIVX instruction when it is |
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2042 // faster than a code which use multiply. |
|
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|
2043 return VM_Version::has_fast_idiv(); |
|
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|
2044 } |
|
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|
2045 |
| 0 | 2046 // Register for DIVI projection of divmodI |
| 2047 RegMask Matcher::divI_proj_mask() { | |
| 2048 ShouldNotReachHere(); | |
| 2049 return RegMask(); | |
| 2050 } | |
| 2051 | |
| 2052 // Register for MODI projection of divmodI | |
| 2053 RegMask Matcher::modI_proj_mask() { | |
| 2054 ShouldNotReachHere(); | |
| 2055 return RegMask(); | |
| 2056 } | |
| 2057 | |
| 2058 // Register for DIVL projection of divmodL | |
| 2059 RegMask Matcher::divL_proj_mask() { | |
| 2060 ShouldNotReachHere(); | |
| 2061 return RegMask(); | |
| 2062 } | |
| 2063 | |
| 2064 // Register for MODL projection of divmodL | |
| 2065 RegMask Matcher::modL_proj_mask() { | |
| 2066 ShouldNotReachHere(); | |
| 2067 return RegMask(); | |
| 2068 } | |
| 2069 | |
|
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|
2070 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
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|
2071 return L7_REGP_mask(); |
|
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|
2072 } |
|
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|
2073 |
| 0 | 2074 %} |
| 2075 | |
| 2076 | |
| 2077 // The intptr_t operand types, defined by textual substitution. | |
| 2078 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
| 2079 #ifdef _LP64 | |
| 824 | 2080 #define immX immL |
| 2081 #define immX13 immL13 | |
| 2082 #define immX13m7 immL13m7 | |
| 2083 #define iRegX iRegL | |
| 2084 #define g1RegX g1RegL | |
| 0 | 2085 #else |
| 824 | 2086 #define immX immI |
| 2087 #define immX13 immI13 | |
| 2088 #define immX13m7 immI13m7 | |
| 2089 #define iRegX iRegI | |
| 2090 #define g1RegX g1RegI | |
| 0 | 2091 #endif |
| 2092 | |
| 2093 //----------ENCODING BLOCK----------------------------------------------------- | |
| 2094 // This block specifies the encoding classes used by the compiler to output | |
| 2095 // byte streams. Encoding classes are parameterized macros used by | |
| 2096 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 2097 // instruction. Operands specify their base encoding interface with the | |
| 2098 // interface keyword. There are currently supported four interfaces, | |
| 2099 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 2100 // operand to generate a function which returns its register number when | |
| 2101 // queried. CONST_INTER causes an operand to generate a function which | |
| 2102 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 2103 // operand to generate four functions which return the Base Register, the | |
| 2104 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 2105 // queried. COND_INTER causes an operand to generate six functions which | |
| 2106 // return the encoding code (ie - encoding bits for the instruction) | |
| 2107 // associated with each basic boolean condition for a conditional instruction. | |
| 2108 // | |
| 2109 // Instructions specify two basic values for encoding. Again, a function | |
| 2110 // is available to check if the constant displacement is an oop. They use the | |
| 2111 // ins_encode keyword to specify their encoding classes (which must be | |
| 2112 // a sequence of enc_class names, and their parameters, specified in | |
| 2113 // the encoding block), and they use the | |
| 2114 // opcode keyword to specify, in order, their primary, secondary, and | |
| 2115 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 2116 // needs for encoding need to be specified. | |
| 2117 encode %{ | |
| 2118 enc_class enc_untested %{ | |
| 2119 #ifdef ASSERT | |
| 2120 MacroAssembler _masm(&cbuf); | |
| 2121 __ untested("encoding"); | |
| 2122 #endif | |
| 2123 %} | |
| 2124 | |
| 2125 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
|
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|
2126 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary, |
| 0 | 2127 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
| 2128 %} | |
| 2129 | |
|
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|
2130 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
|
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|
2131 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, |
|
415
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2132 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
|
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|
2133 %} |
|
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|
2134 |
| 0 | 2135 enc_class form3_mem_prefetch_read( memory mem ) %{ |
|
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|
2136 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, |
| 0 | 2137 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
| 2138 %} | |
| 2139 | |
| 2140 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
|
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|
2141 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, |
| 0 | 2142 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
| 2143 %} | |
| 2144 | |
| 2145 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
|
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|
2146 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
|
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|
2147 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
| 0 | 2148 guarantee($mem$$index == R_G0_enc, "double index?"); |
|
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|
2149 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
|
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|
2150 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
| 0 | 2151 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
| 2152 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
| 2153 %} | |
| 2154 | |
| 2155 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
|
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|
2156 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
|
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|
2157 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
| 0 | 2158 guarantee($mem$$index == R_G0_enc, "double index?"); |
| 2159 // Load long with 2 instructions | |
|
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|
2160 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
|
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|
2161 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
| 0 | 2162 %} |
| 2163 | |
| 2164 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
| 2165 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
| 2166 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
|
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|
2167 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
| 0 | 2168 %} |
| 2169 | |
| 2170 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
| 2171 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2172 if( $rs2$$reg != $rd$$reg ) | |
| 2173 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 2174 %} | |
| 2175 | |
| 2176 // Target lo half of long | |
| 2177 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
| 2178 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2179 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
| 2180 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 2181 %} | |
| 2182 | |
| 2183 // Source lo half of long | |
| 2184 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
| 2185 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2186 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
| 2187 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
| 2188 %} | |
| 2189 | |
| 2190 // Target hi half of long | |
| 2191 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
| 2192 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
| 2193 %} | |
| 2194 | |
| 2195 // Source lo half of long, and leave it sign extended. | |
| 2196 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
| 2197 // Sign extend low half | |
| 2198 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
| 2199 %} | |
| 2200 | |
| 2201 // Source hi half of long, and leave it sign extended. | |
| 2202 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
| 2203 // Shift high half to low half | |
| 2204 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
| 2205 %} | |
| 2206 | |
| 2207 // Source hi half of long | |
| 2208 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
| 2209 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2210 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
| 2211 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
| 2212 %} | |
| 2213 | |
| 2214 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
| 2215 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
| 2216 %} | |
| 2217 | |
| 2218 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
| 2219 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
| 2220 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
| 2221 %} | |
| 2222 | |
| 2223 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
| 2224 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
| 2225 // clear if nothing else is happening | |
| 2226 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
| 2227 // blt,a,pn done | |
| 2228 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
| 2229 // mov dst,-1 in delay slot | |
| 2230 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2231 %} | |
| 2232 | |
| 2233 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
| 2234 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
| 2235 %} | |
| 2236 | |
| 2237 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
| 2238 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
| 2239 %} | |
| 2240 | |
| 2241 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
| 2242 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
| 2243 %} | |
| 2244 | |
| 2245 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
| 2246 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
| 2247 %} | |
| 2248 | |
| 2249 enc_class move_return_pc_to_o1() %{ | |
| 2250 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
| 2251 %} | |
| 2252 | |
| 2253 #ifdef _LP64 | |
| 2254 /* %%% merge with enc_to_bool */ | |
| 2255 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
| 2256 MacroAssembler _masm(&cbuf); | |
| 2257 | |
| 2258 Register src_reg = reg_to_register_object($src$$reg); | |
| 2259 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 2260 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
| 2261 %} | |
| 2262 #endif | |
| 2263 | |
| 2264 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
| 2265 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
| 2266 MacroAssembler _masm(&cbuf); | |
| 2267 | |
| 2268 Register p_reg = reg_to_register_object($p$$reg); | |
| 2269 Register q_reg = reg_to_register_object($q$$reg); | |
| 2270 Register y_reg = reg_to_register_object($y$$reg); | |
| 2271 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
| 2272 | |
| 2273 __ subcc( p_reg, q_reg, p_reg ); | |
| 2274 __ add ( p_reg, y_reg, tmp_reg ); | |
| 2275 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
| 2276 %} | |
| 2277 | |
| 2278 enc_class form_d2i_helper(regD src, regF dst) %{ | |
| 2279 // fcmp %fcc0,$src,$src | |
| 2280 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2281 // branch %fcc0 not-nan, predict taken | |
| 2282 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2283 // fdtoi $src,$dst | |
| 2284 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
| 2285 // fitos $dst,$dst (if nan) | |
| 2286 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2287 // clear $dst (if nan) | |
| 2288 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2289 // carry on here... | |
| 2290 %} | |
| 2291 | |
| 2292 enc_class form_d2l_helper(regD src, regD dst) %{ | |
| 2293 // fcmp %fcc0,$src,$src check for NAN | |
| 2294 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2295 // branch %fcc0 not-nan, predict taken | |
| 2296 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2297 // fdtox $src,$dst convert in delay slot | |
| 2298 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
| 2299 // fxtod $dst,$dst (if nan) | |
| 2300 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2301 // clear $dst (if nan) | |
| 2302 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2303 // carry on here... | |
| 2304 %} | |
| 2305 | |
| 2306 enc_class form_f2i_helper(regF src, regF dst) %{ | |
| 2307 // fcmps %fcc0,$src,$src | |
| 2308 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2309 // branch %fcc0 not-nan, predict taken | |
| 2310 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2311 // fstoi $src,$dst | |
| 2312 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
| 2313 // fitos $dst,$dst (if nan) | |
| 2314 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2315 // clear $dst (if nan) | |
| 2316 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2317 // carry on here... | |
| 2318 %} | |
| 2319 | |
| 2320 enc_class form_f2l_helper(regF src, regD dst) %{ | |
| 2321 // fcmps %fcc0,$src,$src | |
| 2322 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2323 // branch %fcc0 not-nan, predict taken | |
| 2324 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2325 // fstox $src,$dst | |
| 2326 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
| 2327 // fxtod $dst,$dst (if nan) | |
| 2328 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2329 // clear $dst (if nan) | |
| 2330 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2331 // carry on here... | |
| 2332 %} | |
| 2333 | |
| 2334 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2335 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2336 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2337 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2338 | |
| 2339 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2340 | |
| 2341 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2342 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2343 | |
| 2344 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
| 2345 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2346 %} | |
| 2347 | |
| 2348 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
| 2349 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2350 %} | |
| 2351 | |
| 2352 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
| 2353 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2354 %} | |
| 2355 | |
| 2356 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
| 2357 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2358 %} | |
| 2359 | |
| 2360 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
| 2361 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
| 2362 %} | |
| 2363 | |
| 2364 // Encloding class for traceable jumps | |
| 2365 enc_class form_jmpl(g3RegP dest) %{ | |
| 2366 emit_jmpl(cbuf, $dest$$reg); | |
| 2367 %} | |
| 2368 | |
| 2369 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
| 2370 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
| 2371 %} | |
| 2372 | |
| 2373 enc_class form2_nop() %{ | |
| 2374 emit_nop(cbuf); | |
| 2375 %} | |
| 2376 | |
| 2377 enc_class form2_illtrap() %{ | |
| 2378 emit_illtrap(cbuf); | |
| 2379 %} | |
| 2380 | |
| 2381 | |
| 2382 // Compare longs and convert into -1, 0, 1. | |
| 2383 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
| 2384 // CMP $src1,$src2 | |
| 2385 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
| 2386 // blt,a,pn done | |
| 2387 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
| 2388 // mov dst,-1 in delay slot | |
| 2389 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2390 // bgt,a,pn done | |
| 2391 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
| 2392 // mov dst,1 in delay slot | |
| 2393 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
| 2394 // CLR $dst | |
| 2395 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
| 2396 %} | |
| 2397 | |
| 2398 enc_class enc_PartialSubtypeCheck() %{ | |
| 2399 MacroAssembler _masm(&cbuf); | |
| 2400 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
| 2401 __ delayed()->nop(); | |
| 2402 %} | |
| 2403 | |
| 3839 | 2404 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ |
| 0 | 2405 MacroAssembler _masm(&cbuf); |
| 3839 | 2406 Label* L = $labl$$label; |
| 0 | 2407 Assembler::Predict predict_taken = |
| 3839 | 2408 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
| 2409 | |
| 2410 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 0 | 2411 __ delayed()->nop(); |
| 2412 %} | |
| 2413 | |
| 3839 | 2414 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ |
| 0 | 2415 MacroAssembler _masm(&cbuf); |
| 3839 | 2416 Label* L = $labl$$label; |
| 0 | 2417 Assembler::Predict predict_taken = |
| 3839 | 2418 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
| 2419 | |
| 2420 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); | |
| 0 | 2421 __ delayed()->nop(); |
| 2422 %} | |
| 2423 | |
| 2424 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
| 2425 int op = (Assembler::arith_op << 30) | | |
| 2426 ($dst$$reg << 25) | | |
| 2427 (Assembler::movcc_op3 << 19) | | |
| 2428 (1 << 18) | // cc2 bit for 'icc' | |
| 2429 ($cmp$$cmpcode << 14) | | |
| 2430 (0 << 13) | // select register move | |
| 2431 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
| 2432 ($src$$reg << 0); | |
| 1748 | 2433 cbuf.insts()->emit_int32(op); |
| 0 | 2434 %} |
| 2435 | |
| 2436 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
| 2437 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2438 int op = (Assembler::arith_op << 30) | | |
| 2439 ($dst$$reg << 25) | | |
| 2440 (Assembler::movcc_op3 << 19) | | |
| 2441 (1 << 18) | // cc2 bit for 'icc' | |
| 2442 ($cmp$$cmpcode << 14) | | |
| 2443 (1 << 13) | // select immediate move | |
| 2444 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
| 2445 (simm11 << 0); | |
| 1748 | 2446 cbuf.insts()->emit_int32(op); |
| 0 | 2447 %} |
| 2448 | |
| 2449 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
| 2450 int op = (Assembler::arith_op << 30) | | |
| 2451 ($dst$$reg << 25) | | |
| 2452 (Assembler::movcc_op3 << 19) | | |
| 2453 (0 << 18) | // cc2 bit for 'fccX' | |
| 2454 ($cmp$$cmpcode << 14) | | |
| 2455 (0 << 13) | // select register move | |
| 2456 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2457 ($src$$reg << 0); | |
| 1748 | 2458 cbuf.insts()->emit_int32(op); |
| 0 | 2459 %} |
| 2460 | |
| 2461 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
| 2462 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2463 int op = (Assembler::arith_op << 30) | | |
| 2464 ($dst$$reg << 25) | | |
| 2465 (Assembler::movcc_op3 << 19) | | |
| 2466 (0 << 18) | // cc2 bit for 'fccX' | |
| 2467 ($cmp$$cmpcode << 14) | | |
| 2468 (1 << 13) | // select immediate move | |
| 2469 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2470 (simm11 << 0); | |
| 1748 | 2471 cbuf.insts()->emit_int32(op); |
| 0 | 2472 %} |
| 2473 | |
| 2474 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
| 2475 int op = (Assembler::arith_op << 30) | | |
| 2476 ($dst$$reg << 25) | | |
| 2477 (Assembler::fpop2_op3 << 19) | | |
| 2478 (0 << 18) | | |
| 2479 ($cmp$$cmpcode << 14) | | |
| 2480 (1 << 13) | // select register move | |
| 2481 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
| 2482 ($primary << 5) | // select single, double or quad | |
| 2483 ($src$$reg << 0); | |
| 1748 | 2484 cbuf.insts()->emit_int32(op); |
| 0 | 2485 %} |
| 2486 | |
| 2487 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
| 2488 int op = (Assembler::arith_op << 30) | | |
| 2489 ($dst$$reg << 25) | | |
| 2490 (Assembler::fpop2_op3 << 19) | | |
| 2491 (0 << 18) | | |
| 2492 ($cmp$$cmpcode << 14) | | |
| 2493 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
| 2494 ($primary << 5) | // select single, double or quad | |
| 2495 ($src$$reg << 0); | |
| 1748 | 2496 cbuf.insts()->emit_int32(op); |
| 0 | 2497 %} |
| 2498 | |
| 2499 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
| 2500 // the condition comes from opcode-field instead of an argument. | |
| 2501 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
| 2502 int op = (Assembler::arith_op << 30) | | |
| 2503 ($dst$$reg << 25) | | |
| 2504 (Assembler::movcc_op3 << 19) | | |
| 2505 (1 << 18) | // cc2 bit for 'icc' | |
| 2506 ($primary << 14) | | |
| 2507 (0 << 13) | // select register move | |
| 2508 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2509 ($src$$reg << 0); | |
| 1748 | 2510 cbuf.insts()->emit_int32(op); |
| 0 | 2511 %} |
| 2512 | |
| 2513 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
| 2514 int op = (Assembler::arith_op << 30) | | |
| 2515 ($dst$$reg << 25) | | |
| 2516 (Assembler::movcc_op3 << 19) | | |
| 2517 (6 << 16) | // cc2 bit for 'xcc' | |
| 2518 ($primary << 14) | | |
| 2519 (0 << 13) | // select register move | |
| 2520 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2521 ($src$$reg << 0); | |
| 1748 | 2522 cbuf.insts()->emit_int32(op); |
| 0 | 2523 %} |
| 2524 | |
| 2525 enc_class Set13( immI13 src, iRegI rd ) %{ | |
| 2526 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
| 2527 %} | |
| 2528 | |
| 2529 enc_class SetHi22( immI src, iRegI rd ) %{ | |
| 2530 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
| 2531 %} | |
| 2532 | |
| 2533 enc_class Set32( immI src, iRegI rd ) %{ | |
| 2534 MacroAssembler _masm(&cbuf); | |
| 2535 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
| 2536 %} | |
| 2537 | |
| 2538 enc_class call_epilog %{ | |
| 2539 if( VerifyStackAtCalls ) { | |
| 2540 MacroAssembler _masm(&cbuf); | |
| 2541 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
| 2542 Register temp_reg = G3; | |
| 2543 __ add(SP, framesize, temp_reg); | |
| 2544 __ cmp(temp_reg, FP); | |
| 2545 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
| 2546 } | |
| 2547 %} | |
| 2548 | |
| 2549 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
| 2550 // to G1 so the register allocator will not have to deal with the misaligned register | |
| 2551 // pair. | |
| 2552 enc_class adjust_long_from_native_call %{ | |
| 2553 #ifndef _LP64 | |
| 2554 if (returns_long()) { | |
| 2555 // sllx O0,32,O0 | |
| 2556 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
| 2557 // srl O1,0,O1 | |
| 2558 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
| 2559 // or O0,O1,G1 | |
| 2560 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
| 2561 } | |
| 2562 #endif | |
| 2563 %} | |
| 2564 | |
| 2565 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
| 2566 // CALL directly to the runtime | |
| 2567 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
| 2568 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
|
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2569 /*preserve_g2=*/true); |
| 0 | 2570 %} |
| 2571 | |
| 1567 | 2572 enc_class preserve_SP %{ |
| 2573 MacroAssembler _masm(&cbuf); | |
| 2574 __ mov(SP, L7_mh_SP_save); | |
| 2575 %} | |
| 2576 | |
| 2577 enc_class restore_SP %{ | |
| 2578 MacroAssembler _masm(&cbuf); | |
| 2579 __ mov(L7_mh_SP_save, SP); | |
| 2580 %} | |
| 2581 | |
| 0 | 2582 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
| 2583 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2584 // who we intended to call. | |
|
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2585 if (!_method) { |
| 0 | 2586 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); |
| 2587 } else if (_optimized_virtual) { | |
| 2588 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
| 2589 } else { | |
| 2590 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
| 2591 } | |
|
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2592 if (_method) { // Emit stub for static call. |
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2593 CompiledStaticCall::emit_to_interp_stub(cbuf); |
| 0 | 2594 } |
| 2595 %} | |
| 2596 | |
| 2597 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
| 2598 MacroAssembler _masm(&cbuf); | |
| 2599 __ set_inst_mark(); | |
| 2600 int vtable_index = this->_vtable_index; | |
| 2601 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
| 2602 if (vtable_index < 0) { | |
| 2603 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
|
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2604 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
| 0 | 2605 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); |
| 2606 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
| 2607 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
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2608 __ ic_call((address)$meth$$method); |
| 0 | 2609 } else { |
| 2610 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 2611 // Just go thru the vtable | |
| 2612 // get receiver klass (receiver already checked for non-null) | |
| 2613 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
| 2614 int off = __ offset(); | |
|
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2615 __ load_klass(O0, G3_scratch); |
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2616 int klass_load_size; |
|
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2617 if (UseCompressedClassPointers) { |
|
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2618 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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2619 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; |
|
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2620 } else { |
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2621 klass_load_size = 1*BytesPerInstWord; |
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2622 } |
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2623 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
| 0 | 2624 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); |
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2625 if (Assembler::is_simm13(v_off)) { |
| 0 | 2626 __ ld_ptr(G3, v_off, G5_method); |
| 2627 } else { | |
| 2628 // Generate 2 instructions | |
| 2629 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
| 2630 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
| 2631 // ld_ptr, set_hi, set | |
|
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2632 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
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2633 "Unexpected instruction size(s)"); |
| 0 | 2634 __ ld_ptr(G3, G5_method, G5_method); |
| 2635 } | |
| 2636 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
| 2637 // However it may very well end up in handle_wrong_method if the | |
| 2638 // method is abstract for the particular class. | |
|
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2639 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch); |
| 0 | 2640 // jump to target (either compiled code or c2iadapter) |
| 2641 __ jmpl(G3_scratch, G0, O7); | |
| 2642 __ delayed()->nop(); | |
| 2643 } | |
| 2644 %} | |
| 2645 | |
| 2646 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
| 2647 MacroAssembler _masm(&cbuf); | |
| 2648 | |
| 2649 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2650 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
| 2651 // we might be calling a C2I adapter which needs it. | |
| 2652 | |
| 2653 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
| 2654 // Load nmethod | |
|
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2655 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg); |
| 0 | 2656 |
| 2657 // CALL to compiled java, indirect the contents of G3 | |
| 2658 __ set_inst_mark(); | |
| 2659 __ callr(temp_reg, G0); | |
| 2660 __ delayed()->nop(); | |
| 2661 %} | |
| 2662 | |
| 2663 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
| 2664 MacroAssembler _masm(&cbuf); | |
| 2665 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2666 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2667 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2668 | |
| 2669 __ sra(Rdivisor, 0, Rdivisor); | |
| 2670 __ sra(Rdividend, 0, Rdividend); | |
| 2671 __ sdivx(Rdividend, Rdivisor, Rresult); | |
| 2672 %} | |
| 2673 | |
| 2674 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
| 2675 MacroAssembler _masm(&cbuf); | |
| 2676 | |
| 2677 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2678 int divisor = $imm$$constant; | |
| 2679 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2680 | |
| 2681 __ sra(Rdividend, 0, Rdividend); | |
| 2682 __ sdivx(Rdividend, divisor, Rresult); | |
| 2683 %} | |
| 2684 | |
| 2685 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 2686 MacroAssembler _masm(&cbuf); | |
| 2687 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
| 2688 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
| 2689 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2690 | |
| 2691 __ sra( Rsrc1, 0, Rsrc1 ); | |
| 2692 __ sra( Rsrc2, 0, Rsrc2 ); | |
| 2693 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
| 2694 __ srlx( Rdst, 32, Rdst ); | |
| 2695 %} | |
| 2696 | |
| 2697 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
| 2698 MacroAssembler _masm(&cbuf); | |
| 2699 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2700 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2701 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2702 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2703 | |
| 2704 assert(Rdividend != Rscratch, ""); | |
| 2705 assert(Rdivisor != Rscratch, ""); | |
| 2706 | |
| 2707 __ sra(Rdividend, 0, Rdividend); | |
| 2708 __ sra(Rdivisor, 0, Rdivisor); | |
| 2709 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
| 2710 __ mulx(Rscratch, Rdivisor, Rscratch); | |
| 2711 __ sub(Rdividend, Rscratch, Rresult); | |
| 2712 %} | |
| 2713 | |
| 2714 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
| 2715 MacroAssembler _masm(&cbuf); | |
| 2716 | |
| 2717 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2718 int divisor = $imm$$constant; | |
| 2719 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2720 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2721 | |
| 2722 assert(Rdividend != Rscratch, ""); | |
| 2723 | |
| 2724 __ sra(Rdividend, 0, Rdividend); | |
| 2725 __ sdivx(Rdividend, divisor, Rscratch); | |
| 2726 __ mulx(Rscratch, divisor, Rscratch); | |
| 2727 __ sub(Rdividend, Rscratch, Rresult); | |
| 2728 %} | |
| 2729 | |
| 2730 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
| 2731 MacroAssembler _masm(&cbuf); | |
| 2732 | |
| 2733 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2734 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2735 | |
| 2736 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2737 %} | |
| 2738 | |
| 2739 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
| 2740 MacroAssembler _masm(&cbuf); | |
| 2741 | |
| 2742 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2743 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2744 | |
| 2745 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2746 %} | |
| 2747 | |
| 2748 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
| 2749 MacroAssembler _masm(&cbuf); | |
| 2750 | |
| 2751 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2752 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2753 | |
| 2754 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2755 %} | |
| 2756 | |
| 2757 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
| 2758 MacroAssembler _masm(&cbuf); | |
| 2759 | |
| 2760 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2761 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2762 | |
| 2763 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2764 %} | |
| 2765 | |
| 2766 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
| 2767 MacroAssembler _masm(&cbuf); | |
| 2768 | |
| 2769 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2770 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2771 | |
| 2772 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2773 %} | |
| 2774 | |
| 2775 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
| 2776 MacroAssembler _masm(&cbuf); | |
| 2777 | |
| 2778 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2779 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2780 | |
| 2781 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2782 %} | |
| 2783 | |
| 2784 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
| 2785 MacroAssembler _masm(&cbuf); | |
| 2786 | |
| 2787 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2788 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2789 | |
| 2790 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2791 %} | |
| 2792 | |
| 2793 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2794 MacroAssembler _masm(&cbuf); | |
| 2795 | |
| 2796 Register Roop = reg_to_register_object($oop$$reg); | |
| 2797 Register Rbox = reg_to_register_object($box$$reg); | |
| 2798 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2799 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2800 | |
| 2801 assert(Roop != Rscratch, ""); | |
| 2802 assert(Roop != Rmark, ""); | |
| 2803 assert(Rbox != Rscratch, ""); | |
| 2804 assert(Rbox != Rmark, ""); | |
| 2805 | |
|
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2806 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2807 %} |
| 2808 | |
| 2809 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2810 MacroAssembler _masm(&cbuf); | |
| 2811 | |
| 2812 Register Roop = reg_to_register_object($oop$$reg); | |
| 2813 Register Rbox = reg_to_register_object($box$$reg); | |
| 2814 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2815 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2816 | |
| 2817 assert(Roop != Rscratch, ""); | |
| 2818 assert(Roop != Rmark, ""); | |
| 2819 assert(Rbox != Rscratch, ""); | |
| 2820 assert(Rbox != Rmark, ""); | |
| 2821 | |
|
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|
2822 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2823 %} |
| 2824 | |
| 2825 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
| 2826 MacroAssembler _masm(&cbuf); | |
| 2827 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2828 Register Rold = reg_to_register_object($old$$reg); | |
| 2829 Register Rnew = reg_to_register_object($new$$reg); | |
| 2830 | |
| 10997 | 2831 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
| 0 | 2832 __ cmp( Rold, Rnew ); |
| 2833 %} | |
| 2834 | |
| 2835 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
| 2836 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2837 Register Rold = reg_to_register_object($old$$reg); | |
| 2838 Register Rnew = reg_to_register_object($new$$reg); | |
| 2839 | |
| 2840 MacroAssembler _masm(&cbuf); | |
| 2841 __ mov(Rnew, O7); | |
| 2842 __ casx(Rmem, Rold, O7); | |
| 2843 __ cmp( Rold, O7 ); | |
| 2844 %} | |
| 2845 | |
| 2846 // raw int cas, used for compareAndSwap | |
| 2847 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
| 2848 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2849 Register Rold = reg_to_register_object($old$$reg); | |
| 2850 Register Rnew = reg_to_register_object($new$$reg); | |
| 2851 | |
| 2852 MacroAssembler _masm(&cbuf); | |
| 2853 __ mov(Rnew, O7); | |
| 2854 __ cas(Rmem, Rold, O7); | |
| 2855 __ cmp( Rold, O7 ); | |
| 2856 %} | |
| 2857 | |
| 2858 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
| 2859 Register Rres = reg_to_register_object($res$$reg); | |
| 2860 | |
| 2861 MacroAssembler _masm(&cbuf); | |
| 2862 __ mov(1, Rres); | |
| 2863 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
| 2864 %} | |
| 2865 | |
| 2866 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
| 2867 Register Rres = reg_to_register_object($res$$reg); | |
| 2868 | |
| 2869 MacroAssembler _masm(&cbuf); | |
| 2870 __ mov(1, Rres); | |
| 2871 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
| 2872 %} | |
| 2873 | |
| 2874 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
| 2875 MacroAssembler _masm(&cbuf); | |
| 2876 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2877 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
| 2878 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
| 2879 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
| 2880 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
| 2881 | |
| 2882 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
| 2883 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
| 2884 %} | |
| 2885 | |
| 2886 | |
|
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2887 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
| 0 | 2888 Label Ldone, Lloop; |
| 2889 MacroAssembler _masm(&cbuf); | |
| 2890 | |
| 2891 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2892 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
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2893 Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
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2894 Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
| 0 | 2895 Register result_reg = reg_to_register_object($result$$reg); |
| 2896 | |
|
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2897 assert(result_reg != str1_reg && |
|
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2898 result_reg != str2_reg && |
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2899 result_reg != cnt1_reg && |
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2900 result_reg != cnt2_reg , |
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2901 "need different registers"); |
| 0 | 2902 |
| 2903 // Compute the minimum of the string lengths(str1_reg) and the | |
| 2904 // difference of the string lengths (stack) | |
| 2905 | |
| 2906 // See if the lengths are different, and calculate min in str1_reg. | |
| 2907 // Stash diff in O7 in case we need it for a tie-breaker. | |
| 2908 Label Lskip; | |
|
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2909 __ subcc(cnt1_reg, cnt2_reg, O7); |
|
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2910 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2911 __ br(Assembler::greater, true, Assembler::pt, Lskip); |
|
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2912 // cnt2 is shorter, so use its count: |
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2913 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2914 __ bind(Lskip); |
| 2915 | |
|
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2916 // reallocate cnt1_reg, cnt2_reg, result_reg |
| 0 | 2917 // Note: limit_reg holds the string length pre-scaled by 2 |
|
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2918 Register limit_reg = cnt1_reg; |
|
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2919 Register chr2_reg = cnt2_reg; |
| 0 | 2920 Register chr1_reg = result_reg; |
|
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2921 // str{12} are the base pointers |
| 0 | 2922 |
| 2923 // Is the minimum length zero? | |
| 2924 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
| 2925 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2926 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2927 | |
| 2928 // Load first characters | |
|
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2929 __ lduh(str1_reg, 0, chr1_reg); |
|
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|
2930 __ lduh(str2_reg, 0, chr2_reg); |
| 0 | 2931 |
| 2932 // Compare first characters | |
| 2933 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
| 2934 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2935 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2936 __ delayed()->nop(); | |
| 2937 | |
| 2938 { | |
| 2939 // Check after comparing first character to see if strings are equivalent | |
| 2940 Label LSkip2; | |
| 2941 // Check if the strings start at same location | |
|
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2942 __ cmp(str1_reg, str2_reg); |
| 0 | 2943 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
| 2944 __ delayed()->nop(); | |
| 2945 | |
| 2946 // Check if the length difference is zero (in O7) | |
| 2947 __ cmp(G0, O7); | |
| 2948 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2949 __ delayed()->mov(G0, result_reg); // result is zero | |
| 2950 | |
| 2951 // Strings might not be equal | |
| 2952 __ bind(LSkip2); | |
| 2953 } | |
| 2954 | |
|
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2955 // We have no guarantee that on 64 bit the higher half of limit_reg is 0 |
|
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2956 __ signx(limit_reg); |
|
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2957 |
| 0 | 2958 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); |
| 2959 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2960 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2961 | |
|
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2962 // Shift str1_reg and str2_reg to the end of the arrays, negate limit |
|
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2963 __ add(str1_reg, limit_reg, str1_reg); |
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2964 __ add(str2_reg, limit_reg, str2_reg); |
| 0 | 2965 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
| 2966 | |
| 2967 // Compare the rest of the characters | |
|
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2968 __ lduh(str1_reg, limit_reg, chr1_reg); |
| 0 | 2969 __ bind(Lloop); |
|
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2970 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
|
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2971 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 0 | 2972 __ subcc(chr1_reg, chr2_reg, chr1_reg); |
| 2973 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2974 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2975 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
| 2976 // annul LDUH if branch is not taken to prevent access past end of string | |
| 2977 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
|
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2978 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 0 | 2979 |
| 2980 // If strings are equal up to min length, return the length difference. | |
| 2981 __ mov(O7, result_reg); | |
| 2982 | |
| 2983 // Otherwise, return the difference between the first mismatched chars. | |
| 2984 __ bind(Ldone); | |
| 2985 %} | |
| 2986 | |
|
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2987 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
|
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2988 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
| 681 | 2989 MacroAssembler _masm(&cbuf); |
| 2990 | |
| 2991 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2992 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
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2993 Register cnt_reg = reg_to_register_object($cnt$$reg); |
|
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2994 Register tmp1_reg = O7; |
| 681 | 2995 Register result_reg = reg_to_register_object($result$$reg); |
| 2996 | |
|
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2997 assert(result_reg != str1_reg && |
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2998 result_reg != str2_reg && |
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2999 result_reg != cnt_reg && |
|
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|
3000 result_reg != tmp1_reg , |
|
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3001 "need different registers"); |
|
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3002 |
|
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3003 __ cmp(str1_reg, str2_reg); //same char[] ? |
| 681 | 3004 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 3005 __ delayed()->add(G0, 1, result_reg); | |
| 3006 | |
| 3839 | 3007 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn); |
|
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3008 __ delayed()->add(G0, 1, result_reg); // count == 0 |
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3009 |
| 681 | 3010 //rename registers |
|
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3011 Register limit_reg = cnt_reg; |
| 681 | 3012 Register chr1_reg = result_reg; |
|
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3013 Register chr2_reg = tmp1_reg; |
| 681 | 3014 |
|
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3015 // We have no guarantee that on 64 bit the higher half of limit_reg is 0 |
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3016 __ signx(limit_reg); |
|
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3017 |
| 681 | 3018 //check for alignment and position the pointers to the ends |
|
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3019 __ or3(str1_reg, str2_reg, chr1_reg); |
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3020 __ andcc(chr1_reg, 0x3, chr1_reg); |
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3021 // notZero means at least one not 4-byte aligned. |
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3022 // We could optimize the case when both arrays are not aligned |
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3023 // but it is not frequent case and it requires additional checks. |
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3024 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
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3025 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
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3026 |
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3027 // Compare char[] arrays aligned to 4 bytes. |
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3028 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
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3029 chr1_reg, chr2_reg, Ldone); |
| 3839 | 3030 __ ba(Ldone); |
| 681 | 3031 __ delayed()->add(G0, 1, result_reg); |
| 3032 | |
|
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3033 // char by char compare |
| 681 | 3034 __ bind(Lchar); |
|
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3035 __ add(str1_reg, limit_reg, str1_reg); |
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3036 __ add(str2_reg, limit_reg, str2_reg); |
| 681 | 3037 __ neg(limit_reg); //negate count |
| 3038 | |
|
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3039 __ lduh(str1_reg, limit_reg, chr1_reg); |
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3040 // Lchar_loop |
| 681 | 3041 __ bind(Lchar_loop); |
|
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3042 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 681 | 3043 __ cmp(chr1_reg, chr2_reg); |
| 3044 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
| 3045 __ delayed()->mov(G0, result_reg); //not equal | |
| 3046 __ inccc(limit_reg, sizeof(jchar)); | |
| 3047 // annul LDUH if branch is not taken to prevent access past end of string | |
|
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3048 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
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3049 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 681 | 3050 |
| 3051 __ add(G0, 1, result_reg); //equal | |
| 3052 | |
| 3053 __ bind(Ldone); | |
| 3054 %} | |
| 3055 | |
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3056 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
| 681 | 3057 Label Lvector, Ldone, Lloop; |
| 3058 MacroAssembler _masm(&cbuf); | |
| 3059 | |
| 3060 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
| 3061 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
| 3062 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
|
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3063 Register tmp2_reg = O7; |
| 681 | 3064 Register result_reg = reg_to_register_object($result$$reg); |
| 3065 | |
| 3066 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
| 3067 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
| 3068 | |
| 3069 // return true if the same array | |
| 3070 __ cmp(ary1_reg, ary2_reg); | |
| 1016 | 3071 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 681 | 3072 __ delayed()->add(G0, 1, result_reg); // equal |
| 3073 | |
| 3074 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
| 3075 __ delayed()->mov(G0, result_reg); // not equal | |
| 3076 | |
| 3077 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
| 3078 __ delayed()->mov(G0, result_reg); // not equal | |
| 3079 | |
| 3080 //load the lengths of arrays | |
| 727 | 3081 __ ld(Address(ary1_reg, length_offset), tmp1_reg); |
| 3082 __ ld(Address(ary2_reg, length_offset), tmp2_reg); | |
| 681 | 3083 |
| 3084 // return false if the two arrays are not equal length | |
| 3085 __ cmp(tmp1_reg, tmp2_reg); | |
| 3086 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
| 3087 __ delayed()->mov(G0, result_reg); // not equal | |
| 3088 | |
| 3839 | 3089 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn); |
| 681 | 3090 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
| 3091 | |
| 3092 // load array addresses | |
| 3093 __ add(ary1_reg, base_offset, ary1_reg); | |
| 3094 __ add(ary2_reg, base_offset, ary2_reg); | |
| 3095 | |
| 3096 // renaming registers | |
|
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3097 Register chr1_reg = result_reg; // for characters in ary1 |
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3098 Register chr2_reg = tmp2_reg; // for characters in ary2 |
| 681 | 3099 Register limit_reg = tmp1_reg; // length |
| 3100 | |
| 3101 // set byte count | |
| 3102 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
|
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3103 |
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3104 // Compare char[] arrays aligned to 4 bytes. |
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3105 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
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|
3106 chr1_reg, chr2_reg, Ldone); |
| 681 | 3107 __ add(G0, 1, result_reg); // equals |
| 3108 | |
| 3109 __ bind(Ldone); | |
| 3110 %} | |
| 3111 | |
| 0 | 3112 enc_class enc_rethrow() %{ |
| 1748 | 3113 cbuf.set_insts_mark(); |
| 0 | 3114 Register temp_reg = G3; |
| 727 | 3115 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
| 0 | 3116 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
| 3117 MacroAssembler _masm(&cbuf); | |
| 3118 #ifdef ASSERT | |
| 3119 __ save_frame(0); | |
| 727 | 3120 AddressLiteral last_rethrow_addrlit(&last_rethrow); |
| 3121 __ sethi(last_rethrow_addrlit, L1); | |
| 3122 Address addr(L1, last_rethrow_addrlit.low10()); | |
| 10997 | 3123 __ rdpc(L2); |
| 0 | 3124 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to |
| 727 | 3125 __ st_ptr(L2, addr); |
| 0 | 3126 __ restore(); |
| 3127 #endif | |
| 727 | 3128 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
| 0 | 3129 __ delayed()->nop(); |
| 3130 %} | |
| 3131 | |
| 3132 enc_class emit_mem_nop() %{ | |
| 3133 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
| 1748 | 3134 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); |
| 0 | 3135 %} |
| 3136 | |
| 3137 enc_class emit_fadd_nop() %{ | |
| 3138 // Generates the instruction FMOVS f31,f31 | |
| 1748 | 3139 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); |
| 0 | 3140 %} |
| 3141 | |
| 3142 enc_class emit_br_nop() %{ | |
| 3143 // Generates the instruction BPN,PN . | |
| 1748 | 3144 cbuf.insts()->emit_int32((unsigned int) 0x00400000); |
| 0 | 3145 %} |
| 3146 | |
| 3147 enc_class enc_membar_acquire %{ | |
| 3148 MacroAssembler _masm(&cbuf); | |
| 3149 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
| 3150 %} | |
| 3151 | |
| 3152 enc_class enc_membar_release %{ | |
| 3153 MacroAssembler _masm(&cbuf); | |
| 3154 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
| 3155 %} | |
| 3156 | |
| 3157 enc_class enc_membar_volatile %{ | |
| 3158 MacroAssembler _masm(&cbuf); | |
| 3159 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
| 3160 %} | |
|
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3161 |
| 0 | 3162 %} |
| 3163 | |
| 3164 //----------FRAME-------------------------------------------------------------- | |
| 3165 // Definition of frame structure and management information. | |
| 3166 // | |
| 3167 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3168 // | (to get allocators register number | |
| 3169 // G Owned by | | v add VMRegImpl::stack0) | |
| 3170 // r CALLER | | | |
| 3171 // o | +--------+ pad to even-align allocators stack-slot | |
| 3172 // w V | pad0 | numbers; owned by CALLER | |
| 3173 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3174 // h ^ | in | 5 | |
| 3175 // | | args | 4 Holes in incoming args owned by SELF | |
| 3176 // | | | | 3 | |
| 3177 // | | +--------+ | |
| 3178 // V | | old out| Empty on Intel, window on Sparc | |
| 3179 // | old |preserve| Must be even aligned. | |
| 3180 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
| 3181 // | | in | 3 area for Intel ret address | |
| 3182 // Owned by |preserve| Empty on Sparc. | |
| 3183 // SELF +--------+ | |
| 3184 // | | pad2 | 2 pad to align old SP | |
| 3185 // | +--------+ 1 | |
| 3186 // | | locks | 0 | |
| 3187 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
| 3188 // | | pad1 | 11 pad to align new SP | |
| 3189 // | +--------+ | |
| 3190 // | | | 10 | |
| 3191 // | | spills | 9 spills | |
| 3192 // V | | 8 (pad0 slot for callee) | |
| 3193 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3194 // ^ | out | 7 | |
| 3195 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3196 // Owned by +--------+ | |
| 3197 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3198 // | new |preserve| Must be even-aligned. | |
| 3199 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3200 // | | | | |
| 3201 // | |
| 3202 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3203 // known from SELF's arguments and the Java calling convention. | |
| 3204 // Region 6-7 is determined per call site. | |
| 3205 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3206 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3207 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3208 // incoming area, as the Java calling convention is completely under | |
| 3209 // the control of the AD file. Doubles can be sorted and packed to | |
| 3210 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3211 // varargs C calling conventions. | |
| 3212 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3213 // even aligned with pad0 as needed. | |
| 3214 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3215 // region 6-11 is even aligned; it may be padded out more so that | |
| 3216 // the region from SP to FP meets the minimum stack alignment. | |
| 3217 | |
| 3218 frame %{ | |
| 3219 // What direction does stack grow in (assumed to be same for native & Java) | |
| 3220 stack_direction(TOWARDS_LOW); | |
| 3221 | |
| 3222 // These two registers define part of the calling convention | |
| 3223 // between compiled code and the interpreter. | |
|
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3224 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C |
| 0 | 3225 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter |
| 3226 | |
| 3227 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3228 cisc_spilling_operand_name(indOffset); | |
| 3229 | |
| 3230 // Number of stack slots consumed by a Monitor enter | |
| 3231 #ifdef _LP64 | |
| 3232 sync_stack_slots(2); | |
| 3233 #else | |
| 3234 sync_stack_slots(1); | |
| 3235 #endif | |
| 3236 | |
| 3237 // Compiled code's Frame Pointer | |
| 3238 frame_pointer(R_SP); | |
| 3239 | |
| 3240 // Stack alignment requirement | |
| 3241 stack_alignment(StackAlignmentInBytes); | |
| 3242 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
| 3243 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
| 3244 | |
| 3245 // Number of stack slots between incoming argument block and the start of | |
| 3246 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3247 // EPILOG must remove this many slots. | |
| 3248 in_preserve_stack_slots(0); | |
| 3249 | |
| 3250 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3251 // for calls to C. Supports the var-args backing area for register parms. | |
| 3252 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
| 3253 #ifdef _LP64 | |
| 3254 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
| 3255 varargs_C_out_slots_killed(12); | |
| 3256 #else | |
| 3257 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
| 3258 varargs_C_out_slots_killed( 7); | |
| 3259 #endif | |
| 3260 | |
| 3261 // The after-PROLOG location of the return address. Location of | |
| 3262 // return address specifies a type (REG or STACK) and a number | |
| 3263 // representing the register number (i.e. - use a register name) or | |
| 3264 // stack slot. | |
| 3265 return_addr(REG R_I7); // Ret Addr is in register I7 | |
| 3266 | |
| 3267 // Body of function which returns an OptoRegs array locating | |
| 3268 // arguments either in registers or in stack slots for calling | |
| 3269 // java | |
| 3270 calling_convention %{ | |
| 3271 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
| 3272 | |
| 3273 %} | |
| 3274 | |
| 3275 // Body of function which returns an OptoRegs array locating | |
| 3276 // arguments either in registers or in stack slots for callin | |
| 3277 // C. | |
| 3278 c_calling_convention %{ | |
| 3279 // This is obviously always outgoing | |
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3280 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); |
| 0 | 3281 %} |
| 3282 | |
| 3283 // Location of native (C/C++) and interpreter return values. This is specified to | |
| 3284 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
| 3285 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
| 3286 // to and from the register pairs is done by the appropriate call and epilog | |
| 3287 // opcodes. This simplifies the register allocator. | |
| 3288 c_return_value %{ | |
| 3289 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3290 #ifdef _LP64 | |
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3291 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3292 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3293 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3294 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3295 #else // !_LP64 |
|
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3296 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3297 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
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3298 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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|
3299 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
| 0 | 3300 #endif |
| 3301 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3302 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3303 %} | |
| 3304 | |
| 3305 // Location of compiled Java return values. Same as C | |
| 3306 return_value %{ | |
| 3307 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3308 #ifdef _LP64 | |
|
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3309 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3310 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3311 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3312 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3313 #else // !_LP64 |
|
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3314 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3315 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
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3316 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3317 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
| 0 | 3318 #endif |
| 3319 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3320 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3321 %} | |
| 3322 | |
| 3323 %} | |
| 3324 | |
| 3325 | |
| 3326 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3327 //----------Operand Attributes------------------------------------------------- | |
| 3328 op_attrib op_cost(1); // Required cost attribute | |
| 3329 | |
| 3330 //----------Instruction Attributes--------------------------------------------- | |
| 3331 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
| 3842 | 3332 ins_attrib ins_size(32); // Required size attribute (in bits) |
| 3851 | 3333 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back |
| 3842 | 3334 ins_attrib ins_short_branch(0); // Required flag: is this instruction a |
| 3335 // non-matching short branch variant of some | |
| 0 | 3336 // long branch? |
| 3337 | |
| 3338 //----------OPERANDS----------------------------------------------------------- | |
| 3339 // Operand definitions must precede instruction definitions for correct parsing | |
| 3340 // in the ADLC because operands constitute user defined types which are used in | |
| 3341 // instruction definitions. | |
| 3342 | |
| 3343 //----------Simple Operands---------------------------------------------------- | |
| 3344 // Immediate Operands | |
| 3345 // Integer Immediate: 32-bit | |
| 3346 operand immI() %{ | |
| 3347 match(ConI); | |
| 3348 | |
| 3349 op_cost(0); | |
| 3350 // formats are generated automatically for constants and base registers | |
| 3351 format %{ %} | |
| 3352 interface(CONST_INTER); | |
| 3353 %} | |
| 3354 | |
| 824 | 3355 // Integer Immediate: 8-bit |
| 3356 operand immI8() %{ | |
|
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3357 predicate(Assembler::is_simm8(n->get_int())); |
| 824 | 3358 match(ConI); |
| 3359 op_cost(0); | |
| 3360 format %{ %} | |
| 3361 interface(CONST_INTER); | |
| 3362 %} | |
| 3363 | |
| 0 | 3364 // Integer Immediate: 13-bit |
| 3365 operand immI13() %{ | |
| 3366 predicate(Assembler::is_simm13(n->get_int())); | |
| 3367 match(ConI); | |
| 3368 op_cost(0); | |
| 3369 | |
| 3370 format %{ %} | |
| 3371 interface(CONST_INTER); | |
| 3372 %} | |
| 3373 | |
| 785 | 3374 // Integer Immediate: 13-bit minus 7 |
| 3375 operand immI13m7() %{ | |
| 3376 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); | |
| 3377 match(ConI); | |
| 3378 op_cost(0); | |
| 3379 | |
| 3380 format %{ %} | |
| 3381 interface(CONST_INTER); | |
| 3382 %} | |
| 3383 | |
| 824 | 3384 // Integer Immediate: 16-bit |
| 3385 operand immI16() %{ | |
|
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3386 predicate(Assembler::is_simm16(n->get_int())); |
| 824 | 3387 match(ConI); |
| 3388 op_cost(0); | |
| 3389 format %{ %} | |
| 3390 interface(CONST_INTER); | |
| 3391 %} | |
| 3392 | |
|
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3393 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13) |
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3394 operand immU12() %{ |
| 0 | 3395 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); |
| 3396 match(ConI); | |
| 3397 op_cost(0); | |
| 3398 | |
| 3399 format %{ %} | |
| 3400 interface(CONST_INTER); | |
| 3401 %} | |
| 3402 | |
| 3403 // Integer Immediate: 6-bit | |
| 3404 operand immU6() %{ | |
| 3405 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
| 3406 match(ConI); | |
| 3407 op_cost(0); | |
| 3408 format %{ %} | |
| 3409 interface(CONST_INTER); | |
| 3410 %} | |
| 3411 | |
| 3412 // Integer Immediate: 11-bit | |
| 3413 operand immI11() %{ | |
|
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3414 predicate(Assembler::is_simm11(n->get_int())); |
| 0 | 3415 match(ConI); |
| 3416 op_cost(0); | |
| 3417 format %{ %} | |
| 3418 interface(CONST_INTER); | |
| 3419 %} | |
| 3420 | |
| 3851 | 3421 // Integer Immediate: 5-bit |
| 3422 operand immI5() %{ | |
|
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3423 predicate(Assembler::is_simm5(n->get_int())); |
| 3851 | 3424 match(ConI); |
| 3425 op_cost(0); | |
| 3426 format %{ %} | |
| 3427 interface(CONST_INTER); | |
| 3428 %} | |
| 3429 | |
|
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3430 // Int Immediate non-negative |
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3431 operand immU31() |
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3432 %{ |
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3433 predicate(n->get_int() >= 0); |
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3434 match(ConI); |
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3435 |
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3436 op_cost(0); |
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3437 format %{ %} |
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3438 interface(CONST_INTER); |
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3439 %} |
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3440 |
| 0 | 3441 // Integer Immediate: 0-bit |
| 3442 operand immI0() %{ | |
| 3443 predicate(n->get_int() == 0); | |
| 3444 match(ConI); | |
| 3445 op_cost(0); | |
| 3446 | |
| 3447 format %{ %} | |
| 3448 interface(CONST_INTER); | |
| 3449 %} | |
| 3450 | |
| 3451 // Integer Immediate: the value 10 | |
| 3452 operand immI10() %{ | |
| 3453 predicate(n->get_int() == 10); | |
| 3454 match(ConI); | |
| 3455 op_cost(0); | |
| 3456 | |
| 3457 format %{ %} | |
| 3458 interface(CONST_INTER); | |
| 3459 %} | |
| 3460 | |
| 3461 // Integer Immediate: the values 0-31 | |
| 3462 operand immU5() %{ | |
| 3463 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
| 3464 match(ConI); | |
| 3465 op_cost(0); | |
| 3466 | |
| 3467 format %{ %} | |
| 3468 interface(CONST_INTER); | |
| 3469 %} | |
| 3470 | |
| 3471 // Integer Immediate: the values 1-31 | |
| 3472 operand immI_1_31() %{ | |
| 3473 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
| 3474 match(ConI); | |
| 3475 op_cost(0); | |
| 3476 | |
| 3477 format %{ %} | |
| 3478 interface(CONST_INTER); | |
| 3479 %} | |
| 3480 | |
| 3481 // Integer Immediate: the values 32-63 | |
| 3482 operand immI_32_63() %{ | |
| 3483 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
| 3484 match(ConI); | |
| 3485 op_cost(0); | |
| 3486 | |
| 3487 format %{ %} | |
| 3488 interface(CONST_INTER); | |
| 3489 %} | |
| 3490 | |
| 785 | 3491 // Immediates for special shifts (sign extend) |
| 3492 | |
| 3493 // Integer Immediate: the value 16 | |
| 3494 operand immI_16() %{ | |
| 3495 predicate(n->get_int() == 16); | |
| 3496 match(ConI); | |
| 3497 op_cost(0); | |
| 3498 | |
| 3499 format %{ %} | |
| 3500 interface(CONST_INTER); | |
| 3501 %} | |
| 3502 | |
| 3503 // Integer Immediate: the value 24 | |
| 3504 operand immI_24() %{ | |
| 3505 predicate(n->get_int() == 24); | |
| 3506 match(ConI); | |
| 3507 op_cost(0); | |
| 3508 | |
| 3509 format %{ %} | |
| 3510 interface(CONST_INTER); | |
| 3511 %} | |
| 3512 | |
| 0 | 3513 // Integer Immediate: the value 255 |
| 3514 operand immI_255() %{ | |
| 3515 predicate( n->get_int() == 255 ); | |
| 3516 match(ConI); | |
| 3517 op_cost(0); | |
| 3518 | |
| 3519 format %{ %} | |
| 3520 interface(CONST_INTER); | |
| 3521 %} | |
| 3522 | |
| 785 | 3523 // Integer Immediate: the value 65535 |
| 3524 operand immI_65535() %{ | |
| 3525 predicate(n->get_int() == 65535); | |
| 3526 match(ConI); | |
| 3527 op_cost(0); | |
| 3528 | |
| 3529 format %{ %} | |
| 3530 interface(CONST_INTER); | |
| 3531 %} | |
| 3532 | |
| 0 | 3533 // Long Immediate: the value FF |
| 3534 operand immL_FF() %{ | |
| 3535 predicate( n->get_long() == 0xFFL ); | |
| 3536 match(ConL); | |
| 3537 op_cost(0); | |
| 3538 | |
| 3539 format %{ %} | |
| 3540 interface(CONST_INTER); | |
| 3541 %} | |
| 3542 | |
| 3543 // Long Immediate: the value FFFF | |
| 3544 operand immL_FFFF() %{ | |
| 3545 predicate( n->get_long() == 0xFFFFL ); | |
| 3546 match(ConL); | |
| 3547 op_cost(0); | |
| 3548 | |
| 3549 format %{ %} | |
| 3550 interface(CONST_INTER); | |
| 3551 %} | |
| 3552 | |
| 3553 // Pointer Immediate: 32 or 64-bit | |
| 3554 operand immP() %{ | |
| 3555 match(ConP); | |
| 3556 | |
| 3557 op_cost(5); | |
| 3558 // formats are generated automatically for constants and base registers | |
| 3559 format %{ %} | |
| 3560 interface(CONST_INTER); | |
| 3561 %} | |
| 3562 | |
|
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3563 #ifdef _LP64 |
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3564 // Pointer Immediate: 64-bit |
| 2008 | 3565 operand immP_set() %{ |
| 2080 | 3566 predicate(!VM_Version::is_niagara_plus()); |
| 2008 | 3567 match(ConP); |
| 3568 | |
| 3569 op_cost(5); | |
| 3570 // formats are generated automatically for constants and base registers | |
| 3571 format %{ %} | |
| 3572 interface(CONST_INTER); | |
| 3573 %} | |
| 3574 | |
|
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3575 // Pointer Immediate: 64-bit |
| 2008 | 3576 // From Niagara2 processors on a load should be better than materializing. |
| 3577 operand immP_load() %{ | |
| 2080 | 3578 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); |
| 2008 | 3579 match(ConP); |
| 3580 | |
| 3581 op_cost(5); | |
| 3582 // formats are generated automatically for constants and base registers | |
| 3583 format %{ %} | |
| 3584 interface(CONST_INTER); | |
| 3585 %} | |
| 3586 | |
|
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3587 // Pointer Immediate: 64-bit |
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3588 operand immP_no_oop_cheap() %{ |
| 2080 | 3589 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); |
|
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3590 match(ConP); |
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3591 |
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3592 op_cost(5); |
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3593 // formats are generated automatically for constants and base registers |
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3594 format %{ %} |
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3595 interface(CONST_INTER); |
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3596 %} |
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3597 #endif |
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3598 |
| 0 | 3599 operand immP13() %{ |
| 3600 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
| 3601 match(ConP); | |
| 3602 op_cost(0); | |
| 3603 | |
| 3604 format %{ %} | |
| 3605 interface(CONST_INTER); | |
| 3606 %} | |
| 3607 | |
| 3608 operand immP0() %{ | |
| 3609 predicate(n->get_ptr() == 0); | |
| 3610 match(ConP); | |
| 3611 op_cost(0); | |
| 3612 | |
| 3613 format %{ %} | |
| 3614 interface(CONST_INTER); | |
| 3615 %} | |
| 3616 | |
| 3617 operand immP_poll() %{ | |
| 3618 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
| 3619 match(ConP); | |
| 3620 | |
| 3621 // formats are generated automatically for constants and base registers | |
| 3622 format %{ %} | |
| 3623 interface(CONST_INTER); | |
| 3624 %} | |
| 3625 | |
|
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3626 // Pointer Immediate |
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3627 operand immN() |
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3628 %{ |
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3629 match(ConN); |
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3630 |
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3631 op_cost(10); |
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3632 format %{ %} |
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3633 interface(CONST_INTER); |
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3634 %} |
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3635 |
|
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3636 operand immNKlass() |
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3637 %{ |
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3638 match(ConNKlass); |
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3639 |
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3640 op_cost(10); |
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3641 format %{ %} |
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3642 interface(CONST_INTER); |
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3643 %} |
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3644 |
|
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3645 // NULL Pointer Immediate |
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3646 operand immN0() |
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3647 %{ |
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3648 predicate(n->get_narrowcon() == 0); |
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3649 match(ConN); |
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3650 |
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3651 op_cost(0); |
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3652 format %{ %} |
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3653 interface(CONST_INTER); |
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3654 %} |
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3655 |
| 0 | 3656 operand immL() %{ |
| 3657 match(ConL); | |
| 3658 op_cost(40); | |
| 3659 // formats are generated automatically for constants and base registers | |
| 3660 format %{ %} | |
| 3661 interface(CONST_INTER); | |
| 3662 %} | |
| 3663 | |
| 3664 operand immL0() %{ | |
| 3665 predicate(n->get_long() == 0L); | |
| 3666 match(ConL); | |
| 3667 op_cost(0); | |
| 3668 // formats are generated automatically for constants and base registers | |
| 3669 format %{ %} | |
| 3670 interface(CONST_INTER); | |
| 3671 %} | |
| 3672 | |
| 3851 | 3673 // Integer Immediate: 5-bit |
| 3674 operand immL5() %{ | |
|
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3675 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long())); |
| 3851 | 3676 match(ConL); |
| 3677 op_cost(0); | |
| 3678 format %{ %} | |
| 3679 interface(CONST_INTER); | |
| 3680 %} | |
| 3681 | |
| 0 | 3682 // Long Immediate: 13-bit |
| 3683 operand immL13() %{ | |
| 3684 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
| 3685 match(ConL); | |
| 3686 op_cost(0); | |
| 3687 | |
| 3688 format %{ %} | |
| 3689 interface(CONST_INTER); | |
| 3690 %} | |
| 3691 | |
| 785 | 3692 // Long Immediate: 13-bit minus 7 |
| 3693 operand immL13m7() %{ | |
| 3694 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); | |
| 3695 match(ConL); | |
| 3696 op_cost(0); | |
| 3697 | |
| 3698 format %{ %} | |
| 3699 interface(CONST_INTER); | |
| 3700 %} | |
| 3701 | |
| 0 | 3702 // Long Immediate: low 32-bit mask |
| 3703 operand immL_32bits() %{ | |
| 3704 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3705 match(ConL); | |
| 3706 op_cost(0); | |
| 3707 | |
| 3708 format %{ %} | |
| 3709 interface(CONST_INTER); | |
| 3710 %} | |
| 3711 | |
| 2008 | 3712 // Long Immediate: cheap (materialize in <= 3 instructions) |
| 3713 operand immL_cheap() %{ | |
| 2080 | 3714 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); |
| 2008 | 3715 match(ConL); |
| 3716 op_cost(0); | |
| 3717 | |
| 3718 format %{ %} | |
| 3719 interface(CONST_INTER); | |
| 3720 %} | |
| 3721 | |
| 3722 // Long Immediate: expensive (materialize in > 3 instructions) | |
| 3723 operand immL_expensive() %{ | |
| 2080 | 3724 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3); |
| 2008 | 3725 match(ConL); |
| 3726 op_cost(0); | |
| 3727 | |
| 3728 format %{ %} | |
| 3729 interface(CONST_INTER); | |
| 3730 %} | |
| 3731 | |
| 0 | 3732 // Double Immediate |
| 3733 operand immD() %{ | |
| 3734 match(ConD); | |
| 3735 | |
| 3736 op_cost(40); | |
| 3737 format %{ %} | |
| 3738 interface(CONST_INTER); | |
| 3739 %} | |
| 3740 | |
| 3741 operand immD0() %{ | |
| 3742 #ifdef _LP64 | |
| 3743 // on 64-bit architectures this comparision is faster | |
| 3744 predicate(jlong_cast(n->getd()) == 0); | |
| 3745 #else | |
| 3746 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
| 3747 #endif | |
| 3748 match(ConD); | |
| 3749 | |
| 3750 op_cost(0); | |
| 3751 format %{ %} | |
| 3752 interface(CONST_INTER); | |
| 3753 %} | |
| 3754 | |
| 3755 // Float Immediate | |
| 3756 operand immF() %{ | |
| 3757 match(ConF); | |
| 3758 | |
| 3759 op_cost(20); | |
| 3760 format %{ %} | |
| 3761 interface(CONST_INTER); | |
| 3762 %} | |
| 3763 | |
| 3764 // Float Immediate: 0 | |
| 3765 operand immF0() %{ | |
| 3766 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
| 3767 match(ConF); | |
| 3768 | |
| 3769 op_cost(0); | |
| 3770 format %{ %} | |
| 3771 interface(CONST_INTER); | |
| 3772 %} | |
| 3773 | |
| 3774 // Integer Register Operands | |
| 3775 // Integer Register | |
| 3776 operand iRegI() %{ | |
| 3777 constraint(ALLOC_IN_RC(int_reg)); | |
| 3778 match(RegI); | |
| 3779 | |
| 3780 match(notemp_iRegI); | |
| 3781 match(g1RegI); | |
| 3782 match(o0RegI); | |
| 3783 match(iRegIsafe); | |
| 3784 | |
| 3785 format %{ %} | |
| 3786 interface(REG_INTER); | |
| 3787 %} | |
| 3788 | |
| 3789 operand notemp_iRegI() %{ | |
| 3790 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
| 3791 match(RegI); | |
| 3792 | |
| 3793 match(o0RegI); | |
| 3794 | |
| 3795 format %{ %} | |
| 3796 interface(REG_INTER); | |
| 3797 %} | |
| 3798 | |
| 3799 operand o0RegI() %{ | |
| 3800 constraint(ALLOC_IN_RC(o0_regI)); | |
| 3801 match(iRegI); | |
| 3802 | |
| 3803 format %{ %} | |
| 3804 interface(REG_INTER); | |
| 3805 %} | |
| 3806 | |
| 3807 // Pointer Register | |
| 3808 operand iRegP() %{ | |
| 3809 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3810 match(RegP); | |
| 3811 | |
| 3812 match(lock_ptr_RegP); | |
| 3813 match(g1RegP); | |
| 3814 match(g2RegP); | |
| 3815 match(g3RegP); | |
| 3816 match(g4RegP); | |
| 3817 match(i0RegP); | |
| 3818 match(o0RegP); | |
| 3819 match(o1RegP); | |
| 3820 match(l7RegP); | |
| 3821 | |
| 3822 format %{ %} | |
| 3823 interface(REG_INTER); | |
| 3824 %} | |
| 3825 | |
| 3826 operand sp_ptr_RegP() %{ | |
| 3827 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 3828 match(RegP); | |
| 3829 match(iRegP); | |
| 3830 | |
| 3831 format %{ %} | |
| 3832 interface(REG_INTER); | |
| 3833 %} | |
| 3834 | |
| 3835 operand lock_ptr_RegP() %{ | |
| 3836 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
| 3837 match(RegP); | |
| 3838 match(i0RegP); | |
| 3839 match(o0RegP); | |
| 3840 match(o1RegP); | |
| 3841 match(l7RegP); | |
| 3842 | |
| 3843 format %{ %} | |
| 3844 interface(REG_INTER); | |
| 3845 %} | |
| 3846 | |
| 3847 operand g1RegP() %{ | |
| 3848 constraint(ALLOC_IN_RC(g1_regP)); | |
| 3849 match(iRegP); | |
| 3850 | |
| 3851 format %{ %} | |
| 3852 interface(REG_INTER); | |
| 3853 %} | |
| 3854 | |
| 3855 operand g2RegP() %{ | |
| 3856 constraint(ALLOC_IN_RC(g2_regP)); | |
| 3857 match(iRegP); | |
| 3858 | |
| 3859 format %{ %} | |
| 3860 interface(REG_INTER); | |
| 3861 %} | |
| 3862 | |
| 3863 operand g3RegP() %{ | |
| 3864 constraint(ALLOC_IN_RC(g3_regP)); | |
| 3865 match(iRegP); | |
| 3866 | |
| 3867 format %{ %} | |
| 3868 interface(REG_INTER); | |
| 3869 %} | |
| 3870 | |
| 3871 operand g1RegI() %{ | |
| 3872 constraint(ALLOC_IN_RC(g1_regI)); | |
| 3873 match(iRegI); | |
| 3874 | |
| 3875 format %{ %} | |
| 3876 interface(REG_INTER); | |
| 3877 %} | |
| 3878 | |
| 3879 operand g3RegI() %{ | |
| 3880 constraint(ALLOC_IN_RC(g3_regI)); | |
| 3881 match(iRegI); | |
| 3882 | |
| 3883 format %{ %} | |
| 3884 interface(REG_INTER); | |
| 3885 %} | |
| 3886 | |
| 3887 operand g4RegI() %{ | |
| 3888 constraint(ALLOC_IN_RC(g4_regI)); | |
| 3889 match(iRegI); | |
| 3890 | |
| 3891 format %{ %} | |
| 3892 interface(REG_INTER); | |
| 3893 %} | |
| 3894 | |
| 3895 operand g4RegP() %{ | |
| 3896 constraint(ALLOC_IN_RC(g4_regP)); | |
| 3897 match(iRegP); | |
| 3898 | |
| 3899 format %{ %} | |
| 3900 interface(REG_INTER); | |
| 3901 %} | |
| 3902 | |
| 3903 operand i0RegP() %{ | |
| 3904 constraint(ALLOC_IN_RC(i0_regP)); | |
| 3905 match(iRegP); | |
| 3906 | |
| 3907 format %{ %} | |
| 3908 interface(REG_INTER); | |
| 3909 %} | |
| 3910 | |
| 3911 operand o0RegP() %{ | |
| 3912 constraint(ALLOC_IN_RC(o0_regP)); | |
| 3913 match(iRegP); | |
| 3914 | |
| 3915 format %{ %} | |
| 3916 interface(REG_INTER); | |
| 3917 %} | |
| 3918 | |
| 3919 operand o1RegP() %{ | |
| 3920 constraint(ALLOC_IN_RC(o1_regP)); | |
| 3921 match(iRegP); | |
| 3922 | |
| 3923 format %{ %} | |
| 3924 interface(REG_INTER); | |
| 3925 %} | |
| 3926 | |
| 3927 operand o2RegP() %{ | |
| 3928 constraint(ALLOC_IN_RC(o2_regP)); | |
| 3929 match(iRegP); | |
| 3930 | |
| 3931 format %{ %} | |
| 3932 interface(REG_INTER); | |
| 3933 %} | |
| 3934 | |
| 3935 operand o7RegP() %{ | |
| 3936 constraint(ALLOC_IN_RC(o7_regP)); | |
| 3937 match(iRegP); | |
| 3938 | |
| 3939 format %{ %} | |
| 3940 interface(REG_INTER); | |
| 3941 %} | |
| 3942 | |
| 3943 operand l7RegP() %{ | |
| 3944 constraint(ALLOC_IN_RC(l7_regP)); | |
| 3945 match(iRegP); | |
| 3946 | |
| 3947 format %{ %} | |
| 3948 interface(REG_INTER); | |
| 3949 %} | |
| 3950 | |
| 3951 operand o7RegI() %{ | |
| 3952 constraint(ALLOC_IN_RC(o7_regI)); | |
| 3953 match(iRegI); | |
| 3954 | |
| 3955 format %{ %} | |
| 3956 interface(REG_INTER); | |
| 3957 %} | |
| 3958 | |
|
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3959 operand iRegN() %{ |
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3960 constraint(ALLOC_IN_RC(int_reg)); |
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3961 match(RegN); |
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3962 |
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3963 format %{ %} |
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3964 interface(REG_INTER); |
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3965 %} |
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3966 |
| 0 | 3967 // Long Register |
| 3968 operand iRegL() %{ | |
| 3969 constraint(ALLOC_IN_RC(long_reg)); | |
| 3970 match(RegL); | |
| 3971 | |
| 3972 format %{ %} | |
| 3973 interface(REG_INTER); | |
| 3974 %} | |
| 3975 | |
| 3976 operand o2RegL() %{ | |
| 3977 constraint(ALLOC_IN_RC(o2_regL)); | |
| 3978 match(iRegL); | |
| 3979 | |
| 3980 format %{ %} | |
| 3981 interface(REG_INTER); | |
| 3982 %} | |
| 3983 | |
| 3984 operand o7RegL() %{ | |
| 3985 constraint(ALLOC_IN_RC(o7_regL)); | |
| 3986 match(iRegL); | |
| 3987 | |
| 3988 format %{ %} | |
| 3989 interface(REG_INTER); | |
| 3990 %} | |
| 3991 | |
| 3992 operand g1RegL() %{ | |
| 3993 constraint(ALLOC_IN_RC(g1_regL)); | |
| 3994 match(iRegL); | |
| 3995 | |
| 3996 format %{ %} | |
| 3997 interface(REG_INTER); | |
| 3998 %} | |
| 3999 | |
|
420
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4000 operand g3RegL() %{ |
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4001 constraint(ALLOC_IN_RC(g3_regL)); |
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4002 match(iRegL); |
|
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4003 |
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4004 format %{ %} |
|
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4005 interface(REG_INTER); |
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4006 %} |
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4007 |
| 0 | 4008 // Int Register safe |
| 4009 // This is 64bit safe | |
| 4010 operand iRegIsafe() %{ | |
| 4011 constraint(ALLOC_IN_RC(long_reg)); | |
| 4012 | |
| 4013 match(iRegI); | |
| 4014 | |
| 4015 format %{ %} | |
| 4016 interface(REG_INTER); | |
| 4017 %} | |
| 4018 | |
| 4019 // Condition Code Flag Register | |
| 4020 operand flagsReg() %{ | |
| 4021 constraint(ALLOC_IN_RC(int_flags)); | |
| 4022 match(RegFlags); | |
| 4023 | |
| 4024 format %{ "ccr" %} // both ICC and XCC | |
| 4025 interface(REG_INTER); | |
| 4026 %} | |
| 4027 | |
| 4028 // Condition Code Register, unsigned comparisons. | |
| 4029 operand flagsRegU() %{ | |
| 4030 constraint(ALLOC_IN_RC(int_flags)); | |
| 4031 match(RegFlags); | |
| 4032 | |
| 4033 format %{ "icc_U" %} | |
| 4034 interface(REG_INTER); | |
| 4035 %} | |
| 4036 | |
| 4037 // Condition Code Register, pointer comparisons. | |
| 4038 operand flagsRegP() %{ | |
| 4039 constraint(ALLOC_IN_RC(int_flags)); | |
| 4040 match(RegFlags); | |
| 4041 | |
| 4042 #ifdef _LP64 | |
| 4043 format %{ "xcc_P" %} | |
| 4044 #else | |
| 4045 format %{ "icc_P" %} | |
| 4046 #endif | |
| 4047 interface(REG_INTER); | |
| 4048 %} | |
| 4049 | |
| 4050 // Condition Code Register, long comparisons. | |
| 4051 operand flagsRegL() %{ | |
| 4052 constraint(ALLOC_IN_RC(int_flags)); | |
| 4053 match(RegFlags); | |
| 4054 | |
| 4055 format %{ "xcc_L" %} | |
| 4056 interface(REG_INTER); | |
| 4057 %} | |
| 4058 | |
| 4059 // Condition Code Register, floating comparisons, unordered same as "less". | |
| 4060 operand flagsRegF() %{ | |
| 4061 constraint(ALLOC_IN_RC(float_flags)); | |
| 4062 match(RegFlags); | |
| 4063 match(flagsRegF0); | |
| 4064 | |
| 4065 format %{ %} | |
| 4066 interface(REG_INTER); | |
| 4067 %} | |
| 4068 | |
| 4069 operand flagsRegF0() %{ | |
| 4070 constraint(ALLOC_IN_RC(float_flag0)); | |
| 4071 match(RegFlags); | |
| 4072 | |
| 4073 format %{ %} | |
| 4074 interface(REG_INTER); | |
| 4075 %} | |
| 4076 | |
| 4077 | |
| 4078 // Condition Code Flag Register used by long compare | |
| 4079 operand flagsReg_long_LTGE() %{ | |
| 4080 constraint(ALLOC_IN_RC(int_flags)); | |
| 4081 match(RegFlags); | |
| 4082 format %{ "icc_LTGE" %} | |
| 4083 interface(REG_INTER); | |
| 4084 %} | |
| 4085 operand flagsReg_long_EQNE() %{ | |
| 4086 constraint(ALLOC_IN_RC(int_flags)); | |
| 4087 match(RegFlags); | |
| 4088 format %{ "icc_EQNE" %} | |
| 4089 interface(REG_INTER); | |
| 4090 %} | |
| 4091 operand flagsReg_long_LEGT() %{ | |
| 4092 constraint(ALLOC_IN_RC(int_flags)); | |
| 4093 match(RegFlags); | |
| 4094 format %{ "icc_LEGT" %} | |
| 4095 interface(REG_INTER); | |
| 4096 %} | |
| 4097 | |
| 4098 | |
| 4099 operand regD() %{ | |
| 4100 constraint(ALLOC_IN_RC(dflt_reg)); | |
| 4101 match(RegD); | |
| 4102 | |
| 551 | 4103 match(regD_low); |
| 4104 | |
| 0 | 4105 format %{ %} |
| 4106 interface(REG_INTER); | |
| 4107 %} | |
| 4108 | |
| 4109 operand regF() %{ | |
| 4110 constraint(ALLOC_IN_RC(sflt_reg)); | |
| 4111 match(RegF); | |
| 4112 | |
| 4113 format %{ %} | |
| 4114 interface(REG_INTER); | |
| 4115 %} | |
| 4116 | |
| 4117 operand regD_low() %{ | |
| 4118 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
| 551 | 4119 match(regD); |
| 0 | 4120 |
| 4121 format %{ %} | |
| 4122 interface(REG_INTER); | |
| 4123 %} | |
| 4124 | |
| 4125 // Special Registers | |
| 4126 | |
| 4127 // Method Register | |
| 4128 operand inline_cache_regP(iRegP reg) %{ | |
| 4129 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
| 4130 match(reg); | |
| 4131 format %{ %} | |
| 4132 interface(REG_INTER); | |
| 4133 %} | |
| 4134 | |
| 4135 operand interpreter_method_oop_regP(iRegP reg) %{ | |
| 4136 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
| 4137 match(reg); | |
| 4138 format %{ %} | |
| 4139 interface(REG_INTER); | |
| 4140 %} | |
| 4141 | |
| 4142 | |
| 4143 //----------Complex Operands--------------------------------------------------- | |
| 4144 // Indirect Memory Reference | |
| 4145 operand indirect(sp_ptr_RegP reg) %{ | |
| 4146 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4147 match(reg); | |
| 4148 | |
| 4149 op_cost(100); | |
| 4150 format %{ "[$reg]" %} | |
| 4151 interface(MEMORY_INTER) %{ | |
| 4152 base($reg); | |
| 4153 index(0x0); | |
| 4154 scale(0x0); | |
| 4155 disp(0x0); | |
| 4156 %} | |
| 4157 %} | |
| 4158 | |
| 785 | 4159 // Indirect with simm13 Offset |
| 0 | 4160 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
| 4161 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4162 match(AddP reg offset); | |
| 4163 | |
| 4164 op_cost(100); | |
| 4165 format %{ "[$reg + $offset]" %} | |
| 4166 interface(MEMORY_INTER) %{ | |
| 4167 base($reg); | |
| 4168 index(0x0); | |
| 4169 scale(0x0); | |
| 4170 disp($offset); | |
| 4171 %} | |
| 4172 %} | |
| 4173 | |
| 785 | 4174 // Indirect with simm13 Offset minus 7 |
| 4175 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ | |
| 4176 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4177 match(AddP reg offset); | |
| 4178 | |
| 4179 op_cost(100); | |
| 4180 format %{ "[$reg + $offset]" %} | |
| 4181 interface(MEMORY_INTER) %{ | |
| 4182 base($reg); | |
| 4183 index(0x0); | |
| 4184 scale(0x0); | |
| 4185 disp($offset); | |
| 4186 %} | |
| 4187 %} | |
| 4188 | |
| 0 | 4189 // Note: Intel has a swapped version also, like this: |
| 4190 //operand indOffsetX(iRegI reg, immP offset) %{ | |
| 4191 // constraint(ALLOC_IN_RC(int_reg)); | |
| 4192 // match(AddP offset reg); | |
| 4193 // | |
| 4194 // op_cost(100); | |
| 4195 // format %{ "[$reg + $offset]" %} | |
| 4196 // interface(MEMORY_INTER) %{ | |
| 4197 // base($reg); | |
| 4198 // index(0x0); | |
| 4199 // scale(0x0); | |
| 4200 // disp($offset); | |
| 4201 // %} | |
| 4202 //%} | |
| 4203 //// However, it doesn't make sense for SPARC, since | |
| 4204 // we have no particularly good way to embed oops in | |
| 4205 // single instructions. | |
| 4206 | |
| 4207 // Indirect with Register Index | |
| 4208 operand indIndex(iRegP addr, iRegX index) %{ | |
| 4209 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4210 match(AddP addr index); | |
| 4211 | |
| 4212 op_cost(100); | |
| 4213 format %{ "[$addr + $index]" %} | |
| 4214 interface(MEMORY_INTER) %{ | |
| 4215 base($addr); | |
| 4216 index($index); | |
| 4217 scale(0x0); | |
| 4218 disp(0x0); | |
| 4219 %} | |
| 4220 %} | |
| 4221 | |
| 4222 //----------Special Memory Operands-------------------------------------------- | |
| 4223 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4224 // values on the stack where a match requires a value to | |
| 4225 // flow through memory. | |
| 4226 operand stackSlotI(sRegI reg) %{ | |
| 4227 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4228 op_cost(100); | |
| 4229 //match(RegI); | |
| 4230 format %{ "[$reg]" %} | |
| 4231 interface(MEMORY_INTER) %{ | |
| 4232 base(0xE); // R_SP | |
| 4233 index(0x0); | |
| 4234 scale(0x0); | |
| 4235 disp($reg); // Stack Offset | |
| 4236 %} | |
| 4237 %} | |
| 4238 | |
| 4239 operand stackSlotP(sRegP reg) %{ | |
| 4240 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4241 op_cost(100); | |
| 4242 //match(RegP); | |
| 4243 format %{ "[$reg]" %} | |
| 4244 interface(MEMORY_INTER) %{ | |
| 4245 base(0xE); // R_SP | |
| 4246 index(0x0); | |
| 4247 scale(0x0); | |
| 4248 disp($reg); // Stack Offset | |
| 4249 %} | |
| 4250 %} | |
| 4251 | |
| 4252 operand stackSlotF(sRegF reg) %{ | |
| 4253 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4254 op_cost(100); | |
| 4255 //match(RegF); | |
| 4256 format %{ "[$reg]" %} | |
| 4257 interface(MEMORY_INTER) %{ | |
| 4258 base(0xE); // R_SP | |
| 4259 index(0x0); | |
| 4260 scale(0x0); | |
| 4261 disp($reg); // Stack Offset | |
| 4262 %} | |
| 4263 %} | |
| 4264 operand stackSlotD(sRegD reg) %{ | |
| 4265 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4266 op_cost(100); | |
| 4267 //match(RegD); | |
| 4268 format %{ "[$reg]" %} | |
| 4269 interface(MEMORY_INTER) %{ | |
| 4270 base(0xE); // R_SP | |
| 4271 index(0x0); | |
| 4272 scale(0x0); | |
| 4273 disp($reg); // Stack Offset | |
| 4274 %} | |
| 4275 %} | |
| 4276 operand stackSlotL(sRegL reg) %{ | |
| 4277 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4278 op_cost(100); | |
| 4279 //match(RegL); | |
| 4280 format %{ "[$reg]" %} | |
| 4281 interface(MEMORY_INTER) %{ | |
| 4282 base(0xE); // R_SP | |
| 4283 index(0x0); | |
| 4284 scale(0x0); | |
| 4285 disp($reg); // Stack Offset | |
| 4286 %} | |
| 4287 %} | |
| 4288 | |
| 4289 // Operands for expressing Control Flow | |
| 4290 // NOTE: Label is a predefined operand which should not be redefined in | |
| 4291 // the AD file. It is generically handled within the ADLC. | |
| 4292 | |
| 4293 //----------Conditional Branch Operands---------------------------------------- | |
| 4294 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4295 // the following set of codes: | |
| 4296 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4297 // | |
| 4298 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4299 // by the comparison instruction that sets a condition code flags register. | |
| 4300 // That result is represented by a flags operand whose subtype is appropriate | |
| 4301 // to the unsignedness (etc.) of the comparison. | |
| 4302 // | |
| 4303 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4304 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4305 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4306 | |
| 4307 operand cmpOp() %{ | |
| 4308 match(Bool); | |
| 4309 | |
| 4310 format %{ "" %} | |
| 4311 interface(COND_INTER) %{ | |
| 4312 equal(0x1); | |
| 4313 not_equal(0x9); | |
| 4314 less(0x3); | |
| 4315 greater_equal(0xB); | |
| 4316 less_equal(0x2); | |
| 4317 greater(0xA); | |
| 12323 | 4318 overflow(0x7); |
| 4319 no_overflow(0xF); | |
| 0 | 4320 %} |
| 4321 %} | |
| 4322 | |
| 4323 // Comparison Op, unsigned | |
| 4324 operand cmpOpU() %{ | |
| 4325 match(Bool); | |
| 12323 | 4326 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
| 4327 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
| 0 | 4328 |
| 4329 format %{ "u" %} | |
| 4330 interface(COND_INTER) %{ | |
| 4331 equal(0x1); | |
| 4332 not_equal(0x9); | |
| 4333 less(0x5); | |
| 4334 greater_equal(0xD); | |
| 4335 less_equal(0x4); | |
| 4336 greater(0xC); | |
| 12323 | 4337 overflow(0x7); |
| 4338 no_overflow(0xF); | |
| 0 | 4339 %} |
| 4340 %} | |
| 4341 | |
| 4342 // Comparison Op, pointer (same as unsigned) | |
| 4343 operand cmpOpP() %{ | |
| 4344 match(Bool); | |
| 12323 | 4345 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
| 4346 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
| 0 | 4347 |
| 4348 format %{ "p" %} | |
| 4349 interface(COND_INTER) %{ | |
| 4350 equal(0x1); | |
| 4351 not_equal(0x9); | |
| 4352 less(0x5); | |
| 4353 greater_equal(0xD); | |
| 4354 less_equal(0x4); | |
| 4355 greater(0xC); | |
| 12323 | 4356 overflow(0x7); |
| 4357 no_overflow(0xF); | |
| 0 | 4358 %} |
| 4359 %} | |
| 4360 | |
| 4361 // Comparison Op, branch-register encoding | |
| 4362 operand cmpOp_reg() %{ | |
| 4363 match(Bool); | |
| 12323 | 4364 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
| 4365 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
| 0 | 4366 |
| 4367 format %{ "" %} | |
| 4368 interface(COND_INTER) %{ | |
| 4369 equal (0x1); | |
| 4370 not_equal (0x5); | |
| 4371 less (0x3); | |
| 4372 greater_equal(0x7); | |
| 4373 less_equal (0x2); | |
| 4374 greater (0x6); | |
| 12323 | 4375 overflow(0x7); // not supported |
| 4376 no_overflow(0xF); // not supported | |
| 0 | 4377 %} |
| 4378 %} | |
| 4379 | |
| 4380 // Comparison Code, floating, unordered same as less | |
| 4381 operand cmpOpF() %{ | |
| 4382 match(Bool); | |
| 12323 | 4383 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
| 4384 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
| 0 | 4385 |
| 4386 format %{ "fl" %} | |
| 4387 interface(COND_INTER) %{ | |
| 4388 equal(0x9); | |
| 4389 not_equal(0x1); | |
| 4390 less(0x3); | |
| 4391 greater_equal(0xB); | |
| 4392 less_equal(0xE); | |
| 4393 greater(0x6); | |
| 12323 | 4394 |
| 4395 overflow(0x7); // not supported | |
| 4396 no_overflow(0xF); // not supported | |
| 0 | 4397 %} |
| 4398 %} | |
| 4399 | |
| 4400 // Used by long compare | |
| 4401 operand cmpOp_commute() %{ | |
| 4402 match(Bool); | |
| 12323 | 4403 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
| 4404 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
| 0 | 4405 |
| 4406 format %{ "" %} | |
| 4407 interface(COND_INTER) %{ | |
| 4408 equal(0x1); | |
| 4409 not_equal(0x9); | |
| 4410 less(0xA); | |
| 4411 greater_equal(0x2); | |
| 4412 less_equal(0xB); | |
| 4413 greater(0x3); | |
| 12323 | 4414 overflow(0x7); |
| 4415 no_overflow(0xF); | |
| 0 | 4416 %} |
| 4417 %} | |
| 4418 | |
| 4419 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4420 // Operand Classes are groups of operands that are used to simplify | |
| 605 | 4421 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4422 // instructions for every form of operand when the instruction accepts |
| 4423 // multiple operand types with the same basic encoding and format. The classic | |
| 4424 // case of this is memory operands. | |
| 4425 opclass memory( indirect, indOffset13, indIndex ); | |
|
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|
4426 opclass indIndexMemory( indIndex ); |
| 0 | 4427 |
| 4428 //----------PIPELINE----------------------------------------------------------- | |
| 4429 pipeline %{ | |
| 4430 | |
| 4431 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4432 attributes %{ | |
| 4433 fixed_size_instructions; // Fixed size instructions | |
| 4434 branch_has_delay_slot; // Branch has delay slot following | |
| 4435 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
| 4436 instruction_unit_size = 4; // An instruction is 4 bytes long | |
| 4437 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4438 instruction_fetch_units = 1; // of 16 bytes | |
| 4439 | |
| 4440 // List of nop instructions | |
| 4441 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
| 4442 %} | |
| 4443 | |
| 4444 //----------RESOURCES---------------------------------------------------------- | |
| 4445 // Resources are the functional units available to the machine | |
| 4446 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
| 4447 | |
| 4448 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4449 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4450 | |
| 4451 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
| 4452 | |
| 4453 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4454 // Pipeline Classes describe the stages in which input and output are | |
| 4455 // referenced by the hardware pipeline. | |
| 4456 | |
| 4457 // Integer ALU reg-reg operation | |
| 4458 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4459 single_instruction; | |
| 4460 dst : E(write); | |
| 4461 src1 : R(read); | |
| 4462 src2 : R(read); | |
| 4463 IALU : R; | |
| 4464 %} | |
| 4465 | |
| 4466 // Integer ALU reg-reg long operation | |
| 4467 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4468 instruction_count(2); | |
| 4469 dst : E(write); | |
| 4470 src1 : R(read); | |
| 4471 src2 : R(read); | |
| 4472 IALU : R; | |
| 4473 IALU : R; | |
| 4474 %} | |
| 4475 | |
| 4476 // Integer ALU reg-reg long dependent operation | |
| 4477 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
| 4478 instruction_count(1); multiple_bundles; | |
| 4479 dst : E(write); | |
| 4480 src1 : R(read); | |
| 4481 src2 : R(read); | |
| 4482 cr : E(write); | |
| 4483 IALU : R(2); | |
| 4484 %} | |
| 4485 | |
| 4486 // Integer ALU reg-imm operaion | |
| 4487 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4488 single_instruction; | |
| 4489 dst : E(write); | |
| 4490 src1 : R(read); | |
| 4491 IALU : R; | |
| 4492 %} | |
| 4493 | |
| 4494 // Integer ALU reg-reg operation with condition code | |
| 4495 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
| 4496 single_instruction; | |
| 4497 dst : E(write); | |
| 4498 cr : E(write); | |
| 4499 src1 : R(read); | |
| 4500 src2 : R(read); | |
| 4501 IALU : R; | |
| 4502 %} | |
| 4503 | |
| 4504 // Integer ALU reg-imm operation with condition code | |
| 4505 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
| 4506 single_instruction; | |
| 4507 dst : E(write); | |
| 4508 cr : E(write); | |
| 4509 src1 : R(read); | |
| 4510 IALU : R; | |
| 4511 %} | |
| 4512 | |
| 4513 // Integer ALU zero-reg operation | |
| 4514 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 4515 single_instruction; | |
| 4516 dst : E(write); | |
| 4517 src2 : R(read); | |
| 4518 IALU : R; | |
| 4519 %} | |
| 4520 | |
| 4521 // Integer ALU zero-reg operation with condition code only | |
| 4522 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
| 4523 single_instruction; | |
| 4524 cr : E(write); | |
| 4525 src : R(read); | |
| 4526 IALU : R; | |
| 4527 %} | |
| 4528 | |
| 4529 // Integer ALU reg-reg operation with condition code only | |
| 4530 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4531 single_instruction; | |
| 4532 cr : E(write); | |
| 4533 src1 : R(read); | |
| 4534 src2 : R(read); | |
| 4535 IALU : R; | |
| 4536 %} | |
| 4537 | |
| 4538 // Integer ALU reg-imm operation with condition code only | |
| 4539 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4540 single_instruction; | |
| 4541 cr : E(write); | |
| 4542 src1 : R(read); | |
| 4543 IALU : R; | |
| 4544 %} | |
| 4545 | |
| 4546 // Integer ALU reg-reg-zero operation with condition code only | |
| 4547 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
| 4548 single_instruction; | |
| 4549 cr : E(write); | |
| 4550 src1 : R(read); | |
| 4551 src2 : R(read); | |
| 4552 IALU : R; | |
| 4553 %} | |
| 4554 | |
| 4555 // Integer ALU reg-imm-zero operation with condition code only | |
| 4556 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
| 4557 single_instruction; | |
| 4558 cr : E(write); | |
| 4559 src1 : R(read); | |
| 4560 IALU : R; | |
| 4561 %} | |
| 4562 | |
| 4563 // Integer ALU reg-reg operation with condition code, src1 modified | |
| 4564 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4565 single_instruction; | |
| 4566 cr : E(write); | |
| 4567 src1 : E(write); | |
| 4568 src1 : R(read); | |
| 4569 src2 : R(read); | |
| 4570 IALU : R; | |
| 4571 %} | |
| 4572 | |
| 4573 // Integer ALU reg-imm operation with condition code, src1 modified | |
| 4574 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4575 single_instruction; | |
| 4576 cr : E(write); | |
| 4577 src1 : E(write); | |
| 4578 src1 : R(read); | |
| 4579 IALU : R; | |
| 4580 %} | |
| 4581 | |
| 4582 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
| 4583 multiple_bundles; | |
| 4584 dst : E(write)+4; | |
| 4585 cr : E(write); | |
| 4586 src1 : R(read); | |
| 4587 src2 : R(read); | |
| 4588 IALU : R(3); | |
| 4589 BR : R(2); | |
| 4590 %} | |
| 4591 | |
| 4592 // Integer ALU operation | |
| 4593 pipe_class ialu_none(iRegI dst) %{ | |
| 4594 single_instruction; | |
| 4595 dst : E(write); | |
| 4596 IALU : R; | |
| 4597 %} | |
| 4598 | |
| 4599 // Integer ALU reg operation | |
| 4600 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
| 4601 single_instruction; may_have_no_code; | |
| 4602 dst : E(write); | |
| 4603 src : R(read); | |
| 4604 IALU : R; | |
| 4605 %} | |
| 4606 | |
| 4607 // Integer ALU reg conditional operation | |
| 4608 // This instruction has a 1 cycle stall, and cannot execute | |
| 4609 // in the same cycle as the instruction setting the condition | |
| 4610 // code. We kludge this by pretending to read the condition code | |
| 4611 // 1 cycle earlier, and by marking the functional units as busy | |
| 4612 // for 2 cycles with the result available 1 cycle later than | |
| 4613 // is really the case. | |
| 4614 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
| 4615 single_instruction; | |
| 4616 op2_out : C(write); | |
| 4617 op1 : R(read); | |
| 4618 cr : R(read); // This is really E, with a 1 cycle stall | |
| 4619 BR : R(2); | |
| 4620 MS : R(2); | |
| 4621 %} | |
| 4622 | |
| 4623 #ifdef _LP64 | |
| 4624 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
| 4625 instruction_count(1); multiple_bundles; | |
| 4626 dst : C(write)+1; | |
| 4627 src : R(read)+1; | |
| 4628 IALU : R(1); | |
| 4629 BR : E(2); | |
| 4630 MS : E(2); | |
| 4631 %} | |
| 4632 #endif | |
| 4633 | |
| 4634 // Integer ALU reg operation | |
| 4635 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
| 4636 single_instruction; may_have_no_code; | |
| 4637 dst : E(write); | |
| 4638 src : R(read); | |
| 4639 IALU : R; | |
| 4640 %} | |
| 4641 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
| 4642 single_instruction; may_have_no_code; | |
| 4643 dst : E(write); | |
| 4644 src : R(read); | |
| 4645 IALU : R; | |
| 4646 %} | |
| 4647 | |
| 4648 // Two integer ALU reg operations | |
| 4649 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
| 4650 instruction_count(2); | |
| 4651 dst : E(write); | |
| 4652 src : R(read); | |
| 4653 A0 : R; | |
| 4654 A1 : R; | |
| 4655 %} | |
| 4656 | |
| 4657 // Two integer ALU reg operations | |
| 4658 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
| 4659 instruction_count(2); may_have_no_code; | |
| 4660 dst : E(write); | |
| 4661 src : R(read); | |
| 4662 A0 : R; | |
| 4663 A1 : R; | |
| 4664 %} | |
| 4665 | |
| 4666 // Integer ALU imm operation | |
| 4667 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
| 4668 single_instruction; | |
| 4669 dst : E(write); | |
| 4670 IALU : R; | |
| 4671 %} | |
| 4672 | |
| 4673 // Integer ALU reg-reg with carry operation | |
| 4674 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
| 4675 single_instruction; | |
| 4676 dst : E(write); | |
| 4677 src1 : R(read); | |
| 4678 src2 : R(read); | |
| 4679 IALU : R; | |
| 4680 %} | |
| 4681 | |
| 4682 // Integer ALU cc operation | |
| 4683 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
| 4684 single_instruction; | |
| 4685 dst : E(write); | |
| 4686 cc : R(read); | |
| 4687 IALU : R; | |
| 4688 %} | |
| 4689 | |
| 4690 // Integer ALU cc / second IALU operation | |
| 4691 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
| 4692 instruction_count(1); multiple_bundles; | |
| 4693 dst : E(write)+1; | |
| 4694 src : R(read); | |
| 4695 IALU : R; | |
| 4696 %} | |
| 4697 | |
| 4698 // Integer ALU cc / second IALU operation | |
| 4699 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
| 4700 instruction_count(1); multiple_bundles; | |
| 4701 dst : E(write)+1; | |
| 4702 p : R(read); | |
| 4703 q : R(read); | |
| 4704 IALU : R; | |
| 4705 %} | |
| 4706 | |
| 4707 // Integer ALU hi-lo-reg operation | |
| 4708 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
| 4709 instruction_count(1); multiple_bundles; | |
| 4710 dst : E(write)+1; | |
| 4711 IALU : R(2); | |
| 4712 %} | |
| 4713 | |
| 4714 // Float ALU hi-lo-reg operation (with temp) | |
| 4715 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
| 4716 instruction_count(1); multiple_bundles; | |
| 4717 dst : E(write)+1; | |
| 4718 IALU : R(2); | |
| 4719 %} | |
| 4720 | |
| 4721 // Long Constant | |
| 4722 pipe_class loadConL( iRegL dst, immL src ) %{ | |
| 4723 instruction_count(2); multiple_bundles; | |
| 4724 dst : E(write)+1; | |
| 4725 IALU : R(2); | |
| 4726 IALU : R(2); | |
| 4727 %} | |
| 4728 | |
| 4729 // Pointer Constant | |
| 4730 pipe_class loadConP( iRegP dst, immP src ) %{ | |
| 4731 instruction_count(0); multiple_bundles; | |
| 4732 fixed_latency(6); | |
| 4733 %} | |
| 4734 | |
| 4735 // Polling Address | |
| 4736 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
| 4737 #ifdef _LP64 | |
| 4738 instruction_count(0); multiple_bundles; | |
| 4739 fixed_latency(6); | |
| 4740 #else | |
| 4741 dst : E(write); | |
| 4742 IALU : R; | |
| 4743 #endif | |
| 4744 %} | |
| 4745 | |
| 4746 // Long Constant small | |
| 4747 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
| 4748 instruction_count(2); | |
| 4749 dst : E(write); | |
| 4750 IALU : R; | |
| 4751 IALU : R; | |
| 4752 %} | |
| 4753 | |
| 4754 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
| 4755 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
| 4756 instruction_count(1); multiple_bundles; | |
| 4757 src : R(read); | |
| 4758 dst : M(write)+1; | |
| 4759 IALU : R; | |
| 4760 MS : E; | |
| 4761 %} | |
| 4762 | |
| 4763 // Integer ALU nop operation | |
| 4764 pipe_class ialu_nop() %{ | |
| 4765 single_instruction; | |
| 4766 IALU : R; | |
| 4767 %} | |
| 4768 | |
| 4769 // Integer ALU nop operation | |
| 4770 pipe_class ialu_nop_A0() %{ | |
| 4771 single_instruction; | |
| 4772 A0 : R; | |
| 4773 %} | |
| 4774 | |
| 4775 // Integer ALU nop operation | |
| 4776 pipe_class ialu_nop_A1() %{ | |
| 4777 single_instruction; | |
| 4778 A1 : R; | |
| 4779 %} | |
| 4780 | |
| 4781 // Integer Multiply reg-reg operation | |
| 4782 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4783 single_instruction; | |
| 4784 dst : E(write); | |
| 4785 src1 : R(read); | |
| 4786 src2 : R(read); | |
| 4787 MS : R(5); | |
| 4788 %} | |
| 4789 | |
| 4790 // Integer Multiply reg-imm operation | |
| 4791 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4792 single_instruction; | |
| 4793 dst : E(write); | |
| 4794 src1 : R(read); | |
| 4795 MS : R(5); | |
| 4796 %} | |
| 4797 | |
| 4798 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4799 single_instruction; | |
| 4800 dst : E(write)+4; | |
| 4801 src1 : R(read); | |
| 4802 src2 : R(read); | |
| 4803 MS : R(6); | |
| 4804 %} | |
| 4805 | |
| 4806 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4807 single_instruction; | |
| 4808 dst : E(write)+4; | |
| 4809 src1 : R(read); | |
| 4810 MS : R(6); | |
| 4811 %} | |
| 4812 | |
| 4813 // Integer Divide reg-reg | |
| 4814 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
| 4815 instruction_count(1); multiple_bundles; | |
| 4816 dst : E(write); | |
| 4817 temp : E(write); | |
| 4818 src1 : R(read); | |
| 4819 src2 : R(read); | |
| 4820 temp : R(read); | |
| 4821 MS : R(38); | |
| 4822 %} | |
| 4823 | |
| 4824 // Integer Divide reg-imm | |
| 4825 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
| 4826 instruction_count(1); multiple_bundles; | |
| 4827 dst : E(write); | |
| 4828 temp : E(write); | |
| 4829 src1 : R(read); | |
| 4830 temp : R(read); | |
| 4831 MS : R(38); | |
| 4832 %} | |
| 4833 | |
| 4834 // Long Divide | |
| 4835 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4836 dst : E(write)+71; | |
| 4837 src1 : R(read); | |
| 4838 src2 : R(read)+1; | |
| 4839 MS : R(70); | |
| 4840 %} | |
| 4841 | |
| 4842 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4843 dst : E(write)+71; | |
| 4844 src1 : R(read); | |
| 4845 MS : R(70); | |
| 4846 %} | |
| 4847 | |
| 4848 // Floating Point Add Float | |
| 4849 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4850 single_instruction; | |
| 4851 dst : X(write); | |
| 4852 src1 : E(read); | |
| 4853 src2 : E(read); | |
| 4854 FA : R; | |
| 4855 %} | |
| 4856 | |
| 4857 // Floating Point Add Double | |
| 4858 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4859 single_instruction; | |
| 4860 dst : X(write); | |
| 4861 src1 : E(read); | |
| 4862 src2 : E(read); | |
| 4863 FA : R; | |
| 4864 %} | |
| 4865 | |
| 4866 // Floating Point Conditional Move based on integer flags | |
| 4867 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
| 4868 single_instruction; | |
| 4869 dst : X(write); | |
| 4870 src : E(read); | |
| 4871 cr : R(read); | |
| 4872 FA : R(2); | |
| 4873 BR : R(2); | |
| 4874 %} | |
| 4875 | |
| 4876 // Floating Point Conditional Move based on integer flags | |
| 4877 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
| 4878 single_instruction; | |
| 4879 dst : X(write); | |
| 4880 src : E(read); | |
| 4881 cr : R(read); | |
| 4882 FA : R(2); | |
| 4883 BR : R(2); | |
| 4884 %} | |
| 4885 | |
| 4886 // Floating Point Multiply Float | |
| 4887 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4888 single_instruction; | |
| 4889 dst : X(write); | |
| 4890 src1 : E(read); | |
| 4891 src2 : E(read); | |
| 4892 FM : R; | |
| 4893 %} | |
| 4894 | |
| 4895 // Floating Point Multiply Double | |
| 4896 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4897 single_instruction; | |
| 4898 dst : X(write); | |
| 4899 src1 : E(read); | |
| 4900 src2 : E(read); | |
| 4901 FM : R; | |
| 4902 %} | |
| 4903 | |
| 4904 // Floating Point Divide Float | |
| 4905 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4906 single_instruction; | |
| 4907 dst : X(write); | |
| 4908 src1 : E(read); | |
| 4909 src2 : E(read); | |
| 4910 FM : R; | |
| 4911 FDIV : C(14); | |
| 4912 %} | |
| 4913 | |
| 4914 // Floating Point Divide Double | |
| 4915 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4916 single_instruction; | |
| 4917 dst : X(write); | |
| 4918 src1 : E(read); | |
| 4919 src2 : E(read); | |
| 4920 FM : R; | |
| 4921 FDIV : C(17); | |
| 4922 %} | |
| 4923 | |
| 4924 // Floating Point Move/Negate/Abs Float | |
| 4925 pipe_class faddF_reg(regF dst, regF src) %{ | |
| 4926 single_instruction; | |
| 4927 dst : W(write); | |
| 4928 src : E(read); | |
| 4929 FA : R(1); | |
| 4930 %} | |
| 4931 | |
| 4932 // Floating Point Move/Negate/Abs Double | |
| 4933 pipe_class faddD_reg(regD dst, regD src) %{ | |
| 4934 single_instruction; | |
| 4935 dst : W(write); | |
| 4936 src : E(read); | |
| 4937 FA : R; | |
| 4938 %} | |
| 4939 | |
| 4940 // Floating Point Convert F->D | |
| 4941 pipe_class fcvtF2D(regD dst, regF src) %{ | |
| 4942 single_instruction; | |
| 4943 dst : X(write); | |
| 4944 src : E(read); | |
| 4945 FA : R; | |
| 4946 %} | |
| 4947 | |
| 4948 // Floating Point Convert I->D | |
| 4949 pipe_class fcvtI2D(regD dst, regF src) %{ | |
| 4950 single_instruction; | |
| 4951 dst : X(write); | |
| 4952 src : E(read); | |
| 4953 FA : R; | |
| 4954 %} | |
| 4955 | |
| 4956 // Floating Point Convert LHi->D | |
| 4957 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
| 4958 single_instruction; | |
| 4959 dst : X(write); | |
| 4960 src : E(read); | |
| 4961 FA : R; | |
| 4962 %} | |
| 4963 | |
| 4964 // Floating Point Convert L->D | |
| 4965 pipe_class fcvtL2D(regD dst, regF src) %{ | |
| 4966 single_instruction; | |
| 4967 dst : X(write); | |
| 4968 src : E(read); | |
| 4969 FA : R; | |
| 4970 %} | |
| 4971 | |
| 4972 // Floating Point Convert L->F | |
| 4973 pipe_class fcvtL2F(regD dst, regF src) %{ | |
| 4974 single_instruction; | |
| 4975 dst : X(write); | |
| 4976 src : E(read); | |
| 4977 FA : R; | |
| 4978 %} | |
| 4979 | |
| 4980 // Floating Point Convert D->F | |
| 4981 pipe_class fcvtD2F(regD dst, regF src) %{ | |
| 4982 single_instruction; | |
| 4983 dst : X(write); | |
| 4984 src : E(read); | |
| 4985 FA : R; | |
| 4986 %} | |
| 4987 | |
| 4988 // Floating Point Convert I->L | |
| 4989 pipe_class fcvtI2L(regD dst, regF src) %{ | |
| 4990 single_instruction; | |
| 4991 dst : X(write); | |
| 4992 src : E(read); | |
| 4993 FA : R; | |
| 4994 %} | |
| 4995 | |
| 4996 // Floating Point Convert D->F | |
| 4997 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
| 4998 instruction_count(1); multiple_bundles; | |
| 4999 dst : X(write)+6; | |
| 5000 src : E(read); | |
| 5001 FA : R; | |
| 5002 %} | |
| 5003 | |
| 5004 // Floating Point Convert D->L | |
| 5005 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
| 5006 instruction_count(1); multiple_bundles; | |
| 5007 dst : X(write)+6; | |
| 5008 src : E(read); | |
| 5009 FA : R; | |
| 5010 %} | |
| 5011 | |
| 5012 // Floating Point Convert F->I | |
| 5013 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
| 5014 instruction_count(1); multiple_bundles; | |
| 5015 dst : X(write)+6; | |
| 5016 src : E(read); | |
| 5017 FA : R; | |
| 5018 %} | |
| 5019 | |
| 5020 // Floating Point Convert F->L | |
| 5021 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
| 5022 instruction_count(1); multiple_bundles; | |
| 5023 dst : X(write)+6; | |
| 5024 src : E(read); | |
| 5025 FA : R; | |
| 5026 %} | |
| 5027 | |
| 5028 // Floating Point Convert I->F | |
| 5029 pipe_class fcvtI2F(regF dst, regF src) %{ | |
| 5030 single_instruction; | |
| 5031 dst : X(write); | |
| 5032 src : E(read); | |
| 5033 FA : R; | |
| 5034 %} | |
| 5035 | |
| 5036 // Floating Point Compare | |
| 5037 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
| 5038 single_instruction; | |
| 5039 cr : X(write); | |
| 5040 src1 : E(read); | |
| 5041 src2 : E(read); | |
| 5042 FA : R; | |
| 5043 %} | |
| 5044 | |
| 5045 // Floating Point Compare | |
| 5046 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
| 5047 single_instruction; | |
| 5048 cr : X(write); | |
| 5049 src1 : E(read); | |
| 5050 src2 : E(read); | |
| 5051 FA : R; | |
| 5052 %} | |
| 5053 | |
| 5054 // Floating Add Nop | |
| 5055 pipe_class fadd_nop() %{ | |
| 5056 single_instruction; | |
| 5057 FA : R; | |
| 5058 %} | |
| 5059 | |
| 5060 // Integer Store to Memory | |
| 5061 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
| 5062 single_instruction; | |
| 5063 mem : R(read); | |
| 5064 src : C(read); | |
| 5065 MS : R; | |
| 5066 %} | |
| 5067 | |
| 5068 // Integer Store to Memory | |
| 5069 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
| 5070 single_instruction; | |
| 5071 mem : R(read); | |
| 5072 src : C(read); | |
| 5073 MS : R; | |
| 5074 %} | |
| 5075 | |
| 5076 // Integer Store Zero to Memory | |
| 5077 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
| 5078 single_instruction; | |
| 5079 mem : R(read); | |
| 5080 MS : R; | |
| 5081 %} | |
| 5082 | |
| 5083 // Special Stack Slot Store | |
| 5084 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
| 5085 single_instruction; | |
| 5086 stkSlot : R(read); | |
| 5087 src : C(read); | |
| 5088 MS : R; | |
| 5089 %} | |
| 5090 | |
| 5091 // Special Stack Slot Store | |
| 5092 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
| 5093 instruction_count(2); multiple_bundles; | |
| 5094 stkSlot : R(read); | |
| 5095 src : C(read); | |
| 5096 MS : R(2); | |
| 5097 %} | |
| 5098 | |
| 5099 // Float Store | |
| 5100 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
| 5101 single_instruction; | |
| 5102 mem : R(read); | |
| 5103 src : C(read); | |
| 5104 MS : R; | |
| 5105 %} | |
| 5106 | |
| 5107 // Float Store | |
| 5108 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
| 5109 single_instruction; | |
| 5110 mem : R(read); | |
| 5111 MS : R; | |
| 5112 %} | |
| 5113 | |
| 5114 // Double Store | |
| 5115 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
| 5116 instruction_count(1); | |
| 5117 mem : R(read); | |
| 5118 src : C(read); | |
| 5119 MS : R; | |
| 5120 %} | |
| 5121 | |
| 5122 // Double Store | |
| 5123 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
| 5124 single_instruction; | |
| 5125 mem : R(read); | |
| 5126 MS : R; | |
| 5127 %} | |
| 5128 | |
| 5129 // Special Stack Slot Float Store | |
| 5130 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
| 5131 single_instruction; | |
| 5132 stkSlot : R(read); | |
| 5133 src : C(read); | |
| 5134 MS : R; | |
| 5135 %} | |
| 5136 | |
| 5137 // Special Stack Slot Double Store | |
| 5138 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
| 5139 single_instruction; | |
| 5140 stkSlot : R(read); | |
| 5141 src : C(read); | |
| 5142 MS : R; | |
| 5143 %} | |
| 5144 | |
| 5145 // Integer Load (when sign bit propagation not needed) | |
| 5146 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
| 5147 single_instruction; | |
| 5148 mem : R(read); | |
| 5149 dst : C(write); | |
| 5150 MS : R; | |
| 5151 %} | |
| 5152 | |
| 5153 // Integer Load from stack operand | |
| 5154 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
| 5155 single_instruction; | |
| 5156 mem : R(read); | |
| 5157 dst : C(write); | |
| 5158 MS : R; | |
| 5159 %} | |
| 5160 | |
| 5161 // Integer Load (when sign bit propagation or masking is needed) | |
| 5162 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
| 5163 single_instruction; | |
| 5164 mem : R(read); | |
| 5165 dst : M(write); | |
| 5166 MS : R; | |
| 5167 %} | |
| 5168 | |
| 5169 // Float Load | |
| 5170 pipe_class floadF_mem(regF dst, memory mem) %{ | |
| 5171 single_instruction; | |
| 5172 mem : R(read); | |
| 5173 dst : M(write); | |
| 5174 MS : R; | |
| 5175 %} | |
| 5176 | |
| 5177 // Float Load | |
| 5178 pipe_class floadD_mem(regD dst, memory mem) %{ | |
| 5179 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
| 5180 mem : R(read); | |
| 5181 dst : M(write); | |
| 5182 MS : R; | |
| 5183 %} | |
| 5184 | |
| 5185 // Float Load | |
| 5186 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
| 5187 single_instruction; | |
| 5188 stkSlot : R(read); | |
| 5189 dst : M(write); | |
| 5190 MS : R; | |
| 5191 %} | |
| 5192 | |
| 5193 // Float Load | |
| 5194 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
| 5195 single_instruction; | |
| 5196 stkSlot : R(read); | |
| 5197 dst : M(write); | |
| 5198 MS : R; | |
| 5199 %} | |
| 5200 | |
| 5201 // Memory Nop | |
| 5202 pipe_class mem_nop() %{ | |
| 5203 single_instruction; | |
| 5204 MS : R; | |
| 5205 %} | |
| 5206 | |
| 5207 pipe_class sethi(iRegP dst, immI src) %{ | |
| 5208 single_instruction; | |
| 5209 dst : E(write); | |
| 5210 IALU : R; | |
| 5211 %} | |
| 5212 | |
| 5213 pipe_class loadPollP(iRegP poll) %{ | |
| 5214 single_instruction; | |
| 5215 poll : R(read); | |
| 5216 MS : R; | |
| 5217 %} | |
| 5218 | |
| 5219 pipe_class br(Universe br, label labl) %{ | |
| 5220 single_instruction_with_delay_slot; | |
| 5221 BR : R; | |
| 5222 %} | |
| 5223 | |
| 5224 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
| 5225 single_instruction_with_delay_slot; | |
| 5226 cr : E(read); | |
| 5227 BR : R; | |
| 5228 %} | |
| 5229 | |
| 5230 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
| 5231 single_instruction_with_delay_slot; | |
| 5232 op1 : E(read); | |
| 5233 BR : R; | |
| 5234 MS : R; | |
| 5235 %} | |
| 5236 | |
| 3851 | 5237 // Compare and branch |
| 5238 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ | |
| 5239 instruction_count(2); has_delay_slot; | |
| 5240 cr : E(write); | |
| 5241 src1 : R(read); | |
| 5242 src2 : R(read); | |
| 5243 IALU : R; | |
| 5244 BR : R; | |
| 5245 %} | |
| 5246 | |
| 5247 // Compare and branch | |
| 5248 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ | |
| 5249 instruction_count(2); has_delay_slot; | |
| 5250 cr : E(write); | |
| 5251 src1 : R(read); | |
| 5252 IALU : R; | |
| 5253 BR : R; | |
| 5254 %} | |
| 5255 | |
| 5256 // Compare and branch using cbcond | |
| 5257 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ | |
| 5258 single_instruction; | |
| 5259 src1 : E(read); | |
| 5260 src2 : E(read); | |
| 5261 IALU : R; | |
| 5262 BR : R; | |
| 5263 %} | |
| 5264 | |
| 5265 // Compare and branch using cbcond | |
| 5266 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ | |
| 5267 single_instruction; | |
| 5268 src1 : E(read); | |
| 5269 IALU : R; | |
| 5270 BR : R; | |
| 5271 %} | |
| 5272 | |
| 0 | 5273 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ |
| 5274 single_instruction_with_delay_slot; | |
| 5275 cr : E(read); | |
| 5276 BR : R; | |
| 5277 %} | |
| 5278 | |
| 5279 pipe_class br_nop() %{ | |
| 5280 single_instruction; | |
| 5281 BR : R; | |
| 5282 %} | |
| 5283 | |
| 5284 pipe_class simple_call(method meth) %{ | |
| 5285 instruction_count(2); multiple_bundles; force_serialization; | |
| 5286 fixed_latency(100); | |
| 5287 BR : R(1); | |
| 5288 MS : R(1); | |
| 5289 A0 : R(1); | |
| 5290 %} | |
| 5291 | |
| 5292 pipe_class compiled_call(method meth) %{ | |
| 5293 instruction_count(1); multiple_bundles; force_serialization; | |
| 5294 fixed_latency(100); | |
| 5295 MS : R(1); | |
| 5296 %} | |
| 5297 | |
| 5298 pipe_class call(method meth) %{ | |
| 5299 instruction_count(0); multiple_bundles; force_serialization; | |
| 5300 fixed_latency(100); | |
| 5301 %} | |
| 5302 | |
| 5303 pipe_class tail_call(Universe ignore, label labl) %{ | |
| 5304 single_instruction; has_delay_slot; | |
| 5305 fixed_latency(100); | |
| 5306 BR : R(1); | |
| 5307 MS : R(1); | |
| 5308 %} | |
| 5309 | |
| 5310 pipe_class ret(Universe ignore) %{ | |
| 5311 single_instruction; has_delay_slot; | |
| 5312 BR : R(1); | |
| 5313 MS : R(1); | |
| 5314 %} | |
| 5315 | |
| 5316 pipe_class ret_poll(g3RegP poll) %{ | |
| 5317 instruction_count(3); has_delay_slot; | |
| 5318 poll : E(read); | |
| 5319 MS : R; | |
| 5320 %} | |
| 5321 | |
| 5322 // The real do-nothing guy | |
| 5323 pipe_class empty( ) %{ | |
| 5324 instruction_count(0); | |
| 5325 %} | |
| 5326 | |
| 5327 pipe_class long_memory_op() %{ | |
| 5328 instruction_count(0); multiple_bundles; force_serialization; | |
| 5329 fixed_latency(25); | |
| 5330 MS : R(1); | |
| 5331 %} | |
| 5332 | |
| 5333 // Check-cast | |
| 5334 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
| 5335 array : R(read); | |
| 5336 match : R(read); | |
| 5337 IALU : R(2); | |
| 5338 BR : R(2); | |
| 5339 MS : R; | |
| 5340 %} | |
| 5341 | |
| 5342 // Convert FPU flags into +1,0,-1 | |
| 5343 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
| 5344 src1 : E(read); | |
| 5345 src2 : E(read); | |
| 5346 dst : E(write); | |
| 5347 FA : R; | |
| 5348 MS : R(2); | |
| 5349 BR : R(2); | |
| 5350 %} | |
| 5351 | |
| 5352 // Compare for p < q, and conditionally add y | |
| 5353 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
| 5354 p : E(read); | |
| 5355 q : E(read); | |
| 5356 y : E(read); | |
| 5357 IALU : R(3) | |
| 5358 %} | |
| 5359 | |
| 5360 // Perform a compare, then move conditionally in a branch delay slot. | |
| 5361 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
| 5362 src2 : E(read); | |
| 5363 srcdst : E(read); | |
| 5364 IALU : R; | |
| 5365 BR : R; | |
| 5366 %} | |
| 5367 | |
| 5368 // Define the class for the Nop node | |
| 5369 define %{ | |
| 5370 MachNop = ialu_nop; | |
| 5371 %} | |
| 5372 | |
| 5373 %} | |
| 5374 | |
| 5375 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5376 | |
| 5377 //------------Special Stack Slot instructions - no match rules----------------- | |
| 5378 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
| 5379 // No match rule to avoid chain rule match. | |
| 5380 effect(DEF dst, USE src); | |
| 5381 ins_cost(MEMORY_REF_COST); | |
| 5382 size(4); | |
| 5383 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
| 5384 opcode(Assembler::ldf_op3); | |
|
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5385 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5386 ins_pipe(floadF_stk); |
| 5387 %} | |
| 5388 | |
| 5389 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
| 5390 // No match rule to avoid chain rule match. | |
| 5391 effect(DEF dst, USE src); | |
| 5392 ins_cost(MEMORY_REF_COST); | |
| 5393 size(4); | |
| 5394 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
| 5395 opcode(Assembler::lddf_op3); | |
|
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5396 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5397 ins_pipe(floadD_stk); |
| 5398 %} | |
| 5399 | |
| 5400 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
| 5401 // No match rule to avoid chain rule match. | |
| 5402 effect(DEF dst, USE src); | |
| 5403 ins_cost(MEMORY_REF_COST); | |
| 5404 size(4); | |
| 5405 format %{ "STF $src,$dst\t! regF to stkI" %} | |
| 5406 opcode(Assembler::stf_op3); | |
|
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5407 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5408 ins_pipe(fstoreF_stk_reg); |
| 5409 %} | |
| 5410 | |
| 5411 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
| 5412 // No match rule to avoid chain rule match. | |
| 5413 effect(DEF dst, USE src); | |
| 5414 ins_cost(MEMORY_REF_COST); | |
| 5415 size(4); | |
| 5416 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
| 5417 opcode(Assembler::stdf_op3); | |
|
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5418 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5419 ins_pipe(fstoreD_stk_reg); |
| 5420 %} | |
| 5421 | |
| 5422 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
| 5423 effect(DEF dst, USE src); | |
| 5424 ins_cost(MEMORY_REF_COST*2); | |
| 5425 size(8); | |
| 5426 format %{ "STW $src,$dst.hi\t! long\n\t" | |
| 5427 "STW R_G0,$dst.lo" %} | |
| 5428 opcode(Assembler::stw_op3); | |
|
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5429 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
| 0 | 5430 ins_pipe(lstoreI_stk_reg); |
| 5431 %} | |
| 5432 | |
| 5433 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
| 5434 // No match rule to avoid chain rule match. | |
| 5435 effect(DEF dst, USE src); | |
| 5436 ins_cost(MEMORY_REF_COST); | |
| 5437 size(4); | |
| 5438 format %{ "STX $src,$dst\t! regL to stkD" %} | |
| 5439 opcode(Assembler::stx_op3); | |
|
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5440 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5441 ins_pipe(istore_stk_reg); |
| 5442 %} | |
| 5443 | |
| 5444 //---------- Chain stack slots between similar types -------- | |
| 5445 | |
| 5446 // Load integer from stack slot | |
| 5447 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
| 5448 match(Set dst src); | |
| 5449 ins_cost(MEMORY_REF_COST); | |
| 5450 | |
| 5451 size(4); | |
| 5452 format %{ "LDUW $src,$dst\t!stk" %} | |
| 5453 opcode(Assembler::lduw_op3); | |
|
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5454 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5455 ins_pipe(iload_mem); |
| 5456 %} | |
| 5457 | |
| 5458 // Store integer to stack slot | |
| 5459 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
| 5460 match(Set dst src); | |
| 5461 ins_cost(MEMORY_REF_COST); | |
| 5462 | |
| 5463 size(4); | |
| 5464 format %{ "STW $src,$dst\t!stk" %} | |
| 5465 opcode(Assembler::stw_op3); | |
|
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5466 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5467 ins_pipe(istore_mem_reg); |
| 5468 %} | |
| 5469 | |
| 5470 // Load long from stack slot | |
| 5471 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
| 5472 match(Set dst src); | |
| 5473 | |
| 5474 ins_cost(MEMORY_REF_COST); | |
| 5475 size(4); | |
| 5476 format %{ "LDX $src,$dst\t! long" %} | |
| 5477 opcode(Assembler::ldx_op3); | |
|
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5478 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5479 ins_pipe(iload_mem); |
| 5480 %} | |
| 5481 | |
| 5482 // Store long to stack slot | |
| 5483 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
| 5484 match(Set dst src); | |
| 5485 | |
| 5486 ins_cost(MEMORY_REF_COST); | |
| 5487 size(4); | |
| 5488 format %{ "STX $src,$dst\t! long" %} | |
| 5489 opcode(Assembler::stx_op3); | |
|
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5490 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5491 ins_pipe(istore_mem_reg); |
| 5492 %} | |
| 5493 | |
| 5494 #ifdef _LP64 | |
| 5495 // Load pointer from stack slot, 64-bit encoding | |
| 5496 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5497 match(Set dst src); | |
| 5498 ins_cost(MEMORY_REF_COST); | |
| 5499 size(4); | |
| 5500 format %{ "LDX $src,$dst\t!ptr" %} | |
| 5501 opcode(Assembler::ldx_op3); | |
|
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5502 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5503 ins_pipe(iload_mem); |
| 5504 %} | |
| 5505 | |
| 5506 // Store pointer to stack slot | |
| 5507 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5508 match(Set dst src); | |
| 5509 ins_cost(MEMORY_REF_COST); | |
| 5510 size(4); | |
| 5511 format %{ "STX $src,$dst\t!ptr" %} | |
| 5512 opcode(Assembler::stx_op3); | |
|
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5513 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5514 ins_pipe(istore_mem_reg); |
| 5515 %} | |
| 5516 #else // _LP64 | |
| 5517 // Load pointer from stack slot, 32-bit encoding | |
| 5518 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5519 match(Set dst src); | |
| 5520 ins_cost(MEMORY_REF_COST); | |
| 5521 format %{ "LDUW $src,$dst\t!ptr" %} | |
| 5522 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
|
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5523 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5524 ins_pipe(iload_mem); |
| 5525 %} | |
| 5526 | |
| 5527 // Store pointer to stack slot | |
| 5528 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5529 match(Set dst src); | |
| 5530 ins_cost(MEMORY_REF_COST); | |
| 5531 format %{ "STW $src,$dst\t!ptr" %} | |
| 5532 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
|
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5533 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5534 ins_pipe(istore_mem_reg); |
| 5535 %} | |
| 5536 #endif // _LP64 | |
| 5537 | |
| 5538 //------------Special Nop instructions for bundling - no match rules----------- | |
| 5539 // Nop using the A0 functional unit | |
| 5540 instruct Nop_A0() %{ | |
| 5541 ins_cost(0); | |
| 5542 | |
| 5543 format %{ "NOP ! Alu Pipeline" %} | |
| 5544 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5545 ins_encode( form2_nop() ); | |
| 5546 ins_pipe(ialu_nop_A0); | |
| 5547 %} | |
| 5548 | |
| 5549 // Nop using the A1 functional unit | |
| 5550 instruct Nop_A1( ) %{ | |
| 5551 ins_cost(0); | |
| 5552 | |
| 5553 format %{ "NOP ! Alu Pipeline" %} | |
| 5554 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5555 ins_encode( form2_nop() ); | |
| 5556 ins_pipe(ialu_nop_A1); | |
| 5557 %} | |
| 5558 | |
| 5559 // Nop using the memory functional unit | |
| 5560 instruct Nop_MS( ) %{ | |
| 5561 ins_cost(0); | |
| 5562 | |
| 5563 format %{ "NOP ! Memory Pipeline" %} | |
| 5564 ins_encode( emit_mem_nop ); | |
| 5565 ins_pipe(mem_nop); | |
| 5566 %} | |
| 5567 | |
| 5568 // Nop using the floating add functional unit | |
| 5569 instruct Nop_FA( ) %{ | |
| 5570 ins_cost(0); | |
| 5571 | |
| 5572 format %{ "NOP ! Floating Add Pipeline" %} | |
| 5573 ins_encode( emit_fadd_nop ); | |
| 5574 ins_pipe(fadd_nop); | |
| 5575 %} | |
| 5576 | |
| 5577 // Nop using the branch functional unit | |
| 5578 instruct Nop_BR( ) %{ | |
| 5579 ins_cost(0); | |
| 5580 | |
| 5581 format %{ "NOP ! Branch Pipeline" %} | |
| 5582 ins_encode( emit_br_nop ); | |
| 5583 ins_pipe(br_nop); | |
| 5584 %} | |
| 5585 | |
| 5586 //----------Load/Store/Move Instructions--------------------------------------- | |
| 5587 //----------Load Instructions-------------------------------------------------- | |
| 5588 // Load Byte (8bit signed) | |
| 5589 instruct loadB(iRegI dst, memory mem) %{ | |
| 5590 match(Set dst (LoadB mem)); | |
| 5591 ins_cost(MEMORY_REF_COST); | |
| 5592 | |
| 5593 size(4); | |
| 624 | 5594 format %{ "LDSB $mem,$dst\t! byte" %} |
| 727 | 5595 ins_encode %{ |
| 5596 __ ldsb($mem$$Address, $dst$$Register); | |
| 5597 %} | |
| 624 | 5598 ins_pipe(iload_mask_mem); |
| 5599 %} | |
| 5600 | |
| 5601 // Load Byte (8bit signed) into a Long Register | |
| 5602 instruct loadB2L(iRegL dst, memory mem) %{ | |
| 5603 match(Set dst (ConvI2L (LoadB mem))); | |
| 5604 ins_cost(MEMORY_REF_COST); | |
| 5605 | |
| 5606 size(4); | |
| 5607 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
| 727 | 5608 ins_encode %{ |
| 5609 __ ldsb($mem$$Address, $dst$$Register); | |
| 5610 %} | |
| 0 | 5611 ins_pipe(iload_mask_mem); |
| 5612 %} | |
| 5613 | |
| 624 | 5614 // Load Unsigned Byte (8bit UNsigned) into an int reg |
| 5615 instruct loadUB(iRegI dst, memory mem) %{ | |
| 5616 match(Set dst (LoadUB mem)); | |
| 0 | 5617 ins_cost(MEMORY_REF_COST); |
| 5618 | |
| 5619 size(4); | |
| 624 | 5620 format %{ "LDUB $mem,$dst\t! ubyte" %} |
| 727 | 5621 ins_encode %{ |
| 5622 __ ldub($mem$$Address, $dst$$Register); | |
| 5623 %} | |
| 824 | 5624 ins_pipe(iload_mem); |
| 624 | 5625 %} |
| 5626 | |
| 5627 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
| 5628 instruct loadUB2L(iRegL dst, memory mem) %{ | |
| 5629 match(Set dst (ConvI2L (LoadUB mem))); | |
| 5630 ins_cost(MEMORY_REF_COST); | |
| 5631 | |
| 5632 size(4); | |
| 5633 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
| 727 | 5634 ins_encode %{ |
| 5635 __ ldub($mem$$Address, $dst$$Register); | |
| 5636 %} | |
| 824 | 5637 ins_pipe(iload_mem); |
| 5638 %} | |
| 5639 | |
| 5640 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register | |
| 5641 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ | |
| 5642 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5643 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5644 | |
| 5645 size(2*4); | |
| 5646 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" | |
| 5647 "AND $dst,$mask,$dst" %} | |
| 5648 ins_encode %{ | |
| 5649 __ ldub($mem$$Address, $dst$$Register); | |
| 5650 __ and3($dst$$Register, $mask$$constant, $dst$$Register); | |
| 5651 %} | |
| 5652 ins_pipe(iload_mem); | |
| 0 | 5653 %} |
| 5654 | |
| 624 | 5655 // Load Short (16bit signed) |
| 5656 instruct loadS(iRegI dst, memory mem) %{ | |
| 5657 match(Set dst (LoadS mem)); | |
| 5658 ins_cost(MEMORY_REF_COST); | |
| 5659 | |
| 5660 size(4); | |
| 5661 format %{ "LDSH $mem,$dst\t! short" %} | |
| 727 | 5662 ins_encode %{ |
| 5663 __ ldsh($mem$$Address, $dst$$Register); | |
| 5664 %} | |
| 624 | 5665 ins_pipe(iload_mask_mem); |
| 5666 %} | |
| 5667 | |
| 785 | 5668 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 5669 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5670 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 5671 ins_cost(MEMORY_REF_COST); | |
| 5672 | |
| 5673 size(4); | |
| 5674 | |
| 5675 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} | |
| 5676 ins_encode %{ | |
| 5677 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5678 %} | |
| 5679 ins_pipe(iload_mask_mem); | |
| 5680 %} | |
| 5681 | |
| 624 | 5682 // Load Short (16bit signed) into a Long Register |
| 5683 instruct loadS2L(iRegL dst, memory mem) %{ | |
| 5684 match(Set dst (ConvI2L (LoadS mem))); | |
| 0 | 5685 ins_cost(MEMORY_REF_COST); |
| 5686 | |
| 5687 size(4); | |
| 624 | 5688 format %{ "LDSH $mem,$dst\t! short -> long" %} |
| 727 | 5689 ins_encode %{ |
| 5690 __ ldsh($mem$$Address, $dst$$Register); | |
| 5691 %} | |
| 624 | 5692 ins_pipe(iload_mask_mem); |
| 5693 %} | |
| 5694 | |
| 5695 // Load Unsigned Short/Char (16bit UNsigned) | |
| 5696 instruct loadUS(iRegI dst, memory mem) %{ | |
| 5697 match(Set dst (LoadUS mem)); | |
| 5698 ins_cost(MEMORY_REF_COST); | |
| 5699 | |
| 5700 size(4); | |
| 5701 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
| 727 | 5702 ins_encode %{ |
| 5703 __ lduh($mem$$Address, $dst$$Register); | |
| 5704 %} | |
| 824 | 5705 ins_pipe(iload_mem); |
| 0 | 5706 %} |
| 5707 | |
| 785 | 5708 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 5709 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5710 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 5711 ins_cost(MEMORY_REF_COST); | |
| 5712 | |
| 5713 size(4); | |
| 5714 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} | |
| 5715 ins_encode %{ | |
| 5716 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5717 %} | |
| 5718 ins_pipe(iload_mask_mem); | |
| 5719 %} | |
| 5720 | |
|
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5721 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
| 624 | 5722 instruct loadUS2L(iRegL dst, memory mem) %{ |
| 5723 match(Set dst (ConvI2L (LoadUS mem))); | |
| 0 | 5724 ins_cost(MEMORY_REF_COST); |
| 5725 | |
| 5726 size(4); | |
| 624 | 5727 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
| 727 | 5728 ins_encode %{ |
| 5729 __ lduh($mem$$Address, $dst$$Register); | |
| 5730 %} | |
| 824 | 5731 ins_pipe(iload_mem); |
| 5732 %} | |
| 5733 | |
| 5734 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register | |
| 5735 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5736 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5737 ins_cost(MEMORY_REF_COST); | |
| 5738 | |
| 5739 size(4); | |
| 5740 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} | |
| 5741 ins_encode %{ | |
| 5742 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE | |
| 5743 %} | |
| 5744 ins_pipe(iload_mem); | |
| 5745 %} | |
| 5746 | |
| 5747 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register | |
| 5748 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
| 5749 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5750 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5751 | |
| 5752 size(2*4); | |
| 5753 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" | |
| 5754 "AND $dst,$mask,$dst" %} | |
| 5755 ins_encode %{ | |
| 5756 Register Rdst = $dst$$Register; | |
| 5757 __ lduh($mem$$Address, Rdst); | |
| 5758 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5759 %} | |
| 5760 ins_pipe(iload_mem); | |
| 5761 %} | |
| 5762 | |
| 5763 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register | |
| 5764 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | |
| 5765 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5766 effect(TEMP dst, TEMP tmp); | |
| 5767 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5768 | |
| 5769 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" | |
| 5770 "SET $mask,$tmp\n\t" | |
| 5771 "AND $dst,$tmp,$dst" %} | |
| 5772 ins_encode %{ | |
| 5773 Register Rdst = $dst$$Register; | |
| 5774 Register Rtmp = $tmp$$Register; | |
| 5775 __ lduh($mem$$Address, Rdst); | |
| 5776 __ set($mask$$constant, Rtmp); | |
| 5777 __ and3(Rdst, Rtmp, Rdst); | |
| 5778 %} | |
| 5779 ins_pipe(iload_mem); | |
| 0 | 5780 %} |
| 5781 | |
| 5782 // Load Integer | |
| 5783 instruct loadI(iRegI dst, memory mem) %{ | |
| 5784 match(Set dst (LoadI mem)); | |
| 5785 ins_cost(MEMORY_REF_COST); | |
| 624 | 5786 |
| 5787 size(4); | |
| 5788 format %{ "LDUW $mem,$dst\t! int" %} | |
| 727 | 5789 ins_encode %{ |
| 5790 __ lduw($mem$$Address, $dst$$Register); | |
| 5791 %} | |
| 624 | 5792 ins_pipe(iload_mem); |
| 5793 %} | |
| 5794 | |
| 785 | 5795 // Load Integer to Byte (8 bit signed) |
| 5796 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5797 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 5798 ins_cost(MEMORY_REF_COST); | |
| 5799 | |
| 5800 size(4); | |
| 5801 | |
| 5802 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} | |
| 5803 ins_encode %{ | |
| 5804 __ ldsb($mem$$Address, $dst$$Register, 3); | |
| 5805 %} | |
| 5806 ins_pipe(iload_mask_mem); | |
| 5807 %} | |
| 5808 | |
| 5809 // Load Integer to Unsigned Byte (8 bit UNsigned) | |
| 5810 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5811 match(Set dst (AndI (LoadI mem) mask)); | |
| 5812 ins_cost(MEMORY_REF_COST); | |
| 5813 | |
| 5814 size(4); | |
| 5815 | |
| 5816 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} | |
| 5817 ins_encode %{ | |
| 5818 __ ldub($mem$$Address, $dst$$Register, 3); | |
| 5819 %} | |
| 5820 ins_pipe(iload_mask_mem); | |
| 5821 %} | |
| 5822 | |
| 5823 // Load Integer to Short (16 bit signed) | |
| 5824 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ | |
| 5825 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 5826 ins_cost(MEMORY_REF_COST); | |
| 5827 | |
| 5828 size(4); | |
| 5829 | |
| 5830 format %{ "LDSH $mem+2,$dst\t! int -> short" %} | |
| 5831 ins_encode %{ | |
| 5832 __ ldsh($mem$$Address, $dst$$Register, 2); | |
| 5833 %} | |
| 5834 ins_pipe(iload_mask_mem); | |
| 5835 %} | |
| 5836 | |
| 5837 // Load Integer to Unsigned Short (16 bit UNsigned) | |
| 5838 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5839 match(Set dst (AndI (LoadI mem) mask)); | |
| 5840 ins_cost(MEMORY_REF_COST); | |
| 5841 | |
| 5842 size(4); | |
| 5843 | |
| 5844 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} | |
| 5845 ins_encode %{ | |
| 5846 __ lduh($mem$$Address, $dst$$Register, 2); | |
| 5847 %} | |
| 5848 ins_pipe(iload_mask_mem); | |
| 5849 %} | |
| 5850 | |
| 624 | 5851 // Load Integer into a Long Register |
| 5852 instruct loadI2L(iRegL dst, memory mem) %{ | |
| 5853 match(Set dst (ConvI2L (LoadI mem))); | |
| 5854 ins_cost(MEMORY_REF_COST); | |
| 5855 | |
| 5856 size(4); | |
| 5857 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
| 727 | 5858 ins_encode %{ |
| 5859 __ ldsw($mem$$Address, $dst$$Register); | |
| 5860 %} | |
| 824 | 5861 ins_pipe(iload_mask_mem); |
| 5862 %} | |
| 5863 | |
| 5864 // Load Integer with mask 0xFF into a Long Register | |
| 5865 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5866 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5867 ins_cost(MEMORY_REF_COST); | |
| 5868 | |
| 5869 size(4); | |
| 5870 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} | |
| 5871 ins_encode %{ | |
| 5872 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE | |
| 5873 %} | |
| 5874 ins_pipe(iload_mem); | |
| 5875 %} | |
| 5876 | |
| 5877 // Load Integer with mask 0xFFFF into a Long Register | |
| 5878 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5879 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5880 ins_cost(MEMORY_REF_COST); | |
| 5881 | |
| 5882 size(4); | |
| 5883 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} | |
| 5884 ins_encode %{ | |
| 5885 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | |
| 5886 %} | |
| 5887 ins_pipe(iload_mem); | |
| 5888 %} | |
| 5889 | |
|
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5890 // Load Integer with a 12-bit mask into a Long Register |
|
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5891 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{ |
| 824 | 5892 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
| 5893 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5894 | |
| 5895 size(2*4); | |
|
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5896 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t" |
| 824 | 5897 "AND $dst,$mask,$dst" %} |
| 5898 ins_encode %{ | |
| 5899 Register Rdst = $dst$$Register; | |
| 5900 __ lduw($mem$$Address, Rdst); | |
| 5901 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5902 %} | |
| 5903 ins_pipe(iload_mem); | |
| 5904 %} | |
| 5905 | |
|
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5906 // Load Integer with a 31-bit mask into a Long Register |
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5907 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{ |
| 824 | 5908 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
| 5909 effect(TEMP dst, TEMP tmp); | |
| 5910 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5911 | |
|
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5912 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t" |
| 824 | 5913 "SET $mask,$tmp\n\t" |
| 5914 "AND $dst,$tmp,$dst" %} | |
| 5915 ins_encode %{ | |
| 5916 Register Rdst = $dst$$Register; | |
| 5917 Register Rtmp = $tmp$$Register; | |
| 5918 __ lduw($mem$$Address, Rdst); | |
| 5919 __ set($mask$$constant, Rtmp); | |
| 5920 __ and3(Rdst, Rtmp, Rdst); | |
| 5921 %} | |
| 624 | 5922 ins_pipe(iload_mem); |
| 5923 %} | |
| 5924 | |
| 5925 // Load Unsigned Integer into a Long Register | |
| 6849 | 5926 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{ |
| 5927 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
| 624 | 5928 ins_cost(MEMORY_REF_COST); |
| 5929 | |
| 5930 size(4); | |
| 5931 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
| 727 | 5932 ins_encode %{ |
| 5933 __ lduw($mem$$Address, $dst$$Register); | |
| 5934 %} | |
| 0 | 5935 ins_pipe(iload_mem); |
| 5936 %} | |
| 5937 | |
| 5938 // Load Long - aligned | |
| 5939 instruct loadL(iRegL dst, memory mem ) %{ | |
| 5940 match(Set dst (LoadL mem)); | |
| 5941 ins_cost(MEMORY_REF_COST); | |
| 624 | 5942 |
| 0 | 5943 size(4); |
| 5944 format %{ "LDX $mem,$dst\t! long" %} | |
| 727 | 5945 ins_encode %{ |
| 5946 __ ldx($mem$$Address, $dst$$Register); | |
| 5947 %} | |
| 0 | 5948 ins_pipe(iload_mem); |
| 5949 %} | |
| 5950 | |
| 5951 // Load Long - UNaligned | |
| 5952 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
| 5953 match(Set dst (LoadL_unaligned mem)); | |
| 5954 effect(KILL tmp); | |
| 5955 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 5956 size(16); | |
| 5957 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
| 5958 "\tLDUW $mem ,$dst\n" | |
| 5959 "\tSLLX #32, $dst, $dst\n" | |
| 5960 "\tOR $dst, R_O7, $dst" %} | |
| 5961 opcode(Assembler::lduw_op3); | |
|
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5962 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
| 0 | 5963 ins_pipe(iload_mem); |
| 5964 %} | |
| 5965 | |
| 5966 // Load Range | |
| 5967 instruct loadRange(iRegI dst, memory mem) %{ | |
| 5968 match(Set dst (LoadRange mem)); | |
| 5969 ins_cost(MEMORY_REF_COST); | |
| 5970 | |
| 5971 size(4); | |
| 5972 format %{ "LDUW $mem,$dst\t! range" %} | |
| 5973 opcode(Assembler::lduw_op3); | |
|
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5974 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5975 ins_pipe(iload_mem); |
| 5976 %} | |
| 5977 | |
| 5978 // Load Integer into %f register (for fitos/fitod) | |
| 5979 instruct loadI_freg(regF dst, memory mem) %{ | |
| 5980 match(Set dst (LoadI mem)); | |
| 5981 ins_cost(MEMORY_REF_COST); | |
| 5982 size(4); | |
| 5983 | |
| 5984 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
| 5985 opcode(Assembler::ldf_op3); | |
|
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5986 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5987 ins_pipe(floadF_mem); |
| 5988 %} | |
| 5989 | |
| 5990 // Load Pointer | |
| 5991 instruct loadP(iRegP dst, memory mem) %{ | |
| 5992 match(Set dst (LoadP mem)); | |
| 5993 ins_cost(MEMORY_REF_COST); | |
| 5994 size(4); | |
| 5995 | |
| 5996 #ifndef _LP64 | |
| 5997 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 727 | 5998 ins_encode %{ |
| 5999 __ lduw($mem$$Address, $dst$$Register); | |
| 6000 %} | |
| 0 | 6001 #else |
| 6002 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 727 | 6003 ins_encode %{ |
| 6004 __ ldx($mem$$Address, $dst$$Register); | |
| 6005 %} | |
| 0 | 6006 #endif |
| 6007 ins_pipe(iload_mem); | |
| 6008 %} | |
| 6009 | |
|
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6010 // Load Compressed Pointer |
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6011 instruct loadN(iRegN dst, memory mem) %{ |
| 727 | 6012 match(Set dst (LoadN mem)); |
| 6013 ins_cost(MEMORY_REF_COST); | |
| 6014 size(4); | |
| 6015 | |
| 6016 format %{ "LDUW $mem,$dst\t! compressed ptr" %} | |
| 6017 ins_encode %{ | |
| 6018 __ lduw($mem$$Address, $dst$$Register); | |
| 6019 %} | |
| 6020 ins_pipe(iload_mem); | |
|
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6021 %} |
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6022 |
| 0 | 6023 // Load Klass Pointer |
| 6024 instruct loadKlass(iRegP dst, memory mem) %{ | |
| 6025 match(Set dst (LoadKlass mem)); | |
| 6026 ins_cost(MEMORY_REF_COST); | |
| 6027 size(4); | |
| 6028 | |
| 6029 #ifndef _LP64 | |
| 6030 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
| 727 | 6031 ins_encode %{ |
| 6032 __ lduw($mem$$Address, $dst$$Register); | |
| 6033 %} | |
| 0 | 6034 #else |
| 6035 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
| 727 | 6036 ins_encode %{ |
| 6037 __ ldx($mem$$Address, $dst$$Register); | |
| 6038 %} | |
| 0 | 6039 #endif |
| 6040 ins_pipe(iload_mem); | |
| 6041 %} | |
| 6042 | |
|
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6043 // Load narrow Klass Pointer |
|
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6044 instruct loadNKlass(iRegN dst, memory mem) %{ |
|
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6045 match(Set dst (LoadNKlass mem)); |
|
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6046 ins_cost(MEMORY_REF_COST); |
|
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6047 size(4); |
|
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6048 |
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6049 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
|
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6050 ins_encode %{ |
| 727 | 6051 __ lduw($mem$$Address, $dst$$Register); |
|
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6052 %} |
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6053 ins_pipe(iload_mem); |
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6054 %} |
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6055 |
| 0 | 6056 // Load Double |
| 6057 instruct loadD(regD dst, memory mem) %{ | |
| 6058 match(Set dst (LoadD mem)); | |
| 6059 ins_cost(MEMORY_REF_COST); | |
| 6060 | |
| 6061 size(4); | |
| 6062 format %{ "LDDF $mem,$dst" %} | |
| 6063 opcode(Assembler::lddf_op3); | |
|
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6064 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 6065 ins_pipe(floadD_mem); |
| 6066 %} | |
| 6067 | |
| 6068 // Load Double - UNaligned | |
| 6069 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
| 6070 match(Set dst (LoadD_unaligned mem)); | |
| 6071 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 6072 size(8); | |
| 6073 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
| 6074 "\tLDF $mem+4,$dst.lo\t!" %} | |
| 6075 opcode(Assembler::ldf_op3); | |
| 6076 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
| 6077 ins_pipe(iload_mem); | |
| 6078 %} | |
| 6079 | |
| 6080 // Load Float | |
| 6081 instruct loadF(regF dst, memory mem) %{ | |
| 6082 match(Set dst (LoadF mem)); | |
| 6083 ins_cost(MEMORY_REF_COST); | |
| 6084 | |
| 6085 size(4); | |
| 6086 format %{ "LDF $mem,$dst" %} | |
| 6087 opcode(Assembler::ldf_op3); | |
|
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6088 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 6089 ins_pipe(floadF_mem); |
| 6090 %} | |
| 6091 | |
| 6092 // Load Constant | |
| 6093 instruct loadConI( iRegI dst, immI src ) %{ | |
| 6094 match(Set dst src); | |
| 6095 ins_cost(DEFAULT_COST * 3/2); | |
| 6096 format %{ "SET $src,$dst" %} | |
| 6097 ins_encode( Set32(src, dst) ); | |
| 6098 ins_pipe(ialu_hi_lo_reg); | |
| 6099 %} | |
| 6100 | |
| 6101 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
| 6102 match(Set dst src); | |
| 6103 | |
| 6104 size(4); | |
| 6105 format %{ "MOV $src,$dst" %} | |
| 6106 ins_encode( Set13( src, dst ) ); | |
| 6107 ins_pipe(ialu_imm); | |
| 6108 %} | |
| 6109 | |
| 2008 | 6110 #ifndef _LP64 |
| 6111 instruct loadConP(iRegP dst, immP con) %{ | |
| 6112 match(Set dst con); | |
| 6113 ins_cost(DEFAULT_COST * 3/2); | |
| 6114 format %{ "SET $con,$dst\t!ptr" %} | |
| 6115 ins_encode %{ | |
|
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6116 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); |
| 2008 | 6117 intptr_t val = $con$$constant; |
|
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6118 if (constant_reloc == relocInfo::oop_type) { |
| 2008 | 6119 __ set_oop_constant((jobject) val, $dst$$Register); |
|
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6120 } else if (constant_reloc == relocInfo::metadata_type) { |
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6121 __ set_metadata_constant((Metadata*)val, $dst$$Register); |
| 2008 | 6122 } else { // non-oop pointers, e.g. card mark base, heap top |
|
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6123 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); |
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6124 __ set(val, $dst$$Register); |
| 2008 | 6125 } |
| 6126 %} | |
| 6127 ins_pipe(loadConP); | |
| 6128 %} | |
| 6129 #else | |
| 6130 instruct loadConP_set(iRegP dst, immP_set con) %{ | |
| 6131 match(Set dst con); | |
| 0 | 6132 ins_cost(DEFAULT_COST * 3/2); |
| 2008 | 6133 format %{ "SET $con,$dst\t! ptr" %} |
| 6134 ins_encode %{ | |
|
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6135 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); |
| 2008 | 6136 intptr_t val = $con$$constant; |
|
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6137 if (constant_reloc == relocInfo::oop_type) { |
| 2008 | 6138 __ set_oop_constant((jobject) val, $dst$$Register); |
|
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6139 } else if (constant_reloc == relocInfo::metadata_type) { |
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6140 __ set_metadata_constant((Metadata*)val, $dst$$Register); |
| 2008 | 6141 } else { // non-oop pointers, e.g. card mark base, heap top |
|
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6142 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); |
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6143 __ set(val, $dst$$Register); |
| 2008 | 6144 } |
| 6145 %} | |
| 0 | 6146 ins_pipe(loadConP); |
| 2008 | 6147 %} |
| 6148 | |
| 6149 instruct loadConP_load(iRegP dst, immP_load con) %{ | |
| 6150 match(Set dst con); | |
| 6151 ins_cost(MEMORY_REF_COST); | |
| 6152 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} | |
| 6153 ins_encode %{ | |
|
2076
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diff
changeset
|
6154 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
|
7737fa7ec2b5
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diff
changeset
|
6155 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); |
|
7737fa7ec2b5
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twisti
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2012
diff
changeset
|
6156 %} |
|
7737fa7ec2b5
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2012
diff
changeset
|
6157 ins_pipe(loadConP); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
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2012
diff
changeset
|
6158 %} |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
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diff
changeset
|
6159 |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
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diff
changeset
|
6160 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
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2012
diff
changeset
|
6161 match(Set dst con); |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
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2012
diff
changeset
|
6162 ins_cost(DEFAULT_COST * 3/2); |
|
7737fa7ec2b5
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twisti
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2012
diff
changeset
|
6163 format %{ "SET $con,$dst\t! non-oop ptr" %} |
|
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
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2012
diff
changeset
|
6164 ins_encode %{ |
|
7737fa7ec2b5
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2012
diff
changeset
|
6165 __ set($con$$constant, $dst$$Register); |
| 2008 | 6166 %} |
| 6167 ins_pipe(loadConP); | |
| 6168 %} | |
| 6169 #endif // _LP64 | |
| 0 | 6170 |
| 6171 instruct loadConP0(iRegP dst, immP0 src) %{ | |
| 6172 match(Set dst src); | |
| 6173 | |
| 6174 size(4); | |
| 6175 format %{ "CLR $dst\t!ptr" %} | |
| 2008 | 6176 ins_encode %{ |
| 6177 __ clr($dst$$Register); | |
| 6178 %} | |
| 0 | 6179 ins_pipe(ialu_imm); |
| 6180 %} | |
| 6181 | |
| 6182 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
| 6183 match(Set dst src); | |
| 6184 ins_cost(DEFAULT_COST); | |
| 6185 format %{ "SET $src,$dst\t!ptr" %} | |
| 6186 ins_encode %{ | |
| 727 | 6187 AddressLiteral polling_page(os::get_polling_page()); |
| 6188 __ sethi(polling_page, reg_to_register_object($dst$$reg)); | |
| 0 | 6189 %} |
| 6190 ins_pipe(loadConP_poll); | |
| 6191 %} | |
| 6192 | |
|
164
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diff
changeset
|
6193 instruct loadConN0(iRegN dst, immN0 src) %{ |
|
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|
6194 match(Set dst src); |
|
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|
6195 |
|
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changeset
|
6196 size(4); |
|
c436414a719e
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163
diff
changeset
|
6197 format %{ "CLR $dst\t! compressed NULL ptr" %} |
| 2008 | 6198 ins_encode %{ |
| 6199 __ clr($dst$$Register); | |
| 6200 %} | |
|
164
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163
diff
changeset
|
6201 ins_pipe(ialu_imm); |
|
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|
6202 %} |
|
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|
6203 |
|
113
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6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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81
diff
changeset
|
6204 instruct loadConN(iRegN dst, immN src) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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81
diff
changeset
|
6205 match(Set dst src); |
|
164
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163
diff
changeset
|
6206 ins_cost(DEFAULT_COST * 3/2); |
|
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163
diff
changeset
|
6207 format %{ "SET $src,$dst\t! compressed ptr" %} |
|
113
ba764ed4b6f2
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coleenp
parents:
81
diff
changeset
|
6208 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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81
diff
changeset
|
6209 Register dst = $dst$$Register; |
|
164
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163
diff
changeset
|
6210 __ set_narrow_oop((jobject)$src$$constant, dst); |
|
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163
diff
changeset
|
6211 %} |
|
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diff
changeset
|
6212 ins_pipe(ialu_hi_lo_reg); |
|
113
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coleenp
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81
diff
changeset
|
6213 %} |
|
ba764ed4b6f2
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81
diff
changeset
|
6214 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6215 instruct loadConNKlass(iRegN dst, immNKlass src) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6216 match(Set dst src); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6217 ins_cost(DEFAULT_COST * 3/2); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6218 format %{ "SET $src,$dst\t! compressed klass ptr" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6219 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6220 Register dst = $dst$$Register; |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6221 __ set_narrow_klass((Klass*)$src$$constant, dst); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6222 %} |
|
8e47bac5643a
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roland
parents:
6823
diff
changeset
|
6223 ins_pipe(ialu_hi_lo_reg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6224 %} |
|
8e47bac5643a
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diff
changeset
|
6225 |
| 2008 | 6226 // Materialize long value (predicated by immL_cheap). |
| 6227 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ | |
| 6228 match(Set dst con); | |
| 0 | 6229 effect(KILL tmp); |
| 2008 | 6230 ins_cost(DEFAULT_COST * 3); |
| 6231 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} | |
| 6232 ins_encode %{ | |
| 6233 __ set64($con$$constant, $dst$$Register, $tmp$$Register); | |
| 6234 %} | |
| 6235 ins_pipe(loadConL); | |
| 6236 %} | |
| 6237 | |
| 6238 // Load long value from constant table (predicated by immL_expensive). | |
| 6239 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ | |
| 6240 match(Set dst con); | |
| 6241 ins_cost(MEMORY_REF_COST); | |
| 6242 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} | |
| 6243 ins_encode %{ | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6244 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6245 __ ldx($constanttablebase, con_offset, $dst$$Register); |
| 2008 | 6246 %} |
| 0 | 6247 ins_pipe(loadConL); |
| 6248 %} | |
| 6249 | |
| 6250 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
| 6251 match(Set dst src); | |
| 6252 ins_cost(DEFAULT_COST); | |
| 6253 size(4); | |
| 6254 format %{ "CLR $dst\t! long" %} | |
| 6255 ins_encode( Set13( src, dst ) ); | |
| 6256 ins_pipe(ialu_imm); | |
| 6257 %} | |
| 6258 | |
| 6259 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
| 6260 match(Set dst src); | |
| 6261 ins_cost(DEFAULT_COST * 2); | |
| 6262 | |
| 6263 size(4); | |
| 6264 format %{ "MOV $src,$dst\t! long" %} | |
| 6265 ins_encode( Set13( src, dst ) ); | |
| 6266 ins_pipe(ialu_imm); | |
| 6267 %} | |
| 6268 | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6269 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ |
| 2008 | 6270 match(Set dst con); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6271 effect(KILL tmp); |
| 2008 | 6272 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} |
| 727 | 6273 ins_encode %{ |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6274 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6275 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); |
| 727 | 6276 %} |
| 0 | 6277 ins_pipe(loadConFD); |
| 6278 %} | |
| 6279 | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6280 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ |
| 2008 | 6281 match(Set dst con); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6282 effect(KILL tmp); |
| 2008 | 6283 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} |
| 727 | 6284 ins_encode %{ |
|
732
fb4c18a2ec66
6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents:
727
diff
changeset
|
6285 // XXX This is a quick fix for 6833573. |
| 2008 | 6286 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6287 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6288 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 727 | 6289 %} |
| 0 | 6290 ins_pipe(loadConFD); |
| 6291 %} | |
| 6292 | |
| 6293 // Prefetch instructions. | |
| 6294 // Must be safe to execute with invalid address (cannot fault). | |
| 6295 | |
| 6296 instruct prefetchr( memory mem ) %{ | |
| 6297 match( PrefetchRead mem ); | |
| 6298 ins_cost(MEMORY_REF_COST); | |
| 3854 | 6299 size(4); |
| 0 | 6300 |
| 6301 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
| 6302 opcode(Assembler::prefetch_op3); | |
| 6303 ins_encode( form3_mem_prefetch_read( mem ) ); | |
| 6304 ins_pipe(iload_mem); | |
| 6305 %} | |
| 6306 | |
| 6307 instruct prefetchw( memory mem ) %{ | |
| 6308 match( PrefetchWrite mem ); | |
| 6309 ins_cost(MEMORY_REF_COST); | |
| 3854 | 6310 size(4); |
| 0 | 6311 |
| 6312 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
| 6313 opcode(Assembler::prefetch_op3); | |
| 6314 ins_encode( form3_mem_prefetch_write( mem ) ); | |
| 6315 ins_pipe(iload_mem); | |
| 6316 %} | |
| 6317 | |
| 3854 | 6318 // Prefetch instructions for allocation. |
| 6319 | |
| 6320 instruct prefetchAlloc( memory mem ) %{ | |
| 6321 predicate(AllocatePrefetchInstr == 0); | |
| 6322 match( PrefetchAllocation mem ); | |
| 6323 ins_cost(MEMORY_REF_COST); | |
| 6324 size(4); | |
| 6325 | |
| 6326 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %} | |
| 6327 opcode(Assembler::prefetch_op3); | |
| 6328 ins_encode( form3_mem_prefetch_write( mem ) ); | |
| 6329 ins_pipe(iload_mem); | |
| 6330 %} | |
| 6331 | |
| 6332 // Use BIS instruction to prefetch for allocation. | |
| 6333 // Could fault, need space at the end of TLAB. | |
| 6334 instruct prefetchAlloc_bis( iRegP dst ) %{ | |
| 6335 predicate(AllocatePrefetchInstr == 1); | |
| 6336 match( PrefetchAllocation dst ); | |
| 6337 ins_cost(MEMORY_REF_COST); | |
| 6338 size(4); | |
| 6339 | |
| 6340 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %} | |
| 6341 ins_encode %{ | |
| 6342 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); | |
|
1367
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
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diff
changeset
|
6343 %} |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
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1274
diff
changeset
|
6344 ins_pipe(istore_mem_reg); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
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1274
diff
changeset
|
6345 %} |
| 0 | 6346 |
| 3854 | 6347 // Next code is used for finding next cache line address to prefetch. |
| 6348 #ifndef _LP64 | |
| 6349 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{ | |
| 6350 match(Set dst (CastX2P (AndI (CastP2X src) mask))); | |
| 6351 ins_cost(DEFAULT_COST); | |
| 6352 size(4); | |
| 6353 | |
| 6354 format %{ "AND $src,$mask,$dst\t! next cache line address" %} | |
| 6355 ins_encode %{ | |
| 6356 __ and3($src$$Register, $mask$$constant, $dst$$Register); | |
| 6357 %} | |
| 6358 ins_pipe(ialu_reg_imm); | |
| 6359 %} | |
| 6360 #else | |
| 6361 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{ | |
| 6362 match(Set dst (CastX2P (AndL (CastP2X src) mask))); | |
| 6363 ins_cost(DEFAULT_COST); | |
| 6364 size(4); | |
| 6365 | |
| 6366 format %{ "AND $src,$mask,$dst\t! next cache line address" %} | |
| 6367 ins_encode %{ | |
| 6368 __ and3($src$$Register, $mask$$constant, $dst$$Register); | |
| 6369 %} | |
| 6370 ins_pipe(ialu_reg_imm); | |
| 6371 %} | |
| 6372 #endif | |
| 6373 | |
| 0 | 6374 //----------Store Instructions------------------------------------------------- |
| 6375 // Store Byte | |
| 6376 instruct storeB(memory mem, iRegI src) %{ | |
| 6377 match(Set mem (StoreB mem src)); | |
| 6378 ins_cost(MEMORY_REF_COST); | |
| 6379 | |
| 6380 size(4); | |
| 6381 format %{ "STB $src,$mem\t! byte" %} | |
| 6382 opcode(Assembler::stb_op3); | |
|
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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235
diff
changeset
|
6383 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6384 ins_pipe(istore_mem_reg); |
| 6385 %} | |
| 6386 | |
| 6387 instruct storeB0(memory mem, immI0 src) %{ | |
| 6388 match(Set mem (StoreB mem src)); | |
| 6389 ins_cost(MEMORY_REF_COST); | |
| 6390 | |
| 6391 size(4); | |
| 6392 format %{ "STB $src,$mem\t! byte" %} | |
| 6393 opcode(Assembler::stb_op3); | |
|
415
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235
diff
changeset
|
6394 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6395 ins_pipe(istore_mem_zero); |
| 6396 %} | |
| 6397 | |
| 6398 instruct storeCM0(memory mem, immI0 src) %{ | |
| 6399 match(Set mem (StoreCM mem src)); | |
| 6400 ins_cost(MEMORY_REF_COST); | |
| 6401 | |
| 6402 size(4); | |
| 6403 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
| 6404 opcode(Assembler::stb_op3); | |
|
415
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235
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changeset
|
6405 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6406 ins_pipe(istore_mem_zero); |
| 6407 %} | |
| 6408 | |
| 6409 // Store Char/Short | |
| 6410 instruct storeC(memory mem, iRegI src) %{ | |
| 6411 match(Set mem (StoreC mem src)); | |
| 6412 ins_cost(MEMORY_REF_COST); | |
| 6413 | |
| 6414 size(4); | |
| 6415 format %{ "STH $src,$mem\t! short" %} | |
| 6416 opcode(Assembler::sth_op3); | |
|
415
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235
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changeset
|
6417 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6418 ins_pipe(istore_mem_reg); |
| 6419 %} | |
| 6420 | |
| 6421 instruct storeC0(memory mem, immI0 src) %{ | |
| 6422 match(Set mem (StoreC mem src)); | |
| 6423 ins_cost(MEMORY_REF_COST); | |
| 6424 | |
| 6425 size(4); | |
| 6426 format %{ "STH $src,$mem\t! short" %} | |
| 6427 opcode(Assembler::sth_op3); | |
|
415
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parents:
235
diff
changeset
|
6428 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6429 ins_pipe(istore_mem_zero); |
| 6430 %} | |
| 6431 | |
| 6432 // Store Integer | |
| 6433 instruct storeI(memory mem, iRegI src) %{ | |
| 6434 match(Set mem (StoreI mem src)); | |
| 6435 ins_cost(MEMORY_REF_COST); | |
| 6436 | |
| 6437 size(4); | |
| 6438 format %{ "STW $src,$mem" %} | |
| 6439 opcode(Assembler::stw_op3); | |
|
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6440 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6441 ins_pipe(istore_mem_reg); |
| 6442 %} | |
| 6443 | |
| 6444 // Store Long | |
| 6445 instruct storeL(memory mem, iRegL src) %{ | |
| 6446 match(Set mem (StoreL mem src)); | |
| 6447 ins_cost(MEMORY_REF_COST); | |
| 6448 size(4); | |
| 6449 format %{ "STX $src,$mem\t! long" %} | |
| 6450 opcode(Assembler::stx_op3); | |
|
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6451 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6452 ins_pipe(istore_mem_reg); |
| 6453 %} | |
| 6454 | |
| 6455 instruct storeI0(memory mem, immI0 src) %{ | |
| 6456 match(Set mem (StoreI mem src)); | |
| 6457 ins_cost(MEMORY_REF_COST); | |
| 6458 | |
| 6459 size(4); | |
| 6460 format %{ "STW $src,$mem" %} | |
| 6461 opcode(Assembler::stw_op3); | |
|
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6462 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6463 ins_pipe(istore_mem_zero); |
| 6464 %} | |
| 6465 | |
| 6466 instruct storeL0(memory mem, immL0 src) %{ | |
| 6467 match(Set mem (StoreL mem src)); | |
| 6468 ins_cost(MEMORY_REF_COST); | |
| 6469 | |
| 6470 size(4); | |
| 6471 format %{ "STX $src,$mem" %} | |
| 6472 opcode(Assembler::stx_op3); | |
|
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6473 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6474 ins_pipe(istore_mem_zero); |
| 6475 %} | |
| 6476 | |
| 6477 // Store Integer from float register (used after fstoi) | |
| 6478 instruct storeI_Freg(memory mem, regF src) %{ | |
| 6479 match(Set mem (StoreI mem src)); | |
| 6480 ins_cost(MEMORY_REF_COST); | |
| 6481 | |
| 6482 size(4); | |
| 6483 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
| 6484 opcode(Assembler::stf_op3); | |
|
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6485 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6486 ins_pipe(fstoreF_mem_reg); |
| 6487 %} | |
| 6488 | |
| 6489 // Store Pointer | |
| 6490 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
| 6491 match(Set dst (StoreP dst src)); | |
| 6492 ins_cost(MEMORY_REF_COST); | |
| 6493 size(4); | |
| 6494 | |
| 6495 #ifndef _LP64 | |
| 6496 format %{ "STW $src,$dst\t! ptr" %} | |
| 6497 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6498 #else | |
| 6499 format %{ "STX $src,$dst\t! ptr" %} | |
| 6500 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6501 #endif | |
| 6502 ins_encode( form3_mem_reg( dst, src ) ); | |
| 6503 ins_pipe(istore_mem_spORreg); | |
| 6504 %} | |
| 6505 | |
| 6506 instruct storeP0(memory dst, immP0 src) %{ | |
| 6507 match(Set dst (StoreP dst src)); | |
| 6508 ins_cost(MEMORY_REF_COST); | |
| 6509 size(4); | |
| 6510 | |
| 6511 #ifndef _LP64 | |
| 6512 format %{ "STW $src,$dst\t! ptr" %} | |
| 6513 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6514 #else | |
| 6515 format %{ "STX $src,$dst\t! ptr" %} | |
| 6516 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6517 #endif | |
| 6518 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
| 6519 ins_pipe(istore_mem_zero); | |
| 6520 %} | |
| 6521 | |
|
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6522 // Store Compressed Pointer |
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6523 instruct storeN(memory dst, iRegN src) %{ |
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6524 match(Set dst (StoreN dst src)); |
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6525 ins_cost(MEMORY_REF_COST); |
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6526 size(4); |
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6527 |
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6528 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6529 ins_encode %{ |
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6530 Register base = as_Register($dst$$base); |
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6531 Register index = as_Register($dst$$index); |
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6532 Register src = $src$$Register; |
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6533 if (index != G0) { |
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6534 __ stw(src, base, index); |
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6535 } else { |
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6536 __ stw(src, base, $dst$$disp); |
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6537 } |
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6538 %} |
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6539 ins_pipe(istore_mem_spORreg); |
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6540 %} |
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6541 |
|
6848
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|
6542 instruct storeNKlass(memory dst, iRegN src) %{ |
|
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|
6543 match(Set dst (StoreNKlass dst src)); |
|
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|
6544 ins_cost(MEMORY_REF_COST); |
|
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|
6545 size(4); |
|
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|
6546 |
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|
6547 format %{ "STW $src,$dst\t! compressed klass ptr" %} |
|
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|
6548 ins_encode %{ |
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|
6549 Register base = as_Register($dst$$base); |
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|
6550 Register index = as_Register($dst$$index); |
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|
6551 Register src = $src$$Register; |
|
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|
6552 if (index != G0) { |
|
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|
6553 __ stw(src, base, index); |
|
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|
6554 } else { |
|
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|
6555 __ stw(src, base, $dst$$disp); |
|
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|
6556 } |
|
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|
6557 %} |
|
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|
6558 ins_pipe(istore_mem_spORreg); |
|
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|
6559 %} |
|
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|
6560 |
|
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6561 instruct storeN0(memory dst, immN0 src) %{ |
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6562 match(Set dst (StoreN dst src)); |
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6563 ins_cost(MEMORY_REF_COST); |
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|
6564 size(4); |
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|
6565 |
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|
6566 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6567 ins_encode %{ |
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6568 Register base = as_Register($dst$$base); |
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6569 Register index = as_Register($dst$$index); |
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6570 if (index != G0) { |
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|
6571 __ stw(0, base, index); |
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6572 } else { |
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|
6573 __ stw(0, base, $dst$$disp); |
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|
6574 } |
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|
6575 %} |
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|
6576 ins_pipe(istore_mem_zero); |
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6577 %} |
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6578 |
| 0 | 6579 // Store Double |
| 6580 instruct storeD( memory mem, regD src) %{ | |
| 6581 match(Set mem (StoreD mem src)); | |
| 6582 ins_cost(MEMORY_REF_COST); | |
| 6583 | |
| 6584 size(4); | |
| 6585 format %{ "STDF $src,$mem" %} | |
| 6586 opcode(Assembler::stdf_op3); | |
|
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6587 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6588 ins_pipe(fstoreD_mem_reg); |
| 6589 %} | |
| 6590 | |
| 6591 instruct storeD0( memory mem, immD0 src) %{ | |
| 6592 match(Set mem (StoreD mem src)); | |
| 6593 ins_cost(MEMORY_REF_COST); | |
| 6594 | |
| 6595 size(4); | |
| 6596 format %{ "STX $src,$mem" %} | |
| 6597 opcode(Assembler::stx_op3); | |
|
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6598 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6599 ins_pipe(fstoreD_mem_zero); |
| 6600 %} | |
| 6601 | |
| 6602 // Store Float | |
| 6603 instruct storeF( memory mem, regF src) %{ | |
| 6604 match(Set mem (StoreF mem src)); | |
| 6605 ins_cost(MEMORY_REF_COST); | |
| 6606 | |
| 6607 size(4); | |
| 6608 format %{ "STF $src,$mem" %} | |
| 6609 opcode(Assembler::stf_op3); | |
|
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6610 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6611 ins_pipe(fstoreF_mem_reg); |
| 6612 %} | |
| 6613 | |
| 6614 instruct storeF0( memory mem, immF0 src) %{ | |
| 6615 match(Set mem (StoreF mem src)); | |
| 6616 ins_cost(MEMORY_REF_COST); | |
| 6617 | |
| 6618 size(4); | |
| 6619 format %{ "STW $src,$mem\t! storeF0" %} | |
| 6620 opcode(Assembler::stw_op3); | |
|
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6621 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6622 ins_pipe(fstoreF_mem_zero); |
| 6623 %} | |
| 6624 | |
|
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6625 // Convert oop pointer into compressed form |
|
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6626 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
|
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6627 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
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6628 match(Set dst (EncodeP src)); |
|
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|
6629 format %{ "encode_heap_oop $src, $dst" %} |
|
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6630 ins_encode %{ |
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6631 __ encode_heap_oop($src$$Register, $dst$$Register); |
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6632 %} |
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|
6633 ins_pipe(ialu_reg); |
|
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6634 %} |
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|
6635 |
|
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|
6636 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
|
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6637 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
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|
6638 match(Set dst (EncodeP src)); |
|
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|
6639 format %{ "encode_heap_oop_not_null $src, $dst" %} |
|
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|
6640 ins_encode %{ |
|
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|
6641 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
|
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|
6642 %} |
|
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|
6643 ins_pipe(ialu_reg); |
|
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|
6644 %} |
|
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|
6645 |
|
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6646 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
|
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changeset
|
6647 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
|
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diff
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|
6648 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
|
113
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6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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81
diff
changeset
|
6649 match(Set dst (DecodeN src)); |
|
ba764ed4b6f2
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parents:
81
diff
changeset
|
6650 format %{ "decode_heap_oop $src, $dst" %} |
|
ba764ed4b6f2
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coleenp
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81
diff
changeset
|
6651 ins_encode %{ |
|
ba764ed4b6f2
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81
diff
changeset
|
6652 __ decode_heap_oop($src$$Register, $dst$$Register); |
|
ba764ed4b6f2
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81
diff
changeset
|
6653 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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81
diff
changeset
|
6654 ins_pipe(ialu_reg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
81
diff
changeset
|
6655 %} |
|
ba764ed4b6f2
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81
diff
changeset
|
6656 |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6657 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
|
182
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|
6658 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
|
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181
diff
changeset
|
6659 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
|
124
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kvn
parents:
113
diff
changeset
|
6660 match(Set dst (DecodeN src)); |
|
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
6661 format %{ "decode_heap_oop_not_null $src, $dst" %} |
|
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
6662 ins_encode %{ |
|
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
6663 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6664 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6665 ins_pipe(ialu_reg); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6666 %} |
|
b130b98db9cf
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parents:
113
diff
changeset
|
6667 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6668 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6669 match(Set dst (EncodePKlass src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6670 format %{ "encode_klass_not_null $src, $dst" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6671 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6672 __ encode_klass_not_null($src$$Register, $dst$$Register); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6673 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6674 ins_pipe(ialu_reg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6675 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6676 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6677 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6678 match(Set dst (DecodeNKlass src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6679 format %{ "decode_klass_not_null $src, $dst" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6680 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6681 __ decode_klass_not_null($src$$Register, $dst$$Register); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6682 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6683 ins_pipe(ialu_reg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6684 %} |
|
113
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diff
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|
6685 |
| 0 | 6686 //----------MemBar Instructions----------------------------------------------- |
| 6687 // Memory barrier flavors | |
| 6688 | |
| 6689 instruct membar_acquire() %{ | |
| 6690 match(MemBarAcquire); | |
|
14439
50fdb38839eb
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
14435
diff
changeset
|
6691 match(LoadFence); |
| 0 | 6692 ins_cost(4*MEMORY_REF_COST); |
| 6693 | |
| 6694 size(0); | |
| 6695 format %{ "MEMBAR-acquire" %} | |
| 6696 ins_encode( enc_membar_acquire ); | |
| 6697 ins_pipe(long_memory_op); | |
| 6698 %} | |
| 6699 | |
| 6700 instruct membar_acquire_lock() %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6701 match(MemBarAcquireLock); |
| 0 | 6702 ins_cost(0); |
| 6703 | |
| 6704 size(0); | |
| 6705 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
| 6706 ins_encode( ); | |
| 6707 ins_pipe(empty); | |
| 6708 %} | |
| 6709 | |
| 6710 instruct membar_release() %{ | |
| 6711 match(MemBarRelease); | |
|
14439
50fdb38839eb
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
14435
diff
changeset
|
6712 match(StoreFence); |
| 0 | 6713 ins_cost(4*MEMORY_REF_COST); |
| 6714 | |
| 6715 size(0); | |
| 6716 format %{ "MEMBAR-release" %} | |
| 6717 ins_encode( enc_membar_release ); | |
| 6718 ins_pipe(long_memory_op); | |
| 6719 %} | |
| 6720 | |
| 6721 instruct membar_release_lock() %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6722 match(MemBarReleaseLock); |
| 0 | 6723 ins_cost(0); |
| 6724 | |
| 6725 size(0); | |
| 6726 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
| 6727 ins_encode( ); | |
| 6728 ins_pipe(empty); | |
| 6729 %} | |
| 6730 | |
| 6731 instruct membar_volatile() %{ | |
| 6732 match(MemBarVolatile); | |
| 6733 ins_cost(4*MEMORY_REF_COST); | |
| 6734 | |
| 6735 size(4); | |
| 6736 format %{ "MEMBAR-volatile" %} | |
| 6737 ins_encode( enc_membar_volatile ); | |
| 6738 ins_pipe(long_memory_op); | |
| 6739 %} | |
| 6740 | |
| 6741 instruct unnecessary_membar_volatile() %{ | |
| 6742 match(MemBarVolatile); | |
| 6743 predicate(Matcher::post_store_load_barrier(n)); | |
| 6744 ins_cost(0); | |
| 6745 | |
| 6746 size(0); | |
| 6747 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6748 ins_encode( ); | |
| 6749 ins_pipe(empty); | |
| 6750 %} | |
| 6751 | |
|
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6752 instruct membar_storestore() %{ |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6753 match(MemBarStoreStore); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6754 ins_cost(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6755 |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6756 size(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6757 format %{ "!MEMBAR-storestore (empty encoding)" %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6758 ins_encode( ); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6759 ins_pipe(empty); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6760 %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6761 |
| 0 | 6762 //----------Register Move Instructions----------------------------------------- |
| 6763 instruct roundDouble_nop(regD dst) %{ | |
| 6764 match(Set dst (RoundDouble dst)); | |
| 6765 ins_cost(0); | |
| 6766 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6767 ins_encode( ); | |
| 6768 ins_pipe(empty); | |
| 6769 %} | |
| 6770 | |
| 6771 | |
| 6772 instruct roundFloat_nop(regF dst) %{ | |
| 6773 match(Set dst (RoundFloat dst)); | |
| 6774 ins_cost(0); | |
| 6775 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6776 ins_encode( ); | |
| 6777 ins_pipe(empty); | |
| 6778 %} | |
| 6779 | |
| 6780 | |
| 6781 // Cast Index to Pointer for unsafe natives | |
| 6782 instruct castX2P(iRegX src, iRegP dst) %{ | |
| 6783 match(Set dst (CastX2P src)); | |
| 6784 | |
| 6785 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
| 6786 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6787 ins_pipe(ialu_reg); | |
| 6788 %} | |
| 6789 | |
| 6790 // Cast Pointer to Index for unsafe natives | |
| 6791 instruct castP2X(iRegP src, iRegX dst) %{ | |
| 6792 match(Set dst (CastP2X src)); | |
| 6793 | |
| 6794 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
| 6795 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6796 ins_pipe(ialu_reg); | |
| 6797 %} | |
| 6798 | |
| 6799 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
| 6800 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6801 match(Set stkSlot src); // chain rule | |
| 6802 ins_cost(MEMORY_REF_COST); | |
| 6803 format %{ "STDF $src,$stkSlot\t!stk" %} | |
| 6804 opcode(Assembler::stdf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6805 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6806 ins_pipe(fstoreD_stk_reg); |
| 6807 %} | |
| 6808 | |
| 6809 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
| 6810 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6811 match(Set dst stkSlot); // chain rule | |
| 6812 ins_cost(MEMORY_REF_COST); | |
| 6813 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
| 6814 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6815 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
| 0 | 6816 ins_pipe(floadD_stk); |
| 6817 %} | |
| 6818 | |
| 6819 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
| 6820 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6821 match(Set stkSlot src); // chain rule | |
| 6822 ins_cost(MEMORY_REF_COST); | |
| 6823 format %{ "STF $src,$stkSlot\t!stk" %} | |
| 6824 opcode(Assembler::stf_op3); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
235
diff
changeset
|
6825 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6826 ins_pipe(fstoreF_stk_reg); |
| 6827 %} | |
| 6828 | |
| 6829 //----------Conditional Move--------------------------------------------------- | |
| 6830 // Conditional move | |
| 6831 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
| 6832 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6833 ins_cost(150); | |
| 6834 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6835 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6836 ins_pipe(ialu_reg); | |
| 6837 %} | |
| 6838 | |
| 6839 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
| 6840 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6841 ins_cost(140); | |
| 6842 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6843 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6844 ins_pipe(ialu_imm); | |
| 6845 %} | |
| 6846 | |
| 6847 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
| 6848 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6849 ins_cost(150); | |
| 6850 size(4); | |
| 6851 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6852 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6853 ins_pipe(ialu_reg); | |
| 6854 %} | |
| 6855 | |
| 6856 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
| 6857 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6858 ins_cost(140); | |
| 6859 size(4); | |
| 6860 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6861 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6862 ins_pipe(ialu_imm); | |
| 6863 %} | |
| 6864 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6865 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
| 0 | 6866 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6867 ins_cost(150); | |
| 6868 size(4); | |
| 6869 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6870 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6871 ins_pipe(ialu_reg); | |
| 6872 %} | |
| 6873 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6874 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
| 0 | 6875 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6876 ins_cost(140); | |
| 6877 size(4); | |
| 6878 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6879 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6880 ins_pipe(ialu_imm); | |
| 6881 %} | |
| 6882 | |
| 6883 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
| 6884 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6885 ins_cost(150); | |
| 6886 size(4); | |
| 6887 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6888 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6889 ins_pipe(ialu_reg); | |
| 6890 %} | |
| 6891 | |
| 6892 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
| 6893 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6894 ins_cost(140); | |
| 6895 size(4); | |
| 6896 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6897 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6898 ins_pipe(ialu_imm); | |
| 6899 %} | |
| 6900 | |
|
164
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kvn
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163
diff
changeset
|
6901 // Conditional move for RegN. Only cmov(reg,reg). |
|
c436414a719e
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diff
changeset
|
6902 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
|
c436414a719e
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163
diff
changeset
|
6903 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
|
c436414a719e
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163
diff
changeset
|
6904 ins_cost(150); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
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163
diff
changeset
|
6905 format %{ "MOV$cmp $pcc,$src,$dst" %} |
|
c436414a719e
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163
diff
changeset
|
6906 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
|
c436414a719e
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163
diff
changeset
|
6907 ins_pipe(ialu_reg); |
|
c436414a719e
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163
diff
changeset
|
6908 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6909 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6910 // This instruction also works with CmpN so we don't need cmovNN_reg. |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6911 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6912 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
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diff
changeset
|
6913 ins_cost(150); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
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parents:
163
diff
changeset
|
6914 size(4); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6915 format %{ "MOV$cmp $icc,$src,$dst" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6916 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6917 ins_pipe(ialu_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6918 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6919 |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6920 // This instruction also works with CmpN so we don't need cmovNN_reg. |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6921 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6922 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6923 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6924 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6925 format %{ "MOV$cmp $icc,$src,$dst" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6926 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6927 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6928 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6929 |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6930 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6931 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6932 ins_cost(150); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6933 size(4); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6934 format %{ "MOV$cmp $fcc,$src,$dst" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6935 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6936 ins_pipe(ialu_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6937 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6938 |
| 0 | 6939 // Conditional move |
| 6940 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
| 6941 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6942 ins_cost(150); | |
| 6943 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6944 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6945 ins_pipe(ialu_reg); | |
| 6946 %} | |
| 6947 | |
| 6948 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
| 6949 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6950 ins_cost(140); | |
| 6951 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6952 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6953 ins_pipe(ialu_imm); | |
| 6954 %} | |
| 6955 | |
|
164
c436414a719e
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kvn
parents:
163
diff
changeset
|
6956 // This instruction also works with CmpN so we don't need cmovPN_reg. |
| 0 | 6957 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
| 6958 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6959 ins_cost(150); | |
| 6960 | |
| 6961 size(4); | |
| 6962 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6963 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6964 ins_pipe(ialu_reg); | |
| 6965 %} | |
| 6966 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6967 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6968 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6969 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6970 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6971 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6972 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6973 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6974 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6975 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6976 |
| 0 | 6977 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ |
| 6978 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6979 ins_cost(140); | |
| 6980 | |
| 6981 size(4); | |
| 6982 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6983 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6984 ins_pipe(ialu_imm); | |
| 6985 %} | |
| 6986 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6987 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6988 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6989 ins_cost(140); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6990 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6991 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6992 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6993 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6994 ins_pipe(ialu_imm); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6995 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6996 |
| 0 | 6997 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ |
| 6998 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6999 ins_cost(150); | |
| 7000 size(4); | |
| 7001 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 7002 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 7003 ins_pipe(ialu_imm); | |
| 7004 %} | |
| 7005 | |
| 7006 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
| 7007 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 7008 ins_cost(140); | |
| 7009 size(4); | |
| 7010 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 7011 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 7012 ins_pipe(ialu_imm); | |
| 7013 %} | |
| 7014 | |
| 7015 // Conditional move | |
| 7016 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
| 7017 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
| 7018 ins_cost(150); | |
| 7019 opcode(0x101); | |
| 7020 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 7021 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7022 ins_pipe(int_conditional_float_move); | |
| 7023 %} | |
| 7024 | |
| 7025 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
| 7026 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
| 7027 ins_cost(150); | |
| 7028 | |
| 7029 size(4); | |
| 7030 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
| 7031 opcode(0x101); | |
| 7032 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 7033 ins_pipe(int_conditional_float_move); | |
| 7034 %} | |
| 7035 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7036 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7037 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7038 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7039 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7040 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7041 format %{ "FMOVS$cmp $icc,$src,$dst" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7042 opcode(0x101); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7043 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7044 ins_pipe(int_conditional_float_move); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7045 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7046 |
| 0 | 7047 // Conditional move, |
| 7048 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
| 7049 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
| 7050 ins_cost(150); | |
| 7051 size(4); | |
| 7052 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
| 7053 opcode(0x1); | |
| 7054 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 7055 ins_pipe(int_conditional_double_move); | |
| 7056 %} | |
| 7057 | |
| 7058 // Conditional move | |
| 7059 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
| 7060 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
| 7061 ins_cost(150); | |
| 7062 size(4); | |
| 7063 opcode(0x102); | |
| 7064 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 7065 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7066 ins_pipe(int_conditional_double_move); | |
| 7067 %} | |
| 7068 | |
| 7069 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
| 7070 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
| 7071 ins_cost(150); | |
| 7072 | |
| 7073 size(4); | |
| 7074 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
| 7075 opcode(0x102); | |
| 7076 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 7077 ins_pipe(int_conditional_double_move); | |
| 7078 %} | |
| 7079 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7080 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7081 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7082 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7083 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7084 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7085 format %{ "FMOVD$cmp $icc,$src,$dst" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7086 opcode(0x102); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7087 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7088 ins_pipe(int_conditional_double_move); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7089 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7090 |
| 0 | 7091 // Conditional move, |
| 7092 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
| 7093 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
| 7094 ins_cost(150); | |
| 7095 size(4); | |
| 7096 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
| 7097 opcode(0x2); | |
| 7098 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 7099 ins_pipe(int_conditional_double_move); | |
| 7100 %} | |
| 7101 | |
| 7102 // Conditional move | |
| 7103 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
| 7104 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 7105 ins_cost(150); | |
| 7106 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 7107 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7108 ins_pipe(ialu_reg); | |
| 7109 %} | |
| 7110 | |
| 7111 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
| 7112 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 7113 ins_cost(140); | |
| 7114 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 7115 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7116 ins_pipe(ialu_imm); | |
| 7117 %} | |
| 7118 | |
| 7119 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
| 7120 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
| 7121 ins_cost(150); | |
| 7122 | |
| 7123 size(4); | |
| 7124 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
| 7125 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 7126 ins_pipe(ialu_reg); | |
| 7127 %} | |
| 7128 | |
| 7129 | |
|
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7130 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7131 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7132 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7133 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7134 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7135 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7136 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7137 ins_pipe(ialu_reg); |
|
f24201449cac
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diff
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|
7138 %} |
|
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diff
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|
7139 |
|
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|
7140 |
| 0 | 7141 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ |
| 7142 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
| 7143 ins_cost(150); | |
| 7144 | |
| 7145 size(4); | |
| 7146 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
| 7147 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 7148 ins_pipe(ialu_reg); | |
| 7149 %} | |
| 7150 | |
| 7151 | |
| 7152 | |
| 7153 //----------OS and Locking Instructions---------------------------------------- | |
| 7154 | |
| 7155 // This name is KNOWN by the ADLC and cannot be changed. | |
| 7156 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 7157 // for this guy. | |
| 7158 instruct tlsLoadP(g2RegP dst) %{ | |
| 7159 match(Set dst (ThreadLocal)); | |
| 7160 | |
| 7161 size(0); | |
| 7162 ins_cost(0); | |
| 7163 format %{ "# TLS is in G2" %} | |
| 7164 ins_encode( /*empty encoding*/ ); | |
| 7165 ins_pipe(ialu_none); | |
| 7166 %} | |
| 7167 | |
| 7168 instruct checkCastPP( iRegP dst ) %{ | |
| 7169 match(Set dst (CheckCastPP dst)); | |
| 7170 | |
| 7171 size(0); | |
| 7172 format %{ "# checkcastPP of $dst" %} | |
| 7173 ins_encode( /*empty encoding*/ ); | |
| 7174 ins_pipe(empty); | |
| 7175 %} | |
| 7176 | |
| 7177 | |
| 7178 instruct castPP( iRegP dst ) %{ | |
| 7179 match(Set dst (CastPP dst)); | |
| 7180 format %{ "# castPP of $dst" %} | |
| 7181 ins_encode( /*empty encoding*/ ); | |
| 7182 ins_pipe(empty); | |
| 7183 %} | |
| 7184 | |
| 7185 instruct castII( iRegI dst ) %{ | |
| 7186 match(Set dst (CastII dst)); | |
| 7187 format %{ "# castII of $dst" %} | |
| 7188 ins_encode( /*empty encoding*/ ); | |
| 7189 ins_cost(0); | |
| 7190 ins_pipe(empty); | |
| 7191 %} | |
| 7192 | |
| 7193 //----------Arithmetic Instructions-------------------------------------------- | |
| 7194 // Addition Instructions | |
| 7195 // Register Addition | |
| 7196 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7197 match(Set dst (AddI src1 src2)); | |
| 7198 | |
| 7199 size(4); | |
| 7200 format %{ "ADD $src1,$src2,$dst" %} | |
| 7201 ins_encode %{ | |
| 7202 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
| 7203 %} | |
| 7204 ins_pipe(ialu_reg_reg); | |
| 7205 %} | |
| 7206 | |
| 7207 // Immediate Addition | |
| 7208 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7209 match(Set dst (AddI src1 src2)); | |
| 7210 | |
| 7211 size(4); | |
| 7212 format %{ "ADD $src1,$src2,$dst" %} | |
| 7213 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7214 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7215 ins_pipe(ialu_reg_imm); | |
| 7216 %} | |
| 7217 | |
| 7218 // Pointer Register Addition | |
| 7219 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
| 7220 match(Set dst (AddP src1 src2)); | |
| 7221 | |
| 7222 size(4); | |
| 7223 format %{ "ADD $src1,$src2,$dst" %} | |
| 7224 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7225 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7226 ins_pipe(ialu_reg_reg); | |
| 7227 %} | |
| 7228 | |
| 7229 // Pointer Immediate Addition | |
| 7230 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
| 7231 match(Set dst (AddP src1 src2)); | |
| 7232 | |
| 7233 size(4); | |
| 7234 format %{ "ADD $src1,$src2,$dst" %} | |
| 7235 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7236 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7237 ins_pipe(ialu_reg_imm); | |
| 7238 %} | |
| 7239 | |
| 7240 // Long Addition | |
| 7241 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7242 match(Set dst (AddL src1 src2)); | |
| 7243 | |
| 7244 size(4); | |
| 7245 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
| 7246 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7247 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7248 ins_pipe(ialu_reg_reg); | |
| 7249 %} | |
| 7250 | |
| 7251 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7252 match(Set dst (AddL src1 con)); | |
| 7253 | |
| 7254 size(4); | |
| 7255 format %{ "ADD $src1,$con,$dst" %} | |
| 7256 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7257 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7258 ins_pipe(ialu_reg_imm); | |
| 7259 %} | |
| 7260 | |
| 7261 //----------Conditional_store-------------------------------------------------- | |
| 7262 // Conditional-store of the updated heap-top. | |
| 7263 // Used during allocation of the shared heap. | |
| 7264 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
| 7265 | |
| 7266 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
| 7267 instruct loadPLocked(iRegP dst, memory mem) %{ | |
| 7268 match(Set dst (LoadPLocked mem)); | |
| 7269 ins_cost(MEMORY_REF_COST); | |
| 7270 | |
| 7271 #ifndef _LP64 | |
| 7272 size(4); | |
| 7273 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 7274 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
| 7275 #else | |
| 7276 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 7277 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
| 7278 #endif | |
| 7279 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 7280 ins_pipe(iload_mem); | |
| 7281 %} | |
| 7282 | |
| 7283 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
| 7284 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7285 effect( KILL newval ); | |
| 7286 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
| 7287 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
| 7288 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
| 7289 ins_pipe( long_memory_op ); | |
| 7290 %} | |
| 7291 | |
|
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|
7292 // Conditional-store of an int value. |
|
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|
7293 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
|
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|
7294 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
|
a1980da045cc
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|
7295 effect( KILL newval ); |
|
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changeset
|
7296 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
|
a1980da045cc
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changeset
|
7297 "CMP $oldval,$newval\t\t! See if we made progress" %} |
|
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|
7298 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7299 ins_pipe( long_memory_op ); |
| 7300 %} | |
| 7301 | |
|
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|
7302 // Conditional-store of a long value. |
|
a1980da045cc
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|
7303 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
|
a1980da045cc
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|
7304 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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changeset
|
7305 effect( KILL newval ); |
|
a1980da045cc
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changeset
|
7306 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
|
a1980da045cc
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changeset
|
7307 "CMP $oldval,$newval\t\t! See if we made progress" %} |
|
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changeset
|
7308 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7309 ins_pipe( long_memory_op ); |
| 7310 %} | |
| 7311 | |
| 7312 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7313 | |
| 7314 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
|
6795
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|
7315 predicate(VM_Version::supports_cx8()); |
| 0 | 7316 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
| 7317 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7318 format %{ | |
| 7319 "MOV $newval,O7\n\t" | |
| 7320 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7321 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7322 "MOV 1,$res\n\t" | |
| 7323 "MOVne xcc,R_G0,$res" | |
| 7324 %} | |
| 7325 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
| 7326 enc_lflags_ne_to_boolean(res) ); | |
| 7327 ins_pipe( long_memory_op ); | |
| 7328 %} | |
| 7329 | |
| 7330 | |
| 7331 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7332 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 7333 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7334 format %{ | |
| 7335 "MOV $newval,O7\n\t" | |
| 7336 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7337 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7338 "MOV 1,$res\n\t" | |
| 7339 "MOVne icc,R_G0,$res" | |
| 7340 %} | |
| 7341 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
| 7342 enc_iflags_ne_to_boolean(res) ); | |
| 7343 ins_pipe( long_memory_op ); | |
| 7344 %} | |
| 7345 | |
| 7346 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
|
6795
7eca5de9e0b6
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|
7347 #ifdef _LP64 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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|
7348 predicate(VM_Version::supports_cx8()); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
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|
7349 #endif |
| 0 | 7350 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
| 7351 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7352 format %{ | |
| 7353 "MOV $newval,O7\n\t" | |
|
113
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6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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|
7354 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
| 0 | 7355 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
| 7356 "MOV 1,$res\n\t" | |
| 7357 "MOVne xcc,R_G0,$res" | |
| 7358 %} | |
|
113
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|
7359 #ifdef _LP64 |
| 0 | 7360 ins_encode( enc_casx(mem_ptr, oldval, newval), |
| 7361 enc_lflags_ne_to_boolean(res) ); | |
| 7362 #else | |
|
113
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|
7363 ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
ba764ed4b6f2
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changeset
|
7364 enc_iflags_ne_to_boolean(res) ); |
|
ba764ed4b6f2
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changeset
|
7365 #endif |
|
ba764ed4b6f2
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changeset
|
7366 ins_pipe( long_memory_op ); |
|
ba764ed4b6f2
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changeset
|
7367 %} |
|
ba764ed4b6f2
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changeset
|
7368 |
|
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
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|
7369 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
|
113
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|
7370 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
|
181
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|
7371 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
| 0 | 7372 format %{ |
| 7373 "MOV $newval,O7\n\t" | |
| 7374 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7375 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7376 "MOV 1,$res\n\t" | |
| 7377 "MOVne icc,R_G0,$res" | |
| 7378 %} | |
|
181
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|
7379 ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
823298b11afc
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|
7380 enc_iflags_ne_to_boolean(res) ); |
| 0 | 7381 ins_pipe( long_memory_op ); |
| 7382 %} | |
| 7383 | |
|
6795
7eca5de9e0b6
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diff
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|
7384 instruct xchgI( memory mem, iRegI newval) %{ |
|
7eca5de9e0b6
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|
7385 match(Set newval (GetAndSetI mem newval)); |
|
7eca5de9e0b6
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|
7386 format %{ "SWAP [$mem],$newval" %} |
|
7eca5de9e0b6
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|
7387 size(4); |
|
7eca5de9e0b6
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diff
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|
7388 ins_encode %{ |
|
7eca5de9e0b6
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diff
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|
7389 __ swap($mem$$Address, $newval$$Register); |
|
7eca5de9e0b6
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|
7390 %} |
|
7eca5de9e0b6
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|
7391 ins_pipe( long_memory_op ); |
|
7eca5de9e0b6
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|
7392 %} |
|
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|
7393 |
|
7eca5de9e0b6
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|
7394 #ifndef _LP64 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7395 instruct xchgP( memory mem, iRegP newval) %{ |
|
7eca5de9e0b6
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|
7396 match(Set newval (GetAndSetP mem newval)); |
|
7eca5de9e0b6
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|
7397 format %{ "SWAP [$mem],$newval" %} |
|
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|
7398 size(4); |
|
7eca5de9e0b6
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changeset
|
7399 ins_encode %{ |
|
7eca5de9e0b6
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|
7400 __ swap($mem$$Address, $newval$$Register); |
|
7eca5de9e0b6
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|
7401 %} |
|
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changeset
|
7402 ins_pipe( long_memory_op ); |
|
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|
7403 %} |
|
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|
7404 #endif |
|
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|
7405 |
|
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|
7406 instruct xchgN( memory mem, iRegN newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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|
7407 match(Set newval (GetAndSetN mem newval)); |
|
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|
7408 format %{ "SWAP [$mem],$newval" %} |
|
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7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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7409 size(4); |
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7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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7410 ins_encode %{ |
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7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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|
7411 __ swap($mem$$Address, $newval$$Register); |
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7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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7412 %} |
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7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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7413 ins_pipe( long_memory_op ); |
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7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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7414 %} |
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7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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7415 |
| 0 | 7416 //--------------------- |
| 7417 // Subtraction Instructions | |
| 7418 // Register Subtraction | |
| 7419 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7420 match(Set dst (SubI src1 src2)); | |
| 7421 | |
| 7422 size(4); | |
| 7423 format %{ "SUB $src1,$src2,$dst" %} | |
| 7424 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7425 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7426 ins_pipe(ialu_reg_reg); | |
| 7427 %} | |
| 7428 | |
| 7429 // Immediate Subtraction | |
| 7430 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7431 match(Set dst (SubI src1 src2)); | |
| 7432 | |
| 7433 size(4); | |
| 7434 format %{ "SUB $src1,$src2,$dst" %} | |
| 7435 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7436 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7437 ins_pipe(ialu_reg_imm); | |
| 7438 %} | |
| 7439 | |
| 7440 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 7441 match(Set dst (SubI zero src2)); | |
| 7442 | |
| 7443 size(4); | |
| 7444 format %{ "NEG $src2,$dst" %} | |
| 7445 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7446 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7447 ins_pipe(ialu_zero_reg); | |
| 7448 %} | |
| 7449 | |
| 7450 // Long subtraction | |
| 7451 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7452 match(Set dst (SubL src1 src2)); | |
| 7453 | |
| 7454 size(4); | |
| 7455 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7456 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7457 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7458 ins_pipe(ialu_reg_reg); | |
| 7459 %} | |
| 7460 | |
| 7461 // Immediate Subtraction | |
| 7462 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7463 match(Set dst (SubL src1 con)); | |
| 7464 | |
| 7465 size(4); | |
| 7466 format %{ "SUB $src1,$con,$dst\t! long" %} | |
| 7467 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7468 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7469 ins_pipe(ialu_reg_imm); | |
| 7470 %} | |
| 7471 | |
| 7472 // Long negation | |
| 7473 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
| 7474 match(Set dst (SubL zero src2)); | |
| 7475 | |
| 7476 size(4); | |
| 7477 format %{ "NEG $src2,$dst\t! long" %} | |
| 7478 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7479 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7480 ins_pipe(ialu_zero_reg); | |
| 7481 %} | |
| 7482 | |
| 7483 // Multiplication Instructions | |
| 7484 // Integer Multiplication | |
| 7485 // Register Multiplication | |
| 7486 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7487 match(Set dst (MulI src1 src2)); | |
| 7488 | |
| 7489 size(4); | |
| 7490 format %{ "MULX $src1,$src2,$dst" %} | |
| 7491 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7492 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7493 ins_pipe(imul_reg_reg); | |
| 7494 %} | |
| 7495 | |
| 7496 // Immediate Multiplication | |
| 7497 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7498 match(Set dst (MulI src1 src2)); | |
| 7499 | |
| 7500 size(4); | |
| 7501 format %{ "MULX $src1,$src2,$dst" %} | |
| 7502 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7503 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7504 ins_pipe(imul_reg_imm); | |
| 7505 %} | |
| 7506 | |
| 7507 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7508 match(Set dst (MulL src1 src2)); | |
| 7509 ins_cost(DEFAULT_COST * 5); | |
| 7510 size(4); | |
| 7511 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7512 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7513 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7514 ins_pipe(mulL_reg_reg); | |
| 7515 %} | |
| 7516 | |
| 7517 // Immediate Multiplication | |
| 7518 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7519 match(Set dst (MulL src1 src2)); | |
| 7520 ins_cost(DEFAULT_COST * 5); | |
| 7521 size(4); | |
| 7522 format %{ "MULX $src1,$src2,$dst" %} | |
| 7523 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7524 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7525 ins_pipe(mulL_reg_imm); | |
| 7526 %} | |
| 7527 | |
| 7528 // Integer Division | |
| 7529 // Register Division | |
| 7530 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 7531 match(Set dst (DivI src1 src2)); | |
| 7532 ins_cost((2+71)*DEFAULT_COST); | |
| 7533 | |
| 7534 format %{ "SRA $src2,0,$src2\n\t" | |
| 7535 "SRA $src1,0,$src1\n\t" | |
| 7536 "SDIVX $src1,$src2,$dst" %} | |
| 7537 ins_encode( idiv_reg( src1, src2, dst ) ); | |
| 7538 ins_pipe(sdiv_reg_reg); | |
| 7539 %} | |
| 7540 | |
| 7541 // Immediate Division | |
| 7542 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
| 7543 match(Set dst (DivI src1 src2)); | |
| 7544 ins_cost((2+71)*DEFAULT_COST); | |
| 7545 | |
| 7546 format %{ "SRA $src1,0,$src1\n\t" | |
| 7547 "SDIVX $src1,$src2,$dst" %} | |
| 7548 ins_encode( idiv_imm( src1, src2, dst ) ); | |
| 7549 ins_pipe(sdiv_reg_imm); | |
| 7550 %} | |
| 7551 | |
| 7552 //----------Div-By-10-Expansion------------------------------------------------ | |
| 7553 // Extract hi bits of a 32x32->64 bit multiply. | |
| 7554 // Expand rule only, not matched | |
| 7555 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
| 7556 effect( DEF dst, USE src1, USE src2 ); | |
| 7557 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
| 7558 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
| 7559 ins_encode( enc_mul_hi(dst,src1,src2)); | |
| 7560 ins_pipe(sdiv_reg_reg); | |
| 7561 %} | |
| 7562 | |
| 605 | 7563 // Magic constant, reciprocal of 10 |
| 0 | 7564 instruct loadConI_x66666667(iRegIsafe dst) %{ |
| 7565 effect( DEF dst ); | |
| 7566 | |
| 7567 size(8); | |
| 7568 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
| 7569 ins_encode( Set32(0x66666667, dst) ); | |
| 7570 ins_pipe(ialu_hi_lo_reg); | |
| 7571 %} | |
| 7572 | |
| 605 | 7573 // Register Shift Right Arithmetic Long by 32-63 |
| 0 | 7574 instruct sra_31( iRegI dst, iRegI src ) %{ |
| 7575 effect( DEF dst, USE src ); | |
| 7576 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
| 7577 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
| 7578 ins_pipe(ialu_reg_reg); | |
| 7579 %} | |
| 7580 | |
| 7581 // Arithmetic Shift Right by 8-bit immediate | |
| 7582 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
| 7583 effect( DEF dst, USE src ); | |
| 7584 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
| 7585 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7586 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
| 7587 ins_pipe(ialu_reg_imm); | |
| 7588 %} | |
| 7589 | |
| 7590 // Integer DIV with 10 | |
| 7591 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
| 7592 match(Set dst (DivI src div)); | |
| 7593 ins_cost((6+6)*DEFAULT_COST); | |
| 7594 expand %{ | |
| 7595 iRegIsafe tmp1; // Killed temps; | |
| 7596 iRegIsafe tmp2; // Killed temps; | |
| 7597 iRegI tmp3; // Killed temps; | |
| 7598 iRegI tmp4; // Killed temps; | |
| 7599 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
| 7600 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
| 7601 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
| 7602 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
| 7603 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
| 7604 %} | |
| 7605 %} | |
| 7606 | |
| 7607 // Register Long Division | |
| 7608 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7609 match(Set dst (DivL src1 src2)); | |
| 7610 ins_cost(DEFAULT_COST*71); | |
| 7611 size(4); | |
| 7612 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7613 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7614 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7615 ins_pipe(divL_reg_reg); | |
| 7616 %} | |
| 7617 | |
| 7618 // Register Long Division | |
| 7619 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7620 match(Set dst (DivL src1 src2)); | |
| 7621 ins_cost(DEFAULT_COST*71); | |
| 7622 size(4); | |
| 7623 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7624 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7625 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7626 ins_pipe(divL_reg_imm); | |
| 7627 %} | |
| 7628 | |
| 7629 // Integer Remainder | |
| 7630 // Register Remainder | |
| 7631 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7632 match(Set dst (ModI src1 src2)); | |
| 7633 effect( KILL ccr, KILL temp); | |
| 7634 | |
| 7635 format %{ "SREM $src1,$src2,$dst" %} | |
| 7636 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
| 7637 ins_pipe(sdiv_reg_reg); | |
| 7638 %} | |
| 7639 | |
| 7640 // Immediate Remainder | |
| 7641 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7642 match(Set dst (ModI src1 src2)); | |
| 7643 effect( KILL ccr, KILL temp); | |
| 7644 | |
| 7645 format %{ "SREM $src1,$src2,$dst" %} | |
| 7646 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
| 7647 ins_pipe(sdiv_reg_imm); | |
| 7648 %} | |
| 7649 | |
| 7650 // Register Long Remainder | |
| 7651 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7652 effect(DEF dst, USE src1, USE src2); | |
| 7653 size(4); | |
| 7654 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7655 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7656 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7657 ins_pipe(divL_reg_reg); | |
| 7658 %} | |
| 7659 | |
| 7660 // Register Long Division | |
| 7661 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7662 effect(DEF dst, USE src1, USE src2); | |
| 7663 size(4); | |
| 7664 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7665 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7666 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7667 ins_pipe(divL_reg_imm); | |
| 7668 %} | |
| 7669 | |
| 7670 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7671 effect(DEF dst, USE src1, USE src2); | |
| 7672 size(4); | |
| 7673 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7674 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7675 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7676 ins_pipe(mulL_reg_reg); | |
| 7677 %} | |
| 7678 | |
| 7679 // Immediate Multiplication | |
| 7680 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7681 effect(DEF dst, USE src1, USE src2); | |
| 7682 size(4); | |
| 7683 format %{ "MULX $src1,$src2,$dst" %} | |
| 7684 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7685 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7686 ins_pipe(mulL_reg_imm); | |
| 7687 %} | |
| 7688 | |
| 7689 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7690 effect(DEF dst, USE src1, USE src2); | |
| 7691 size(4); | |
| 7692 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7693 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7694 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7695 ins_pipe(ialu_reg_reg); | |
| 7696 %} | |
| 7697 | |
| 7698 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7699 effect(DEF dst, USE src1, USE src2); | |
| 7700 size(4); | |
| 7701 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7702 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7703 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7704 ins_pipe(ialu_reg_reg); | |
| 7705 %} | |
| 7706 | |
| 7707 // Register Long Remainder | |
| 7708 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7709 match(Set dst (ModL src1 src2)); | |
| 7710 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7711 expand %{ | |
| 7712 iRegL tmp1; | |
| 7713 iRegL tmp2; | |
| 7714 divL_reg_reg_1(tmp1, src1, src2); | |
| 7715 mulL_reg_reg_1(tmp2, tmp1, src2); | |
| 7716 subL_reg_reg_1(dst, src1, tmp2); | |
| 7717 %} | |
| 7718 %} | |
| 7719 | |
| 7720 // Register Long Remainder | |
| 7721 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7722 match(Set dst (ModL src1 src2)); | |
| 7723 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7724 expand %{ | |
| 7725 iRegL tmp1; | |
| 7726 iRegL tmp2; | |
| 7727 divL_reg_imm13_1(tmp1, src1, src2); | |
| 7728 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
| 7729 subL_reg_reg_2 (dst, src1, tmp2); | |
| 7730 %} | |
| 7731 %} | |
| 7732 | |
| 7733 // Integer Shift Instructions | |
| 7734 // Register Shift Left | |
| 7735 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7736 match(Set dst (LShiftI src1 src2)); | |
| 7737 | |
| 7738 size(4); | |
| 7739 format %{ "SLL $src1,$src2,$dst" %} | |
| 7740 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7741 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7742 ins_pipe(ialu_reg_reg); | |
| 7743 %} | |
| 7744 | |
| 7745 // Register Shift Left Immediate | |
| 7746 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7747 match(Set dst (LShiftI src1 src2)); | |
| 7748 | |
| 7749 size(4); | |
| 7750 format %{ "SLL $src1,$src2,$dst" %} | |
| 7751 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7752 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7753 ins_pipe(ialu_reg_imm); | |
| 7754 %} | |
| 7755 | |
| 7756 // Register Shift Left | |
| 7757 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7758 match(Set dst (LShiftL src1 src2)); | |
| 7759 | |
| 7760 size(4); | |
| 7761 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7762 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7763 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7764 ins_pipe(ialu_reg_reg); | |
| 7765 %} | |
| 7766 | |
| 7767 // Register Shift Left Immediate | |
| 7768 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7769 match(Set dst (LShiftL src1 src2)); | |
| 7770 | |
| 7771 size(4); | |
| 7772 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7773 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7774 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7775 ins_pipe(ialu_reg_imm); | |
| 7776 %} | |
| 7777 | |
| 7778 // Register Arithmetic Shift Right | |
| 7779 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7780 match(Set dst (RShiftI src1 src2)); | |
| 7781 size(4); | |
| 7782 format %{ "SRA $src1,$src2,$dst" %} | |
| 7783 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7784 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7785 ins_pipe(ialu_reg_reg); | |
| 7786 %} | |
| 7787 | |
| 7788 // Register Arithmetic Shift Right Immediate | |
| 7789 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7790 match(Set dst (RShiftI src1 src2)); | |
| 7791 | |
| 7792 size(4); | |
| 7793 format %{ "SRA $src1,$src2,$dst" %} | |
| 7794 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7795 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7796 ins_pipe(ialu_reg_imm); | |
| 7797 %} | |
| 7798 | |
| 7799 // Register Shift Right Arithmatic Long | |
| 7800 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7801 match(Set dst (RShiftL src1 src2)); | |
| 7802 | |
| 7803 size(4); | |
| 7804 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7805 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7806 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7807 ins_pipe(ialu_reg_reg); | |
| 7808 %} | |
| 7809 | |
| 7810 // Register Shift Left Immediate | |
| 7811 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7812 match(Set dst (RShiftL src1 src2)); | |
| 7813 | |
| 7814 size(4); | |
| 7815 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7816 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7817 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7818 ins_pipe(ialu_reg_imm); | |
| 7819 %} | |
| 7820 | |
| 7821 // Register Shift Right | |
| 7822 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7823 match(Set dst (URShiftI src1 src2)); | |
| 7824 | |
| 7825 size(4); | |
| 7826 format %{ "SRL $src1,$src2,$dst" %} | |
| 7827 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7828 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7829 ins_pipe(ialu_reg_reg); | |
| 7830 %} | |
| 7831 | |
| 7832 // Register Shift Right Immediate | |
| 7833 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7834 match(Set dst (URShiftI src1 src2)); | |
| 7835 | |
| 7836 size(4); | |
| 7837 format %{ "SRL $src1,$src2,$dst" %} | |
| 7838 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7839 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7840 ins_pipe(ialu_reg_imm); | |
| 7841 %} | |
| 7842 | |
| 7843 // Register Shift Right | |
| 7844 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7845 match(Set dst (URShiftL src1 src2)); | |
| 7846 | |
| 7847 size(4); | |
| 7848 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7849 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7850 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7851 ins_pipe(ialu_reg_reg); | |
| 7852 %} | |
| 7853 | |
| 7854 // Register Shift Right Immediate | |
| 7855 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7856 match(Set dst (URShiftL src1 src2)); | |
| 7857 | |
| 7858 size(4); | |
| 7859 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7860 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7861 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7862 ins_pipe(ialu_reg_imm); | |
| 7863 %} | |
| 7864 | |
| 7865 // Register Shift Right Immediate with a CastP2X | |
| 7866 #ifdef _LP64 | |
| 7867 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
| 7868 match(Set dst (URShiftL (CastP2X src1) src2)); | |
| 7869 size(4); | |
| 7870 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
| 7871 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7872 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7873 ins_pipe(ialu_reg_imm); | |
| 7874 %} | |
| 7875 #else | |
| 7876 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
| 7877 match(Set dst (URShiftI (CastP2X src1) src2)); | |
| 7878 size(4); | |
| 7879 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
| 7880 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7881 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7882 ins_pipe(ialu_reg_imm); | |
| 7883 %} | |
| 7884 #endif | |
| 7885 | |
| 7886 | |
| 7887 //----------Floating Point Arithmetic Instructions----------------------------- | |
| 7888 | |
| 7889 // Add float single precision | |
| 7890 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7891 match(Set dst (AddF src1 src2)); | |
| 7892 | |
| 7893 size(4); | |
| 7894 format %{ "FADDS $src1,$src2,$dst" %} | |
| 7895 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
| 7896 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7897 ins_pipe(faddF_reg_reg); | |
| 7898 %} | |
| 7899 | |
| 7900 // Add float double precision | |
| 7901 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7902 match(Set dst (AddD src1 src2)); | |
| 7903 | |
| 7904 size(4); | |
| 7905 format %{ "FADDD $src1,$src2,$dst" %} | |
| 7906 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 7907 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7908 ins_pipe(faddD_reg_reg); | |
| 7909 %} | |
| 7910 | |
| 7911 // Sub float single precision | |
| 7912 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7913 match(Set dst (SubF src1 src2)); | |
| 7914 | |
| 7915 size(4); | |
| 7916 format %{ "FSUBS $src1,$src2,$dst" %} | |
| 7917 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
| 7918 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7919 ins_pipe(faddF_reg_reg); | |
| 7920 %} | |
| 7921 | |
| 7922 // Sub float double precision | |
| 7923 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7924 match(Set dst (SubD src1 src2)); | |
| 7925 | |
| 7926 size(4); | |
| 7927 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 7928 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 7929 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7930 ins_pipe(faddD_reg_reg); | |
| 7931 %} | |
| 7932 | |
| 7933 // Mul float single precision | |
| 7934 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7935 match(Set dst (MulF src1 src2)); | |
| 7936 | |
| 7937 size(4); | |
| 7938 format %{ "FMULS $src1,$src2,$dst" %} | |
| 7939 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
| 7940 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7941 ins_pipe(fmulF_reg_reg); | |
| 7942 %} | |
| 7943 | |
| 7944 // Mul float double precision | |
| 7945 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7946 match(Set dst (MulD src1 src2)); | |
| 7947 | |
| 7948 size(4); | |
| 7949 format %{ "FMULD $src1,$src2,$dst" %} | |
| 7950 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 7951 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7952 ins_pipe(fmulD_reg_reg); | |
| 7953 %} | |
| 7954 | |
| 7955 // Div float single precision | |
| 7956 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7957 match(Set dst (DivF src1 src2)); | |
| 7958 | |
| 7959 size(4); | |
| 7960 format %{ "FDIVS $src1,$src2,$dst" %} | |
| 7961 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
| 7962 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7963 ins_pipe(fdivF_reg_reg); | |
| 7964 %} | |
| 7965 | |
| 7966 // Div float double precision | |
| 7967 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7968 match(Set dst (DivD src1 src2)); | |
| 7969 | |
| 7970 size(4); | |
| 7971 format %{ "FDIVD $src1,$src2,$dst" %} | |
| 7972 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
| 7973 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7974 ins_pipe(fdivD_reg_reg); | |
| 7975 %} | |
| 7976 | |
| 7977 // Absolute float double precision | |
| 7978 instruct absD_reg(regD dst, regD src) %{ | |
| 7979 match(Set dst (AbsD src)); | |
| 7980 | |
| 7981 format %{ "FABSd $src,$dst" %} | |
| 7982 ins_encode(fabsd(dst, src)); | |
| 7983 ins_pipe(faddD_reg); | |
| 7984 %} | |
| 7985 | |
| 7986 // Absolute float single precision | |
| 7987 instruct absF_reg(regF dst, regF src) %{ | |
| 7988 match(Set dst (AbsF src)); | |
| 7989 | |
| 7990 format %{ "FABSs $src,$dst" %} | |
| 7991 ins_encode(fabss(dst, src)); | |
| 7992 ins_pipe(faddF_reg); | |
| 7993 %} | |
| 7994 | |
| 7995 instruct negF_reg(regF dst, regF src) %{ | |
| 7996 match(Set dst (NegF src)); | |
| 7997 | |
| 7998 size(4); | |
| 7999 format %{ "FNEGs $src,$dst" %} | |
| 8000 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
| 8001 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
| 8002 ins_pipe(faddF_reg); | |
| 8003 %} | |
| 8004 | |
| 8005 instruct negD_reg(regD dst, regD src) %{ | |
| 8006 match(Set dst (NegD src)); | |
| 8007 | |
| 8008 format %{ "FNEGd $src,$dst" %} | |
| 8009 ins_encode(fnegd(dst, src)); | |
| 8010 ins_pipe(faddD_reg); | |
| 8011 %} | |
| 8012 | |
| 8013 // Sqrt float double precision | |
| 8014 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
| 8015 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 8016 | |
| 8017 size(4); | |
| 8018 format %{ "FSQRTS $src,$dst" %} | |
| 8019 ins_encode(fsqrts(dst, src)); | |
| 8020 ins_pipe(fdivF_reg_reg); | |
| 8021 %} | |
| 8022 | |
| 8023 // Sqrt float double precision | |
| 8024 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
| 8025 match(Set dst (SqrtD src)); | |
| 8026 | |
| 8027 size(4); | |
| 8028 format %{ "FSQRTD $src,$dst" %} | |
| 8029 ins_encode(fsqrtd(dst, src)); | |
| 8030 ins_pipe(fdivD_reg_reg); | |
| 8031 %} | |
| 8032 | |
| 8033 //----------Logical Instructions----------------------------------------------- | |
| 8034 // And Instructions | |
| 8035 // Register And | |
| 8036 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 8037 match(Set dst (AndI src1 src2)); | |
| 8038 | |
| 8039 size(4); | |
| 8040 format %{ "AND $src1,$src2,$dst" %} | |
| 8041 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 8042 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8043 ins_pipe(ialu_reg_reg); | |
| 8044 %} | |
| 8045 | |
| 8046 // Immediate And | |
| 8047 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 8048 match(Set dst (AndI src1 src2)); | |
| 8049 | |
| 8050 size(4); | |
| 8051 format %{ "AND $src1,$src2,$dst" %} | |
| 8052 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 8053 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 8054 ins_pipe(ialu_reg_imm); | |
| 8055 %} | |
| 8056 | |
| 8057 // Register And Long | |
| 8058 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 8059 match(Set dst (AndL src1 src2)); | |
| 8060 | |
| 8061 ins_cost(DEFAULT_COST); | |
| 8062 size(4); | |
| 8063 format %{ "AND $src1,$src2,$dst\t! long" %} | |
| 8064 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 8065 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8066 ins_pipe(ialu_reg_reg); | |
| 8067 %} | |
| 8068 | |
| 8069 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 8070 match(Set dst (AndL src1 con)); | |
| 8071 | |
| 8072 ins_cost(DEFAULT_COST); | |
| 8073 size(4); | |
| 8074 format %{ "AND $src1,$con,$dst\t! long" %} | |
| 8075 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 8076 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 8077 ins_pipe(ialu_reg_imm); | |
| 8078 %} | |
| 8079 | |
| 8080 // Or Instructions | |
| 8081 // Register Or | |
| 8082 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 8083 match(Set dst (OrI src1 src2)); | |
| 8084 | |
| 8085 size(4); | |
| 8086 format %{ "OR $src1,$src2,$dst" %} | |
| 8087 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8088 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8089 ins_pipe(ialu_reg_reg); | |
| 8090 %} | |
| 8091 | |
| 8092 // Immediate Or | |
| 8093 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 8094 match(Set dst (OrI src1 src2)); | |
| 8095 | |
| 8096 size(4); | |
| 8097 format %{ "OR $src1,$src2,$dst" %} | |
| 8098 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8099 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 8100 ins_pipe(ialu_reg_imm); | |
| 8101 %} | |
| 8102 | |
| 8103 // Register Or Long | |
| 8104 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 8105 match(Set dst (OrL src1 src2)); | |
| 8106 | |
| 8107 ins_cost(DEFAULT_COST); | |
| 8108 size(4); | |
| 8109 format %{ "OR $src1,$src2,$dst\t! long" %} | |
| 8110 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8111 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8112 ins_pipe(ialu_reg_reg); | |
| 8113 %} | |
| 8114 | |
| 8115 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 8116 match(Set dst (OrL src1 con)); | |
| 8117 ins_cost(DEFAULT_COST*2); | |
| 8118 | |
| 8119 ins_cost(DEFAULT_COST); | |
| 8120 size(4); | |
| 8121 format %{ "OR $src1,$con,$dst\t! long" %} | |
| 8122 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8123 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 8124 ins_pipe(ialu_reg_imm); | |
| 8125 %} | |
| 8126 | |
|
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8127 #ifndef _LP64 |
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8128 |
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8129 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
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8130 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
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8131 match(Set dst (OrI src1 (CastP2X src2))); |
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8132 |
|
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8133 size(4); |
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8134 format %{ "OR $src1,$src2,$dst" %} |
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8135 opcode(Assembler::or_op3, Assembler::arith_op); |
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8136 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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8137 ins_pipe(ialu_reg_reg); |
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8138 %} |
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8139 |
|
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8140 #else |
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8141 |
|
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8142 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
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8143 match(Set dst (OrL src1 (CastP2X src2))); |
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8144 |
|
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8145 ins_cost(DEFAULT_COST); |
|
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8146 size(4); |
|
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8147 format %{ "OR $src1,$src2,$dst\t! long" %} |
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8148 opcode(Assembler::or_op3, Assembler::arith_op); |
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8149 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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8150 ins_pipe(ialu_reg_reg); |
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8151 %} |
|
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8152 |
|
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8153 #endif |
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8154 |
| 0 | 8155 // Xor Instructions |
| 8156 // Register Xor | |
| 8157 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 8158 match(Set dst (XorI src1 src2)); | |
| 8159 | |
| 8160 size(4); | |
| 8161 format %{ "XOR $src1,$src2,$dst" %} | |
| 8162 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8163 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8164 ins_pipe(ialu_reg_reg); | |
| 8165 %} | |
| 8166 | |
| 8167 // Immediate Xor | |
| 8168 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 8169 match(Set dst (XorI src1 src2)); | |
| 8170 | |
| 8171 size(4); | |
| 8172 format %{ "XOR $src1,$src2,$dst" %} | |
| 8173 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8174 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 8175 ins_pipe(ialu_reg_imm); | |
| 8176 %} | |
| 8177 | |
| 8178 // Register Xor Long | |
| 8179 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 8180 match(Set dst (XorL src1 src2)); | |
| 8181 | |
| 8182 ins_cost(DEFAULT_COST); | |
| 8183 size(4); | |
| 8184 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
| 8185 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8186 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8187 ins_pipe(ialu_reg_reg); | |
| 8188 %} | |
| 8189 | |
| 8190 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 8191 match(Set dst (XorL src1 con)); | |
| 8192 | |
| 8193 ins_cost(DEFAULT_COST); | |
| 8194 size(4); | |
| 8195 format %{ "XOR $src1,$con,$dst\t! long" %} | |
| 8196 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8197 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 8198 ins_pipe(ialu_reg_imm); | |
| 8199 %} | |
| 8200 | |
| 8201 //----------Convert to Boolean------------------------------------------------- | |
| 8202 // Nice hack for 32-bit tests but doesn't work for | |
| 8203 // 64-bit pointers. | |
| 8204 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
| 8205 match(Set dst (Conv2B src)); | |
| 8206 effect( KILL ccr ); | |
| 8207 ins_cost(DEFAULT_COST*2); | |
| 8208 format %{ "CMP R_G0,$src\n\t" | |
| 8209 "ADDX R_G0,0,$dst" %} | |
| 8210 ins_encode( enc_to_bool( src, dst ) ); | |
| 8211 ins_pipe(ialu_reg_ialu); | |
| 8212 %} | |
| 8213 | |
| 8214 #ifndef _LP64 | |
| 8215 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
| 8216 match(Set dst (Conv2B src)); | |
| 8217 effect( KILL ccr ); | |
| 8218 ins_cost(DEFAULT_COST*2); | |
| 8219 format %{ "CMP R_G0,$src\n\t" | |
| 8220 "ADDX R_G0,0,$dst" %} | |
| 8221 ins_encode( enc_to_bool( src, dst ) ); | |
| 8222 ins_pipe(ialu_reg_ialu); | |
| 8223 %} | |
| 8224 #else | |
| 8225 instruct convP2B( iRegI dst, iRegP src ) %{ | |
| 8226 match(Set dst (Conv2B src)); | |
| 8227 ins_cost(DEFAULT_COST*2); | |
| 8228 format %{ "MOV $src,$dst\n\t" | |
| 8229 "MOVRNZ $src,1,$dst" %} | |
| 8230 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
| 8231 ins_pipe(ialu_clr_and_mover); | |
| 8232 %} | |
| 8233 #endif | |
| 8234 | |
|
2254
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7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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|
8235 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ |
|
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7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8236 match(Set dst (CmpLTMask src zero)); |
|
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7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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diff
changeset
|
8237 effect(KILL ccr); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8238 size(4); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8239 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8240 ins_encode %{ |
|
ab42c7e1cf83
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2121
diff
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|
8241 __ sra($src$$Register, 31, $dst$$Register); |
|
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|
8242 %} |
|
ab42c7e1cf83
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2121
diff
changeset
|
8243 ins_pipe(ialu_reg_imm); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
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2121
diff
changeset
|
8244 %} |
|
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changeset
|
8245 |
| 0 | 8246 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ |
| 8247 match(Set dst (CmpLTMask p q)); | |
| 8248 effect( KILL ccr ); | |
| 8249 ins_cost(DEFAULT_COST*4); | |
| 8250 format %{ "CMP $p,$q\n\t" | |
| 8251 "MOV #0,$dst\n\t" | |
| 8252 "BLT,a .+8\n\t" | |
| 8253 "MOV #-1,$dst" %} | |
| 8254 ins_encode( enc_ltmask(p,q,dst) ); | |
| 8255 ins_pipe(ialu_reg_reg_ialu); | |
| 8256 %} | |
| 8257 | |
| 8258 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
| 8259 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 8260 effect(KILL ccr, TEMP tmp); | |
| 8261 ins_cost(DEFAULT_COST*3); | |
| 8262 | |
| 8263 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
| 8264 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
|
2254
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7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
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changeset
|
8265 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} |
| 9154 | 8266 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp)); |
| 8267 ins_pipe(cadd_cmpltmask); | |
| 8268 %} | |
| 8269 | |
| 8270 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{ | |
| 8271 match(Set p (AndI (CmpLTMask p q) y)); | |
| 8272 effect(KILL ccr); | |
| 8273 ins_cost(DEFAULT_COST*3); | |
| 8274 | |
| 8275 format %{ "CMP $p,$q\n\t" | |
| 8276 "MOV $y,$p\n\t" | |
| 8277 "MOVge G0,$p" %} | |
| 8278 ins_encode %{ | |
| 8279 __ cmp($p$$Register, $q$$Register); | |
| 8280 __ mov($y$$Register, $p$$Register); | |
| 8281 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register); | |
| 8282 %} | |
| 8283 ins_pipe(ialu_reg_reg_ialu); | |
| 8284 %} | |
| 3804 | 8285 |
| 8286 //----------------------------------------------------------------- | |
| 8287 // Direct raw moves between float and general registers using VIS3. | |
| 8288 | |
| 8289 // ins_pipe(faddF_reg); | |
| 8290 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ | |
| 8291 predicate(UseVIS >= 3); | |
| 8292 match(Set dst (MoveF2I src)); | |
| 8293 | |
| 8294 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} | |
| 8295 ins_encode %{ | |
| 8296 __ movstouw($src$$FloatRegister, $dst$$Register); | |
| 8297 %} | |
| 8298 ins_pipe(ialu_reg_reg); | |
| 8299 %} | |
| 8300 | |
| 8301 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ | |
| 8302 predicate(UseVIS >= 3); | |
| 8303 match(Set dst (MoveI2F src)); | |
| 8304 | |
| 8305 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} | |
| 8306 ins_encode %{ | |
| 8307 __ movwtos($src$$Register, $dst$$FloatRegister); | |
| 8308 %} | |
| 0 | 8309 ins_pipe(ialu_reg_reg); |
| 8310 %} | |
| 8311 | |
| 3804 | 8312 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ |
| 8313 predicate(UseVIS >= 3); | |
| 8314 match(Set dst (MoveD2L src)); | |
| 8315 | |
| 8316 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} | |
| 8317 ins_encode %{ | |
| 8318 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); | |
| 8319 %} | |
| 0 | 8320 ins_pipe(ialu_reg_reg); |
| 8321 %} | |
| 8322 | |
| 3804 | 8323 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ |
| 8324 predicate(UseVIS >= 3); | |
| 8325 match(Set dst (MoveL2D src)); | |
| 8326 | |
| 8327 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} | |
| 8328 ins_encode %{ | |
| 8329 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); | |
| 8330 %} | |
| 0 | 8331 ins_pipe(ialu_reg_reg); |
| 8332 %} | |
| 8333 | |
| 3804 | 8334 |
| 8335 // Raw moves between float and general registers using stack. | |
| 8336 | |
| 0 | 8337 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ |
| 8338 match(Set dst (MoveF2I src)); | |
| 8339 effect(DEF dst, USE src); | |
| 8340 ins_cost(MEMORY_REF_COST); | |
| 8341 | |
| 8342 size(4); | |
| 8343 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
| 8344 opcode(Assembler::lduw_op3); | |
|
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|
8345 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8346 ins_pipe(iload_mem); |
| 8347 %} | |
| 8348 | |
| 8349 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 8350 match(Set dst (MoveI2F src)); | |
| 8351 effect(DEF dst, USE src); | |
| 8352 ins_cost(MEMORY_REF_COST); | |
| 8353 | |
| 8354 size(4); | |
| 8355 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
| 8356 opcode(Assembler::ldf_op3); | |
|
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changeset
|
8357 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8358 ins_pipe(floadF_stk); |
| 8359 %} | |
| 8360 | |
| 8361 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
| 8362 match(Set dst (MoveD2L src)); | |
| 8363 effect(DEF dst, USE src); | |
| 8364 ins_cost(MEMORY_REF_COST); | |
| 8365 | |
| 8366 size(4); | |
| 8367 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
| 8368 opcode(Assembler::ldx_op3); | |
|
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changeset
|
8369 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8370 ins_pipe(iload_mem); |
| 8371 %} | |
| 8372 | |
| 8373 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 8374 match(Set dst (MoveL2D src)); | |
| 8375 effect(DEF dst, USE src); | |
| 8376 ins_cost(MEMORY_REF_COST); | |
| 8377 | |
| 8378 size(4); | |
| 8379 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
| 8380 opcode(Assembler::lddf_op3); | |
|
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changeset
|
8381 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8382 ins_pipe(floadD_stk); |
| 8383 %} | |
| 8384 | |
| 8385 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 8386 match(Set dst (MoveF2I src)); | |
| 8387 effect(DEF dst, USE src); | |
| 8388 ins_cost(MEMORY_REF_COST); | |
| 8389 | |
| 8390 size(4); | |
| 3804 | 8391 format %{ "STF $src,$dst\t! MoveF2I" %} |
| 0 | 8392 opcode(Assembler::stf_op3); |
|
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diff
changeset
|
8393 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8394 ins_pipe(fstoreF_stk_reg); |
| 8395 %} | |
| 8396 | |
| 8397 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
| 8398 match(Set dst (MoveI2F src)); | |
| 8399 effect(DEF dst, USE src); | |
| 8400 ins_cost(MEMORY_REF_COST); | |
| 8401 | |
| 8402 size(4); | |
| 3804 | 8403 format %{ "STW $src,$dst\t! MoveI2F" %} |
| 0 | 8404 opcode(Assembler::stw_op3); |
|
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235
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|
8405 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8406 ins_pipe(istore_mem_reg); |
| 8407 %} | |
| 8408 | |
| 8409 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 8410 match(Set dst (MoveD2L src)); | |
| 8411 effect(DEF dst, USE src); | |
| 8412 ins_cost(MEMORY_REF_COST); | |
| 8413 | |
| 8414 size(4); | |
| 3804 | 8415 format %{ "STDF $src,$dst\t! MoveD2L" %} |
| 0 | 8416 opcode(Assembler::stdf_op3); |
|
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235
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|
8417 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8418 ins_pipe(fstoreD_stk_reg); |
| 8419 %} | |
| 8420 | |
| 8421 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
| 8422 match(Set dst (MoveL2D src)); | |
| 8423 effect(DEF dst, USE src); | |
| 8424 ins_cost(MEMORY_REF_COST); | |
| 8425 | |
| 8426 size(4); | |
| 3804 | 8427 format %{ "STX $src,$dst\t! MoveL2D" %} |
| 0 | 8428 opcode(Assembler::stx_op3); |
|
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235
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|
8429 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8430 ins_pipe(istore_mem_reg); |
| 8431 %} | |
| 8432 | |
| 8433 | |
| 3804 | 8434 //----------Arithmetic Conversion Instructions--------------------------------- |
| 8435 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 8436 | |
| 8437 instruct convD2F_reg(regF dst, regD src) %{ | |
| 8438 match(Set dst (ConvD2F src)); | |
| 8439 size(4); | |
| 8440 format %{ "FDTOS $src,$dst" %} | |
| 8441 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
| 8442 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
| 8443 ins_pipe(fcvtD2F); | |
| 8444 %} | |
| 8445 | |
| 8446 | |
| 8447 // Convert a double to an int in a float register. | |
| 8448 // If the double is a NAN, stuff a zero in instead. | |
| 8449 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
| 8450 effect(DEF dst, USE src, KILL fcc0); | |
| 8451 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8452 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8453 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8454 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8455 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8456 "skip:" %} | |
| 8457 ins_encode(form_d2i_helper(src,dst)); | |
| 8458 ins_pipe(fcvtD2I); | |
| 8459 %} | |
| 8460 | |
| 8461 instruct convD2I_stk(stackSlotI dst, regD src) %{ | |
| 8462 match(Set dst (ConvD2I src)); | |
| 8463 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8464 expand %{ | |
| 8465 regF tmp; | |
| 8466 convD2I_helper(tmp, src); | |
| 8467 regF_to_stkI(dst, tmp); | |
| 8468 %} | |
| 8469 %} | |
| 8470 | |
| 8471 instruct convD2I_reg(iRegI dst, regD src) %{ | |
| 8472 predicate(UseVIS >= 3); | |
| 8473 match(Set dst (ConvD2I src)); | |
| 8474 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8475 expand %{ | |
| 8476 regF tmp; | |
| 8477 convD2I_helper(tmp, src); | |
| 8478 MoveF2I_reg_reg(dst, tmp); | |
| 8479 %} | |
| 8480 %} | |
| 8481 | |
| 8482 | |
| 8483 // Convert a double to a long in a double register. | |
| 8484 // If the double is a NAN, stuff a zero in instead. | |
| 8485 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
| 8486 effect(DEF dst, USE src, KILL fcc0); | |
| 8487 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8488 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8489 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8490 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8491 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8492 "skip:" %} | |
| 8493 ins_encode(form_d2l_helper(src,dst)); | |
| 8494 ins_pipe(fcvtD2L); | |
| 8495 %} | |
| 8496 | |
| 8497 instruct convD2L_stk(stackSlotL dst, regD src) %{ | |
| 8498 match(Set dst (ConvD2L src)); | |
| 8499 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8500 expand %{ | |
| 8501 regD tmp; | |
| 8502 convD2L_helper(tmp, src); | |
| 8503 regD_to_stkL(dst, tmp); | |
| 8504 %} | |
| 8505 %} | |
| 8506 | |
| 8507 instruct convD2L_reg(iRegL dst, regD src) %{ | |
| 8508 predicate(UseVIS >= 3); | |
| 8509 match(Set dst (ConvD2L src)); | |
| 8510 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8511 expand %{ | |
| 8512 regD tmp; | |
| 8513 convD2L_helper(tmp, src); | |
| 8514 MoveD2L_reg_reg(dst, tmp); | |
| 8515 %} | |
| 8516 %} | |
| 8517 | |
| 8518 | |
| 8519 instruct convF2D_reg(regD dst, regF src) %{ | |
| 8520 match(Set dst (ConvF2D src)); | |
| 8521 format %{ "FSTOD $src,$dst" %} | |
| 8522 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
| 8523 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
| 8524 ins_pipe(fcvtF2D); | |
| 8525 %} | |
| 8526 | |
| 8527 | |
| 8528 // Convert a float to an int in a float register. | |
| 8529 // If the float is a NAN, stuff a zero in instead. | |
| 8530 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
| 8531 effect(DEF dst, USE src, KILL fcc0); | |
| 8532 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8533 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8534 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8535 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8536 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8537 "skip:" %} | |
| 8538 ins_encode(form_f2i_helper(src,dst)); | |
| 8539 ins_pipe(fcvtF2I); | |
| 8540 %} | |
| 8541 | |
| 8542 instruct convF2I_stk(stackSlotI dst, regF src) %{ | |
| 8543 match(Set dst (ConvF2I src)); | |
| 8544 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8545 expand %{ | |
| 8546 regF tmp; | |
| 8547 convF2I_helper(tmp, src); | |
| 8548 regF_to_stkI(dst, tmp); | |
| 8549 %} | |
| 8550 %} | |
| 8551 | |
| 8552 instruct convF2I_reg(iRegI dst, regF src) %{ | |
| 8553 predicate(UseVIS >= 3); | |
| 8554 match(Set dst (ConvF2I src)); | |
| 8555 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8556 expand %{ | |
| 8557 regF tmp; | |
| 8558 convF2I_helper(tmp, src); | |
| 8559 MoveF2I_reg_reg(dst, tmp); | |
| 8560 %} | |
| 8561 %} | |
| 8562 | |
| 8563 | |
| 8564 // Convert a float to a long in a float register. | |
| 8565 // If the float is a NAN, stuff a zero in instead. | |
| 8566 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
| 8567 effect(DEF dst, USE src, KILL fcc0); | |
| 8568 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8569 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8570 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8571 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8572 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8573 "skip:" %} | |
| 8574 ins_encode(form_f2l_helper(src,dst)); | |
| 8575 ins_pipe(fcvtF2L); | |
| 8576 %} | |
| 8577 | |
| 8578 instruct convF2L_stk(stackSlotL dst, regF src) %{ | |
| 8579 match(Set dst (ConvF2L src)); | |
| 8580 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8581 expand %{ | |
| 8582 regD tmp; | |
| 8583 convF2L_helper(tmp, src); | |
| 8584 regD_to_stkL(dst, tmp); | |
| 8585 %} | |
| 8586 %} | |
| 8587 | |
| 8588 instruct convF2L_reg(iRegL dst, regF src) %{ | |
| 8589 predicate(UseVIS >= 3); | |
| 8590 match(Set dst (ConvF2L src)); | |
| 8591 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8592 expand %{ | |
| 8593 regD tmp; | |
| 8594 convF2L_helper(tmp, src); | |
| 8595 MoveD2L_reg_reg(dst, tmp); | |
| 8596 %} | |
| 8597 %} | |
| 8598 | |
| 8599 | |
| 8600 instruct convI2D_helper(regD dst, regF tmp) %{ | |
| 8601 effect(USE tmp, DEF dst); | |
| 8602 format %{ "FITOD $tmp,$dst" %} | |
| 8603 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8604 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
| 8605 ins_pipe(fcvtI2D); | |
| 8606 %} | |
| 8607 | |
| 8608 instruct convI2D_stk(stackSlotI src, regD dst) %{ | |
| 8609 match(Set dst (ConvI2D src)); | |
| 8610 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8611 expand %{ | |
| 8612 regF tmp; | |
| 8613 stkI_to_regF(tmp, src); | |
| 8614 convI2D_helper(dst, tmp); | |
| 8615 %} | |
| 8616 %} | |
| 8617 | |
| 8618 instruct convI2D_reg(regD_low dst, iRegI src) %{ | |
| 8619 predicate(UseVIS >= 3); | |
| 8620 match(Set dst (ConvI2D src)); | |
| 8621 expand %{ | |
| 8622 regF tmp; | |
| 8623 MoveI2F_reg_reg(tmp, src); | |
| 8624 convI2D_helper(dst, tmp); | |
| 8625 %} | |
| 8626 %} | |
| 8627 | |
| 8628 instruct convI2D_mem(regD_low dst, memory mem) %{ | |
| 8629 match(Set dst (ConvI2D (LoadI mem))); | |
| 8630 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8631 size(8); | |
| 8632 format %{ "LDF $mem,$dst\n\t" | |
| 8633 "FITOD $dst,$dst" %} | |
| 8634 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
| 8635 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
| 8636 ins_pipe(floadF_mem); | |
| 8637 %} | |
| 8638 | |
| 8639 | |
| 8640 instruct convI2F_helper(regF dst, regF tmp) %{ | |
| 8641 effect(DEF dst, USE tmp); | |
| 8642 format %{ "FITOS $tmp,$dst" %} | |
| 8643 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
| 8644 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
| 8645 ins_pipe(fcvtI2F); | |
| 8646 %} | |
| 8647 | |
| 8648 instruct convI2F_stk(regF dst, stackSlotI src) %{ | |
| 8649 match(Set dst (ConvI2F src)); | |
| 8650 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8651 expand %{ | |
| 8652 regF tmp; | |
| 8653 stkI_to_regF(tmp,src); | |
| 8654 convI2F_helper(dst, tmp); | |
| 8655 %} | |
| 8656 %} | |
| 8657 | |
| 8658 instruct convI2F_reg(regF dst, iRegI src) %{ | |
| 8659 predicate(UseVIS >= 3); | |
| 8660 match(Set dst (ConvI2F src)); | |
| 8661 ins_cost(DEFAULT_COST); | |
| 8662 expand %{ | |
| 8663 regF tmp; | |
| 8664 MoveI2F_reg_reg(tmp, src); | |
| 8665 convI2F_helper(dst, tmp); | |
| 8666 %} | |
| 8667 %} | |
| 8668 | |
| 8669 instruct convI2F_mem( regF dst, memory mem ) %{ | |
| 8670 match(Set dst (ConvI2F (LoadI mem))); | |
| 8671 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8672 size(8); | |
| 8673 format %{ "LDF $mem,$dst\n\t" | |
| 8674 "FITOS $dst,$dst" %} | |
| 8675 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
| 8676 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
| 8677 ins_pipe(floadF_mem); | |
| 8678 %} | |
| 8679 | |
| 8680 | |
| 8681 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
| 8682 match(Set dst (ConvI2L src)); | |
| 8683 size(4); | |
| 8684 format %{ "SRA $src,0,$dst\t! int->long" %} | |
| 8685 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 8686 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8687 ins_pipe(ialu_reg_reg); | |
| 8688 %} | |
| 8689 | |
| 8690 // Zero-extend convert int to long | |
| 8691 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
| 8692 match(Set dst (AndL (ConvI2L src) mask) ); | |
| 8693 size(4); | |
| 8694 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
| 8695 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8696 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8697 ins_pipe(ialu_reg_reg); | |
| 8698 %} | |
| 8699 | |
| 8700 // Zero-extend long | |
| 8701 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
| 8702 match(Set dst (AndL src mask) ); | |
| 8703 size(4); | |
| 8704 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
| 8705 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8706 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8707 ins_pipe(ialu_reg_reg); | |
| 8708 %} | |
| 8709 | |
| 8710 | |
| 0 | 8711 //----------- |
| 8712 // Long to Double conversion using V8 opcodes. | |
| 8713 // Still useful because cheetah traps and becomes | |
| 8714 // amazingly slow for some common numbers. | |
| 8715 | |
| 8716 // Magic constant, 0x43300000 | |
| 8717 instruct loadConI_x43300000(iRegI dst) %{ | |
| 8718 effect(DEF dst); | |
| 8719 size(4); | |
| 8720 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
| 8721 ins_encode(SetHi22(0x43300000, dst)); | |
| 8722 ins_pipe(ialu_none); | |
| 8723 %} | |
| 8724 | |
| 8725 // Magic constant, 0x41f00000 | |
| 8726 instruct loadConI_x41f00000(iRegI dst) %{ | |
| 8727 effect(DEF dst); | |
| 8728 size(4); | |
| 8729 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
| 8730 ins_encode(SetHi22(0x41f00000, dst)); | |
| 8731 ins_pipe(ialu_none); | |
| 8732 %} | |
| 8733 | |
| 8734 // Construct a double from two float halves | |
| 8735 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
| 8736 effect(DEF dst, USE src1, USE src2); | |
| 8737 size(8); | |
| 8738 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
| 8739 "FMOVS $src2.lo,$dst.lo" %} | |
| 8740 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
| 8741 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
| 8742 ins_pipe(faddD_reg_reg); | |
| 8743 %} | |
| 8744 | |
| 8745 // Convert integer in high half of a double register (in the lower half of | |
| 8746 // the double register file) to double | |
| 8747 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
| 8748 effect(DEF dst, USE src); | |
| 8749 size(4); | |
| 8750 format %{ "FITOD $src,$dst" %} | |
| 8751 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8752 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
| 8753 ins_pipe(fcvtLHi2D); | |
| 8754 %} | |
| 8755 | |
| 8756 // Add float double precision | |
| 8757 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8758 effect(DEF dst, USE src1, USE src2); | |
| 8759 size(4); | |
| 8760 format %{ "FADDD $src1,$src2,$dst" %} | |
| 8761 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 8762 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8763 ins_pipe(faddD_reg_reg); | |
| 8764 %} | |
| 8765 | |
| 8766 // Sub float double precision | |
| 8767 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8768 effect(DEF dst, USE src1, USE src2); | |
| 8769 size(4); | |
| 8770 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 8771 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 8772 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8773 ins_pipe(faddD_reg_reg); | |
| 8774 %} | |
| 8775 | |
| 8776 // Mul float double precision | |
| 8777 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8778 effect(DEF dst, USE src1, USE src2); | |
| 8779 size(4); | |
| 8780 format %{ "FMULD $src1,$src2,$dst" %} | |
| 8781 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 8782 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8783 ins_pipe(fmulD_reg_reg); | |
| 8784 %} | |
| 8785 | |
| 8786 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
| 8787 match(Set dst (ConvL2D src)); | |
| 8788 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
| 8789 | |
| 8790 expand %{ | |
| 8791 regD_low tmpsrc; | |
| 8792 iRegI ix43300000; | |
| 8793 iRegI ix41f00000; | |
| 8794 stackSlotL lx43300000; | |
| 8795 stackSlotL lx41f00000; | |
| 8796 regD_low dx43300000; | |
| 8797 regD dx41f00000; | |
| 8798 regD tmp1; | |
| 8799 regD_low tmp2; | |
| 8800 regD tmp3; | |
| 8801 regD tmp4; | |
| 8802 | |
| 8803 stkL_to_regD(tmpsrc, src); | |
| 8804 | |
| 8805 loadConI_x43300000(ix43300000); | |
| 8806 loadConI_x41f00000(ix41f00000); | |
| 8807 regI_to_stkLHi(lx43300000, ix43300000); | |
| 8808 regI_to_stkLHi(lx41f00000, ix41f00000); | |
| 8809 stkL_to_regD(dx43300000, lx43300000); | |
| 8810 stkL_to_regD(dx41f00000, lx41f00000); | |
| 8811 | |
| 8812 convI2D_regDHi_regD(tmp1, tmpsrc); | |
| 8813 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
| 8814 subD_regD_regD(tmp3, tmp2, dx43300000); | |
| 8815 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
| 8816 addD_regD_regD(dst, tmp3, tmp4); | |
| 8817 %} | |
| 8818 %} | |
| 8819 | |
| 8820 // Long to Double conversion using fast fxtof | |
| 8821 instruct convL2D_helper(regD dst, regD tmp) %{ | |
| 8822 effect(DEF dst, USE tmp); | |
| 8823 size(4); | |
| 8824 format %{ "FXTOD $tmp,$dst" %} | |
| 8825 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
| 8826 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
| 8827 ins_pipe(fcvtL2D); | |
| 8828 %} | |
| 8829 | |
| 3804 | 8830 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ |
| 0 | 8831 predicate(VM_Version::has_fast_fxtof()); |
| 8832 match(Set dst (ConvL2D src)); | |
| 8833 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
| 8834 expand %{ | |
| 8835 regD tmp; | |
| 8836 stkL_to_regD(tmp, src); | |
| 8837 convL2D_helper(dst, tmp); | |
| 8838 %} | |
| 8839 %} | |
| 8840 | |
| 3804 | 8841 instruct convL2D_reg(regD dst, iRegL src) %{ |
| 8842 predicate(UseVIS >= 3); | |
| 8843 match(Set dst (ConvL2D src)); | |
| 8844 expand %{ | |
| 8845 regD tmp; | |
| 8846 MoveL2D_reg_reg(tmp, src); | |
| 8847 convL2D_helper(dst, tmp); | |
| 8848 %} | |
| 8849 %} | |
| 0 | 8850 |
| 8851 // Long to Float conversion using fast fxtof | |
| 8852 instruct convL2F_helper(regF dst, regD tmp) %{ | |
| 8853 effect(DEF dst, USE tmp); | |
| 8854 size(4); | |
| 8855 format %{ "FXTOS $tmp,$dst" %} | |
| 8856 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
| 8857 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
| 8858 ins_pipe(fcvtL2F); | |
| 8859 %} | |
| 8860 | |
| 3804 | 8861 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ |
| 0 | 8862 match(Set dst (ConvL2F src)); |
| 8863 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8864 expand %{ | |
| 8865 regD tmp; | |
| 8866 stkL_to_regD(tmp, src); | |
| 8867 convL2F_helper(dst, tmp); | |
| 8868 %} | |
| 8869 %} | |
| 3804 | 8870 |
| 8871 instruct convL2F_reg(regF dst, iRegL src) %{ | |
| 8872 predicate(UseVIS >= 3); | |
| 8873 match(Set dst (ConvL2F src)); | |
| 8874 ins_cost(DEFAULT_COST); | |
| 8875 expand %{ | |
| 8876 regD tmp; | |
| 8877 MoveL2D_reg_reg(tmp, src); | |
| 8878 convL2F_helper(dst, tmp); | |
| 8879 %} | |
| 8880 %} | |
| 8881 | |
| 0 | 8882 //----------- |
| 8883 | |
| 8884 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
| 8885 match(Set dst (ConvL2I src)); | |
| 8886 #ifndef _LP64 | |
| 8887 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
| 8888 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
| 8889 ins_pipe(ialu_move_reg_I_to_L); | |
| 8890 #else | |
| 8891 size(4); | |
| 8892 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
| 8893 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
| 8894 ins_pipe(ialu_reg); | |
| 8895 #endif | |
| 8896 %} | |
| 8897 | |
| 8898 // Register Shift Right Immediate | |
| 8899 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
| 8900 match(Set dst (ConvL2I (RShiftL src cnt))); | |
| 8901 | |
| 8902 size(4); | |
| 8903 format %{ "SRAX $src,$cnt,$dst" %} | |
| 8904 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 8905 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
| 8906 ins_pipe(ialu_reg_imm); | |
| 8907 %} | |
| 8908 | |
| 8909 //----------Control Flow Instructions------------------------------------------ | |
| 8910 // Compare Instructions | |
| 8911 // Compare Integers | |
| 8912 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
| 8913 match(Set icc (CmpI op1 op2)); | |
| 8914 effect( DEF icc, USE op1, USE op2 ); | |
| 8915 | |
| 8916 size(4); | |
| 8917 format %{ "CMP $op1,$op2" %} | |
| 8918 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8919 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8920 ins_pipe(ialu_cconly_reg_reg); | |
| 8921 %} | |
| 8922 | |
| 8923 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
| 8924 match(Set icc (CmpU op1 op2)); | |
| 8925 | |
| 8926 size(4); | |
| 8927 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 8928 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8929 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8930 ins_pipe(ialu_cconly_reg_reg); | |
| 8931 %} | |
| 8932 | |
| 8933 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
| 8934 match(Set icc (CmpI op1 op2)); | |
| 8935 effect( DEF icc, USE op1 ); | |
| 8936 | |
| 8937 size(4); | |
| 8938 format %{ "CMP $op1,$op2" %} | |
| 8939 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8940 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8941 ins_pipe(ialu_cconly_reg_imm); | |
| 8942 %} | |
| 8943 | |
| 8944 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
| 8945 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8946 | |
| 8947 size(4); | |
| 8948 format %{ "BTST $op2,$op1" %} | |
| 8949 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8950 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8951 ins_pipe(ialu_cconly_reg_reg_zero); | |
| 8952 %} | |
| 8953 | |
| 8954 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
| 8955 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8956 | |
| 8957 size(4); | |
| 8958 format %{ "BTST $op2,$op1" %} | |
| 8959 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8960 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8961 ins_pipe(ialu_cconly_reg_imm_zero); | |
| 8962 %} | |
| 8963 | |
| 8964 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
| 8965 match(Set xcc (CmpL op1 op2)); | |
| 8966 effect( DEF xcc, USE op1, USE op2 ); | |
| 8967 | |
| 8968 size(4); | |
| 8969 format %{ "CMP $op1,$op2\t\t! long" %} | |
| 8970 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8971 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8972 ins_pipe(ialu_cconly_reg_reg); | |
| 8973 %} | |
| 8974 | |
| 8975 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
| 8976 match(Set xcc (CmpL op1 con)); | |
| 8977 effect( DEF xcc, USE op1, USE con ); | |
| 8978 | |
| 8979 size(4); | |
| 8980 format %{ "CMP $op1,$con\t\t! long" %} | |
| 8981 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8982 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 8983 ins_pipe(ialu_cconly_reg_reg); | |
| 8984 %} | |
| 8985 | |
| 8986 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
| 8987 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
| 8988 effect( DEF xcc, USE op1, USE op2 ); | |
| 8989 | |
| 8990 size(4); | |
| 8991 format %{ "BTST $op1,$op2\t\t! long" %} | |
| 8992 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8993 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8994 ins_pipe(ialu_cconly_reg_reg); | |
| 8995 %} | |
| 8996 | |
| 8997 // useful for checking the alignment of a pointer: | |
| 8998 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
| 8999 match(Set xcc (CmpL (AndL op1 con) zero)); | |
| 9000 effect( DEF xcc, USE op1, USE con ); | |
| 9001 | |
| 9002 size(4); | |
| 9003 format %{ "BTST $op1,$con\t\t! long" %} | |
| 9004 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 9005 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 9006 ins_pipe(ialu_cconly_reg_reg); | |
| 9007 %} | |
| 9008 | |
|
17506
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9009 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{ |
| 0 | 9010 match(Set icc (CmpU op1 op2)); |
| 9011 | |
| 9012 size(4); | |
| 9013 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 9014 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 9015 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 9016 ins_pipe(ialu_cconly_reg_imm); | |
| 9017 %} | |
| 9018 | |
| 9019 // Compare Pointers | |
| 9020 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
| 9021 match(Set pcc (CmpP op1 op2)); | |
| 9022 | |
| 9023 size(4); | |
| 9024 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 9025 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 9026 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 9027 ins_pipe(ialu_cconly_reg_reg); | |
| 9028 %} | |
| 9029 | |
| 9030 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
| 9031 match(Set pcc (CmpP op1 op2)); | |
| 9032 | |
| 9033 size(4); | |
| 9034 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 9035 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 9036 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 9037 ins_pipe(ialu_cconly_reg_imm); | |
| 9038 %} | |
| 9039 | |
|
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163
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|
9040 // Compare Narrow oops |
|
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diff
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|
9041 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
|
c436414a719e
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diff
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|
9042 match(Set icc (CmpN op1 op2)); |
|
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|
9043 |
|
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|
9044 size(4); |
|
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|
9045 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
|
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9046 opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
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9047 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
|
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9048 ins_pipe(ialu_cconly_reg_reg); |
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9049 %} |
|
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|
9050 |
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9051 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
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9052 match(Set icc (CmpN op1 op2)); |
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9053 |
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9054 size(4); |
|
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9055 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
|
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9056 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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9057 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
|
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9058 ins_pipe(ialu_cconly_reg_imm); |
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9059 %} |
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9060 |
| 0 | 9061 //----------Max and Min-------------------------------------------------------- |
| 9062 // Min Instructions | |
| 9063 // Conditional move for min | |
| 9064 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 9065 effect( USE_DEF op2, USE op1, USE icc ); | |
| 9066 | |
| 9067 size(4); | |
| 9068 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
| 9069 opcode(Assembler::less); | |
| 9070 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 9071 ins_pipe(ialu_reg_flags); | |
| 9072 %} | |
| 9073 | |
| 9074 // Min Register with Register. | |
| 9075 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
| 9076 match(Set op2 (MinI op1 op2)); | |
| 9077 ins_cost(DEFAULT_COST*2); | |
| 9078 expand %{ | |
| 9079 flagsReg icc; | |
| 9080 compI_iReg(icc,op1,op2); | |
| 9081 cmovI_reg_lt(op2,op1,icc); | |
| 9082 %} | |
| 9083 %} | |
| 9084 | |
| 9085 // Max Instructions | |
| 9086 // Conditional move for max | |
| 9087 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 9088 effect( USE_DEF op2, USE op1, USE icc ); | |
| 9089 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
| 9090 opcode(Assembler::greater); | |
| 9091 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 9092 ins_pipe(ialu_reg_flags); | |
| 9093 %} | |
| 9094 | |
| 9095 // Max Register with Register | |
| 9096 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
| 9097 match(Set op2 (MaxI op1 op2)); | |
| 9098 ins_cost(DEFAULT_COST*2); | |
| 9099 expand %{ | |
| 9100 flagsReg icc; | |
| 9101 compI_iReg(icc,op1,op2); | |
| 9102 cmovI_reg_gt(op2,op1,icc); | |
| 9103 %} | |
| 9104 %} | |
| 9105 | |
| 9106 | |
| 9107 //----------Float Compares---------------------------------------------------- | |
| 9108 // Compare floating, generate condition code | |
| 9109 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
| 9110 match(Set fcc (CmpF src1 src2)); | |
| 9111 | |
| 9112 size(4); | |
| 9113 format %{ "FCMPs $fcc,$src1,$src2" %} | |
| 9114 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
| 9115 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
| 9116 ins_pipe(faddF_fcc_reg_reg_zero); | |
| 9117 %} | |
| 9118 | |
| 9119 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
| 9120 match(Set fcc (CmpD src1 src2)); | |
| 9121 | |
| 9122 size(4); | |
| 9123 format %{ "FCMPd $fcc,$src1,$src2" %} | |
| 9124 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
| 9125 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
| 9126 ins_pipe(faddD_fcc_reg_reg_zero); | |
| 9127 %} | |
| 9128 | |
| 9129 | |
| 9130 // Compare floating, generate -1,0,1 | |
| 9131 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
| 9132 match(Set dst (CmpF3 src1 src2)); | |
| 9133 effect(KILL fcc0); | |
| 9134 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 9135 format %{ "fcmpl $dst,$src1,$src2" %} | |
| 9136 // Primary = float | |
| 9137 opcode( true ); | |
| 9138 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 9139 ins_pipe( floating_cmp ); | |
| 9140 %} | |
| 9141 | |
| 9142 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
| 9143 match(Set dst (CmpD3 src1 src2)); | |
| 9144 effect(KILL fcc0); | |
| 9145 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 9146 format %{ "dcmpl $dst,$src1,$src2" %} | |
| 9147 // Primary = double (not float) | |
| 9148 opcode( false ); | |
| 9149 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 9150 ins_pipe( floating_cmp ); | |
| 9151 %} | |
| 9152 | |
| 9153 //----------Branches--------------------------------------------------------- | |
| 9154 // Jump | |
| 9155 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
| 9156 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
| 9157 match(Jump switch_val); | |
|
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9158 effect(TEMP table); |
| 0 | 9159 |
| 9160 ins_cost(350); | |
| 9161 | |
| 2008 | 9162 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" |
| 9163 "LD [O7 + $switch_val], O7\n\t" | |
|
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|
9164 "JUMP O7" %} |
| 2008 | 9165 ins_encode %{ |
| 9166 // Calculate table address into a register. | |
| 9167 Register table_reg; | |
| 9168 Register label_reg = O7; | |
|
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9169 // If we are calculating the size of this instruction don't trust |
|
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|
9170 // zero offsets because they might change when |
|
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9171 // MachConstantBaseNode decides to optimize the constant table |
|
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9172 // base. |
|
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9173 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) { |
| 2008 | 9174 table_reg = $constanttablebase; |
| 9175 } else { | |
| 9176 table_reg = O7; | |
|
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5fe0781a8560
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|
9177 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); |
|
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|
9178 __ add($constanttablebase, con_offset, table_reg); |
| 2008 | 9179 } |
| 9180 | |
| 9181 // Jump to base address + switch value | |
| 9182 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); | |
| 9183 __ jmp(label_reg, G0); | |
| 9184 __ delayed()->nop(); | |
| 9185 %} | |
| 0 | 9186 ins_pipe(ialu_reg_reg); |
| 9187 %} | |
| 9188 | |
| 9189 // Direct Branch. Use V8 version with longer range. | |
| 9190 instruct branch(label labl) %{ | |
| 9191 match(Goto); | |
| 9192 effect(USE labl); | |
| 9193 | |
| 9194 size(8); | |
| 9195 ins_cost(BRANCH_COST); | |
| 9196 format %{ "BA $labl" %} | |
| 3839 | 9197 ins_encode %{ |
| 9198 Label* L = $labl$$label; | |
| 9199 __ ba(*L); | |
| 9200 __ delayed()->nop(); | |
| 9201 %} | |
| 0 | 9202 ins_pipe(br); |
| 9203 %} | |
| 9204 | |
| 3851 | 9205 // Direct Branch, short with no delay slot |
| 9206 instruct branch_short(label labl) %{ | |
| 9207 match(Goto); | |
| 9208 predicate(UseCBCond); | |
| 9209 effect(USE labl); | |
| 9210 | |
| 9211 size(4); | |
| 9212 ins_cost(BRANCH_COST); | |
| 9213 format %{ "BA $labl\t! short branch" %} | |
|
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9214 ins_encode %{ |
| 3851 | 9215 Label* L = $labl$$label; |
| 9216 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9217 __ ba_short(*L); | |
| 9218 %} | |
| 9219 ins_short_branch(1); | |
| 9220 ins_avoid_back_to_back(1); | |
| 9221 ins_pipe(cbcond_reg_imm); | |
| 9222 %} | |
| 9223 | |
| 0 | 9224 // Conditional Direct Branch |
| 9225 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 9226 match(If cmp icc); | |
| 9227 effect(USE labl); | |
| 9228 | |
| 9229 size(8); | |
| 9230 ins_cost(BRANCH_COST); | |
| 9231 format %{ "BP$cmp $icc,$labl" %} | |
| 9232 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9233 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9234 ins_pipe(br_cc); | |
| 9235 %} | |
| 9236 | |
| 9237 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9238 match(If cmp icc); | |
| 9239 effect(USE labl); | |
| 9240 | |
| 3851 | 9241 ins_cost(BRANCH_COST); |
| 0 | 9242 format %{ "BP$cmp $icc,$labl" %} |
| 9243 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9244 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9245 ins_pipe(br_cc); | |
| 9246 %} | |
| 9247 | |
| 9248 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
| 9249 match(If cmp pcc); | |
| 9250 effect(USE labl); | |
| 9251 | |
| 9252 size(8); | |
| 9253 ins_cost(BRANCH_COST); | |
| 9254 format %{ "BP$cmp $pcc,$labl" %} | |
| 3839 | 9255 ins_encode %{ |
| 9256 Label* L = $labl$$label; | |
| 9257 Assembler::Predict predict_taken = | |
| 9258 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9259 | |
| 9260 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
| 9261 __ delayed()->nop(); | |
| 9262 %} | |
| 0 | 9263 ins_pipe(br_cc); |
| 9264 %} | |
| 9265 | |
| 9266 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
| 9267 match(If cmp fcc); | |
| 9268 effect(USE labl); | |
| 9269 | |
| 9270 size(8); | |
| 9271 ins_cost(BRANCH_COST); | |
| 9272 format %{ "FBP$cmp $fcc,$labl" %} | |
| 3839 | 9273 ins_encode %{ |
| 9274 Label* L = $labl$$label; | |
| 9275 Assembler::Predict predict_taken = | |
| 9276 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9277 | |
| 9278 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); | |
| 9279 __ delayed()->nop(); | |
| 9280 %} | |
| 0 | 9281 ins_pipe(br_fcc); |
| 9282 %} | |
| 9283 | |
| 9284 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 9285 match(CountedLoopEnd cmp icc); | |
| 9286 effect(USE labl); | |
| 9287 | |
| 9288 size(8); | |
| 9289 ins_cost(BRANCH_COST); | |
| 9290 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9291 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9292 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9293 ins_pipe(br_cc); | |
| 9294 %} | |
| 9295 | |
| 9296 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9297 match(CountedLoopEnd cmp icc); | |
| 9298 effect(USE labl); | |
| 9299 | |
| 9300 size(8); | |
| 9301 ins_cost(BRANCH_COST); | |
| 9302 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9303 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9304 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9305 ins_pipe(br_cc); | |
| 9306 %} | |
| 9307 | |
| 3851 | 9308 // Compare and branch instructions |
| 9309 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
| 9310 match(If cmp (CmpI op1 op2)); | |
| 9311 effect(USE labl, KILL icc); | |
| 9312 | |
| 9313 size(12); | |
| 9314 ins_cost(BRANCH_COST); | |
| 9315 format %{ "CMP $op1,$op2\t! int\n\t" | |
| 9316 "BP$cmp $labl" %} | |
| 9317 ins_encode %{ | |
| 9318 Label* L = $labl$$label; | |
| 9319 Assembler::Predict predict_taken = | |
| 9320 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9321 __ cmp($op1$$Register, $op2$$Register); | |
| 9322 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9323 __ delayed()->nop(); | |
| 9324 %} | |
| 9325 ins_pipe(cmp_br_reg_reg); | |
| 9326 %} | |
| 9327 | |
| 9328 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
| 9329 match(If cmp (CmpI op1 op2)); | |
| 9330 effect(USE labl, KILL icc); | |
| 9331 | |
| 9332 size(12); | |
| 9333 ins_cost(BRANCH_COST); | |
| 9334 format %{ "CMP $op1,$op2\t! int\n\t" | |
| 9335 "BP$cmp $labl" %} | |
| 9336 ins_encode %{ | |
| 9337 Label* L = $labl$$label; | |
| 9338 Assembler::Predict predict_taken = | |
| 9339 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9340 __ cmp($op1$$Register, $op2$$constant); | |
| 9341 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9342 __ delayed()->nop(); | |
| 9343 %} | |
| 9344 ins_pipe(cmp_br_reg_imm); | |
| 9345 %} | |
| 9346 | |
| 9347 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
| 9348 match(If cmp (CmpU op1 op2)); | |
| 9349 effect(USE labl, KILL icc); | |
| 9350 | |
| 9351 size(12); | |
| 9352 ins_cost(BRANCH_COST); | |
| 9353 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
| 9354 "BP$cmp $labl" %} | |
| 9355 ins_encode %{ | |
| 9356 Label* L = $labl$$label; | |
| 9357 Assembler::Predict predict_taken = | |
| 9358 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9359 __ cmp($op1$$Register, $op2$$Register); | |
| 9360 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9361 __ delayed()->nop(); | |
| 9362 %} | |
| 9363 ins_pipe(cmp_br_reg_reg); | |
| 9364 %} | |
| 9365 | |
| 9366 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
| 9367 match(If cmp (CmpU op1 op2)); | |
| 9368 effect(USE labl, KILL icc); | |
| 9369 | |
| 9370 size(12); | |
| 9371 ins_cost(BRANCH_COST); | |
| 9372 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
| 9373 "BP$cmp $labl" %} | |
| 9374 ins_encode %{ | |
| 9375 Label* L = $labl$$label; | |
| 9376 Assembler::Predict predict_taken = | |
| 9377 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9378 __ cmp($op1$$Register, $op2$$constant); | |
| 9379 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9380 __ delayed()->nop(); | |
| 9381 %} | |
| 9382 ins_pipe(cmp_br_reg_imm); | |
| 9383 %} | |
| 9384 | |
| 9385 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
| 9386 match(If cmp (CmpL op1 op2)); | |
| 9387 effect(USE labl, KILL xcc); | |
| 9388 | |
| 9389 size(12); | |
| 9390 ins_cost(BRANCH_COST); | |
| 9391 format %{ "CMP $op1,$op2\t! long\n\t" | |
| 9392 "BP$cmp $labl" %} | |
| 9393 ins_encode %{ | |
| 9394 Label* L = $labl$$label; | |
| 9395 Assembler::Predict predict_taken = | |
| 9396 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9397 __ cmp($op1$$Register, $op2$$Register); | |
| 9398 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
| 9399 __ delayed()->nop(); | |
| 9400 %} | |
| 9401 ins_pipe(cmp_br_reg_reg); | |
| 9402 %} | |
| 9403 | |
| 9404 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
| 9405 match(If cmp (CmpL op1 op2)); | |
| 9406 effect(USE labl, KILL xcc); | |
| 9407 | |
| 9408 size(12); | |
| 9409 ins_cost(BRANCH_COST); | |
| 9410 format %{ "CMP $op1,$op2\t! long\n\t" | |
| 9411 "BP$cmp $labl" %} | |
| 9412 ins_encode %{ | |
| 9413 Label* L = $labl$$label; | |
| 9414 Assembler::Predict predict_taken = | |
| 9415 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9416 __ cmp($op1$$Register, $op2$$constant); | |
| 9417 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
| 9418 __ delayed()->nop(); | |
| 9419 %} | |
| 9420 ins_pipe(cmp_br_reg_imm); | |
| 9421 %} | |
| 9422 | |
| 9423 // Compare Pointers and branch | |
| 9424 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
| 9425 match(If cmp (CmpP op1 op2)); | |
| 9426 effect(USE labl, KILL pcc); | |
| 9427 | |
| 9428 size(12); | |
| 9429 ins_cost(BRANCH_COST); | |
| 9430 format %{ "CMP $op1,$op2\t! ptr\n\t" | |
| 9431 "B$cmp $labl" %} | |
| 9432 ins_encode %{ | |
| 9433 Label* L = $labl$$label; | |
| 9434 Assembler::Predict predict_taken = | |
| 9435 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9436 __ cmp($op1$$Register, $op2$$Register); | |
| 9437 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
| 9438 __ delayed()->nop(); | |
| 9439 %} | |
| 9440 ins_pipe(cmp_br_reg_reg); | |
| 9441 %} | |
| 9442 | |
| 9443 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
| 9444 match(If cmp (CmpP op1 null)); | |
| 9445 effect(USE labl, KILL pcc); | |
| 9446 | |
| 9447 size(12); | |
| 9448 ins_cost(BRANCH_COST); | |
| 9449 format %{ "CMP $op1,0\t! ptr\n\t" | |
| 9450 "B$cmp $labl" %} | |
| 9451 ins_encode %{ | |
| 9452 Label* L = $labl$$label; | |
| 9453 Assembler::Predict predict_taken = | |
| 9454 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9455 __ cmp($op1$$Register, G0); | |
| 9456 // bpr() is not used here since it has shorter distance. | |
| 9457 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
| 9458 __ delayed()->nop(); | |
| 9459 %} | |
| 9460 ins_pipe(cmp_br_reg_reg); | |
| 9461 %} | |
| 9462 | |
| 9463 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
| 9464 match(If cmp (CmpN op1 op2)); | |
| 9465 effect(USE labl, KILL icc); | |
| 9466 | |
| 9467 size(12); | |
| 9468 ins_cost(BRANCH_COST); | |
| 9469 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" | |
| 9470 "BP$cmp $labl" %} | |
| 9471 ins_encode %{ | |
| 9472 Label* L = $labl$$label; | |
| 9473 Assembler::Predict predict_taken = | |
| 9474 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9475 __ cmp($op1$$Register, $op2$$Register); | |
| 9476 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9477 __ delayed()->nop(); | |
| 9478 %} | |
| 9479 ins_pipe(cmp_br_reg_reg); | |
| 9480 %} | |
| 9481 | |
| 9482 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
| 9483 match(If cmp (CmpN op1 null)); | |
| 9484 effect(USE labl, KILL icc); | |
| 9485 | |
| 9486 size(12); | |
| 9487 ins_cost(BRANCH_COST); | |
| 9488 format %{ "CMP $op1,0\t! compressed ptr\n\t" | |
| 9489 "BP$cmp $labl" %} | |
| 9490 ins_encode %{ | |
| 9491 Label* L = $labl$$label; | |
| 9492 Assembler::Predict predict_taken = | |
| 9493 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9494 __ cmp($op1$$Register, G0); | |
| 9495 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9496 __ delayed()->nop(); | |
| 9497 %} | |
| 9498 ins_pipe(cmp_br_reg_reg); | |
| 9499 %} | |
| 9500 | |
| 9501 // Loop back branch | |
| 9502 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
| 9503 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
| 9504 effect(USE labl, KILL icc); | |
| 9505 | |
| 9506 size(12); | |
| 9507 ins_cost(BRANCH_COST); | |
| 9508 format %{ "CMP $op1,$op2\t! int\n\t" | |
| 9509 "BP$cmp $labl\t! Loop end" %} | |
| 9510 ins_encode %{ | |
| 9511 Label* L = $labl$$label; | |
| 9512 Assembler::Predict predict_taken = | |
| 9513 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9514 __ cmp($op1$$Register, $op2$$Register); | |
| 9515 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9516 __ delayed()->nop(); | |
| 9517 %} | |
| 9518 ins_pipe(cmp_br_reg_reg); | |
| 9519 %} | |
| 9520 | |
| 9521 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
| 9522 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
| 9523 effect(USE labl, KILL icc); | |
| 9524 | |
| 9525 size(12); | |
| 9526 ins_cost(BRANCH_COST); | |
| 9527 format %{ "CMP $op1,$op2\t! int\n\t" | |
| 9528 "BP$cmp $labl\t! Loop end" %} | |
| 9529 ins_encode %{ | |
| 9530 Label* L = $labl$$label; | |
| 9531 Assembler::Predict predict_taken = | |
| 9532 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9533 __ cmp($op1$$Register, $op2$$constant); | |
| 9534 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9535 __ delayed()->nop(); | |
| 9536 %} | |
| 9537 ins_pipe(cmp_br_reg_imm); | |
| 9538 %} | |
| 9539 | |
| 9540 // Short compare and branch instructions | |
| 9541 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
| 9542 match(If cmp (CmpI op1 op2)); | |
| 9543 predicate(UseCBCond); | |
| 9544 effect(USE labl, KILL icc); | |
| 9545 | |
| 9546 size(4); | |
| 9547 ins_cost(BRANCH_COST); | |
| 9548 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
| 9549 ins_encode %{ | |
| 9550 Label* L = $labl$$label; | |
| 9551 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9552 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
| 9553 %} | |
| 9554 ins_short_branch(1); | |
| 9555 ins_avoid_back_to_back(1); | |
| 9556 ins_pipe(cbcond_reg_reg); | |
| 9557 %} | |
| 9558 | |
| 9559 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
| 9560 match(If cmp (CmpI op1 op2)); | |
| 9561 predicate(UseCBCond); | |
| 9562 effect(USE labl, KILL icc); | |
| 9563 | |
| 9564 size(4); | |
| 9565 ins_cost(BRANCH_COST); | |
| 9566 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
| 9567 ins_encode %{ | |
| 9568 Label* L = $labl$$label; | |
| 9569 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9570 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
| 9571 %} | |
| 9572 ins_short_branch(1); | |
| 9573 ins_avoid_back_to_back(1); | |
| 9574 ins_pipe(cbcond_reg_imm); | |
| 9575 %} | |
| 9576 | |
| 9577 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
| 9578 match(If cmp (CmpU op1 op2)); | |
| 9579 predicate(UseCBCond); | |
| 9580 effect(USE labl, KILL icc); | |
| 9581 | |
| 9582 size(4); | |
| 9583 ins_cost(BRANCH_COST); | |
| 9584 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
| 9585 ins_encode %{ | |
| 9586 Label* L = $labl$$label; | |
| 9587 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9588 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
| 9589 %} | |
| 9590 ins_short_branch(1); | |
| 9591 ins_avoid_back_to_back(1); | |
| 9592 ins_pipe(cbcond_reg_reg); | |
| 9593 %} | |
| 9594 | |
| 9595 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
| 9596 match(If cmp (CmpU op1 op2)); | |
| 9597 predicate(UseCBCond); | |
| 9598 effect(USE labl, KILL icc); | |
| 9599 | |
| 9600 size(4); | |
| 9601 ins_cost(BRANCH_COST); | |
| 9602 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
| 9603 ins_encode %{ | |
| 9604 Label* L = $labl$$label; | |
| 9605 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9606 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
| 9607 %} | |
| 9608 ins_short_branch(1); | |
| 9609 ins_avoid_back_to_back(1); | |
| 9610 ins_pipe(cbcond_reg_imm); | |
| 9611 %} | |
| 9612 | |
| 9613 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
| 9614 match(If cmp (CmpL op1 op2)); | |
| 9615 predicate(UseCBCond); | |
| 9616 effect(USE labl, KILL xcc); | |
| 9617 | |
| 9618 size(4); | |
| 9619 ins_cost(BRANCH_COST); | |
| 9620 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
| 9621 ins_encode %{ | |
| 9622 Label* L = $labl$$label; | |
| 9623 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9624 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); | |
| 9625 %} | |
| 9626 ins_short_branch(1); | |
| 9627 ins_avoid_back_to_back(1); | |
| 9628 ins_pipe(cbcond_reg_reg); | |
| 9629 %} | |
| 9630 | |
| 9631 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
| 9632 match(If cmp (CmpL op1 op2)); | |
| 9633 predicate(UseCBCond); | |
| 9634 effect(USE labl, KILL xcc); | |
| 9635 | |
| 9636 size(4); | |
| 9637 ins_cost(BRANCH_COST); | |
| 9638 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
| 9639 ins_encode %{ | |
| 9640 Label* L = $labl$$label; | |
| 9641 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9642 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); | |
| 9643 %} | |
| 9644 ins_short_branch(1); | |
| 9645 ins_avoid_back_to_back(1); | |
| 9646 ins_pipe(cbcond_reg_imm); | |
| 9647 %} | |
| 9648 | |
| 9649 // Compare Pointers and branch | |
| 9650 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
| 9651 match(If cmp (CmpP op1 op2)); | |
| 9652 predicate(UseCBCond); | |
| 9653 effect(USE labl, KILL pcc); | |
| 9654 | |
| 9655 size(4); | |
| 9656 ins_cost(BRANCH_COST); | |
| 9657 #ifdef _LP64 | |
| 9658 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} | |
| 9659 #else | |
| 9660 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %} | |
| 9661 #endif | |
| 9662 ins_encode %{ | |
| 9663 Label* L = $labl$$label; | |
| 9664 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9665 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); | |
| 9666 %} | |
| 9667 ins_short_branch(1); | |
| 9668 ins_avoid_back_to_back(1); | |
| 9669 ins_pipe(cbcond_reg_reg); | |
| 9670 %} | |
| 9671 | |
| 9672 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
| 9673 match(If cmp (CmpP op1 null)); | |
| 9674 predicate(UseCBCond); | |
| 9675 effect(USE labl, KILL pcc); | |
| 9676 | |
| 9677 size(4); | |
| 9678 ins_cost(BRANCH_COST); | |
| 9679 #ifdef _LP64 | |
| 9680 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} | |
| 9681 #else | |
| 9682 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %} | |
| 9683 #endif | |
| 9684 ins_encode %{ | |
| 9685 Label* L = $labl$$label; | |
| 9686 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9687 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); | |
| 9688 %} | |
| 9689 ins_short_branch(1); | |
| 9690 ins_avoid_back_to_back(1); | |
| 9691 ins_pipe(cbcond_reg_reg); | |
| 9692 %} | |
| 9693 | |
| 9694 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
| 9695 match(If cmp (CmpN op1 op2)); | |
| 9696 predicate(UseCBCond); | |
| 9697 effect(USE labl, KILL icc); | |
| 9698 | |
| 9699 size(4); | |
| 9700 ins_cost(BRANCH_COST); | |
| 9701 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %} | |
| 9702 ins_encode %{ | |
| 9703 Label* L = $labl$$label; | |
| 9704 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9705 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
| 9706 %} | |
| 9707 ins_short_branch(1); | |
| 9708 ins_avoid_back_to_back(1); | |
| 9709 ins_pipe(cbcond_reg_reg); | |
| 9710 %} | |
| 9711 | |
| 9712 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
| 9713 match(If cmp (CmpN op1 null)); | |
| 9714 predicate(UseCBCond); | |
| 9715 effect(USE labl, KILL icc); | |
| 9716 | |
| 9717 size(4); | |
| 9718 ins_cost(BRANCH_COST); | |
| 9719 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} | |
| 9720 ins_encode %{ | |
| 9721 Label* L = $labl$$label; | |
| 9722 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9723 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); | |
| 9724 %} | |
| 9725 ins_short_branch(1); | |
| 9726 ins_avoid_back_to_back(1); | |
| 9727 ins_pipe(cbcond_reg_reg); | |
| 9728 %} | |
| 9729 | |
| 9730 // Loop back branch | |
| 9731 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
| 9732 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
| 9733 predicate(UseCBCond); | |
| 9734 effect(USE labl, KILL icc); | |
| 9735 | |
| 9736 size(4); | |
| 9737 ins_cost(BRANCH_COST); | |
| 9738 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
| 9739 ins_encode %{ | |
| 9740 Label* L = $labl$$label; | |
| 9741 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9742 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
| 9743 %} | |
| 9744 ins_short_branch(1); | |
| 9745 ins_avoid_back_to_back(1); | |
| 9746 ins_pipe(cbcond_reg_reg); | |
| 9747 %} | |
| 9748 | |
| 9749 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
| 9750 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
| 9751 predicate(UseCBCond); | |
| 9752 effect(USE labl, KILL icc); | |
| 9753 | |
| 9754 size(4); | |
| 9755 ins_cost(BRANCH_COST); | |
| 9756 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
| 9757 ins_encode %{ | |
| 9758 Label* L = $labl$$label; | |
| 9759 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9760 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
| 9761 %} | |
| 9762 ins_short_branch(1); | |
| 9763 ins_avoid_back_to_back(1); | |
| 9764 ins_pipe(cbcond_reg_imm); | |
| 9765 %} | |
| 9766 | |
| 9767 // Branch-on-register tests all 64 bits. We assume that values | |
| 9768 // in 64-bit registers always remains zero or sign extended | |
| 9769 // unless our code munges the high bits. Interrupts can chop | |
| 9770 // the high order bits to zero or sign at any time. | |
| 9771 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
| 9772 match(If cmp (CmpI op1 zero)); | |
| 9773 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9774 effect(USE labl); | |
| 9775 | |
| 9776 size(8); | |
| 9777 ins_cost(BRANCH_COST); | |
| 9778 format %{ "BR$cmp $op1,$labl" %} | |
| 9779 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9780 ins_pipe(br_reg); | |
| 9781 %} | |
| 9782 | |
| 9783 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
| 9784 match(If cmp (CmpP op1 null)); | |
| 9785 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9786 effect(USE labl); | |
| 9787 | |
| 9788 size(8); | |
| 9789 ins_cost(BRANCH_COST); | |
| 9790 format %{ "BR$cmp $op1,$labl" %} | |
| 9791 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9792 ins_pipe(br_reg); | |
| 9793 %} | |
| 9794 | |
| 9795 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
| 9796 match(If cmp (CmpL op1 zero)); | |
| 9797 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9798 effect(USE labl); | |
| 9799 | |
| 9800 size(8); | |
| 9801 ins_cost(BRANCH_COST); | |
| 9802 format %{ "BR$cmp $op1,$labl" %} | |
| 9803 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9804 ins_pipe(br_reg); | |
| 9805 %} | |
| 9806 | |
| 9807 | |
| 0 | 9808 // ============================================================================ |
| 9809 // Long Compare | |
| 9810 // | |
| 9811 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 9812 // is tricky. The flavor of compare used depends on whether we are testing | |
| 9813 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 9814 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 9815 // the operands (yielding a GE test) and then negating; negate again for the | |
| 9816 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 9817 // NE test is negated from that. | |
| 9818 | |
| 9819 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 9820 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 9821 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 9822 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 9823 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 9824 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 9825 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 9826 // both forms beat the trinary form of long-compare and both are very useful | |
| 9827 // on Intel which has so few registers. | |
| 9828 | |
| 9829 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
| 9830 match(If cmp xcc); | |
| 9831 effect(USE labl); | |
| 9832 | |
| 9833 size(8); | |
| 9834 ins_cost(BRANCH_COST); | |
| 9835 format %{ "BP$cmp $xcc,$labl" %} | |
| 3839 | 9836 ins_encode %{ |
| 9837 Label* L = $labl$$label; | |
| 9838 Assembler::Predict predict_taken = | |
| 9839 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9840 | |
| 9841 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
| 9842 __ delayed()->nop(); | |
| 9843 %} | |
| 0 | 9844 ins_pipe(br_cc); |
| 9845 %} | |
| 9846 | |
| 9847 // Manifest a CmpL3 result in an integer register. Very painful. | |
| 9848 // This is the test to avoid. | |
| 9849 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
| 9850 match(Set dst (CmpL3 src1 src2) ); | |
| 9851 effect( KILL ccr ); | |
| 9852 ins_cost(6*DEFAULT_COST); | |
| 9853 size(24); | |
| 9854 format %{ "CMP $src1,$src2\t\t! long\n" | |
| 9855 "\tBLT,a,pn done\n" | |
| 9856 "\tMOV -1,$dst\t! delay slot\n" | |
| 9857 "\tBGT,a,pn done\n" | |
| 9858 "\tMOV 1,$dst\t! delay slot\n" | |
| 9859 "\tCLR $dst\n" | |
| 9860 "done:" %} | |
| 9861 ins_encode( cmpl_flag(src1,src2,dst) ); | |
| 9862 ins_pipe(cmpL_reg); | |
| 9863 %} | |
| 9864 | |
| 9865 // Conditional move | |
| 9866 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
| 9867 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9868 ins_cost(150); | |
| 9869 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9870 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9871 ins_pipe(ialu_reg); | |
| 9872 %} | |
| 9873 | |
| 9874 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
| 9875 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9876 ins_cost(140); | |
| 9877 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9878 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9879 ins_pipe(ialu_imm); | |
| 9880 %} | |
| 9881 | |
| 9882 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
| 9883 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9884 ins_cost(150); | |
| 9885 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9886 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9887 ins_pipe(ialu_reg); | |
| 9888 %} | |
| 9889 | |
| 9890 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
| 9891 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9892 ins_cost(140); | |
| 9893 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9894 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9895 ins_pipe(ialu_imm); | |
| 9896 %} | |
| 9897 | |
|
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9898 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
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9899 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
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9900 ins_cost(150); |
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9901 format %{ "MOV$cmp $xcc,$src,$dst" %} |
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9902 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
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9903 ins_pipe(ialu_reg); |
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9904 %} |
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9905 |
| 0 | 9906 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
| 9907 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 9908 ins_cost(150); | |
| 9909 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9910 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9911 ins_pipe(ialu_reg); | |
| 9912 %} | |
| 9913 | |
| 9914 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
| 9915 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 9916 ins_cost(140); | |
| 9917 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9918 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9919 ins_pipe(ialu_imm); | |
| 9920 %} | |
| 9921 | |
| 9922 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
| 9923 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
| 9924 ins_cost(150); | |
| 9925 opcode(0x101); | |
| 9926 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
| 9927 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9928 ins_pipe(int_conditional_float_move); | |
| 9929 %} | |
| 9930 | |
| 9931 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
| 9932 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
| 9933 ins_cost(150); | |
| 9934 opcode(0x102); | |
| 9935 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
| 9936 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9937 ins_pipe(int_conditional_float_move); | |
| 9938 %} | |
| 9939 | |
| 9940 // ============================================================================ | |
| 9941 // Safepoint Instruction | |
| 9942 instruct safePoint_poll(iRegP poll) %{ | |
| 9943 match(SafePoint poll); | |
| 9944 effect(USE poll); | |
| 9945 | |
| 9946 size(4); | |
| 9947 #ifdef _LP64 | |
| 9948 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 9949 #else | |
| 9950 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 9951 #endif | |
| 9952 ins_encode %{ | |
| 9953 __ relocate(relocInfo::poll_type); | |
| 9954 __ ld_ptr($poll$$Register, 0, G0); | |
| 9955 %} | |
| 9956 ins_pipe(loadPollP); | |
| 9957 %} | |
| 9958 | |
| 9959 // ============================================================================ | |
| 9960 // Call Instructions | |
| 9961 // Call Java Static Instruction | |
| 9962 instruct CallStaticJavaDirect( method meth ) %{ | |
| 9963 match(CallStaticJava); | |
| 1567 | 9964 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
| 0 | 9965 effect(USE meth); |
| 9966 | |
| 9967 size(8); | |
| 9968 ins_cost(CALL_COST); | |
| 9969 format %{ "CALL,static ; NOP ==> " %} | |
| 9970 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
| 9971 ins_pipe(simple_call); | |
| 9972 %} | |
| 9973 | |
| 1567 | 9974 // Call Java Static Instruction (method handle version) |
| 9975 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ | |
| 9976 match(CallStaticJava); | |
| 9977 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); | |
| 9978 effect(USE meth, KILL l7_mh_SP_save); | |
| 9979 | |
|
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9980 size(16); |
| 1567 | 9981 ins_cost(CALL_COST); |
| 9982 format %{ "CALL,static/MethodHandle" %} | |
| 9983 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); | |
| 9984 ins_pipe(simple_call); | |
| 9985 %} | |
| 9986 | |
| 0 | 9987 // Call Java Dynamic Instruction |
| 9988 instruct CallDynamicJavaDirect( method meth ) %{ | |
| 9989 match(CallDynamicJava); | |
| 9990 effect(USE meth); | |
| 9991 | |
| 9992 ins_cost(CALL_COST); | |
| 9993 format %{ "SET (empty),R_G5\n\t" | |
| 9994 "CALL,dynamic ; NOP ==> " %} | |
| 9995 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
| 9996 ins_pipe(call); | |
| 9997 %} | |
| 9998 | |
| 9999 // Call Runtime Instruction | |
| 10000 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
| 10001 match(CallRuntime); | |
| 10002 effect(USE meth, KILL l7); | |
| 10003 ins_cost(CALL_COST); | |
| 10004 format %{ "CALL,runtime" %} | |
| 10005 ins_encode( Java_To_Runtime( meth ), | |
| 10006 call_epilog, adjust_long_from_native_call ); | |
| 10007 ins_pipe(simple_call); | |
| 10008 %} | |
| 10009 | |
| 10010 // Call runtime without safepoint - same as CallRuntime | |
| 10011 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
| 10012 match(CallLeaf); | |
| 10013 effect(USE meth, KILL l7); | |
| 10014 ins_cost(CALL_COST); | |
| 10015 format %{ "CALL,runtime leaf" %} | |
| 10016 ins_encode( Java_To_Runtime( meth ), | |
| 10017 call_epilog, | |
| 10018 adjust_long_from_native_call ); | |
| 10019 ins_pipe(simple_call); | |
| 10020 %} | |
| 10021 | |
| 10022 // Call runtime without safepoint - same as CallLeaf | |
| 10023 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
| 10024 match(CallLeafNoFP); | |
| 10025 effect(USE meth, KILL l7); | |
| 10026 ins_cost(CALL_COST); | |
| 10027 format %{ "CALL,runtime leaf nofp" %} | |
| 10028 ins_encode( Java_To_Runtime( meth ), | |
| 10029 call_epilog, | |
| 10030 adjust_long_from_native_call ); | |
| 10031 ins_pipe(simple_call); | |
| 10032 %} | |
| 10033 | |
| 10034 // Tail Call; Jump from runtime stub to Java code. | |
| 10035 // Also known as an 'interprocedural jump'. | |
| 10036 // Target of jump will eventually return to caller. | |
| 10037 // TailJump below removes the return address. | |
| 10038 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
| 10039 match(TailCall jump_target method_oop ); | |
| 10040 | |
| 10041 ins_cost(CALL_COST); | |
| 10042 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
| 10043 ins_encode(form_jmpl(jump_target)); | |
| 10044 ins_pipe(tail_call); | |
| 10045 %} | |
| 10046 | |
| 10047 | |
| 10048 // Return Instruction | |
| 10049 instruct Ret() %{ | |
| 10050 match(Return); | |
| 10051 | |
| 10052 // The epilogue node did the ret already. | |
| 10053 size(0); | |
| 10054 format %{ "! return" %} | |
| 10055 ins_encode(); | |
| 10056 ins_pipe(empty); | |
| 10057 %} | |
| 10058 | |
| 10059 | |
| 10060 // Tail Jump; remove the return address; jump to target. | |
| 10061 // TailCall above leaves the return address around. | |
| 10062 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
| 10063 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
| 10064 // "restore" before this instruction (in Epilogue), we need to materialize it | |
| 10065 // in %i0. | |
| 10066 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
| 10067 match( TailJump jump_target ex_oop ); | |
| 10068 ins_cost(CALL_COST); | |
| 10069 format %{ "! discard R_O7\n\t" | |
| 10070 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
| 10071 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
| 10072 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
| 10073 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
| 10074 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
| 10075 ins_pipe(tail_call); | |
| 10076 %} | |
| 10077 | |
| 10078 // Create exception oop: created by stack-crawling runtime code. | |
| 10079 // Created exception is now available to this handler, and is setup | |
| 10080 // just prior to jumping to this handler. No code emitted. | |
| 10081 instruct CreateException( o0RegP ex_oop ) | |
| 10082 %{ | |
| 10083 match(Set ex_oop (CreateEx)); | |
| 10084 ins_cost(0); | |
| 10085 | |
| 10086 size(0); | |
| 10087 // use the following format syntax | |
| 10088 format %{ "! exception oop is in R_O0; no code emitted" %} | |
| 10089 ins_encode(); | |
| 10090 ins_pipe(empty); | |
| 10091 %} | |
| 10092 | |
| 10093 | |
| 10094 // Rethrow exception: | |
| 10095 // The exception oop will come in the first argument position. | |
| 10096 // Then JUMP (not call) to the rethrow stub code. | |
| 10097 instruct RethrowException() | |
| 10098 %{ | |
| 10099 match(Rethrow); | |
| 10100 ins_cost(CALL_COST); | |
| 10101 | |
| 10102 // use the following format syntax | |
| 10103 format %{ "Jmp rethrow_stub" %} | |
| 10104 ins_encode(enc_rethrow); | |
| 10105 ins_pipe(tail_call); | |
| 10106 %} | |
| 10107 | |
| 10108 | |
| 10109 // Die now | |
| 10110 instruct ShouldNotReachHere( ) | |
| 10111 %{ | |
| 10112 match(Halt); | |
| 10113 ins_cost(CALL_COST); | |
| 10114 | |
| 10115 size(4); | |
| 10116 // Use the following format syntax | |
| 10117 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
| 10118 ins_encode( form2_illtrap() ); | |
| 10119 ins_pipe(tail_call); | |
| 10120 %} | |
| 10121 | |
| 10122 // ============================================================================ | |
| 10123 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 10124 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 10125 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 10126 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 10127 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
| 10128 match(Set index (PartialSubtypeCheck sub super)); | |
| 10129 effect( KILL pcc, KILL o7 ); | |
| 10130 ins_cost(DEFAULT_COST*10); | |
| 10131 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
| 10132 ins_encode( enc_PartialSubtypeCheck() ); | |
| 10133 ins_pipe(partial_subtype_check_pipe); | |
| 10134 %} | |
| 10135 | |
| 10136 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
| 10137 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 10138 effect( KILL idx, KILL o7 ); | |
| 10139 ins_cost(DEFAULT_COST*10); | |
| 10140 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
| 10141 ins_encode( enc_PartialSubtypeCheck() ); | |
| 10142 ins_pipe(partial_subtype_check_pipe); | |
| 10143 %} | |
| 10144 | |
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10145 |
| 0 | 10146 // ============================================================================ |
| 10147 // inlined locking and unlocking | |
| 10148 | |
| 4777 | 10149 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ |
| 0 | 10150 match(Set pcc (FastLock object box)); |
| 10151 | |
| 4777 | 10152 effect(TEMP scratch2, USE_KILL box, KILL scratch); |
| 0 | 10153 ins_cost(100); |
| 10154 | |
| 4777 | 10155 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} |
| 0 | 10156 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); |
| 10157 ins_pipe(long_memory_op); | |
| 10158 %} | |
| 10159 | |
| 10160 | |
| 4777 | 10161 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ |
| 0 | 10162 match(Set pcc (FastUnlock object box)); |
| 4777 | 10163 effect(TEMP scratch2, USE_KILL box, KILL scratch); |
| 0 | 10164 ins_cost(100); |
| 10165 | |
| 4777 | 10166 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} |
| 0 | 10167 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); |
| 10168 ins_pipe(long_memory_op); | |
| 10169 %} | |
| 10170 | |
| 3892 | 10171 // The encodings are generic. |
| 0 | 10172 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ |
| 3892 | 10173 predicate(!use_block_zeroing(n->in(2)) ); |
| 0 | 10174 match(Set dummy (ClearArray cnt base)); |
| 10175 effect(TEMP temp, KILL ccr); | |
| 10176 ins_cost(300); | |
| 10177 format %{ "MOV $cnt,$temp\n" | |
| 10178 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
| 10179 " BRge loop\t\t! Clearing loop\n" | |
| 10180 " STX G0,[$base+$temp]\t! delay slot" %} | |
| 3892 | 10181 |
| 10182 ins_encode %{ | |
| 10183 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
| 10184 Register nof_bytes_arg = $cnt$$Register; | |
| 10185 Register nof_bytes_tmp = $temp$$Register; | |
| 10186 Register base_pointer_arg = $base$$Register; | |
| 10187 | |
| 10188 Label loop; | |
| 10189 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
| 10190 | |
| 10191 // Loop and clear, walking backwards through the array. | |
| 10192 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
| 10193 __ bind(loop); | |
| 10194 __ deccc(nof_bytes_tmp, 8); | |
| 10195 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
| 10196 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
| 10197 // %%%% this mini-loop must not cross a cache boundary! | |
| 10198 %} | |
| 10199 ins_pipe(long_memory_op); | |
| 10200 %} | |
| 10201 | |
| 10202 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{ | |
| 10203 predicate(use_block_zeroing(n->in(2))); | |
| 10204 match(Set dummy (ClearArray cnt base)); | |
| 10205 effect(USE_KILL cnt, USE_KILL base, KILL ccr); | |
| 10206 ins_cost(300); | |
| 10207 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} | |
| 10208 | |
| 10209 ins_encode %{ | |
| 10210 | |
| 10211 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); | |
| 10212 Register to = $base$$Register; | |
| 10213 Register count = $cnt$$Register; | |
| 10214 | |
| 10215 Label Ldone; | |
| 10216 __ nop(); // Separate short branches | |
| 10217 // Use BIS for zeroing (temp is not used). | |
| 10218 __ bis_zeroing(to, count, G0, Ldone); | |
| 10219 __ bind(Ldone); | |
| 10220 | |
| 10221 %} | |
| 10222 ins_pipe(long_memory_op); | |
| 10223 %} | |
| 10224 | |
| 10225 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{ | |
| 10226 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit)); | |
| 10227 match(Set dummy (ClearArray cnt base)); | |
| 10228 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr); | |
| 10229 ins_cost(300); | |
| 10230 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} | |
| 10231 | |
| 10232 ins_encode %{ | |
| 10233 | |
| 10234 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); | |
| 10235 Register to = $base$$Register; | |
| 10236 Register count = $cnt$$Register; | |
| 10237 Register temp = $tmp$$Register; | |
| 10238 | |
| 10239 Label Ldone; | |
| 10240 __ nop(); // Separate short branches | |
| 10241 // Use BIS for zeroing | |
| 10242 __ bis_zeroing(to, count, temp, Ldone); | |
| 10243 __ bind(Ldone); | |
| 10244 | |
| 10245 %} | |
| 0 | 10246 ins_pipe(long_memory_op); |
| 10247 %} | |
| 10248 | |
|
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10249 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
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10250 o7RegI tmp, flagsReg ccr) %{ |
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10251 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
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10252 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
| 0 | 10253 ins_cost(300); |
|
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10254 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
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10255 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
| 0 | 10256 ins_pipe(long_memory_op); |
| 10257 %} | |
| 10258 | |
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10259 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
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10260 o7RegI tmp, flagsReg ccr) %{ |
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10261 match(Set result (StrEquals (Binary str1 str2) cnt)); |
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10262 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
| 681 | 10263 ins_cost(300); |
|
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10264 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
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10265 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
| 681 | 10266 ins_pipe(long_memory_op); |
| 10267 %} | |
| 10268 | |
|
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10269 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
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62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10270 o7RegI tmp2, flagsReg ccr) %{ |
| 681 | 10271 match(Set result (AryEq ary1 ary2)); |
| 10272 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
| 10273 ins_cost(300); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10274 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10275 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
| 681 | 10276 ins_pipe(long_memory_op); |
| 10277 %} | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10278 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10279 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10280 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10281 |
|
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10282 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10283 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10284 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10285 effect(TEMP dst, TEMP tmp, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10286 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10287 // x |= (x >> 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10288 // x |= (x >> 2); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10289 // x |= (x >> 4); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10290 // x |= (x >> 8); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10291 // x |= (x >> 16); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10292 // return (WORDBITS - popc(x)); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10293 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10294 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10295 "OR $dst,$tmp,$dst\n\t" |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10296 "SRL $dst,2,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10297 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10298 "SRL $dst,4,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10299 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10300 "SRL $dst,8,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10301 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10302 "SRL $dst,16,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10303 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10304 "POPC $dst,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10305 "MOV 32,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10306 "SUB $tmp,$dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10307 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10308 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10309 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10310 Register Rtmp = $tmp$$Register; |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10311 __ srl(Rsrc, 1, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10312 __ srl(Rsrc, 0, Rdst); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10313 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10314 __ srl(Rdst, 2, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10315 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10316 __ srl(Rdst, 4, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10317 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10318 __ srl(Rdst, 8, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10319 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10320 __ srl(Rdst, 16, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10321 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10322 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10323 __ mov(BitsPerInt, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10324 __ sub(Rtmp, Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10325 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10326 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10327 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10328 |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10329 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10330 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10331 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10332 effect(TEMP dst, TEMP tmp, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10333 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10334 // x |= (x >> 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10335 // x |= (x >> 2); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10336 // x |= (x >> 4); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10337 // x |= (x >> 8); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10338 // x |= (x >> 16); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10339 // x |= (x >> 32); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10340 // return (WORDBITS - popc(x)); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10341 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10342 "OR $src,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10343 "SRLX $dst,2,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10344 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10345 "SRLX $dst,4,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10346 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10347 "SRLX $dst,8,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10348 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10349 "SRLX $dst,16,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10350 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10351 "SRLX $dst,32,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10352 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10353 "POPC $dst,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10354 "MOV 64,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10355 "SUB $tmp,$dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10356 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10357 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10358 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10359 Register Rtmp = $tmp$$Register; |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10360 __ srlx(Rsrc, 1, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10361 __ or3( Rsrc, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10362 __ srlx(Rdst, 2, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10363 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10364 __ srlx(Rdst, 4, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10365 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10366 __ srlx(Rdst, 8, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10367 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10368 __ srlx(Rdst, 16, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10369 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10370 __ srlx(Rdst, 32, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10371 __ or3( Rdst, Rtmp, Rdst); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10372 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10373 __ mov(BitsPerLong, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10374 __ sub(Rtmp, Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10375 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10376 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10377 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10378 |
|
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10379 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10380 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10381 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10382 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10383 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10384 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10385 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10386 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10387 "SRL $dst,R_G0,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10388 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10389 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10390 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10391 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10392 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10393 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10394 __ srl(Rdst, G0, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10395 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10396 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10397 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10398 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10399 |
|
4003
4bac06a82bc3
7100757: The BitSet.nextSetBit() produces incorrect result in 32bit VM on Sparc
kvn
parents:
3898
diff
changeset
|
10400 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10401 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10402 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10403 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10404 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10405 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10406 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10407 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10408 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10409 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10410 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10411 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10412 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10413 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10414 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10415 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10416 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10417 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10418 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10419 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10420 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10421 |
|
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10422 instruct popCountI(iRegIsafe dst, iRegI src) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10423 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10424 match(Set dst (PopCountI src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10425 |
|
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10426 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t" |
|
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10427 "POPC $dst, $dst" %} |
|
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10428 ins_encode %{ |
|
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10429 __ srl($src$$Register, G0, $dst$$Register); |
|
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10430 __ popc($dst$$Register, $dst$$Register); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10431 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10432 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10433 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10434 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10435 // Note: Long.bitCount(long) returns an int. |
|
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10436 instruct popCountL(iRegIsafe dst, iRegL src) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10437 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10438 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10439 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10440 format %{ "POPC $src, $dst" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10441 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10442 __ popc($src$$Register, $dst$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10443 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10444 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10445 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10446 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10447 |
| 0 | 10448 // ============================================================================ |
| 10449 //------------Bytes reverse-------------------------------------------------- | |
| 10450 | |
| 10451 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
| 10452 match(Set dst (ReverseBytesI src)); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10453 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10454 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10455 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10456 // onto a stack slot. |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10457 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10458 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10459 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10460 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10461 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10462 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10463 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10464 ins_pipe( iload_mem ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10465 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10466 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10467 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10468 match(Set dst (ReverseBytesL src)); |
| 0 | 10469 |
| 10470 // Op cost is artificially doubled to make sure that load or store | |
| 10471 // instructions are preferred over this one which requires a spill | |
| 10472 // onto a stack slot. | |
| 10473 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10474 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10475 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10476 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10477 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10478 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10479 %} |
| 0 | 10480 ins_pipe( iload_mem ); |
| 10481 %} | |
| 10482 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10483 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10484 match(Set dst (ReverseBytesUS src)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10485 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10486 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10487 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10488 // onto a stack slot. |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10489 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10490 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10491 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10492 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10493 // the value was spilled as an int so bias the load |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10494 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10495 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10496 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10497 ins_pipe( iload_mem ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10498 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10499 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10500 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10501 match(Set dst (ReverseBytesS src)); |
| 0 | 10502 |
| 10503 // Op cost is artificially doubled to make sure that load or store | |
| 10504 // instructions are preferred over this one which requires a spill | |
| 10505 // onto a stack slot. | |
| 10506 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10507 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10508 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10509 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10510 // the value was spilled as an int so bias the load |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10511 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10512 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10513 %} |
| 0 | 10514 ins_pipe( iload_mem ); |
| 10515 %} | |
| 10516 | |
| 10517 // Load Integer reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10518 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ |
| 0 | 10519 match(Set dst (ReverseBytesI (LoadI src))); |
| 10520 | |
| 10521 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10522 size(4); |
| 0 | 10523 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
| 10524 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10525 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10526 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10527 %} |
| 0 | 10528 ins_pipe(iload_mem); |
| 10529 %} | |
| 10530 | |
| 10531 // Load Long - aligned and reversed | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10532 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ |
| 0 | 10533 match(Set dst (ReverseBytesL (LoadL src))); |
| 10534 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10535 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10536 size(4); |
| 0 | 10537 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
| 10538 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10539 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10540 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10541 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10542 ins_pipe(iload_mem); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10543 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10544 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10545 // Load unsigned short / char reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10546 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10547 match(Set dst (ReverseBytesUS (LoadUS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10548 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10549 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10550 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10551 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10552 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10553 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10554 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10555 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10556 ins_pipe(iload_mem); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10557 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10558 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10559 // Load short reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10560 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10561 match(Set dst (ReverseBytesS (LoadS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10562 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10563 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10564 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10565 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10566 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10567 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10568 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10569 %} |
| 0 | 10570 ins_pipe(iload_mem); |
| 10571 %} | |
| 10572 | |
| 10573 // Store Integer reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10574 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ |
| 0 | 10575 match(Set dst (StoreI dst (ReverseBytesI src))); |
| 10576 | |
| 10577 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10578 size(4); |
| 0 | 10579 format %{ "STWA $src, $dst\t!asi=primary_little" %} |
| 10580 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10581 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10582 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10583 %} |
| 0 | 10584 ins_pipe(istore_mem_reg); |
| 10585 %} | |
| 10586 | |
| 10587 // Store Long reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10588 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ |
| 0 | 10589 match(Set dst (StoreL dst (ReverseBytesL src))); |
| 10590 | |
| 10591 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10592 size(4); |
| 0 | 10593 format %{ "STXA $src, $dst\t!asi=primary_little" %} |
| 10594 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10595 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10596 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10597 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10598 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10599 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10600 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10601 // Store unsighed short/char reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10602 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10603 match(Set dst (StoreC dst (ReverseBytesUS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10604 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10605 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10606 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10607 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10608 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10609 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10610 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10611 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10612 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10613 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10614 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10615 // Store short reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10616 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10617 match(Set dst (StoreC dst (ReverseBytesS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10618 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10619 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10620 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10621 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10622 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10623 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10624 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10625 %} |
| 0 | 10626 ins_pipe(istore_mem_reg); |
| 10627 %} | |
| 10628 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10629 // ====================VECTOR INSTRUCTIONS===================================== |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10630 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10631 // Load Aligned Packed values into a Double Register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10632 instruct loadV8(regD dst, memory mem) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10633 predicate(n->as_LoadVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10634 match(Set dst (LoadVector mem)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10635 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10636 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10637 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10638 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10639 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10640 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10641 ins_pipe(floadD_mem); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10642 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10643 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10644 // Store Vector in Double register to memory |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10645 instruct storeV8(memory mem, regD src) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10646 predicate(n->as_StoreVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10647 match(Set mem (StoreVector mem src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10648 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10649 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10650 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10651 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10652 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10653 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10654 ins_pipe(fstoreD_mem_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10655 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10656 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10657 // Store Zero into vector in memory |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10658 instruct storeV8B_zero(memory mem, immI0 zero) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10659 predicate(n->as_StoreVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10660 match(Set mem (StoreVector mem (ReplicateB zero))); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10661 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10662 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10663 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10664 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10665 __ stx(G0, $mem$$Address); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10666 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10667 ins_pipe(fstoreD_mem_zero); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10668 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10669 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10670 instruct storeV4S_zero(memory mem, immI0 zero) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10671 predicate(n->as_StoreVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10672 match(Set mem (StoreVector mem (ReplicateS zero))); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10673 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10674 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10675 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10676 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10677 __ stx(G0, $mem$$Address); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10678 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10679 ins_pipe(fstoreD_mem_zero); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10680 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10681 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10682 instruct storeV2I_zero(memory mem, immI0 zero) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10683 predicate(n->as_StoreVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10684 match(Set mem (StoreVector mem (ReplicateI zero))); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10685 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10686 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10687 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10688 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10689 __ stx(G0, $mem$$Address); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10690 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10691 ins_pipe(fstoreD_mem_zero); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10692 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10693 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10694 instruct storeV2F_zero(memory mem, immF0 zero) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10695 predicate(n->as_StoreVector()->memory_size() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10696 match(Set mem (StoreVector mem (ReplicateF zero))); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10697 ins_cost(MEMORY_REF_COST); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10698 size(4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10699 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10700 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10701 __ stx(G0, $mem$$Address); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10702 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10703 ins_pipe(fstoreD_mem_zero); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10704 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10705 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10706 // Replicate scalar to packed byte values into Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10707 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10708 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10709 match(Set dst (ReplicateB src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10710 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10711 format %{ "SLLX $src,56,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10712 "SRLX $tmp, 8,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10713 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10714 "SRLX $tmp,16,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10715 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10716 "SRLX $tmp,32,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10717 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10718 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10719 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10720 Register Rsrc = $src$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10721 Register Rtmp = $tmp$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10722 Register Rtmp2 = $tmp2$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10723 __ sllx(Rsrc, 56, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10724 __ srlx(Rtmp, 8, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10725 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10726 __ srlx(Rtmp, 16, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10727 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10728 __ srlx(Rtmp, 32, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10729 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10730 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10731 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10732 ins_pipe(ialu_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10733 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10734 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10735 // Replicate scalar to packed byte values into Double stack |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10736 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10737 predicate(n->as_Vector()->length() == 8 && UseVIS < 3); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10738 match(Set dst (ReplicateB src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10739 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10740 format %{ "SLLX $src,56,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10741 "SRLX $tmp, 8,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10742 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10743 "SRLX $tmp,16,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10744 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10745 "SRLX $tmp,32,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10746 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10747 "STX $tmp,$dst\t! regL to stkD" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10748 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10749 Register Rsrc = $src$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10750 Register Rtmp = $tmp$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10751 Register Rtmp2 = $tmp2$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10752 __ sllx(Rsrc, 56, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10753 __ srlx(Rtmp, 8, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10754 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10755 __ srlx(Rtmp, 16, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10756 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10757 __ srlx(Rtmp, 32, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10758 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10759 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10760 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10761 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10762 ins_pipe(ialu_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10763 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10764 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10765 // Replicate scalar constant to packed byte values in Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10766 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10767 predicate(n->as_Vector()->length() == 8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10768 match(Set dst (ReplicateB con)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10769 effect(KILL tmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10770 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10771 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10772 // XXX This is a quick fix for 6833573. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10773 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10774 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10775 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10776 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10777 ins_pipe(loadConFD); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10778 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10779 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10780 // Replicate scalar to packed char/short values into Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10781 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10782 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10783 match(Set dst (ReplicateS src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10784 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10785 format %{ "SLLX $src,48,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10786 "SRLX $tmp,16,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10787 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10788 "SRLX $tmp,32,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10789 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10790 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10791 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10792 Register Rsrc = $src$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10793 Register Rtmp = $tmp$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10794 Register Rtmp2 = $tmp2$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10795 __ sllx(Rsrc, 48, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10796 __ srlx(Rtmp, 16, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10797 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10798 __ srlx(Rtmp, 32, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10799 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10800 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10801 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10802 ins_pipe(ialu_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10803 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10804 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10805 // Replicate scalar to packed char/short values into Double stack |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10806 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10807 predicate(n->as_Vector()->length() == 4 && UseVIS < 3); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10808 match(Set dst (ReplicateS src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10809 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10810 format %{ "SLLX $src,48,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10811 "SRLX $tmp,16,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10812 "OR $tmp,$tmp2,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10813 "SRLX $tmp,32,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10814 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10815 "STX $tmp,$dst\t! regL to stkD" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10816 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10817 Register Rsrc = $src$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10818 Register Rtmp = $tmp$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10819 Register Rtmp2 = $tmp2$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10820 __ sllx(Rsrc, 48, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10821 __ srlx(Rtmp, 16, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10822 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10823 __ srlx(Rtmp, 32, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10824 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10825 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10826 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10827 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10828 ins_pipe(ialu_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10829 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10830 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10831 // Replicate scalar constant to packed char/short values in Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10832 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10833 predicate(n->as_Vector()->length() == 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10834 match(Set dst (ReplicateS con)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10835 effect(KILL tmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10836 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10837 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10838 // XXX This is a quick fix for 6833573. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10839 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10840 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10841 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10842 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10843 ins_pipe(loadConFD); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10844 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10845 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10846 // Replicate scalar to packed int values into Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10847 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10848 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10849 match(Set dst (ReplicateI src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10850 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10851 format %{ "SLLX $src,32,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10852 "SRLX $tmp,32,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10853 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10854 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10855 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10856 Register Rsrc = $src$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10857 Register Rtmp = $tmp$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10858 Register Rtmp2 = $tmp2$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10859 __ sllx(Rsrc, 32, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10860 __ srlx(Rtmp, 32, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10861 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10862 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10863 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10864 ins_pipe(ialu_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10865 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10866 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10867 // Replicate scalar to packed int values into Double stack |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10868 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10869 predicate(n->as_Vector()->length() == 2 && UseVIS < 3); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10870 match(Set dst (ReplicateI src)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10871 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10872 format %{ "SLLX $src,32,$tmp\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10873 "SRLX $tmp,32,$tmp2\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10874 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10875 "STX $tmp,$dst\t! regL to stkD" %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10876 ins_encode %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10877 Register Rsrc = $src$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10878 Register Rtmp = $tmp$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10879 Register Rtmp2 = $tmp2$$Register; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10880 __ sllx(Rsrc, 32, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10881 __ srlx(Rtmp, 32, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10882 __ or3 (Rtmp, Rtmp2, Rtmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10883 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10884 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10885 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10886 ins_pipe(ialu_reg); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10887 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10888 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10889 // Replicate scalar zero constant to packed int values in Double register |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10890 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10891 predicate(n->as_Vector()->length() == 2); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10892 match(Set dst (ReplicateI con)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10893 effect(KILL tmp); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10894 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} |
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10895 ins_encode %{ |
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10896 // XXX This is a quick fix for 6833573. |
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10897 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); |
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10898 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); |
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10899 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
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10900 %} |
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10901 ins_pipe(loadConFD); |
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10902 %} |
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10903 |
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10904 // Replicate scalar to packed float values into Double stack |
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10905 instruct Repl2F_stk(stackSlotD dst, regF src) %{ |
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10906 predicate(n->as_Vector()->length() == 2); |
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10907 match(Set dst (ReplicateF src)); |
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10908 ins_cost(MEMORY_REF_COST*2); |
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10909 format %{ "STF $src,$dst.hi\t! packed2F\n\t" |
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10910 "STF $src,$dst.lo" %} |
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10911 opcode(Assembler::stf_op3); |
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10912 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src)); |
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10913 ins_pipe(fstoreF_stk_reg); |
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10914 %} |
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10915 |
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10916 // Replicate scalar zero constant to packed float values in Double register |
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10917 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{ |
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10918 predicate(n->as_Vector()->length() == 2); |
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10919 match(Set dst (ReplicateF con)); |
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10920 effect(KILL tmp); |
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10921 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %} |
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10922 ins_encode %{ |
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10923 // XXX This is a quick fix for 6833573. |
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10924 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister); |
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10925 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register); |
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10926 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
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10927 %} |
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10928 ins_pipe(loadConFD); |
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10929 %} |
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10930 |
| 0 | 10931 //----------PEEPHOLE RULES----------------------------------------------------- |
| 10932 // These must follow all instruction definitions as they use the names | |
| 10933 // defined in the instructions definitions. | |
| 10934 // | |
| 605 | 10935 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 10936 // |
| 10937 // peepconstraint %{ | |
| 10938 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 10939 // [, ...] ); | |
| 10940 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 10941 // | |
| 10942 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 10943 // // provide an instruction_number.operand_name for each operand that appears | |
| 10944 // // in the replacement instruction's match rule | |
| 10945 // | |
| 10946 // ---------VM FLAGS--------------------------------------------------------- | |
| 10947 // | |
| 10948 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 10949 // | |
| 10950 // Each peephole rule is given an identifying number starting with zero and | |
| 10951 // increasing by one in the order seen by the parser. An individual peephole | |
| 10952 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 10953 // on the command-line. | |
| 10954 // | |
| 10955 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 10956 // | |
| 10957 // Only match adjacent instructions in same basic block | |
| 10958 // Only equality constraints | |
| 10959 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 10960 // Only one replacement instruction | |
| 10961 // | |
| 10962 // ---------EXAMPLE---------------------------------------------------------- | |
| 10963 // | |
| 10964 // // pertinent parts of existing instructions in architecture description | |
| 10965 // instruct movI(eRegI dst, eRegI src) %{ | |
| 10966 // match(Set dst (CopyI src)); | |
| 10967 // %} | |
| 10968 // | |
| 10969 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 10970 // match(Set dst (AddI dst src)); | |
| 10971 // effect(KILL cr); | |
| 10972 // %} | |
| 10973 // | |
| 10974 // // Change (inc mov) to lea | |
| 10975 // peephole %{ | |
| 10976 // // increment preceeded by register-register move | |
| 10977 // peepmatch ( incI_eReg movI ); | |
| 10978 // // require that the destination register of the increment | |
| 10979 // // match the destination register of the move | |
| 10980 // peepconstraint ( 0.dst == 1.dst ); | |
| 10981 // // construct a replacement instruction that sets | |
| 10982 // // the destination to ( move's source register + one ) | |
| 10983 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
| 10984 // %} | |
| 10985 // | |
| 10986 | |
| 10987 // // Change load of spilled value to only a spill | |
| 10988 // instruct storeI(memory mem, eRegI src) %{ | |
| 10989 // match(Set mem (StoreI mem src)); | |
| 10990 // %} | |
| 10991 // | |
| 10992 // instruct loadI(eRegI dst, memory mem) %{ | |
| 10993 // match(Set dst (LoadI mem)); | |
| 10994 // %} | |
| 10995 // | |
| 10996 // peephole %{ | |
| 10997 // peepmatch ( loadI storeI ); | |
| 10998 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 10999 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 11000 // %} | |
| 11001 | |
| 11002 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 11003 // These must follow all instruction definitions as they use the names | |
| 11004 // defined in the instructions definitions. | |
| 11005 // | |
| 11006 // SPARC will probably not have any of these rules due to RISC instruction set. | |
| 11007 | |
| 11008 //----------PIPELINE----------------------------------------------------------- | |
| 11009 // Rules which define the behavior of the target architectures pipeline. |