Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sparc.ad @ 6795:7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
Summary: use shorter instruction sequences for atomic add and atomic exchange when possible.
Reviewed-by: kvn, jrose
author | roland |
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date | Thu, 20 Sep 2012 16:49:17 +0200 |
parents | da91efe96a93 |
children | 859c45fb8cea |
rev | line source |
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0 | 1 // |
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2 // Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved. |
0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 // | |
5 // This code is free software; you can redistribute it and/or modify it | |
6 // under the terms of the GNU General Public License version 2 only, as | |
7 // published by the Free Software Foundation. | |
8 // | |
9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 // version 2 for more details (a copy is included in the LICENSE file that | |
13 // accompanied this code). | |
14 // | |
15 // You should have received a copy of the GNU General Public License version | |
16 // 2 along with this work; if not, write to the Free Software Foundation, | |
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 // | |
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
0 | 22 // |
23 // | |
24 | |
25 // SPARC Architecture Description File | |
26 | |
27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
28 // This information is used by the matcher and the register allocator to | |
29 // describe individual registers and classes of registers within the target | |
30 // archtecture. | |
31 register %{ | |
32 //----------Architecture Description Register Definitions---------------------- | |
33 // General Registers | |
34 // "reg_def" name ( register save type, C convention save type, | |
35 // ideal register type, encoding, vm name ); | |
36 // Register Save Types: | |
37 // | |
38 // NS = No-Save: The register allocator assumes that these registers | |
39 // can be used without saving upon entry to the method, & | |
40 // that they do not need to be saved at call sites. | |
41 // | |
42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
43 // can be used without saving upon entry to the method, | |
44 // but that they must be saved at call sites. | |
45 // | |
46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
47 // must be saved before using them upon entry to the | |
48 // method, but they do not need to be saved at call | |
49 // sites. | |
50 // | |
51 // AS = Always-Save: The register allocator assumes that these registers | |
52 // must be saved before using them upon entry to the | |
53 // method, & that they must be saved at call sites. | |
54 // | |
55 // Ideal Register Type is used to determine how to save & restore a | |
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
58 // | |
59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
60 | |
61 | |
62 // ---------------------------- | |
63 // Integer/Long Registers | |
64 // ---------------------------- | |
65 | |
66 // Need to expose the hi/lo aspect of 64-bit registers | |
67 // This register set is used for both the 64-bit build and | |
68 // the 32-bit build with 1-register longs. | |
69 | |
70 // Global Registers 0-7 | |
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
87 | |
88 // Output Registers 0-7 | |
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
105 | |
106 // Local Registers 0-7 | |
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
123 | |
124 // Input Registers 0-7 | |
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
141 | |
142 // ---------------------------- | |
143 // Float/Double Registers | |
144 // ---------------------------- | |
145 | |
146 // Float Registers | |
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
179 | |
180 // Double Registers | |
181 // The rules of ADL require that double registers be defined in pairs. | |
182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
183 // single float registers. In each pair, ADLC-assigned register numbers | |
184 // must be adjacent, with the lower number even. Finally, when the | |
185 // CPU stores such a register pair to memory, the word associated with | |
186 // the lower ADLC-assigned number must be stored to the lower address. | |
187 | |
188 // These definitions specify the actual bit encodings of the sparc | |
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
190 // wants 0-63, so we have to convert every time we want to use fp regs | |
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
605 | 192 // 255 is a flag meaning "don't go here". |
0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
194 // the place in the sparc stack crawler that asserts on the 255 is | |
195 // fixed up. | |
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196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
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197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
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198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
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199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
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200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
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201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
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202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
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203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
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204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
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205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
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206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
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207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
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208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
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209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
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210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
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211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
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212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
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213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
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214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
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215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
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216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
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217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
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218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
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219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
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220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
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221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
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222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
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223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
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224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
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225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
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226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
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227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
0 | 228 |
229 | |
230 // ---------------------------- | |
231 // Special Registers | |
232 // Condition Codes Flag Registers | |
233 // I tried to break out ICC and XCC but it's not very pretty. | |
234 // Every Sparc instruction which defs/kills one also kills the other. | |
235 // Hence every compare instruction which defs one kind of flags ends | |
236 // up needing a kill of the other. | |
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
238 | |
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
243 | |
244 // ---------------------------- | |
245 // Specify the enum values for the registers. These enums are only used by the | |
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
247 // for visibility to the rest of the vm. The order of this enum influences the | |
248 // register allocator so having the freedom to set this order and not be stuck | |
249 // with the order that is natural for the rest of the vm is worth it. | |
250 alloc_class chunk0( | |
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
255 | |
256 // Note that a register is not allocatable unless it is also mentioned | |
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
258 | |
259 alloc_class chunk1( | |
260 // The first registers listed here are those most likely to be used | |
261 // as temporaries. We move F0..F7 away from the front of the list, | |
262 // to reduce the likelihood of interferences with parameters and | |
263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
264 // since they are used for return values. | |
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
274 | |
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
276 | |
277 //----------Architecture Description Register Classes-------------------------- | |
278 // Several register classes are automatically defined based upon information in | |
279 // this architecture description. | |
280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
283 // | |
284 | |
285 // G0 is not included in integer class since it has special meaning. | |
286 reg_class g0_reg(R_G0); | |
287 | |
288 // ---------------------------- | |
289 // Integer Register Classes | |
290 // ---------------------------- | |
291 // Exclusions from i_reg: | |
292 // R_G0: hardwired zero | |
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
294 // R_G6: reserved by Solaris ABI to tools | |
295 // R_G7: reserved by Solaris ABI to libthread | |
296 // R_O7: Used as a temp in many encodings | |
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
298 | |
299 // Class for all integer registers, except the G registers. This is used for | |
300 // encodings which use G registers as temps. The regular inputs to such | |
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
302 // will not put an input into a temp register. | |
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
304 | |
305 reg_class g1_regI(R_G1); | |
306 reg_class g3_regI(R_G3); | |
307 reg_class g4_regI(R_G4); | |
308 reg_class o0_regI(R_O0); | |
309 reg_class o7_regI(R_O7); | |
310 | |
311 // ---------------------------- | |
312 // Pointer Register Classes | |
313 // ---------------------------- | |
314 #ifdef _LP64 | |
315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
320 // Lock encodings use G3 and G4 internally | |
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
326 // It is also used for memory addressing, allowing direct TLS addressing. | |
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
332 // We use it to save R_G2 across calls out of Java. | |
333 reg_class l7_regP(R_L7H,R_L7); | |
334 | |
335 // Other special pointer regs | |
336 reg_class g1_regP(R_G1H,R_G1); | |
337 reg_class g2_regP(R_G2H,R_G2); | |
338 reg_class g3_regP(R_G3H,R_G3); | |
339 reg_class g4_regP(R_G4H,R_G4); | |
340 reg_class g5_regP(R_G5H,R_G5); | |
341 reg_class i0_regP(R_I0H,R_I0); | |
342 reg_class o0_regP(R_O0H,R_O0); | |
343 reg_class o1_regP(R_O1H,R_O1); | |
344 reg_class o2_regP(R_O2H,R_O2); | |
345 reg_class o7_regP(R_O7H,R_O7); | |
346 | |
347 #else // _LP64 | |
348 // 32-bit build means 32-bit pointers means 1 register. | |
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
353 // Lock encodings use G3 and G4 internally | |
354 reg_class lock_ptr_reg(R_G1, R_G5, | |
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
359 // It is also used for memory addressing, allowing direct TLS addressing. | |
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
365 // We use it to save R_G2 across calls out of Java. | |
366 reg_class l7_regP(R_L7); | |
367 | |
368 // Other special pointer regs | |
369 reg_class g1_regP(R_G1); | |
370 reg_class g2_regP(R_G2); | |
371 reg_class g3_regP(R_G3); | |
372 reg_class g4_regP(R_G4); | |
373 reg_class g5_regP(R_G5); | |
374 reg_class i0_regP(R_I0); | |
375 reg_class o0_regP(R_O0); | |
376 reg_class o1_regP(R_O1); | |
377 reg_class o2_regP(R_O2); | |
378 reg_class o7_regP(R_O7); | |
379 #endif // _LP64 | |
380 | |
381 | |
382 // ---------------------------- | |
383 // Long Register Classes | |
384 // ---------------------------- | |
385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
389 #ifdef _LP64 | |
390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
394 #endif // _LP64 | |
395 ); | |
396 | |
397 reg_class g1_regL(R_G1H,R_G1); | |
420
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398 reg_class g3_regL(R_G3H,R_G3); |
0 | 399 reg_class o2_regL(R_O2H,R_O2); |
400 reg_class o7_regL(R_O7H,R_O7); | |
401 | |
402 // ---------------------------- | |
403 // Special Class for Condition Code Flags Register | |
404 reg_class int_flags(CCR); | |
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
406 reg_class float_flag0(FCC0); | |
407 | |
408 | |
409 // ---------------------------- | |
410 // Float Point Register Classes | |
411 // ---------------------------- | |
412 // Skip F30/F31, they are reserved for mem-mem copies | |
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
414 | |
415 // Paired floating point registers--they show up in the same order as the floats, | |
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
422 ); | |
423 | |
424 // Paired floating point registers--they show up in the same order as the floats, | |
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
3804 | 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); |
0 | 429 %} |
430 | |
431 //----------DEFINITION BLOCK--------------------------------------------------- | |
432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
434 // Format: | |
435 // int_def <name> ( <int_value>, <expression>); | |
436 // Generated Code in ad_<arch>.hpp | |
437 // #define <name> (<expression>) | |
438 // // value == <int_value> | |
439 // Generated code in ad_<arch>.cpp adlc_verification() | |
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
441 // | |
442 definitions %{ | |
443 // The default cost (of an ALU instruction). | |
444 int_def DEFAULT_COST ( 100, 100); | |
445 int_def HUGE_COST (1000000, 1000000); | |
446 | |
447 // Memory refs are twice as expensive as run-of-the-mill. | |
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
449 | |
450 // Branches are even more expensive. | |
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
453 %} | |
454 | |
455 | |
456 //----------SOURCE BLOCK------------------------------------------------------- | |
457 // This is a block of C++ code which provides values, functions, and | |
458 // definitions necessary in the rest of the architecture description | |
459 source_hpp %{ | |
460 // Must be visible to the DFA in dfa_sparc.cpp | |
461 extern bool can_branch_register( Node *bol, Node *cmp ); | |
462 | |
3892 | 463 extern bool use_block_zeroing(Node* count); |
464 | |
0 | 465 // Macros to extract hi & lo halves from a long pair. |
466 // G0 is not part of any long pair, so assert on that. | |
605 | 467 // Prevents accidentally using G1 instead of G0. |
0 | 468 #define LONG_HI_REG(x) (x) |
469 #define LONG_LO_REG(x) (x) | |
470 | |
471 %} | |
472 | |
473 source %{ | |
474 #define __ _masm. | |
475 | |
476 // tertiary op of a LoadP or StoreP encoding | |
477 #define REGP_OP true | |
478 | |
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
481 static Register reg_to_register_object(int register_encoding); | |
482 | |
483 // Used by the DFA in dfa_sparc.cpp. | |
484 // Check for being able to use a V9 branch-on-register. Requires a | |
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
486 // extended. Doesn't work following an integer ADD, for example, because of | |
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
489 // replace them with zero, which could become sign-extension in a different OS | |
490 // release. There's no obvious reason why an interrupt will ever fill these | |
491 // bits with non-zero junk (the registers are reloaded with standard LD | |
492 // instructions which either zero-fill or sign-fill). | |
493 bool can_branch_register( Node *bol, Node *cmp ) { | |
494 if( !BranchOnRegister ) return false; | |
495 #ifdef _LP64 | |
496 if( cmp->Opcode() == Op_CmpP ) | |
497 return true; // No problems with pointer compares | |
498 #endif | |
499 if( cmp->Opcode() == Op_CmpL ) | |
500 return true; // No problems with long compares | |
501 | |
502 if( !SparcV9RegsHiBitsZero ) return false; | |
503 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
504 bol->as_Bool()->_test._test != BoolTest::eq ) | |
505 return false; | |
506 | |
507 // Check for comparing against a 'safe' value. Any operation which | |
508 // clears out the high word is safe. Thus, loads and certain shifts | |
509 // are safe, as are non-negative constants. Any operation which | |
510 // preserves zero bits in the high word is safe as long as each of its | |
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
512 // inputs are safe. At present, the only important case to recognize | |
513 // seems to be loads. Constants should fold away, and shifts & | |
514 // logicals can use the 'cc' forms. | |
515 Node *x = cmp->in(1); | |
516 if( x->is_Load() ) return true; | |
517 if( x->is_Phi() ) { | |
518 for( uint i = 1; i < x->req(); i++ ) | |
519 if( !x->in(i)->is_Load() ) | |
520 return false; | |
521 return true; | |
522 } | |
523 return false; | |
524 } | |
525 | |
3892 | 526 bool use_block_zeroing(Node* count) { |
527 // Use BIS for zeroing if count is not constant | |
528 // or it is >= BlockZeroingLowLimit. | |
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit); | |
530 } | |
531 | |
0 | 532 // **************************************************************************** |
533 | |
534 // REQUIRED FUNCTIONALITY | |
535 | |
536 // !!!!! Special hack to get all type of calls to specify the byte offset | |
537 // from the start of the call to the point where the return address | |
538 // will point. | |
539 // The "return address" is the address of the call instruction, plus 8. | |
540 | |
541 int MachCallStaticJavaNode::ret_addr_offset() { | |
1567 | 542 int offset = NativeCall::instruction_size; // call; delay slot |
543 if (_method_handle_invoke) | |
544 offset += 4; // restore SP | |
545 return offset; | |
0 | 546 } |
547 | |
548 int MachCallDynamicJavaNode::ret_addr_offset() { | |
549 int vtable_index = this->_vtable_index; | |
550 if (vtable_index < 0) { | |
551 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
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552 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
0 | 553 return (NativeMovConstReg::instruction_size + |
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
555 } else { | |
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
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557 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
0 | 558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); |
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559 int klass_load_size; |
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560 if (UseCompressedOops && UseCompressedKlassPointers) { |
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561 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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562 if (Universe::narrow_oop_base() == NULL) |
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563 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() |
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564 else |
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565 klass_load_size = 3*BytesPerInstWord; |
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566 } else { |
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567 klass_load_size = 1*BytesPerInstWord; |
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568 } |
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569 if (Assembler::is_simm13(v_off)) { |
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570 return klass_load_size + |
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571 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
0 | 572 NativeCall::instruction_size); // call; delay slot |
573 } else { | |
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574 return klass_load_size + |
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575 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
0 | 576 NativeCall::instruction_size); // call; delay slot |
577 } | |
578 } | |
579 } | |
580 | |
581 int MachCallRuntimeNode::ret_addr_offset() { | |
582 #ifdef _LP64 | |
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583 if (MacroAssembler::is_far_target(entry_point())) { |
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584 return NativeFarCall::instruction_size; |
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585 } else { |
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586 return NativeCall::instruction_size; |
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587 } |
0 | 588 #else |
589 return NativeCall::instruction_size; // call; delay slot | |
590 #endif | |
591 } | |
592 | |
593 // Indicate if the safepoint node needs the polling page as an input. | |
594 // Since Sparc does not have absolute addressing, it does. | |
595 bool SafePointNode::needs_polling_address_input() { | |
596 return true; | |
597 } | |
598 | |
599 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
600 void emit_break(CodeBuffer &cbuf) { | |
601 MacroAssembler _masm(&cbuf); | |
602 __ breakpoint_trap(); | |
603 } | |
604 | |
605 #ifndef PRODUCT | |
606 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
607 st->print("TA"); | |
608 } | |
609 #endif | |
610 | |
611 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
612 emit_break(cbuf); | |
613 } | |
614 | |
615 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
616 return MachNode::size(ra_); | |
617 } | |
618 | |
619 // Traceable jump | |
620 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
621 MacroAssembler _masm(&cbuf); | |
622 Register rdest = reg_to_register_object(jump_target); | |
623 __ JMP(rdest, 0); | |
624 __ delayed()->nop(); | |
625 } | |
626 | |
627 // Traceable jump and set exception pc | |
628 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
629 MacroAssembler _masm(&cbuf); | |
630 Register rdest = reg_to_register_object(jump_target); | |
631 __ JMP(rdest, 0); | |
632 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
633 } | |
634 | |
635 void emit_nop(CodeBuffer &cbuf) { | |
636 MacroAssembler _masm(&cbuf); | |
637 __ nop(); | |
638 } | |
639 | |
640 void emit_illtrap(CodeBuffer &cbuf) { | |
641 MacroAssembler _masm(&cbuf); | |
642 __ illtrap(0); | |
643 } | |
644 | |
645 | |
646 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
647 assert(n->rule() != loadUB_rule, ""); | |
648 | |
649 intptr_t offset = 0; | |
650 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
651 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
652 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
653 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
654 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
655 atype = atype->add_offset(offset); | |
656 assert(disp32 == offset, "wrong disp32"); | |
657 return atype->_offset; | |
658 } | |
659 | |
660 | |
661 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
662 assert(n->rule() != loadUB_rule, ""); | |
663 | |
664 intptr_t offset = 0; | |
665 Node* addr = n->in(2); | |
666 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
667 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
668 Node* a = addr->in(2/*AddPNode::Address*/); | |
669 Node* o = addr->in(3/*AddPNode::Offset*/); | |
670 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
671 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
672 assert(atype->isa_oop_ptr(), "still an oop"); | |
673 } | |
674 offset = atype->is_ptr()->_offset; | |
675 if (offset != Type::OffsetBot) offset += disp32; | |
676 return offset; | |
677 } | |
678 | |
2008 | 679 static inline jdouble replicate_immI(int con, int count, int width) { |
680 // Load a constant replicated "count" times with width "width" | |
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681 assert(count*width == 8 && width <= 4, "sanity"); |
2008 | 682 int bit_width = width * 8; |
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683 jlong val = con; |
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684 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits |
2008 | 685 for (int i = 0; i < count - 1; i++) { |
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686 val |= (val << bit_width); |
2008 | 687 } |
688 jdouble dval = *((jdouble*) &val); // coerce to double type | |
689 return dval; | |
690 } | |
691 | |
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692 static inline jdouble replicate_immF(float con) { |
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693 // Replicate float con 2 times and pack into vector. |
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694 int val = *((int*)&con); |
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695 jlong lval = val; |
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696 lval = (lval << 32) | (lval & 0xFFFFFFFFl); |
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697 jdouble dval = *((jdouble*) &lval); // coerce to double type |
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698 return dval; |
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699 } |
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700 |
0 | 701 // Standard Sparc opcode form2 field breakdown |
702 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
703 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
704 int op = (f30 << 30) | | |
705 (f29 << 29) | | |
706 (f25 << 25) | | |
707 (f22 << 22) | | |
708 (f20 << 20) | | |
709 (f19 << 19) | | |
710 (f0 << 0); | |
1748 | 711 cbuf.insts()->emit_int32(op); |
0 | 712 } |
713 | |
714 // Standard Sparc opcode form2 field breakdown | |
715 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
716 f0 >>= 10; // Drop 10 bits | |
717 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
718 int op = (f30 << 30) | | |
719 (f25 << 25) | | |
720 (f22 << 22) | | |
721 (f0 << 0); | |
1748 | 722 cbuf.insts()->emit_int32(op); |
0 | 723 } |
724 | |
725 // Standard Sparc opcode form3 field breakdown | |
726 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
727 int op = (f30 << 30) | | |
728 (f25 << 25) | | |
729 (f19 << 19) | | |
730 (f14 << 14) | | |
731 (f5 << 5) | | |
732 (f0 << 0); | |
1748 | 733 cbuf.insts()->emit_int32(op); |
0 | 734 } |
735 | |
736 // Standard Sparc opcode form3 field breakdown | |
737 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
738 simm13 &= (1<<13)-1; // Mask to 13 bits | |
739 int op = (f30 << 30) | | |
740 (f25 << 25) | | |
741 (f19 << 19) | | |
742 (f14 << 14) | | |
743 (1 << 13) | // bit to indicate immediate-mode | |
744 (simm13<<0); | |
1748 | 745 cbuf.insts()->emit_int32(op); |
0 | 746 } |
747 | |
748 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
749 simm10 &= (1<<10)-1; // Mask to 10 bits | |
750 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
751 } | |
752 | |
753 #ifdef ASSERT | |
754 // Helper function for VerifyOops in emit_form3_mem_reg | |
755 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
756 warning("VerifyOops encountered unexpected instruction:"); | |
757 n->dump(2); | |
758 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
759 } | |
760 #endif | |
761 | |
762 | |
763 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
764 int src1_enc, int disp32, int src2_enc, int dst_enc) { | |
765 | |
766 #ifdef ASSERT | |
767 // The following code implements the +VerifyOops feature. | |
768 // It verifies oop values which are loaded into or stored out of | |
769 // the current method activation. +VerifyOops complements techniques | |
770 // like ScavengeALot, because it eagerly inspects oops in transit, | |
771 // as they enter or leave the stack, as opposed to ScavengeALot, | |
772 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
773 // For this reason, +VerifyOops can sometimes detect bugs very close | |
774 // to their point of creation. It can also serve as a cross-check | |
775 // on the validity of oop maps, when used toegether with ScavengeALot. | |
776 | |
777 // It would be good to verify oops at other points, especially | |
778 // when an oop is used as a base pointer for a load or store. | |
779 // This is presently difficult, because it is hard to know when | |
780 // a base address is biased or not. (If we had such information, | |
781 // it would be easy and useful to make a two-argument version of | |
782 // verify_oop which unbiases the base, and performs verification.) | |
783 | |
784 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
785 bool is_verified_oop_base = false; | |
786 bool is_verified_oop_load = false; | |
787 bool is_verified_oop_store = false; | |
788 int tmp_enc = -1; | |
789 if (VerifyOops && src1_enc != R_SP_enc) { | |
790 // classify the op, mainly for an assert check | |
791 int st_op = 0, ld_op = 0; | |
792 switch (primary) { | |
793 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
794 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
795 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
796 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
797 case Assembler::std_op3: st_op = Op_StoreL; break; | |
798 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
799 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
800 | |
801 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
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802 case Assembler::ldub_op3: ld_op = Op_LoadUB; break; |
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803 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
0 | 804 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
805 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
806 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
807 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
808 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
809 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
810 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
811 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
812 | |
813 default: ShouldNotReachHere(); | |
814 } | |
815 if (tertiary == REGP_OP) { | |
816 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
817 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
818 else ShouldNotReachHere(); | |
819 if (st_op) { | |
820 // a store | |
821 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
822 Node* n2 = n->in(3); | |
823 if (n2 != NULL) { | |
824 const Type* t = n2->bottom_type(); | |
825 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
826 } | |
827 } else { | |
828 // a load | |
829 const Type* t = n->bottom_type(); | |
830 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
831 } | |
832 } | |
833 | |
834 if (ld_op) { | |
835 // a Load | |
836 // inputs are (0:control, 1:memory, 2:address) | |
837 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
838 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
839 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
840 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
841 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
842 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
843 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
844 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
845 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
846 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
847 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
848 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
849 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
3898 | 850 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) && |
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851 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) && |
0 | 852 !(n->rule() == loadUB_rule)) { |
853 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
854 } | |
855 } else if (st_op) { | |
856 // a Store | |
857 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
858 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
859 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
860 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
861 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
862 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
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863 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) && |
0 | 864 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { |
865 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
866 } | |
867 } | |
868 | |
869 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
870 Node* addr = n->in(2); | |
871 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
872 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
873 if (atype != NULL) { | |
874 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
875 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
876 if (offset != offset_2) { | |
877 get_offset_from_base(n, atype, disp32); | |
878 get_offset_from_base_2(n, atype, disp32); | |
879 } | |
880 assert(offset == offset_2, "different offsets"); | |
881 if (offset == disp32) { | |
882 // we now know that src1 is a true oop pointer | |
883 is_verified_oop_base = true; | |
884 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
885 if( primary == Assembler::ldd_op3 ) { | |
886 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
887 } else { | |
888 tmp_enc = dst_enc; | |
889 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
890 assert(src1_enc != dst_enc, ""); | |
891 } | |
892 } | |
893 } | |
894 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
895 || offset == oopDesc::mark_offset_in_bytes())) { | |
896 // loading the mark should not be allowed either, but | |
897 // we don't check this since it conflicts with InlineObjectHash | |
898 // usage of LoadINode to get the mark. We could keep the | |
899 // check if we create a new LoadMarkNode | |
900 // but do not verify the object before its header is initialized | |
901 ShouldNotReachHere(); | |
902 } | |
903 } | |
904 } | |
905 } | |
906 } | |
907 #endif | |
908 | |
909 uint instr; | |
910 instr = (Assembler::ldst_op << 30) | |
911 | (dst_enc << 25) | |
912 | (primary << 19) | |
913 | (src1_enc << 14); | |
914 | |
915 uint index = src2_enc; | |
916 int disp = disp32; | |
917 | |
918 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
919 disp += STACK_BIAS; | |
920 | |
921 // We should have a compiler bailout here rather than a guarantee. | |
922 // Better yet would be some mechanism to handle variable-size matches correctly. | |
923 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
924 | |
925 if( disp == 0 ) { | |
926 // use reg-reg form | |
927 // bit 13 is already zero | |
928 instr |= index; | |
929 } else { | |
930 // use reg-imm form | |
931 instr |= 0x00002000; // set bit 13 to one | |
932 instr |= disp & 0x1FFF; | |
933 } | |
934 | |
1748 | 935 cbuf.insts()->emit_int32(instr); |
0 | 936 |
937 #ifdef ASSERT | |
938 { | |
939 MacroAssembler _masm(&cbuf); | |
940 if (is_verified_oop_base) { | |
941 __ verify_oop(reg_to_register_object(src1_enc)); | |
942 } | |
943 if (is_verified_oop_store) { | |
944 __ verify_oop(reg_to_register_object(dst_enc)); | |
945 } | |
946 if (tmp_enc != -1) { | |
947 __ mov(O7, reg_to_register_object(tmp_enc)); | |
948 } | |
949 if (is_verified_oop_load) { | |
950 __ verify_oop(reg_to_register_object(dst_enc)); | |
951 } | |
952 } | |
953 #endif | |
954 } | |
955 | |
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956 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) { |
0 | 957 // The method which records debug information at every safepoint |
958 // expects the call to be the first instruction in the snippet as | |
959 // it creates a PcDesc structure which tracks the offset of a call | |
960 // from the start of the codeBlob. This offset is computed as | |
961 // code_end() - code_begin() of the code which has been emitted | |
962 // so far. | |
963 // In this particular case we have skirted around the problem by | |
964 // putting the "mov" instruction in the delay slot but the problem | |
965 // may bite us again at some other point and a cleaner/generic | |
966 // solution using relocations would be needed. | |
967 MacroAssembler _masm(&cbuf); | |
968 __ set_inst_mark(); | |
969 | |
970 // We flush the current window just so that there is a valid stack copy | |
971 // the fact that the current window becomes active again instantly is | |
972 // not a problem there is nothing live in it. | |
973 | |
974 #ifdef ASSERT | |
975 int startpos = __ offset(); | |
976 #endif /* ASSERT */ | |
977 | |
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978 __ call((address)entry_point, rtype); |
0 | 979 |
980 if (preserve_g2) __ delayed()->mov(G2, L7); | |
981 else __ delayed()->nop(); | |
982 | |
983 if (preserve_g2) __ mov(L7, G2); | |
984 | |
985 #ifdef ASSERT | |
986 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
987 #ifdef _LP64 | |
988 // Trash argument dump slots. | |
989 __ set(0xb0b8ac0db0b8ac0d, G1); | |
990 __ mov(G1, G5); | |
991 __ stx(G1, SP, STACK_BIAS + 0x80); | |
992 __ stx(G1, SP, STACK_BIAS + 0x88); | |
993 __ stx(G1, SP, STACK_BIAS + 0x90); | |
994 __ stx(G1, SP, STACK_BIAS + 0x98); | |
995 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
996 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
997 #else // _LP64 | |
998 // this is also a native call, so smash the first 7 stack locations, | |
999 // and the various registers | |
1000 | |
1001 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
1002 // while [SP+0x44..0x58] are the argument dump slots. | |
1003 __ set((intptr_t)0xbaadf00d, G1); | |
1004 __ mov(G1, G5); | |
1005 __ sllx(G1, 32, G1); | |
1006 __ or3(G1, G5, G1); | |
1007 __ mov(G1, G5); | |
1008 __ stx(G1, SP, 0x40); | |
1009 __ stx(G1, SP, 0x48); | |
1010 __ stx(G1, SP, 0x50); | |
1011 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
1012 #endif // _LP64 | |
1013 } | |
1014 #endif /*ASSERT*/ | |
1015 } | |
1016 | |
1017 //============================================================================= | |
1018 // REQUIRED FUNCTIONALITY for encoding | |
1019 void emit_lo(CodeBuffer &cbuf, int val) { } | |
1020 void emit_hi(CodeBuffer &cbuf, int val) { } | |
1021 | |
1022 | |
1023 //============================================================================= | |
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1024 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask(); |
2008 | 1025 |
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1026 int Compile::ConstantTable::calculate_table_base_offset() const { |
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1027 if (UseRDPCForConstantTableBase) { |
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1028 // The table base offset might be less but then it fits into |
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1029 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit). |
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1030 return Assembler::min_simm13(); |
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1031 } else { |
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1032 int offset = -(size() / 2); |
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1033 if (!Assembler::is_simm13(offset)) { |
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1034 offset = Assembler::min_simm13(); |
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1035 } |
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1036 return offset; |
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1037 } |
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1038 } |
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1039 |
2008 | 1040 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
1041 Compile* C = ra_->C; | |
1042 Compile::ConstantTable& constant_table = C->constant_table(); | |
1043 MacroAssembler _masm(&cbuf); | |
1044 | |
1045 Register r = as_Register(ra_->get_encode(this)); | |
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1046 CodeSection* consts_section = __ code()->consts(); |
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1047 int consts_size = consts_section->align_at_start(consts_section->size()); |
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1048 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); |
2008 | 1049 |
1050 if (UseRDPCForConstantTableBase) { | |
1051 // For the following RDPC logic to work correctly the consts | |
1052 // section must be allocated right before the insts section. This | |
1053 // assert checks for that. The layout and the SECT_* constants | |
1054 // are defined in src/share/vm/asm/codeBuffer.hpp. | |
1055 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); | |
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1056 int insts_offset = __ offset(); |
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1057 |
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1058 // Layout: |
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1059 // |
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1060 // |----------- consts section ------------|----------- insts section -----------... |
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1061 // |------ constant table -----|- padding -|------------------x---- |
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1062 // \ current PC (RDPC instruction) |
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1063 // |<------------- consts_size ----------->|<- insts_offset ->| |
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1064 // \ table base |
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1065 // The table base offset is later added to the load displacement |
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1066 // so it has to be negative. |
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1067 int table_base_offset = -(consts_size + insts_offset); |
2008 | 1068 int disp; |
1069 | |
1070 // If the displacement from the current PC to the constant table | |
1071 // base fits into simm13 we set the constant table base to the | |
1072 // current PC. | |
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1073 if (Assembler::is_simm13(table_base_offset)) { |
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1074 constant_table.set_table_base_offset(table_base_offset); |
2008 | 1075 disp = 0; |
1076 } else { | |
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1077 // Otherwise we set the constant table base offset to the |
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1078 // maximum negative displacement of load instructions to keep |
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1079 // the disp as small as possible: |
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1080 // |
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1081 // |<------------- consts_size ----------->|<- insts_offset ->| |
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1082 // |<--------- min_simm13 --------->|<-------- disp --------->| |
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1083 // \ table base |
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1084 table_base_offset = Assembler::min_simm13(); |
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1085 constant_table.set_table_base_offset(table_base_offset); |
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1086 disp = (consts_size + insts_offset) + table_base_offset; |
2008 | 1087 } |
1088 | |
1089 __ rdpc(r); | |
1090 | |
1091 if (disp != 0) { | |
1092 assert(r != O7, "need temporary"); | |
1093 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); | |
1094 } | |
1095 } | |
1096 else { | |
1097 // Materialize the constant table base. | |
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1098 address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); |
2008 | 1099 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); |
1100 AddressLiteral base(baseaddr, rspec); | |
1101 __ set(base, r); | |
1102 } | |
1103 } | |
1104 | |
1105 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { | |
1106 if (UseRDPCForConstantTableBase) { | |
1107 // This is really the worst case but generally it's only 1 instruction. | |
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1108 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; |
2008 | 1109 } else { |
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1110 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; |
2008 | 1111 } |
1112 } | |
1113 | |
1114 #ifndef PRODUCT | |
1115 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
1116 char reg[128]; | |
1117 ra_->dump_register(this, reg); | |
1118 if (UseRDPCForConstantTableBase) { | |
1119 st->print("RDPC %s\t! constant table base", reg); | |
1120 } else { | |
1121 st->print("SET &constanttable,%s\t! constant table base", reg); | |
1122 } | |
1123 } | |
1124 #endif | |
1125 | |
1126 | |
1127 //============================================================================= | |
0 | 1128 |
1129 #ifndef PRODUCT | |
1130 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1131 Compile* C = ra_->C; | |
1132 | |
1133 for (int i = 0; i < OptoPrologueNops; i++) { | |
1134 st->print_cr("NOP"); st->print("\t"); | |
1135 } | |
1136 | |
1137 if( VerifyThread ) { | |
1138 st->print_cr("Verify_Thread"); st->print("\t"); | |
1139 } | |
1140 | |
1141 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
1142 | |
1143 // Calls to C2R adapters often do not accept exceptional returns. | |
1144 // We require that their callers must bang for them. But be careful, because | |
1145 // some VM calls (such as call site linkage) can use several kilobytes of | |
1146 // stack. But the stack safety zone should account for that. | |
1147 // See bugs 4446381, 4468289, 4497237. | |
1148 if (C->need_stack_bang(framesize)) { | |
1149 st->print_cr("! stack bang"); st->print("\t"); | |
1150 } | |
1151 | |
1152 if (Assembler::is_simm13(-framesize)) { | |
1153 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
1154 } else { | |
1155 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
1156 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
1157 st->print ("SAVE R_SP,R_G3,R_SP"); | |
1158 } | |
1159 | |
1160 } | |
1161 #endif | |
1162 | |
1163 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1164 Compile* C = ra_->C; | |
1165 MacroAssembler _masm(&cbuf); | |
1166 | |
1167 for (int i = 0; i < OptoPrologueNops; i++) { | |
1168 __ nop(); | |
1169 } | |
1170 | |
1171 __ verify_thread(); | |
1172 | |
1173 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
1174 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
1175 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
1176 | |
1177 // Calls to C2R adapters often do not accept exceptional returns. | |
1178 // We require that their callers must bang for them. But be careful, because | |
1179 // some VM calls (such as call site linkage) can use several kilobytes of | |
1180 // stack. But the stack safety zone should account for that. | |
1181 // See bugs 4446381, 4468289, 4497237. | |
1182 if (C->need_stack_bang(framesize)) { | |
1183 __ generate_stack_overflow_check(framesize); | |
1184 } | |
1185 | |
1186 if (Assembler::is_simm13(-framesize)) { | |
1187 __ save(SP, -framesize, SP); | |
1188 } else { | |
1189 __ sethi(-framesize & ~0x3ff, G3); | |
1190 __ add(G3, -framesize & 0x3ff, G3); | |
1191 __ save(SP, G3, SP); | |
1192 } | |
1193 C->set_frame_complete( __ offset() ); | |
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1194 |
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1195 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) { |
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1196 // NOTE: We set the table base offset here because users might be |
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1197 // emitted before MachConstantBaseNode. |
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1198 Compile::ConstantTable& constant_table = C->constant_table(); |
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1199 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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1200 } |
0 | 1201 } |
1202 | |
1203 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
1204 return MachNode::size(ra_); | |
1205 } | |
1206 | |
1207 int MachPrologNode::reloc() const { | |
1208 return 10; // a large enough number | |
1209 } | |
1210 | |
1211 //============================================================================= | |
1212 #ifndef PRODUCT | |
1213 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1214 Compile* C = ra_->C; | |
1215 | |
1216 if( do_polling() && ra_->C->is_method_compilation() ) { | |
1217 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
1218 #ifdef _LP64 | |
1219 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
1220 #else | |
1221 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
1222 #endif | |
1223 } | |
1224 | |
1225 if( do_polling() ) | |
1226 st->print("RET\n\t"); | |
1227 | |
1228 st->print("RESTORE"); | |
1229 } | |
1230 #endif | |
1231 | |
1232 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1233 MacroAssembler _masm(&cbuf); | |
1234 Compile* C = ra_->C; | |
1235 | |
1236 __ verify_thread(); | |
1237 | |
1238 // If this does safepoint polling, then do it here | |
1239 if( do_polling() && ra_->C->is_method_compilation() ) { | |
727 | 1240 AddressLiteral polling_page(os::get_polling_page()); |
1241 __ sethi(polling_page, L0); | |
0 | 1242 __ relocate(relocInfo::poll_return_type); |
1243 __ ld_ptr( L0, 0, G0 ); | |
1244 } | |
1245 | |
1246 // If this is a return, then stuff the restore in the delay slot | |
1247 if( do_polling() ) { | |
1248 __ ret(); | |
1249 __ delayed()->restore(); | |
1250 } else { | |
1251 __ restore(); | |
1252 } | |
1253 } | |
1254 | |
1255 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
1256 return MachNode::size(ra_); | |
1257 } | |
1258 | |
1259 int MachEpilogNode::reloc() const { | |
1260 return 16; // a large enough number | |
1261 } | |
1262 | |
1263 const Pipeline * MachEpilogNode::pipeline() const { | |
1264 return MachNode::pipeline_class(); | |
1265 } | |
1266 | |
1267 int MachEpilogNode::safepoint_offset() const { | |
1268 assert( do_polling(), "no return for this epilog node"); | |
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1269 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; |
0 | 1270 } |
1271 | |
1272 //============================================================================= | |
1273 | |
1274 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
1275 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
1276 static enum RC rc_class( OptoReg::Name reg ) { | |
1277 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
1278 if (OptoReg::is_stack(reg)) return rc_stack; | |
1279 VMReg r = OptoReg::as_VMReg(reg); | |
1280 if (r->is_Register()) return rc_int; | |
1281 assert(r->is_FloatRegister(), "must be"); | |
1282 return rc_float; | |
1283 } | |
1284 | |
1285 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { | |
1286 if( cbuf ) { | |
1287 // Better yet would be some mechanism to handle variable-size matches correctly | |
1288 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
1289 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
1290 } else { | |
1291 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
1292 } | |
1293 } | |
1294 #ifndef PRODUCT | |
1295 else if( !do_size ) { | |
1296 if( size != 0 ) st->print("\n\t"); | |
1297 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | |
1298 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | |
1299 } | |
1300 #endif | |
1301 return size+4; | |
1302 } | |
1303 | |
1304 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
1305 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
1306 #ifndef PRODUCT | |
1307 else if( !do_size ) { | |
1308 if( size != 0 ) st->print("\n\t"); | |
1309 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
1310 } | |
1311 #endif | |
1312 return size+4; | |
1313 } | |
1314 | |
1315 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
1316 PhaseRegAlloc *ra_, | |
1317 bool do_size, | |
1318 outputStream* st ) const { | |
1319 // Get registers to move | |
1320 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
1321 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
1322 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
1323 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
1324 | |
1325 enum RC src_second_rc = rc_class(src_second); | |
1326 enum RC src_first_rc = rc_class(src_first); | |
1327 enum RC dst_second_rc = rc_class(dst_second); | |
1328 enum RC dst_first_rc = rc_class(dst_first); | |
1329 | |
1330 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
1331 | |
1332 // Generate spill code! | |
1333 int size = 0; | |
1334 | |
1335 if( src_first == dst_first && src_second == dst_second ) | |
1336 return size; // Self copy, no move | |
1337 | |
1338 // -------------------------------------- | |
1339 // Check for mem-mem move. Load into unused float registers and fall into | |
1340 // the float-store case. | |
1341 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
1342 int offset = ra_->reg2offset(src_first); | |
1343 // Further check for aligned-adjacent pair, so we can use a double load | |
1344 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
1345 src_second = OptoReg::Name(R_F31_num); | |
1346 src_second_rc = rc_float; | |
1347 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
1348 } else { | |
1349 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
1350 } | |
1351 src_first = OptoReg::Name(R_F30_num); | |
1352 src_first_rc = rc_float; | |
1353 } | |
1354 | |
1355 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
1356 int offset = ra_->reg2offset(src_second); | |
1357 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
1358 src_second = OptoReg::Name(R_F31_num); | |
1359 src_second_rc = rc_float; | |
1360 } | |
1361 | |
1362 // -------------------------------------- | |
1363 // Check for float->int copy; requires a trip through memory | |
3804 | 1364 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { |
0 | 1365 int offset = frame::register_save_words*wordSize; |
3804 | 1366 if (cbuf) { |
0 | 1367 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); |
1368 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1369 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1370 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
1371 } | |
1372 #ifndef PRODUCT | |
3804 | 1373 else if (!do_size) { |
1374 if (size != 0) st->print("\n\t"); | |
0 | 1375 st->print( "SUB R_SP,16,R_SP\n"); |
1376 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1377 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1378 st->print("\tADD R_SP,16,R_SP\n"); | |
1379 } | |
1380 #endif | |
1381 size += 16; | |
1382 } | |
1383 | |
3804 | 1384 // Check for float->int copy on T4 |
1385 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { | |
1386 // Further check for aligned-adjacent pair, so we can use a double move | |
1387 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
1388 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st); | |
1389 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st); | |
1390 } | |
1391 // Check for int->float copy on T4 | |
1392 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { | |
1393 // Further check for aligned-adjacent pair, so we can use a double move | |
1394 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
1395 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st); | |
1396 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st); | |
1397 } | |
1398 | |
0 | 1399 // -------------------------------------- |
1400 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
1401 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
1402 // hardware does the flop for me. Doubles are always aligned, so no problem | |
1403 // there. Misaligned sources only come from native-long-returns (handled | |
1404 // special below). | |
1405 #ifndef _LP64 | |
1406 if( src_first_rc == rc_int && // source is already big-endian | |
1407 src_second_rc != rc_bad && // 64-bit move | |
1408 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
1409 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
1410 // Do the big-endian flop. | |
1411 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
1412 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
1413 } | |
1414 #endif | |
1415 | |
1416 // -------------------------------------- | |
1417 // Check for integer reg-reg copy | |
1418 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
1419 #ifndef _LP64 | |
1420 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
1421 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1422 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1423 // operand contains the least significant word of the 64-bit value and vice versa. | |
1424 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
1425 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
1426 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
1427 if( cbuf ) { | |
1428 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
1429 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
1430 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
1431 #ifndef PRODUCT | |
1432 } else if( !do_size ) { | |
1433 if( size != 0 ) st->print("\n\t"); | |
1434 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
1435 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
1436 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
1437 #endif | |
1438 } | |
1439 return size+12; | |
1440 } | |
1441 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
1442 // returning a long value in I0/I1 | |
1443 // a SpillCopy must be able to target a return instruction's reg_class | |
1444 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1445 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1446 // operand contains the least significant word of the 64-bit value and vice versa. | |
1447 OptoReg::Name tdest = dst_first; | |
1448 | |
1449 if (src_first == dst_first) { | |
1450 tdest = OptoReg::Name(R_O7_num); | |
1451 size += 4; | |
1452 } | |
1453 | |
1454 if( cbuf ) { | |
1455 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
1456 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
1457 // ShrL_reg_imm6 | |
1458 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
1459 // ShrR_reg_imm6 src, 0, dst | |
1460 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
1461 if (tdest != dst_first) { | |
1462 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
1463 } | |
1464 } | |
1465 #ifndef PRODUCT | |
1466 else if( !do_size ) { | |
1467 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
1468 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
1469 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
1470 if (tdest != dst_first) { | |
1471 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
1472 } | |
1473 } | |
1474 #endif // PRODUCT | |
1475 return size+8; | |
1476 } | |
1477 #endif // !_LP64 | |
1478 // Else normal reg-reg copy | |
1479 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
1480 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
1481 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
1482 // This moves an aligned adjacent pair. | |
1483 // See if we are done. | |
1484 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
1485 return size; | |
1486 } | |
1487 | |
1488 // Check for integer store | |
1489 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
1490 int offset = ra_->reg2offset(dst_first); | |
1491 // Further check for aligned-adjacent pair, so we can use a double store | |
1492 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1493 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
1494 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
1495 } | |
1496 | |
1497 // Check for integer load | |
1498 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
1499 int offset = ra_->reg2offset(src_first); | |
1500 // Further check for aligned-adjacent pair, so we can use a double load | |
1501 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1502 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
1503 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1504 } | |
1505 | |
1506 // Check for float reg-reg copy | |
1507 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
1508 // Further check for aligned-adjacent pair, so we can use a double move | |
1509 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1510 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
1511 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
1512 } | |
1513 | |
1514 // Check for float store | |
1515 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
1516 int offset = ra_->reg2offset(dst_first); | |
1517 // Further check for aligned-adjacent pair, so we can use a double store | |
1518 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1519 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
1520 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1521 } | |
1522 | |
1523 // Check for float load | |
1524 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
1525 int offset = ra_->reg2offset(src_first); | |
1526 // Further check for aligned-adjacent pair, so we can use a double load | |
1527 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1528 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
1529 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
1530 } | |
1531 | |
1532 // -------------------------------------------------------------------- | |
1533 // Check for hi bits still needing moving. Only happens for misaligned | |
1534 // arguments to native calls. | |
1535 if( src_second == dst_second ) | |
1536 return size; // Self copy; no move | |
1537 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
1538 | |
1539 #ifndef _LP64 | |
1540 // In the LP64 build, all registers can be moved as aligned/adjacent | |
605 | 1541 // pairs, so there's never any need to move the high bits separately. |
0 | 1542 // The 32-bit builds have to deal with the 32-bit ABI which can force |
1543 // all sorts of silly alignment problems. | |
1544 | |
1545 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
1546 // 32-bits of a 64-bit register, but are needed in low bits of another | |
1547 // register (else it's a hi-bits-to-hi-bits copy which should have | |
1548 // happened already as part of a 64-bit move) | |
1549 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
1550 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
1551 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
1552 // Shift src_second down to dst_second's low bits. | |
1553 if( cbuf ) { | |
1554 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1555 #ifndef PRODUCT | |
1556 } else if( !do_size ) { | |
1557 if( size != 0 ) st->print("\n\t"); | |
1558 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
1559 #endif | |
1560 } | |
1561 return size+4; | |
1562 } | |
1563 | |
1564 // Check for high word integer store. Must down-shift the hi bits | |
1565 // into a temp register, then fall into the case of storing int bits. | |
1566 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
1567 // Shift src_second down to dst_second's low bits. | |
1568 if( cbuf ) { | |
1569 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1570 #ifndef PRODUCT | |
1571 } else if( !do_size ) { | |
1572 if( size != 0 ) st->print("\n\t"); | |
1573 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
1574 #endif | |
1575 } | |
1576 size+=4; | |
1577 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
1578 } | |
1579 | |
1580 // Check for high word integer load | |
1581 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
1582 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
1583 | |
1584 // Check for high word integer store | |
1585 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
1586 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
1587 | |
1588 // Check for high word float store | |
1589 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
1590 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
1591 | |
1592 #endif // !_LP64 | |
1593 | |
1594 Unimplemented(); | |
1595 } | |
1596 | |
1597 #ifndef PRODUCT | |
1598 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1599 implementation( NULL, ra_, false, st ); | |
1600 } | |
1601 #endif | |
1602 | |
1603 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1604 implementation( &cbuf, ra_, false, NULL ); | |
1605 } | |
1606 | |
1607 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
1608 return implementation( NULL, ra_, true, NULL ); | |
1609 } | |
1610 | |
1611 //============================================================================= | |
1612 #ifndef PRODUCT | |
1613 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
1614 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
1615 } | |
1616 #endif | |
1617 | |
1618 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
1619 MacroAssembler _masm(&cbuf); | |
1620 for(int i = 0; i < _count; i += 1) { | |
1621 __ nop(); | |
1622 } | |
1623 } | |
1624 | |
1625 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
1626 return 4 * _count; | |
1627 } | |
1628 | |
1629 | |
1630 //============================================================================= | |
1631 #ifndef PRODUCT | |
1632 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1633 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
1634 int reg = ra_->get_reg_first(this); | |
1635 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
1636 } | |
1637 #endif | |
1638 | |
1639 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1640 MacroAssembler _masm(&cbuf); | |
1641 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
1642 int reg = ra_->get_encode(this); | |
1643 | |
1644 if (Assembler::is_simm13(offset)) { | |
1645 __ add(SP, offset, reg_to_register_object(reg)); | |
1646 } else { | |
1647 __ set(offset, O7); | |
1648 __ add(SP, O7, reg_to_register_object(reg)); | |
1649 } | |
1650 } | |
1651 | |
1652 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
1653 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
1654 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
1655 return ra_->C->scratch_emit_size(this); | |
1656 } | |
1657 | |
1658 //============================================================================= | |
1659 | |
1660 // emit call stub, compiled java to interpretor | |
1661 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
1662 | |
1663 // Stub is fixed up when the corresponding call is converted from calling | |
1664 // compiled code to calling interpreted code. | |
1665 // set (empty), G5 | |
1666 // jmp -1 | |
1667 | |
1748 | 1668 address mark = cbuf.insts_mark(); // get mark within main instrs section |
0 | 1669 |
1670 MacroAssembler _masm(&cbuf); | |
1671 | |
1672 address base = | |
1673 __ start_a_stub(Compile::MAX_stubs_size); | |
1674 if (base == NULL) return; // CodeBuffer::expand failed | |
1675 | |
1676 // static stub relocation stores the instruction address of the call | |
1677 __ relocate(static_stub_Relocation::spec(mark)); | |
1678 | |
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6964458: Reimplement class meta-data storage to use native memory
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1679 __ set_metadata(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); |
0 | 1680 |
1681 __ set_inst_mark(); | |
727 | 1682 AddressLiteral addrlit(-1); |
1683 __ JUMP(addrlit, G3, 0); | |
0 | 1684 |
1685 __ delayed()->nop(); | |
1686 | |
1687 // Update current stubs pointer and restore code_end. | |
1688 __ end_a_stub(); | |
1689 } | |
1690 | |
1691 // size of call stub, compiled java to interpretor | |
1692 uint size_java_to_interp() { | |
1693 // This doesn't need to be accurate but it must be larger or equal to | |
1694 // the real size of the stub. | |
1695 return (NativeMovConstReg::instruction_size + // sethi/setlo; | |
1696 NativeJump::instruction_size + // sethi; jmp; nop | |
1697 (TraceJumps ? 20 * BytesPerInstWord : 0) ); | |
1698 } | |
1699 // relocation entries for call stub, compiled java to interpretor | |
1700 uint reloc_java_to_interp() { | |
1701 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call | |
1702 } | |
1703 | |
1704 | |
1705 //============================================================================= | |
1706 #ifndef PRODUCT | |
1707 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1708 st->print_cr("\nUEP:"); | |
1709 #ifdef _LP64 | |
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1710 if (UseCompressedOops) { |
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1711 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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1712 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
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1713 st->print_cr("\tSLL R_G5,3,R_G5"); |
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1714 if (Universe::narrow_oop_base() != NULL) |
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1715 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
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1716 } else { |
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1717 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
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1718 } |
0 | 1719 st->print_cr("\tCMP R_G5,R_G3" ); |
1720 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1721 #else // _LP64 | |
1722 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
1723 st->print_cr("\tCMP R_G5,R_G3" ); | |
1724 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1725 #endif // _LP64 | |
1726 } | |
1727 #endif | |
1728 | |
1729 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1730 MacroAssembler _masm(&cbuf); | |
1731 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
1732 Register temp_reg = G3; | |
1733 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
1734 | |
605 | 1735 // Load klass from receiver |
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1736 __ load_klass(O0, temp_reg); |
0 | 1737 // Compare against expected klass |
1738 __ cmp(temp_reg, G5_ic_reg); | |
1739 // Branch to miss code, checks xcc or icc depending | |
1740 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
1741 } | |
1742 | |
1743 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
1744 return MachNode::size(ra_); | |
1745 } | |
1746 | |
1747 | |
1748 //============================================================================= | |
1749 | |
1750 uint size_exception_handler() { | |
1751 if (TraceJumps) { | |
1752 return (400); // just a guess | |
1753 } | |
1754 return ( NativeJump::instruction_size ); // sethi;jmp;nop | |
1755 } | |
1756 | |
1757 uint size_deopt_handler() { | |
1758 if (TraceJumps) { | |
1759 return (400); // just a guess | |
1760 } | |
1761 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore | |
1762 } | |
1763 | |
1764 // Emit exception handler code. | |
1765 int emit_exception_handler(CodeBuffer& cbuf) { | |
1766 Register temp_reg = G3; | |
1748 | 1767 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); |
0 | 1768 MacroAssembler _masm(&cbuf); |
1769 | |
1770 address base = | |
1771 __ start_a_stub(size_exception_handler()); | |
1772 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1773 | |
1774 int offset = __ offset(); | |
1775 | |
727 | 1776 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
0 | 1777 __ delayed()->nop(); |
1778 | |
1779 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
1780 | |
1781 __ end_a_stub(); | |
1782 | |
1783 return offset; | |
1784 } | |
1785 | |
1786 int emit_deopt_handler(CodeBuffer& cbuf) { | |
1787 // Can't use any of the current frame's registers as we may have deopted | |
1788 // at a poll and everything (including G3) can be live. | |
1789 Register temp_reg = L0; | |
727 | 1790 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
0 | 1791 MacroAssembler _masm(&cbuf); |
1792 | |
1793 address base = | |
1794 __ start_a_stub(size_deopt_handler()); | |
1795 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1796 | |
1797 int offset = __ offset(); | |
1798 __ save_frame(0); | |
727 | 1799 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
0 | 1800 __ delayed()->restore(); |
1801 | |
1802 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
1803 | |
1804 __ end_a_stub(); | |
1805 return offset; | |
1806 | |
1807 } | |
1808 | |
1809 // Given a register encoding, produce a Integer Register object | |
1810 static Register reg_to_register_object(int register_encoding) { | |
1811 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
1812 return as_Register(register_encoding); | |
1813 } | |
1814 | |
1815 // Given a register encoding, produce a single-precision Float Register object | |
1816 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
1817 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
1818 return as_SingleFloatRegister(register_encoding); | |
1819 } | |
1820 | |
1821 // Given a register encoding, produce a double-precision Float Register object | |
1822 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
1823 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
1824 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
1825 return as_DoubleFloatRegister(register_encoding); | |
1826 } | |
1827 | |
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1828 const bool Matcher::match_rule_supported(int opcode) { |
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1829 if (!has_match_rule(opcode)) |
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1830 return false; |
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1831 |
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1832 switch (opcode) { |
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1833 case Op_CountLeadingZerosI: |
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1834 case Op_CountLeadingZerosL: |
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1835 case Op_CountTrailingZerosI: |
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1836 case Op_CountTrailingZerosL: |
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1837 case Op_PopCountI: |
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1838 case Op_PopCountL: |
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1839 if (!UsePopCountInstruction) |
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1840 return false; |
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1841 case Op_CompareAndSwapL: |
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1842 #ifdef _LP64 |
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1843 case Op_CompareAndSwapP: |
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1844 #endif |
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1845 if (!VM_Version::supports_cx8()) |
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1846 return false; |
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1847 break; |
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1848 } |
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1849 |
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1850 return true; // Per default match rules are supported. |
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1851 } |
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1852 |
0 | 1853 int Matcher::regnum_to_fpu_offset(int regnum) { |
1854 return regnum - 32; // The FP registers are in the second chunk | |
1855 } | |
1856 | |
1857 #ifdef ASSERT | |
1858 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
1859 #endif | |
1860 | |
1861 // Vector width in bytes | |
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1862 const int Matcher::vector_width_in_bytes(BasicType bt) { |
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1863 assert(MaxVectorSize == 8, ""); |
0 | 1864 return 8; |
1865 } | |
1866 | |
1867 // Vector ideal reg | |
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1868 const int Matcher::vector_ideal_reg(int size) { |
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1869 assert(MaxVectorSize == 8, ""); |
0 | 1870 return Op_RegD; |
1871 } | |
1872 | |
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1873 // Limits on vector size (number of elements) loaded into vector. |
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1874 const int Matcher::max_vector_size(const BasicType bt) { |
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1875 assert(is_java_primitive(bt), "only primitive type vectors"); |
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1876 return vector_width_in_bytes(bt)/type2aelembytes(bt); |
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1877 } |
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1878 |
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1879 const int Matcher::min_vector_size(const BasicType bt) { |
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1880 return max_vector_size(bt); // Same as max. |
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1881 } |
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1882 |
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1883 // SPARC doesn't support misaligned vectors store/load. |
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1884 const bool Matcher::misaligned_vectors_ok() { |
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1885 return false; |
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1886 } |
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1887 |
0 | 1888 // USII supports fxtof through the whole range of number, USIII doesn't |
1889 const bool Matcher::convL2FSupported(void) { | |
1890 return VM_Version::has_fast_fxtof(); | |
1891 } | |
1892 | |
1893 // Is this branch offset short enough that a short branch can be used? | |
1894 // | |
1895 // NOTE: If the platform does not provide any short branch variants, then | |
1896 // this method should return false for offset 0. | |
3851 | 1897 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
1898 // The passed offset is relative to address of the branch. | |
1899 // Don't need to adjust the offset. | |
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1900 return UseCBCond && Assembler::is_simm12(offset); |
0 | 1901 } |
1902 | |
1903 const bool Matcher::isSimpleConstant64(jlong value) { | |
1904 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
1905 // Depends on optimizations in MacroAssembler::setx. | |
1906 int hi = (int)(value >> 32); | |
1907 int lo = (int)(value & ~0); | |
1908 return (hi == 0) || (hi == -1) || (lo == 0); | |
1909 } | |
1910 | |
1911 // No scaling for the parameter the ClearArray node. | |
1912 const bool Matcher::init_array_count_is_in_bytes = true; | |
1913 | |
1914 // Threshold size for cleararray. | |
1915 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
1916 | |
4047 | 1917 // No additional cost for CMOVL. |
1918 const int Matcher::long_cmove_cost() { return 0; } | |
1919 | |
1920 // CMOVF/CMOVD are expensive on T4 and on SPARC64. | |
1921 const int Matcher::float_cmove_cost() { | |
1922 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; | |
1923 } | |
1924 | |
0 | 1925 // Should the Matcher clone shifts on addressing modes, expecting them to |
1926 // be subsumed into complex addressing expressions or compute them into | |
1927 // registers? True for Intel but false for most RISCs | |
1928 const bool Matcher::clone_shift_expressions = false; | |
1929 | |
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1930 // Do we need to mask the count passed to shift instructions or does |
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1931 // the cpu only look at the lower 5/6 bits anyway? |
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1932 const bool Matcher::need_masked_shift_count = false; |
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1933 |
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1934 bool Matcher::narrow_oop_use_complex_address() { |
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1935 NOT_LP64(ShouldNotCallThis()); |
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1936 assert(UseCompressedOops, "only for compressed oops code"); |
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1937 return false; |
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1938 } |
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1939 |
0 | 1940 // Is it better to copy float constants, or load them directly from memory? |
1941 // Intel can load a float constant from a direct address, requiring no | |
1942 // extra registers. Most RISCs will have to materialize an address into a | |
1943 // register first, so they would do better to copy the constant from stack. | |
1944 const bool Matcher::rematerialize_float_constants = false; | |
1945 | |
1946 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
1947 // needed. Else we split the double into 2 integer pieces and move it | |
1948 // piece-by-piece. Only happens when passing doubles into C code as the | |
1949 // Java calling convention forces doubles to be aligned. | |
1950 #ifdef _LP64 | |
1951 const bool Matcher::misaligned_doubles_ok = true; | |
1952 #else | |
1953 const bool Matcher::misaligned_doubles_ok = false; | |
1954 #endif | |
1955 | |
1956 // No-op on SPARC. | |
1957 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
1958 } | |
1959 | |
1960 // Advertise here if the CPU requires explicit rounding operations | |
1961 // to implement the UseStrictFP mode. | |
1962 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
1963 | |
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1964 // Are floats conerted to double when stored to stack during deoptimization? |
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1965 // Sparc does not handle callee-save floats. |
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1966 bool Matcher::float_in_double() { return false; } |
0 | 1967 |
1968 // Do ints take an entire long register or just half? | |
1969 // Note that we if-def off of _LP64. | |
1970 // The relevant question is how the int is callee-saved. In _LP64 | |
1971 // the whole long is written but de-opt'ing will have to extract | |
1972 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
1973 #ifdef _LP64 | |
1974 const bool Matcher::int_in_long = true; | |
1975 #else | |
1976 const bool Matcher::int_in_long = false; | |
1977 #endif | |
1978 | |
1979 // Return whether or not this register is ever used as an argument. This | |
1980 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
1981 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
1982 // arguments in those registers not be available to the callee. | |
1983 bool Matcher::can_be_java_arg( int reg ) { | |
1984 // Standard sparc 6 args in registers | |
1985 if( reg == R_I0_num || | |
1986 reg == R_I1_num || | |
1987 reg == R_I2_num || | |
1988 reg == R_I3_num || | |
1989 reg == R_I4_num || | |
1990 reg == R_I5_num ) return true; | |
1991 #ifdef _LP64 | |
1992 // 64-bit builds can pass 64-bit pointers and longs in | |
1993 // the high I registers | |
1994 if( reg == R_I0H_num || | |
1995 reg == R_I1H_num || | |
1996 reg == R_I2H_num || | |
1997 reg == R_I3H_num || | |
1998 reg == R_I4H_num || | |
1999 reg == R_I5H_num ) return true; | |
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2000 |
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2001 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
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2002 return true; |
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2003 } |
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2004 |
0 | 2005 #else |
2006 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
2007 // Longs cannot be passed in O regs, because O regs become I regs | |
2008 // after a 'save' and I regs get their high bits chopped off on | |
2009 // interrupt. | |
2010 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
2011 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
2012 #endif | |
2013 // A few float args in registers | |
2014 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
2015 | |
2016 return false; | |
2017 } | |
2018 | |
2019 bool Matcher::is_spillable_arg( int reg ) { | |
2020 return can_be_java_arg(reg); | |
2021 } | |
2022 | |
1914
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2023 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
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2024 // Use hardware SDIVX instruction when it is |
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2025 // faster than a code which use multiply. |
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2026 return VM_Version::has_fast_idiv(); |
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2027 } |
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2028 |
0 | 2029 // Register for DIVI projection of divmodI |
2030 RegMask Matcher::divI_proj_mask() { | |
2031 ShouldNotReachHere(); | |
2032 return RegMask(); | |
2033 } | |
2034 | |
2035 // Register for MODI projection of divmodI | |
2036 RegMask Matcher::modI_proj_mask() { | |
2037 ShouldNotReachHere(); | |
2038 return RegMask(); | |
2039 } | |
2040 | |
2041 // Register for DIVL projection of divmodL | |
2042 RegMask Matcher::divL_proj_mask() { | |
2043 ShouldNotReachHere(); | |
2044 return RegMask(); | |
2045 } | |
2046 | |
2047 // Register for MODL projection of divmodL | |
2048 RegMask Matcher::modL_proj_mask() { | |
2049 ShouldNotReachHere(); | |
2050 return RegMask(); | |
2051 } | |
2052 | |
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2053 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
4121
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2054 return L7_REGP_mask(); |
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2055 } |
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2056 |
0 | 2057 %} |
2058 | |
2059 | |
2060 // The intptr_t operand types, defined by textual substitution. | |
2061 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
2062 #ifdef _LP64 | |
824 | 2063 #define immX immL |
2064 #define immX13 immL13 | |
2065 #define immX13m7 immL13m7 | |
2066 #define iRegX iRegL | |
2067 #define g1RegX g1RegL | |
0 | 2068 #else |
824 | 2069 #define immX immI |
2070 #define immX13 immI13 | |
2071 #define immX13m7 immI13m7 | |
2072 #define iRegX iRegI | |
2073 #define g1RegX g1RegI | |
0 | 2074 #endif |
2075 | |
2076 //----------ENCODING BLOCK----------------------------------------------------- | |
2077 // This block specifies the encoding classes used by the compiler to output | |
2078 // byte streams. Encoding classes are parameterized macros used by | |
2079 // Machine Instruction Nodes in order to generate the bit encoding of the | |
2080 // instruction. Operands specify their base encoding interface with the | |
2081 // interface keyword. There are currently supported four interfaces, | |
2082 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
2083 // operand to generate a function which returns its register number when | |
2084 // queried. CONST_INTER causes an operand to generate a function which | |
2085 // returns the value of the constant when queried. MEMORY_INTER causes an | |
2086 // operand to generate four functions which return the Base Register, the | |
2087 // Index Register, the Scale Value, and the Offset Value of the operand when | |
2088 // queried. COND_INTER causes an operand to generate six functions which | |
2089 // return the encoding code (ie - encoding bits for the instruction) | |
2090 // associated with each basic boolean condition for a conditional instruction. | |
2091 // | |
2092 // Instructions specify two basic values for encoding. Again, a function | |
2093 // is available to check if the constant displacement is an oop. They use the | |
2094 // ins_encode keyword to specify their encoding classes (which must be | |
2095 // a sequence of enc_class names, and their parameters, specified in | |
2096 // the encoding block), and they use the | |
2097 // opcode keyword to specify, in order, their primary, secondary, and | |
2098 // tertiary opcode. Only the opcode sections which a particular instruction | |
2099 // needs for encoding need to be specified. | |
2100 encode %{ | |
2101 enc_class enc_untested %{ | |
2102 #ifdef ASSERT | |
2103 MacroAssembler _masm(&cbuf); | |
2104 __ untested("encoding"); | |
2105 #endif | |
2106 %} | |
2107 | |
2108 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
2109 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
2110 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | |
2111 %} | |
2112 | |
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2113 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
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2114 emit_form3_mem_reg(cbuf, this, $primary, -1, |
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2115 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
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2116 %} |
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2117 |
0 | 2118 enc_class form3_mem_prefetch_read( memory mem ) %{ |
415
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2119 emit_form3_mem_reg(cbuf, this, $primary, -1, |
0 | 2120 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
2121 %} | |
2122 | |
2123 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
415
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2124 emit_form3_mem_reg(cbuf, this, $primary, -1, |
0 | 2125 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
2126 %} | |
2127 | |
2128 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
4114
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2129 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
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2130 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
0 | 2131 guarantee($mem$$index == R_G0_enc, "double index?"); |
415
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2132 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
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2133 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
0 | 2134 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
2135 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
2136 %} | |
2137 | |
2138 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
4114
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2139 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
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2140 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
0 | 2141 guarantee($mem$$index == R_G0_enc, "double index?"); |
2142 // Load long with 2 instructions | |
415
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2143 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
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2144 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
0 | 2145 %} |
2146 | |
2147 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
2148 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
2149 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
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2150 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
0 | 2151 %} |
2152 | |
2153 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
2154 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2155 if( $rs2$$reg != $rd$$reg ) | |
2156 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
2157 %} | |
2158 | |
2159 // Target lo half of long | |
2160 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
2161 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2162 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
2163 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
2164 %} | |
2165 | |
2166 // Source lo half of long | |
2167 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
2168 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2169 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
2170 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
2171 %} | |
2172 | |
2173 // Target hi half of long | |
2174 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
2175 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
2176 %} | |
2177 | |
2178 // Source lo half of long, and leave it sign extended. | |
2179 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
2180 // Sign extend low half | |
2181 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
2182 %} | |
2183 | |
2184 // Source hi half of long, and leave it sign extended. | |
2185 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
2186 // Shift high half to low half | |
2187 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
2188 %} | |
2189 | |
2190 // Source hi half of long | |
2191 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
2192 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2193 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
2194 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
2195 %} | |
2196 | |
2197 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
2198 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
2199 %} | |
2200 | |
2201 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
2202 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
2203 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
2204 %} | |
2205 | |
2206 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
2207 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
2208 // clear if nothing else is happening | |
2209 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
2210 // blt,a,pn done | |
2211 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
2212 // mov dst,-1 in delay slot | |
2213 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2214 %} | |
2215 | |
2216 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
2217 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
2218 %} | |
2219 | |
2220 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
2221 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
2222 %} | |
2223 | |
2224 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
2225 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
2226 %} | |
2227 | |
2228 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
2229 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
2230 %} | |
2231 | |
2232 enc_class move_return_pc_to_o1() %{ | |
2233 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
2234 %} | |
2235 | |
2236 #ifdef _LP64 | |
2237 /* %%% merge with enc_to_bool */ | |
2238 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
2239 MacroAssembler _masm(&cbuf); | |
2240 | |
2241 Register src_reg = reg_to_register_object($src$$reg); | |
2242 Register dst_reg = reg_to_register_object($dst$$reg); | |
2243 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
2244 %} | |
2245 #endif | |
2246 | |
2247 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
2248 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
2249 MacroAssembler _masm(&cbuf); | |
2250 | |
2251 Register p_reg = reg_to_register_object($p$$reg); | |
2252 Register q_reg = reg_to_register_object($q$$reg); | |
2253 Register y_reg = reg_to_register_object($y$$reg); | |
2254 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
2255 | |
2256 __ subcc( p_reg, q_reg, p_reg ); | |
2257 __ add ( p_reg, y_reg, tmp_reg ); | |
2258 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
2259 %} | |
2260 | |
2261 enc_class form_d2i_helper(regD src, regF dst) %{ | |
2262 // fcmp %fcc0,$src,$src | |
2263 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2264 // branch %fcc0 not-nan, predict taken | |
2265 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2266 // fdtoi $src,$dst | |
2267 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
2268 // fitos $dst,$dst (if nan) | |
2269 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2270 // clear $dst (if nan) | |
2271 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2272 // carry on here... | |
2273 %} | |
2274 | |
2275 enc_class form_d2l_helper(regD src, regD dst) %{ | |
2276 // fcmp %fcc0,$src,$src check for NAN | |
2277 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2278 // branch %fcc0 not-nan, predict taken | |
2279 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2280 // fdtox $src,$dst convert in delay slot | |
2281 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
2282 // fxtod $dst,$dst (if nan) | |
2283 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2284 // clear $dst (if nan) | |
2285 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2286 // carry on here... | |
2287 %} | |
2288 | |
2289 enc_class form_f2i_helper(regF src, regF dst) %{ | |
2290 // fcmps %fcc0,$src,$src | |
2291 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2292 // branch %fcc0 not-nan, predict taken | |
2293 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2294 // fstoi $src,$dst | |
2295 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
2296 // fitos $dst,$dst (if nan) | |
2297 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2298 // clear $dst (if nan) | |
2299 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2300 // carry on here... | |
2301 %} | |
2302 | |
2303 enc_class form_f2l_helper(regF src, regD dst) %{ | |
2304 // fcmps %fcc0,$src,$src | |
2305 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2306 // branch %fcc0 not-nan, predict taken | |
2307 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2308 // fstox $src,$dst | |
2309 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
2310 // fxtod $dst,$dst (if nan) | |
2311 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2312 // clear $dst (if nan) | |
2313 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2314 // carry on here... | |
2315 %} | |
2316 | |
2317 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2318 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2319 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2320 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2321 | |
2322 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2323 | |
2324 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2325 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2326 | |
2327 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
2328 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2329 %} | |
2330 | |
2331 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
2332 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2333 %} | |
2334 | |
2335 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
2336 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2337 %} | |
2338 | |
2339 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
2340 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2341 %} | |
2342 | |
2343 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
2344 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
2345 %} | |
2346 | |
2347 // Encloding class for traceable jumps | |
2348 enc_class form_jmpl(g3RegP dest) %{ | |
2349 emit_jmpl(cbuf, $dest$$reg); | |
2350 %} | |
2351 | |
2352 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
2353 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
2354 %} | |
2355 | |
2356 enc_class form2_nop() %{ | |
2357 emit_nop(cbuf); | |
2358 %} | |
2359 | |
2360 enc_class form2_illtrap() %{ | |
2361 emit_illtrap(cbuf); | |
2362 %} | |
2363 | |
2364 | |
2365 // Compare longs and convert into -1, 0, 1. | |
2366 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
2367 // CMP $src1,$src2 | |
2368 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
2369 // blt,a,pn done | |
2370 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
2371 // mov dst,-1 in delay slot | |
2372 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2373 // bgt,a,pn done | |
2374 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
2375 // mov dst,1 in delay slot | |
2376 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
2377 // CLR $dst | |
2378 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
2379 %} | |
2380 | |
2381 enc_class enc_PartialSubtypeCheck() %{ | |
2382 MacroAssembler _masm(&cbuf); | |
2383 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
2384 __ delayed()->nop(); | |
2385 %} | |
2386 | |
3839 | 2387 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ |
0 | 2388 MacroAssembler _masm(&cbuf); |
3839 | 2389 Label* L = $labl$$label; |
0 | 2390 Assembler::Predict predict_taken = |
3839 | 2391 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
2392 | |
2393 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
0 | 2394 __ delayed()->nop(); |
2395 %} | |
2396 | |
3839 | 2397 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ |
0 | 2398 MacroAssembler _masm(&cbuf); |
3839 | 2399 Label* L = $labl$$label; |
0 | 2400 Assembler::Predict predict_taken = |
3839 | 2401 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
2402 | |
2403 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); | |
0 | 2404 __ delayed()->nop(); |
2405 %} | |
2406 | |
2407 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
2408 int op = (Assembler::arith_op << 30) | | |
2409 ($dst$$reg << 25) | | |
2410 (Assembler::movcc_op3 << 19) | | |
2411 (1 << 18) | // cc2 bit for 'icc' | |
2412 ($cmp$$cmpcode << 14) | | |
2413 (0 << 13) | // select register move | |
2414 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
2415 ($src$$reg << 0); | |
1748 | 2416 cbuf.insts()->emit_int32(op); |
0 | 2417 %} |
2418 | |
2419 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
2420 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2421 int op = (Assembler::arith_op << 30) | | |
2422 ($dst$$reg << 25) | | |
2423 (Assembler::movcc_op3 << 19) | | |
2424 (1 << 18) | // cc2 bit for 'icc' | |
2425 ($cmp$$cmpcode << 14) | | |
2426 (1 << 13) | // select immediate move | |
2427 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
2428 (simm11 << 0); | |
1748 | 2429 cbuf.insts()->emit_int32(op); |
0 | 2430 %} |
2431 | |
2432 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
2433 int op = (Assembler::arith_op << 30) | | |
2434 ($dst$$reg << 25) | | |
2435 (Assembler::movcc_op3 << 19) | | |
2436 (0 << 18) | // cc2 bit for 'fccX' | |
2437 ($cmp$$cmpcode << 14) | | |
2438 (0 << 13) | // select register move | |
2439 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2440 ($src$$reg << 0); | |
1748 | 2441 cbuf.insts()->emit_int32(op); |
0 | 2442 %} |
2443 | |
2444 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
2445 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2446 int op = (Assembler::arith_op << 30) | | |
2447 ($dst$$reg << 25) | | |
2448 (Assembler::movcc_op3 << 19) | | |
2449 (0 << 18) | // cc2 bit for 'fccX' | |
2450 ($cmp$$cmpcode << 14) | | |
2451 (1 << 13) | // select immediate move | |
2452 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2453 (simm11 << 0); | |
1748 | 2454 cbuf.insts()->emit_int32(op); |
0 | 2455 %} |
2456 | |
2457 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
2458 int op = (Assembler::arith_op << 30) | | |
2459 ($dst$$reg << 25) | | |
2460 (Assembler::fpop2_op3 << 19) | | |
2461 (0 << 18) | | |
2462 ($cmp$$cmpcode << 14) | | |
2463 (1 << 13) | // select register move | |
2464 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
2465 ($primary << 5) | // select single, double or quad | |
2466 ($src$$reg << 0); | |
1748 | 2467 cbuf.insts()->emit_int32(op); |
0 | 2468 %} |
2469 | |
2470 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
2471 int op = (Assembler::arith_op << 30) | | |
2472 ($dst$$reg << 25) | | |
2473 (Assembler::fpop2_op3 << 19) | | |
2474 (0 << 18) | | |
2475 ($cmp$$cmpcode << 14) | | |
2476 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
2477 ($primary << 5) | // select single, double or quad | |
2478 ($src$$reg << 0); | |
1748 | 2479 cbuf.insts()->emit_int32(op); |
0 | 2480 %} |
2481 | |
2482 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
2483 // the condition comes from opcode-field instead of an argument. | |
2484 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
2485 int op = (Assembler::arith_op << 30) | | |
2486 ($dst$$reg << 25) | | |
2487 (Assembler::movcc_op3 << 19) | | |
2488 (1 << 18) | // cc2 bit for 'icc' | |
2489 ($primary << 14) | | |
2490 (0 << 13) | // select register move | |
2491 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2492 ($src$$reg << 0); | |
1748 | 2493 cbuf.insts()->emit_int32(op); |
0 | 2494 %} |
2495 | |
2496 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
2497 int op = (Assembler::arith_op << 30) | | |
2498 ($dst$$reg << 25) | | |
2499 (Assembler::movcc_op3 << 19) | | |
2500 (6 << 16) | // cc2 bit for 'xcc' | |
2501 ($primary << 14) | | |
2502 (0 << 13) | // select register move | |
2503 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2504 ($src$$reg << 0); | |
1748 | 2505 cbuf.insts()->emit_int32(op); |
0 | 2506 %} |
2507 | |
2508 enc_class Set13( immI13 src, iRegI rd ) %{ | |
2509 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
2510 %} | |
2511 | |
2512 enc_class SetHi22( immI src, iRegI rd ) %{ | |
2513 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
2514 %} | |
2515 | |
2516 enc_class Set32( immI src, iRegI rd ) %{ | |
2517 MacroAssembler _masm(&cbuf); | |
2518 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
2519 %} | |
2520 | |
2521 enc_class call_epilog %{ | |
2522 if( VerifyStackAtCalls ) { | |
2523 MacroAssembler _masm(&cbuf); | |
2524 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
2525 Register temp_reg = G3; | |
2526 __ add(SP, framesize, temp_reg); | |
2527 __ cmp(temp_reg, FP); | |
2528 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
2529 } | |
2530 %} | |
2531 | |
2532 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
2533 // to G1 so the register allocator will not have to deal with the misaligned register | |
2534 // pair. | |
2535 enc_class adjust_long_from_native_call %{ | |
2536 #ifndef _LP64 | |
2537 if (returns_long()) { | |
2538 // sllx O0,32,O0 | |
2539 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
2540 // srl O1,0,O1 | |
2541 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
2542 // or O0,O1,G1 | |
2543 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
2544 } | |
2545 #endif | |
2546 %} | |
2547 | |
2548 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
2549 // CALL directly to the runtime | |
2550 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
2551 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
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2552 /*preserve_g2=*/true); |
0 | 2553 %} |
2554 | |
1567 | 2555 enc_class preserve_SP %{ |
2556 MacroAssembler _masm(&cbuf); | |
2557 __ mov(SP, L7_mh_SP_save); | |
2558 %} | |
2559 | |
2560 enc_class restore_SP %{ | |
2561 MacroAssembler _masm(&cbuf); | |
2562 __ mov(L7_mh_SP_save, SP); | |
2563 %} | |
2564 | |
0 | 2565 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
2566 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
2567 // who we intended to call. | |
2568 if ( !_method ) { | |
2569 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); | |
2570 } else if (_optimized_virtual) { | |
2571 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
2572 } else { | |
2573 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
2574 } | |
2575 if( _method ) { // Emit stub for static call | |
2576 emit_java_to_interp(cbuf); | |
2577 } | |
2578 %} | |
2579 | |
2580 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
2581 MacroAssembler _masm(&cbuf); | |
2582 __ set_inst_mark(); | |
2583 int vtable_index = this->_vtable_index; | |
2584 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
2585 if (vtable_index < 0) { | |
2586 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
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2587 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
0 | 2588 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); |
2589 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
2590 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
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2591 __ ic_call((address)$meth$$method); |
0 | 2592 } else { |
2593 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
2594 // Just go thru the vtable | |
2595 // get receiver klass (receiver already checked for non-null) | |
2596 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
2597 int off = __ offset(); | |
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2598 __ load_klass(O0, G3_scratch); |
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2599 int klass_load_size; |
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2600 if (UseCompressedOops && UseCompressedKlassPointers) { |
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2601 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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2602 if (Universe::narrow_oop_base() == NULL) |
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2603 klass_load_size = 2*BytesPerInstWord; |
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2604 else |
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2605 klass_load_size = 3*BytesPerInstWord; |
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2606 } else { |
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2607 klass_load_size = 1*BytesPerInstWord; |
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2608 } |
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2609 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
0 | 2610 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); |
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2611 if (Assembler::is_simm13(v_off)) { |
0 | 2612 __ ld_ptr(G3, v_off, G5_method); |
2613 } else { | |
2614 // Generate 2 instructions | |
2615 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
2616 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
2617 // ld_ptr, set_hi, set | |
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2618 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
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2619 "Unexpected instruction size(s)"); |
0 | 2620 __ ld_ptr(G3, G5_method, G5_method); |
2621 } | |
2622 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
2623 // However it may very well end up in handle_wrong_method if the | |
2624 // method is abstract for the particular class. | |
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2625 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch); |
0 | 2626 // jump to target (either compiled code or c2iadapter) |
2627 __ jmpl(G3_scratch, G0, O7); | |
2628 __ delayed()->nop(); | |
2629 } | |
2630 %} | |
2631 | |
2632 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
2633 MacroAssembler _masm(&cbuf); | |
2634 | |
2635 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
2636 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
2637 // we might be calling a C2I adapter which needs it. | |
2638 | |
2639 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
2640 // Load nmethod | |
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2641 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg); |
0 | 2642 |
2643 // CALL to compiled java, indirect the contents of G3 | |
2644 __ set_inst_mark(); | |
2645 __ callr(temp_reg, G0); | |
2646 __ delayed()->nop(); | |
2647 %} | |
2648 | |
2649 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
2650 MacroAssembler _masm(&cbuf); | |
2651 Register Rdividend = reg_to_register_object($src1$$reg); | |
2652 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2653 Register Rresult = reg_to_register_object($dst$$reg); | |
2654 | |
2655 __ sra(Rdivisor, 0, Rdivisor); | |
2656 __ sra(Rdividend, 0, Rdividend); | |
2657 __ sdivx(Rdividend, Rdivisor, Rresult); | |
2658 %} | |
2659 | |
2660 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
2661 MacroAssembler _masm(&cbuf); | |
2662 | |
2663 Register Rdividend = reg_to_register_object($src1$$reg); | |
2664 int divisor = $imm$$constant; | |
2665 Register Rresult = reg_to_register_object($dst$$reg); | |
2666 | |
2667 __ sra(Rdividend, 0, Rdividend); | |
2668 __ sdivx(Rdividend, divisor, Rresult); | |
2669 %} | |
2670 | |
2671 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
2672 MacroAssembler _masm(&cbuf); | |
2673 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
2674 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
2675 Register Rdst = reg_to_register_object($dst$$reg); | |
2676 | |
2677 __ sra( Rsrc1, 0, Rsrc1 ); | |
2678 __ sra( Rsrc2, 0, Rsrc2 ); | |
2679 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
2680 __ srlx( Rdst, 32, Rdst ); | |
2681 %} | |
2682 | |
2683 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
2684 MacroAssembler _masm(&cbuf); | |
2685 Register Rdividend = reg_to_register_object($src1$$reg); | |
2686 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2687 Register Rresult = reg_to_register_object($dst$$reg); | |
2688 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2689 | |
2690 assert(Rdividend != Rscratch, ""); | |
2691 assert(Rdivisor != Rscratch, ""); | |
2692 | |
2693 __ sra(Rdividend, 0, Rdividend); | |
2694 __ sra(Rdivisor, 0, Rdivisor); | |
2695 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
2696 __ mulx(Rscratch, Rdivisor, Rscratch); | |
2697 __ sub(Rdividend, Rscratch, Rresult); | |
2698 %} | |
2699 | |
2700 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
2701 MacroAssembler _masm(&cbuf); | |
2702 | |
2703 Register Rdividend = reg_to_register_object($src1$$reg); | |
2704 int divisor = $imm$$constant; | |
2705 Register Rresult = reg_to_register_object($dst$$reg); | |
2706 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2707 | |
2708 assert(Rdividend != Rscratch, ""); | |
2709 | |
2710 __ sra(Rdividend, 0, Rdividend); | |
2711 __ sdivx(Rdividend, divisor, Rscratch); | |
2712 __ mulx(Rscratch, divisor, Rscratch); | |
2713 __ sub(Rdividend, Rscratch, Rresult); | |
2714 %} | |
2715 | |
2716 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
2717 MacroAssembler _masm(&cbuf); | |
2718 | |
2719 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2720 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2721 | |
2722 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
2723 %} | |
2724 | |
2725 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
2726 MacroAssembler _masm(&cbuf); | |
2727 | |
2728 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2729 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2730 | |
2731 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
2732 %} | |
2733 | |
2734 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
2735 MacroAssembler _masm(&cbuf); | |
2736 | |
2737 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2738 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2739 | |
2740 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
2741 %} | |
2742 | |
2743 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
2744 MacroAssembler _masm(&cbuf); | |
2745 | |
2746 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2747 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2748 | |
2749 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
2750 %} | |
2751 | |
2752 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
2753 MacroAssembler _masm(&cbuf); | |
2754 | |
2755 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2756 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2757 | |
2758 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
2759 %} | |
2760 | |
2761 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
2762 MacroAssembler _masm(&cbuf); | |
2763 | |
2764 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2765 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2766 | |
2767 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
2768 %} | |
2769 | |
2770 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
2771 MacroAssembler _masm(&cbuf); | |
2772 | |
2773 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2774 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2775 | |
2776 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
2777 %} | |
2778 | |
2779 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2780 MacroAssembler _masm(&cbuf); | |
2781 | |
2782 Register Roop = reg_to_register_object($oop$$reg); | |
2783 Register Rbox = reg_to_register_object($box$$reg); | |
2784 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2785 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2786 | |
2787 assert(Roop != Rscratch, ""); | |
2788 assert(Roop != Rmark, ""); | |
2789 assert(Rbox != Rscratch, ""); | |
2790 assert(Rbox != Rmark, ""); | |
2791 | |
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2792 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2793 %} |
2794 | |
2795 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2796 MacroAssembler _masm(&cbuf); | |
2797 | |
2798 Register Roop = reg_to_register_object($oop$$reg); | |
2799 Register Rbox = reg_to_register_object($box$$reg); | |
2800 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2801 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2802 | |
2803 assert(Roop != Rscratch, ""); | |
2804 assert(Roop != Rmark, ""); | |
2805 assert(Rbox != Rscratch, ""); | |
2806 assert(Rbox != Rmark, ""); | |
2807 | |
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2808 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2809 %} |
2810 | |
2811 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
2812 MacroAssembler _masm(&cbuf); | |
2813 Register Rmem = reg_to_register_object($mem$$reg); | |
2814 Register Rold = reg_to_register_object($old$$reg); | |
2815 Register Rnew = reg_to_register_object($new$$reg); | |
2816 | |
2817 // casx_under_lock picks 1 of 3 encodings: | |
2818 // For 32-bit pointers you get a 32-bit CAS | |
2819 // For 64-bit pointers you get a 64-bit CASX | |
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2820 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
0 | 2821 __ cmp( Rold, Rnew ); |
2822 %} | |
2823 | |
2824 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
2825 Register Rmem = reg_to_register_object($mem$$reg); | |
2826 Register Rold = reg_to_register_object($old$$reg); | |
2827 Register Rnew = reg_to_register_object($new$$reg); | |
2828 | |
2829 MacroAssembler _masm(&cbuf); | |
2830 __ mov(Rnew, O7); | |
2831 __ casx(Rmem, Rold, O7); | |
2832 __ cmp( Rold, O7 ); | |
2833 %} | |
2834 | |
2835 // raw int cas, used for compareAndSwap | |
2836 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
2837 Register Rmem = reg_to_register_object($mem$$reg); | |
2838 Register Rold = reg_to_register_object($old$$reg); | |
2839 Register Rnew = reg_to_register_object($new$$reg); | |
2840 | |
2841 MacroAssembler _masm(&cbuf); | |
2842 __ mov(Rnew, O7); | |
2843 __ cas(Rmem, Rold, O7); | |
2844 __ cmp( Rold, O7 ); | |
2845 %} | |
2846 | |
2847 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
2848 Register Rres = reg_to_register_object($res$$reg); | |
2849 | |
2850 MacroAssembler _masm(&cbuf); | |
2851 __ mov(1, Rres); | |
2852 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
2853 %} | |
2854 | |
2855 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
2856 Register Rres = reg_to_register_object($res$$reg); | |
2857 | |
2858 MacroAssembler _masm(&cbuf); | |
2859 __ mov(1, Rres); | |
2860 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
2861 %} | |
2862 | |
2863 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
2864 MacroAssembler _masm(&cbuf); | |
2865 Register Rdst = reg_to_register_object($dst$$reg); | |
2866 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
2867 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
2868 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
2869 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
2870 | |
2871 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
2872 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
2873 %} | |
2874 | |
2875 | |
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2876 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
0 | 2877 Label Ldone, Lloop; |
2878 MacroAssembler _masm(&cbuf); | |
2879 | |
2880 Register str1_reg = reg_to_register_object($str1$$reg); | |
2881 Register str2_reg = reg_to_register_object($str2$$reg); | |
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2882 Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
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2883 Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
0 | 2884 Register result_reg = reg_to_register_object($result$$reg); |
2885 | |
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2886 assert(result_reg != str1_reg && |
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2887 result_reg != str2_reg && |
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2888 result_reg != cnt1_reg && |
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2889 result_reg != cnt2_reg , |
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2890 "need different registers"); |
0 | 2891 |
2892 // Compute the minimum of the string lengths(str1_reg) and the | |
2893 // difference of the string lengths (stack) | |
2894 | |
2895 // See if the lengths are different, and calculate min in str1_reg. | |
2896 // Stash diff in O7 in case we need it for a tie-breaker. | |
2897 Label Lskip; | |
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2898 __ subcc(cnt1_reg, cnt2_reg, O7); |
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2899 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
0 | 2900 __ br(Assembler::greater, true, Assembler::pt, Lskip); |
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2901 // cnt2 is shorter, so use its count: |
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2902 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
0 | 2903 __ bind(Lskip); |
2904 | |
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2905 // reallocate cnt1_reg, cnt2_reg, result_reg |
0 | 2906 // Note: limit_reg holds the string length pre-scaled by 2 |
986
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2907 Register limit_reg = cnt1_reg; |
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2908 Register chr2_reg = cnt2_reg; |
0 | 2909 Register chr1_reg = result_reg; |
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2910 // str{12} are the base pointers |
0 | 2911 |
2912 // Is the minimum length zero? | |
2913 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
2914 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2915 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2916 | |
2917 // Load first characters | |
986
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2918 __ lduh(str1_reg, 0, chr1_reg); |
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2919 __ lduh(str2_reg, 0, chr2_reg); |
0 | 2920 |
2921 // Compare first characters | |
2922 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
2923 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2924 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2925 __ delayed()->nop(); | |
2926 | |
2927 { | |
2928 // Check after comparing first character to see if strings are equivalent | |
2929 Label LSkip2; | |
2930 // Check if the strings start at same location | |
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2931 __ cmp(str1_reg, str2_reg); |
0 | 2932 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
2933 __ delayed()->nop(); | |
2934 | |
2935 // Check if the length difference is zero (in O7) | |
2936 __ cmp(G0, O7); | |
2937 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2938 __ delayed()->mov(G0, result_reg); // result is zero | |
2939 | |
2940 // Strings might not be equal | |
2941 __ bind(LSkip2); | |
2942 } | |
2943 | |
2944 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); | |
2945 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2946 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2947 | |
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2948 // Shift str1_reg and str2_reg to the end of the arrays, negate limit |
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2949 __ add(str1_reg, limit_reg, str1_reg); |
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2950 __ add(str2_reg, limit_reg, str2_reg); |
0 | 2951 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
2952 | |
2953 // Compare the rest of the characters | |
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2954 __ lduh(str1_reg, limit_reg, chr1_reg); |
0 | 2955 __ bind(Lloop); |
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2956 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
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2957 __ lduh(str2_reg, limit_reg, chr2_reg); |
0 | 2958 __ subcc(chr1_reg, chr2_reg, chr1_reg); |
2959 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2960 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2961 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
2962 // annul LDUH if branch is not taken to prevent access past end of string | |
2963 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
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2964 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
0 | 2965 |
2966 // If strings are equal up to min length, return the length difference. | |
2967 __ mov(O7, result_reg); | |
2968 | |
2969 // Otherwise, return the difference between the first mismatched chars. | |
2970 __ bind(Ldone); | |
2971 %} | |
2972 | |
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2973 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
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2974 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
681 | 2975 MacroAssembler _masm(&cbuf); |
2976 | |
2977 Register str1_reg = reg_to_register_object($str1$$reg); | |
2978 Register str2_reg = reg_to_register_object($str2$$reg); | |
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2979 Register cnt_reg = reg_to_register_object($cnt$$reg); |
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2980 Register tmp1_reg = O7; |
681 | 2981 Register result_reg = reg_to_register_object($result$$reg); |
2982 | |
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2983 assert(result_reg != str1_reg && |
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2984 result_reg != str2_reg && |
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2985 result_reg != cnt_reg && |
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2986 result_reg != tmp1_reg , |
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2987 "need different registers"); |
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2988 |
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2989 __ cmp(str1_reg, str2_reg); //same char[] ? |
681 | 2990 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
2991 __ delayed()->add(G0, 1, result_reg); | |
2992 | |
3839 | 2993 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn); |
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2994 __ delayed()->add(G0, 1, result_reg); // count == 0 |
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2995 |
681 | 2996 //rename registers |
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2997 Register limit_reg = cnt_reg; |
681 | 2998 Register chr1_reg = result_reg; |
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2999 Register chr2_reg = tmp1_reg; |
681 | 3000 |
3001 //check for alignment and position the pointers to the ends | |
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3002 __ or3(str1_reg, str2_reg, chr1_reg); |
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3003 __ andcc(chr1_reg, 0x3, chr1_reg); |
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3004 // notZero means at least one not 4-byte aligned. |
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3005 // We could optimize the case when both arrays are not aligned |
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3006 // but it is not frequent case and it requires additional checks. |
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3007 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
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3008 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
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3009 |
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3010 // Compare char[] arrays aligned to 4 bytes. |
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3011 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
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3012 chr1_reg, chr2_reg, Ldone); |
3839 | 3013 __ ba(Ldone); |
681 | 3014 __ delayed()->add(G0, 1, result_reg); |
3015 | |
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3016 // char by char compare |
681 | 3017 __ bind(Lchar); |
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3018 __ add(str1_reg, limit_reg, str1_reg); |
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3019 __ add(str2_reg, limit_reg, str2_reg); |
681 | 3020 __ neg(limit_reg); //negate count |
3021 | |
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3022 __ lduh(str1_reg, limit_reg, chr1_reg); |
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3023 // Lchar_loop |
681 | 3024 __ bind(Lchar_loop); |
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3025 __ lduh(str2_reg, limit_reg, chr2_reg); |
681 | 3026 __ cmp(chr1_reg, chr2_reg); |
3027 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
3028 __ delayed()->mov(G0, result_reg); //not equal | |
3029 __ inccc(limit_reg, sizeof(jchar)); | |
3030 // annul LDUH if branch is not taken to prevent access past end of string | |
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3031 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
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3032 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
681 | 3033 |
3034 __ add(G0, 1, result_reg); //equal | |
3035 | |
3036 __ bind(Ldone); | |
3037 %} | |
3038 | |
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3039 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
681 | 3040 Label Lvector, Ldone, Lloop; |
3041 MacroAssembler _masm(&cbuf); | |
3042 | |
3043 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
3044 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
3045 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
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3046 Register tmp2_reg = O7; |
681 | 3047 Register result_reg = reg_to_register_object($result$$reg); |
3048 | |
3049 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
3050 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
3051 | |
3052 // return true if the same array | |
3053 __ cmp(ary1_reg, ary2_reg); | |
1016 | 3054 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
681 | 3055 __ delayed()->add(G0, 1, result_reg); // equal |
3056 | |
3057 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
3058 __ delayed()->mov(G0, result_reg); // not equal | |
3059 | |
3060 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
3061 __ delayed()->mov(G0, result_reg); // not equal | |
3062 | |
3063 //load the lengths of arrays | |
727 | 3064 __ ld(Address(ary1_reg, length_offset), tmp1_reg); |
3065 __ ld(Address(ary2_reg, length_offset), tmp2_reg); | |
681 | 3066 |
3067 // return false if the two arrays are not equal length | |
3068 __ cmp(tmp1_reg, tmp2_reg); | |
3069 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
3070 __ delayed()->mov(G0, result_reg); // not equal | |
3071 | |
3839 | 3072 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn); |
681 | 3073 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
3074 | |
3075 // load array addresses | |
3076 __ add(ary1_reg, base_offset, ary1_reg); | |
3077 __ add(ary2_reg, base_offset, ary2_reg); | |
3078 | |
3079 // renaming registers | |
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3080 Register chr1_reg = result_reg; // for characters in ary1 |
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3081 Register chr2_reg = tmp2_reg; // for characters in ary2 |
681 | 3082 Register limit_reg = tmp1_reg; // length |
3083 | |
3084 // set byte count | |
3085 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
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3086 |
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3087 // Compare char[] arrays aligned to 4 bytes. |
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3088 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
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3089 chr1_reg, chr2_reg, Ldone); |
681 | 3090 __ add(G0, 1, result_reg); // equals |
3091 | |
3092 __ bind(Ldone); | |
3093 %} | |
3094 | |
0 | 3095 enc_class enc_rethrow() %{ |
1748 | 3096 cbuf.set_insts_mark(); |
0 | 3097 Register temp_reg = G3; |
727 | 3098 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
0 | 3099 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
3100 MacroAssembler _masm(&cbuf); | |
3101 #ifdef ASSERT | |
3102 __ save_frame(0); | |
727 | 3103 AddressLiteral last_rethrow_addrlit(&last_rethrow); |
3104 __ sethi(last_rethrow_addrlit, L1); | |
3105 Address addr(L1, last_rethrow_addrlit.low10()); | |
0 | 3106 __ get_pc(L2); |
3107 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to | |
727 | 3108 __ st_ptr(L2, addr); |
0 | 3109 __ restore(); |
3110 #endif | |
727 | 3111 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
0 | 3112 __ delayed()->nop(); |
3113 %} | |
3114 | |
3115 enc_class emit_mem_nop() %{ | |
3116 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
1748 | 3117 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); |
0 | 3118 %} |
3119 | |
3120 enc_class emit_fadd_nop() %{ | |
3121 // Generates the instruction FMOVS f31,f31 | |
1748 | 3122 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); |
0 | 3123 %} |
3124 | |
3125 enc_class emit_br_nop() %{ | |
3126 // Generates the instruction BPN,PN . | |
1748 | 3127 cbuf.insts()->emit_int32((unsigned int) 0x00400000); |
0 | 3128 %} |
3129 | |
3130 enc_class enc_membar_acquire %{ | |
3131 MacroAssembler _masm(&cbuf); | |
3132 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
3133 %} | |
3134 | |
3135 enc_class enc_membar_release %{ | |
3136 MacroAssembler _masm(&cbuf); | |
3137 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
3138 %} | |
3139 | |
3140 enc_class enc_membar_volatile %{ | |
3141 MacroAssembler _masm(&cbuf); | |
3142 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
3143 %} | |
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3144 |
0 | 3145 %} |
3146 | |
3147 //----------FRAME-------------------------------------------------------------- | |
3148 // Definition of frame structure and management information. | |
3149 // | |
3150 // S T A C K L A Y O U T Allocators stack-slot number | |
3151 // | (to get allocators register number | |
3152 // G Owned by | | v add VMRegImpl::stack0) | |
3153 // r CALLER | | | |
3154 // o | +--------+ pad to even-align allocators stack-slot | |
3155 // w V | pad0 | numbers; owned by CALLER | |
3156 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
3157 // h ^ | in | 5 | |
3158 // | | args | 4 Holes in incoming args owned by SELF | |
3159 // | | | | 3 | |
3160 // | | +--------+ | |
3161 // V | | old out| Empty on Intel, window on Sparc | |
3162 // | old |preserve| Must be even aligned. | |
3163 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
3164 // | | in | 3 area for Intel ret address | |
3165 // Owned by |preserve| Empty on Sparc. | |
3166 // SELF +--------+ | |
3167 // | | pad2 | 2 pad to align old SP | |
3168 // | +--------+ 1 | |
3169 // | | locks | 0 | |
3170 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
3171 // | | pad1 | 11 pad to align new SP | |
3172 // | +--------+ | |
3173 // | | | 10 | |
3174 // | | spills | 9 spills | |
3175 // V | | 8 (pad0 slot for callee) | |
3176 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
3177 // ^ | out | 7 | |
3178 // | | args | 6 Holes in outgoing args owned by CALLEE | |
3179 // Owned by +--------+ | |
3180 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
3181 // | new |preserve| Must be even-aligned. | |
3182 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
3183 // | | | | |
3184 // | |
3185 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
3186 // known from SELF's arguments and the Java calling convention. | |
3187 // Region 6-7 is determined per call site. | |
3188 // Note 2: If the calling convention leaves holes in the incoming argument | |
3189 // area, those holes are owned by SELF. Holes in the outgoing area | |
3190 // are owned by the CALLEE. Holes should not be nessecary in the | |
3191 // incoming area, as the Java calling convention is completely under | |
3192 // the control of the AD file. Doubles can be sorted and packed to | |
3193 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
3194 // varargs C calling conventions. | |
3195 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
3196 // even aligned with pad0 as needed. | |
3197 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
3198 // region 6-11 is even aligned; it may be padded out more so that | |
3199 // the region from SP to FP meets the minimum stack alignment. | |
3200 | |
3201 frame %{ | |
3202 // What direction does stack grow in (assumed to be same for native & Java) | |
3203 stack_direction(TOWARDS_LOW); | |
3204 | |
3205 // These two registers define part of the calling convention | |
3206 // between compiled code and the interpreter. | |
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3207 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C |
0 | 3208 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter |
3209 | |
3210 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
3211 cisc_spilling_operand_name(indOffset); | |
3212 | |
3213 // Number of stack slots consumed by a Monitor enter | |
3214 #ifdef _LP64 | |
3215 sync_stack_slots(2); | |
3216 #else | |
3217 sync_stack_slots(1); | |
3218 #endif | |
3219 | |
3220 // Compiled code's Frame Pointer | |
3221 frame_pointer(R_SP); | |
3222 | |
3223 // Stack alignment requirement | |
3224 stack_alignment(StackAlignmentInBytes); | |
3225 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
3226 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
3227 | |
3228 // Number of stack slots between incoming argument block and the start of | |
3229 // a new frame. The PROLOG must add this many slots to the stack. The | |
3230 // EPILOG must remove this many slots. | |
3231 in_preserve_stack_slots(0); | |
3232 | |
3233 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
3234 // for calls to C. Supports the var-args backing area for register parms. | |
3235 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
3236 #ifdef _LP64 | |
3237 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
3238 varargs_C_out_slots_killed(12); | |
3239 #else | |
3240 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
3241 varargs_C_out_slots_killed( 7); | |
3242 #endif | |
3243 | |
3244 // The after-PROLOG location of the return address. Location of | |
3245 // return address specifies a type (REG or STACK) and a number | |
3246 // representing the register number (i.e. - use a register name) or | |
3247 // stack slot. | |
3248 return_addr(REG R_I7); // Ret Addr is in register I7 | |
3249 | |
3250 // Body of function which returns an OptoRegs array locating | |
3251 // arguments either in registers or in stack slots for calling | |
3252 // java | |
3253 calling_convention %{ | |
3254 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
3255 | |
3256 %} | |
3257 | |
3258 // Body of function which returns an OptoRegs array locating | |
3259 // arguments either in registers or in stack slots for callin | |
3260 // C. | |
3261 c_calling_convention %{ | |
3262 // This is obviously always outgoing | |
3263 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
3264 %} | |
3265 | |
3266 // Location of native (C/C++) and interpreter return values. This is specified to | |
3267 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
3268 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
3269 // to and from the register pairs is done by the appropriate call and epilog | |
3270 // opcodes. This simplifies the register allocator. | |
3271 c_return_value %{ | |
3272 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3273 #ifdef _LP64 | |
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3274 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3275 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3276 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3277 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3278 #else // !_LP64 |
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3279 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3280 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
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3281 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3282 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
0 | 3283 #endif |
3284 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3285 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3286 %} | |
3287 | |
3288 // Location of compiled Java return values. Same as C | |
3289 return_value %{ | |
3290 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3291 #ifdef _LP64 | |
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3292 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3293 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3294 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3295 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3296 #else // !_LP64 |
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3297 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3298 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
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3299 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3300 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
0 | 3301 #endif |
3302 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3303 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3304 %} | |
3305 | |
3306 %} | |
3307 | |
3308 | |
3309 //----------ATTRIBUTES--------------------------------------------------------- | |
3310 //----------Operand Attributes------------------------------------------------- | |
3311 op_attrib op_cost(1); // Required cost attribute | |
3312 | |
3313 //----------Instruction Attributes--------------------------------------------- | |
3314 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
3842 | 3315 ins_attrib ins_size(32); // Required size attribute (in bits) |
3851 | 3316 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back |
3842 | 3317 ins_attrib ins_short_branch(0); // Required flag: is this instruction a |
3318 // non-matching short branch variant of some | |
0 | 3319 // long branch? |
3320 | |
3321 //----------OPERANDS----------------------------------------------------------- | |
3322 // Operand definitions must precede instruction definitions for correct parsing | |
3323 // in the ADLC because operands constitute user defined types which are used in | |
3324 // instruction definitions. | |
3325 | |
3326 //----------Simple Operands---------------------------------------------------- | |
3327 // Immediate Operands | |
3328 // Integer Immediate: 32-bit | |
3329 operand immI() %{ | |
3330 match(ConI); | |
3331 | |
3332 op_cost(0); | |
3333 // formats are generated automatically for constants and base registers | |
3334 format %{ %} | |
3335 interface(CONST_INTER); | |
3336 %} | |
3337 | |
824 | 3338 // Integer Immediate: 8-bit |
3339 operand immI8() %{ | |
4114
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3340 predicate(Assembler::is_simm8(n->get_int())); |
824 | 3341 match(ConI); |
3342 op_cost(0); | |
3343 format %{ %} | |
3344 interface(CONST_INTER); | |
3345 %} | |
3346 | |
0 | 3347 // Integer Immediate: 13-bit |
3348 operand immI13() %{ | |
3349 predicate(Assembler::is_simm13(n->get_int())); | |
3350 match(ConI); | |
3351 op_cost(0); | |
3352 | |
3353 format %{ %} | |
3354 interface(CONST_INTER); | |
3355 %} | |
3356 | |
785 | 3357 // Integer Immediate: 13-bit minus 7 |
3358 operand immI13m7() %{ | |
3359 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); | |
3360 match(ConI); | |
3361 op_cost(0); | |
3362 | |
3363 format %{ %} | |
3364 interface(CONST_INTER); | |
3365 %} | |
3366 | |
824 | 3367 // Integer Immediate: 16-bit |
3368 operand immI16() %{ | |
4114
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3369 predicate(Assembler::is_simm16(n->get_int())); |
824 | 3370 match(ConI); |
3371 op_cost(0); | |
3372 format %{ %} | |
3373 interface(CONST_INTER); | |
3374 %} | |
3375 | |
0 | 3376 // Unsigned (positive) Integer Immediate: 13-bit |
3377 operand immU13() %{ | |
3378 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | |
3379 match(ConI); | |
3380 op_cost(0); | |
3381 | |
3382 format %{ %} | |
3383 interface(CONST_INTER); | |
3384 %} | |
3385 | |
3386 // Integer Immediate: 6-bit | |
3387 operand immU6() %{ | |
3388 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
3389 match(ConI); | |
3390 op_cost(0); | |
3391 format %{ %} | |
3392 interface(CONST_INTER); | |
3393 %} | |
3394 | |
3395 // Integer Immediate: 11-bit | |
3396 operand immI11() %{ | |
4114
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3397 predicate(Assembler::is_simm11(n->get_int())); |
0 | 3398 match(ConI); |
3399 op_cost(0); | |
3400 format %{ %} | |
3401 interface(CONST_INTER); | |
3402 %} | |
3403 | |
3851 | 3404 // Integer Immediate: 5-bit |
3405 operand immI5() %{ | |
4114
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3406 predicate(Assembler::is_simm5(n->get_int())); |
3851 | 3407 match(ConI); |
3408 op_cost(0); | |
3409 format %{ %} | |
3410 interface(CONST_INTER); | |
3411 %} | |
3412 | |
0 | 3413 // Integer Immediate: 0-bit |
3414 operand immI0() %{ | |
3415 predicate(n->get_int() == 0); | |
3416 match(ConI); | |
3417 op_cost(0); | |
3418 | |
3419 format %{ %} | |
3420 interface(CONST_INTER); | |
3421 %} | |
3422 | |
3423 // Integer Immediate: the value 10 | |
3424 operand immI10() %{ | |
3425 predicate(n->get_int() == 10); | |
3426 match(ConI); | |
3427 op_cost(0); | |
3428 | |
3429 format %{ %} | |
3430 interface(CONST_INTER); | |
3431 %} | |
3432 | |
3433 // Integer Immediate: the values 0-31 | |
3434 operand immU5() %{ | |
3435 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
3436 match(ConI); | |
3437 op_cost(0); | |
3438 | |
3439 format %{ %} | |
3440 interface(CONST_INTER); | |
3441 %} | |
3442 | |
3443 // Integer Immediate: the values 1-31 | |
3444 operand immI_1_31() %{ | |
3445 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
3446 match(ConI); | |
3447 op_cost(0); | |
3448 | |
3449 format %{ %} | |
3450 interface(CONST_INTER); | |
3451 %} | |
3452 | |
3453 // Integer Immediate: the values 32-63 | |
3454 operand immI_32_63() %{ | |
3455 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
3456 match(ConI); | |
3457 op_cost(0); | |
3458 | |
3459 format %{ %} | |
3460 interface(CONST_INTER); | |
3461 %} | |
3462 | |
785 | 3463 // Immediates for special shifts (sign extend) |
3464 | |
3465 // Integer Immediate: the value 16 | |
3466 operand immI_16() %{ | |
3467 predicate(n->get_int() == 16); | |
3468 match(ConI); | |
3469 op_cost(0); | |
3470 | |
3471 format %{ %} | |
3472 interface(CONST_INTER); | |
3473 %} | |
3474 | |
3475 // Integer Immediate: the value 24 | |
3476 operand immI_24() %{ | |
3477 predicate(n->get_int() == 24); | |
3478 match(ConI); | |
3479 op_cost(0); | |
3480 | |
3481 format %{ %} | |
3482 interface(CONST_INTER); | |
3483 %} | |
3484 | |
0 | 3485 // Integer Immediate: the value 255 |
3486 operand immI_255() %{ | |
3487 predicate( n->get_int() == 255 ); | |
3488 match(ConI); | |
3489 op_cost(0); | |
3490 | |
3491 format %{ %} | |
3492 interface(CONST_INTER); | |
3493 %} | |
3494 | |
785 | 3495 // Integer Immediate: the value 65535 |
3496 operand immI_65535() %{ | |
3497 predicate(n->get_int() == 65535); | |
3498 match(ConI); | |
3499 op_cost(0); | |
3500 | |
3501 format %{ %} | |
3502 interface(CONST_INTER); | |
3503 %} | |
3504 | |
0 | 3505 // Long Immediate: the value FF |
3506 operand immL_FF() %{ | |
3507 predicate( n->get_long() == 0xFFL ); | |
3508 match(ConL); | |
3509 op_cost(0); | |
3510 | |
3511 format %{ %} | |
3512 interface(CONST_INTER); | |
3513 %} | |
3514 | |
3515 // Long Immediate: the value FFFF | |
3516 operand immL_FFFF() %{ | |
3517 predicate( n->get_long() == 0xFFFFL ); | |
3518 match(ConL); | |
3519 op_cost(0); | |
3520 | |
3521 format %{ %} | |
3522 interface(CONST_INTER); | |
3523 %} | |
3524 | |
3525 // Pointer Immediate: 32 or 64-bit | |
3526 operand immP() %{ | |
3527 match(ConP); | |
3528 | |
3529 op_cost(5); | |
3530 // formats are generated automatically for constants and base registers | |
3531 format %{ %} | |
3532 interface(CONST_INTER); | |
3533 %} | |
3534 | |
2076
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3535 #ifdef _LP64 |
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3536 // Pointer Immediate: 64-bit |
2008 | 3537 operand immP_set() %{ |
2080 | 3538 predicate(!VM_Version::is_niagara_plus()); |
2008 | 3539 match(ConP); |
3540 | |
3541 op_cost(5); | |
3542 // formats are generated automatically for constants and base registers | |
3543 format %{ %} | |
3544 interface(CONST_INTER); | |
3545 %} | |
3546 | |
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3547 // Pointer Immediate: 64-bit |
2008 | 3548 // From Niagara2 processors on a load should be better than materializing. |
3549 operand immP_load() %{ | |
2080 | 3550 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); |
2008 | 3551 match(ConP); |
3552 | |
3553 op_cost(5); | |
3554 // formats are generated automatically for constants and base registers | |
3555 format %{ %} | |
3556 interface(CONST_INTER); | |
3557 %} | |
3558 | |
2076
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3559 // Pointer Immediate: 64-bit |
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3560 operand immP_no_oop_cheap() %{ |
2080 | 3561 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); |
2076
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3562 match(ConP); |
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3563 |
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3564 op_cost(5); |
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3565 // formats are generated automatically for constants and base registers |
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3566 format %{ %} |
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3567 interface(CONST_INTER); |
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3568 %} |
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3569 #endif |
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3570 |
0 | 3571 operand immP13() %{ |
3572 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
3573 match(ConP); | |
3574 op_cost(0); | |
3575 | |
3576 format %{ %} | |
3577 interface(CONST_INTER); | |
3578 %} | |
3579 | |
3580 operand immP0() %{ | |
3581 predicate(n->get_ptr() == 0); | |
3582 match(ConP); | |
3583 op_cost(0); | |
3584 | |
3585 format %{ %} | |
3586 interface(CONST_INTER); | |
3587 %} | |
3588 | |
3589 operand immP_poll() %{ | |
3590 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
3591 match(ConP); | |
3592 | |
3593 // formats are generated automatically for constants and base registers | |
3594 format %{ %} | |
3595 interface(CONST_INTER); | |
3596 %} | |
3597 | |
113
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3598 // Pointer Immediate |
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3599 operand immN() |
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3600 %{ |
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3601 match(ConN); |
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3602 |
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3603 op_cost(10); |
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3604 format %{ %} |
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3605 interface(CONST_INTER); |
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3606 %} |
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3607 |
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3608 // NULL Pointer Immediate |
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3609 operand immN0() |
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3610 %{ |
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3611 predicate(n->get_narrowcon() == 0); |
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3612 match(ConN); |
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3613 |
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3614 op_cost(0); |
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3615 format %{ %} |
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3616 interface(CONST_INTER); |
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3617 %} |
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3618 |
0 | 3619 operand immL() %{ |
3620 match(ConL); | |
3621 op_cost(40); | |
3622 // formats are generated automatically for constants and base registers | |
3623 format %{ %} | |
3624 interface(CONST_INTER); | |
3625 %} | |
3626 | |
3627 operand immL0() %{ | |
3628 predicate(n->get_long() == 0L); | |
3629 match(ConL); | |
3630 op_cost(0); | |
3631 // formats are generated automatically for constants and base registers | |
3632 format %{ %} | |
3633 interface(CONST_INTER); | |
3634 %} | |
3635 | |
3851 | 3636 // Integer Immediate: 5-bit |
3637 operand immL5() %{ | |
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3638 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long())); |
3851 | 3639 match(ConL); |
3640 op_cost(0); | |
3641 format %{ %} | |
3642 interface(CONST_INTER); | |
3643 %} | |
3644 | |
0 | 3645 // Long Immediate: 13-bit |
3646 operand immL13() %{ | |
3647 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
3648 match(ConL); | |
3649 op_cost(0); | |
3650 | |
3651 format %{ %} | |
3652 interface(CONST_INTER); | |
3653 %} | |
3654 | |
785 | 3655 // Long Immediate: 13-bit minus 7 |
3656 operand immL13m7() %{ | |
3657 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); | |
3658 match(ConL); | |
3659 op_cost(0); | |
3660 | |
3661 format %{ %} | |
3662 interface(CONST_INTER); | |
3663 %} | |
3664 | |
0 | 3665 // Long Immediate: low 32-bit mask |
3666 operand immL_32bits() %{ | |
3667 predicate(n->get_long() == 0xFFFFFFFFL); | |
3668 match(ConL); | |
3669 op_cost(0); | |
3670 | |
3671 format %{ %} | |
3672 interface(CONST_INTER); | |
3673 %} | |
3674 | |
2008 | 3675 // Long Immediate: cheap (materialize in <= 3 instructions) |
3676 operand immL_cheap() %{ | |
2080 | 3677 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); |
2008 | 3678 match(ConL); |
3679 op_cost(0); | |
3680 | |
3681 format %{ %} | |
3682 interface(CONST_INTER); | |
3683 %} | |
3684 | |
3685 // Long Immediate: expensive (materialize in > 3 instructions) | |
3686 operand immL_expensive() %{ | |
2080 | 3687 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3); |
2008 | 3688 match(ConL); |
3689 op_cost(0); | |
3690 | |
3691 format %{ %} | |
3692 interface(CONST_INTER); | |
3693 %} | |
3694 | |
0 | 3695 // Double Immediate |
3696 operand immD() %{ | |
3697 match(ConD); | |
3698 | |
3699 op_cost(40); | |
3700 format %{ %} | |
3701 interface(CONST_INTER); | |
3702 %} | |
3703 | |
3704 operand immD0() %{ | |
3705 #ifdef _LP64 | |
3706 // on 64-bit architectures this comparision is faster | |
3707 predicate(jlong_cast(n->getd()) == 0); | |
3708 #else | |
3709 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
3710 #endif | |
3711 match(ConD); | |
3712 | |
3713 op_cost(0); | |
3714 format %{ %} | |
3715 interface(CONST_INTER); | |
3716 %} | |
3717 | |
3718 // Float Immediate | |
3719 operand immF() %{ | |
3720 match(ConF); | |
3721 | |
3722 op_cost(20); | |
3723 format %{ %} | |
3724 interface(CONST_INTER); | |
3725 %} | |
3726 | |
3727 // Float Immediate: 0 | |
3728 operand immF0() %{ | |
3729 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
3730 match(ConF); | |
3731 | |
3732 op_cost(0); | |
3733 format %{ %} | |
3734 interface(CONST_INTER); | |
3735 %} | |
3736 | |
3737 // Integer Register Operands | |
3738 // Integer Register | |
3739 operand iRegI() %{ | |
3740 constraint(ALLOC_IN_RC(int_reg)); | |
3741 match(RegI); | |
3742 | |
3743 match(notemp_iRegI); | |
3744 match(g1RegI); | |
3745 match(o0RegI); | |
3746 match(iRegIsafe); | |
3747 | |
3748 format %{ %} | |
3749 interface(REG_INTER); | |
3750 %} | |
3751 | |
3752 operand notemp_iRegI() %{ | |
3753 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
3754 match(RegI); | |
3755 | |
3756 match(o0RegI); | |
3757 | |
3758 format %{ %} | |
3759 interface(REG_INTER); | |
3760 %} | |
3761 | |
3762 operand o0RegI() %{ | |
3763 constraint(ALLOC_IN_RC(o0_regI)); | |
3764 match(iRegI); | |
3765 | |
3766 format %{ %} | |
3767 interface(REG_INTER); | |
3768 %} | |
3769 | |
3770 // Pointer Register | |
3771 operand iRegP() %{ | |
3772 constraint(ALLOC_IN_RC(ptr_reg)); | |
3773 match(RegP); | |
3774 | |
3775 match(lock_ptr_RegP); | |
3776 match(g1RegP); | |
3777 match(g2RegP); | |
3778 match(g3RegP); | |
3779 match(g4RegP); | |
3780 match(i0RegP); | |
3781 match(o0RegP); | |
3782 match(o1RegP); | |
3783 match(l7RegP); | |
3784 | |
3785 format %{ %} | |
3786 interface(REG_INTER); | |
3787 %} | |
3788 | |
3789 operand sp_ptr_RegP() %{ | |
3790 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
3791 match(RegP); | |
3792 match(iRegP); | |
3793 | |
3794 format %{ %} | |
3795 interface(REG_INTER); | |
3796 %} | |
3797 | |
3798 operand lock_ptr_RegP() %{ | |
3799 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
3800 match(RegP); | |
3801 match(i0RegP); | |
3802 match(o0RegP); | |
3803 match(o1RegP); | |
3804 match(l7RegP); | |
3805 | |
3806 format %{ %} | |
3807 interface(REG_INTER); | |
3808 %} | |
3809 | |
3810 operand g1RegP() %{ | |
3811 constraint(ALLOC_IN_RC(g1_regP)); | |
3812 match(iRegP); | |
3813 | |
3814 format %{ %} | |
3815 interface(REG_INTER); | |
3816 %} | |
3817 | |
3818 operand g2RegP() %{ | |
3819 constraint(ALLOC_IN_RC(g2_regP)); | |
3820 match(iRegP); | |
3821 | |
3822 format %{ %} | |
3823 interface(REG_INTER); | |
3824 %} | |
3825 | |
3826 operand g3RegP() %{ | |
3827 constraint(ALLOC_IN_RC(g3_regP)); | |
3828 match(iRegP); | |
3829 | |
3830 format %{ %} | |
3831 interface(REG_INTER); | |
3832 %} | |
3833 | |
3834 operand g1RegI() %{ | |
3835 constraint(ALLOC_IN_RC(g1_regI)); | |
3836 match(iRegI); | |
3837 | |
3838 format %{ %} | |
3839 interface(REG_INTER); | |
3840 %} | |
3841 | |
3842 operand g3RegI() %{ | |
3843 constraint(ALLOC_IN_RC(g3_regI)); | |
3844 match(iRegI); | |
3845 | |
3846 format %{ %} | |
3847 interface(REG_INTER); | |
3848 %} | |
3849 | |
3850 operand g4RegI() %{ | |
3851 constraint(ALLOC_IN_RC(g4_regI)); | |
3852 match(iRegI); | |
3853 | |
3854 format %{ %} | |
3855 interface(REG_INTER); | |
3856 %} | |
3857 | |
3858 operand g4RegP() %{ | |
3859 constraint(ALLOC_IN_RC(g4_regP)); | |
3860 match(iRegP); | |
3861 | |
3862 format %{ %} | |
3863 interface(REG_INTER); | |
3864 %} | |
3865 | |
3866 operand i0RegP() %{ | |
3867 constraint(ALLOC_IN_RC(i0_regP)); | |
3868 match(iRegP); | |
3869 | |
3870 format %{ %} | |
3871 interface(REG_INTER); | |
3872 %} | |
3873 | |
3874 operand o0RegP() %{ | |
3875 constraint(ALLOC_IN_RC(o0_regP)); | |
3876 match(iRegP); | |
3877 | |
3878 format %{ %} | |
3879 interface(REG_INTER); | |
3880 %} | |
3881 | |
3882 operand o1RegP() %{ | |
3883 constraint(ALLOC_IN_RC(o1_regP)); | |
3884 match(iRegP); | |
3885 | |
3886 format %{ %} | |
3887 interface(REG_INTER); | |
3888 %} | |
3889 | |
3890 operand o2RegP() %{ | |
3891 constraint(ALLOC_IN_RC(o2_regP)); | |
3892 match(iRegP); | |
3893 | |
3894 format %{ %} | |
3895 interface(REG_INTER); | |
3896 %} | |
3897 | |
3898 operand o7RegP() %{ | |
3899 constraint(ALLOC_IN_RC(o7_regP)); | |
3900 match(iRegP); | |
3901 | |
3902 format %{ %} | |
3903 interface(REG_INTER); | |
3904 %} | |
3905 | |
3906 operand l7RegP() %{ | |
3907 constraint(ALLOC_IN_RC(l7_regP)); | |
3908 match(iRegP); | |
3909 | |
3910 format %{ %} | |
3911 interface(REG_INTER); | |
3912 %} | |
3913 | |
3914 operand o7RegI() %{ | |
3915 constraint(ALLOC_IN_RC(o7_regI)); | |
3916 match(iRegI); | |
3917 | |
3918 format %{ %} | |
3919 interface(REG_INTER); | |
3920 %} | |
3921 | |
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3922 operand iRegN() %{ |
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3923 constraint(ALLOC_IN_RC(int_reg)); |
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3924 match(RegN); |
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3925 |
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3926 format %{ %} |
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3927 interface(REG_INTER); |
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3928 %} |
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3929 |
0 | 3930 // Long Register |
3931 operand iRegL() %{ | |
3932 constraint(ALLOC_IN_RC(long_reg)); | |
3933 match(RegL); | |
3934 | |
3935 format %{ %} | |
3936 interface(REG_INTER); | |
3937 %} | |
3938 | |
3939 operand o2RegL() %{ | |
3940 constraint(ALLOC_IN_RC(o2_regL)); | |
3941 match(iRegL); | |
3942 | |
3943 format %{ %} | |
3944 interface(REG_INTER); | |
3945 %} | |
3946 | |
3947 operand o7RegL() %{ | |
3948 constraint(ALLOC_IN_RC(o7_regL)); | |
3949 match(iRegL); | |
3950 | |
3951 format %{ %} | |
3952 interface(REG_INTER); | |
3953 %} | |
3954 | |
3955 operand g1RegL() %{ | |
3956 constraint(ALLOC_IN_RC(g1_regL)); | |
3957 match(iRegL); | |
3958 | |
3959 format %{ %} | |
3960 interface(REG_INTER); | |
3961 %} | |
3962 | |
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3963 operand g3RegL() %{ |
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3964 constraint(ALLOC_IN_RC(g3_regL)); |
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3965 match(iRegL); |
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3966 |
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3967 format %{ %} |
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3968 interface(REG_INTER); |
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3969 %} |
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3970 |
0 | 3971 // Int Register safe |
3972 // This is 64bit safe | |
3973 operand iRegIsafe() %{ | |
3974 constraint(ALLOC_IN_RC(long_reg)); | |
3975 | |
3976 match(iRegI); | |
3977 | |
3978 format %{ %} | |
3979 interface(REG_INTER); | |
3980 %} | |
3981 | |
3982 // Condition Code Flag Register | |
3983 operand flagsReg() %{ | |
3984 constraint(ALLOC_IN_RC(int_flags)); | |
3985 match(RegFlags); | |
3986 | |
3987 format %{ "ccr" %} // both ICC and XCC | |
3988 interface(REG_INTER); | |
3989 %} | |
3990 | |
3991 // Condition Code Register, unsigned comparisons. | |
3992 operand flagsRegU() %{ | |
3993 constraint(ALLOC_IN_RC(int_flags)); | |
3994 match(RegFlags); | |
3995 | |
3996 format %{ "icc_U" %} | |
3997 interface(REG_INTER); | |
3998 %} | |
3999 | |
4000 // Condition Code Register, pointer comparisons. | |
4001 operand flagsRegP() %{ | |
4002 constraint(ALLOC_IN_RC(int_flags)); | |
4003 match(RegFlags); | |
4004 | |
4005 #ifdef _LP64 | |
4006 format %{ "xcc_P" %} | |
4007 #else | |
4008 format %{ "icc_P" %} | |
4009 #endif | |
4010 interface(REG_INTER); | |
4011 %} | |
4012 | |
4013 // Condition Code Register, long comparisons. | |
4014 operand flagsRegL() %{ | |
4015 constraint(ALLOC_IN_RC(int_flags)); | |
4016 match(RegFlags); | |
4017 | |
4018 format %{ "xcc_L" %} | |
4019 interface(REG_INTER); | |
4020 %} | |
4021 | |
4022 // Condition Code Register, floating comparisons, unordered same as "less". | |
4023 operand flagsRegF() %{ | |
4024 constraint(ALLOC_IN_RC(float_flags)); | |
4025 match(RegFlags); | |
4026 match(flagsRegF0); | |
4027 | |
4028 format %{ %} | |
4029 interface(REG_INTER); | |
4030 %} | |
4031 | |
4032 operand flagsRegF0() %{ | |
4033 constraint(ALLOC_IN_RC(float_flag0)); | |
4034 match(RegFlags); | |
4035 | |
4036 format %{ %} | |
4037 interface(REG_INTER); | |
4038 %} | |
4039 | |
4040 | |
4041 // Condition Code Flag Register used by long compare | |
4042 operand flagsReg_long_LTGE() %{ | |
4043 constraint(ALLOC_IN_RC(int_flags)); | |
4044 match(RegFlags); | |
4045 format %{ "icc_LTGE" %} | |
4046 interface(REG_INTER); | |
4047 %} | |
4048 operand flagsReg_long_EQNE() %{ | |
4049 constraint(ALLOC_IN_RC(int_flags)); | |
4050 match(RegFlags); | |
4051 format %{ "icc_EQNE" %} | |
4052 interface(REG_INTER); | |
4053 %} | |
4054 operand flagsReg_long_LEGT() %{ | |
4055 constraint(ALLOC_IN_RC(int_flags)); | |
4056 match(RegFlags); | |
4057 format %{ "icc_LEGT" %} | |
4058 interface(REG_INTER); | |
4059 %} | |
4060 | |
4061 | |
4062 operand regD() %{ | |
4063 constraint(ALLOC_IN_RC(dflt_reg)); | |
4064 match(RegD); | |
4065 | |
551 | 4066 match(regD_low); |
4067 | |
0 | 4068 format %{ %} |
4069 interface(REG_INTER); | |
4070 %} | |
4071 | |
4072 operand regF() %{ | |
4073 constraint(ALLOC_IN_RC(sflt_reg)); | |
4074 match(RegF); | |
4075 | |
4076 format %{ %} | |
4077 interface(REG_INTER); | |
4078 %} | |
4079 | |
4080 operand regD_low() %{ | |
4081 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
551 | 4082 match(regD); |
0 | 4083 |
4084 format %{ %} | |
4085 interface(REG_INTER); | |
4086 %} | |
4087 | |
4088 // Special Registers | |
4089 | |
4090 // Method Register | |
4091 operand inline_cache_regP(iRegP reg) %{ | |
4092 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
4093 match(reg); | |
4094 format %{ %} | |
4095 interface(REG_INTER); | |
4096 %} | |
4097 | |
4098 operand interpreter_method_oop_regP(iRegP reg) %{ | |
4099 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
4100 match(reg); | |
4101 format %{ %} | |
4102 interface(REG_INTER); | |
4103 %} | |
4104 | |
4105 | |
4106 //----------Complex Operands--------------------------------------------------- | |
4107 // Indirect Memory Reference | |
4108 operand indirect(sp_ptr_RegP reg) %{ | |
4109 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4110 match(reg); | |
4111 | |
4112 op_cost(100); | |
4113 format %{ "[$reg]" %} | |
4114 interface(MEMORY_INTER) %{ | |
4115 base($reg); | |
4116 index(0x0); | |
4117 scale(0x0); | |
4118 disp(0x0); | |
4119 %} | |
4120 %} | |
4121 | |
785 | 4122 // Indirect with simm13 Offset |
0 | 4123 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
4124 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4125 match(AddP reg offset); | |
4126 | |
4127 op_cost(100); | |
4128 format %{ "[$reg + $offset]" %} | |
4129 interface(MEMORY_INTER) %{ | |
4130 base($reg); | |
4131 index(0x0); | |
4132 scale(0x0); | |
4133 disp($offset); | |
4134 %} | |
4135 %} | |
4136 | |
785 | 4137 // Indirect with simm13 Offset minus 7 |
4138 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ | |
4139 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4140 match(AddP reg offset); | |
4141 | |
4142 op_cost(100); | |
4143 format %{ "[$reg + $offset]" %} | |
4144 interface(MEMORY_INTER) %{ | |
4145 base($reg); | |
4146 index(0x0); | |
4147 scale(0x0); | |
4148 disp($offset); | |
4149 %} | |
4150 %} | |
4151 | |
0 | 4152 // Note: Intel has a swapped version also, like this: |
4153 //operand indOffsetX(iRegI reg, immP offset) %{ | |
4154 // constraint(ALLOC_IN_RC(int_reg)); | |
4155 // match(AddP offset reg); | |
4156 // | |
4157 // op_cost(100); | |
4158 // format %{ "[$reg + $offset]" %} | |
4159 // interface(MEMORY_INTER) %{ | |
4160 // base($reg); | |
4161 // index(0x0); | |
4162 // scale(0x0); | |
4163 // disp($offset); | |
4164 // %} | |
4165 //%} | |
4166 //// However, it doesn't make sense for SPARC, since | |
4167 // we have no particularly good way to embed oops in | |
4168 // single instructions. | |
4169 | |
4170 // Indirect with Register Index | |
4171 operand indIndex(iRegP addr, iRegX index) %{ | |
4172 constraint(ALLOC_IN_RC(ptr_reg)); | |
4173 match(AddP addr index); | |
4174 | |
4175 op_cost(100); | |
4176 format %{ "[$addr + $index]" %} | |
4177 interface(MEMORY_INTER) %{ | |
4178 base($addr); | |
4179 index($index); | |
4180 scale(0x0); | |
4181 disp(0x0); | |
4182 %} | |
4183 %} | |
4184 | |
4185 //----------Special Memory Operands-------------------------------------------- | |
4186 // Stack Slot Operand - This operand is used for loading and storing temporary | |
4187 // values on the stack where a match requires a value to | |
4188 // flow through memory. | |
4189 operand stackSlotI(sRegI reg) %{ | |
4190 constraint(ALLOC_IN_RC(stack_slots)); | |
4191 op_cost(100); | |
4192 //match(RegI); | |
4193 format %{ "[$reg]" %} | |
4194 interface(MEMORY_INTER) %{ | |
4195 base(0xE); // R_SP | |
4196 index(0x0); | |
4197 scale(0x0); | |
4198 disp($reg); // Stack Offset | |
4199 %} | |
4200 %} | |
4201 | |
4202 operand stackSlotP(sRegP reg) %{ | |
4203 constraint(ALLOC_IN_RC(stack_slots)); | |
4204 op_cost(100); | |
4205 //match(RegP); | |
4206 format %{ "[$reg]" %} | |
4207 interface(MEMORY_INTER) %{ | |
4208 base(0xE); // R_SP | |
4209 index(0x0); | |
4210 scale(0x0); | |
4211 disp($reg); // Stack Offset | |
4212 %} | |
4213 %} | |
4214 | |
4215 operand stackSlotF(sRegF reg) %{ | |
4216 constraint(ALLOC_IN_RC(stack_slots)); | |
4217 op_cost(100); | |
4218 //match(RegF); | |
4219 format %{ "[$reg]" %} | |
4220 interface(MEMORY_INTER) %{ | |
4221 base(0xE); // R_SP | |
4222 index(0x0); | |
4223 scale(0x0); | |
4224 disp($reg); // Stack Offset | |
4225 %} | |
4226 %} | |
4227 operand stackSlotD(sRegD reg) %{ | |
4228 constraint(ALLOC_IN_RC(stack_slots)); | |
4229 op_cost(100); | |
4230 //match(RegD); | |
4231 format %{ "[$reg]" %} | |
4232 interface(MEMORY_INTER) %{ | |
4233 base(0xE); // R_SP | |
4234 index(0x0); | |
4235 scale(0x0); | |
4236 disp($reg); // Stack Offset | |
4237 %} | |
4238 %} | |
4239 operand stackSlotL(sRegL reg) %{ | |
4240 constraint(ALLOC_IN_RC(stack_slots)); | |
4241 op_cost(100); | |
4242 //match(RegL); | |
4243 format %{ "[$reg]" %} | |
4244 interface(MEMORY_INTER) %{ | |
4245 base(0xE); // R_SP | |
4246 index(0x0); | |
4247 scale(0x0); | |
4248 disp($reg); // Stack Offset | |
4249 %} | |
4250 %} | |
4251 | |
4252 // Operands for expressing Control Flow | |
4253 // NOTE: Label is a predefined operand which should not be redefined in | |
4254 // the AD file. It is generically handled within the ADLC. | |
4255 | |
4256 //----------Conditional Branch Operands---------------------------------------- | |
4257 // Comparison Op - This is the operation of the comparison, and is limited to | |
4258 // the following set of codes: | |
4259 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
4260 // | |
4261 // Other attributes of the comparison, such as unsignedness, are specified | |
4262 // by the comparison instruction that sets a condition code flags register. | |
4263 // That result is represented by a flags operand whose subtype is appropriate | |
4264 // to the unsignedness (etc.) of the comparison. | |
4265 // | |
4266 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
4267 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
4268 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
4269 | |
4270 operand cmpOp() %{ | |
4271 match(Bool); | |
4272 | |
4273 format %{ "" %} | |
4274 interface(COND_INTER) %{ | |
4275 equal(0x1); | |
4276 not_equal(0x9); | |
4277 less(0x3); | |
4278 greater_equal(0xB); | |
4279 less_equal(0x2); | |
4280 greater(0xA); | |
4281 %} | |
4282 %} | |
4283 | |
4284 // Comparison Op, unsigned | |
4285 operand cmpOpU() %{ | |
4286 match(Bool); | |
4287 | |
4288 format %{ "u" %} | |
4289 interface(COND_INTER) %{ | |
4290 equal(0x1); | |
4291 not_equal(0x9); | |
4292 less(0x5); | |
4293 greater_equal(0xD); | |
4294 less_equal(0x4); | |
4295 greater(0xC); | |
4296 %} | |
4297 %} | |
4298 | |
4299 // Comparison Op, pointer (same as unsigned) | |
4300 operand cmpOpP() %{ | |
4301 match(Bool); | |
4302 | |
4303 format %{ "p" %} | |
4304 interface(COND_INTER) %{ | |
4305 equal(0x1); | |
4306 not_equal(0x9); | |
4307 less(0x5); | |
4308 greater_equal(0xD); | |
4309 less_equal(0x4); | |
4310 greater(0xC); | |
4311 %} | |
4312 %} | |
4313 | |
4314 // Comparison Op, branch-register encoding | |
4315 operand cmpOp_reg() %{ | |
4316 match(Bool); | |
4317 | |
4318 format %{ "" %} | |
4319 interface(COND_INTER) %{ | |
4320 equal (0x1); | |
4321 not_equal (0x5); | |
4322 less (0x3); | |
4323 greater_equal(0x7); | |
4324 less_equal (0x2); | |
4325 greater (0x6); | |
4326 %} | |
4327 %} | |
4328 | |
4329 // Comparison Code, floating, unordered same as less | |
4330 operand cmpOpF() %{ | |
4331 match(Bool); | |
4332 | |
4333 format %{ "fl" %} | |
4334 interface(COND_INTER) %{ | |
4335 equal(0x9); | |
4336 not_equal(0x1); | |
4337 less(0x3); | |
4338 greater_equal(0xB); | |
4339 less_equal(0xE); | |
4340 greater(0x6); | |
4341 %} | |
4342 %} | |
4343 | |
4344 // Used by long compare | |
4345 operand cmpOp_commute() %{ | |
4346 match(Bool); | |
4347 | |
4348 format %{ "" %} | |
4349 interface(COND_INTER) %{ | |
4350 equal(0x1); | |
4351 not_equal(0x9); | |
4352 less(0xA); | |
4353 greater_equal(0x2); | |
4354 less_equal(0xB); | |
4355 greater(0x3); | |
4356 %} | |
4357 %} | |
4358 | |
4359 //----------OPERAND CLASSES---------------------------------------------------- | |
4360 // Operand Classes are groups of operands that are used to simplify | |
605 | 4361 // instruction definitions by not requiring the AD writer to specify separate |
0 | 4362 // instructions for every form of operand when the instruction accepts |
4363 // multiple operand types with the same basic encoding and format. The classic | |
4364 // case of this is memory operands. | |
4365 opclass memory( indirect, indOffset13, indIndex ); | |
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4366 opclass indIndexMemory( indIndex ); |
0 | 4367 |
4368 //----------PIPELINE----------------------------------------------------------- | |
4369 pipeline %{ | |
4370 | |
4371 //----------ATTRIBUTES--------------------------------------------------------- | |
4372 attributes %{ | |
4373 fixed_size_instructions; // Fixed size instructions | |
4374 branch_has_delay_slot; // Branch has delay slot following | |
4375 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
4376 instruction_unit_size = 4; // An instruction is 4 bytes long | |
4377 instruction_fetch_unit_size = 16; // The processor fetches one line | |
4378 instruction_fetch_units = 1; // of 16 bytes | |
4379 | |
4380 // List of nop instructions | |
4381 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
4382 %} | |
4383 | |
4384 //----------RESOURCES---------------------------------------------------------- | |
4385 // Resources are the functional units available to the machine | |
4386 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
4387 | |
4388 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
4389 // Pipeline Description specifies the stages in the machine's pipeline | |
4390 | |
4391 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
4392 | |
4393 //----------PIPELINE CLASSES--------------------------------------------------- | |
4394 // Pipeline Classes describe the stages in which input and output are | |
4395 // referenced by the hardware pipeline. | |
4396 | |
4397 // Integer ALU reg-reg operation | |
4398 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4399 single_instruction; | |
4400 dst : E(write); | |
4401 src1 : R(read); | |
4402 src2 : R(read); | |
4403 IALU : R; | |
4404 %} | |
4405 | |
4406 // Integer ALU reg-reg long operation | |
4407 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
4408 instruction_count(2); | |
4409 dst : E(write); | |
4410 src1 : R(read); | |
4411 src2 : R(read); | |
4412 IALU : R; | |
4413 IALU : R; | |
4414 %} | |
4415 | |
4416 // Integer ALU reg-reg long dependent operation | |
4417 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
4418 instruction_count(1); multiple_bundles; | |
4419 dst : E(write); | |
4420 src1 : R(read); | |
4421 src2 : R(read); | |
4422 cr : E(write); | |
4423 IALU : R(2); | |
4424 %} | |
4425 | |
4426 // Integer ALU reg-imm operaion | |
4427 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4428 single_instruction; | |
4429 dst : E(write); | |
4430 src1 : R(read); | |
4431 IALU : R; | |
4432 %} | |
4433 | |
4434 // Integer ALU reg-reg operation with condition code | |
4435 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
4436 single_instruction; | |
4437 dst : E(write); | |
4438 cr : E(write); | |
4439 src1 : R(read); | |
4440 src2 : R(read); | |
4441 IALU : R; | |
4442 %} | |
4443 | |
4444 // Integer ALU reg-imm operation with condition code | |
4445 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
4446 single_instruction; | |
4447 dst : E(write); | |
4448 cr : E(write); | |
4449 src1 : R(read); | |
4450 IALU : R; | |
4451 %} | |
4452 | |
4453 // Integer ALU zero-reg operation | |
4454 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
4455 single_instruction; | |
4456 dst : E(write); | |
4457 src2 : R(read); | |
4458 IALU : R; | |
4459 %} | |
4460 | |
4461 // Integer ALU zero-reg operation with condition code only | |
4462 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
4463 single_instruction; | |
4464 cr : E(write); | |
4465 src : R(read); | |
4466 IALU : R; | |
4467 %} | |
4468 | |
4469 // Integer ALU reg-reg operation with condition code only | |
4470 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4471 single_instruction; | |
4472 cr : E(write); | |
4473 src1 : R(read); | |
4474 src2 : R(read); | |
4475 IALU : R; | |
4476 %} | |
4477 | |
4478 // Integer ALU reg-imm operation with condition code only | |
4479 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4480 single_instruction; | |
4481 cr : E(write); | |
4482 src1 : R(read); | |
4483 IALU : R; | |
4484 %} | |
4485 | |
4486 // Integer ALU reg-reg-zero operation with condition code only | |
4487 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
4488 single_instruction; | |
4489 cr : E(write); | |
4490 src1 : R(read); | |
4491 src2 : R(read); | |
4492 IALU : R; | |
4493 %} | |
4494 | |
4495 // Integer ALU reg-imm-zero operation with condition code only | |
4496 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
4497 single_instruction; | |
4498 cr : E(write); | |
4499 src1 : R(read); | |
4500 IALU : R; | |
4501 %} | |
4502 | |
4503 // Integer ALU reg-reg operation with condition code, src1 modified | |
4504 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4505 single_instruction; | |
4506 cr : E(write); | |
4507 src1 : E(write); | |
4508 src1 : R(read); | |
4509 src2 : R(read); | |
4510 IALU : R; | |
4511 %} | |
4512 | |
4513 // Integer ALU reg-imm operation with condition code, src1 modified | |
4514 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4515 single_instruction; | |
4516 cr : E(write); | |
4517 src1 : E(write); | |
4518 src1 : R(read); | |
4519 IALU : R; | |
4520 %} | |
4521 | |
4522 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
4523 multiple_bundles; | |
4524 dst : E(write)+4; | |
4525 cr : E(write); | |
4526 src1 : R(read); | |
4527 src2 : R(read); | |
4528 IALU : R(3); | |
4529 BR : R(2); | |
4530 %} | |
4531 | |
4532 // Integer ALU operation | |
4533 pipe_class ialu_none(iRegI dst) %{ | |
4534 single_instruction; | |
4535 dst : E(write); | |
4536 IALU : R; | |
4537 %} | |
4538 | |
4539 // Integer ALU reg operation | |
4540 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
4541 single_instruction; may_have_no_code; | |
4542 dst : E(write); | |
4543 src : R(read); | |
4544 IALU : R; | |
4545 %} | |
4546 | |
4547 // Integer ALU reg conditional operation | |
4548 // This instruction has a 1 cycle stall, and cannot execute | |
4549 // in the same cycle as the instruction setting the condition | |
4550 // code. We kludge this by pretending to read the condition code | |
4551 // 1 cycle earlier, and by marking the functional units as busy | |
4552 // for 2 cycles with the result available 1 cycle later than | |
4553 // is really the case. | |
4554 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
4555 single_instruction; | |
4556 op2_out : C(write); | |
4557 op1 : R(read); | |
4558 cr : R(read); // This is really E, with a 1 cycle stall | |
4559 BR : R(2); | |
4560 MS : R(2); | |
4561 %} | |
4562 | |
4563 #ifdef _LP64 | |
4564 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
4565 instruction_count(1); multiple_bundles; | |
4566 dst : C(write)+1; | |
4567 src : R(read)+1; | |
4568 IALU : R(1); | |
4569 BR : E(2); | |
4570 MS : E(2); | |
4571 %} | |
4572 #endif | |
4573 | |
4574 // Integer ALU reg operation | |
4575 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
4576 single_instruction; may_have_no_code; | |
4577 dst : E(write); | |
4578 src : R(read); | |
4579 IALU : R; | |
4580 %} | |
4581 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
4582 single_instruction; may_have_no_code; | |
4583 dst : E(write); | |
4584 src : R(read); | |
4585 IALU : R; | |
4586 %} | |
4587 | |
4588 // Two integer ALU reg operations | |
4589 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
4590 instruction_count(2); | |
4591 dst : E(write); | |
4592 src : R(read); | |
4593 A0 : R; | |
4594 A1 : R; | |
4595 %} | |
4596 | |
4597 // Two integer ALU reg operations | |
4598 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
4599 instruction_count(2); may_have_no_code; | |
4600 dst : E(write); | |
4601 src : R(read); | |
4602 A0 : R; | |
4603 A1 : R; | |
4604 %} | |
4605 | |
4606 // Integer ALU imm operation | |
4607 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
4608 single_instruction; | |
4609 dst : E(write); | |
4610 IALU : R; | |
4611 %} | |
4612 | |
4613 // Integer ALU reg-reg with carry operation | |
4614 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
4615 single_instruction; | |
4616 dst : E(write); | |
4617 src1 : R(read); | |
4618 src2 : R(read); | |
4619 IALU : R; | |
4620 %} | |
4621 | |
4622 // Integer ALU cc operation | |
4623 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
4624 single_instruction; | |
4625 dst : E(write); | |
4626 cc : R(read); | |
4627 IALU : R; | |
4628 %} | |
4629 | |
4630 // Integer ALU cc / second IALU operation | |
4631 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
4632 instruction_count(1); multiple_bundles; | |
4633 dst : E(write)+1; | |
4634 src : R(read); | |
4635 IALU : R; | |
4636 %} | |
4637 | |
4638 // Integer ALU cc / second IALU operation | |
4639 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
4640 instruction_count(1); multiple_bundles; | |
4641 dst : E(write)+1; | |
4642 p : R(read); | |
4643 q : R(read); | |
4644 IALU : R; | |
4645 %} | |
4646 | |
4647 // Integer ALU hi-lo-reg operation | |
4648 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
4649 instruction_count(1); multiple_bundles; | |
4650 dst : E(write)+1; | |
4651 IALU : R(2); | |
4652 %} | |
4653 | |
4654 // Float ALU hi-lo-reg operation (with temp) | |
4655 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
4656 instruction_count(1); multiple_bundles; | |
4657 dst : E(write)+1; | |
4658 IALU : R(2); | |
4659 %} | |
4660 | |
4661 // Long Constant | |
4662 pipe_class loadConL( iRegL dst, immL src ) %{ | |
4663 instruction_count(2); multiple_bundles; | |
4664 dst : E(write)+1; | |
4665 IALU : R(2); | |
4666 IALU : R(2); | |
4667 %} | |
4668 | |
4669 // Pointer Constant | |
4670 pipe_class loadConP( iRegP dst, immP src ) %{ | |
4671 instruction_count(0); multiple_bundles; | |
4672 fixed_latency(6); | |
4673 %} | |
4674 | |
4675 // Polling Address | |
4676 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
4677 #ifdef _LP64 | |
4678 instruction_count(0); multiple_bundles; | |
4679 fixed_latency(6); | |
4680 #else | |
4681 dst : E(write); | |
4682 IALU : R; | |
4683 #endif | |
4684 %} | |
4685 | |
4686 // Long Constant small | |
4687 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
4688 instruction_count(2); | |
4689 dst : E(write); | |
4690 IALU : R; | |
4691 IALU : R; | |
4692 %} | |
4693 | |
4694 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
4695 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
4696 instruction_count(1); multiple_bundles; | |
4697 src : R(read); | |
4698 dst : M(write)+1; | |
4699 IALU : R; | |
4700 MS : E; | |
4701 %} | |
4702 | |
4703 // Integer ALU nop operation | |
4704 pipe_class ialu_nop() %{ | |
4705 single_instruction; | |
4706 IALU : R; | |
4707 %} | |
4708 | |
4709 // Integer ALU nop operation | |
4710 pipe_class ialu_nop_A0() %{ | |
4711 single_instruction; | |
4712 A0 : R; | |
4713 %} | |
4714 | |
4715 // Integer ALU nop operation | |
4716 pipe_class ialu_nop_A1() %{ | |
4717 single_instruction; | |
4718 A1 : R; | |
4719 %} | |
4720 | |
4721 // Integer Multiply reg-reg operation | |
4722 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4723 single_instruction; | |
4724 dst : E(write); | |
4725 src1 : R(read); | |
4726 src2 : R(read); | |
4727 MS : R(5); | |
4728 %} | |
4729 | |
4730 // Integer Multiply reg-imm operation | |
4731 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4732 single_instruction; | |
4733 dst : E(write); | |
4734 src1 : R(read); | |
4735 MS : R(5); | |
4736 %} | |
4737 | |
4738 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4739 single_instruction; | |
4740 dst : E(write)+4; | |
4741 src1 : R(read); | |
4742 src2 : R(read); | |
4743 MS : R(6); | |
4744 %} | |
4745 | |
4746 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4747 single_instruction; | |
4748 dst : E(write)+4; | |
4749 src1 : R(read); | |
4750 MS : R(6); | |
4751 %} | |
4752 | |
4753 // Integer Divide reg-reg | |
4754 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
4755 instruction_count(1); multiple_bundles; | |
4756 dst : E(write); | |
4757 temp : E(write); | |
4758 src1 : R(read); | |
4759 src2 : R(read); | |
4760 temp : R(read); | |
4761 MS : R(38); | |
4762 %} | |
4763 | |
4764 // Integer Divide reg-imm | |
4765 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
4766 instruction_count(1); multiple_bundles; | |
4767 dst : E(write); | |
4768 temp : E(write); | |
4769 src1 : R(read); | |
4770 temp : R(read); | |
4771 MS : R(38); | |
4772 %} | |
4773 | |
4774 // Long Divide | |
4775 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4776 dst : E(write)+71; | |
4777 src1 : R(read); | |
4778 src2 : R(read)+1; | |
4779 MS : R(70); | |
4780 %} | |
4781 | |
4782 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4783 dst : E(write)+71; | |
4784 src1 : R(read); | |
4785 MS : R(70); | |
4786 %} | |
4787 | |
4788 // Floating Point Add Float | |
4789 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4790 single_instruction; | |
4791 dst : X(write); | |
4792 src1 : E(read); | |
4793 src2 : E(read); | |
4794 FA : R; | |
4795 %} | |
4796 | |
4797 // Floating Point Add Double | |
4798 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4799 single_instruction; | |
4800 dst : X(write); | |
4801 src1 : E(read); | |
4802 src2 : E(read); | |
4803 FA : R; | |
4804 %} | |
4805 | |
4806 // Floating Point Conditional Move based on integer flags | |
4807 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
4808 single_instruction; | |
4809 dst : X(write); | |
4810 src : E(read); | |
4811 cr : R(read); | |
4812 FA : R(2); | |
4813 BR : R(2); | |
4814 %} | |
4815 | |
4816 // Floating Point Conditional Move based on integer flags | |
4817 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
4818 single_instruction; | |
4819 dst : X(write); | |
4820 src : E(read); | |
4821 cr : R(read); | |
4822 FA : R(2); | |
4823 BR : R(2); | |
4824 %} | |
4825 | |
4826 // Floating Point Multiply Float | |
4827 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4828 single_instruction; | |
4829 dst : X(write); | |
4830 src1 : E(read); | |
4831 src2 : E(read); | |
4832 FM : R; | |
4833 %} | |
4834 | |
4835 // Floating Point Multiply Double | |
4836 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4837 single_instruction; | |
4838 dst : X(write); | |
4839 src1 : E(read); | |
4840 src2 : E(read); | |
4841 FM : R; | |
4842 %} | |
4843 | |
4844 // Floating Point Divide Float | |
4845 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4846 single_instruction; | |
4847 dst : X(write); | |
4848 src1 : E(read); | |
4849 src2 : E(read); | |
4850 FM : R; | |
4851 FDIV : C(14); | |
4852 %} | |
4853 | |
4854 // Floating Point Divide Double | |
4855 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4856 single_instruction; | |
4857 dst : X(write); | |
4858 src1 : E(read); | |
4859 src2 : E(read); | |
4860 FM : R; | |
4861 FDIV : C(17); | |
4862 %} | |
4863 | |
4864 // Floating Point Move/Negate/Abs Float | |
4865 pipe_class faddF_reg(regF dst, regF src) %{ | |
4866 single_instruction; | |
4867 dst : W(write); | |
4868 src : E(read); | |
4869 FA : R(1); | |
4870 %} | |
4871 | |
4872 // Floating Point Move/Negate/Abs Double | |
4873 pipe_class faddD_reg(regD dst, regD src) %{ | |
4874 single_instruction; | |
4875 dst : W(write); | |
4876 src : E(read); | |
4877 FA : R; | |
4878 %} | |
4879 | |
4880 // Floating Point Convert F->D | |
4881 pipe_class fcvtF2D(regD dst, regF src) %{ | |
4882 single_instruction; | |
4883 dst : X(write); | |
4884 src : E(read); | |
4885 FA : R; | |
4886 %} | |
4887 | |
4888 // Floating Point Convert I->D | |
4889 pipe_class fcvtI2D(regD dst, regF src) %{ | |
4890 single_instruction; | |
4891 dst : X(write); | |
4892 src : E(read); | |
4893 FA : R; | |
4894 %} | |
4895 | |
4896 // Floating Point Convert LHi->D | |
4897 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
4898 single_instruction; | |
4899 dst : X(write); | |
4900 src : E(read); | |
4901 FA : R; | |
4902 %} | |
4903 | |
4904 // Floating Point Convert L->D | |
4905 pipe_class fcvtL2D(regD dst, regF src) %{ | |
4906 single_instruction; | |
4907 dst : X(write); | |
4908 src : E(read); | |
4909 FA : R; | |
4910 %} | |
4911 | |
4912 // Floating Point Convert L->F | |
4913 pipe_class fcvtL2F(regD dst, regF src) %{ | |
4914 single_instruction; | |
4915 dst : X(write); | |
4916 src : E(read); | |
4917 FA : R; | |
4918 %} | |
4919 | |
4920 // Floating Point Convert D->F | |
4921 pipe_class fcvtD2F(regD dst, regF src) %{ | |
4922 single_instruction; | |
4923 dst : X(write); | |
4924 src : E(read); | |
4925 FA : R; | |
4926 %} | |
4927 | |
4928 // Floating Point Convert I->L | |
4929 pipe_class fcvtI2L(regD dst, regF src) %{ | |
4930 single_instruction; | |
4931 dst : X(write); | |
4932 src : E(read); | |
4933 FA : R; | |
4934 %} | |
4935 | |
4936 // Floating Point Convert D->F | |
4937 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
4938 instruction_count(1); multiple_bundles; | |
4939 dst : X(write)+6; | |
4940 src : E(read); | |
4941 FA : R; | |
4942 %} | |
4943 | |
4944 // Floating Point Convert D->L | |
4945 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
4946 instruction_count(1); multiple_bundles; | |
4947 dst : X(write)+6; | |
4948 src : E(read); | |
4949 FA : R; | |
4950 %} | |
4951 | |
4952 // Floating Point Convert F->I | |
4953 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
4954 instruction_count(1); multiple_bundles; | |
4955 dst : X(write)+6; | |
4956 src : E(read); | |
4957 FA : R; | |
4958 %} | |
4959 | |
4960 // Floating Point Convert F->L | |
4961 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
4962 instruction_count(1); multiple_bundles; | |
4963 dst : X(write)+6; | |
4964 src : E(read); | |
4965 FA : R; | |
4966 %} | |
4967 | |
4968 // Floating Point Convert I->F | |
4969 pipe_class fcvtI2F(regF dst, regF src) %{ | |
4970 single_instruction; | |
4971 dst : X(write); | |
4972 src : E(read); | |
4973 FA : R; | |
4974 %} | |
4975 | |
4976 // Floating Point Compare | |
4977 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
4978 single_instruction; | |
4979 cr : X(write); | |
4980 src1 : E(read); | |
4981 src2 : E(read); | |
4982 FA : R; | |
4983 %} | |
4984 | |
4985 // Floating Point Compare | |
4986 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
4987 single_instruction; | |
4988 cr : X(write); | |
4989 src1 : E(read); | |
4990 src2 : E(read); | |
4991 FA : R; | |
4992 %} | |
4993 | |
4994 // Floating Add Nop | |
4995 pipe_class fadd_nop() %{ | |
4996 single_instruction; | |
4997 FA : R; | |
4998 %} | |
4999 | |
5000 // Integer Store to Memory | |
5001 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
5002 single_instruction; | |
5003 mem : R(read); | |
5004 src : C(read); | |
5005 MS : R; | |
5006 %} | |
5007 | |
5008 // Integer Store to Memory | |
5009 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
5010 single_instruction; | |
5011 mem : R(read); | |
5012 src : C(read); | |
5013 MS : R; | |
5014 %} | |
5015 | |
5016 // Integer Store Zero to Memory | |
5017 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
5018 single_instruction; | |
5019 mem : R(read); | |
5020 MS : R; | |
5021 %} | |
5022 | |
5023 // Special Stack Slot Store | |
5024 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
5025 single_instruction; | |
5026 stkSlot : R(read); | |
5027 src : C(read); | |
5028 MS : R; | |
5029 %} | |
5030 | |
5031 // Special Stack Slot Store | |
5032 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
5033 instruction_count(2); multiple_bundles; | |
5034 stkSlot : R(read); | |
5035 src : C(read); | |
5036 MS : R(2); | |
5037 %} | |
5038 | |
5039 // Float Store | |
5040 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
5041 single_instruction; | |
5042 mem : R(read); | |
5043 src : C(read); | |
5044 MS : R; | |
5045 %} | |
5046 | |
5047 // Float Store | |
5048 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
5049 single_instruction; | |
5050 mem : R(read); | |
5051 MS : R; | |
5052 %} | |
5053 | |
5054 // Double Store | |
5055 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
5056 instruction_count(1); | |
5057 mem : R(read); | |
5058 src : C(read); | |
5059 MS : R; | |
5060 %} | |
5061 | |
5062 // Double Store | |
5063 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
5064 single_instruction; | |
5065 mem : R(read); | |
5066 MS : R; | |
5067 %} | |
5068 | |
5069 // Special Stack Slot Float Store | |
5070 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
5071 single_instruction; | |
5072 stkSlot : R(read); | |
5073 src : C(read); | |
5074 MS : R; | |
5075 %} | |
5076 | |
5077 // Special Stack Slot Double Store | |
5078 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
5079 single_instruction; | |
5080 stkSlot : R(read); | |
5081 src : C(read); | |
5082 MS : R; | |
5083 %} | |
5084 | |
5085 // Integer Load (when sign bit propagation not needed) | |
5086 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
5087 single_instruction; | |
5088 mem : R(read); | |
5089 dst : C(write); | |
5090 MS : R; | |
5091 %} | |
5092 | |
5093 // Integer Load from stack operand | |
5094 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
5095 single_instruction; | |
5096 mem : R(read); | |
5097 dst : C(write); | |
5098 MS : R; | |
5099 %} | |
5100 | |
5101 // Integer Load (when sign bit propagation or masking is needed) | |
5102 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
5103 single_instruction; | |
5104 mem : R(read); | |
5105 dst : M(write); | |
5106 MS : R; | |
5107 %} | |
5108 | |
5109 // Float Load | |
5110 pipe_class floadF_mem(regF dst, memory mem) %{ | |
5111 single_instruction; | |
5112 mem : R(read); | |
5113 dst : M(write); | |
5114 MS : R; | |
5115 %} | |
5116 | |
5117 // Float Load | |
5118 pipe_class floadD_mem(regD dst, memory mem) %{ | |
5119 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
5120 mem : R(read); | |
5121 dst : M(write); | |
5122 MS : R; | |
5123 %} | |
5124 | |
5125 // Float Load | |
5126 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
5127 single_instruction; | |
5128 stkSlot : R(read); | |
5129 dst : M(write); | |
5130 MS : R; | |
5131 %} | |
5132 | |
5133 // Float Load | |
5134 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
5135 single_instruction; | |
5136 stkSlot : R(read); | |
5137 dst : M(write); | |
5138 MS : R; | |
5139 %} | |
5140 | |
5141 // Memory Nop | |
5142 pipe_class mem_nop() %{ | |
5143 single_instruction; | |
5144 MS : R; | |
5145 %} | |
5146 | |
5147 pipe_class sethi(iRegP dst, immI src) %{ | |
5148 single_instruction; | |
5149 dst : E(write); | |
5150 IALU : R; | |
5151 %} | |
5152 | |
5153 pipe_class loadPollP(iRegP poll) %{ | |
5154 single_instruction; | |
5155 poll : R(read); | |
5156 MS : R; | |
5157 %} | |
5158 | |
5159 pipe_class br(Universe br, label labl) %{ | |
5160 single_instruction_with_delay_slot; | |
5161 BR : R; | |
5162 %} | |
5163 | |
5164 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
5165 single_instruction_with_delay_slot; | |
5166 cr : E(read); | |
5167 BR : R; | |
5168 %} | |
5169 | |
5170 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
5171 single_instruction_with_delay_slot; | |
5172 op1 : E(read); | |
5173 BR : R; | |
5174 MS : R; | |
5175 %} | |
5176 | |
3851 | 5177 // Compare and branch |
5178 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ | |
5179 instruction_count(2); has_delay_slot; | |
5180 cr : E(write); | |
5181 src1 : R(read); | |
5182 src2 : R(read); | |
5183 IALU : R; | |
5184 BR : R; | |
5185 %} | |
5186 | |
5187 // Compare and branch | |
5188 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ | |
5189 instruction_count(2); has_delay_slot; | |
5190 cr : E(write); | |
5191 src1 : R(read); | |
5192 IALU : R; | |
5193 BR : R; | |
5194 %} | |
5195 | |
5196 // Compare and branch using cbcond | |
5197 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ | |
5198 single_instruction; | |
5199 src1 : E(read); | |
5200 src2 : E(read); | |
5201 IALU : R; | |
5202 BR : R; | |
5203 %} | |
5204 | |
5205 // Compare and branch using cbcond | |
5206 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ | |
5207 single_instruction; | |
5208 src1 : E(read); | |
5209 IALU : R; | |
5210 BR : R; | |
5211 %} | |
5212 | |
0 | 5213 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ |
5214 single_instruction_with_delay_slot; | |
5215 cr : E(read); | |
5216 BR : R; | |
5217 %} | |
5218 | |
5219 pipe_class br_nop() %{ | |
5220 single_instruction; | |
5221 BR : R; | |
5222 %} | |
5223 | |
5224 pipe_class simple_call(method meth) %{ | |
5225 instruction_count(2); multiple_bundles; force_serialization; | |
5226 fixed_latency(100); | |
5227 BR : R(1); | |
5228 MS : R(1); | |
5229 A0 : R(1); | |
5230 %} | |
5231 | |
5232 pipe_class compiled_call(method meth) %{ | |
5233 instruction_count(1); multiple_bundles; force_serialization; | |
5234 fixed_latency(100); | |
5235 MS : R(1); | |
5236 %} | |
5237 | |
5238 pipe_class call(method meth) %{ | |
5239 instruction_count(0); multiple_bundles; force_serialization; | |
5240 fixed_latency(100); | |
5241 %} | |
5242 | |
5243 pipe_class tail_call(Universe ignore, label labl) %{ | |
5244 single_instruction; has_delay_slot; | |
5245 fixed_latency(100); | |
5246 BR : R(1); | |
5247 MS : R(1); | |
5248 %} | |
5249 | |
5250 pipe_class ret(Universe ignore) %{ | |
5251 single_instruction; has_delay_slot; | |
5252 BR : R(1); | |
5253 MS : R(1); | |
5254 %} | |
5255 | |
5256 pipe_class ret_poll(g3RegP poll) %{ | |
5257 instruction_count(3); has_delay_slot; | |
5258 poll : E(read); | |
5259 MS : R; | |
5260 %} | |
5261 | |
5262 // The real do-nothing guy | |
5263 pipe_class empty( ) %{ | |
5264 instruction_count(0); | |
5265 %} | |
5266 | |
5267 pipe_class long_memory_op() %{ | |
5268 instruction_count(0); multiple_bundles; force_serialization; | |
5269 fixed_latency(25); | |
5270 MS : R(1); | |
5271 %} | |
5272 | |
5273 // Check-cast | |
5274 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
5275 array : R(read); | |
5276 match : R(read); | |
5277 IALU : R(2); | |
5278 BR : R(2); | |
5279 MS : R; | |
5280 %} | |
5281 | |
5282 // Convert FPU flags into +1,0,-1 | |
5283 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
5284 src1 : E(read); | |
5285 src2 : E(read); | |
5286 dst : E(write); | |
5287 FA : R; | |
5288 MS : R(2); | |
5289 BR : R(2); | |
5290 %} | |
5291 | |
5292 // Compare for p < q, and conditionally add y | |
5293 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
5294 p : E(read); | |
5295 q : E(read); | |
5296 y : E(read); | |
5297 IALU : R(3) | |
5298 %} | |
5299 | |
5300 // Perform a compare, then move conditionally in a branch delay slot. | |
5301 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
5302 src2 : E(read); | |
5303 srcdst : E(read); | |
5304 IALU : R; | |
5305 BR : R; | |
5306 %} | |
5307 | |
5308 // Define the class for the Nop node | |
5309 define %{ | |
5310 MachNop = ialu_nop; | |
5311 %} | |
5312 | |
5313 %} | |
5314 | |
5315 //----------INSTRUCTIONS------------------------------------------------------- | |
5316 | |
5317 //------------Special Stack Slot instructions - no match rules----------------- | |
5318 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
5319 // No match rule to avoid chain rule match. | |
5320 effect(DEF dst, USE src); | |
5321 ins_cost(MEMORY_REF_COST); | |
5322 size(4); | |
5323 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
5324 opcode(Assembler::ldf_op3); | |
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5325 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5326 ins_pipe(floadF_stk); |
5327 %} | |
5328 | |
5329 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
5330 // No match rule to avoid chain rule match. | |
5331 effect(DEF dst, USE src); | |
5332 ins_cost(MEMORY_REF_COST); | |
5333 size(4); | |
5334 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
5335 opcode(Assembler::lddf_op3); | |
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5336 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5337 ins_pipe(floadD_stk); |
5338 %} | |
5339 | |
5340 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
5341 // No match rule to avoid chain rule match. | |
5342 effect(DEF dst, USE src); | |
5343 ins_cost(MEMORY_REF_COST); | |
5344 size(4); | |
5345 format %{ "STF $src,$dst\t! regF to stkI" %} | |
5346 opcode(Assembler::stf_op3); | |
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5347 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5348 ins_pipe(fstoreF_stk_reg); |
5349 %} | |
5350 | |
5351 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
5352 // No match rule to avoid chain rule match. | |
5353 effect(DEF dst, USE src); | |
5354 ins_cost(MEMORY_REF_COST); | |
5355 size(4); | |
5356 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
5357 opcode(Assembler::stdf_op3); | |
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5358 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5359 ins_pipe(fstoreD_stk_reg); |
5360 %} | |
5361 | |
5362 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
5363 effect(DEF dst, USE src); | |
5364 ins_cost(MEMORY_REF_COST*2); | |
5365 size(8); | |
5366 format %{ "STW $src,$dst.hi\t! long\n\t" | |
5367 "STW R_G0,$dst.lo" %} | |
5368 opcode(Assembler::stw_op3); | |
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5369 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
0 | 5370 ins_pipe(lstoreI_stk_reg); |
5371 %} | |
5372 | |
5373 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
5374 // No match rule to avoid chain rule match. | |
5375 effect(DEF dst, USE src); | |
5376 ins_cost(MEMORY_REF_COST); | |
5377 size(4); | |
5378 format %{ "STX $src,$dst\t! regL to stkD" %} | |
5379 opcode(Assembler::stx_op3); | |
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5380 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5381 ins_pipe(istore_stk_reg); |
5382 %} | |
5383 | |
5384 //---------- Chain stack slots between similar types -------- | |
5385 | |
5386 // Load integer from stack slot | |
5387 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
5388 match(Set dst src); | |
5389 ins_cost(MEMORY_REF_COST); | |
5390 | |
5391 size(4); | |
5392 format %{ "LDUW $src,$dst\t!stk" %} | |
5393 opcode(Assembler::lduw_op3); | |
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5394 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5395 ins_pipe(iload_mem); |
5396 %} | |
5397 | |
5398 // Store integer to stack slot | |
5399 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
5400 match(Set dst src); | |
5401 ins_cost(MEMORY_REF_COST); | |
5402 | |
5403 size(4); | |
5404 format %{ "STW $src,$dst\t!stk" %} | |
5405 opcode(Assembler::stw_op3); | |
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5406 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5407 ins_pipe(istore_mem_reg); |
5408 %} | |
5409 | |
5410 // Load long from stack slot | |
5411 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
5412 match(Set dst src); | |
5413 | |
5414 ins_cost(MEMORY_REF_COST); | |
5415 size(4); | |
5416 format %{ "LDX $src,$dst\t! long" %} | |
5417 opcode(Assembler::ldx_op3); | |
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5418 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5419 ins_pipe(iload_mem); |
5420 %} | |
5421 | |
5422 // Store long to stack slot | |
5423 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
5424 match(Set dst src); | |
5425 | |
5426 ins_cost(MEMORY_REF_COST); | |
5427 size(4); | |
5428 format %{ "STX $src,$dst\t! long" %} | |
5429 opcode(Assembler::stx_op3); | |
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5430 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5431 ins_pipe(istore_mem_reg); |
5432 %} | |
5433 | |
5434 #ifdef _LP64 | |
5435 // Load pointer from stack slot, 64-bit encoding | |
5436 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5437 match(Set dst src); | |
5438 ins_cost(MEMORY_REF_COST); | |
5439 size(4); | |
5440 format %{ "LDX $src,$dst\t!ptr" %} | |
5441 opcode(Assembler::ldx_op3); | |
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5442 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5443 ins_pipe(iload_mem); |
5444 %} | |
5445 | |
5446 // Store pointer to stack slot | |
5447 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5448 match(Set dst src); | |
5449 ins_cost(MEMORY_REF_COST); | |
5450 size(4); | |
5451 format %{ "STX $src,$dst\t!ptr" %} | |
5452 opcode(Assembler::stx_op3); | |
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5453 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5454 ins_pipe(istore_mem_reg); |
5455 %} | |
5456 #else // _LP64 | |
5457 // Load pointer from stack slot, 32-bit encoding | |
5458 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5459 match(Set dst src); | |
5460 ins_cost(MEMORY_REF_COST); | |
5461 format %{ "LDUW $src,$dst\t!ptr" %} | |
5462 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
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5463 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5464 ins_pipe(iload_mem); |
5465 %} | |
5466 | |
5467 // Store pointer to stack slot | |
5468 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5469 match(Set dst src); | |
5470 ins_cost(MEMORY_REF_COST); | |
5471 format %{ "STW $src,$dst\t!ptr" %} | |
5472 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
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5473 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5474 ins_pipe(istore_mem_reg); |
5475 %} | |
5476 #endif // _LP64 | |
5477 | |
5478 //------------Special Nop instructions for bundling - no match rules----------- | |
5479 // Nop using the A0 functional unit | |
5480 instruct Nop_A0() %{ | |
5481 ins_cost(0); | |
5482 | |
5483 format %{ "NOP ! Alu Pipeline" %} | |
5484 opcode(Assembler::or_op3, Assembler::arith_op); | |
5485 ins_encode( form2_nop() ); | |
5486 ins_pipe(ialu_nop_A0); | |
5487 %} | |
5488 | |
5489 // Nop using the A1 functional unit | |
5490 instruct Nop_A1( ) %{ | |
5491 ins_cost(0); | |
5492 | |
5493 format %{ "NOP ! Alu Pipeline" %} | |
5494 opcode(Assembler::or_op3, Assembler::arith_op); | |
5495 ins_encode( form2_nop() ); | |
5496 ins_pipe(ialu_nop_A1); | |
5497 %} | |
5498 | |
5499 // Nop using the memory functional unit | |
5500 instruct Nop_MS( ) %{ | |
5501 ins_cost(0); | |
5502 | |
5503 format %{ "NOP ! Memory Pipeline" %} | |
5504 ins_encode( emit_mem_nop ); | |
5505 ins_pipe(mem_nop); | |
5506 %} | |
5507 | |
5508 // Nop using the floating add functional unit | |
5509 instruct Nop_FA( ) %{ | |
5510 ins_cost(0); | |
5511 | |
5512 format %{ "NOP ! Floating Add Pipeline" %} | |
5513 ins_encode( emit_fadd_nop ); | |
5514 ins_pipe(fadd_nop); | |
5515 %} | |
5516 | |
5517 // Nop using the branch functional unit | |
5518 instruct Nop_BR( ) %{ | |
5519 ins_cost(0); | |
5520 | |
5521 format %{ "NOP ! Branch Pipeline" %} | |
5522 ins_encode( emit_br_nop ); | |
5523 ins_pipe(br_nop); | |
5524 %} | |
5525 | |
5526 //----------Load/Store/Move Instructions--------------------------------------- | |
5527 //----------Load Instructions-------------------------------------------------- | |
5528 // Load Byte (8bit signed) | |
5529 instruct loadB(iRegI dst, memory mem) %{ | |
5530 match(Set dst (LoadB mem)); | |
5531 ins_cost(MEMORY_REF_COST); | |
5532 | |
5533 size(4); | |
624 | 5534 format %{ "LDSB $mem,$dst\t! byte" %} |
727 | 5535 ins_encode %{ |
5536 __ ldsb($mem$$Address, $dst$$Register); | |
5537 %} | |
624 | 5538 ins_pipe(iload_mask_mem); |
5539 %} | |
5540 | |
5541 // Load Byte (8bit signed) into a Long Register | |
5542 instruct loadB2L(iRegL dst, memory mem) %{ | |
5543 match(Set dst (ConvI2L (LoadB mem))); | |
5544 ins_cost(MEMORY_REF_COST); | |
5545 | |
5546 size(4); | |
5547 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
727 | 5548 ins_encode %{ |
5549 __ ldsb($mem$$Address, $dst$$Register); | |
5550 %} | |
0 | 5551 ins_pipe(iload_mask_mem); |
5552 %} | |
5553 | |
624 | 5554 // Load Unsigned Byte (8bit UNsigned) into an int reg |
5555 instruct loadUB(iRegI dst, memory mem) %{ | |
5556 match(Set dst (LoadUB mem)); | |
0 | 5557 ins_cost(MEMORY_REF_COST); |
5558 | |
5559 size(4); | |
624 | 5560 format %{ "LDUB $mem,$dst\t! ubyte" %} |
727 | 5561 ins_encode %{ |
5562 __ ldub($mem$$Address, $dst$$Register); | |
5563 %} | |
824 | 5564 ins_pipe(iload_mem); |
624 | 5565 %} |
5566 | |
5567 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
5568 instruct loadUB2L(iRegL dst, memory mem) %{ | |
5569 match(Set dst (ConvI2L (LoadUB mem))); | |
5570 ins_cost(MEMORY_REF_COST); | |
5571 | |
5572 size(4); | |
5573 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
727 | 5574 ins_encode %{ |
5575 __ ldub($mem$$Address, $dst$$Register); | |
5576 %} | |
824 | 5577 ins_pipe(iload_mem); |
5578 %} | |
5579 | |
5580 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register | |
5581 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ | |
5582 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
5583 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5584 | |
5585 size(2*4); | |
5586 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" | |
5587 "AND $dst,$mask,$dst" %} | |
5588 ins_encode %{ | |
5589 __ ldub($mem$$Address, $dst$$Register); | |
5590 __ and3($dst$$Register, $mask$$constant, $dst$$Register); | |
5591 %} | |
5592 ins_pipe(iload_mem); | |
0 | 5593 %} |
5594 | |
624 | 5595 // Load Short (16bit signed) |
5596 instruct loadS(iRegI dst, memory mem) %{ | |
5597 match(Set dst (LoadS mem)); | |
5598 ins_cost(MEMORY_REF_COST); | |
5599 | |
5600 size(4); | |
5601 format %{ "LDSH $mem,$dst\t! short" %} | |
727 | 5602 ins_encode %{ |
5603 __ ldsh($mem$$Address, $dst$$Register); | |
5604 %} | |
624 | 5605 ins_pipe(iload_mask_mem); |
5606 %} | |
5607 | |
785 | 5608 // Load Short (16 bit signed) to Byte (8 bit signed) |
5609 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5610 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
5611 ins_cost(MEMORY_REF_COST); | |
5612 | |
5613 size(4); | |
5614 | |
5615 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} | |
5616 ins_encode %{ | |
5617 __ ldsb($mem$$Address, $dst$$Register, 1); | |
5618 %} | |
5619 ins_pipe(iload_mask_mem); | |
5620 %} | |
5621 | |
624 | 5622 // Load Short (16bit signed) into a Long Register |
5623 instruct loadS2L(iRegL dst, memory mem) %{ | |
5624 match(Set dst (ConvI2L (LoadS mem))); | |
0 | 5625 ins_cost(MEMORY_REF_COST); |
5626 | |
5627 size(4); | |
624 | 5628 format %{ "LDSH $mem,$dst\t! short -> long" %} |
727 | 5629 ins_encode %{ |
5630 __ ldsh($mem$$Address, $dst$$Register); | |
5631 %} | |
624 | 5632 ins_pipe(iload_mask_mem); |
5633 %} | |
5634 | |
5635 // Load Unsigned Short/Char (16bit UNsigned) | |
5636 instruct loadUS(iRegI dst, memory mem) %{ | |
5637 match(Set dst (LoadUS mem)); | |
5638 ins_cost(MEMORY_REF_COST); | |
5639 | |
5640 size(4); | |
5641 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
727 | 5642 ins_encode %{ |
5643 __ lduh($mem$$Address, $dst$$Register); | |
5644 %} | |
824 | 5645 ins_pipe(iload_mem); |
0 | 5646 %} |
5647 | |
785 | 5648 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
5649 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5650 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
5651 ins_cost(MEMORY_REF_COST); | |
5652 | |
5653 size(4); | |
5654 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} | |
5655 ins_encode %{ | |
5656 __ ldsb($mem$$Address, $dst$$Register, 1); | |
5657 %} | |
5658 ins_pipe(iload_mask_mem); | |
5659 %} | |
5660 | |
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|
5661 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
624 | 5662 instruct loadUS2L(iRegL dst, memory mem) %{ |
5663 match(Set dst (ConvI2L (LoadUS mem))); | |
0 | 5664 ins_cost(MEMORY_REF_COST); |
5665 | |
5666 size(4); | |
624 | 5667 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
727 | 5668 ins_encode %{ |
5669 __ lduh($mem$$Address, $dst$$Register); | |
5670 %} | |
824 | 5671 ins_pipe(iload_mem); |
5672 %} | |
5673 | |
5674 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register | |
5675 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
5676 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5677 ins_cost(MEMORY_REF_COST); | |
5678 | |
5679 size(4); | |
5680 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} | |
5681 ins_encode %{ | |
5682 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE | |
5683 %} | |
5684 ins_pipe(iload_mem); | |
5685 %} | |
5686 | |
5687 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register | |
5688 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
5689 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5690 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5691 | |
5692 size(2*4); | |
5693 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" | |
5694 "AND $dst,$mask,$dst" %} | |
5695 ins_encode %{ | |
5696 Register Rdst = $dst$$Register; | |
5697 __ lduh($mem$$Address, Rdst); | |
5698 __ and3(Rdst, $mask$$constant, Rdst); | |
5699 %} | |
5700 ins_pipe(iload_mem); | |
5701 %} | |
5702 | |
5703 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register | |
5704 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | |
5705 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5706 effect(TEMP dst, TEMP tmp); | |
5707 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
5708 | |
951
1fbd5d696bf4
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824
diff
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|
5709 size((3+1)*4); // set may use two instructions. |
824 | 5710 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
5711 "SET $mask,$tmp\n\t" | |
5712 "AND $dst,$tmp,$dst" %} | |
5713 ins_encode %{ | |
5714 Register Rdst = $dst$$Register; | |
5715 Register Rtmp = $tmp$$Register; | |
5716 __ lduh($mem$$Address, Rdst); | |
5717 __ set($mask$$constant, Rtmp); | |
5718 __ and3(Rdst, Rtmp, Rdst); | |
5719 %} | |
5720 ins_pipe(iload_mem); | |
0 | 5721 %} |
5722 | |
5723 // Load Integer | |
5724 instruct loadI(iRegI dst, memory mem) %{ | |
5725 match(Set dst (LoadI mem)); | |
5726 ins_cost(MEMORY_REF_COST); | |
624 | 5727 |
5728 size(4); | |
5729 format %{ "LDUW $mem,$dst\t! int" %} | |
727 | 5730 ins_encode %{ |
5731 __ lduw($mem$$Address, $dst$$Register); | |
5732 %} | |
624 | 5733 ins_pipe(iload_mem); |
5734 %} | |
5735 | |
785 | 5736 // Load Integer to Byte (8 bit signed) |
5737 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5738 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
5739 ins_cost(MEMORY_REF_COST); | |
5740 | |
5741 size(4); | |
5742 | |
5743 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} | |
5744 ins_encode %{ | |
5745 __ ldsb($mem$$Address, $dst$$Register, 3); | |
5746 %} | |
5747 ins_pipe(iload_mask_mem); | |
5748 %} | |
5749 | |
5750 // Load Integer to Unsigned Byte (8 bit UNsigned) | |
5751 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ | |
5752 match(Set dst (AndI (LoadI mem) mask)); | |
5753 ins_cost(MEMORY_REF_COST); | |
5754 | |
5755 size(4); | |
5756 | |
5757 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} | |
5758 ins_encode %{ | |
5759 __ ldub($mem$$Address, $dst$$Register, 3); | |
5760 %} | |
5761 ins_pipe(iload_mask_mem); | |
5762 %} | |
5763 | |
5764 // Load Integer to Short (16 bit signed) | |
5765 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ | |
5766 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
5767 ins_cost(MEMORY_REF_COST); | |
5768 | |
5769 size(4); | |
5770 | |
5771 format %{ "LDSH $mem+2,$dst\t! int -> short" %} | |
5772 ins_encode %{ | |
5773 __ ldsh($mem$$Address, $dst$$Register, 2); | |
5774 %} | |
5775 ins_pipe(iload_mask_mem); | |
5776 %} | |
5777 | |
5778 // Load Integer to Unsigned Short (16 bit UNsigned) | |
5779 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ | |
5780 match(Set dst (AndI (LoadI mem) mask)); | |
5781 ins_cost(MEMORY_REF_COST); | |
5782 | |
5783 size(4); | |
5784 | |
5785 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} | |
5786 ins_encode %{ | |
5787 __ lduh($mem$$Address, $dst$$Register, 2); | |
5788 %} | |
5789 ins_pipe(iload_mask_mem); | |
5790 %} | |
5791 | |
624 | 5792 // Load Integer into a Long Register |
5793 instruct loadI2L(iRegL dst, memory mem) %{ | |
5794 match(Set dst (ConvI2L (LoadI mem))); | |
5795 ins_cost(MEMORY_REF_COST); | |
5796 | |
5797 size(4); | |
5798 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
727 | 5799 ins_encode %{ |
5800 __ ldsw($mem$$Address, $dst$$Register); | |
5801 %} | |
824 | 5802 ins_pipe(iload_mask_mem); |
5803 %} | |
5804 | |
5805 // Load Integer with mask 0xFF into a Long Register | |
5806 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
5807 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5808 ins_cost(MEMORY_REF_COST); | |
5809 | |
5810 size(4); | |
5811 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} | |
5812 ins_encode %{ | |
5813 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE | |
5814 %} | |
5815 ins_pipe(iload_mem); | |
5816 %} | |
5817 | |
5818 // Load Integer with mask 0xFFFF into a Long Register | |
5819 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ | |
5820 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5821 ins_cost(MEMORY_REF_COST); | |
5822 | |
5823 size(4); | |
5824 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} | |
5825 ins_encode %{ | |
5826 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | |
5827 %} | |
5828 ins_pipe(iload_mem); | |
5829 %} | |
5830 | |
5831 // Load Integer with a 13-bit mask into a Long Register | |
5832 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
5833 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5834 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5835 | |
5836 size(2*4); | |
5837 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" | |
5838 "AND $dst,$mask,$dst" %} | |
5839 ins_encode %{ | |
5840 Register Rdst = $dst$$Register; | |
5841 __ lduw($mem$$Address, Rdst); | |
5842 __ and3(Rdst, $mask$$constant, Rdst); | |
5843 %} | |
5844 ins_pipe(iload_mem); | |
5845 %} | |
5846 | |
5847 // Load Integer with a 32-bit mask into a Long Register | |
5848 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ | |
5849 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5850 effect(TEMP dst, TEMP tmp); | |
5851 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
5852 | |
951
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|
5853 size((3+1)*4); // set may use two instructions. |
824 | 5854 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" |
5855 "SET $mask,$tmp\n\t" | |
5856 "AND $dst,$tmp,$dst" %} | |
5857 ins_encode %{ | |
5858 Register Rdst = $dst$$Register; | |
5859 Register Rtmp = $tmp$$Register; | |
5860 __ lduw($mem$$Address, Rdst); | |
5861 __ set($mask$$constant, Rtmp); | |
5862 __ and3(Rdst, Rtmp, Rdst); | |
5863 %} | |
624 | 5864 ins_pipe(iload_mem); |
5865 %} | |
5866 | |
5867 // Load Unsigned Integer into a Long Register | |
5868 instruct loadUI2L(iRegL dst, memory mem) %{ | |
5869 match(Set dst (LoadUI2L mem)); | |
5870 ins_cost(MEMORY_REF_COST); | |
5871 | |
5872 size(4); | |
5873 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
727 | 5874 ins_encode %{ |
5875 __ lduw($mem$$Address, $dst$$Register); | |
5876 %} | |
0 | 5877 ins_pipe(iload_mem); |
5878 %} | |
5879 | |
5880 // Load Long - aligned | |
5881 instruct loadL(iRegL dst, memory mem ) %{ | |
5882 match(Set dst (LoadL mem)); | |
5883 ins_cost(MEMORY_REF_COST); | |
624 | 5884 |
0 | 5885 size(4); |
5886 format %{ "LDX $mem,$dst\t! long" %} | |
727 | 5887 ins_encode %{ |
5888 __ ldx($mem$$Address, $dst$$Register); | |
5889 %} | |
0 | 5890 ins_pipe(iload_mem); |
5891 %} | |
5892 | |
5893 // Load Long - UNaligned | |
5894 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
5895 match(Set dst (LoadL_unaligned mem)); | |
5896 effect(KILL tmp); | |
5897 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
5898 size(16); | |
5899 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
5900 "\tLDUW $mem ,$dst\n" | |
5901 "\tSLLX #32, $dst, $dst\n" | |
5902 "\tOR $dst, R_O7, $dst" %} | |
5903 opcode(Assembler::lduw_op3); | |
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235
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|
5904 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
0 | 5905 ins_pipe(iload_mem); |
5906 %} | |
5907 | |
5908 // Load Range | |
5909 instruct loadRange(iRegI dst, memory mem) %{ | |
5910 match(Set dst (LoadRange mem)); | |
5911 ins_cost(MEMORY_REF_COST); | |
5912 | |
5913 size(4); | |
5914 format %{ "LDUW $mem,$dst\t! range" %} | |
5915 opcode(Assembler::lduw_op3); | |
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235
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|
5916 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5917 ins_pipe(iload_mem); |
5918 %} | |
5919 | |
5920 // Load Integer into %f register (for fitos/fitod) | |
5921 instruct loadI_freg(regF dst, memory mem) %{ | |
5922 match(Set dst (LoadI mem)); | |
5923 ins_cost(MEMORY_REF_COST); | |
5924 size(4); | |
5925 | |
5926 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
5927 opcode(Assembler::ldf_op3); | |
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235
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|
5928 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5929 ins_pipe(floadF_mem); |
5930 %} | |
5931 | |
5932 // Load Pointer | |
5933 instruct loadP(iRegP dst, memory mem) %{ | |
5934 match(Set dst (LoadP mem)); | |
5935 ins_cost(MEMORY_REF_COST); | |
5936 size(4); | |
5937 | |
5938 #ifndef _LP64 | |
5939 format %{ "LDUW $mem,$dst\t! ptr" %} | |
727 | 5940 ins_encode %{ |
5941 __ lduw($mem$$Address, $dst$$Register); | |
5942 %} | |
0 | 5943 #else |
5944 format %{ "LDX $mem,$dst\t! ptr" %} | |
727 | 5945 ins_encode %{ |
5946 __ ldx($mem$$Address, $dst$$Register); | |
5947 %} | |
0 | 5948 #endif |
5949 ins_pipe(iload_mem); | |
5950 %} | |
5951 | |
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|
5952 // Load Compressed Pointer |
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5953 instruct loadN(iRegN dst, memory mem) %{ |
727 | 5954 match(Set dst (LoadN mem)); |
5955 ins_cost(MEMORY_REF_COST); | |
5956 size(4); | |
5957 | |
5958 format %{ "LDUW $mem,$dst\t! compressed ptr" %} | |
5959 ins_encode %{ | |
5960 __ lduw($mem$$Address, $dst$$Register); | |
5961 %} | |
5962 ins_pipe(iload_mem); | |
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|
5963 %} |
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|
5964 |
0 | 5965 // Load Klass Pointer |
5966 instruct loadKlass(iRegP dst, memory mem) %{ | |
5967 match(Set dst (LoadKlass mem)); | |
5968 ins_cost(MEMORY_REF_COST); | |
5969 size(4); | |
5970 | |
5971 #ifndef _LP64 | |
5972 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
727 | 5973 ins_encode %{ |
5974 __ lduw($mem$$Address, $dst$$Register); | |
5975 %} | |
0 | 5976 #else |
5977 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
727 | 5978 ins_encode %{ |
5979 __ ldx($mem$$Address, $dst$$Register); | |
5980 %} | |
0 | 5981 #endif |
5982 ins_pipe(iload_mem); | |
5983 %} | |
5984 | |
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|
5985 // Load narrow Klass Pointer |
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5986 instruct loadNKlass(iRegN dst, memory mem) %{ |
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5987 match(Set dst (LoadNKlass mem)); |
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5988 ins_cost(MEMORY_REF_COST); |
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5989 size(4); |
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|
5990 |
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|
5991 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
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5992 ins_encode %{ |
727 | 5993 __ lduw($mem$$Address, $dst$$Register); |
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5994 %} |
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|
5995 ins_pipe(iload_mem); |
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|
5996 %} |
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|
5997 |
0 | 5998 // Load Double |
5999 instruct loadD(regD dst, memory mem) %{ | |
6000 match(Set dst (LoadD mem)); | |
6001 ins_cost(MEMORY_REF_COST); | |
6002 | |
6003 size(4); | |
6004 format %{ "LDDF $mem,$dst" %} | |
6005 opcode(Assembler::lddf_op3); | |
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6006 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 6007 ins_pipe(floadD_mem); |
6008 %} | |
6009 | |
6010 // Load Double - UNaligned | |
6011 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
6012 match(Set dst (LoadD_unaligned mem)); | |
6013 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
6014 size(8); | |
6015 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
6016 "\tLDF $mem+4,$dst.lo\t!" %} | |
6017 opcode(Assembler::ldf_op3); | |
6018 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
6019 ins_pipe(iload_mem); | |
6020 %} | |
6021 | |
6022 // Load Float | |
6023 instruct loadF(regF dst, memory mem) %{ | |
6024 match(Set dst (LoadF mem)); | |
6025 ins_cost(MEMORY_REF_COST); | |
6026 | |
6027 size(4); | |
6028 format %{ "LDF $mem,$dst" %} | |
6029 opcode(Assembler::ldf_op3); | |
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6030 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 6031 ins_pipe(floadF_mem); |
6032 %} | |
6033 | |
6034 // Load Constant | |
6035 instruct loadConI( iRegI dst, immI src ) %{ | |
6036 match(Set dst src); | |
6037 ins_cost(DEFAULT_COST * 3/2); | |
6038 format %{ "SET $src,$dst" %} | |
6039 ins_encode( Set32(src, dst) ); | |
6040 ins_pipe(ialu_hi_lo_reg); | |
6041 %} | |
6042 | |
6043 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
6044 match(Set dst src); | |
6045 | |
6046 size(4); | |
6047 format %{ "MOV $src,$dst" %} | |
6048 ins_encode( Set13( src, dst ) ); | |
6049 ins_pipe(ialu_imm); | |
6050 %} | |
6051 | |
2008 | 6052 #ifndef _LP64 |
6053 instruct loadConP(iRegP dst, immP con) %{ | |
6054 match(Set dst con); | |
6055 ins_cost(DEFAULT_COST * 3/2); | |
6056 format %{ "SET $con,$dst\t!ptr" %} | |
6057 ins_encode %{ | |
6725
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6058 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); |
2008 | 6059 intptr_t val = $con$$constant; |
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6060 if (constant_reloc == relocInfo::oop_type) { |
2008 | 6061 __ set_oop_constant((jobject) val, $dst$$Register); |
6725
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6179
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|
6062 } else if (constant_reloc == relocInfo::metadata_type) { |
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6179
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changeset
|
6063 __ set_metadata_constant((Metadata*)val, $dst$$Register); |
2008 | 6064 } else { // non-oop pointers, e.g. card mark base, heap top |
6725
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6179
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|
6065 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); |
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|
6066 __ set(val, $dst$$Register); |
2008 | 6067 } |
6068 %} | |
6069 ins_pipe(loadConP); | |
6070 %} | |
6071 #else | |
6072 instruct loadConP_set(iRegP dst, immP_set con) %{ | |
6073 match(Set dst con); | |
0 | 6074 ins_cost(DEFAULT_COST * 3/2); |
2008 | 6075 format %{ "SET $con,$dst\t! ptr" %} |
6076 ins_encode %{ | |
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|
6077 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); |
2008 | 6078 intptr_t val = $con$$constant; |
6725
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|
6079 if (constant_reloc == relocInfo::oop_type) { |
2008 | 6080 __ set_oop_constant((jobject) val, $dst$$Register); |
6725
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|
6081 } else if (constant_reloc == relocInfo::metadata_type) { |
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6179
diff
changeset
|
6082 __ set_metadata_constant((Metadata*)val, $dst$$Register); |
2008 | 6083 } else { // non-oop pointers, e.g. card mark base, heap top |
6725
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diff
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|
6084 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); |
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|
6085 __ set(val, $dst$$Register); |
2008 | 6086 } |
6087 %} | |
0 | 6088 ins_pipe(loadConP); |
2008 | 6089 %} |
6090 | |
6091 instruct loadConP_load(iRegP dst, immP_load con) %{ | |
6092 match(Set dst con); | |
6093 ins_cost(MEMORY_REF_COST); | |
6094 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} | |
6095 ins_encode %{ | |
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changeset
|
6096 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
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diff
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|
6097 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); |
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|
6098 %} |
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changeset
|
6099 ins_pipe(loadConP); |
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|
6100 %} |
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|
6101 |
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diff
changeset
|
6102 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ |
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diff
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|
6103 match(Set dst con); |
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|
6104 ins_cost(DEFAULT_COST * 3/2); |
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twisti
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diff
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|
6105 format %{ "SET $con,$dst\t! non-oop ptr" %} |
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diff
changeset
|
6106 ins_encode %{ |
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|
6107 __ set($con$$constant, $dst$$Register); |
2008 | 6108 %} |
6109 ins_pipe(loadConP); | |
6110 %} | |
6111 #endif // _LP64 | |
0 | 6112 |
6113 instruct loadConP0(iRegP dst, immP0 src) %{ | |
6114 match(Set dst src); | |
6115 | |
6116 size(4); | |
6117 format %{ "CLR $dst\t!ptr" %} | |
2008 | 6118 ins_encode %{ |
6119 __ clr($dst$$Register); | |
6120 %} | |
0 | 6121 ins_pipe(ialu_imm); |
6122 %} | |
6123 | |
6124 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
6125 match(Set dst src); | |
6126 ins_cost(DEFAULT_COST); | |
6127 format %{ "SET $src,$dst\t!ptr" %} | |
6128 ins_encode %{ | |
727 | 6129 AddressLiteral polling_page(os::get_polling_page()); |
6130 __ sethi(polling_page, reg_to_register_object($dst$$reg)); | |
0 | 6131 %} |
6132 ins_pipe(loadConP_poll); | |
6133 %} | |
6134 | |
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6135 instruct loadConN0(iRegN dst, immN0 src) %{ |
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6136 match(Set dst src); |
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|
6137 |
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|
6138 size(4); |
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6139 format %{ "CLR $dst\t! compressed NULL ptr" %} |
2008 | 6140 ins_encode %{ |
6141 __ clr($dst$$Register); | |
6142 %} | |
164
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|
6143 ins_pipe(ialu_imm); |
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|
6144 %} |
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|
6145 |
113
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|
6146 instruct loadConN(iRegN dst, immN src) %{ |
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diff
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|
6147 match(Set dst src); |
164
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|
6148 ins_cost(DEFAULT_COST * 3/2); |
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|
6149 format %{ "SET $src,$dst\t! compressed ptr" %} |
113
ba764ed4b6f2
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|
6150 ins_encode %{ |
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|
6151 Register dst = $dst$$Register; |
164
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|
6152 __ set_narrow_oop((jobject)$src$$constant, dst); |
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|
6153 %} |
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|
6154 ins_pipe(ialu_hi_lo_reg); |
113
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|
6155 %} |
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|
6156 |
2008 | 6157 // Materialize long value (predicated by immL_cheap). |
6158 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ | |
6159 match(Set dst con); | |
0 | 6160 effect(KILL tmp); |
2008 | 6161 ins_cost(DEFAULT_COST * 3); |
6162 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} | |
6163 ins_encode %{ | |
6164 __ set64($con$$constant, $dst$$Register, $tmp$$Register); | |
6165 %} | |
6166 ins_pipe(loadConL); | |
6167 %} | |
6168 | |
6169 // Load long value from constant table (predicated by immL_expensive). | |
6170 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ | |
6171 match(Set dst con); | |
6172 ins_cost(MEMORY_REF_COST); | |
6173 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} | |
6174 ins_encode %{ | |
2012
5fe0781a8560
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kvn
parents:
2008
diff
changeset
|
6175 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
5fe0781a8560
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kvn
parents:
2008
diff
changeset
|
6176 __ ldx($constanttablebase, con_offset, $dst$$Register); |
2008 | 6177 %} |
0 | 6178 ins_pipe(loadConL); |
6179 %} | |
6180 | |
6181 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
6182 match(Set dst src); | |
6183 ins_cost(DEFAULT_COST); | |
6184 size(4); | |
6185 format %{ "CLR $dst\t! long" %} | |
6186 ins_encode( Set13( src, dst ) ); | |
6187 ins_pipe(ialu_imm); | |
6188 %} | |
6189 | |
6190 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
6191 match(Set dst src); | |
6192 ins_cost(DEFAULT_COST * 2); | |
6193 | |
6194 size(4); | |
6195 format %{ "MOV $src,$dst\t! long" %} | |
6196 ins_encode( Set13( src, dst ) ); | |
6197 ins_pipe(ialu_imm); | |
6198 %} | |
6199 | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6200 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ |
2008 | 6201 match(Set dst con); |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6202 effect(KILL tmp); |
2008 | 6203 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} |
727 | 6204 ins_encode %{ |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6205 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
5fe0781a8560
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kvn
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2008
diff
changeset
|
6206 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); |
727 | 6207 %} |
0 | 6208 ins_pipe(loadConFD); |
6209 %} | |
6210 | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6211 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ |
2008 | 6212 match(Set dst con); |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6213 effect(KILL tmp); |
2008 | 6214 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} |
727 | 6215 ins_encode %{ |
732
fb4c18a2ec66
6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents:
727
diff
changeset
|
6216 // XXX This is a quick fix for 6833573. |
2008 | 6217 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); |
2012
5fe0781a8560
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diff
changeset
|
6218 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
5fe0781a8560
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kvn
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2008
diff
changeset
|
6219 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
727 | 6220 %} |
0 | 6221 ins_pipe(loadConFD); |
6222 %} | |
6223 | |
6224 // Prefetch instructions. | |
6225 // Must be safe to execute with invalid address (cannot fault). | |
6226 | |
6227 instruct prefetchr( memory mem ) %{ | |
6228 match( PrefetchRead mem ); | |
6229 ins_cost(MEMORY_REF_COST); | |
3854 | 6230 size(4); |
0 | 6231 |
6232 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
6233 opcode(Assembler::prefetch_op3); | |
6234 ins_encode( form3_mem_prefetch_read( mem ) ); | |
6235 ins_pipe(iload_mem); | |
6236 %} | |
6237 | |
6238 instruct prefetchw( memory mem ) %{ | |
6239 match( PrefetchWrite mem ); | |
6240 ins_cost(MEMORY_REF_COST); | |
3854 | 6241 size(4); |
0 | 6242 |
6243 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
6244 opcode(Assembler::prefetch_op3); | |
6245 ins_encode( form3_mem_prefetch_write( mem ) ); | |
6246 ins_pipe(iload_mem); | |
6247 %} | |
6248 | |
3854 | 6249 // Prefetch instructions for allocation. |
6250 | |
6251 instruct prefetchAlloc( memory mem ) %{ | |
6252 predicate(AllocatePrefetchInstr == 0); | |
6253 match( PrefetchAllocation mem ); | |
6254 ins_cost(MEMORY_REF_COST); | |
6255 size(4); | |
6256 | |
6257 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %} | |
6258 opcode(Assembler::prefetch_op3); | |
6259 ins_encode( form3_mem_prefetch_write( mem ) ); | |
6260 ins_pipe(iload_mem); | |
6261 %} | |
6262 | |
6263 // Use BIS instruction to prefetch for allocation. | |
6264 // Could fault, need space at the end of TLAB. | |
6265 instruct prefetchAlloc_bis( iRegP dst ) %{ | |
6266 predicate(AllocatePrefetchInstr == 1); | |
6267 match( PrefetchAllocation dst ); | |
6268 ins_cost(MEMORY_REF_COST); | |
6269 size(4); | |
6270 | |
6271 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %} | |
6272 ins_encode %{ | |
6273 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); | |
1367
9e321dcfa5b7
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1274
diff
changeset
|
6274 %} |
9e321dcfa5b7
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diff
changeset
|
6275 ins_pipe(istore_mem_reg); |
9e321dcfa5b7
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|
6276 %} |
0 | 6277 |
3854 | 6278 // Next code is used for finding next cache line address to prefetch. |
6279 #ifndef _LP64 | |
6280 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{ | |
6281 match(Set dst (CastX2P (AndI (CastP2X src) mask))); | |
6282 ins_cost(DEFAULT_COST); | |
6283 size(4); | |
6284 | |
6285 format %{ "AND $src,$mask,$dst\t! next cache line address" %} | |
6286 ins_encode %{ | |
6287 __ and3($src$$Register, $mask$$constant, $dst$$Register); | |
6288 %} | |
6289 ins_pipe(ialu_reg_imm); | |
6290 %} | |
6291 #else | |
6292 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{ | |
6293 match(Set dst (CastX2P (AndL (CastP2X src) mask))); | |
6294 ins_cost(DEFAULT_COST); | |
6295 size(4); | |
6296 | |
6297 format %{ "AND $src,$mask,$dst\t! next cache line address" %} | |
6298 ins_encode %{ | |
6299 __ and3($src$$Register, $mask$$constant, $dst$$Register); | |
6300 %} | |
6301 ins_pipe(ialu_reg_imm); | |
6302 %} | |
6303 #endif | |
6304 | |
0 | 6305 //----------Store Instructions------------------------------------------------- |
6306 // Store Byte | |
6307 instruct storeB(memory mem, iRegI src) %{ | |
6308 match(Set mem (StoreB mem src)); | |
6309 ins_cost(MEMORY_REF_COST); | |
6310 | |
6311 size(4); | |
6312 format %{ "STB $src,$mem\t! byte" %} | |
6313 opcode(Assembler::stb_op3); | |
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6314 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6315 ins_pipe(istore_mem_reg); |
6316 %} | |
6317 | |
6318 instruct storeB0(memory mem, immI0 src) %{ | |
6319 match(Set mem (StoreB mem src)); | |
6320 ins_cost(MEMORY_REF_COST); | |
6321 | |
6322 size(4); | |
6323 format %{ "STB $src,$mem\t! byte" %} | |
6324 opcode(Assembler::stb_op3); | |
415
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6325 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6326 ins_pipe(istore_mem_zero); |
6327 %} | |
6328 | |
6329 instruct storeCM0(memory mem, immI0 src) %{ | |
6330 match(Set mem (StoreCM mem src)); | |
6331 ins_cost(MEMORY_REF_COST); | |
6332 | |
6333 size(4); | |
6334 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
6335 opcode(Assembler::stb_op3); | |
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6336 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6337 ins_pipe(istore_mem_zero); |
6338 %} | |
6339 | |
6340 // Store Char/Short | |
6341 instruct storeC(memory mem, iRegI src) %{ | |
6342 match(Set mem (StoreC mem src)); | |
6343 ins_cost(MEMORY_REF_COST); | |
6344 | |
6345 size(4); | |
6346 format %{ "STH $src,$mem\t! short" %} | |
6347 opcode(Assembler::sth_op3); | |
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6348 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6349 ins_pipe(istore_mem_reg); |
6350 %} | |
6351 | |
6352 instruct storeC0(memory mem, immI0 src) %{ | |
6353 match(Set mem (StoreC mem src)); | |
6354 ins_cost(MEMORY_REF_COST); | |
6355 | |
6356 size(4); | |
6357 format %{ "STH $src,$mem\t! short" %} | |
6358 opcode(Assembler::sth_op3); | |
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6359 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6360 ins_pipe(istore_mem_zero); |
6361 %} | |
6362 | |
6363 // Store Integer | |
6364 instruct storeI(memory mem, iRegI src) %{ | |
6365 match(Set mem (StoreI mem src)); | |
6366 ins_cost(MEMORY_REF_COST); | |
6367 | |
6368 size(4); | |
6369 format %{ "STW $src,$mem" %} | |
6370 opcode(Assembler::stw_op3); | |
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6371 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6372 ins_pipe(istore_mem_reg); |
6373 %} | |
6374 | |
6375 // Store Long | |
6376 instruct storeL(memory mem, iRegL src) %{ | |
6377 match(Set mem (StoreL mem src)); | |
6378 ins_cost(MEMORY_REF_COST); | |
6379 size(4); | |
6380 format %{ "STX $src,$mem\t! long" %} | |
6381 opcode(Assembler::stx_op3); | |
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6382 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6383 ins_pipe(istore_mem_reg); |
6384 %} | |
6385 | |
6386 instruct storeI0(memory mem, immI0 src) %{ | |
6387 match(Set mem (StoreI mem src)); | |
6388 ins_cost(MEMORY_REF_COST); | |
6389 | |
6390 size(4); | |
6391 format %{ "STW $src,$mem" %} | |
6392 opcode(Assembler::stw_op3); | |
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6393 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6394 ins_pipe(istore_mem_zero); |
6395 %} | |
6396 | |
6397 instruct storeL0(memory mem, immL0 src) %{ | |
6398 match(Set mem (StoreL mem src)); | |
6399 ins_cost(MEMORY_REF_COST); | |
6400 | |
6401 size(4); | |
6402 format %{ "STX $src,$mem" %} | |
6403 opcode(Assembler::stx_op3); | |
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6404 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6405 ins_pipe(istore_mem_zero); |
6406 %} | |
6407 | |
6408 // Store Integer from float register (used after fstoi) | |
6409 instruct storeI_Freg(memory mem, regF src) %{ | |
6410 match(Set mem (StoreI mem src)); | |
6411 ins_cost(MEMORY_REF_COST); | |
6412 | |
6413 size(4); | |
6414 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
6415 opcode(Assembler::stf_op3); | |
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6416 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6417 ins_pipe(fstoreF_mem_reg); |
6418 %} | |
6419 | |
6420 // Store Pointer | |
6421 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
6422 match(Set dst (StoreP dst src)); | |
6423 ins_cost(MEMORY_REF_COST); | |
6424 size(4); | |
6425 | |
6426 #ifndef _LP64 | |
6427 format %{ "STW $src,$dst\t! ptr" %} | |
6428 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6429 #else | |
6430 format %{ "STX $src,$dst\t! ptr" %} | |
6431 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6432 #endif | |
6433 ins_encode( form3_mem_reg( dst, src ) ); | |
6434 ins_pipe(istore_mem_spORreg); | |
6435 %} | |
6436 | |
6437 instruct storeP0(memory dst, immP0 src) %{ | |
6438 match(Set dst (StoreP dst src)); | |
6439 ins_cost(MEMORY_REF_COST); | |
6440 size(4); | |
6441 | |
6442 #ifndef _LP64 | |
6443 format %{ "STW $src,$dst\t! ptr" %} | |
6444 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6445 #else | |
6446 format %{ "STX $src,$dst\t! ptr" %} | |
6447 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6448 #endif | |
6449 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
6450 ins_pipe(istore_mem_zero); | |
6451 %} | |
6452 | |
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6453 // Store Compressed Pointer |
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6454 instruct storeN(memory dst, iRegN src) %{ |
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6455 match(Set dst (StoreN dst src)); |
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6456 ins_cost(MEMORY_REF_COST); |
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6457 size(4); |
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6458 |
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6459 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6460 ins_encode %{ |
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6461 Register base = as_Register($dst$$base); |
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6462 Register index = as_Register($dst$$index); |
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6463 Register src = $src$$Register; |
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6464 if (index != G0) { |
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6465 __ stw(src, base, index); |
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6466 } else { |
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6467 __ stw(src, base, $dst$$disp); |
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6468 } |
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6469 %} |
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6470 ins_pipe(istore_mem_spORreg); |
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6471 %} |
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6472 |
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6473 instruct storeN0(memory dst, immN0 src) %{ |
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6474 match(Set dst (StoreN dst src)); |
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6475 ins_cost(MEMORY_REF_COST); |
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6476 size(4); |
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6477 |
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6478 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6479 ins_encode %{ |
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6480 Register base = as_Register($dst$$base); |
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6481 Register index = as_Register($dst$$index); |
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6482 if (index != G0) { |
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6483 __ stw(0, base, index); |
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6484 } else { |
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6485 __ stw(0, base, $dst$$disp); |
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6486 } |
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6487 %} |
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6488 ins_pipe(istore_mem_zero); |
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6489 %} |
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6490 |
0 | 6491 // Store Double |
6492 instruct storeD( memory mem, regD src) %{ | |
6493 match(Set mem (StoreD mem src)); | |
6494 ins_cost(MEMORY_REF_COST); | |
6495 | |
6496 size(4); | |
6497 format %{ "STDF $src,$mem" %} | |
6498 opcode(Assembler::stdf_op3); | |
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6499 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6500 ins_pipe(fstoreD_mem_reg); |
6501 %} | |
6502 | |
6503 instruct storeD0( memory mem, immD0 src) %{ | |
6504 match(Set mem (StoreD mem src)); | |
6505 ins_cost(MEMORY_REF_COST); | |
6506 | |
6507 size(4); | |
6508 format %{ "STX $src,$mem" %} | |
6509 opcode(Assembler::stx_op3); | |
415
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6510 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6511 ins_pipe(fstoreD_mem_zero); |
6512 %} | |
6513 | |
6514 // Store Float | |
6515 instruct storeF( memory mem, regF src) %{ | |
6516 match(Set mem (StoreF mem src)); | |
6517 ins_cost(MEMORY_REF_COST); | |
6518 | |
6519 size(4); | |
6520 format %{ "STF $src,$mem" %} | |
6521 opcode(Assembler::stf_op3); | |
415
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6522 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6523 ins_pipe(fstoreF_mem_reg); |
6524 %} | |
6525 | |
6526 instruct storeF0( memory mem, immF0 src) %{ | |
6527 match(Set mem (StoreF mem src)); | |
6528 ins_cost(MEMORY_REF_COST); | |
6529 | |
6530 size(4); | |
6531 format %{ "STW $src,$mem\t! storeF0" %} | |
6532 opcode(Assembler::stw_op3); | |
415
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6533 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6534 ins_pipe(fstoreF_mem_zero); |
6535 %} | |
6536 | |
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6537 // Convert oop pointer into compressed form |
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6538 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
221
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6539 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
113
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6540 match(Set dst (EncodeP src)); |
124
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6541 format %{ "encode_heap_oop $src, $dst" %} |
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6542 ins_encode %{ |
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6543 __ encode_heap_oop($src$$Register, $dst$$Register); |
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6544 %} |
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6545 ins_pipe(ialu_reg); |
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6546 %} |
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6547 |
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6548 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
221
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6549 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
124
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|
6550 match(Set dst (EncodeP src)); |
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6551 format %{ "encode_heap_oop_not_null $src, $dst" %} |
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6552 ins_encode %{ |
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6553 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
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6554 %} |
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|
6555 ins_pipe(ialu_reg); |
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|
6556 %} |
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|
6557 |
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6558 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
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6559 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
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6560 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
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6561 match(Set dst (DecodeN src)); |
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6562 format %{ "decode_heap_oop $src, $dst" %} |
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6563 ins_encode %{ |
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6564 __ decode_heap_oop($src$$Register, $dst$$Register); |
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|
6565 %} |
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6566 ins_pipe(ialu_reg); |
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|
6567 %} |
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|
6568 |
124
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|
6569 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
182
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6570 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
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6571 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
124
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|
6572 match(Set dst (DecodeN src)); |
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|
6573 format %{ "decode_heap_oop_not_null $src, $dst" %} |
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|
6574 ins_encode %{ |
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|
6575 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
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|
6576 %} |
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changeset
|
6577 ins_pipe(ialu_reg); |
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113
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|
6578 %} |
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113
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|
6579 |
113
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6580 |
0 | 6581 //----------MemBar Instructions----------------------------------------------- |
6582 // Memory barrier flavors | |
6583 | |
6584 instruct membar_acquire() %{ | |
6585 match(MemBarAcquire); | |
6586 ins_cost(4*MEMORY_REF_COST); | |
6587 | |
6588 size(0); | |
6589 format %{ "MEMBAR-acquire" %} | |
6590 ins_encode( enc_membar_acquire ); | |
6591 ins_pipe(long_memory_op); | |
6592 %} | |
6593 | |
6594 instruct membar_acquire_lock() %{ | |
3849
f1c12354c3f7
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roland
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|
6595 match(MemBarAcquireLock); |
0 | 6596 ins_cost(0); |
6597 | |
6598 size(0); | |
6599 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
6600 ins_encode( ); | |
6601 ins_pipe(empty); | |
6602 %} | |
6603 | |
6604 instruct membar_release() %{ | |
6605 match(MemBarRelease); | |
6606 ins_cost(4*MEMORY_REF_COST); | |
6607 | |
6608 size(0); | |
6609 format %{ "MEMBAR-release" %} | |
6610 ins_encode( enc_membar_release ); | |
6611 ins_pipe(long_memory_op); | |
6612 %} | |
6613 | |
6614 instruct membar_release_lock() %{ | |
3849
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|
6615 match(MemBarReleaseLock); |
0 | 6616 ins_cost(0); |
6617 | |
6618 size(0); | |
6619 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
6620 ins_encode( ); | |
6621 ins_pipe(empty); | |
6622 %} | |
6623 | |
6624 instruct membar_volatile() %{ | |
6625 match(MemBarVolatile); | |
6626 ins_cost(4*MEMORY_REF_COST); | |
6627 | |
6628 size(4); | |
6629 format %{ "MEMBAR-volatile" %} | |
6630 ins_encode( enc_membar_volatile ); | |
6631 ins_pipe(long_memory_op); | |
6632 %} | |
6633 | |
6634 instruct unnecessary_membar_volatile() %{ | |
6635 match(MemBarVolatile); | |
6636 predicate(Matcher::post_store_load_barrier(n)); | |
6637 ins_cost(0); | |
6638 | |
6639 size(0); | |
6640 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
6641 ins_encode( ); | |
6642 ins_pipe(empty); | |
6643 %} | |
6644 | |
4763
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4121
diff
changeset
|
6645 instruct membar_storestore() %{ |
1dc233a8c7fe
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roland
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4121
diff
changeset
|
6646 match(MemBarStoreStore); |
1dc233a8c7fe
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4121
diff
changeset
|
6647 ins_cost(0); |
1dc233a8c7fe
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4121
diff
changeset
|
6648 |
1dc233a8c7fe
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roland
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4121
diff
changeset
|
6649 size(0); |
1dc233a8c7fe
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4121
diff
changeset
|
6650 format %{ "!MEMBAR-storestore (empty encoding)" %} |
1dc233a8c7fe
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4121
diff
changeset
|
6651 ins_encode( ); |
1dc233a8c7fe
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diff
changeset
|
6652 ins_pipe(empty); |
1dc233a8c7fe
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4121
diff
changeset
|
6653 %} |
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diff
changeset
|
6654 |
0 | 6655 //----------Register Move Instructions----------------------------------------- |
6656 instruct roundDouble_nop(regD dst) %{ | |
6657 match(Set dst (RoundDouble dst)); | |
6658 ins_cost(0); | |
6659 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6660 ins_encode( ); | |
6661 ins_pipe(empty); | |
6662 %} | |
6663 | |
6664 | |
6665 instruct roundFloat_nop(regF dst) %{ | |
6666 match(Set dst (RoundFloat dst)); | |
6667 ins_cost(0); | |
6668 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6669 ins_encode( ); | |
6670 ins_pipe(empty); | |
6671 %} | |
6672 | |
6673 | |
6674 // Cast Index to Pointer for unsafe natives | |
6675 instruct castX2P(iRegX src, iRegP dst) %{ | |
6676 match(Set dst (CastX2P src)); | |
6677 | |
6678 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
6679 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6680 ins_pipe(ialu_reg); | |
6681 %} | |
6682 | |
6683 // Cast Pointer to Index for unsafe natives | |
6684 instruct castP2X(iRegP src, iRegX dst) %{ | |
6685 match(Set dst (CastP2X src)); | |
6686 | |
6687 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
6688 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6689 ins_pipe(ialu_reg); | |
6690 %} | |
6691 | |
6692 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
6693 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6694 match(Set stkSlot src); // chain rule | |
6695 ins_cost(MEMORY_REF_COST); | |
6696 format %{ "STDF $src,$stkSlot\t!stk" %} | |
6697 opcode(Assembler::stdf_op3); | |
415
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|
6698 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6699 ins_pipe(fstoreD_stk_reg); |
6700 %} | |
6701 | |
6702 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
6703 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6704 match(Set dst stkSlot); // chain rule | |
6705 ins_cost(MEMORY_REF_COST); | |
6706 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
6707 opcode(Assembler::lddf_op3); | |
415
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|
6708 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
0 | 6709 ins_pipe(floadD_stk); |
6710 %} | |
6711 | |
6712 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
6713 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6714 match(Set stkSlot src); // chain rule | |
6715 ins_cost(MEMORY_REF_COST); | |
6716 format %{ "STF $src,$stkSlot\t!stk" %} | |
6717 opcode(Assembler::stf_op3); | |
415
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6718 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6719 ins_pipe(fstoreF_stk_reg); |
6720 %} | |
6721 | |
6722 //----------Conditional Move--------------------------------------------------- | |
6723 // Conditional move | |
6724 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
6725 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6726 ins_cost(150); | |
6727 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6728 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6729 ins_pipe(ialu_reg); | |
6730 %} | |
6731 | |
6732 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
6733 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6734 ins_cost(140); | |
6735 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6736 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6737 ins_pipe(ialu_imm); | |
6738 %} | |
6739 | |
6740 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
6741 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6742 ins_cost(150); | |
6743 size(4); | |
6744 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6745 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6746 ins_pipe(ialu_reg); | |
6747 %} | |
6748 | |
6749 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
6750 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6751 ins_cost(140); | |
6752 size(4); | |
6753 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6754 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6755 ins_pipe(ialu_imm); | |
6756 %} | |
6757 | |
1160
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1137
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|
6758 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
0 | 6759 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6760 ins_cost(150); | |
6761 size(4); | |
6762 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6763 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6764 ins_pipe(ialu_reg); | |
6765 %} | |
6766 | |
1160
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1137
diff
changeset
|
6767 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
0 | 6768 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6769 ins_cost(140); | |
6770 size(4); | |
6771 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6772 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6773 ins_pipe(ialu_imm); | |
6774 %} | |
6775 | |
6776 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
6777 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6778 ins_cost(150); | |
6779 size(4); | |
6780 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6781 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6782 ins_pipe(ialu_reg); | |
6783 %} | |
6784 | |
6785 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
6786 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6787 ins_cost(140); | |
6788 size(4); | |
6789 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6790 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
6791 ins_pipe(ialu_imm); | |
6792 %} | |
6793 | |
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|
6794 // Conditional move for RegN. Only cmov(reg,reg). |
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|
6795 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
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|
6796 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
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|
6797 ins_cost(150); |
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|
6798 format %{ "MOV$cmp $pcc,$src,$dst" %} |
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|
6799 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
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|
6800 ins_pipe(ialu_reg); |
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|
6801 %} |
c436414a719e
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diff
changeset
|
6802 |
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diff
changeset
|
6803 // This instruction also works with CmpN so we don't need cmovNN_reg. |
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diff
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|
6804 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
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|
6805 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
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|
6806 ins_cost(150); |
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|
6807 size(4); |
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|
6808 format %{ "MOV$cmp $icc,$src,$dst" %} |
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|
6809 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
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|
6810 ins_pipe(ialu_reg); |
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|
6811 %} |
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diff
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|
6812 |
1160
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|
6813 // This instruction also works with CmpN so we don't need cmovNN_reg. |
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diff
changeset
|
6814 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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diff
changeset
|
6815 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6816 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6817 size(4); |
f24201449cac
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diff
changeset
|
6818 format %{ "MOV$cmp $icc,$src,$dst" %} |
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diff
changeset
|
6819 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6820 ins_pipe(ialu_reg); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
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diff
changeset
|
6821 %} |
f24201449cac
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diff
changeset
|
6822 |
164
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diff
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|
6823 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
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|
6824 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
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|
6825 ins_cost(150); |
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diff
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|
6826 size(4); |
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diff
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|
6827 format %{ "MOV$cmp $fcc,$src,$dst" %} |
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|
6828 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
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|
6829 ins_pipe(ialu_reg); |
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|
6830 %} |
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|
6831 |
0 | 6832 // Conditional move |
6833 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
6834 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6835 ins_cost(150); | |
6836 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6837 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6838 ins_pipe(ialu_reg); | |
6839 %} | |
6840 | |
6841 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
6842 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6843 ins_cost(140); | |
6844 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6845 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6846 ins_pipe(ialu_imm); | |
6847 %} | |
6848 | |
164
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6849 // This instruction also works with CmpN so we don't need cmovPN_reg. |
0 | 6850 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
6851 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
6852 ins_cost(150); | |
6853 | |
6854 size(4); | |
6855 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
6856 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6857 ins_pipe(ialu_reg); | |
6858 %} | |
6859 | |
1160
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changeset
|
6860 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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|
6861 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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|
6862 ins_cost(150); |
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diff
changeset
|
6863 |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6864 size(4); |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6865 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
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|
6866 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
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changeset
|
6867 ins_pipe(ialu_reg); |
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changeset
|
6868 %} |
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|
6869 |
0 | 6870 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ |
6871 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
6872 ins_cost(140); | |
6873 | |
6874 size(4); | |
6875 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
6876 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6877 ins_pipe(ialu_imm); | |
6878 %} | |
6879 | |
1160
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changeset
|
6880 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ |
f24201449cac
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|
6881 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6882 ins_cost(140); |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6883 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6884 size(4); |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6885 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
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changeset
|
6886 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
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changeset
|
6887 ins_pipe(ialu_imm); |
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changeset
|
6888 %} |
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|
6889 |
0 | 6890 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ |
6891 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
6892 ins_cost(150); | |
6893 size(4); | |
6894 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6895 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6896 ins_pipe(ialu_imm); | |
6897 %} | |
6898 | |
6899 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
6900 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
6901 ins_cost(140); | |
6902 size(4); | |
6903 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6904 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
6905 ins_pipe(ialu_imm); | |
6906 %} | |
6907 | |
6908 // Conditional move | |
6909 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
6910 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
6911 ins_cost(150); | |
6912 opcode(0x101); | |
6913 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
6914 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6915 ins_pipe(int_conditional_float_move); | |
6916 %} | |
6917 | |
6918 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
6919 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
6920 ins_cost(150); | |
6921 | |
6922 size(4); | |
6923 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
6924 opcode(0x101); | |
6925 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
6926 ins_pipe(int_conditional_float_move); | |
6927 %} | |
6928 | |
1160
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6929 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6930 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
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changeset
|
6931 ins_cost(150); |
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changeset
|
6932 |
f24201449cac
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changeset
|
6933 size(4); |
f24201449cac
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changeset
|
6934 format %{ "FMOVS$cmp $icc,$src,$dst" %} |
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changeset
|
6935 opcode(0x101); |
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|
6936 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
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changeset
|
6937 ins_pipe(int_conditional_float_move); |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6938 %} |
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changeset
|
6939 |
0 | 6940 // Conditional move, |
6941 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
6942 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
6943 ins_cost(150); | |
6944 size(4); | |
6945 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
6946 opcode(0x1); | |
6947 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
6948 ins_pipe(int_conditional_double_move); | |
6949 %} | |
6950 | |
6951 // Conditional move | |
6952 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
6953 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
6954 ins_cost(150); | |
6955 size(4); | |
6956 opcode(0x102); | |
6957 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
6958 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6959 ins_pipe(int_conditional_double_move); | |
6960 %} | |
6961 | |
6962 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
6963 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
6964 ins_cost(150); | |
6965 | |
6966 size(4); | |
6967 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
6968 opcode(0x102); | |
6969 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
6970 ins_pipe(int_conditional_double_move); | |
6971 %} | |
6972 | |
1160
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changeset
|
6973 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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|
6974 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6975 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6976 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6977 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6978 format %{ "FMOVD$cmp $icc,$src,$dst" %} |
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changeset
|
6979 opcode(0x102); |
f24201449cac
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changeset
|
6980 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
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changeset
|
6981 ins_pipe(int_conditional_double_move); |
f24201449cac
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changeset
|
6982 %} |
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changeset
|
6983 |
0 | 6984 // Conditional move, |
6985 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
6986 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
6987 ins_cost(150); | |
6988 size(4); | |
6989 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
6990 opcode(0x2); | |
6991 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
6992 ins_pipe(int_conditional_double_move); | |
6993 %} | |
6994 | |
6995 // Conditional move | |
6996 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
6997 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
6998 ins_cost(150); | |
6999 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
7000 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
7001 ins_pipe(ialu_reg); | |
7002 %} | |
7003 | |
7004 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
7005 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
7006 ins_cost(140); | |
7007 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
7008 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
7009 ins_pipe(ialu_imm); | |
7010 %} | |
7011 | |
7012 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
7013 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
7014 ins_cost(150); | |
7015 | |
7016 size(4); | |
7017 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
7018 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
7019 ins_pipe(ialu_reg); | |
7020 %} | |
7021 | |
7022 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
7023 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
7024 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
7025 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
7026 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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changeset
|
7027 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
7028 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
7029 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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changeset
|
7030 ins_pipe(ialu_reg); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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changeset
|
7031 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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changeset
|
7032 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
7033 |
0 | 7034 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ |
7035 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
7036 ins_cost(150); | |
7037 | |
7038 size(4); | |
7039 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
7040 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
7041 ins_pipe(ialu_reg); | |
7042 %} | |
7043 | |
7044 | |
7045 | |
7046 //----------OS and Locking Instructions---------------------------------------- | |
7047 | |
7048 // This name is KNOWN by the ADLC and cannot be changed. | |
7049 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
7050 // for this guy. | |
7051 instruct tlsLoadP(g2RegP dst) %{ | |
7052 match(Set dst (ThreadLocal)); | |
7053 | |
7054 size(0); | |
7055 ins_cost(0); | |
7056 format %{ "# TLS is in G2" %} | |
7057 ins_encode( /*empty encoding*/ ); | |
7058 ins_pipe(ialu_none); | |
7059 %} | |
7060 | |
7061 instruct checkCastPP( iRegP dst ) %{ | |
7062 match(Set dst (CheckCastPP dst)); | |
7063 | |
7064 size(0); | |
7065 format %{ "# checkcastPP of $dst" %} | |
7066 ins_encode( /*empty encoding*/ ); | |
7067 ins_pipe(empty); | |
7068 %} | |
7069 | |
7070 | |
7071 instruct castPP( iRegP dst ) %{ | |
7072 match(Set dst (CastPP dst)); | |
7073 format %{ "# castPP of $dst" %} | |
7074 ins_encode( /*empty encoding*/ ); | |
7075 ins_pipe(empty); | |
7076 %} | |
7077 | |
7078 instruct castII( iRegI dst ) %{ | |
7079 match(Set dst (CastII dst)); | |
7080 format %{ "# castII of $dst" %} | |
7081 ins_encode( /*empty encoding*/ ); | |
7082 ins_cost(0); | |
7083 ins_pipe(empty); | |
7084 %} | |
7085 | |
7086 //----------Arithmetic Instructions-------------------------------------------- | |
7087 // Addition Instructions | |
7088 // Register Addition | |
7089 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7090 match(Set dst (AddI src1 src2)); | |
7091 | |
7092 size(4); | |
7093 format %{ "ADD $src1,$src2,$dst" %} | |
7094 ins_encode %{ | |
7095 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
7096 %} | |
7097 ins_pipe(ialu_reg_reg); | |
7098 %} | |
7099 | |
7100 // Immediate Addition | |
7101 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7102 match(Set dst (AddI src1 src2)); | |
7103 | |
7104 size(4); | |
7105 format %{ "ADD $src1,$src2,$dst" %} | |
7106 opcode(Assembler::add_op3, Assembler::arith_op); | |
7107 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7108 ins_pipe(ialu_reg_imm); | |
7109 %} | |
7110 | |
7111 // Pointer Register Addition | |
7112 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
7113 match(Set dst (AddP src1 src2)); | |
7114 | |
7115 size(4); | |
7116 format %{ "ADD $src1,$src2,$dst" %} | |
7117 opcode(Assembler::add_op3, Assembler::arith_op); | |
7118 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7119 ins_pipe(ialu_reg_reg); | |
7120 %} | |
7121 | |
7122 // Pointer Immediate Addition | |
7123 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
7124 match(Set dst (AddP src1 src2)); | |
7125 | |
7126 size(4); | |
7127 format %{ "ADD $src1,$src2,$dst" %} | |
7128 opcode(Assembler::add_op3, Assembler::arith_op); | |
7129 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7130 ins_pipe(ialu_reg_imm); | |
7131 %} | |
7132 | |
7133 // Long Addition | |
7134 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7135 match(Set dst (AddL src1 src2)); | |
7136 | |
7137 size(4); | |
7138 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
7139 opcode(Assembler::add_op3, Assembler::arith_op); | |
7140 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7141 ins_pipe(ialu_reg_reg); | |
7142 %} | |
7143 | |
7144 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7145 match(Set dst (AddL src1 con)); | |
7146 | |
7147 size(4); | |
7148 format %{ "ADD $src1,$con,$dst" %} | |
7149 opcode(Assembler::add_op3, Assembler::arith_op); | |
7150 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7151 ins_pipe(ialu_reg_imm); | |
7152 %} | |
7153 | |
7154 //----------Conditional_store-------------------------------------------------- | |
7155 // Conditional-store of the updated heap-top. | |
7156 // Used during allocation of the shared heap. | |
7157 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
7158 | |
7159 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
7160 instruct loadPLocked(iRegP dst, memory mem) %{ | |
7161 match(Set dst (LoadPLocked mem)); | |
7162 ins_cost(MEMORY_REF_COST); | |
7163 | |
7164 #ifndef _LP64 | |
7165 size(4); | |
7166 format %{ "LDUW $mem,$dst\t! ptr" %} | |
7167 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
7168 #else | |
7169 format %{ "LDX $mem,$dst\t! ptr" %} | |
7170 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
7171 #endif | |
7172 ins_encode( form3_mem_reg( mem, dst ) ); | |
7173 ins_pipe(iload_mem); | |
7174 %} | |
7175 | |
7176 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
7177 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
7178 effect( KILL newval ); | |
7179 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
7180 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
7181 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
7182 ins_pipe( long_memory_op ); | |
7183 %} | |
7184 | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7185 // Conditional-store of an int value. |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7186 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7187 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7188 effect( KILL newval ); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7189 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7190 "CMP $oldval,$newval\t\t! See if we made progress" %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7191 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 7192 ins_pipe( long_memory_op ); |
7193 %} | |
7194 | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7195 // Conditional-store of a long value. |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7196 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
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diff
changeset
|
7197 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7198 effect( KILL newval ); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7199 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
a1980da045cc
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parents:
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diff
changeset
|
7200 "CMP $oldval,$newval\t\t! See if we made progress" %} |
a1980da045cc
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415
diff
changeset
|
7201 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 7202 ins_pipe( long_memory_op ); |
7203 %} | |
7204 | |
7205 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
7206 | |
7207 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
6795
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7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7208 predicate(VM_Version::supports_cx8()); |
0 | 7209 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
7210 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7211 format %{ | |
7212 "MOV $newval,O7\n\t" | |
7213 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7214 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7215 "MOV 1,$res\n\t" | |
7216 "MOVne xcc,R_G0,$res" | |
7217 %} | |
7218 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
7219 enc_lflags_ne_to_boolean(res) ); | |
7220 ins_pipe( long_memory_op ); | |
7221 %} | |
7222 | |
7223 | |
7224 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
7225 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
7226 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7227 format %{ | |
7228 "MOV $newval,O7\n\t" | |
7229 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7230 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7231 "MOV 1,$res\n\t" | |
7232 "MOVne icc,R_G0,$res" | |
7233 %} | |
7234 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
7235 enc_iflags_ne_to_boolean(res) ); | |
7236 ins_pipe( long_memory_op ); | |
7237 %} | |
7238 | |
7239 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
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diff
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|
7240 #ifdef _LP64 |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7241 predicate(VM_Version::supports_cx8()); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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diff
changeset
|
7242 #endif |
0 | 7243 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
7244 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7245 format %{ | |
7246 "MOV $newval,O7\n\t" | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
81
diff
changeset
|
7247 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
0 | 7248 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
7249 "MOV 1,$res\n\t" | |
7250 "MOVne xcc,R_G0,$res" | |
7251 %} | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
81
diff
changeset
|
7252 #ifdef _LP64 |
0 | 7253 ins_encode( enc_casx(mem_ptr, oldval, newval), |
7254 enc_lflags_ne_to_boolean(res) ); | |
7255 #else | |
113
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81
diff
changeset
|
7256 ins_encode( enc_casi(mem_ptr, oldval, newval), |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7257 enc_iflags_ne_to_boolean(res) ); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
81
diff
changeset
|
7258 #endif |
ba764ed4b6f2
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parents:
81
diff
changeset
|
7259 ins_pipe( long_memory_op ); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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81
diff
changeset
|
7260 %} |
ba764ed4b6f2
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81
diff
changeset
|
7261 |
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7262 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
113
ba764ed4b6f2
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parents:
81
diff
changeset
|
7263 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7264 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
0 | 7265 format %{ |
7266 "MOV $newval,O7\n\t" | |
7267 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7268 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7269 "MOV 1,$res\n\t" | |
7270 "MOVne icc,R_G0,$res" | |
7271 %} | |
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7272 ins_encode( enc_casi(mem_ptr, oldval, newval), |
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7273 enc_iflags_ne_to_boolean(res) ); |
0 | 7274 ins_pipe( long_memory_op ); |
7275 %} | |
7276 | |
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7277 instruct xchgI( memory mem, iRegI newval) %{ |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7278 match(Set newval (GetAndSetI mem newval)); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7279 format %{ "SWAP [$mem],$newval" %} |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7280 size(4); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7281 ins_encode %{ |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7282 __ swap($mem$$Address, $newval$$Register); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7283 %} |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7284 ins_pipe( long_memory_op ); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7285 %} |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7286 |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7287 #ifndef _LP64 |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7288 instruct xchgP( memory mem, iRegP newval) %{ |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7289 match(Set newval (GetAndSetP mem newval)); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7290 format %{ "SWAP [$mem],$newval" %} |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7291 size(4); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7292 ins_encode %{ |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7293 __ swap($mem$$Address, $newval$$Register); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7294 %} |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7295 ins_pipe( long_memory_op ); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7296 %} |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7297 #endif |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7298 |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7299 instruct xchgN( memory mem, iRegN newval) %{ |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7300 match(Set newval (GetAndSetN mem newval)); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7301 format %{ "SWAP [$mem],$newval" %} |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7302 size(4); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7303 ins_encode %{ |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7304 __ swap($mem$$Address, $newval$$Register); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7305 %} |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7306 ins_pipe( long_memory_op ); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7307 %} |
7eca5de9e0b6
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parents:
6725
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changeset
|
7308 |
0 | 7309 //--------------------- |
7310 // Subtraction Instructions | |
7311 // Register Subtraction | |
7312 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7313 match(Set dst (SubI src1 src2)); | |
7314 | |
7315 size(4); | |
7316 format %{ "SUB $src1,$src2,$dst" %} | |
7317 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7318 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7319 ins_pipe(ialu_reg_reg); | |
7320 %} | |
7321 | |
7322 // Immediate Subtraction | |
7323 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7324 match(Set dst (SubI src1 src2)); | |
7325 | |
7326 size(4); | |
7327 format %{ "SUB $src1,$src2,$dst" %} | |
7328 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7329 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7330 ins_pipe(ialu_reg_imm); | |
7331 %} | |
7332 | |
7333 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
7334 match(Set dst (SubI zero src2)); | |
7335 | |
7336 size(4); | |
7337 format %{ "NEG $src2,$dst" %} | |
7338 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7339 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
7340 ins_pipe(ialu_zero_reg); | |
7341 %} | |
7342 | |
7343 // Long subtraction | |
7344 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7345 match(Set dst (SubL src1 src2)); | |
7346 | |
7347 size(4); | |
7348 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7349 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7350 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7351 ins_pipe(ialu_reg_reg); | |
7352 %} | |
7353 | |
7354 // Immediate Subtraction | |
7355 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7356 match(Set dst (SubL src1 con)); | |
7357 | |
7358 size(4); | |
7359 format %{ "SUB $src1,$con,$dst\t! long" %} | |
7360 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7361 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7362 ins_pipe(ialu_reg_imm); | |
7363 %} | |
7364 | |
7365 // Long negation | |
7366 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
7367 match(Set dst (SubL zero src2)); | |
7368 | |
7369 size(4); | |
7370 format %{ "NEG $src2,$dst\t! long" %} | |
7371 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7372 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
7373 ins_pipe(ialu_zero_reg); | |
7374 %} | |
7375 | |
7376 // Multiplication Instructions | |
7377 // Integer Multiplication | |
7378 // Register Multiplication | |
7379 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7380 match(Set dst (MulI src1 src2)); | |
7381 | |
7382 size(4); | |
7383 format %{ "MULX $src1,$src2,$dst" %} | |
7384 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7385 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7386 ins_pipe(imul_reg_reg); | |
7387 %} | |
7388 | |
7389 // Immediate Multiplication | |
7390 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7391 match(Set dst (MulI src1 src2)); | |
7392 | |
7393 size(4); | |
7394 format %{ "MULX $src1,$src2,$dst" %} | |
7395 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7396 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7397 ins_pipe(imul_reg_imm); | |
7398 %} | |
7399 | |
7400 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7401 match(Set dst (MulL src1 src2)); | |
7402 ins_cost(DEFAULT_COST * 5); | |
7403 size(4); | |
7404 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7405 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7406 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7407 ins_pipe(mulL_reg_reg); | |
7408 %} | |
7409 | |
7410 // Immediate Multiplication | |
7411 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7412 match(Set dst (MulL src1 src2)); | |
7413 ins_cost(DEFAULT_COST * 5); | |
7414 size(4); | |
7415 format %{ "MULX $src1,$src2,$dst" %} | |
7416 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7417 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7418 ins_pipe(mulL_reg_imm); | |
7419 %} | |
7420 | |
7421 // Integer Division | |
7422 // Register Division | |
7423 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
7424 match(Set dst (DivI src1 src2)); | |
7425 ins_cost((2+71)*DEFAULT_COST); | |
7426 | |
7427 format %{ "SRA $src2,0,$src2\n\t" | |
7428 "SRA $src1,0,$src1\n\t" | |
7429 "SDIVX $src1,$src2,$dst" %} | |
7430 ins_encode( idiv_reg( src1, src2, dst ) ); | |
7431 ins_pipe(sdiv_reg_reg); | |
7432 %} | |
7433 | |
7434 // Immediate Division | |
7435 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
7436 match(Set dst (DivI src1 src2)); | |
7437 ins_cost((2+71)*DEFAULT_COST); | |
7438 | |
7439 format %{ "SRA $src1,0,$src1\n\t" | |
7440 "SDIVX $src1,$src2,$dst" %} | |
7441 ins_encode( idiv_imm( src1, src2, dst ) ); | |
7442 ins_pipe(sdiv_reg_imm); | |
7443 %} | |
7444 | |
7445 //----------Div-By-10-Expansion------------------------------------------------ | |
7446 // Extract hi bits of a 32x32->64 bit multiply. | |
7447 // Expand rule only, not matched | |
7448 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
7449 effect( DEF dst, USE src1, USE src2 ); | |
7450 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
7451 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
7452 ins_encode( enc_mul_hi(dst,src1,src2)); | |
7453 ins_pipe(sdiv_reg_reg); | |
7454 %} | |
7455 | |
605 | 7456 // Magic constant, reciprocal of 10 |
0 | 7457 instruct loadConI_x66666667(iRegIsafe dst) %{ |
7458 effect( DEF dst ); | |
7459 | |
7460 size(8); | |
7461 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
7462 ins_encode( Set32(0x66666667, dst) ); | |
7463 ins_pipe(ialu_hi_lo_reg); | |
7464 %} | |
7465 | |
605 | 7466 // Register Shift Right Arithmetic Long by 32-63 |
0 | 7467 instruct sra_31( iRegI dst, iRegI src ) %{ |
7468 effect( DEF dst, USE src ); | |
7469 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
7470 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
7471 ins_pipe(ialu_reg_reg); | |
7472 %} | |
7473 | |
7474 // Arithmetic Shift Right by 8-bit immediate | |
7475 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
7476 effect( DEF dst, USE src ); | |
7477 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
7478 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7479 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
7480 ins_pipe(ialu_reg_imm); | |
7481 %} | |
7482 | |
7483 // Integer DIV with 10 | |
7484 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
7485 match(Set dst (DivI src div)); | |
7486 ins_cost((6+6)*DEFAULT_COST); | |
7487 expand %{ | |
7488 iRegIsafe tmp1; // Killed temps; | |
7489 iRegIsafe tmp2; // Killed temps; | |
7490 iRegI tmp3; // Killed temps; | |
7491 iRegI tmp4; // Killed temps; | |
7492 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
7493 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
7494 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
7495 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
7496 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
7497 %} | |
7498 %} | |
7499 | |
7500 // Register Long Division | |
7501 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7502 match(Set dst (DivL src1 src2)); | |
7503 ins_cost(DEFAULT_COST*71); | |
7504 size(4); | |
7505 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7506 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7507 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7508 ins_pipe(divL_reg_reg); | |
7509 %} | |
7510 | |
7511 // Register Long Division | |
7512 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7513 match(Set dst (DivL src1 src2)); | |
7514 ins_cost(DEFAULT_COST*71); | |
7515 size(4); | |
7516 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7517 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7518 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7519 ins_pipe(divL_reg_imm); | |
7520 %} | |
7521 | |
7522 // Integer Remainder | |
7523 // Register Remainder | |
7524 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
7525 match(Set dst (ModI src1 src2)); | |
7526 effect( KILL ccr, KILL temp); | |
7527 | |
7528 format %{ "SREM $src1,$src2,$dst" %} | |
7529 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
7530 ins_pipe(sdiv_reg_reg); | |
7531 %} | |
7532 | |
7533 // Immediate Remainder | |
7534 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
7535 match(Set dst (ModI src1 src2)); | |
7536 effect( KILL ccr, KILL temp); | |
7537 | |
7538 format %{ "SREM $src1,$src2,$dst" %} | |
7539 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
7540 ins_pipe(sdiv_reg_imm); | |
7541 %} | |
7542 | |
7543 // Register Long Remainder | |
7544 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7545 effect(DEF dst, USE src1, USE src2); | |
7546 size(4); | |
7547 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7548 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7549 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7550 ins_pipe(divL_reg_reg); | |
7551 %} | |
7552 | |
7553 // Register Long Division | |
7554 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7555 effect(DEF dst, USE src1, USE src2); | |
7556 size(4); | |
7557 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7558 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7559 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7560 ins_pipe(divL_reg_imm); | |
7561 %} | |
7562 | |
7563 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7564 effect(DEF dst, USE src1, USE src2); | |
7565 size(4); | |
7566 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7567 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7568 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7569 ins_pipe(mulL_reg_reg); | |
7570 %} | |
7571 | |
7572 // Immediate Multiplication | |
7573 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7574 effect(DEF dst, USE src1, USE src2); | |
7575 size(4); | |
7576 format %{ "MULX $src1,$src2,$dst" %} | |
7577 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7578 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7579 ins_pipe(mulL_reg_imm); | |
7580 %} | |
7581 | |
7582 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7583 effect(DEF dst, USE src1, USE src2); | |
7584 size(4); | |
7585 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7586 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7587 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7588 ins_pipe(ialu_reg_reg); | |
7589 %} | |
7590 | |
7591 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
7592 effect(DEF dst, USE src1, USE src2); | |
7593 size(4); | |
7594 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7595 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7596 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7597 ins_pipe(ialu_reg_reg); | |
7598 %} | |
7599 | |
7600 // Register Long Remainder | |
7601 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7602 match(Set dst (ModL src1 src2)); | |
7603 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7604 expand %{ | |
7605 iRegL tmp1; | |
7606 iRegL tmp2; | |
7607 divL_reg_reg_1(tmp1, src1, src2); | |
7608 mulL_reg_reg_1(tmp2, tmp1, src2); | |
7609 subL_reg_reg_1(dst, src1, tmp2); | |
7610 %} | |
7611 %} | |
7612 | |
7613 // Register Long Remainder | |
7614 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7615 match(Set dst (ModL src1 src2)); | |
7616 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7617 expand %{ | |
7618 iRegL tmp1; | |
7619 iRegL tmp2; | |
7620 divL_reg_imm13_1(tmp1, src1, src2); | |
7621 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
7622 subL_reg_reg_2 (dst, src1, tmp2); | |
7623 %} | |
7624 %} | |
7625 | |
7626 // Integer Shift Instructions | |
7627 // Register Shift Left | |
7628 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7629 match(Set dst (LShiftI src1 src2)); | |
7630 | |
7631 size(4); | |
7632 format %{ "SLL $src1,$src2,$dst" %} | |
7633 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7634 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7635 ins_pipe(ialu_reg_reg); | |
7636 %} | |
7637 | |
7638 // Register Shift Left Immediate | |
7639 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7640 match(Set dst (LShiftI src1 src2)); | |
7641 | |
7642 size(4); | |
7643 format %{ "SLL $src1,$src2,$dst" %} | |
7644 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7645 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7646 ins_pipe(ialu_reg_imm); | |
7647 %} | |
7648 | |
7649 // Register Shift Left | |
7650 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7651 match(Set dst (LShiftL src1 src2)); | |
7652 | |
7653 size(4); | |
7654 format %{ "SLLX $src1,$src2,$dst" %} | |
7655 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7656 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7657 ins_pipe(ialu_reg_reg); | |
7658 %} | |
7659 | |
7660 // Register Shift Left Immediate | |
7661 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7662 match(Set dst (LShiftL src1 src2)); | |
7663 | |
7664 size(4); | |
7665 format %{ "SLLX $src1,$src2,$dst" %} | |
7666 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7667 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7668 ins_pipe(ialu_reg_imm); | |
7669 %} | |
7670 | |
7671 // Register Arithmetic Shift Right | |
7672 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7673 match(Set dst (RShiftI src1 src2)); | |
7674 size(4); | |
7675 format %{ "SRA $src1,$src2,$dst" %} | |
7676 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7677 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7678 ins_pipe(ialu_reg_reg); | |
7679 %} | |
7680 | |
7681 // Register Arithmetic Shift Right Immediate | |
7682 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7683 match(Set dst (RShiftI src1 src2)); | |
7684 | |
7685 size(4); | |
7686 format %{ "SRA $src1,$src2,$dst" %} | |
7687 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7688 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7689 ins_pipe(ialu_reg_imm); | |
7690 %} | |
7691 | |
7692 // Register Shift Right Arithmatic Long | |
7693 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7694 match(Set dst (RShiftL src1 src2)); | |
7695 | |
7696 size(4); | |
7697 format %{ "SRAX $src1,$src2,$dst" %} | |
7698 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7699 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7700 ins_pipe(ialu_reg_reg); | |
7701 %} | |
7702 | |
7703 // Register Shift Left Immediate | |
7704 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7705 match(Set dst (RShiftL src1 src2)); | |
7706 | |
7707 size(4); | |
7708 format %{ "SRAX $src1,$src2,$dst" %} | |
7709 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7710 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7711 ins_pipe(ialu_reg_imm); | |
7712 %} | |
7713 | |
7714 // Register Shift Right | |
7715 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7716 match(Set dst (URShiftI src1 src2)); | |
7717 | |
7718 size(4); | |
7719 format %{ "SRL $src1,$src2,$dst" %} | |
7720 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7721 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7722 ins_pipe(ialu_reg_reg); | |
7723 %} | |
7724 | |
7725 // Register Shift Right Immediate | |
7726 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7727 match(Set dst (URShiftI src1 src2)); | |
7728 | |
7729 size(4); | |
7730 format %{ "SRL $src1,$src2,$dst" %} | |
7731 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7732 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7733 ins_pipe(ialu_reg_imm); | |
7734 %} | |
7735 | |
7736 // Register Shift Right | |
7737 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7738 match(Set dst (URShiftL src1 src2)); | |
7739 | |
7740 size(4); | |
7741 format %{ "SRLX $src1,$src2,$dst" %} | |
7742 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7743 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7744 ins_pipe(ialu_reg_reg); | |
7745 %} | |
7746 | |
7747 // Register Shift Right Immediate | |
7748 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7749 match(Set dst (URShiftL src1 src2)); | |
7750 | |
7751 size(4); | |
7752 format %{ "SRLX $src1,$src2,$dst" %} | |
7753 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7754 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7755 ins_pipe(ialu_reg_imm); | |
7756 %} | |
7757 | |
7758 // Register Shift Right Immediate with a CastP2X | |
7759 #ifdef _LP64 | |
7760 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
7761 match(Set dst (URShiftL (CastP2X src1) src2)); | |
7762 size(4); | |
7763 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
7764 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7765 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7766 ins_pipe(ialu_reg_imm); | |
7767 %} | |
7768 #else | |
7769 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
7770 match(Set dst (URShiftI (CastP2X src1) src2)); | |
7771 size(4); | |
7772 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
7773 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7774 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7775 ins_pipe(ialu_reg_imm); | |
7776 %} | |
7777 #endif | |
7778 | |
7779 | |
7780 //----------Floating Point Arithmetic Instructions----------------------------- | |
7781 | |
7782 // Add float single precision | |
7783 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7784 match(Set dst (AddF src1 src2)); | |
7785 | |
7786 size(4); | |
7787 format %{ "FADDS $src1,$src2,$dst" %} | |
7788 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
7789 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7790 ins_pipe(faddF_reg_reg); | |
7791 %} | |
7792 | |
7793 // Add float double precision | |
7794 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7795 match(Set dst (AddD src1 src2)); | |
7796 | |
7797 size(4); | |
7798 format %{ "FADDD $src1,$src2,$dst" %} | |
7799 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
7800 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7801 ins_pipe(faddD_reg_reg); | |
7802 %} | |
7803 | |
7804 // Sub float single precision | |
7805 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7806 match(Set dst (SubF src1 src2)); | |
7807 | |
7808 size(4); | |
7809 format %{ "FSUBS $src1,$src2,$dst" %} | |
7810 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
7811 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7812 ins_pipe(faddF_reg_reg); | |
7813 %} | |
7814 | |
7815 // Sub float double precision | |
7816 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7817 match(Set dst (SubD src1 src2)); | |
7818 | |
7819 size(4); | |
7820 format %{ "FSUBD $src1,$src2,$dst" %} | |
7821 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
7822 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7823 ins_pipe(faddD_reg_reg); | |
7824 %} | |
7825 | |
7826 // Mul float single precision | |
7827 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7828 match(Set dst (MulF src1 src2)); | |
7829 | |
7830 size(4); | |
7831 format %{ "FMULS $src1,$src2,$dst" %} | |
7832 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
7833 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7834 ins_pipe(fmulF_reg_reg); | |
7835 %} | |
7836 | |
7837 // Mul float double precision | |
7838 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7839 match(Set dst (MulD src1 src2)); | |
7840 | |
7841 size(4); | |
7842 format %{ "FMULD $src1,$src2,$dst" %} | |
7843 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
7844 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7845 ins_pipe(fmulD_reg_reg); | |
7846 %} | |
7847 | |
7848 // Div float single precision | |
7849 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7850 match(Set dst (DivF src1 src2)); | |
7851 | |
7852 size(4); | |
7853 format %{ "FDIVS $src1,$src2,$dst" %} | |
7854 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
7855 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7856 ins_pipe(fdivF_reg_reg); | |
7857 %} | |
7858 | |
7859 // Div float double precision | |
7860 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7861 match(Set dst (DivD src1 src2)); | |
7862 | |
7863 size(4); | |
7864 format %{ "FDIVD $src1,$src2,$dst" %} | |
7865 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
7866 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7867 ins_pipe(fdivD_reg_reg); | |
7868 %} | |
7869 | |
7870 // Absolute float double precision | |
7871 instruct absD_reg(regD dst, regD src) %{ | |
7872 match(Set dst (AbsD src)); | |
7873 | |
7874 format %{ "FABSd $src,$dst" %} | |
7875 ins_encode(fabsd(dst, src)); | |
7876 ins_pipe(faddD_reg); | |
7877 %} | |
7878 | |
7879 // Absolute float single precision | |
7880 instruct absF_reg(regF dst, regF src) %{ | |
7881 match(Set dst (AbsF src)); | |
7882 | |
7883 format %{ "FABSs $src,$dst" %} | |
7884 ins_encode(fabss(dst, src)); | |
7885 ins_pipe(faddF_reg); | |
7886 %} | |
7887 | |
7888 instruct negF_reg(regF dst, regF src) %{ | |
7889 match(Set dst (NegF src)); | |
7890 | |
7891 size(4); | |
7892 format %{ "FNEGs $src,$dst" %} | |
7893 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
7894 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
7895 ins_pipe(faddF_reg); | |
7896 %} | |
7897 | |
7898 instruct negD_reg(regD dst, regD src) %{ | |
7899 match(Set dst (NegD src)); | |
7900 | |
7901 format %{ "FNEGd $src,$dst" %} | |
7902 ins_encode(fnegd(dst, src)); | |
7903 ins_pipe(faddD_reg); | |
7904 %} | |
7905 | |
7906 // Sqrt float double precision | |
7907 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
7908 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
7909 | |
7910 size(4); | |
7911 format %{ "FSQRTS $src,$dst" %} | |
7912 ins_encode(fsqrts(dst, src)); | |
7913 ins_pipe(fdivF_reg_reg); | |
7914 %} | |
7915 | |
7916 // Sqrt float double precision | |
7917 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
7918 match(Set dst (SqrtD src)); | |
7919 | |
7920 size(4); | |
7921 format %{ "FSQRTD $src,$dst" %} | |
7922 ins_encode(fsqrtd(dst, src)); | |
7923 ins_pipe(fdivD_reg_reg); | |
7924 %} | |
7925 | |
7926 //----------Logical Instructions----------------------------------------------- | |
7927 // And Instructions | |
7928 // Register And | |
7929 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7930 match(Set dst (AndI src1 src2)); | |
7931 | |
7932 size(4); | |
7933 format %{ "AND $src1,$src2,$dst" %} | |
7934 opcode(Assembler::and_op3, Assembler::arith_op); | |
7935 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7936 ins_pipe(ialu_reg_reg); | |
7937 %} | |
7938 | |
7939 // Immediate And | |
7940 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7941 match(Set dst (AndI src1 src2)); | |
7942 | |
7943 size(4); | |
7944 format %{ "AND $src1,$src2,$dst" %} | |
7945 opcode(Assembler::and_op3, Assembler::arith_op); | |
7946 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7947 ins_pipe(ialu_reg_imm); | |
7948 %} | |
7949 | |
7950 // Register And Long | |
7951 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7952 match(Set dst (AndL src1 src2)); | |
7953 | |
7954 ins_cost(DEFAULT_COST); | |
7955 size(4); | |
7956 format %{ "AND $src1,$src2,$dst\t! long" %} | |
7957 opcode(Assembler::and_op3, Assembler::arith_op); | |
7958 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7959 ins_pipe(ialu_reg_reg); | |
7960 %} | |
7961 | |
7962 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7963 match(Set dst (AndL src1 con)); | |
7964 | |
7965 ins_cost(DEFAULT_COST); | |
7966 size(4); | |
7967 format %{ "AND $src1,$con,$dst\t! long" %} | |
7968 opcode(Assembler::and_op3, Assembler::arith_op); | |
7969 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7970 ins_pipe(ialu_reg_imm); | |
7971 %} | |
7972 | |
7973 // Or Instructions | |
7974 // Register Or | |
7975 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7976 match(Set dst (OrI src1 src2)); | |
7977 | |
7978 size(4); | |
7979 format %{ "OR $src1,$src2,$dst" %} | |
7980 opcode(Assembler::or_op3, Assembler::arith_op); | |
7981 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7982 ins_pipe(ialu_reg_reg); | |
7983 %} | |
7984 | |
7985 // Immediate Or | |
7986 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7987 match(Set dst (OrI src1 src2)); | |
7988 | |
7989 size(4); | |
7990 format %{ "OR $src1,$src2,$dst" %} | |
7991 opcode(Assembler::or_op3, Assembler::arith_op); | |
7992 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7993 ins_pipe(ialu_reg_imm); | |
7994 %} | |
7995 | |
7996 // Register Or Long | |
7997 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7998 match(Set dst (OrL src1 src2)); | |
7999 | |
8000 ins_cost(DEFAULT_COST); | |
8001 size(4); | |
8002 format %{ "OR $src1,$src2,$dst\t! long" %} | |
8003 opcode(Assembler::or_op3, Assembler::arith_op); | |
8004 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8005 ins_pipe(ialu_reg_reg); | |
8006 %} | |
8007 | |
8008 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
8009 match(Set dst (OrL src1 con)); | |
8010 ins_cost(DEFAULT_COST*2); | |
8011 | |
8012 ins_cost(DEFAULT_COST); | |
8013 size(4); | |
8014 format %{ "OR $src1,$con,$dst\t! long" %} | |
8015 opcode(Assembler::or_op3, Assembler::arith_op); | |
8016 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
8017 ins_pipe(ialu_reg_imm); | |
8018 %} | |
8019 | |
420
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|
8020 #ifndef _LP64 |
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|
8021 |
a1980da045cc
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|
8022 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
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|
8023 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
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|
8024 match(Set dst (OrI src1 (CastP2X src2))); |
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|
8025 |
a1980da045cc
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|
8026 size(4); |
a1980da045cc
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|
8027 format %{ "OR $src1,$src2,$dst" %} |
a1980da045cc
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|
8028 opcode(Assembler::or_op3, Assembler::arith_op); |
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|
8029 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
a1980da045cc
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|
8030 ins_pipe(ialu_reg_reg); |
a1980da045cc
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|
8031 %} |
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|
8032 |
a1980da045cc
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|
8033 #else |
a1980da045cc
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|
8034 |
a1980da045cc
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changeset
|
8035 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
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|
8036 match(Set dst (OrL src1 (CastP2X src2))); |
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|
8037 |
a1980da045cc
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|
8038 ins_cost(DEFAULT_COST); |
a1980da045cc
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diff
changeset
|
8039 size(4); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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changeset
|
8040 format %{ "OR $src1,$src2,$dst\t! long" %} |
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|
8041 opcode(Assembler::or_op3, Assembler::arith_op); |
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diff
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|
8042 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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|
8043 ins_pipe(ialu_reg_reg); |
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|
8044 %} |
a1980da045cc
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|
8045 |
a1980da045cc
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|
8046 #endif |
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|
8047 |
0 | 8048 // Xor Instructions |
8049 // Register Xor | |
8050 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
8051 match(Set dst (XorI src1 src2)); | |
8052 | |
8053 size(4); | |
8054 format %{ "XOR $src1,$src2,$dst" %} | |
8055 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8056 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8057 ins_pipe(ialu_reg_reg); | |
8058 %} | |
8059 | |
8060 // Immediate Xor | |
8061 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
8062 match(Set dst (XorI src1 src2)); | |
8063 | |
8064 size(4); | |
8065 format %{ "XOR $src1,$src2,$dst" %} | |
8066 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8067 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
8068 ins_pipe(ialu_reg_imm); | |
8069 %} | |
8070 | |
8071 // Register Xor Long | |
8072 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
8073 match(Set dst (XorL src1 src2)); | |
8074 | |
8075 ins_cost(DEFAULT_COST); | |
8076 size(4); | |
8077 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
8078 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8079 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8080 ins_pipe(ialu_reg_reg); | |
8081 %} | |
8082 | |
8083 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
8084 match(Set dst (XorL src1 con)); | |
8085 | |
8086 ins_cost(DEFAULT_COST); | |
8087 size(4); | |
8088 format %{ "XOR $src1,$con,$dst\t! long" %} | |
8089 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8090 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
8091 ins_pipe(ialu_reg_imm); | |
8092 %} | |
8093 | |
8094 //----------Convert to Boolean------------------------------------------------- | |
8095 // Nice hack for 32-bit tests but doesn't work for | |
8096 // 64-bit pointers. | |
8097 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
8098 match(Set dst (Conv2B src)); | |
8099 effect( KILL ccr ); | |
8100 ins_cost(DEFAULT_COST*2); | |
8101 format %{ "CMP R_G0,$src\n\t" | |
8102 "ADDX R_G0,0,$dst" %} | |
8103 ins_encode( enc_to_bool( src, dst ) ); | |
8104 ins_pipe(ialu_reg_ialu); | |
8105 %} | |
8106 | |
8107 #ifndef _LP64 | |
8108 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
8109 match(Set dst (Conv2B src)); | |
8110 effect( KILL ccr ); | |
8111 ins_cost(DEFAULT_COST*2); | |
8112 format %{ "CMP R_G0,$src\n\t" | |
8113 "ADDX R_G0,0,$dst" %} | |
8114 ins_encode( enc_to_bool( src, dst ) ); | |
8115 ins_pipe(ialu_reg_ialu); | |
8116 %} | |
8117 #else | |
8118 instruct convP2B( iRegI dst, iRegP src ) %{ | |
8119 match(Set dst (Conv2B src)); | |
8120 ins_cost(DEFAULT_COST*2); | |
8121 format %{ "MOV $src,$dst\n\t" | |
8122 "MOVRNZ $src,1,$dst" %} | |
8123 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
8124 ins_pipe(ialu_clr_and_mover); | |
8125 %} | |
8126 #endif | |
8127 | |
2254
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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diff
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|
8128 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ |
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7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
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|
8129 match(Set dst (CmpLTMask src zero)); |
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7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8130 effect(KILL ccr); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8131 size(4); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8132 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} |
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7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8133 ins_encode %{ |
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7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8134 __ sra($src$$Register, 31, $dst$$Register); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8135 %} |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8136 ins_pipe(ialu_reg_imm); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
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|
8137 %} |
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2121
diff
changeset
|
8138 |
0 | 8139 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ |
8140 match(Set dst (CmpLTMask p q)); | |
8141 effect( KILL ccr ); | |
8142 ins_cost(DEFAULT_COST*4); | |
8143 format %{ "CMP $p,$q\n\t" | |
8144 "MOV #0,$dst\n\t" | |
8145 "BLT,a .+8\n\t" | |
8146 "MOV #-1,$dst" %} | |
8147 ins_encode( enc_ltmask(p,q,dst) ); | |
8148 ins_pipe(ialu_reg_reg_ialu); | |
8149 %} | |
8150 | |
8151 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
8152 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
8153 effect(KILL ccr, TEMP tmp); | |
8154 ins_cost(DEFAULT_COST*3); | |
8155 | |
8156 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
8157 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
2254
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8158 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} |
0 | 8159 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); |
8160 ins_pipe( cadd_cmpltmask ); | |
8161 %} | |
8162 | |
3804 | 8163 |
8164 //----------------------------------------------------------------- | |
8165 // Direct raw moves between float and general registers using VIS3. | |
8166 | |
8167 // ins_pipe(faddF_reg); | |
8168 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ | |
8169 predicate(UseVIS >= 3); | |
8170 match(Set dst (MoveF2I src)); | |
8171 | |
8172 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} | |
8173 ins_encode %{ | |
8174 __ movstouw($src$$FloatRegister, $dst$$Register); | |
8175 %} | |
8176 ins_pipe(ialu_reg_reg); | |
8177 %} | |
8178 | |
8179 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ | |
8180 predicate(UseVIS >= 3); | |
8181 match(Set dst (MoveI2F src)); | |
8182 | |
8183 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} | |
8184 ins_encode %{ | |
8185 __ movwtos($src$$Register, $dst$$FloatRegister); | |
8186 %} | |
0 | 8187 ins_pipe(ialu_reg_reg); |
8188 %} | |
8189 | |
3804 | 8190 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ |
8191 predicate(UseVIS >= 3); | |
8192 match(Set dst (MoveD2L src)); | |
8193 | |
8194 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} | |
8195 ins_encode %{ | |
8196 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); | |
8197 %} | |
0 | 8198 ins_pipe(ialu_reg_reg); |
8199 %} | |
8200 | |
3804 | 8201 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ |
8202 predicate(UseVIS >= 3); | |
8203 match(Set dst (MoveL2D src)); | |
8204 | |
8205 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} | |
8206 ins_encode %{ | |
8207 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); | |
8208 %} | |
0 | 8209 ins_pipe(ialu_reg_reg); |
8210 %} | |
8211 | |
3804 | 8212 |
8213 // Raw moves between float and general registers using stack. | |
8214 | |
0 | 8215 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ |
8216 match(Set dst (MoveF2I src)); | |
8217 effect(DEF dst, USE src); | |
8218 ins_cost(MEMORY_REF_COST); | |
8219 | |
8220 size(4); | |
8221 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
8222 opcode(Assembler::lduw_op3); | |
415
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diff
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|
8223 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8224 ins_pipe(iload_mem); |
8225 %} | |
8226 | |
8227 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
8228 match(Set dst (MoveI2F src)); | |
8229 effect(DEF dst, USE src); | |
8230 ins_cost(MEMORY_REF_COST); | |
8231 | |
8232 size(4); | |
8233 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
8234 opcode(Assembler::ldf_op3); | |
415
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diff
changeset
|
8235 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8236 ins_pipe(floadF_stk); |
8237 %} | |
8238 | |
8239 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
8240 match(Set dst (MoveD2L src)); | |
8241 effect(DEF dst, USE src); | |
8242 ins_cost(MEMORY_REF_COST); | |
8243 | |
8244 size(4); | |
8245 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
8246 opcode(Assembler::ldx_op3); | |
415
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diff
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|
8247 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8248 ins_pipe(iload_mem); |
8249 %} | |
8250 | |
8251 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
8252 match(Set dst (MoveL2D src)); | |
8253 effect(DEF dst, USE src); | |
8254 ins_cost(MEMORY_REF_COST); | |
8255 | |
8256 size(4); | |
8257 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
8258 opcode(Assembler::lddf_op3); | |
415
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diff
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|
8259 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8260 ins_pipe(floadD_stk); |
8261 %} | |
8262 | |
8263 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
8264 match(Set dst (MoveF2I src)); | |
8265 effect(DEF dst, USE src); | |
8266 ins_cost(MEMORY_REF_COST); | |
8267 | |
8268 size(4); | |
3804 | 8269 format %{ "STF $src,$dst\t! MoveF2I" %} |
0 | 8270 opcode(Assembler::stf_op3); |
415
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diff
changeset
|
8271 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8272 ins_pipe(fstoreF_stk_reg); |
8273 %} | |
8274 | |
8275 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
8276 match(Set dst (MoveI2F src)); | |
8277 effect(DEF dst, USE src); | |
8278 ins_cost(MEMORY_REF_COST); | |
8279 | |
8280 size(4); | |
3804 | 8281 format %{ "STW $src,$dst\t! MoveI2F" %} |
0 | 8282 opcode(Assembler::stw_op3); |
415
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diff
changeset
|
8283 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8284 ins_pipe(istore_mem_reg); |
8285 %} | |
8286 | |
8287 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
8288 match(Set dst (MoveD2L src)); | |
8289 effect(DEF dst, USE src); | |
8290 ins_cost(MEMORY_REF_COST); | |
8291 | |
8292 size(4); | |
3804 | 8293 format %{ "STDF $src,$dst\t! MoveD2L" %} |
0 | 8294 opcode(Assembler::stdf_op3); |
415
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235
diff
changeset
|
8295 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8296 ins_pipe(fstoreD_stk_reg); |
8297 %} | |
8298 | |
8299 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
8300 match(Set dst (MoveL2D src)); | |
8301 effect(DEF dst, USE src); | |
8302 ins_cost(MEMORY_REF_COST); | |
8303 | |
8304 size(4); | |
3804 | 8305 format %{ "STX $src,$dst\t! MoveL2D" %} |
0 | 8306 opcode(Assembler::stx_op3); |
415
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235
diff
changeset
|
8307 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8308 ins_pipe(istore_mem_reg); |
8309 %} | |
8310 | |
8311 | |
3804 | 8312 //----------Arithmetic Conversion Instructions--------------------------------- |
8313 // The conversions operations are all Alpha sorted. Please keep it that way! | |
8314 | |
8315 instruct convD2F_reg(regF dst, regD src) %{ | |
8316 match(Set dst (ConvD2F src)); | |
8317 size(4); | |
8318 format %{ "FDTOS $src,$dst" %} | |
8319 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
8320 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
8321 ins_pipe(fcvtD2F); | |
8322 %} | |
8323 | |
8324 | |
8325 // Convert a double to an int in a float register. | |
8326 // If the double is a NAN, stuff a zero in instead. | |
8327 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
8328 effect(DEF dst, USE src, KILL fcc0); | |
8329 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
8330 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8331 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
8332 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
8333 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
8334 "skip:" %} | |
8335 ins_encode(form_d2i_helper(src,dst)); | |
8336 ins_pipe(fcvtD2I); | |
8337 %} | |
8338 | |
8339 instruct convD2I_stk(stackSlotI dst, regD src) %{ | |
8340 match(Set dst (ConvD2I src)); | |
8341 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8342 expand %{ | |
8343 regF tmp; | |
8344 convD2I_helper(tmp, src); | |
8345 regF_to_stkI(dst, tmp); | |
8346 %} | |
8347 %} | |
8348 | |
8349 instruct convD2I_reg(iRegI dst, regD src) %{ | |
8350 predicate(UseVIS >= 3); | |
8351 match(Set dst (ConvD2I src)); | |
8352 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
8353 expand %{ | |
8354 regF tmp; | |
8355 convD2I_helper(tmp, src); | |
8356 MoveF2I_reg_reg(dst, tmp); | |
8357 %} | |
8358 %} | |
8359 | |
8360 | |
8361 // Convert a double to a long in a double register. | |
8362 // If the double is a NAN, stuff a zero in instead. | |
8363 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
8364 effect(DEF dst, USE src, KILL fcc0); | |
8365 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
8366 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8367 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
8368 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
8369 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
8370 "skip:" %} | |
8371 ins_encode(form_d2l_helper(src,dst)); | |
8372 ins_pipe(fcvtD2L); | |
8373 %} | |
8374 | |
8375 instruct convD2L_stk(stackSlotL dst, regD src) %{ | |
8376 match(Set dst (ConvD2L src)); | |
8377 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8378 expand %{ | |
8379 regD tmp; | |
8380 convD2L_helper(tmp, src); | |
8381 regD_to_stkL(dst, tmp); | |
8382 %} | |
8383 %} | |
8384 | |
8385 instruct convD2L_reg(iRegL dst, regD src) %{ | |
8386 predicate(UseVIS >= 3); | |
8387 match(Set dst (ConvD2L src)); | |
8388 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
8389 expand %{ | |
8390 regD tmp; | |
8391 convD2L_helper(tmp, src); | |
8392 MoveD2L_reg_reg(dst, tmp); | |
8393 %} | |
8394 %} | |
8395 | |
8396 | |
8397 instruct convF2D_reg(regD dst, regF src) %{ | |
8398 match(Set dst (ConvF2D src)); | |
8399 format %{ "FSTOD $src,$dst" %} | |
8400 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
8401 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
8402 ins_pipe(fcvtF2D); | |
8403 %} | |
8404 | |
8405 | |
8406 // Convert a float to an int in a float register. | |
8407 // If the float is a NAN, stuff a zero in instead. | |
8408 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
8409 effect(DEF dst, USE src, KILL fcc0); | |
8410 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
8411 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8412 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
8413 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
8414 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
8415 "skip:" %} | |
8416 ins_encode(form_f2i_helper(src,dst)); | |
8417 ins_pipe(fcvtF2I); | |
8418 %} | |
8419 | |
8420 instruct convF2I_stk(stackSlotI dst, regF src) %{ | |
8421 match(Set dst (ConvF2I src)); | |
8422 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8423 expand %{ | |
8424 regF tmp; | |
8425 convF2I_helper(tmp, src); | |
8426 regF_to_stkI(dst, tmp); | |
8427 %} | |
8428 %} | |
8429 | |
8430 instruct convF2I_reg(iRegI dst, regF src) %{ | |
8431 predicate(UseVIS >= 3); | |
8432 match(Set dst (ConvF2I src)); | |
8433 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
8434 expand %{ | |
8435 regF tmp; | |
8436 convF2I_helper(tmp, src); | |
8437 MoveF2I_reg_reg(dst, tmp); | |
8438 %} | |
8439 %} | |
8440 | |
8441 | |
8442 // Convert a float to a long in a float register. | |
8443 // If the float is a NAN, stuff a zero in instead. | |
8444 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
8445 effect(DEF dst, USE src, KILL fcc0); | |
8446 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
8447 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8448 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
8449 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
8450 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
8451 "skip:" %} | |
8452 ins_encode(form_f2l_helper(src,dst)); | |
8453 ins_pipe(fcvtF2L); | |
8454 %} | |
8455 | |
8456 instruct convF2L_stk(stackSlotL dst, regF src) %{ | |
8457 match(Set dst (ConvF2L src)); | |
8458 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8459 expand %{ | |
8460 regD tmp; | |
8461 convF2L_helper(tmp, src); | |
8462 regD_to_stkL(dst, tmp); | |
8463 %} | |
8464 %} | |
8465 | |
8466 instruct convF2L_reg(iRegL dst, regF src) %{ | |
8467 predicate(UseVIS >= 3); | |
8468 match(Set dst (ConvF2L src)); | |
8469 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
8470 expand %{ | |
8471 regD tmp; | |
8472 convF2L_helper(tmp, src); | |
8473 MoveD2L_reg_reg(dst, tmp); | |
8474 %} | |
8475 %} | |
8476 | |
8477 | |
8478 instruct convI2D_helper(regD dst, regF tmp) %{ | |
8479 effect(USE tmp, DEF dst); | |
8480 format %{ "FITOD $tmp,$dst" %} | |
8481 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
8482 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
8483 ins_pipe(fcvtI2D); | |
8484 %} | |
8485 | |
8486 instruct convI2D_stk(stackSlotI src, regD dst) %{ | |
8487 match(Set dst (ConvI2D src)); | |
8488 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8489 expand %{ | |
8490 regF tmp; | |
8491 stkI_to_regF(tmp, src); | |
8492 convI2D_helper(dst, tmp); | |
8493 %} | |
8494 %} | |
8495 | |
8496 instruct convI2D_reg(regD_low dst, iRegI src) %{ | |
8497 predicate(UseVIS >= 3); | |
8498 match(Set dst (ConvI2D src)); | |
8499 expand %{ | |
8500 regF tmp; | |
8501 MoveI2F_reg_reg(tmp, src); | |
8502 convI2D_helper(dst, tmp); | |
8503 %} | |
8504 %} | |
8505 | |
8506 instruct convI2D_mem(regD_low dst, memory mem) %{ | |
8507 match(Set dst (ConvI2D (LoadI mem))); | |
8508 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8509 size(8); | |
8510 format %{ "LDF $mem,$dst\n\t" | |
8511 "FITOD $dst,$dst" %} | |
8512 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
8513 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
8514 ins_pipe(floadF_mem); | |
8515 %} | |
8516 | |
8517 | |
8518 instruct convI2F_helper(regF dst, regF tmp) %{ | |
8519 effect(DEF dst, USE tmp); | |
8520 format %{ "FITOS $tmp,$dst" %} | |
8521 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
8522 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
8523 ins_pipe(fcvtI2F); | |
8524 %} | |
8525 | |
8526 instruct convI2F_stk(regF dst, stackSlotI src) %{ | |
8527 match(Set dst (ConvI2F src)); | |
8528 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8529 expand %{ | |
8530 regF tmp; | |
8531 stkI_to_regF(tmp,src); | |
8532 convI2F_helper(dst, tmp); | |
8533 %} | |
8534 %} | |
8535 | |
8536 instruct convI2F_reg(regF dst, iRegI src) %{ | |
8537 predicate(UseVIS >= 3); | |
8538 match(Set dst (ConvI2F src)); | |
8539 ins_cost(DEFAULT_COST); | |
8540 expand %{ | |
8541 regF tmp; | |
8542 MoveI2F_reg_reg(tmp, src); | |
8543 convI2F_helper(dst, tmp); | |
8544 %} | |
8545 %} | |
8546 | |
8547 instruct convI2F_mem( regF dst, memory mem ) %{ | |
8548 match(Set dst (ConvI2F (LoadI mem))); | |
8549 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8550 size(8); | |
8551 format %{ "LDF $mem,$dst\n\t" | |
8552 "FITOS $dst,$dst" %} | |
8553 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
8554 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
8555 ins_pipe(floadF_mem); | |
8556 %} | |
8557 | |
8558 | |
8559 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
8560 match(Set dst (ConvI2L src)); | |
8561 size(4); | |
8562 format %{ "SRA $src,0,$dst\t! int->long" %} | |
8563 opcode(Assembler::sra_op3, Assembler::arith_op); | |
8564 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8565 ins_pipe(ialu_reg_reg); | |
8566 %} | |
8567 | |
8568 // Zero-extend convert int to long | |
8569 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
8570 match(Set dst (AndL (ConvI2L src) mask) ); | |
8571 size(4); | |
8572 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
8573 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8574 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8575 ins_pipe(ialu_reg_reg); | |
8576 %} | |
8577 | |
8578 // Zero-extend long | |
8579 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
8580 match(Set dst (AndL src mask) ); | |
8581 size(4); | |
8582 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
8583 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8584 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8585 ins_pipe(ialu_reg_reg); | |
8586 %} | |
8587 | |
8588 | |
0 | 8589 //----------- |
8590 // Long to Double conversion using V8 opcodes. | |
8591 // Still useful because cheetah traps and becomes | |
8592 // amazingly slow for some common numbers. | |
8593 | |
8594 // Magic constant, 0x43300000 | |
8595 instruct loadConI_x43300000(iRegI dst) %{ | |
8596 effect(DEF dst); | |
8597 size(4); | |
8598 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
8599 ins_encode(SetHi22(0x43300000, dst)); | |
8600 ins_pipe(ialu_none); | |
8601 %} | |
8602 | |
8603 // Magic constant, 0x41f00000 | |
8604 instruct loadConI_x41f00000(iRegI dst) %{ | |
8605 effect(DEF dst); | |
8606 size(4); | |
8607 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
8608 ins_encode(SetHi22(0x41f00000, dst)); | |
8609 ins_pipe(ialu_none); | |
8610 %} | |
8611 | |
8612 // Construct a double from two float halves | |
8613 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
8614 effect(DEF dst, USE src1, USE src2); | |
8615 size(8); | |
8616 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
8617 "FMOVS $src2.lo,$dst.lo" %} | |
8618 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
8619 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
8620 ins_pipe(faddD_reg_reg); | |
8621 %} | |
8622 | |
8623 // Convert integer in high half of a double register (in the lower half of | |
8624 // the double register file) to double | |
8625 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
8626 effect(DEF dst, USE src); | |
8627 size(4); | |
8628 format %{ "FITOD $src,$dst" %} | |
8629 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
8630 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
8631 ins_pipe(fcvtLHi2D); | |
8632 %} | |
8633 | |
8634 // Add float double precision | |
8635 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8636 effect(DEF dst, USE src1, USE src2); | |
8637 size(4); | |
8638 format %{ "FADDD $src1,$src2,$dst" %} | |
8639 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
8640 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8641 ins_pipe(faddD_reg_reg); | |
8642 %} | |
8643 | |
8644 // Sub float double precision | |
8645 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8646 effect(DEF dst, USE src1, USE src2); | |
8647 size(4); | |
8648 format %{ "FSUBD $src1,$src2,$dst" %} | |
8649 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
8650 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8651 ins_pipe(faddD_reg_reg); | |
8652 %} | |
8653 | |
8654 // Mul float double precision | |
8655 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8656 effect(DEF dst, USE src1, USE src2); | |
8657 size(4); | |
8658 format %{ "FMULD $src1,$src2,$dst" %} | |
8659 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
8660 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8661 ins_pipe(fmulD_reg_reg); | |
8662 %} | |
8663 | |
8664 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
8665 match(Set dst (ConvL2D src)); | |
8666 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
8667 | |
8668 expand %{ | |
8669 regD_low tmpsrc; | |
8670 iRegI ix43300000; | |
8671 iRegI ix41f00000; | |
8672 stackSlotL lx43300000; | |
8673 stackSlotL lx41f00000; | |
8674 regD_low dx43300000; | |
8675 regD dx41f00000; | |
8676 regD tmp1; | |
8677 regD_low tmp2; | |
8678 regD tmp3; | |
8679 regD tmp4; | |
8680 | |
8681 stkL_to_regD(tmpsrc, src); | |
8682 | |
8683 loadConI_x43300000(ix43300000); | |
8684 loadConI_x41f00000(ix41f00000); | |
8685 regI_to_stkLHi(lx43300000, ix43300000); | |
8686 regI_to_stkLHi(lx41f00000, ix41f00000); | |
8687 stkL_to_regD(dx43300000, lx43300000); | |
8688 stkL_to_regD(dx41f00000, lx41f00000); | |
8689 | |
8690 convI2D_regDHi_regD(tmp1, tmpsrc); | |
8691 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
8692 subD_regD_regD(tmp3, tmp2, dx43300000); | |
8693 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
8694 addD_regD_regD(dst, tmp3, tmp4); | |
8695 %} | |
8696 %} | |
8697 | |
8698 // Long to Double conversion using fast fxtof | |
8699 instruct convL2D_helper(regD dst, regD tmp) %{ | |
8700 effect(DEF dst, USE tmp); | |
8701 size(4); | |
8702 format %{ "FXTOD $tmp,$dst" %} | |
8703 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
8704 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
8705 ins_pipe(fcvtL2D); | |
8706 %} | |
8707 | |
3804 | 8708 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ |
0 | 8709 predicate(VM_Version::has_fast_fxtof()); |
8710 match(Set dst (ConvL2D src)); | |
8711 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
8712 expand %{ | |
8713 regD tmp; | |
8714 stkL_to_regD(tmp, src); | |
8715 convL2D_helper(dst, tmp); | |
8716 %} | |
8717 %} | |
8718 | |
3804 | 8719 instruct convL2D_reg(regD dst, iRegL src) %{ |
8720 predicate(UseVIS >= 3); | |
8721 match(Set dst (ConvL2D src)); | |
8722 expand %{ | |
8723 regD tmp; | |
8724 MoveL2D_reg_reg(tmp, src); | |
8725 convL2D_helper(dst, tmp); | |
8726 %} | |
8727 %} | |
0 | 8728 |
8729 // Long to Float conversion using fast fxtof | |
8730 instruct convL2F_helper(regF dst, regD tmp) %{ | |
8731 effect(DEF dst, USE tmp); | |
8732 size(4); | |
8733 format %{ "FXTOS $tmp,$dst" %} | |
8734 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
8735 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
8736 ins_pipe(fcvtL2F); | |
8737 %} | |
8738 | |
3804 | 8739 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ |
0 | 8740 match(Set dst (ConvL2F src)); |
8741 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8742 expand %{ | |
8743 regD tmp; | |
8744 stkL_to_regD(tmp, src); | |
8745 convL2F_helper(dst, tmp); | |
8746 %} | |
8747 %} | |
3804 | 8748 |
8749 instruct convL2F_reg(regF dst, iRegL src) %{ | |
8750 predicate(UseVIS >= 3); | |
8751 match(Set dst (ConvL2F src)); | |
8752 ins_cost(DEFAULT_COST); | |
8753 expand %{ | |
8754 regD tmp; | |
8755 MoveL2D_reg_reg(tmp, src); | |
8756 convL2F_helper(dst, tmp); | |
8757 %} | |
8758 %} | |
8759 | |
0 | 8760 //----------- |
8761 | |
8762 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
8763 match(Set dst (ConvL2I src)); | |
8764 #ifndef _LP64 | |
8765 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
8766 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
8767 ins_pipe(ialu_move_reg_I_to_L); | |
8768 #else | |
8769 size(4); | |
8770 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
8771 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
8772 ins_pipe(ialu_reg); | |
8773 #endif | |
8774 %} | |
8775 | |
8776 // Register Shift Right Immediate | |
8777 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
8778 match(Set dst (ConvL2I (RShiftL src cnt))); | |
8779 | |
8780 size(4); | |
8781 format %{ "SRAX $src,$cnt,$dst" %} | |
8782 opcode(Assembler::srax_op3, Assembler::arith_op); | |
8783 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
8784 ins_pipe(ialu_reg_imm); | |
8785 %} | |
8786 | |
8787 //----------Control Flow Instructions------------------------------------------ | |
8788 // Compare Instructions | |
8789 // Compare Integers | |
8790 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
8791 match(Set icc (CmpI op1 op2)); | |
8792 effect( DEF icc, USE op1, USE op2 ); | |
8793 | |
8794 size(4); | |
8795 format %{ "CMP $op1,$op2" %} | |
8796 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8797 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8798 ins_pipe(ialu_cconly_reg_reg); | |
8799 %} | |
8800 | |
8801 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
8802 match(Set icc (CmpU op1 op2)); | |
8803 | |
8804 size(4); | |
8805 format %{ "CMP $op1,$op2\t! unsigned" %} | |
8806 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8807 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8808 ins_pipe(ialu_cconly_reg_reg); | |
8809 %} | |
8810 | |
8811 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
8812 match(Set icc (CmpI op1 op2)); | |
8813 effect( DEF icc, USE op1 ); | |
8814 | |
8815 size(4); | |
8816 format %{ "CMP $op1,$op2" %} | |
8817 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8818 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8819 ins_pipe(ialu_cconly_reg_imm); | |
8820 %} | |
8821 | |
8822 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
8823 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8824 | |
8825 size(4); | |
8826 format %{ "BTST $op2,$op1" %} | |
8827 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8828 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8829 ins_pipe(ialu_cconly_reg_reg_zero); | |
8830 %} | |
8831 | |
8832 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
8833 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8834 | |
8835 size(4); | |
8836 format %{ "BTST $op2,$op1" %} | |
8837 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8838 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8839 ins_pipe(ialu_cconly_reg_imm_zero); | |
8840 %} | |
8841 | |
8842 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
8843 match(Set xcc (CmpL op1 op2)); | |
8844 effect( DEF xcc, USE op1, USE op2 ); | |
8845 | |
8846 size(4); | |
8847 format %{ "CMP $op1,$op2\t\t! long" %} | |
8848 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8849 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8850 ins_pipe(ialu_cconly_reg_reg); | |
8851 %} | |
8852 | |
8853 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
8854 match(Set xcc (CmpL op1 con)); | |
8855 effect( DEF xcc, USE op1, USE con ); | |
8856 | |
8857 size(4); | |
8858 format %{ "CMP $op1,$con\t\t! long" %} | |
8859 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8860 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
8861 ins_pipe(ialu_cconly_reg_reg); | |
8862 %} | |
8863 | |
8864 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
8865 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
8866 effect( DEF xcc, USE op1, USE op2 ); | |
8867 | |
8868 size(4); | |
8869 format %{ "BTST $op1,$op2\t\t! long" %} | |
8870 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8871 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8872 ins_pipe(ialu_cconly_reg_reg); | |
8873 %} | |
8874 | |
8875 // useful for checking the alignment of a pointer: | |
8876 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
8877 match(Set xcc (CmpL (AndL op1 con) zero)); | |
8878 effect( DEF xcc, USE op1, USE con ); | |
8879 | |
8880 size(4); | |
8881 format %{ "BTST $op1,$con\t\t! long" %} | |
8882 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8883 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
8884 ins_pipe(ialu_cconly_reg_reg); | |
8885 %} | |
8886 | |
8887 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ | |
8888 match(Set icc (CmpU op1 op2)); | |
8889 | |
8890 size(4); | |
8891 format %{ "CMP $op1,$op2\t! unsigned" %} | |
8892 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8893 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8894 ins_pipe(ialu_cconly_reg_imm); | |
8895 %} | |
8896 | |
8897 // Compare Pointers | |
8898 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
8899 match(Set pcc (CmpP op1 op2)); | |
8900 | |
8901 size(4); | |
8902 format %{ "CMP $op1,$op2\t! ptr" %} | |
8903 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8904 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8905 ins_pipe(ialu_cconly_reg_reg); | |
8906 %} | |
8907 | |
8908 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
8909 match(Set pcc (CmpP op1 op2)); | |
8910 | |
8911 size(4); | |
8912 format %{ "CMP $op1,$op2\t! ptr" %} | |
8913 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8914 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8915 ins_pipe(ialu_cconly_reg_imm); | |
8916 %} | |
8917 | |
164
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8918 // Compare Narrow oops |
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8919 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
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8920 match(Set icc (CmpN op1 op2)); |
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8921 |
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8922 size(4); |
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8923 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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8924 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8925 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
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8926 ins_pipe(ialu_cconly_reg_reg); |
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8927 %} |
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8928 |
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8929 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
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8930 match(Set icc (CmpN op1 op2)); |
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8931 |
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8932 size(4); |
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8933 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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8934 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8935 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
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8936 ins_pipe(ialu_cconly_reg_imm); |
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8937 %} |
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8938 |
0 | 8939 //----------Max and Min-------------------------------------------------------- |
8940 // Min Instructions | |
8941 // Conditional move for min | |
8942 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
8943 effect( USE_DEF op2, USE op1, USE icc ); | |
8944 | |
8945 size(4); | |
8946 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
8947 opcode(Assembler::less); | |
8948 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
8949 ins_pipe(ialu_reg_flags); | |
8950 %} | |
8951 | |
8952 // Min Register with Register. | |
8953 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
8954 match(Set op2 (MinI op1 op2)); | |
8955 ins_cost(DEFAULT_COST*2); | |
8956 expand %{ | |
8957 flagsReg icc; | |
8958 compI_iReg(icc,op1,op2); | |
8959 cmovI_reg_lt(op2,op1,icc); | |
8960 %} | |
8961 %} | |
8962 | |
8963 // Max Instructions | |
8964 // Conditional move for max | |
8965 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
8966 effect( USE_DEF op2, USE op1, USE icc ); | |
8967 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
8968 opcode(Assembler::greater); | |
8969 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
8970 ins_pipe(ialu_reg_flags); | |
8971 %} | |
8972 | |
8973 // Max Register with Register | |
8974 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
8975 match(Set op2 (MaxI op1 op2)); | |
8976 ins_cost(DEFAULT_COST*2); | |
8977 expand %{ | |
8978 flagsReg icc; | |
8979 compI_iReg(icc,op1,op2); | |
8980 cmovI_reg_gt(op2,op1,icc); | |
8981 %} | |
8982 %} | |
8983 | |
8984 | |
8985 //----------Float Compares---------------------------------------------------- | |
8986 // Compare floating, generate condition code | |
8987 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
8988 match(Set fcc (CmpF src1 src2)); | |
8989 | |
8990 size(4); | |
8991 format %{ "FCMPs $fcc,$src1,$src2" %} | |
8992 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
8993 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
8994 ins_pipe(faddF_fcc_reg_reg_zero); | |
8995 %} | |
8996 | |
8997 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
8998 match(Set fcc (CmpD src1 src2)); | |
8999 | |
9000 size(4); | |
9001 format %{ "FCMPd $fcc,$src1,$src2" %} | |
9002 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
9003 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
9004 ins_pipe(faddD_fcc_reg_reg_zero); | |
9005 %} | |
9006 | |
9007 | |
9008 // Compare floating, generate -1,0,1 | |
9009 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
9010 match(Set dst (CmpF3 src1 src2)); | |
9011 effect(KILL fcc0); | |
9012 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
9013 format %{ "fcmpl $dst,$src1,$src2" %} | |
9014 // Primary = float | |
9015 opcode( true ); | |
9016 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
9017 ins_pipe( floating_cmp ); | |
9018 %} | |
9019 | |
9020 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
9021 match(Set dst (CmpD3 src1 src2)); | |
9022 effect(KILL fcc0); | |
9023 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
9024 format %{ "dcmpl $dst,$src1,$src2" %} | |
9025 // Primary = double (not float) | |
9026 opcode( false ); | |
9027 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
9028 ins_pipe( floating_cmp ); | |
9029 %} | |
9030 | |
9031 //----------Branches--------------------------------------------------------- | |
9032 // Jump | |
9033 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
9034 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
9035 match(Jump switch_val); | |
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9036 effect(TEMP table); |
0 | 9037 |
9038 ins_cost(350); | |
9039 | |
2008 | 9040 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" |
9041 "LD [O7 + $switch_val], O7\n\t" | |
4114
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9042 "JUMP O7" %} |
2008 | 9043 ins_encode %{ |
9044 // Calculate table address into a register. | |
9045 Register table_reg; | |
9046 Register label_reg = O7; | |
4114
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9047 // If we are calculating the size of this instruction don't trust |
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9048 // zero offsets because they might change when |
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9049 // MachConstantBaseNode decides to optimize the constant table |
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9050 // base. |
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9051 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) { |
2008 | 9052 table_reg = $constanttablebase; |
9053 } else { | |
9054 table_reg = O7; | |
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9055 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); |
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9056 __ add($constanttablebase, con_offset, table_reg); |
2008 | 9057 } |
9058 | |
9059 // Jump to base address + switch value | |
9060 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); | |
9061 __ jmp(label_reg, G0); | |
9062 __ delayed()->nop(); | |
9063 %} | |
0 | 9064 ins_pipe(ialu_reg_reg); |
9065 %} | |
9066 | |
9067 // Direct Branch. Use V8 version with longer range. | |
9068 instruct branch(label labl) %{ | |
9069 match(Goto); | |
9070 effect(USE labl); | |
9071 | |
9072 size(8); | |
9073 ins_cost(BRANCH_COST); | |
9074 format %{ "BA $labl" %} | |
3839 | 9075 ins_encode %{ |
9076 Label* L = $labl$$label; | |
9077 __ ba(*L); | |
9078 __ delayed()->nop(); | |
9079 %} | |
0 | 9080 ins_pipe(br); |
9081 %} | |
9082 | |
3851 | 9083 // Direct Branch, short with no delay slot |
9084 instruct branch_short(label labl) %{ | |
9085 match(Goto); | |
9086 predicate(UseCBCond); | |
9087 effect(USE labl); | |
9088 | |
9089 size(4); | |
9090 ins_cost(BRANCH_COST); | |
9091 format %{ "BA $labl\t! short branch" %} | |
9092 ins_encode %{ | |
9093 Label* L = $labl$$label; | |
9094 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9095 __ ba_short(*L); | |
9096 %} | |
9097 ins_short_branch(1); | |
9098 ins_avoid_back_to_back(1); | |
9099 ins_pipe(cbcond_reg_imm); | |
9100 %} | |
9101 | |
0 | 9102 // Conditional Direct Branch |
9103 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
9104 match(If cmp icc); | |
9105 effect(USE labl); | |
9106 | |
9107 size(8); | |
9108 ins_cost(BRANCH_COST); | |
9109 format %{ "BP$cmp $icc,$labl" %} | |
9110 // Prim = bits 24-22, Secnd = bits 31-30 | |
9111 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9112 ins_pipe(br_cc); | |
9113 %} | |
9114 | |
9115 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9116 match(If cmp icc); | |
9117 effect(USE labl); | |
9118 | |
3851 | 9119 ins_cost(BRANCH_COST); |
0 | 9120 format %{ "BP$cmp $icc,$labl" %} |
9121 // Prim = bits 24-22, Secnd = bits 31-30 | |
9122 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9123 ins_pipe(br_cc); | |
9124 %} | |
9125 | |
9126 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
9127 match(If cmp pcc); | |
9128 effect(USE labl); | |
9129 | |
9130 size(8); | |
9131 ins_cost(BRANCH_COST); | |
9132 format %{ "BP$cmp $pcc,$labl" %} | |
3839 | 9133 ins_encode %{ |
9134 Label* L = $labl$$label; | |
9135 Assembler::Predict predict_taken = | |
9136 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9137 | |
9138 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
9139 __ delayed()->nop(); | |
9140 %} | |
0 | 9141 ins_pipe(br_cc); |
9142 %} | |
9143 | |
9144 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
9145 match(If cmp fcc); | |
9146 effect(USE labl); | |
9147 | |
9148 size(8); | |
9149 ins_cost(BRANCH_COST); | |
9150 format %{ "FBP$cmp $fcc,$labl" %} | |
3839 | 9151 ins_encode %{ |
9152 Label* L = $labl$$label; | |
9153 Assembler::Predict predict_taken = | |
9154 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9155 | |
9156 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); | |
9157 __ delayed()->nop(); | |
9158 %} | |
0 | 9159 ins_pipe(br_fcc); |
9160 %} | |
9161 | |
9162 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
9163 match(CountedLoopEnd cmp icc); | |
9164 effect(USE labl); | |
9165 | |
9166 size(8); | |
9167 ins_cost(BRANCH_COST); | |
9168 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9169 // Prim = bits 24-22, Secnd = bits 31-30 | |
9170 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9171 ins_pipe(br_cc); | |
9172 %} | |
9173 | |
9174 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9175 match(CountedLoopEnd cmp icc); | |
9176 effect(USE labl); | |
9177 | |
9178 size(8); | |
9179 ins_cost(BRANCH_COST); | |
9180 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9181 // Prim = bits 24-22, Secnd = bits 31-30 | |
9182 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9183 ins_pipe(br_cc); | |
9184 %} | |
9185 | |
3851 | 9186 // Compare and branch instructions |
9187 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9188 match(If cmp (CmpI op1 op2)); | |
9189 effect(USE labl, KILL icc); | |
9190 | |
9191 size(12); | |
9192 ins_cost(BRANCH_COST); | |
9193 format %{ "CMP $op1,$op2\t! int\n\t" | |
9194 "BP$cmp $labl" %} | |
9195 ins_encode %{ | |
9196 Label* L = $labl$$label; | |
9197 Assembler::Predict predict_taken = | |
9198 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9199 __ cmp($op1$$Register, $op2$$Register); | |
9200 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9201 __ delayed()->nop(); | |
9202 %} | |
9203 ins_pipe(cmp_br_reg_reg); | |
9204 %} | |
9205 | |
9206 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9207 match(If cmp (CmpI op1 op2)); | |
9208 effect(USE labl, KILL icc); | |
9209 | |
9210 size(12); | |
9211 ins_cost(BRANCH_COST); | |
9212 format %{ "CMP $op1,$op2\t! int\n\t" | |
9213 "BP$cmp $labl" %} | |
9214 ins_encode %{ | |
9215 Label* L = $labl$$label; | |
9216 Assembler::Predict predict_taken = | |
9217 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9218 __ cmp($op1$$Register, $op2$$constant); | |
9219 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9220 __ delayed()->nop(); | |
9221 %} | |
9222 ins_pipe(cmp_br_reg_imm); | |
9223 %} | |
9224 | |
9225 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
9226 match(If cmp (CmpU op1 op2)); | |
9227 effect(USE labl, KILL icc); | |
9228 | |
9229 size(12); | |
9230 ins_cost(BRANCH_COST); | |
9231 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
9232 "BP$cmp $labl" %} | |
9233 ins_encode %{ | |
9234 Label* L = $labl$$label; | |
9235 Assembler::Predict predict_taken = | |
9236 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9237 __ cmp($op1$$Register, $op2$$Register); | |
9238 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9239 __ delayed()->nop(); | |
9240 %} | |
9241 ins_pipe(cmp_br_reg_reg); | |
9242 %} | |
9243 | |
9244 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
9245 match(If cmp (CmpU op1 op2)); | |
9246 effect(USE labl, KILL icc); | |
9247 | |
9248 size(12); | |
9249 ins_cost(BRANCH_COST); | |
9250 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
9251 "BP$cmp $labl" %} | |
9252 ins_encode %{ | |
9253 Label* L = $labl$$label; | |
9254 Assembler::Predict predict_taken = | |
9255 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9256 __ cmp($op1$$Register, $op2$$constant); | |
9257 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9258 __ delayed()->nop(); | |
9259 %} | |
9260 ins_pipe(cmp_br_reg_imm); | |
9261 %} | |
9262 | |
9263 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
9264 match(If cmp (CmpL op1 op2)); | |
9265 effect(USE labl, KILL xcc); | |
9266 | |
9267 size(12); | |
9268 ins_cost(BRANCH_COST); | |
9269 format %{ "CMP $op1,$op2\t! long\n\t" | |
9270 "BP$cmp $labl" %} | |
9271 ins_encode %{ | |
9272 Label* L = $labl$$label; | |
9273 Assembler::Predict predict_taken = | |
9274 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9275 __ cmp($op1$$Register, $op2$$Register); | |
9276 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
9277 __ delayed()->nop(); | |
9278 %} | |
9279 ins_pipe(cmp_br_reg_reg); | |
9280 %} | |
9281 | |
9282 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
9283 match(If cmp (CmpL op1 op2)); | |
9284 effect(USE labl, KILL xcc); | |
9285 | |
9286 size(12); | |
9287 ins_cost(BRANCH_COST); | |
9288 format %{ "CMP $op1,$op2\t! long\n\t" | |
9289 "BP$cmp $labl" %} | |
9290 ins_encode %{ | |
9291 Label* L = $labl$$label; | |
9292 Assembler::Predict predict_taken = | |
9293 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9294 __ cmp($op1$$Register, $op2$$constant); | |
9295 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
9296 __ delayed()->nop(); | |
9297 %} | |
9298 ins_pipe(cmp_br_reg_imm); | |
9299 %} | |
9300 | |
9301 // Compare Pointers and branch | |
9302 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
9303 match(If cmp (CmpP op1 op2)); | |
9304 effect(USE labl, KILL pcc); | |
9305 | |
9306 size(12); | |
9307 ins_cost(BRANCH_COST); | |
9308 format %{ "CMP $op1,$op2\t! ptr\n\t" | |
9309 "B$cmp $labl" %} | |
9310 ins_encode %{ | |
9311 Label* L = $labl$$label; | |
9312 Assembler::Predict predict_taken = | |
9313 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9314 __ cmp($op1$$Register, $op2$$Register); | |
9315 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
9316 __ delayed()->nop(); | |
9317 %} | |
9318 ins_pipe(cmp_br_reg_reg); | |
9319 %} | |
9320 | |
9321 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
9322 match(If cmp (CmpP op1 null)); | |
9323 effect(USE labl, KILL pcc); | |
9324 | |
9325 size(12); | |
9326 ins_cost(BRANCH_COST); | |
9327 format %{ "CMP $op1,0\t! ptr\n\t" | |
9328 "B$cmp $labl" %} | |
9329 ins_encode %{ | |
9330 Label* L = $labl$$label; | |
9331 Assembler::Predict predict_taken = | |
9332 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9333 __ cmp($op1$$Register, G0); | |
9334 // bpr() is not used here since it has shorter distance. | |
9335 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
9336 __ delayed()->nop(); | |
9337 %} | |
9338 ins_pipe(cmp_br_reg_reg); | |
9339 %} | |
9340 | |
9341 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
9342 match(If cmp (CmpN op1 op2)); | |
9343 effect(USE labl, KILL icc); | |
9344 | |
9345 size(12); | |
9346 ins_cost(BRANCH_COST); | |
9347 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" | |
9348 "BP$cmp $labl" %} | |
9349 ins_encode %{ | |
9350 Label* L = $labl$$label; | |
9351 Assembler::Predict predict_taken = | |
9352 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9353 __ cmp($op1$$Register, $op2$$Register); | |
9354 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9355 __ delayed()->nop(); | |
9356 %} | |
9357 ins_pipe(cmp_br_reg_reg); | |
9358 %} | |
9359 | |
9360 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
9361 match(If cmp (CmpN op1 null)); | |
9362 effect(USE labl, KILL icc); | |
9363 | |
9364 size(12); | |
9365 ins_cost(BRANCH_COST); | |
9366 format %{ "CMP $op1,0\t! compressed ptr\n\t" | |
9367 "BP$cmp $labl" %} | |
9368 ins_encode %{ | |
9369 Label* L = $labl$$label; | |
9370 Assembler::Predict predict_taken = | |
9371 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9372 __ cmp($op1$$Register, G0); | |
9373 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9374 __ delayed()->nop(); | |
9375 %} | |
9376 ins_pipe(cmp_br_reg_reg); | |
9377 %} | |
9378 | |
9379 // Loop back branch | |
9380 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9381 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9382 effect(USE labl, KILL icc); | |
9383 | |
9384 size(12); | |
9385 ins_cost(BRANCH_COST); | |
9386 format %{ "CMP $op1,$op2\t! int\n\t" | |
9387 "BP$cmp $labl\t! Loop end" %} | |
9388 ins_encode %{ | |
9389 Label* L = $labl$$label; | |
9390 Assembler::Predict predict_taken = | |
9391 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9392 __ cmp($op1$$Register, $op2$$Register); | |
9393 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9394 __ delayed()->nop(); | |
9395 %} | |
9396 ins_pipe(cmp_br_reg_reg); | |
9397 %} | |
9398 | |
9399 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9400 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9401 effect(USE labl, KILL icc); | |
9402 | |
9403 size(12); | |
9404 ins_cost(BRANCH_COST); | |
9405 format %{ "CMP $op1,$op2\t! int\n\t" | |
9406 "BP$cmp $labl\t! Loop end" %} | |
9407 ins_encode %{ | |
9408 Label* L = $labl$$label; | |
9409 Assembler::Predict predict_taken = | |
9410 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9411 __ cmp($op1$$Register, $op2$$constant); | |
9412 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9413 __ delayed()->nop(); | |
9414 %} | |
9415 ins_pipe(cmp_br_reg_imm); | |
9416 %} | |
9417 | |
9418 // Short compare and branch instructions | |
9419 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9420 match(If cmp (CmpI op1 op2)); | |
9421 predicate(UseCBCond); | |
9422 effect(USE labl, KILL icc); | |
9423 | |
9424 size(4); | |
9425 ins_cost(BRANCH_COST); | |
9426 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
9427 ins_encode %{ | |
9428 Label* L = $labl$$label; | |
9429 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9430 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9431 %} | |
9432 ins_short_branch(1); | |
9433 ins_avoid_back_to_back(1); | |
9434 ins_pipe(cbcond_reg_reg); | |
9435 %} | |
9436 | |
9437 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9438 match(If cmp (CmpI op1 op2)); | |
9439 predicate(UseCBCond); | |
9440 effect(USE labl, KILL icc); | |
9441 | |
9442 size(4); | |
9443 ins_cost(BRANCH_COST); | |
9444 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
9445 ins_encode %{ | |
9446 Label* L = $labl$$label; | |
9447 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9448 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
9449 %} | |
9450 ins_short_branch(1); | |
9451 ins_avoid_back_to_back(1); | |
9452 ins_pipe(cbcond_reg_imm); | |
9453 %} | |
9454 | |
9455 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
9456 match(If cmp (CmpU op1 op2)); | |
9457 predicate(UseCBCond); | |
9458 effect(USE labl, KILL icc); | |
9459 | |
9460 size(4); | |
9461 ins_cost(BRANCH_COST); | |
9462 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
9463 ins_encode %{ | |
9464 Label* L = $labl$$label; | |
9465 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9466 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9467 %} | |
9468 ins_short_branch(1); | |
9469 ins_avoid_back_to_back(1); | |
9470 ins_pipe(cbcond_reg_reg); | |
9471 %} | |
9472 | |
9473 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
9474 match(If cmp (CmpU op1 op2)); | |
9475 predicate(UseCBCond); | |
9476 effect(USE labl, KILL icc); | |
9477 | |
9478 size(4); | |
9479 ins_cost(BRANCH_COST); | |
9480 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
9481 ins_encode %{ | |
9482 Label* L = $labl$$label; | |
9483 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9484 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
9485 %} | |
9486 ins_short_branch(1); | |
9487 ins_avoid_back_to_back(1); | |
9488 ins_pipe(cbcond_reg_imm); | |
9489 %} | |
9490 | |
9491 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
9492 match(If cmp (CmpL op1 op2)); | |
9493 predicate(UseCBCond); | |
9494 effect(USE labl, KILL xcc); | |
9495 | |
9496 size(4); | |
9497 ins_cost(BRANCH_COST); | |
9498 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
9499 ins_encode %{ | |
9500 Label* L = $labl$$label; | |
9501 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9502 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); | |
9503 %} | |
9504 ins_short_branch(1); | |
9505 ins_avoid_back_to_back(1); | |
9506 ins_pipe(cbcond_reg_reg); | |
9507 %} | |
9508 | |
9509 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
9510 match(If cmp (CmpL op1 op2)); | |
9511 predicate(UseCBCond); | |
9512 effect(USE labl, KILL xcc); | |
9513 | |
9514 size(4); | |
9515 ins_cost(BRANCH_COST); | |
9516 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
9517 ins_encode %{ | |
9518 Label* L = $labl$$label; | |
9519 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9520 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); | |
9521 %} | |
9522 ins_short_branch(1); | |
9523 ins_avoid_back_to_back(1); | |
9524 ins_pipe(cbcond_reg_imm); | |
9525 %} | |
9526 | |
9527 // Compare Pointers and branch | |
9528 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
9529 match(If cmp (CmpP op1 op2)); | |
9530 predicate(UseCBCond); | |
9531 effect(USE labl, KILL pcc); | |
9532 | |
9533 size(4); | |
9534 ins_cost(BRANCH_COST); | |
9535 #ifdef _LP64 | |
9536 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} | |
9537 #else | |
9538 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %} | |
9539 #endif | |
9540 ins_encode %{ | |
9541 Label* L = $labl$$label; | |
9542 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9543 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); | |
9544 %} | |
9545 ins_short_branch(1); | |
9546 ins_avoid_back_to_back(1); | |
9547 ins_pipe(cbcond_reg_reg); | |
9548 %} | |
9549 | |
9550 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
9551 match(If cmp (CmpP op1 null)); | |
9552 predicate(UseCBCond); | |
9553 effect(USE labl, KILL pcc); | |
9554 | |
9555 size(4); | |
9556 ins_cost(BRANCH_COST); | |
9557 #ifdef _LP64 | |
9558 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} | |
9559 #else | |
9560 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %} | |
9561 #endif | |
9562 ins_encode %{ | |
9563 Label* L = $labl$$label; | |
9564 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9565 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); | |
9566 %} | |
9567 ins_short_branch(1); | |
9568 ins_avoid_back_to_back(1); | |
9569 ins_pipe(cbcond_reg_reg); | |
9570 %} | |
9571 | |
9572 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
9573 match(If cmp (CmpN op1 op2)); | |
9574 predicate(UseCBCond); | |
9575 effect(USE labl, KILL icc); | |
9576 | |
9577 size(4); | |
9578 ins_cost(BRANCH_COST); | |
9579 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %} | |
9580 ins_encode %{ | |
9581 Label* L = $labl$$label; | |
9582 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9583 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9584 %} | |
9585 ins_short_branch(1); | |
9586 ins_avoid_back_to_back(1); | |
9587 ins_pipe(cbcond_reg_reg); | |
9588 %} | |
9589 | |
9590 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
9591 match(If cmp (CmpN op1 null)); | |
9592 predicate(UseCBCond); | |
9593 effect(USE labl, KILL icc); | |
9594 | |
9595 size(4); | |
9596 ins_cost(BRANCH_COST); | |
9597 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} | |
9598 ins_encode %{ | |
9599 Label* L = $labl$$label; | |
9600 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9601 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); | |
9602 %} | |
9603 ins_short_branch(1); | |
9604 ins_avoid_back_to_back(1); | |
9605 ins_pipe(cbcond_reg_reg); | |
9606 %} | |
9607 | |
9608 // Loop back branch | |
9609 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9610 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9611 predicate(UseCBCond); | |
9612 effect(USE labl, KILL icc); | |
9613 | |
9614 size(4); | |
9615 ins_cost(BRANCH_COST); | |
9616 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
9617 ins_encode %{ | |
9618 Label* L = $labl$$label; | |
9619 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9620 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9621 %} | |
9622 ins_short_branch(1); | |
9623 ins_avoid_back_to_back(1); | |
9624 ins_pipe(cbcond_reg_reg); | |
9625 %} | |
9626 | |
9627 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9628 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9629 predicate(UseCBCond); | |
9630 effect(USE labl, KILL icc); | |
9631 | |
9632 size(4); | |
9633 ins_cost(BRANCH_COST); | |
9634 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
9635 ins_encode %{ | |
9636 Label* L = $labl$$label; | |
9637 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9638 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
9639 %} | |
9640 ins_short_branch(1); | |
9641 ins_avoid_back_to_back(1); | |
9642 ins_pipe(cbcond_reg_imm); | |
9643 %} | |
9644 | |
9645 // Branch-on-register tests all 64 bits. We assume that values | |
9646 // in 64-bit registers always remains zero or sign extended | |
9647 // unless our code munges the high bits. Interrupts can chop | |
9648 // the high order bits to zero or sign at any time. | |
9649 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
9650 match(If cmp (CmpI op1 zero)); | |
9651 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
9652 effect(USE labl); | |
9653 | |
9654 size(8); | |
9655 ins_cost(BRANCH_COST); | |
9656 format %{ "BR$cmp $op1,$labl" %} | |
9657 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
9658 ins_pipe(br_reg); | |
9659 %} | |
9660 | |
9661 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
9662 match(If cmp (CmpP op1 null)); | |
9663 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
9664 effect(USE labl); | |
9665 | |
9666 size(8); | |
9667 ins_cost(BRANCH_COST); | |
9668 format %{ "BR$cmp $op1,$labl" %} | |
9669 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
9670 ins_pipe(br_reg); | |
9671 %} | |
9672 | |
9673 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
9674 match(If cmp (CmpL op1 zero)); | |
9675 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
9676 effect(USE labl); | |
9677 | |
9678 size(8); | |
9679 ins_cost(BRANCH_COST); | |
9680 format %{ "BR$cmp $op1,$labl" %} | |
9681 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
9682 ins_pipe(br_reg); | |
9683 %} | |
9684 | |
9685 | |
0 | 9686 // ============================================================================ |
9687 // Long Compare | |
9688 // | |
9689 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
9690 // is tricky. The flavor of compare used depends on whether we are testing | |
9691 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
9692 // The GE test is the negated LT test. The LE test can be had by commuting | |
9693 // the operands (yielding a GE test) and then negating; negate again for the | |
9694 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
9695 // NE test is negated from that. | |
9696 | |
9697 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
9698 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
9699 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
9700 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
9701 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
9702 // foo match ends up with the wrong leaf. One fix is to not match both | |
9703 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
9704 // both forms beat the trinary form of long-compare and both are very useful | |
9705 // on Intel which has so few registers. | |
9706 | |
9707 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
9708 match(If cmp xcc); | |
9709 effect(USE labl); | |
9710 | |
9711 size(8); | |
9712 ins_cost(BRANCH_COST); | |
9713 format %{ "BP$cmp $xcc,$labl" %} | |
3839 | 9714 ins_encode %{ |
9715 Label* L = $labl$$label; | |
9716 Assembler::Predict predict_taken = | |
9717 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9718 | |
9719 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
9720 __ delayed()->nop(); | |
9721 %} | |
0 | 9722 ins_pipe(br_cc); |
9723 %} | |
9724 | |
9725 // Manifest a CmpL3 result in an integer register. Very painful. | |
9726 // This is the test to avoid. | |
9727 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
9728 match(Set dst (CmpL3 src1 src2) ); | |
9729 effect( KILL ccr ); | |
9730 ins_cost(6*DEFAULT_COST); | |
9731 size(24); | |
9732 format %{ "CMP $src1,$src2\t\t! long\n" | |
9733 "\tBLT,a,pn done\n" | |
9734 "\tMOV -1,$dst\t! delay slot\n" | |
9735 "\tBGT,a,pn done\n" | |
9736 "\tMOV 1,$dst\t! delay slot\n" | |
9737 "\tCLR $dst\n" | |
9738 "done:" %} | |
9739 ins_encode( cmpl_flag(src1,src2,dst) ); | |
9740 ins_pipe(cmpL_reg); | |
9741 %} | |
9742 | |
9743 // Conditional move | |
9744 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
9745 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
9746 ins_cost(150); | |
9747 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
9748 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9749 ins_pipe(ialu_reg); | |
9750 %} | |
9751 | |
9752 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
9753 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
9754 ins_cost(140); | |
9755 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
9756 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9757 ins_pipe(ialu_imm); | |
9758 %} | |
9759 | |
9760 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
9761 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
9762 ins_cost(150); | |
9763 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9764 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9765 ins_pipe(ialu_reg); | |
9766 %} | |
9767 | |
9768 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
9769 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
9770 ins_cost(140); | |
9771 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9772 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9773 ins_pipe(ialu_imm); | |
9774 %} | |
9775 | |
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9776 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
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9777 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
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9778 ins_cost(150); |
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9779 format %{ "MOV$cmp $xcc,$src,$dst" %} |
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9780 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
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9781 ins_pipe(ialu_reg); |
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9782 %} |
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9783 |
0 | 9784 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
9785 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
9786 ins_cost(150); | |
9787 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9788 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9789 ins_pipe(ialu_reg); | |
9790 %} | |
9791 | |
9792 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
9793 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
9794 ins_cost(140); | |
9795 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9796 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9797 ins_pipe(ialu_imm); | |
9798 %} | |
9799 | |
9800 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
9801 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
9802 ins_cost(150); | |
9803 opcode(0x101); | |
9804 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
9805 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9806 ins_pipe(int_conditional_float_move); | |
9807 %} | |
9808 | |
9809 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
9810 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
9811 ins_cost(150); | |
9812 opcode(0x102); | |
9813 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
9814 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9815 ins_pipe(int_conditional_float_move); | |
9816 %} | |
9817 | |
9818 // ============================================================================ | |
9819 // Safepoint Instruction | |
9820 instruct safePoint_poll(iRegP poll) %{ | |
9821 match(SafePoint poll); | |
9822 effect(USE poll); | |
9823 | |
9824 size(4); | |
9825 #ifdef _LP64 | |
9826 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
9827 #else | |
9828 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
9829 #endif | |
9830 ins_encode %{ | |
9831 __ relocate(relocInfo::poll_type); | |
9832 __ ld_ptr($poll$$Register, 0, G0); | |
9833 %} | |
9834 ins_pipe(loadPollP); | |
9835 %} | |
9836 | |
9837 // ============================================================================ | |
9838 // Call Instructions | |
9839 // Call Java Static Instruction | |
9840 instruct CallStaticJavaDirect( method meth ) %{ | |
9841 match(CallStaticJava); | |
1567 | 9842 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
0 | 9843 effect(USE meth); |
9844 | |
9845 size(8); | |
9846 ins_cost(CALL_COST); | |
9847 format %{ "CALL,static ; NOP ==> " %} | |
9848 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
9849 ins_pipe(simple_call); | |
9850 %} | |
9851 | |
1567 | 9852 // Call Java Static Instruction (method handle version) |
9853 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ | |
9854 match(CallStaticJava); | |
9855 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); | |
9856 effect(USE meth, KILL l7_mh_SP_save); | |
9857 | |
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9858 size(16); |
1567 | 9859 ins_cost(CALL_COST); |
9860 format %{ "CALL,static/MethodHandle" %} | |
9861 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); | |
9862 ins_pipe(simple_call); | |
9863 %} | |
9864 | |
0 | 9865 // Call Java Dynamic Instruction |
9866 instruct CallDynamicJavaDirect( method meth ) %{ | |
9867 match(CallDynamicJava); | |
9868 effect(USE meth); | |
9869 | |
9870 ins_cost(CALL_COST); | |
9871 format %{ "SET (empty),R_G5\n\t" | |
9872 "CALL,dynamic ; NOP ==> " %} | |
9873 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
9874 ins_pipe(call); | |
9875 %} | |
9876 | |
9877 // Call Runtime Instruction | |
9878 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
9879 match(CallRuntime); | |
9880 effect(USE meth, KILL l7); | |
9881 ins_cost(CALL_COST); | |
9882 format %{ "CALL,runtime" %} | |
9883 ins_encode( Java_To_Runtime( meth ), | |
9884 call_epilog, adjust_long_from_native_call ); | |
9885 ins_pipe(simple_call); | |
9886 %} | |
9887 | |
9888 // Call runtime without safepoint - same as CallRuntime | |
9889 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
9890 match(CallLeaf); | |
9891 effect(USE meth, KILL l7); | |
9892 ins_cost(CALL_COST); | |
9893 format %{ "CALL,runtime leaf" %} | |
9894 ins_encode( Java_To_Runtime( meth ), | |
9895 call_epilog, | |
9896 adjust_long_from_native_call ); | |
9897 ins_pipe(simple_call); | |
9898 %} | |
9899 | |
9900 // Call runtime without safepoint - same as CallLeaf | |
9901 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
9902 match(CallLeafNoFP); | |
9903 effect(USE meth, KILL l7); | |
9904 ins_cost(CALL_COST); | |
9905 format %{ "CALL,runtime leaf nofp" %} | |
9906 ins_encode( Java_To_Runtime( meth ), | |
9907 call_epilog, | |
9908 adjust_long_from_native_call ); | |
9909 ins_pipe(simple_call); | |
9910 %} | |
9911 | |
9912 // Tail Call; Jump from runtime stub to Java code. | |
9913 // Also known as an 'interprocedural jump'. | |
9914 // Target of jump will eventually return to caller. | |
9915 // TailJump below removes the return address. | |
9916 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
9917 match(TailCall jump_target method_oop ); | |
9918 | |
9919 ins_cost(CALL_COST); | |
9920 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
9921 ins_encode(form_jmpl(jump_target)); | |
9922 ins_pipe(tail_call); | |
9923 %} | |
9924 | |
9925 | |
9926 // Return Instruction | |
9927 instruct Ret() %{ | |
9928 match(Return); | |
9929 | |
9930 // The epilogue node did the ret already. | |
9931 size(0); | |
9932 format %{ "! return" %} | |
9933 ins_encode(); | |
9934 ins_pipe(empty); | |
9935 %} | |
9936 | |
9937 | |
9938 // Tail Jump; remove the return address; jump to target. | |
9939 // TailCall above leaves the return address around. | |
9940 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
9941 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
9942 // "restore" before this instruction (in Epilogue), we need to materialize it | |
9943 // in %i0. | |
9944 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
9945 match( TailJump jump_target ex_oop ); | |
9946 ins_cost(CALL_COST); | |
9947 format %{ "! discard R_O7\n\t" | |
9948 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
9949 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
9950 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
9951 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
9952 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
9953 ins_pipe(tail_call); | |
9954 %} | |
9955 | |
9956 // Create exception oop: created by stack-crawling runtime code. | |
9957 // Created exception is now available to this handler, and is setup | |
9958 // just prior to jumping to this handler. No code emitted. | |
9959 instruct CreateException( o0RegP ex_oop ) | |
9960 %{ | |
9961 match(Set ex_oop (CreateEx)); | |
9962 ins_cost(0); | |
9963 | |
9964 size(0); | |
9965 // use the following format syntax | |
9966 format %{ "! exception oop is in R_O0; no code emitted" %} | |
9967 ins_encode(); | |
9968 ins_pipe(empty); | |
9969 %} | |
9970 | |
9971 | |
9972 // Rethrow exception: | |
9973 // The exception oop will come in the first argument position. | |
9974 // Then JUMP (not call) to the rethrow stub code. | |
9975 instruct RethrowException() | |
9976 %{ | |
9977 match(Rethrow); | |
9978 ins_cost(CALL_COST); | |
9979 | |
9980 // use the following format syntax | |
9981 format %{ "Jmp rethrow_stub" %} | |
9982 ins_encode(enc_rethrow); | |
9983 ins_pipe(tail_call); | |
9984 %} | |
9985 | |
9986 | |
9987 // Die now | |
9988 instruct ShouldNotReachHere( ) | |
9989 %{ | |
9990 match(Halt); | |
9991 ins_cost(CALL_COST); | |
9992 | |
9993 size(4); | |
9994 // Use the following format syntax | |
9995 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
9996 ins_encode( form2_illtrap() ); | |
9997 ins_pipe(tail_call); | |
9998 %} | |
9999 | |
10000 // ============================================================================ | |
10001 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
10002 // array for an instance of the superklass. Set a hidden internal cache on a | |
10003 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
10004 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
10005 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
10006 match(Set index (PartialSubtypeCheck sub super)); | |
10007 effect( KILL pcc, KILL o7 ); | |
10008 ins_cost(DEFAULT_COST*10); | |
10009 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
10010 ins_encode( enc_PartialSubtypeCheck() ); | |
10011 ins_pipe(partial_subtype_check_pipe); | |
10012 %} | |
10013 | |
10014 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
10015 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
10016 effect( KILL idx, KILL o7 ); | |
10017 ins_cost(DEFAULT_COST*10); | |
10018 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
10019 ins_encode( enc_PartialSubtypeCheck() ); | |
10020 ins_pipe(partial_subtype_check_pipe); | |
10021 %} | |
10022 | |
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10023 |
0 | 10024 // ============================================================================ |
10025 // inlined locking and unlocking | |
10026 | |
4777 | 10027 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ |
0 | 10028 match(Set pcc (FastLock object box)); |
10029 | |
4777 | 10030 effect(TEMP scratch2, USE_KILL box, KILL scratch); |
0 | 10031 ins_cost(100); |
10032 | |
4777 | 10033 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} |
0 | 10034 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); |
10035 ins_pipe(long_memory_op); | |
10036 %} | |
10037 | |
10038 | |
4777 | 10039 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ |
0 | 10040 match(Set pcc (FastUnlock object box)); |
4777 | 10041 effect(TEMP scratch2, USE_KILL box, KILL scratch); |
0 | 10042 ins_cost(100); |
10043 | |
4777 | 10044 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} |
0 | 10045 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); |
10046 ins_pipe(long_memory_op); | |
10047 %} | |
10048 | |
3892 | 10049 // The encodings are generic. |
0 | 10050 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ |
3892 | 10051 predicate(!use_block_zeroing(n->in(2)) ); |
0 | 10052 match(Set dummy (ClearArray cnt base)); |
10053 effect(TEMP temp, KILL ccr); | |
10054 ins_cost(300); | |
10055 format %{ "MOV $cnt,$temp\n" | |
10056 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
10057 " BRge loop\t\t! Clearing loop\n" | |
10058 " STX G0,[$base+$temp]\t! delay slot" %} | |
3892 | 10059 |
10060 ins_encode %{ | |
10061 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
10062 Register nof_bytes_arg = $cnt$$Register; | |
10063 Register nof_bytes_tmp = $temp$$Register; | |
10064 Register base_pointer_arg = $base$$Register; | |
10065 | |
10066 Label loop; | |
10067 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
10068 | |
10069 // Loop and clear, walking backwards through the array. | |
10070 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
10071 __ bind(loop); | |
10072 __ deccc(nof_bytes_tmp, 8); | |
10073 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
10074 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
10075 // %%%% this mini-loop must not cross a cache boundary! | |
10076 %} | |
10077 ins_pipe(long_memory_op); | |
10078 %} | |
10079 | |
10080 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{ | |
10081 predicate(use_block_zeroing(n->in(2))); | |
10082 match(Set dummy (ClearArray cnt base)); | |
10083 effect(USE_KILL cnt, USE_KILL base, KILL ccr); | |
10084 ins_cost(300); | |
10085 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} | |
10086 | |
10087 ins_encode %{ | |
10088 | |
10089 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); | |
10090 Register to = $base$$Register; | |
10091 Register count = $cnt$$Register; | |
10092 | |
10093 Label Ldone; | |
10094 __ nop(); // Separate short branches | |
10095 // Use BIS for zeroing (temp is not used). | |
10096 __ bis_zeroing(to, count, G0, Ldone); | |
10097 __ bind(Ldone); | |
10098 | |
10099 %} | |
10100 ins_pipe(long_memory_op); | |
10101 %} | |
10102 | |
10103 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{ | |
10104 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit)); | |
10105 match(Set dummy (ClearArray cnt base)); | |
10106 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr); | |
10107 ins_cost(300); | |
10108 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} | |
10109 | |
10110 ins_encode %{ | |
10111 | |
10112 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); | |
10113 Register to = $base$$Register; | |
10114 Register count = $cnt$$Register; | |
10115 Register temp = $tmp$$Register; | |
10116 | |
10117 Label Ldone; | |
10118 __ nop(); // Separate short branches | |
10119 // Use BIS for zeroing | |
10120 __ bis_zeroing(to, count, temp, Ldone); | |
10121 __ bind(Ldone); | |
10122 | |
10123 %} | |
0 | 10124 ins_pipe(long_memory_op); |
10125 %} | |
10126 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
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951
diff
changeset
|
10127 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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|
10128 o7RegI tmp, flagsReg ccr) %{ |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10129 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10130 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
0 | 10131 ins_cost(300); |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
951
diff
changeset
|
10132 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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951
diff
changeset
|
10133 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
0 | 10134 ins_pipe(long_memory_op); |
10135 %} | |
10136 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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951
diff
changeset
|
10137 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10138 o7RegI tmp, flagsReg ccr) %{ |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10139 match(Set result (StrEquals (Binary str1 str2) cnt)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
951
diff
changeset
|
10140 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
681 | 10141 ins_cost(300); |
986
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6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10142 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
951
diff
changeset
|
10143 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
681 | 10144 ins_pipe(long_memory_op); |
10145 %} | |
10146 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
951
diff
changeset
|
10147 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
951
diff
changeset
|
10148 o7RegI tmp2, flagsReg ccr) %{ |
681 | 10149 match(Set result (AryEq ary1 ary2)); |
10150 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
10151 ins_cost(300); | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10152 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
951
diff
changeset
|
10153 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
681 | 10154 ins_pipe(long_memory_op); |
10155 %} | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
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|
10156 |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10157 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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732
diff
changeset
|
10158 //---------- Zeros Count Instructions ------------------------------------------ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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732
diff
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|
10159 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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732
diff
changeset
|
10160 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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732
diff
changeset
|
10161 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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732
diff
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|
10162 match(Set dst (CountLeadingZerosI src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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732
diff
changeset
|
10163 effect(TEMP dst, TEMP tmp, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10164 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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732
diff
changeset
|
10165 // x |= (x >> 1); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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732
diff
changeset
|
10166 // x |= (x >> 2); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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732
diff
changeset
|
10167 // x |= (x >> 4); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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732
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changeset
|
10168 // x |= (x >> 8); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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732
diff
changeset
|
10169 // x |= (x >> 16); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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732
diff
changeset
|
10170 // return (WORDBITS - popc(x)); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10171 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10172 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10173 "OR $dst,$tmp,$dst\n\t" |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10174 "SRL $dst,2,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10175 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10176 "SRL $dst,4,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10177 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10178 "SRL $dst,8,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10179 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10180 "SRL $dst,16,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10181 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10182 "POPC $dst,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10183 "MOV 32,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10184 "SUB $tmp,$dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10185 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10186 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10187 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10188 Register Rtmp = $tmp$$Register; |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10189 __ srl(Rsrc, 1, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10190 __ srl(Rsrc, 0, Rdst); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10191 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10192 __ srl(Rdst, 2, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10193 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10194 __ srl(Rdst, 4, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10195 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10196 __ srl(Rdst, 8, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10197 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10198 __ srl(Rdst, 16, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10199 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10200 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10201 __ mov(BitsPerInt, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10202 __ sub(Rtmp, Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
10203 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10204 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10205 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10206 |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10207 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10208 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10209 match(Set dst (CountLeadingZerosL src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10210 effect(TEMP dst, TEMP tmp, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10211 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10212 // x |= (x >> 1); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10213 // x |= (x >> 2); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10214 // x |= (x >> 4); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10215 // x |= (x >> 8); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10216 // x |= (x >> 16); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10217 // x |= (x >> 32); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10218 // return (WORDBITS - popc(x)); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10219 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10220 "OR $src,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10221 "SRLX $dst,2,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10222 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10223 "SRLX $dst,4,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10224 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10225 "SRLX $dst,8,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10226 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10227 "SRLX $dst,16,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10228 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10229 "SRLX $dst,32,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10230 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10231 "POPC $dst,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10232 "MOV 64,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10233 "SUB $tmp,$dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10234 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10235 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10236 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10237 Register Rtmp = $tmp$$Register; |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10238 __ srlx(Rsrc, 1, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10239 __ or3( Rsrc, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10240 __ srlx(Rdst, 2, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10241 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10242 __ srlx(Rdst, 4, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10243 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10244 __ srlx(Rdst, 8, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10245 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10246 __ srlx(Rdst, 16, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10247 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10248 __ srlx(Rdst, 32, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10249 __ or3( Rdst, Rtmp, Rdst); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10250 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10251 __ mov(BitsPerLong, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10252 __ sub(Rtmp, Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10253 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10254 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10255 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10256 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10257 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10258 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10259 match(Set dst (CountTrailingZerosI src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10260 effect(TEMP dst, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10261 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10262 // return popc(~x & (x - 1)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10263 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10264 "ANDN $dst,$src,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10265 "SRL $dst,R_G0,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10266 "POPC $dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10267 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10268 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10269 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10270 __ sub(Rsrc, 1, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10271 __ andn(Rdst, Rsrc, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10272 __ srl(Rdst, G0, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10273 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10274 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10275 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10276 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10277 |
4003
4bac06a82bc3
7100757: The BitSet.nextSetBit() produces incorrect result in 32bit VM on Sparc
kvn
parents:
3898
diff
changeset
|
10278 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{ |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10279 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10280 match(Set dst (CountTrailingZerosL src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10281 effect(TEMP dst, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10282 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10283 // return popc(~x & (x - 1)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10284 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10285 "ANDN $dst,$src,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10286 "POPC $dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10287 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10288 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10289 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10290 __ sub(Rsrc, 1, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10291 __ andn(Rdst, Rsrc, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10292 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10293 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10294 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10295 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10296 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10297 |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10298 //---------- Population Count Instructions ------------------------------------- |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10299 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10300 instruct popCountI(iRegI dst, iRegI src) %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10301 predicate(UsePopCountInstruction); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10302 match(Set dst (PopCountI src)); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10303 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10304 format %{ "POPC $src, $dst" %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10305 ins_encode %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10306 __ popc($src$$Register, $dst$$Register); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10307 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10308 ins_pipe(ialu_reg); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10309 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10310 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10311 // Note: Long.bitCount(long) returns an int. |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10312 instruct popCountL(iRegI dst, iRegL src) %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10313 predicate(UsePopCountInstruction); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10314 match(Set dst (PopCountL src)); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10315 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10316 format %{ "POPC $src, $dst" %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10317 ins_encode %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10318 __ popc($src$$Register, $dst$$Register); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10319 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10320 ins_pipe(ialu_reg); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10321 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10322 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10323 |
0 | 10324 // ============================================================================ |
10325 //------------Bytes reverse-------------------------------------------------- | |
10326 | |
10327 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
10328 match(Set dst (ReverseBytesI src)); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10329 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10330 // Op cost is artificially doubled to make sure that load or store |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10331 // instructions are preferred over this one which requires a spill |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10332 // onto a stack slot. |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10333 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10334 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10335 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10336 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10337 __ set($src$$disp + STACK_BIAS, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10338 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10339 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10340 ins_pipe( iload_mem ); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10341 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10342 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10343 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10344 match(Set dst (ReverseBytesL src)); |
0 | 10345 |
10346 // Op cost is artificially doubled to make sure that load or store | |
10347 // instructions are preferred over this one which requires a spill | |
10348 // onto a stack slot. | |
10349 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10350 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10351 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10352 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10353 __ set($src$$disp + STACK_BIAS, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10354 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10355 %} |
0 | 10356 ins_pipe( iload_mem ); |
10357 %} | |
10358 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10359 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10360 match(Set dst (ReverseBytesUS src)); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10361 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10362 // Op cost is artificially doubled to make sure that load or store |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10363 // instructions are preferred over this one which requires a spill |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10364 // onto a stack slot. |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10365 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10366 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10367 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10368 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10369 // the value was spilled as an int so bias the load |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10370 __ set($src$$disp + STACK_BIAS + 2, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10371 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10372 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10373 ins_pipe( iload_mem ); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10374 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10375 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10376 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10377 match(Set dst (ReverseBytesS src)); |
0 | 10378 |
10379 // Op cost is artificially doubled to make sure that load or store | |
10380 // instructions are preferred over this one which requires a spill | |
10381 // onto a stack slot. | |
10382 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10383 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10384 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10385 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10386 // the value was spilled as an int so bias the load |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10387 __ set($src$$disp + STACK_BIAS + 2, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10388 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10389 %} |
0 | 10390 ins_pipe( iload_mem ); |
10391 %} | |
10392 | |
10393 // Load Integer reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10394 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ |
0 | 10395 match(Set dst (ReverseBytesI (LoadI src))); |
10396 | |
10397 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10398 size(4); |
0 | 10399 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
10400 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10401 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10402 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10403 %} |
0 | 10404 ins_pipe(iload_mem); |
10405 %} | |
10406 | |
10407 // Load Long - aligned and reversed | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10408 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ |
0 | 10409 match(Set dst (ReverseBytesL (LoadL src))); |
10410 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10411 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10412 size(4); |
0 | 10413 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
10414 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10415 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10416 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10417 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10418 ins_pipe(iload_mem); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10419 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10420 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10421 // Load unsigned short / char reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10422 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10423 match(Set dst (ReverseBytesUS (LoadUS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10424 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10425 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10426 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10427 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10428 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10429 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10430 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10431 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10432 ins_pipe(iload_mem); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10433 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10434 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10435 // Load short reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10436 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10437 match(Set dst (ReverseBytesS (LoadS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10438 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10439 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10440 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10441 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10442 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10443 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10444 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10445 %} |
0 | 10446 ins_pipe(iload_mem); |
10447 %} | |
10448 | |
10449 // Store Integer reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10450 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ |
0 | 10451 match(Set dst (StoreI dst (ReverseBytesI src))); |
10452 | |
10453 ins_cost(MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10454 size(4); |
0 | 10455 format %{ "STWA $src, $dst\t!asi=primary_little" %} |
10456 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10457 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10458 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10459 %} |
0 | 10460 ins_pipe(istore_mem_reg); |
10461 %} | |
10462 | |
10463 // Store Long reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10464 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ |
0 | 10465 match(Set dst (StoreL dst (ReverseBytesL src))); |
10466 | |
10467 ins_cost(MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10468 size(4); |
0 | 10469 format %{ "STXA $src, $dst\t!asi=primary_little" %} |
10470 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10471 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10472 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10473 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10474 ins_pipe(istore_mem_reg); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10475 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10476 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10477 // Store unsighed short/char reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10478 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10479 match(Set dst (StoreC dst (ReverseBytesUS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10480 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10481 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10482 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10483 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10484 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10485 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10486 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10487 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10488 ins_pipe(istore_mem_reg); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10489 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10490 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10491 // Store short reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10492 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10493 match(Set dst (StoreC dst (ReverseBytesS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10494 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10495 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10496 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10497 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10498 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10499 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10500 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10501 %} |
0 | 10502 ins_pipe(istore_mem_reg); |
10503 %} | |
10504 | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10505 // ====================VECTOR INSTRUCTIONS===================================== |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10506 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10507 // Load Aligned Packed values into a Double Register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10508 instruct loadV8(regD dst, memory mem) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10509 predicate(n->as_LoadVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10510 match(Set dst (LoadVector mem)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10511 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10512 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10513 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10514 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10515 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10516 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10517 ins_pipe(floadD_mem); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10518 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10519 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10520 // Store Vector in Double register to memory |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10521 instruct storeV8(memory mem, regD src) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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parents:
6143
diff
changeset
|
10522 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10523 match(Set mem (StoreVector mem src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10524 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10525 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10526 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10527 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10528 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10529 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10530 ins_pipe(fstoreD_mem_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10531 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10532 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10533 // Store Zero into vector in memory |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10534 instruct storeV8B_zero(memory mem, immI0 zero) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10535 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10536 match(Set mem (StoreVector mem (ReplicateB zero))); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10537 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10538 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10539 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10540 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10541 __ stx(G0, $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10542 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10543 ins_pipe(fstoreD_mem_zero); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10544 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10545 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10546 instruct storeV4S_zero(memory mem, immI0 zero) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10547 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10548 match(Set mem (StoreVector mem (ReplicateS zero))); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10549 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10550 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10551 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10552 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10553 __ stx(G0, $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10554 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10555 ins_pipe(fstoreD_mem_zero); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10556 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10557 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10558 instruct storeV2I_zero(memory mem, immI0 zero) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10559 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10560 match(Set mem (StoreVector mem (ReplicateI zero))); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10561 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10562 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10563 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10564 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10565 __ stx(G0, $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10566 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10567 ins_pipe(fstoreD_mem_zero); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10568 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10569 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10570 instruct storeV2F_zero(memory mem, immF0 zero) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10571 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10572 match(Set mem (StoreVector mem (ReplicateF zero))); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10573 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10574 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10575 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10576 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10577 __ stx(G0, $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10578 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10579 ins_pipe(fstoreD_mem_zero); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10580 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10581 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10582 // Replicate scalar to packed byte values into Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10583 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10584 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10585 match(Set dst (ReplicateB src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10586 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10587 format %{ "SLLX $src,56,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10588 "SRLX $tmp, 8,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10589 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10590 "SRLX $tmp,16,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10591 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10592 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10593 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10594 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10595 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10596 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10597 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10598 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10599 __ sllx(Rsrc, 56, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10600 __ srlx(Rtmp, 8, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10601 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10602 __ srlx(Rtmp, 16, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10603 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10604 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10605 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10606 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10607 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10608 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10609 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10610 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10611 // Replicate scalar to packed byte values into Double stack |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10612 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10613 predicate(n->as_Vector()->length() == 8 && UseVIS < 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10614 match(Set dst (ReplicateB src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10615 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10616 format %{ "SLLX $src,56,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10617 "SRLX $tmp, 8,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10618 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10619 "SRLX $tmp,16,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10620 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10621 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10622 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10623 "STX $tmp,$dst\t! regL to stkD" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10624 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10625 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10626 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10627 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10628 __ sllx(Rsrc, 56, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10629 __ srlx(Rtmp, 8, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10630 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10631 __ srlx(Rtmp, 16, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10632 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10633 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10634 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10635 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10636 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10637 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10638 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10639 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10640 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10641 // Replicate scalar constant to packed byte values in Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10642 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10643 predicate(n->as_Vector()->length() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10644 match(Set dst (ReplicateB con)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10645 effect(KILL tmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10646 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10647 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10648 // XXX This is a quick fix for 6833573. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10649 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10650 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10651 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10652 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10653 ins_pipe(loadConFD); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10654 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10655 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10656 // Replicate scalar to packed char/short values into Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10657 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10658 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10659 match(Set dst (ReplicateS src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10660 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10661 format %{ "SLLX $src,48,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10662 "SRLX $tmp,16,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10663 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10664 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10665 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10666 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10667 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10668 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10669 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10670 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10671 __ sllx(Rsrc, 48, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10672 __ srlx(Rtmp, 16, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10673 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10674 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10675 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10676 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10677 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10678 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10679 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10680 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10681 // Replicate scalar to packed char/short values into Double stack |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10682 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10683 predicate(n->as_Vector()->length() == 4 && UseVIS < 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10684 match(Set dst (ReplicateS src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10685 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10686 format %{ "SLLX $src,48,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10687 "SRLX $tmp,16,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10688 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10689 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10690 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10691 "STX $tmp,$dst\t! regL to stkD" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10692 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10693 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10694 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10695 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10696 __ sllx(Rsrc, 48, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10697 __ srlx(Rtmp, 16, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10698 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10699 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10700 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10701 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10702 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10703 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10704 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10705 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10706 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10707 // Replicate scalar constant to packed char/short values in Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10708 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10709 predicate(n->as_Vector()->length() == 4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10710 match(Set dst (ReplicateS con)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10711 effect(KILL tmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10712 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10713 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10714 // XXX This is a quick fix for 6833573. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10715 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10716 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10717 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10718 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10719 ins_pipe(loadConFD); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10720 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10721 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10722 // Replicate scalar to packed int values into Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10723 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10724 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10725 match(Set dst (ReplicateI src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10726 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10727 format %{ "SLLX $src,32,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10728 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10729 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10730 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10731 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10732 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10733 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10734 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10735 __ sllx(Rsrc, 32, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10736 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10737 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10738 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10739 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10740 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10741 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10742 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10743 // Replicate scalar to packed int values into Double stack |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10744 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10745 predicate(n->as_Vector()->length() == 2 && UseVIS < 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10746 match(Set dst (ReplicateI src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10747 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10748 format %{ "SLLX $src,32,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10749 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10750 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10751 "STX $tmp,$dst\t! regL to stkD" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10752 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10753 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10754 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10755 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10756 __ sllx(Rsrc, 32, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10757 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10758 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10759 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10760 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10761 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10762 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10763 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10764 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10765 // Replicate scalar zero constant to packed int values in Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10766 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10767 predicate(n->as_Vector()->length() == 2); |
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10768 match(Set dst (ReplicateI con)); |
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10769 effect(KILL tmp); |
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10770 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} |
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10771 ins_encode %{ |
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10772 // XXX This is a quick fix for 6833573. |
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10773 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); |
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10774 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); |
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10775 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
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10776 %} |
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10777 ins_pipe(loadConFD); |
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10778 %} |
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10779 |
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10780 // Replicate scalar to packed float values into Double stack |
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10781 instruct Repl2F_stk(stackSlotD dst, regF src) %{ |
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10782 predicate(n->as_Vector()->length() == 2); |
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10783 match(Set dst (ReplicateF src)); |
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10784 ins_cost(MEMORY_REF_COST*2); |
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10785 format %{ "STF $src,$dst.hi\t! packed2F\n\t" |
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10786 "STF $src,$dst.lo" %} |
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10787 opcode(Assembler::stf_op3); |
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10788 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src)); |
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10789 ins_pipe(fstoreF_stk_reg); |
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10790 %} |
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10791 |
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10792 // Replicate scalar zero constant to packed float values in Double register |
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10793 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{ |
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10794 predicate(n->as_Vector()->length() == 2); |
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10795 match(Set dst (ReplicateF con)); |
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10796 effect(KILL tmp); |
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10797 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %} |
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10798 ins_encode %{ |
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10799 // XXX This is a quick fix for 6833573. |
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10800 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister); |
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10801 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register); |
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10802 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
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10803 %} |
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10804 ins_pipe(loadConFD); |
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10805 %} |
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10806 |
0 | 10807 //----------PEEPHOLE RULES----------------------------------------------------- |
10808 // These must follow all instruction definitions as they use the names | |
10809 // defined in the instructions definitions. | |
10810 // | |
605 | 10811 // peepmatch ( root_instr_name [preceding_instruction]* ); |
0 | 10812 // |
10813 // peepconstraint %{ | |
10814 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
10815 // [, ...] ); | |
10816 // // instruction numbers are zero-based using left to right order in peepmatch | |
10817 // | |
10818 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
10819 // // provide an instruction_number.operand_name for each operand that appears | |
10820 // // in the replacement instruction's match rule | |
10821 // | |
10822 // ---------VM FLAGS--------------------------------------------------------- | |
10823 // | |
10824 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
10825 // | |
10826 // Each peephole rule is given an identifying number starting with zero and | |
10827 // increasing by one in the order seen by the parser. An individual peephole | |
10828 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
10829 // on the command-line. | |
10830 // | |
10831 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
10832 // | |
10833 // Only match adjacent instructions in same basic block | |
10834 // Only equality constraints | |
10835 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
10836 // Only one replacement instruction | |
10837 // | |
10838 // ---------EXAMPLE---------------------------------------------------------- | |
10839 // | |
10840 // // pertinent parts of existing instructions in architecture description | |
10841 // instruct movI(eRegI dst, eRegI src) %{ | |
10842 // match(Set dst (CopyI src)); | |
10843 // %} | |
10844 // | |
10845 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
10846 // match(Set dst (AddI dst src)); | |
10847 // effect(KILL cr); | |
10848 // %} | |
10849 // | |
10850 // // Change (inc mov) to lea | |
10851 // peephole %{ | |
10852 // // increment preceeded by register-register move | |
10853 // peepmatch ( incI_eReg movI ); | |
10854 // // require that the destination register of the increment | |
10855 // // match the destination register of the move | |
10856 // peepconstraint ( 0.dst == 1.dst ); | |
10857 // // construct a replacement instruction that sets | |
10858 // // the destination to ( move's source register + one ) | |
10859 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
10860 // %} | |
10861 // | |
10862 | |
10863 // // Change load of spilled value to only a spill | |
10864 // instruct storeI(memory mem, eRegI src) %{ | |
10865 // match(Set mem (StoreI mem src)); | |
10866 // %} | |
10867 // | |
10868 // instruct loadI(eRegI dst, memory mem) %{ | |
10869 // match(Set dst (LoadI mem)); | |
10870 // %} | |
10871 // | |
10872 // peephole %{ | |
10873 // peepmatch ( loadI storeI ); | |
10874 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
10875 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
10876 // %} | |
10877 | |
10878 //----------SMARTSPILL RULES--------------------------------------------------- | |
10879 // These must follow all instruction definitions as they use the names | |
10880 // defined in the instructions definitions. | |
10881 // | |
10882 // SPARC will probably not have any of these rules due to RISC instruction set. | |
10883 | |
10884 //----------PIPELINE----------------------------------------------------------- | |
10885 // Rules which define the behavior of the target architectures pipeline. |