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annotate src/cpu/x86/vm/x86_64.ad @ 3096:8073f5ad1d87

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IdealGraphVisualizer: Rename predecessors to "Nodes Above" and successors to "Nodes Below" and actions "Expand Predecessors" and "Expand Successors" to "Expand Above" and "Expand Below" to avoid ambiguity with the Graal concept of successors and predecessors
author Peter Hofer <peter.hofer@jku.at>
date Wed, 29 Jun 2011 18:27:14 +0200
parents b40d4fa697bf
children 9340a27154cb
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1 //
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41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
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2 // Copyright (c) 2003, 2011, Oracle and/or its affiliates. All rights reserved.
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3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 //
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5 // This code is free software; you can redistribute it and/or modify it
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6 // under the terms of the GNU General Public License version 2 only, as
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7 // published by the Free Software Foundation.
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8 //
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9 // This code is distributed in the hope that it will be useful, but WITHOUT
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10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 // version 2 for more details (a copy is included in the LICENSE file that
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13 // accompanied this code).
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14 //
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15 // You should have received a copy of the GNU General Public License version
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16 // 2 along with this work; if not, write to the Free Software Foundation,
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17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 //
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c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 // or visit www.oracle.com if you need additional information or have any
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21 // questions.
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22 //
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23 //
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24
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25 // AMD64 Architecture Description File
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26
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27 //----------REGISTER DEFINITION BLOCK------------------------------------------
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28 // This information is used by the matcher and the register allocator to
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29 // describe individual registers and classes of registers within the target
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30 // archtecture.
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31
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32 register %{
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33 //----------Architecture Description Register Definitions----------------------
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34 // General Registers
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35 // "reg_def" name ( register save type, C convention save type,
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36 // ideal register type, encoding );
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37 // Register Save Types:
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38 //
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39 // NS = No-Save: The register allocator assumes that these registers
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40 // can be used without saving upon entry to the method, &
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41 // that they do not need to be saved at call sites.
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42 //
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43 // SOC = Save-On-Call: The register allocator assumes that these registers
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44 // can be used without saving upon entry to the method,
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45 // but that they must be saved at call sites.
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46 //
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47 // SOE = Save-On-Entry: The register allocator assumes that these registers
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48 // must be saved before using them upon entry to the
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49 // method, but they do not need to be saved at call
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50 // sites.
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51 //
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52 // AS = Always-Save: The register allocator assumes that these registers
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53 // must be saved before using them upon entry to the
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54 // method, & that they must be saved at call sites.
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55 //
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56 // Ideal Register Type is used to determine how to save & restore a
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57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
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58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
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59 //
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60 // The encoding number is the actual bit-pattern placed into the opcodes.
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61
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62 // General Registers
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63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
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64 // used as byte registers)
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65
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66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
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67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
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68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
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69
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70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
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71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
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72
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73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
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74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
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75
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76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
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77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
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78
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79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
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80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
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81
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82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
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83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
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84
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85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
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86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
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87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
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88
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89 #ifdef _WIN64
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90
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91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
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92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
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93
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94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
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95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
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96
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97 #else
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98
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99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
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100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
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101
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102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
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103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
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104
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105 #endif
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106
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107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
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108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
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109
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110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
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111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
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112
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113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
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114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
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115
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116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
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117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
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118
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119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
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120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
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121
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122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
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123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
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124
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125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
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126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
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127
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128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
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129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
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130
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131
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132 // Floating Point Registers
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133
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134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d.
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135 // Word a in each register holds a Float, words ab hold a Double. We
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136 // currently do not use the SIMD capabilities, so registers cd are
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137 // unused at the moment.
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138 // XMM8-XMM15 must be encoded with REX.
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139 // Linux ABI: No register preserved across function calls
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140 // XMM0-XMM7 might hold parameters
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141 // Windows ABI: XMM6-XMM15 preserved across function calls
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142 // XMM0-XMM3 might hold parameters
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143
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144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
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145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
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146
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147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
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148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
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149
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150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
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151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
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152
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153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
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154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
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155
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156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
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157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
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158
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159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
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160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
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161
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162 #ifdef _WIN64
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163
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164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg());
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165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next());
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166
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167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg());
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168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next());
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169
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170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg());
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171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next());
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172
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173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg());
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174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next());
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175
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176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg());
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177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next());
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178
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179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg());
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180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next());
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181
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182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg());
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183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next());
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184
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185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg());
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186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next());
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187
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188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg());
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189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next());
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190
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191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg());
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192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next());
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193
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194 #else
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195
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196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
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197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
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198
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199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
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200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
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201
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202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg());
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203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next());
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204
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205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg());
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206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next());
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207
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208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg());
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209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next());
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210
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211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg());
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212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next());
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213
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214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg());
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215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next());
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216
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217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg());
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218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next());
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219
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220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg());
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221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next());
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222
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223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg());
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224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next());
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225
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226 #endif // _WIN64
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227
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228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad());
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229
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230 // Specify priority of register selection within phases of register
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231 // allocation. Highest priority is first. A useful heuristic is to
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232 // give registers a low priority when they are required by machine
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233 // instructions, like EAX and EDX on I486, and choose no-save registers
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234 // before save-on-call, & save-on-call before save-on-entry. Registers
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235 // which participate in fixed calling sequences should come last.
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236 // Registers which are used as pairs must fall on an even boundary.
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237
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238 alloc_class chunk0(R10, R10_H,
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239 R11, R11_H,
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240 R8, R8_H,
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241 R9, R9_H,
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242 R12, R12_H,
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243 RCX, RCX_H,
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244 RBX, RBX_H,
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245 RDI, RDI_H,
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246 RDX, RDX_H,
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247 RSI, RSI_H,
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248 RAX, RAX_H,
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249 RBP, RBP_H,
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250 R13, R13_H,
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251 R14, R14_H,
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252 R15, R15_H,
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253 RSP, RSP_H);
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254
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255 // XXX probably use 8-15 first on Linux
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256 alloc_class chunk1(XMM0, XMM0_H,
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257 XMM1, XMM1_H,
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258 XMM2, XMM2_H,
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259 XMM3, XMM3_H,
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260 XMM4, XMM4_H,
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261 XMM5, XMM5_H,
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262 XMM6, XMM6_H,
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263 XMM7, XMM7_H,
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264 XMM8, XMM8_H,
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265 XMM9, XMM9_H,
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266 XMM10, XMM10_H,
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267 XMM11, XMM11_H,
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268 XMM12, XMM12_H,
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269 XMM13, XMM13_H,
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270 XMM14, XMM14_H,
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271 XMM15, XMM15_H);
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272
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273 alloc_class chunk2(RFLAGS);
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274
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275
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276 //----------Architecture Description Register Classes--------------------------
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277 // Several register classes are automatically defined based upon information in
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278 // this architecture description.
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279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
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280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
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281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
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282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
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283 //
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284
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285 // Class for all pointer registers (including RSP)
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286 reg_class any_reg(RAX, RAX_H,
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287 RDX, RDX_H,
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288 RBP, RBP_H,
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289 RDI, RDI_H,
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290 RSI, RSI_H,
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291 RCX, RCX_H,
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292 RBX, RBX_H,
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293 RSP, RSP_H,
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294 R8, R8_H,
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parents:
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295 R9, R9_H,
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parents:
diff changeset
296 R10, R10_H,
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parents:
diff changeset
297 R11, R11_H,
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parents:
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298 R12, R12_H,
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parents:
diff changeset
299 R13, R13_H,
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parents:
diff changeset
300 R14, R14_H,
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parents:
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301 R15, R15_H);
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302
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parents:
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303 // Class for all pointer registers except RSP
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304 reg_class ptr_reg(RAX, RAX_H,
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305 RDX, RDX_H,
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parents:
diff changeset
306 RBP, RBP_H,
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parents:
diff changeset
307 RDI, RDI_H,
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parents:
diff changeset
308 RSI, RSI_H,
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parents:
diff changeset
309 RCX, RCX_H,
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parents:
diff changeset
310 RBX, RBX_H,
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parents:
diff changeset
311 R8, R8_H,
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parents:
diff changeset
312 R9, R9_H,
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parents:
diff changeset
313 R10, R10_H,
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parents:
diff changeset
314 R11, R11_H,
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parents:
diff changeset
315 R13, R13_H,
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diff changeset
316 R14, R14_H);
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diff changeset
317
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parents:
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318 // Class for all pointer registers except RAX and RSP
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parents:
diff changeset
319 reg_class ptr_no_rax_reg(RDX, RDX_H,
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parents:
diff changeset
320 RBP, RBP_H,
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parents:
diff changeset
321 RDI, RDI_H,
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parents:
diff changeset
322 RSI, RSI_H,
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parents:
diff changeset
323 RCX, RCX_H,
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parents:
diff changeset
324 RBX, RBX_H,
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parents:
diff changeset
325 R8, R8_H,
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parents:
diff changeset
326 R9, R9_H,
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parents:
diff changeset
327 R10, R10_H,
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parents:
diff changeset
328 R11, R11_H,
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parents:
diff changeset
329 R13, R13_H,
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diff changeset
330 R14, R14_H);
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parents:
diff changeset
331
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diff changeset
332 reg_class ptr_no_rbp_reg(RDX, RDX_H,
a61af66fc99e Initial load
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parents:
diff changeset
333 RAX, RAX_H,
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parents:
diff changeset
334 RDI, RDI_H,
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parents:
diff changeset
335 RSI, RSI_H,
a61af66fc99e Initial load
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parents:
diff changeset
336 RCX, RCX_H,
a61af66fc99e Initial load
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parents:
diff changeset
337 RBX, RBX_H,
a61af66fc99e Initial load
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parents:
diff changeset
338 R8, R8_H,
a61af66fc99e Initial load
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parents:
diff changeset
339 R9, R9_H,
a61af66fc99e Initial load
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parents:
diff changeset
340 R10, R10_H,
a61af66fc99e Initial load
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parents:
diff changeset
341 R11, R11_H,
a61af66fc99e Initial load
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parents:
diff changeset
342 R13, R13_H,
a61af66fc99e Initial load
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parents:
diff changeset
343 R14, R14_H);
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parents:
diff changeset
344
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parents:
diff changeset
345 // Class for all pointer registers except RAX, RBX and RSP
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parents:
diff changeset
346 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
a61af66fc99e Initial load
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parents:
diff changeset
347 RBP, RBP_H,
a61af66fc99e Initial load
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parents:
diff changeset
348 RDI, RDI_H,
a61af66fc99e Initial load
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parents:
diff changeset
349 RSI, RSI_H,
a61af66fc99e Initial load
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parents:
diff changeset
350 RCX, RCX_H,
a61af66fc99e Initial load
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parents:
diff changeset
351 R8, R8_H,
a61af66fc99e Initial load
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parents:
diff changeset
352 R9, R9_H,
a61af66fc99e Initial load
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parents:
diff changeset
353 R10, R10_H,
a61af66fc99e Initial load
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parents:
diff changeset
354 R11, R11_H,
a61af66fc99e Initial load
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parents:
diff changeset
355 R13, R13_H,
a61af66fc99e Initial load
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parents:
diff changeset
356 R14, R14_H);
a61af66fc99e Initial load
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parents:
diff changeset
357
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parents:
diff changeset
358 // Singleton class for RAX pointer register
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parents:
diff changeset
359 reg_class ptr_rax_reg(RAX, RAX_H);
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360
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parents:
diff changeset
361 // Singleton class for RBX pointer register
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parents:
diff changeset
362 reg_class ptr_rbx_reg(RBX, RBX_H);
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parents:
diff changeset
363
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parents:
diff changeset
364 // Singleton class for RSI pointer register
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parents:
diff changeset
365 reg_class ptr_rsi_reg(RSI, RSI_H);
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parents:
diff changeset
366
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parents:
diff changeset
367 // Singleton class for RDI pointer register
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parents:
diff changeset
368 reg_class ptr_rdi_reg(RDI, RDI_H);
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parents:
diff changeset
369
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parents:
diff changeset
370 // Singleton class for RBP pointer register
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parents:
diff changeset
371 reg_class ptr_rbp_reg(RBP, RBP_H);
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parents:
diff changeset
372
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parents:
diff changeset
373 // Singleton class for stack pointer
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parents:
diff changeset
374 reg_class ptr_rsp_reg(RSP, RSP_H);
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diff changeset
375
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parents:
diff changeset
376 // Singleton class for TLS pointer
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parents:
diff changeset
377 reg_class ptr_r15_reg(R15, R15_H);
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diff changeset
378
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parents:
diff changeset
379 // Class for all long registers (except RSP)
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parents:
diff changeset
380 reg_class long_reg(RAX, RAX_H,
a61af66fc99e Initial load
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parents:
diff changeset
381 RDX, RDX_H,
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parents:
diff changeset
382 RBP, RBP_H,
a61af66fc99e Initial load
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parents:
diff changeset
383 RDI, RDI_H,
a61af66fc99e Initial load
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parents:
diff changeset
384 RSI, RSI_H,
a61af66fc99e Initial load
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parents:
diff changeset
385 RCX, RCX_H,
a61af66fc99e Initial load
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parents:
diff changeset
386 RBX, RBX_H,
a61af66fc99e Initial load
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parents:
diff changeset
387 R8, R8_H,
a61af66fc99e Initial load
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parents:
diff changeset
388 R9, R9_H,
a61af66fc99e Initial load
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parents:
diff changeset
389 R10, R10_H,
a61af66fc99e Initial load
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parents:
diff changeset
390 R11, R11_H,
a61af66fc99e Initial load
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parents:
diff changeset
391 R13, R13_H,
a61af66fc99e Initial load
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parents:
diff changeset
392 R14, R14_H);
a61af66fc99e Initial load
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parents:
diff changeset
393
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parents:
diff changeset
394 // Class for all long registers except RAX, RDX (and RSP)
a61af66fc99e Initial load
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parents:
diff changeset
395 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
a61af66fc99e Initial load
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parents:
diff changeset
396 RDI, RDI_H,
a61af66fc99e Initial load
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parents:
diff changeset
397 RSI, RSI_H,
a61af66fc99e Initial load
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parents:
diff changeset
398 RCX, RCX_H,
a61af66fc99e Initial load
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parents:
diff changeset
399 RBX, RBX_H,
a61af66fc99e Initial load
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parents:
diff changeset
400 R8, R8_H,
a61af66fc99e Initial load
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parents:
diff changeset
401 R9, R9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
402 R10, R10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
403 R11, R11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
404 R13, R13_H,
a61af66fc99e Initial load
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parents:
diff changeset
405 R14, R14_H);
a61af66fc99e Initial load
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parents:
diff changeset
406
a61af66fc99e Initial load
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parents:
diff changeset
407 // Class for all long registers except RCX (and RSP)
a61af66fc99e Initial load
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parents:
diff changeset
408 reg_class long_no_rcx_reg(RBP, RBP_H,
a61af66fc99e Initial load
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parents:
diff changeset
409 RDI, RDI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
410 RSI, RSI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
411 RAX, RAX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
412 RDX, RDX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
413 RBX, RBX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
414 R8, R8_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
415 R9, R9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
416 R10, R10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
417 R11, R11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
418 R13, R13_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
419 R14, R14_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
420
a61af66fc99e Initial load
duke
parents:
diff changeset
421 // Class for all long registers except RAX (and RSP)
a61af66fc99e Initial load
duke
parents:
diff changeset
422 reg_class long_no_rax_reg(RBP, RBP_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
423 RDX, RDX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
424 RDI, RDI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
425 RSI, RSI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
426 RCX, RCX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
427 RBX, RBX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
428 R8, R8_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
429 R9, R9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
430 R10, R10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
431 R11, R11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
432 R13, R13_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
433 R14, R14_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
434
a61af66fc99e Initial load
duke
parents:
diff changeset
435 // Singleton class for RAX long register
a61af66fc99e Initial load
duke
parents:
diff changeset
436 reg_class long_rax_reg(RAX, RAX_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
437
a61af66fc99e Initial load
duke
parents:
diff changeset
438 // Singleton class for RCX long register
a61af66fc99e Initial load
duke
parents:
diff changeset
439 reg_class long_rcx_reg(RCX, RCX_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
440
a61af66fc99e Initial load
duke
parents:
diff changeset
441 // Singleton class for RDX long register
a61af66fc99e Initial load
duke
parents:
diff changeset
442 reg_class long_rdx_reg(RDX, RDX_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
443
a61af66fc99e Initial load
duke
parents:
diff changeset
444 // Class for all int registers (except RSP)
a61af66fc99e Initial load
duke
parents:
diff changeset
445 reg_class int_reg(RAX,
a61af66fc99e Initial load
duke
parents:
diff changeset
446 RDX,
a61af66fc99e Initial load
duke
parents:
diff changeset
447 RBP,
a61af66fc99e Initial load
duke
parents:
diff changeset
448 RDI,
a61af66fc99e Initial load
duke
parents:
diff changeset
449 RSI,
a61af66fc99e Initial load
duke
parents:
diff changeset
450 RCX,
a61af66fc99e Initial load
duke
parents:
diff changeset
451 RBX,
a61af66fc99e Initial load
duke
parents:
diff changeset
452 R8,
a61af66fc99e Initial load
duke
parents:
diff changeset
453 R9,
a61af66fc99e Initial load
duke
parents:
diff changeset
454 R10,
a61af66fc99e Initial load
duke
parents:
diff changeset
455 R11,
a61af66fc99e Initial load
duke
parents:
diff changeset
456 R13,
a61af66fc99e Initial load
duke
parents:
diff changeset
457 R14);
a61af66fc99e Initial load
duke
parents:
diff changeset
458
a61af66fc99e Initial load
duke
parents:
diff changeset
459 // Class for all int registers except RCX (and RSP)
a61af66fc99e Initial load
duke
parents:
diff changeset
460 reg_class int_no_rcx_reg(RAX,
a61af66fc99e Initial load
duke
parents:
diff changeset
461 RDX,
a61af66fc99e Initial load
duke
parents:
diff changeset
462 RBP,
a61af66fc99e Initial load
duke
parents:
diff changeset
463 RDI,
a61af66fc99e Initial load
duke
parents:
diff changeset
464 RSI,
a61af66fc99e Initial load
duke
parents:
diff changeset
465 RBX,
a61af66fc99e Initial load
duke
parents:
diff changeset
466 R8,
a61af66fc99e Initial load
duke
parents:
diff changeset
467 R9,
a61af66fc99e Initial load
duke
parents:
diff changeset
468 R10,
a61af66fc99e Initial load
duke
parents:
diff changeset
469 R11,
a61af66fc99e Initial load
duke
parents:
diff changeset
470 R13,
a61af66fc99e Initial load
duke
parents:
diff changeset
471 R14);
a61af66fc99e Initial load
duke
parents:
diff changeset
472
a61af66fc99e Initial load
duke
parents:
diff changeset
473 // Class for all int registers except RAX, RDX (and RSP)
a61af66fc99e Initial load
duke
parents:
diff changeset
474 reg_class int_no_rax_rdx_reg(RBP,
304
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parents: 235
diff changeset
475 RDI,
0
a61af66fc99e Initial load
duke
parents:
diff changeset
476 RSI,
a61af66fc99e Initial load
duke
parents:
diff changeset
477 RCX,
a61af66fc99e Initial load
duke
parents:
diff changeset
478 RBX,
a61af66fc99e Initial load
duke
parents:
diff changeset
479 R8,
a61af66fc99e Initial load
duke
parents:
diff changeset
480 R9,
a61af66fc99e Initial load
duke
parents:
diff changeset
481 R10,
a61af66fc99e Initial load
duke
parents:
diff changeset
482 R11,
a61af66fc99e Initial load
duke
parents:
diff changeset
483 R13,
a61af66fc99e Initial load
duke
parents:
diff changeset
484 R14);
a61af66fc99e Initial load
duke
parents:
diff changeset
485
a61af66fc99e Initial load
duke
parents:
diff changeset
486 // Singleton class for RAX int register
a61af66fc99e Initial load
duke
parents:
diff changeset
487 reg_class int_rax_reg(RAX);
a61af66fc99e Initial load
duke
parents:
diff changeset
488
a61af66fc99e Initial load
duke
parents:
diff changeset
489 // Singleton class for RBX int register
a61af66fc99e Initial load
duke
parents:
diff changeset
490 reg_class int_rbx_reg(RBX);
a61af66fc99e Initial load
duke
parents:
diff changeset
491
a61af66fc99e Initial load
duke
parents:
diff changeset
492 // Singleton class for RCX int register
a61af66fc99e Initial load
duke
parents:
diff changeset
493 reg_class int_rcx_reg(RCX);
a61af66fc99e Initial load
duke
parents:
diff changeset
494
a61af66fc99e Initial load
duke
parents:
diff changeset
495 // Singleton class for RCX int register
a61af66fc99e Initial load
duke
parents:
diff changeset
496 reg_class int_rdx_reg(RDX);
a61af66fc99e Initial load
duke
parents:
diff changeset
497
a61af66fc99e Initial load
duke
parents:
diff changeset
498 // Singleton class for RCX int register
a61af66fc99e Initial load
duke
parents:
diff changeset
499 reg_class int_rdi_reg(RDI);
a61af66fc99e Initial load
duke
parents:
diff changeset
500
a61af66fc99e Initial load
duke
parents:
diff changeset
501 // Singleton class for instruction pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
502 // reg_class ip_reg(RIP);
a61af66fc99e Initial load
duke
parents:
diff changeset
503
a61af66fc99e Initial load
duke
parents:
diff changeset
504 // Singleton class for condition codes
a61af66fc99e Initial load
duke
parents:
diff changeset
505 reg_class int_flags(RFLAGS);
a61af66fc99e Initial load
duke
parents:
diff changeset
506
a61af66fc99e Initial load
duke
parents:
diff changeset
507 // Class for all float registers
a61af66fc99e Initial load
duke
parents:
diff changeset
508 reg_class float_reg(XMM0,
a61af66fc99e Initial load
duke
parents:
diff changeset
509 XMM1,
a61af66fc99e Initial load
duke
parents:
diff changeset
510 XMM2,
a61af66fc99e Initial load
duke
parents:
diff changeset
511 XMM3,
a61af66fc99e Initial load
duke
parents:
diff changeset
512 XMM4,
a61af66fc99e Initial load
duke
parents:
diff changeset
513 XMM5,
a61af66fc99e Initial load
duke
parents:
diff changeset
514 XMM6,
a61af66fc99e Initial load
duke
parents:
diff changeset
515 XMM7,
a61af66fc99e Initial load
duke
parents:
diff changeset
516 XMM8,
a61af66fc99e Initial load
duke
parents:
diff changeset
517 XMM9,
a61af66fc99e Initial load
duke
parents:
diff changeset
518 XMM10,
a61af66fc99e Initial load
duke
parents:
diff changeset
519 XMM11,
a61af66fc99e Initial load
duke
parents:
diff changeset
520 XMM12,
a61af66fc99e Initial load
duke
parents:
diff changeset
521 XMM13,
a61af66fc99e Initial load
duke
parents:
diff changeset
522 XMM14,
a61af66fc99e Initial load
duke
parents:
diff changeset
523 XMM15);
a61af66fc99e Initial load
duke
parents:
diff changeset
524
a61af66fc99e Initial load
duke
parents:
diff changeset
525 // Class for all double registers
a61af66fc99e Initial load
duke
parents:
diff changeset
526 reg_class double_reg(XMM0, XMM0_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
527 XMM1, XMM1_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
528 XMM2, XMM2_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
529 XMM3, XMM3_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
530 XMM4, XMM4_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
531 XMM5, XMM5_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
532 XMM6, XMM6_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
533 XMM7, XMM7_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
534 XMM8, XMM8_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
535 XMM9, XMM9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
536 XMM10, XMM10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
537 XMM11, XMM11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
538 XMM12, XMM12_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
539 XMM13, XMM13_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
540 XMM14, XMM14_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
541 XMM15, XMM15_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
542 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
543
a61af66fc99e Initial load
duke
parents:
diff changeset
544
a61af66fc99e Initial load
duke
parents:
diff changeset
545 //----------SOURCE BLOCK-------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
546 // This is a block of C++ code which provides values, functions, and
a61af66fc99e Initial load
duke
parents:
diff changeset
547 // definitions necessary in the rest of the architecture description
a61af66fc99e Initial load
duke
parents:
diff changeset
548 source %{
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
549 #define RELOC_IMM64 Assembler::imm_operand
0
a61af66fc99e Initial load
duke
parents:
diff changeset
550 #define RELOC_DISP32 Assembler::disp32_operand
a61af66fc99e Initial load
duke
parents:
diff changeset
551
a61af66fc99e Initial load
duke
parents:
diff changeset
552 #define __ _masm.
a61af66fc99e Initial load
duke
parents:
diff changeset
553
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
554 static int preserve_SP_size() {
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
555 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg)
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
556 }
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
557
0
a61af66fc99e Initial load
duke
parents:
diff changeset
558 // !!!!! Special hack to get all types of calls to specify the byte offset
a61af66fc99e Initial load
duke
parents:
diff changeset
559 // from the start of the call to the point where the return address
a61af66fc99e Initial load
duke
parents:
diff changeset
560 // will point.
a61af66fc99e Initial load
duke
parents:
diff changeset
561 int MachCallStaticJavaNode::ret_addr_offset()
a61af66fc99e Initial load
duke
parents:
diff changeset
562 {
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
563 int offset = 5; // 5 bytes from start of call to where return address points
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
564 if (_method_handle_invoke)
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
565 offset += preserve_SP_size();
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
566 return offset;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
567 }
a61af66fc99e Initial load
duke
parents:
diff changeset
568
a61af66fc99e Initial load
duke
parents:
diff changeset
569 int MachCallDynamicJavaNode::ret_addr_offset()
a61af66fc99e Initial load
duke
parents:
diff changeset
570 {
a61af66fc99e Initial load
duke
parents:
diff changeset
571 return 15; // 15 bytes from start of call to where return address points
a61af66fc99e Initial load
duke
parents:
diff changeset
572 }
a61af66fc99e Initial load
duke
parents:
diff changeset
573
a61af66fc99e Initial load
duke
parents:
diff changeset
574 // In os_cpu .ad file
a61af66fc99e Initial load
duke
parents:
diff changeset
575 // int MachCallRuntimeNode::ret_addr_offset()
a61af66fc99e Initial load
duke
parents:
diff changeset
576
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
577 // Indicate if the safepoint node needs the polling page as an input,
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
578 // it does if the polling page is more than disp32 away.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
579 bool SafePointNode::needs_polling_address_input()
a61af66fc99e Initial load
duke
parents:
diff changeset
580 {
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
581 return Assembler::is_polling_page_far();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
582 }
a61af66fc99e Initial load
duke
parents:
diff changeset
583
a61af66fc99e Initial load
duke
parents:
diff changeset
584 //
a61af66fc99e Initial load
duke
parents:
diff changeset
585 // Compute padding required for nodes which need alignment
a61af66fc99e Initial load
duke
parents:
diff changeset
586 //
a61af66fc99e Initial load
duke
parents:
diff changeset
587
a61af66fc99e Initial load
duke
parents:
diff changeset
588 // The address of the call instruction needs to be 4-byte aligned to
a61af66fc99e Initial load
duke
parents:
diff changeset
589 // ensure that it does not span a cache line so that it can be patched.
a61af66fc99e Initial load
duke
parents:
diff changeset
590 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
a61af66fc99e Initial load
duke
parents:
diff changeset
591 {
a61af66fc99e Initial load
duke
parents:
diff changeset
592 current_offset += 1; // skip call opcode byte
a61af66fc99e Initial load
duke
parents:
diff changeset
593 return round_to(current_offset, alignment_required()) - current_offset;
a61af66fc99e Initial load
duke
parents:
diff changeset
594 }
a61af66fc99e Initial load
duke
parents:
diff changeset
595
a61af66fc99e Initial load
duke
parents:
diff changeset
596 // The address of the call instruction needs to be 4-byte aligned to
a61af66fc99e Initial load
duke
parents:
diff changeset
597 // ensure that it does not span a cache line so that it can be patched.
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
598 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
599 {
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
600 current_offset += preserve_SP_size(); // skip mov rbp, rsp
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
601 current_offset += 1; // skip call opcode byte
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
602 return round_to(current_offset, alignment_required()) - current_offset;
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
603 }
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
604
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
605 // The address of the call instruction needs to be 4-byte aligned to
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
606 // ensure that it does not span a cache line so that it can be patched.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
607 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
a61af66fc99e Initial load
duke
parents:
diff changeset
608 {
a61af66fc99e Initial load
duke
parents:
diff changeset
609 current_offset += 11; // skip movq instruction + call opcode byte
a61af66fc99e Initial load
duke
parents:
diff changeset
610 return round_to(current_offset, alignment_required()) - current_offset;
a61af66fc99e Initial load
duke
parents:
diff changeset
611 }
a61af66fc99e Initial load
duke
parents:
diff changeset
612
a61af66fc99e Initial load
duke
parents:
diff changeset
613 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
614 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const
a61af66fc99e Initial load
duke
parents:
diff changeset
615 {
a61af66fc99e Initial load
duke
parents:
diff changeset
616 st->print("INT3");
a61af66fc99e Initial load
duke
parents:
diff changeset
617 }
a61af66fc99e Initial load
duke
parents:
diff changeset
618 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
619
a61af66fc99e Initial load
duke
parents:
diff changeset
620 // EMIT_RM()
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
621 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
622 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
623 cbuf.insts()->emit_int8(c);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
624 }
a61af66fc99e Initial load
duke
parents:
diff changeset
625
a61af66fc99e Initial load
duke
parents:
diff changeset
626 // EMIT_CC()
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
627 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
628 unsigned char c = (unsigned char) (f1 | f2);
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
629 cbuf.insts()->emit_int8(c);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
630 }
a61af66fc99e Initial load
duke
parents:
diff changeset
631
a61af66fc99e Initial load
duke
parents:
diff changeset
632 // EMIT_OPCODE()
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
633 void emit_opcode(CodeBuffer &cbuf, int code) {
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
634 cbuf.insts()->emit_int8((unsigned char) code);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
635 }
a61af66fc99e Initial load
duke
parents:
diff changeset
636
a61af66fc99e Initial load
duke
parents:
diff changeset
637 // EMIT_OPCODE() w/ relocation information
a61af66fc99e Initial load
duke
parents:
diff changeset
638 void emit_opcode(CodeBuffer &cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
639 int code, relocInfo::relocType reloc, int offset, int format)
a61af66fc99e Initial load
duke
parents:
diff changeset
640 {
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
641 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
642 emit_opcode(cbuf, code);
a61af66fc99e Initial load
duke
parents:
diff changeset
643 }
a61af66fc99e Initial load
duke
parents:
diff changeset
644
a61af66fc99e Initial load
duke
parents:
diff changeset
645 // EMIT_D8()
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
646 void emit_d8(CodeBuffer &cbuf, int d8) {
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
647 cbuf.insts()->emit_int8((unsigned char) d8);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
648 }
a61af66fc99e Initial load
duke
parents:
diff changeset
649
a61af66fc99e Initial load
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parents:
diff changeset
650 // EMIT_D16()
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
651 void emit_d16(CodeBuffer &cbuf, int d16) {
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
652 cbuf.insts()->emit_int16(d16);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
653 }
a61af66fc99e Initial load
duke
parents:
diff changeset
654
a61af66fc99e Initial load
duke
parents:
diff changeset
655 // EMIT_D32()
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
656 void emit_d32(CodeBuffer &cbuf, int d32) {
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
657 cbuf.insts()->emit_int32(d32);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
658 }
a61af66fc99e Initial load
duke
parents:
diff changeset
659
a61af66fc99e Initial load
duke
parents:
diff changeset
660 // EMIT_D64()
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
661 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
662 cbuf.insts()->emit_int64(d64);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
663 }
a61af66fc99e Initial load
duke
parents:
diff changeset
664
a61af66fc99e Initial load
duke
parents:
diff changeset
665 // emit 32 bit value and construct relocation entry from relocInfo::relocType
a61af66fc99e Initial load
duke
parents:
diff changeset
666 void emit_d32_reloc(CodeBuffer& cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
667 int d32,
a61af66fc99e Initial load
duke
parents:
diff changeset
668 relocInfo::relocType reloc,
a61af66fc99e Initial load
duke
parents:
diff changeset
669 int format)
a61af66fc99e Initial load
duke
parents:
diff changeset
670 {
a61af66fc99e Initial load
duke
parents:
diff changeset
671 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
672 cbuf.relocate(cbuf.insts_mark(), reloc, format);
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
673 cbuf.insts()->emit_int32(d32);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
674 }
a61af66fc99e Initial load
duke
parents:
diff changeset
675
a61af66fc99e Initial load
duke
parents:
diff changeset
676 // emit 32 bit value and construct relocation entry from RelocationHolder
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
677 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
678 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
679 if (rspec.reloc()->type() == relocInfo::oop_type &&
a61af66fc99e Initial load
duke
parents:
diff changeset
680 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
989
148e5441d916 6863023: need non-perm oops in code cache for JSR 292
jrose
parents: 986
diff changeset
681 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
682 }
a61af66fc99e Initial load
duke
parents:
diff changeset
683 #endif
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
684 cbuf.relocate(cbuf.insts_mark(), rspec, format);
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
685 cbuf.insts()->emit_int32(d32);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
686 }
a61af66fc99e Initial load
duke
parents:
diff changeset
687
a61af66fc99e Initial load
duke
parents:
diff changeset
688 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
689 address next_ip = cbuf.insts_end() + 4;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
690 emit_d32_reloc(cbuf, (int) (addr - next_ip),
a61af66fc99e Initial load
duke
parents:
diff changeset
691 external_word_Relocation::spec(addr),
a61af66fc99e Initial load
duke
parents:
diff changeset
692 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
693 }
a61af66fc99e Initial load
duke
parents:
diff changeset
694
a61af66fc99e Initial load
duke
parents:
diff changeset
695
a61af66fc99e Initial load
duke
parents:
diff changeset
696 // emit 64 bit value and construct relocation entry from relocInfo::relocType
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
697 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
698 cbuf.relocate(cbuf.insts_mark(), reloc, format);
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
699 cbuf.insts()->emit_int64(d64);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
700 }
a61af66fc99e Initial load
duke
parents:
diff changeset
701
a61af66fc99e Initial load
duke
parents:
diff changeset
702 // emit 64 bit value and construct relocation entry from RelocationHolder
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
703 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
704 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
705 if (rspec.reloc()->type() == relocInfo::oop_type &&
a61af66fc99e Initial load
duke
parents:
diff changeset
706 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
989
148e5441d916 6863023: need non-perm oops in code cache for JSR 292
jrose
parents: 986
diff changeset
707 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()),
148e5441d916 6863023: need non-perm oops in code cache for JSR 292
jrose
parents: 986
diff changeset
708 "cannot embed scavengable oops in code");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
709 }
a61af66fc99e Initial load
duke
parents:
diff changeset
710 #endif
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
711 cbuf.relocate(cbuf.insts_mark(), rspec, format);
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
712 cbuf.insts()->emit_int64(d64);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
713 }
a61af66fc99e Initial load
duke
parents:
diff changeset
714
a61af66fc99e Initial load
duke
parents:
diff changeset
715 // Access stack slot for load or store
a61af66fc99e Initial load
duke
parents:
diff changeset
716 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
a61af66fc99e Initial load
duke
parents:
diff changeset
717 {
a61af66fc99e Initial load
duke
parents:
diff changeset
718 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
a61af66fc99e Initial load
duke
parents:
diff changeset
719 if (-0x80 <= disp && disp < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
720 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
721 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
a61af66fc99e Initial load
duke
parents:
diff changeset
722 emit_d8(cbuf, disp); // Displacement // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
723 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
724 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
725 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
a61af66fc99e Initial load
duke
parents:
diff changeset
726 emit_d32(cbuf, disp); // Displacement // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
727 }
a61af66fc99e Initial load
duke
parents:
diff changeset
728 }
a61af66fc99e Initial load
duke
parents:
diff changeset
729
a61af66fc99e Initial load
duke
parents:
diff changeset
730 // rRegI ereg, memory mem) %{ // emit_reg_mem
a61af66fc99e Initial load
duke
parents:
diff changeset
731 void encode_RegMem(CodeBuffer &cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
732 int reg,
a61af66fc99e Initial load
duke
parents:
diff changeset
733 int base, int index, int scale, int disp, bool disp_is_oop)
a61af66fc99e Initial load
duke
parents:
diff changeset
734 {
a61af66fc99e Initial load
duke
parents:
diff changeset
735 assert(!disp_is_oop, "cannot have disp");
a61af66fc99e Initial load
duke
parents:
diff changeset
736 int regenc = reg & 7;
a61af66fc99e Initial load
duke
parents:
diff changeset
737 int baseenc = base & 7;
a61af66fc99e Initial load
duke
parents:
diff changeset
738 int indexenc = index & 7;
a61af66fc99e Initial load
duke
parents:
diff changeset
739
a61af66fc99e Initial load
duke
parents:
diff changeset
740 // There is no index & no scale, use form without SIB byte
a61af66fc99e Initial load
duke
parents:
diff changeset
741 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
a61af66fc99e Initial load
duke
parents:
diff changeset
742 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
a61af66fc99e Initial load
duke
parents:
diff changeset
743 if (disp == 0 && base != RBP_enc && base != R13_enc) {
a61af66fc99e Initial load
duke
parents:
diff changeset
744 emit_rm(cbuf, 0x0, regenc, baseenc); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
745 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
a61af66fc99e Initial load
duke
parents:
diff changeset
746 // If 8-bit displacement, mode 0x1
a61af66fc99e Initial load
duke
parents:
diff changeset
747 emit_rm(cbuf, 0x1, regenc, baseenc); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
748 emit_d8(cbuf, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
749 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
750 // If 32-bit displacement
a61af66fc99e Initial load
duke
parents:
diff changeset
751 if (base == -1) { // Special flag for absolute address
a61af66fc99e Initial load
duke
parents:
diff changeset
752 emit_rm(cbuf, 0x0, regenc, 0x5); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
753 if (disp_is_oop) {
a61af66fc99e Initial load
duke
parents:
diff changeset
754 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
755 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
756 emit_d32(cbuf, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
757 }
a61af66fc99e Initial load
duke
parents:
diff changeset
758 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
759 // Normal base + offset
a61af66fc99e Initial load
duke
parents:
diff changeset
760 emit_rm(cbuf, 0x2, regenc, baseenc); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
761 if (disp_is_oop) {
a61af66fc99e Initial load
duke
parents:
diff changeset
762 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
763 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
764 emit_d32(cbuf, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
765 }
a61af66fc99e Initial load
duke
parents:
diff changeset
766 }
a61af66fc99e Initial load
duke
parents:
diff changeset
767 }
a61af66fc99e Initial load
duke
parents:
diff changeset
768 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
769 // Else, encode with the SIB byte
a61af66fc99e Initial load
duke
parents:
diff changeset
770 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
a61af66fc99e Initial load
duke
parents:
diff changeset
771 if (disp == 0 && base != RBP_enc && base != R13_enc) {
a61af66fc99e Initial load
duke
parents:
diff changeset
772 // If no displacement
a61af66fc99e Initial load
duke
parents:
diff changeset
773 emit_rm(cbuf, 0x0, regenc, 0x4); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
774 emit_rm(cbuf, scale, indexenc, baseenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
775 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
776 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
a61af66fc99e Initial load
duke
parents:
diff changeset
777 // If 8-bit displacement, mode 0x1
a61af66fc99e Initial load
duke
parents:
diff changeset
778 emit_rm(cbuf, 0x1, regenc, 0x4); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
779 emit_rm(cbuf, scale, indexenc, baseenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
780 emit_d8(cbuf, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
781 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
782 // If 32-bit displacement
a61af66fc99e Initial load
duke
parents:
diff changeset
783 if (base == 0x04 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
784 emit_rm(cbuf, 0x2, regenc, 0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
785 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
a61af66fc99e Initial load
duke
parents:
diff changeset
786 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
787 emit_rm(cbuf, 0x2, regenc, 0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
788 emit_rm(cbuf, scale, indexenc, baseenc); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
789 }
a61af66fc99e Initial load
duke
parents:
diff changeset
790 if (disp_is_oop) {
a61af66fc99e Initial load
duke
parents:
diff changeset
791 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
792 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
793 emit_d32(cbuf, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
794 }
a61af66fc99e Initial load
duke
parents:
diff changeset
795 }
a61af66fc99e Initial load
duke
parents:
diff changeset
796 }
a61af66fc99e Initial load
duke
parents:
diff changeset
797 }
a61af66fc99e Initial load
duke
parents:
diff changeset
798 }
a61af66fc99e Initial load
duke
parents:
diff changeset
799
a61af66fc99e Initial load
duke
parents:
diff changeset
800 void encode_copy(CodeBuffer &cbuf, int dstenc, int srcenc)
a61af66fc99e Initial load
duke
parents:
diff changeset
801 {
a61af66fc99e Initial load
duke
parents:
diff changeset
802 if (dstenc != srcenc) {
a61af66fc99e Initial load
duke
parents:
diff changeset
803 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
804 if (srcenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
805 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
806 srcenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
807 }
a61af66fc99e Initial load
duke
parents:
diff changeset
808 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
809 if (srcenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
810 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
811 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
812 emit_opcode(cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
813 srcenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
814 }
a61af66fc99e Initial load
duke
parents:
diff changeset
815 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
816 }
a61af66fc99e Initial load
duke
parents:
diff changeset
817
a61af66fc99e Initial load
duke
parents:
diff changeset
818 emit_opcode(cbuf, 0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
819 emit_rm(cbuf, 0x3, dstenc, srcenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
820 }
a61af66fc99e Initial load
duke
parents:
diff changeset
821 }
a61af66fc99e Initial load
duke
parents:
diff changeset
822
a61af66fc99e Initial load
duke
parents:
diff changeset
823 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
824 if( dst_encoding == src_encoding ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
825 // reg-reg copy, use an empty encoding
a61af66fc99e Initial load
duke
parents:
diff changeset
826 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
827 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
828
a61af66fc99e Initial load
duke
parents:
diff changeset
829 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
a61af66fc99e Initial load
duke
parents:
diff changeset
830 }
a61af66fc99e Initial load
duke
parents:
diff changeset
831 }
a61af66fc99e Initial load
duke
parents:
diff changeset
832
a61af66fc99e Initial load
duke
parents:
diff changeset
833
a61af66fc99e Initial load
duke
parents:
diff changeset
834 //=============================================================================
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
835 const bool Matcher::constant_table_absolute_addressing = true;
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
836 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
837
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
838 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
839 // Empty encoding
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
840 }
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
841
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
842 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
843 return 0;
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
844 }
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
845
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
846 #ifndef PRODUCT
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
847 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
848 st->print("# MachConstantBaseNode (empty encoding)");
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
849 }
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
850 #endif
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
851
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
852
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
853 //=============================================================================
0
a61af66fc99e Initial load
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parents:
diff changeset
854 #ifndef PRODUCT
a61af66fc99e Initial load
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parents:
diff changeset
855 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const
a61af66fc99e Initial load
duke
parents:
diff changeset
856 {
a61af66fc99e Initial load
duke
parents:
diff changeset
857 Compile* C = ra_->C;
a61af66fc99e Initial load
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parents:
diff changeset
858
a61af66fc99e Initial load
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parents:
diff changeset
859 int framesize = C->frame_slots() << LogBytesPerInt;
a61af66fc99e Initial load
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parents:
diff changeset
860 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
a61af66fc99e Initial load
duke
parents:
diff changeset
861 // Remove wordSize for return adr already pushed
a61af66fc99e Initial load
duke
parents:
diff changeset
862 // and another for the RBP we are going to save
a61af66fc99e Initial load
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parents:
diff changeset
863 framesize -= 2*wordSize;
a61af66fc99e Initial load
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parents:
diff changeset
864 bool need_nop = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
865
a61af66fc99e Initial load
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parents:
diff changeset
866 // Calls to C2R adapters often do not accept exceptional returns.
a61af66fc99e Initial load
duke
parents:
diff changeset
867 // We require that their callers must bang for them. But be
a61af66fc99e Initial load
duke
parents:
diff changeset
868 // careful, because some VM calls (such as call site linkage) can
a61af66fc99e Initial load
duke
parents:
diff changeset
869 // use several kilobytes of stack. But the stack safety zone should
a61af66fc99e Initial load
duke
parents:
diff changeset
870 // account for that. See bugs 4446381, 4468289, 4497237.
a61af66fc99e Initial load
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parents:
diff changeset
871 if (C->need_stack_bang(framesize)) {
a61af66fc99e Initial load
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parents:
diff changeset
872 st->print_cr("# stack bang"); st->print("\t");
a61af66fc99e Initial load
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parents:
diff changeset
873 need_nop = false;
a61af66fc99e Initial load
duke
parents:
diff changeset
874 }
a61af66fc99e Initial load
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parents:
diff changeset
875 st->print_cr("pushq rbp"); st->print("\t");
a61af66fc99e Initial load
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parents:
diff changeset
876
a61af66fc99e Initial load
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parents:
diff changeset
877 if (VerifyStackAtCalls) {
a61af66fc99e Initial load
duke
parents:
diff changeset
878 // Majik cookie to verify stack depth
a61af66fc99e Initial load
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parents:
diff changeset
879 st->print_cr("pushq 0xffffffffbadb100d"
a61af66fc99e Initial load
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parents:
diff changeset
880 "\t# Majik cookie for stack depth check");
a61af66fc99e Initial load
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parents:
diff changeset
881 st->print("\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
882 framesize -= wordSize; // Remove 2 for cookie
a61af66fc99e Initial load
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parents:
diff changeset
883 need_nop = false;
a61af66fc99e Initial load
duke
parents:
diff changeset
884 }
a61af66fc99e Initial load
duke
parents:
diff changeset
885
a61af66fc99e Initial load
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parents:
diff changeset
886 if (framesize) {
a61af66fc99e Initial load
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parents:
diff changeset
887 st->print("subq rsp, #%d\t# Create frame", framesize);
a61af66fc99e Initial load
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parents:
diff changeset
888 if (framesize < 0x80 && need_nop) {
a61af66fc99e Initial load
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parents:
diff changeset
889 st->print("\n\tnop\t# nop for patch_verified_entry");
a61af66fc99e Initial load
duke
parents:
diff changeset
890 }
a61af66fc99e Initial load
duke
parents:
diff changeset
891 }
a61af66fc99e Initial load
duke
parents:
diff changeset
892 }
a61af66fc99e Initial load
duke
parents:
diff changeset
893 #endif
a61af66fc99e Initial load
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parents:
diff changeset
894
a61af66fc99e Initial load
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parents:
diff changeset
895 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
a61af66fc99e Initial load
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parents:
diff changeset
896 {
a61af66fc99e Initial load
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parents:
diff changeset
897 Compile* C = ra_->C;
a61af66fc99e Initial load
duke
parents:
diff changeset
898
a61af66fc99e Initial load
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parents:
diff changeset
899 // WARNING: Initial instruction MUST be 5 bytes or longer so that
a61af66fc99e Initial load
duke
parents:
diff changeset
900 // NativeJump::patch_verified_entry will be able to patch out the entry
a61af66fc99e Initial load
duke
parents:
diff changeset
901 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
a61af66fc99e Initial load
duke
parents:
diff changeset
902 // depth is ok at 5 bytes, the frame allocation can be either 3 or
a61af66fc99e Initial load
duke
parents:
diff changeset
903 // 6 bytes. So if we don't do the fldcw or the push then we must
a61af66fc99e Initial load
duke
parents:
diff changeset
904 // use the 6 byte frame allocation even if we have no frame. :-(
a61af66fc99e Initial load
duke
parents:
diff changeset
905 // If method sets FPU control word do it now
a61af66fc99e Initial load
duke
parents:
diff changeset
906
a61af66fc99e Initial load
duke
parents:
diff changeset
907 int framesize = C->frame_slots() << LogBytesPerInt;
a61af66fc99e Initial load
duke
parents:
diff changeset
908 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
a61af66fc99e Initial load
duke
parents:
diff changeset
909 // Remove wordSize for return adr already pushed
a61af66fc99e Initial load
duke
parents:
diff changeset
910 // and another for the RBP we are going to save
a61af66fc99e Initial load
duke
parents:
diff changeset
911 framesize -= 2*wordSize;
a61af66fc99e Initial load
duke
parents:
diff changeset
912 bool need_nop = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
913
a61af66fc99e Initial load
duke
parents:
diff changeset
914 // Calls to C2R adapters often do not accept exceptional returns.
a61af66fc99e Initial load
duke
parents:
diff changeset
915 // We require that their callers must bang for them. But be
a61af66fc99e Initial load
duke
parents:
diff changeset
916 // careful, because some VM calls (such as call site linkage) can
a61af66fc99e Initial load
duke
parents:
diff changeset
917 // use several kilobytes of stack. But the stack safety zone should
a61af66fc99e Initial load
duke
parents:
diff changeset
918 // account for that. See bugs 4446381, 4468289, 4497237.
a61af66fc99e Initial load
duke
parents:
diff changeset
919 if (C->need_stack_bang(framesize)) {
a61af66fc99e Initial load
duke
parents:
diff changeset
920 MacroAssembler masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
921 masm.generate_stack_overflow_check(framesize);
a61af66fc99e Initial load
duke
parents:
diff changeset
922 need_nop = false;
a61af66fc99e Initial load
duke
parents:
diff changeset
923 }
a61af66fc99e Initial load
duke
parents:
diff changeset
924
a61af66fc99e Initial load
duke
parents:
diff changeset
925 // We always push rbp so that on return to interpreter rbp will be
a61af66fc99e Initial load
duke
parents:
diff changeset
926 // restored correctly and we can correct the stack.
a61af66fc99e Initial load
duke
parents:
diff changeset
927 emit_opcode(cbuf, 0x50 | RBP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
928
a61af66fc99e Initial load
duke
parents:
diff changeset
929 if (VerifyStackAtCalls) {
a61af66fc99e Initial load
duke
parents:
diff changeset
930 // Majik cookie to verify stack depth
a61af66fc99e Initial load
duke
parents:
diff changeset
931 emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d
a61af66fc99e Initial load
duke
parents:
diff changeset
932 emit_d32(cbuf, 0xbadb100d);
a61af66fc99e Initial load
duke
parents:
diff changeset
933 framesize -= wordSize; // Remove 2 for cookie
a61af66fc99e Initial load
duke
parents:
diff changeset
934 need_nop = false;
a61af66fc99e Initial load
duke
parents:
diff changeset
935 }
a61af66fc99e Initial load
duke
parents:
diff changeset
936
a61af66fc99e Initial load
duke
parents:
diff changeset
937 if (framesize) {
a61af66fc99e Initial load
duke
parents:
diff changeset
938 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
939 if (framesize < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
940 emit_opcode(cbuf, 0x83); // sub SP,#framesize
a61af66fc99e Initial load
duke
parents:
diff changeset
941 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
942 emit_d8(cbuf, framesize);
a61af66fc99e Initial load
duke
parents:
diff changeset
943 if (need_nop) {
a61af66fc99e Initial load
duke
parents:
diff changeset
944 emit_opcode(cbuf, 0x90); // nop
a61af66fc99e Initial load
duke
parents:
diff changeset
945 }
a61af66fc99e Initial load
duke
parents:
diff changeset
946 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
947 emit_opcode(cbuf, 0x81); // sub SP,#framesize
a61af66fc99e Initial load
duke
parents:
diff changeset
948 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
949 emit_d32(cbuf, framesize);
a61af66fc99e Initial load
duke
parents:
diff changeset
950 }
a61af66fc99e Initial load
duke
parents:
diff changeset
951 }
a61af66fc99e Initial load
duke
parents:
diff changeset
952
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
953 C->set_frame_complete(cbuf.insts_size());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
954
a61af66fc99e Initial load
duke
parents:
diff changeset
955 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
956 if (VerifyStackAtCalls) {
a61af66fc99e Initial load
duke
parents:
diff changeset
957 Label L;
a61af66fc99e Initial load
duke
parents:
diff changeset
958 MacroAssembler masm(&cbuf);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
959 masm.push(rax);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
960 masm.mov(rax, rsp);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
961 masm.andptr(rax, StackAlignmentInBytes-1);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
962 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
963 masm.pop(rax);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
964 masm.jcc(Assembler::equal, L);
a61af66fc99e Initial load
duke
parents:
diff changeset
965 masm.stop("Stack is not properly aligned!");
a61af66fc99e Initial load
duke
parents:
diff changeset
966 masm.bind(L);
a61af66fc99e Initial load
duke
parents:
diff changeset
967 }
a61af66fc99e Initial load
duke
parents:
diff changeset
968 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
969 }
a61af66fc99e Initial load
duke
parents:
diff changeset
970
a61af66fc99e Initial load
duke
parents:
diff changeset
971 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
972 {
a61af66fc99e Initial load
duke
parents:
diff changeset
973 return MachNode::size(ra_); // too many variables; just compute it
a61af66fc99e Initial load
duke
parents:
diff changeset
974 // the hard way
a61af66fc99e Initial load
duke
parents:
diff changeset
975 }
a61af66fc99e Initial load
duke
parents:
diff changeset
976
a61af66fc99e Initial load
duke
parents:
diff changeset
977 int MachPrologNode::reloc() const
a61af66fc99e Initial load
duke
parents:
diff changeset
978 {
a61af66fc99e Initial load
duke
parents:
diff changeset
979 return 0; // a large enough number
a61af66fc99e Initial load
duke
parents:
diff changeset
980 }
a61af66fc99e Initial load
duke
parents:
diff changeset
981
a61af66fc99e Initial load
duke
parents:
diff changeset
982 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
983 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
984 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
a61af66fc99e Initial load
duke
parents:
diff changeset
985 {
a61af66fc99e Initial load
duke
parents:
diff changeset
986 Compile* C = ra_->C;
a61af66fc99e Initial load
duke
parents:
diff changeset
987 int framesize = C->frame_slots() << LogBytesPerInt;
a61af66fc99e Initial load
duke
parents:
diff changeset
988 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
a61af66fc99e Initial load
duke
parents:
diff changeset
989 // Remove word for return adr already pushed
a61af66fc99e Initial load
duke
parents:
diff changeset
990 // and RBP
a61af66fc99e Initial load
duke
parents:
diff changeset
991 framesize -= 2*wordSize;
a61af66fc99e Initial load
duke
parents:
diff changeset
992
a61af66fc99e Initial load
duke
parents:
diff changeset
993 if (framesize) {
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
994 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
995 st->print("\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
996 }
a61af66fc99e Initial load
duke
parents:
diff changeset
997
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
998 st->print_cr("popq rbp");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
999 if (do_polling() && C->is_method_compilation()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1000 st->print("\t");
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1001 if (Assembler::is_polling_page_far()) {
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1002 st->print_cr("movq rscratch1, #polling_page_address\n\t"
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1003 "testl rax, [rscratch1]\t"
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1004 "# Safepoint: poll for GC");
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1005 } else {
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1006 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1007 "# Safepoint: poll for GC");
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1008 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1009 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1010 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1011 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1012
a61af66fc99e Initial load
duke
parents:
diff changeset
1013 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1014 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1015 Compile* C = ra_->C;
a61af66fc99e Initial load
duke
parents:
diff changeset
1016 int framesize = C->frame_slots() << LogBytesPerInt;
a61af66fc99e Initial load
duke
parents:
diff changeset
1017 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
a61af66fc99e Initial load
duke
parents:
diff changeset
1018 // Remove word for return adr already pushed
a61af66fc99e Initial load
duke
parents:
diff changeset
1019 // and RBP
a61af66fc99e Initial load
duke
parents:
diff changeset
1020 framesize -= 2*wordSize;
a61af66fc99e Initial load
duke
parents:
diff changeset
1021
a61af66fc99e Initial load
duke
parents:
diff changeset
1022 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
a61af66fc99e Initial load
duke
parents:
diff changeset
1023
a61af66fc99e Initial load
duke
parents:
diff changeset
1024 if (framesize) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1025 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
1026 if (framesize < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1027 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
a61af66fc99e Initial load
duke
parents:
diff changeset
1028 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
1029 emit_d8(cbuf, framesize);
a61af66fc99e Initial load
duke
parents:
diff changeset
1030 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1031 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
a61af66fc99e Initial load
duke
parents:
diff changeset
1032 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
1033 emit_d32(cbuf, framesize);
a61af66fc99e Initial load
duke
parents:
diff changeset
1034 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1035 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1036
a61af66fc99e Initial load
duke
parents:
diff changeset
1037 // popq rbp
a61af66fc99e Initial load
duke
parents:
diff changeset
1038 emit_opcode(cbuf, 0x58 | RBP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
1039
a61af66fc99e Initial load
duke
parents:
diff changeset
1040 if (do_polling() && C->is_method_compilation()) {
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1041 MacroAssembler _masm(&cbuf);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1042 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1043 if (Assembler::is_polling_page_far()) {
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1044 __ lea(rscratch1, polling_page);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1045 __ relocate(relocInfo::poll_return_type);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1046 __ testl(rax, Address(rscratch1, 0));
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1047 } else {
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1048 __ testl(rax, polling_page);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1049 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1050 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1051 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1052
a61af66fc99e Initial load
duke
parents:
diff changeset
1053 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1054 {
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1055 return MachNode::size(ra_); // too many variables; just compute it
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
1056 // the hard way
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1057 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1058
a61af66fc99e Initial load
duke
parents:
diff changeset
1059 int MachEpilogNode::reloc() const
a61af66fc99e Initial load
duke
parents:
diff changeset
1060 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1061 return 2; // a large enough number
a61af66fc99e Initial load
duke
parents:
diff changeset
1062 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1063
a61af66fc99e Initial load
duke
parents:
diff changeset
1064 const Pipeline* MachEpilogNode::pipeline() const
a61af66fc99e Initial load
duke
parents:
diff changeset
1065 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1066 return MachNode::pipeline_class();
a61af66fc99e Initial load
duke
parents:
diff changeset
1067 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1068
a61af66fc99e Initial load
duke
parents:
diff changeset
1069 int MachEpilogNode::safepoint_offset() const
a61af66fc99e Initial load
duke
parents:
diff changeset
1070 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1071 return 0;
a61af66fc99e Initial load
duke
parents:
diff changeset
1072 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1073
a61af66fc99e Initial load
duke
parents:
diff changeset
1074 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1075
a61af66fc99e Initial load
duke
parents:
diff changeset
1076 enum RC {
a61af66fc99e Initial load
duke
parents:
diff changeset
1077 rc_bad,
a61af66fc99e Initial load
duke
parents:
diff changeset
1078 rc_int,
a61af66fc99e Initial load
duke
parents:
diff changeset
1079 rc_float,
a61af66fc99e Initial load
duke
parents:
diff changeset
1080 rc_stack
a61af66fc99e Initial load
duke
parents:
diff changeset
1081 };
a61af66fc99e Initial load
duke
parents:
diff changeset
1082
a61af66fc99e Initial load
duke
parents:
diff changeset
1083 static enum RC rc_class(OptoReg::Name reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
1084 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1085 if( !OptoReg::is_valid(reg) ) return rc_bad;
a61af66fc99e Initial load
duke
parents:
diff changeset
1086
a61af66fc99e Initial load
duke
parents:
diff changeset
1087 if (OptoReg::is_stack(reg)) return rc_stack;
a61af66fc99e Initial load
duke
parents:
diff changeset
1088
a61af66fc99e Initial load
duke
parents:
diff changeset
1089 VMReg r = OptoReg::as_VMReg(reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
1090
a61af66fc99e Initial load
duke
parents:
diff changeset
1091 if (r->is_Register()) return rc_int;
a61af66fc99e Initial load
duke
parents:
diff changeset
1092
a61af66fc99e Initial load
duke
parents:
diff changeset
1093 assert(r->is_XMMRegister(), "must be");
a61af66fc99e Initial load
duke
parents:
diff changeset
1094 return rc_float;
a61af66fc99e Initial load
duke
parents:
diff changeset
1095 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1096
a61af66fc99e Initial load
duke
parents:
diff changeset
1097 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
1098 PhaseRegAlloc* ra_,
a61af66fc99e Initial load
duke
parents:
diff changeset
1099 bool do_size,
a61af66fc99e Initial load
duke
parents:
diff changeset
1100 outputStream* st) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1101 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1102
a61af66fc99e Initial load
duke
parents:
diff changeset
1103 // Get registers to move
a61af66fc99e Initial load
duke
parents:
diff changeset
1104 OptoReg::Name src_second = ra_->get_reg_second(in(1));
a61af66fc99e Initial load
duke
parents:
diff changeset
1105 OptoReg::Name src_first = ra_->get_reg_first(in(1));
a61af66fc99e Initial load
duke
parents:
diff changeset
1106 OptoReg::Name dst_second = ra_->get_reg_second(this);
a61af66fc99e Initial load
duke
parents:
diff changeset
1107 OptoReg::Name dst_first = ra_->get_reg_first(this);
a61af66fc99e Initial load
duke
parents:
diff changeset
1108
a61af66fc99e Initial load
duke
parents:
diff changeset
1109 enum RC src_second_rc = rc_class(src_second);
a61af66fc99e Initial load
duke
parents:
diff changeset
1110 enum RC src_first_rc = rc_class(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1111 enum RC dst_second_rc = rc_class(dst_second);
a61af66fc99e Initial load
duke
parents:
diff changeset
1112 enum RC dst_first_rc = rc_class(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1113
a61af66fc99e Initial load
duke
parents:
diff changeset
1114 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
a61af66fc99e Initial load
duke
parents:
diff changeset
1115 "must move at least 1 register" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1116
a61af66fc99e Initial load
duke
parents:
diff changeset
1117 if (src_first == dst_first && src_second == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1118 // Self copy, no move
a61af66fc99e Initial load
duke
parents:
diff changeset
1119 return 0;
a61af66fc99e Initial load
duke
parents:
diff changeset
1120 } else if (src_first_rc == rc_stack) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1121 // mem ->
a61af66fc99e Initial load
duke
parents:
diff changeset
1122 if (dst_first_rc == rc_stack) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1123 // mem -> mem
a61af66fc99e Initial load
duke
parents:
diff changeset
1124 assert(src_second != dst_first, "overlap");
a61af66fc99e Initial load
duke
parents:
diff changeset
1125 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1126 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1127 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1128 int src_offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1129 int dst_offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1130 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1131 emit_opcode(*cbuf, 0xFF);
a61af66fc99e Initial load
duke
parents:
diff changeset
1132 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false);
a61af66fc99e Initial load
duke
parents:
diff changeset
1133
a61af66fc99e Initial load
duke
parents:
diff changeset
1134 emit_opcode(*cbuf, 0x8F);
a61af66fc99e Initial load
duke
parents:
diff changeset
1135 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false);
a61af66fc99e Initial load
duke
parents:
diff changeset
1136
a61af66fc99e Initial load
duke
parents:
diff changeset
1137 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1138 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1139 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
1140 "popq [rsp + #%d]",
a61af66fc99e Initial load
duke
parents:
diff changeset
1141 src_offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1142 dst_offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1143 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1144 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1145 return
a61af66fc99e Initial load
duke
parents:
diff changeset
1146 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) +
a61af66fc99e Initial load
duke
parents:
diff changeset
1147 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4));
a61af66fc99e Initial load
duke
parents:
diff changeset
1148 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1149 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1150 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1151 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1152 // No pushl/popl, so:
a61af66fc99e Initial load
duke
parents:
diff changeset
1153 int src_offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1154 int dst_offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1155 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1156 emit_opcode(*cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
1157 emit_opcode(*cbuf, 0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
1158 emit_opcode(*cbuf, 0x44);
a61af66fc99e Initial load
duke
parents:
diff changeset
1159 emit_opcode(*cbuf, 0x24);
a61af66fc99e Initial load
duke
parents:
diff changeset
1160 emit_opcode(*cbuf, 0xF8);
a61af66fc99e Initial load
duke
parents:
diff changeset
1161
a61af66fc99e Initial load
duke
parents:
diff changeset
1162 emit_opcode(*cbuf, 0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
1163 encode_RegMem(*cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
1164 RAX_enc,
a61af66fc99e Initial load
duke
parents:
diff changeset
1165 RSP_enc, 0x4, 0, src_offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1166 false);
a61af66fc99e Initial load
duke
parents:
diff changeset
1167
a61af66fc99e Initial load
duke
parents:
diff changeset
1168 emit_opcode(*cbuf, 0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
1169 encode_RegMem(*cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
1170 RAX_enc,
a61af66fc99e Initial load
duke
parents:
diff changeset
1171 RSP_enc, 0x4, 0, dst_offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1172 false);
a61af66fc99e Initial load
duke
parents:
diff changeset
1173
a61af66fc99e Initial load
duke
parents:
diff changeset
1174 emit_opcode(*cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
1175 emit_opcode(*cbuf, 0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
1176 emit_opcode(*cbuf, 0x44);
a61af66fc99e Initial load
duke
parents:
diff changeset
1177 emit_opcode(*cbuf, 0x24);
a61af66fc99e Initial load
duke
parents:
diff changeset
1178 emit_opcode(*cbuf, 0xF8);
a61af66fc99e Initial load
duke
parents:
diff changeset
1179
a61af66fc99e Initial load
duke
parents:
diff changeset
1180 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1181 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1182 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
1183 "movl rax, [rsp + #%d]\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
1184 "movl [rsp + #%d], rax\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
1185 "movq rax, [rsp - #8]",
a61af66fc99e Initial load
duke
parents:
diff changeset
1186 src_offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1187 dst_offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1188 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1189 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1190 return
a61af66fc99e Initial load
duke
parents:
diff changeset
1191 5 + // movq
a61af66fc99e Initial load
duke
parents:
diff changeset
1192 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl
a61af66fc99e Initial load
duke
parents:
diff changeset
1193 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl
a61af66fc99e Initial load
duke
parents:
diff changeset
1194 5; // movq
a61af66fc99e Initial load
duke
parents:
diff changeset
1195 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1196 } else if (dst_first_rc == rc_int) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1197 // mem -> gpr
a61af66fc99e Initial load
duke
parents:
diff changeset
1198 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1199 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1200 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1201 int offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1202 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1203 if (Matcher::_regEncode[dst_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1204 emit_opcode(*cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
1205 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1206 emit_opcode(*cbuf, Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
1207 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1208 emit_opcode(*cbuf, 0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
1209 encode_RegMem(*cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
1210 Matcher::_regEncode[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1211 RSP_enc, 0x4, 0, offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1212 false);
a61af66fc99e Initial load
duke
parents:
diff changeset
1213 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1214 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1215 st->print("movq %s, [rsp + #%d]\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1216 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1217 offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1218 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1219 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1220 return
a61af66fc99e Initial load
duke
parents:
diff changeset
1221 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1222 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1223 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1224 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1225 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1226 int offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1227 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1228 if (Matcher::_regEncode[dst_first] >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1229 emit_opcode(*cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
1230 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1231 emit_opcode(*cbuf, 0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
1232 encode_RegMem(*cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
1233 Matcher::_regEncode[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1234 RSP_enc, 0x4, 0, offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1235 false);
a61af66fc99e Initial load
duke
parents:
diff changeset
1236 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1237 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1238 st->print("movl %s, [rsp + #%d]\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1239 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1240 offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1241 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1242 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1243 return
a61af66fc99e Initial load
duke
parents:
diff changeset
1244 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
a61af66fc99e Initial load
duke
parents:
diff changeset
1245 ((Matcher::_regEncode[dst_first] < 8)
a61af66fc99e Initial load
duke
parents:
diff changeset
1246 ? 3
a61af66fc99e Initial load
duke
parents:
diff changeset
1247 : 4); // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1248 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1249 } else if (dst_first_rc == rc_float) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1250 // mem-> xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
1251 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1252 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1253 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1254 int offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1255 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1256 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
a61af66fc99e Initial load
duke
parents:
diff changeset
1257 if (Matcher::_regEncode[dst_first] >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1258 emit_opcode(*cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
1259 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1260 emit_opcode(*cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
1261 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
a61af66fc99e Initial load
duke
parents:
diff changeset
1262 encode_RegMem(*cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
1263 Matcher::_regEncode[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1264 RSP_enc, 0x4, 0, offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1265 false);
a61af66fc99e Initial load
duke
parents:
diff changeset
1266 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1267 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1268 st->print("%s %s, [rsp + #%d]\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1269 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
a61af66fc99e Initial load
duke
parents:
diff changeset
1270 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1271 offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1272 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1273 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1274 return
a61af66fc99e Initial load
duke
parents:
diff changeset
1275 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
a61af66fc99e Initial load
duke
parents:
diff changeset
1276 ((Matcher::_regEncode[dst_first] < 8)
a61af66fc99e Initial load
duke
parents:
diff changeset
1277 ? 5
a61af66fc99e Initial load
duke
parents:
diff changeset
1278 : 6); // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1279 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1280 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1281 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1282 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1283 int offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1284 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1285 emit_opcode(*cbuf, 0xF3);
a61af66fc99e Initial load
duke
parents:
diff changeset
1286 if (Matcher::_regEncode[dst_first] >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1287 emit_opcode(*cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
1288 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1289 emit_opcode(*cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
1290 emit_opcode(*cbuf, 0x10);
a61af66fc99e Initial load
duke
parents:
diff changeset
1291 encode_RegMem(*cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
1292 Matcher::_regEncode[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1293 RSP_enc, 0x4, 0, offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1294 false);
a61af66fc99e Initial load
duke
parents:
diff changeset
1295 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1296 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1297 st->print("movss %s, [rsp + #%d]\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1298 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1299 offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1300 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1301 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1302 return
a61af66fc99e Initial load
duke
parents:
diff changeset
1303 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
a61af66fc99e Initial load
duke
parents:
diff changeset
1304 ((Matcher::_regEncode[dst_first] < 8)
a61af66fc99e Initial load
duke
parents:
diff changeset
1305 ? 5
a61af66fc99e Initial load
duke
parents:
diff changeset
1306 : 6); // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1307 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1308 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1309 } else if (src_first_rc == rc_int) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1310 // gpr ->
a61af66fc99e Initial load
duke
parents:
diff changeset
1311 if (dst_first_rc == rc_stack) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1312 // gpr -> mem
a61af66fc99e Initial load
duke
parents:
diff changeset
1313 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1314 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1315 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1316 int offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1317 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1318 if (Matcher::_regEncode[src_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1319 emit_opcode(*cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
1320 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1321 emit_opcode(*cbuf, Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
1322 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1323 emit_opcode(*cbuf, 0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
1324 encode_RegMem(*cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
1325 Matcher::_regEncode[src_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1326 RSP_enc, 0x4, 0, offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1327 false);
a61af66fc99e Initial load
duke
parents:
diff changeset
1328 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1329 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1330 st->print("movq [rsp + #%d], %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1331 offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1332 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1333 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1334 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1335 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1336 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1337 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1338 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1339 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1340 int offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1341 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1342 if (Matcher::_regEncode[src_first] >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1343 emit_opcode(*cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
1344 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1345 emit_opcode(*cbuf, 0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
1346 encode_RegMem(*cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
1347 Matcher::_regEncode[src_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1348 RSP_enc, 0x4, 0, offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1349 false);
a61af66fc99e Initial load
duke
parents:
diff changeset
1350 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1351 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1352 st->print("movl [rsp + #%d], %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1353 offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1354 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1355 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1356 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1357 return
a61af66fc99e Initial load
duke
parents:
diff changeset
1358 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
a61af66fc99e Initial load
duke
parents:
diff changeset
1359 ((Matcher::_regEncode[src_first] < 8)
a61af66fc99e Initial load
duke
parents:
diff changeset
1360 ? 3
a61af66fc99e Initial load
duke
parents:
diff changeset
1361 : 4); // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1362 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1363 } else if (dst_first_rc == rc_int) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1364 // gpr -> gpr
a61af66fc99e Initial load
duke
parents:
diff changeset
1365 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1366 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1367 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1368 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1369 if (Matcher::_regEncode[dst_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1370 if (Matcher::_regEncode[src_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1371 emit_opcode(*cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
1372 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1373 emit_opcode(*cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
1374 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1375 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1376 if (Matcher::_regEncode[src_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1377 emit_opcode(*cbuf, Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
1378 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1379 emit_opcode(*cbuf, Assembler::REX_WRB);
a61af66fc99e Initial load
duke
parents:
diff changeset
1380 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1381 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1382 emit_opcode(*cbuf, 0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
1383 emit_rm(*cbuf, 0x3,
a61af66fc99e Initial load
duke
parents:
diff changeset
1384 Matcher::_regEncode[dst_first] & 7,
a61af66fc99e Initial load
duke
parents:
diff changeset
1385 Matcher::_regEncode[src_first] & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1386 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1387 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1388 st->print("movq %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1389 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1390 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1391 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1392 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1393 return 3; // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1394 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1395 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1396 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1397 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1398 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1399 if (Matcher::_regEncode[dst_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1400 if (Matcher::_regEncode[src_first] >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1401 emit_opcode(*cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
1402 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1403 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1404 if (Matcher::_regEncode[src_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1405 emit_opcode(*cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
1406 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1407 emit_opcode(*cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
1408 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1409 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1410 emit_opcode(*cbuf, 0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
1411 emit_rm(*cbuf, 0x3,
a61af66fc99e Initial load
duke
parents:
diff changeset
1412 Matcher::_regEncode[dst_first] & 7,
a61af66fc99e Initial load
duke
parents:
diff changeset
1413 Matcher::_regEncode[src_first] & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1414 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1415 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1416 st->print("movl %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1417 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1418 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1419 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1420 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1421 return
a61af66fc99e Initial load
duke
parents:
diff changeset
1422 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
a61af66fc99e Initial load
duke
parents:
diff changeset
1423 ? 2
a61af66fc99e Initial load
duke
parents:
diff changeset
1424 : 3; // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1425 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1426 } else if (dst_first_rc == rc_float) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1427 // gpr -> xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
1428 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1429 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1430 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1431 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1432 emit_opcode(*cbuf, 0x66);
a61af66fc99e Initial load
duke
parents:
diff changeset
1433 if (Matcher::_regEncode[dst_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1434 if (Matcher::_regEncode[src_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1435 emit_opcode(*cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
1436 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1437 emit_opcode(*cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
1438 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1439 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1440 if (Matcher::_regEncode[src_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1441 emit_opcode(*cbuf, Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
1442 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1443 emit_opcode(*cbuf, Assembler::REX_WRB);
a61af66fc99e Initial load
duke
parents:
diff changeset
1444 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1445 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1446 emit_opcode(*cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
1447 emit_opcode(*cbuf, 0x6E);
a61af66fc99e Initial load
duke
parents:
diff changeset
1448 emit_rm(*cbuf, 0x3,
a61af66fc99e Initial load
duke
parents:
diff changeset
1449 Matcher::_regEncode[dst_first] & 7,
a61af66fc99e Initial load
duke
parents:
diff changeset
1450 Matcher::_regEncode[src_first] & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1451 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1452 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1453 st->print("movdq %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1454 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1455 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1456 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1457 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1458 return 5; // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1459 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1460 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1461 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1462 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1463 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1464 emit_opcode(*cbuf, 0x66);
a61af66fc99e Initial load
duke
parents:
diff changeset
1465 if (Matcher::_regEncode[dst_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1466 if (Matcher::_regEncode[src_first] >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1467 emit_opcode(*cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
1468 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1469 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1470 if (Matcher::_regEncode[src_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1471 emit_opcode(*cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
1472 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1473 emit_opcode(*cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
1474 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1475 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1476 emit_opcode(*cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
1477 emit_opcode(*cbuf, 0x6E);
a61af66fc99e Initial load
duke
parents:
diff changeset
1478 emit_rm(*cbuf, 0x3,
a61af66fc99e Initial load
duke
parents:
diff changeset
1479 Matcher::_regEncode[dst_first] & 7,
a61af66fc99e Initial load
duke
parents:
diff changeset
1480 Matcher::_regEncode[src_first] & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1481 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1482 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1483 st->print("movdl %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1484 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1485 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1486 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1487 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1488 return
a61af66fc99e Initial load
duke
parents:
diff changeset
1489 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
a61af66fc99e Initial load
duke
parents:
diff changeset
1490 ? 4
a61af66fc99e Initial load
duke
parents:
diff changeset
1491 : 5; // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1492 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1493 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1494 } else if (src_first_rc == rc_float) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1495 // xmm ->
a61af66fc99e Initial load
duke
parents:
diff changeset
1496 if (dst_first_rc == rc_stack) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1497 // xmm -> mem
a61af66fc99e Initial load
duke
parents:
diff changeset
1498 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1499 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1500 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1501 int offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1502 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1503 emit_opcode(*cbuf, 0xF2);
a61af66fc99e Initial load
duke
parents:
diff changeset
1504 if (Matcher::_regEncode[src_first] >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1505 emit_opcode(*cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
1506 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1507 emit_opcode(*cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
1508 emit_opcode(*cbuf, 0x11);
a61af66fc99e Initial load
duke
parents:
diff changeset
1509 encode_RegMem(*cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
1510 Matcher::_regEncode[src_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1511 RSP_enc, 0x4, 0, offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1512 false);
a61af66fc99e Initial load
duke
parents:
diff changeset
1513 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1514 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1515 st->print("movsd [rsp + #%d], %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1516 offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1517 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1518 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1519 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1520 return
a61af66fc99e Initial load
duke
parents:
diff changeset
1521 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
a61af66fc99e Initial load
duke
parents:
diff changeset
1522 ((Matcher::_regEncode[src_first] < 8)
a61af66fc99e Initial load
duke
parents:
diff changeset
1523 ? 5
a61af66fc99e Initial load
duke
parents:
diff changeset
1524 : 6); // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1525 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1526 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1527 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1528 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1529 int offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1530 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1531 emit_opcode(*cbuf, 0xF3);
a61af66fc99e Initial load
duke
parents:
diff changeset
1532 if (Matcher::_regEncode[src_first] >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1533 emit_opcode(*cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
1534 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1535 emit_opcode(*cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
1536 emit_opcode(*cbuf, 0x11);
a61af66fc99e Initial load
duke
parents:
diff changeset
1537 encode_RegMem(*cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
1538 Matcher::_regEncode[src_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1539 RSP_enc, 0x4, 0, offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1540 false);
a61af66fc99e Initial load
duke
parents:
diff changeset
1541 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1542 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1543 st->print("movss [rsp + #%d], %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1544 offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1545 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1546 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1547 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1548 return
a61af66fc99e Initial load
duke
parents:
diff changeset
1549 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
a61af66fc99e Initial load
duke
parents:
diff changeset
1550 ((Matcher::_regEncode[src_first] < 8)
a61af66fc99e Initial load
duke
parents:
diff changeset
1551 ? 5
a61af66fc99e Initial load
duke
parents:
diff changeset
1552 : 6); // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1553 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1554 } else if (dst_first_rc == rc_int) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1555 // xmm -> gpr
a61af66fc99e Initial load
duke
parents:
diff changeset
1556 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1557 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1558 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1559 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1560 emit_opcode(*cbuf, 0x66);
a61af66fc99e Initial load
duke
parents:
diff changeset
1561 if (Matcher::_regEncode[dst_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1562 if (Matcher::_regEncode[src_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1563 emit_opcode(*cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
1564 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1565 emit_opcode(*cbuf, Assembler::REX_WR); // attention!
a61af66fc99e Initial load
duke
parents:
diff changeset
1566 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1567 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1568 if (Matcher::_regEncode[src_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1569 emit_opcode(*cbuf, Assembler::REX_WB); // attention!
a61af66fc99e Initial load
duke
parents:
diff changeset
1570 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1571 emit_opcode(*cbuf, Assembler::REX_WRB);
a61af66fc99e Initial load
duke
parents:
diff changeset
1572 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1573 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1574 emit_opcode(*cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
1575 emit_opcode(*cbuf, 0x7E);
a61af66fc99e Initial load
duke
parents:
diff changeset
1576 emit_rm(*cbuf, 0x3,
1730
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1579
diff changeset
1577 Matcher::_regEncode[src_first] & 7,
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1579
diff changeset
1578 Matcher::_regEncode[dst_first] & 7);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1579 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1580 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1581 st->print("movdq %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1582 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1583 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1584 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1585 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1586 return 5; // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1587 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1588 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1589 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1590 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1591 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1592 emit_opcode(*cbuf, 0x66);
a61af66fc99e Initial load
duke
parents:
diff changeset
1593 if (Matcher::_regEncode[dst_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1594 if (Matcher::_regEncode[src_first] >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1595 emit_opcode(*cbuf, Assembler::REX_R); // attention!
a61af66fc99e Initial load
duke
parents:
diff changeset
1596 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1597 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1598 if (Matcher::_regEncode[src_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1599 emit_opcode(*cbuf, Assembler::REX_B); // attention!
a61af66fc99e Initial load
duke
parents:
diff changeset
1600 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1601 emit_opcode(*cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
1602 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1603 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1604 emit_opcode(*cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
1605 emit_opcode(*cbuf, 0x7E);
a61af66fc99e Initial load
duke
parents:
diff changeset
1606 emit_rm(*cbuf, 0x3,
1730
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1579
diff changeset
1607 Matcher::_regEncode[src_first] & 7,
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1579
diff changeset
1608 Matcher::_regEncode[dst_first] & 7);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1609 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1610 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1611 st->print("movdl %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1612 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1613 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1614 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1615 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1616 return
a61af66fc99e Initial load
duke
parents:
diff changeset
1617 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
a61af66fc99e Initial load
duke
parents:
diff changeset
1618 ? 4
a61af66fc99e Initial load
duke
parents:
diff changeset
1619 : 5; // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1620 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1621 } else if (dst_first_rc == rc_float) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1622 // xmm -> xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
1623 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1624 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1625 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1626 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1627 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
a61af66fc99e Initial load
duke
parents:
diff changeset
1628 if (Matcher::_regEncode[dst_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1629 if (Matcher::_regEncode[src_first] >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1630 emit_opcode(*cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
1631 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1632 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1633 if (Matcher::_regEncode[src_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1634 emit_opcode(*cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
1635 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1636 emit_opcode(*cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
1637 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1638 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1639 emit_opcode(*cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
1640 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
a61af66fc99e Initial load
duke
parents:
diff changeset
1641 emit_rm(*cbuf, 0x3,
a61af66fc99e Initial load
duke
parents:
diff changeset
1642 Matcher::_regEncode[dst_first] & 7,
a61af66fc99e Initial load
duke
parents:
diff changeset
1643 Matcher::_regEncode[src_first] & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1644 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1645 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1646 st->print("%s %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1647 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
a61af66fc99e Initial load
duke
parents:
diff changeset
1648 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1649 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1650 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1651 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1652 return
a61af66fc99e Initial load
duke
parents:
diff changeset
1653 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
a61af66fc99e Initial load
duke
parents:
diff changeset
1654 ? 4
a61af66fc99e Initial load
duke
parents:
diff changeset
1655 : 5; // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1656 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1657 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1658 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1659 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1660 if (cbuf) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1661 if (!UseXmmRegToRegMoveAll)
a61af66fc99e Initial load
duke
parents:
diff changeset
1662 emit_opcode(*cbuf, 0xF3);
a61af66fc99e Initial load
duke
parents:
diff changeset
1663 if (Matcher::_regEncode[dst_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1664 if (Matcher::_regEncode[src_first] >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1665 emit_opcode(*cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
1666 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1667 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1668 if (Matcher::_regEncode[src_first] < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1669 emit_opcode(*cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
1670 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1671 emit_opcode(*cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
1672 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1673 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1674 emit_opcode(*cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
1675 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
a61af66fc99e Initial load
duke
parents:
diff changeset
1676 emit_rm(*cbuf, 0x3,
a61af66fc99e Initial load
duke
parents:
diff changeset
1677 Matcher::_regEncode[dst_first] & 7,
a61af66fc99e Initial load
duke
parents:
diff changeset
1678 Matcher::_regEncode[src_first] & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1679 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1680 } else if (!do_size) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1681 st->print("%s %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1682 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
a61af66fc99e Initial load
duke
parents:
diff changeset
1683 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1684 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1685 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1686 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1687 return
a61af66fc99e Initial load
duke
parents:
diff changeset
1688 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
a61af66fc99e Initial load
duke
parents:
diff changeset
1689 ? (UseXmmRegToRegMoveAll ? 3 : 4)
a61af66fc99e Initial load
duke
parents:
diff changeset
1690 : (UseXmmRegToRegMoveAll ? 4 : 5); // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1691 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1692 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1693 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1694
a61af66fc99e Initial load
duke
parents:
diff changeset
1695 assert(0," foo ");
a61af66fc99e Initial load
duke
parents:
diff changeset
1696 Unimplemented();
a61af66fc99e Initial load
duke
parents:
diff changeset
1697
a61af66fc99e Initial load
duke
parents:
diff changeset
1698 return 0;
a61af66fc99e Initial load
duke
parents:
diff changeset
1699 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1700
a61af66fc99e Initial load
duke
parents:
diff changeset
1701 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1702 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1703 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1704 implementation(NULL, ra_, false, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1705 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1706 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1707
a61af66fc99e Initial load
duke
parents:
diff changeset
1708 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1709 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1710 implementation(&cbuf, ra_, false, NULL);
a61af66fc99e Initial load
duke
parents:
diff changeset
1711 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1712
a61af66fc99e Initial load
duke
parents:
diff changeset
1713 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1714 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1715 return implementation(NULL, ra_, true, NULL);
a61af66fc99e Initial load
duke
parents:
diff changeset
1716 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1717
a61af66fc99e Initial load
duke
parents:
diff changeset
1718 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1719 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1720 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1721 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1722 st->print("nop \t# %d bytes pad for loops and calls", _count);
a61af66fc99e Initial load
duke
parents:
diff changeset
1723 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1724 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1725
a61af66fc99e Initial load
duke
parents:
diff changeset
1726 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1727 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1728 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
1729 __ nop(_count);
a61af66fc99e Initial load
duke
parents:
diff changeset
1730 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1731
a61af66fc99e Initial load
duke
parents:
diff changeset
1732 uint MachNopNode::size(PhaseRegAlloc*) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1733 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1734 return _count;
a61af66fc99e Initial load
duke
parents:
diff changeset
1735 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1736
a61af66fc99e Initial load
duke
parents:
diff changeset
1737
a61af66fc99e Initial load
duke
parents:
diff changeset
1738 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1739 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1740 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1741 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1742 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
a61af66fc99e Initial load
duke
parents:
diff changeset
1743 int reg = ra_->get_reg_first(this);
a61af66fc99e Initial load
duke
parents:
diff changeset
1744 st->print("leaq %s, [rsp + #%d]\t# box lock",
a61af66fc99e Initial load
duke
parents:
diff changeset
1745 Matcher::regName[reg], offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1746 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1747 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1748
a61af66fc99e Initial load
duke
parents:
diff changeset
1749 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1750 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1751 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
a61af66fc99e Initial load
duke
parents:
diff changeset
1752 int reg = ra_->get_encode(this);
a61af66fc99e Initial load
duke
parents:
diff changeset
1753 if (offset >= 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1754 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
1755 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
a61af66fc99e Initial load
duke
parents:
diff changeset
1756 emit_rm(cbuf, 0x2, reg & 7, 0x04);
a61af66fc99e Initial load
duke
parents:
diff changeset
1757 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
1758 emit_d32(cbuf, offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1759 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1760 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
1761 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
a61af66fc99e Initial load
duke
parents:
diff changeset
1762 emit_rm(cbuf, 0x1, reg & 7, 0x04);
a61af66fc99e Initial load
duke
parents:
diff changeset
1763 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
1764 emit_d8(cbuf, offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1765 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1766 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1767
a61af66fc99e Initial load
duke
parents:
diff changeset
1768 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1769 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1770 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
a61af66fc99e Initial load
duke
parents:
diff changeset
1771 return (offset < 0x80) ? 5 : 8; // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1772 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1773
a61af66fc99e Initial load
duke
parents:
diff changeset
1774 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1775
a61af66fc99e Initial load
duke
parents:
diff changeset
1776 // emit call stub, compiled java to interpreter
a61af66fc99e Initial load
duke
parents:
diff changeset
1777 void emit_java_to_interp(CodeBuffer& cbuf)
a61af66fc99e Initial load
duke
parents:
diff changeset
1778 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1779 // Stub is fixed up when the corresponding call is converted from
a61af66fc99e Initial load
duke
parents:
diff changeset
1780 // calling compiled code to calling interpreted code.
a61af66fc99e Initial load
duke
parents:
diff changeset
1781 // movq rbx, 0
a61af66fc99e Initial load
duke
parents:
diff changeset
1782 // jmp -5 # to self
a61af66fc99e Initial load
duke
parents:
diff changeset
1783
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1784 address mark = cbuf.insts_mark(); // get mark within main instrs section
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1785
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1786 // Note that the code buffer's insts_mark is always relative to insts.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1787 // That's why we must use the macroassembler to generate a stub.
a61af66fc99e Initial load
duke
parents:
diff changeset
1788 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
1789
a61af66fc99e Initial load
duke
parents:
diff changeset
1790 address base =
a61af66fc99e Initial load
duke
parents:
diff changeset
1791 __ start_a_stub(Compile::MAX_stubs_size);
a61af66fc99e Initial load
duke
parents:
diff changeset
1792 if (base == NULL) return; // CodeBuffer::expand failed
a61af66fc99e Initial load
duke
parents:
diff changeset
1793 // static stub relocation stores the instruction address of the call
a61af66fc99e Initial load
duke
parents:
diff changeset
1794 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
a61af66fc99e Initial load
duke
parents:
diff changeset
1795 // static stub relocation also tags the methodOop in the code-stream.
a61af66fc99e Initial load
duke
parents:
diff changeset
1796 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
1797 // This is recognized as unresolved by relocs/nativeinst/ic code
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1798 __ jump(RuntimeAddress(__ pc()));
a61af66fc99e Initial load
duke
parents:
diff changeset
1799
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1800 // Update current stubs pointer and restore insts_end.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1801 __ end_a_stub();
a61af66fc99e Initial load
duke
parents:
diff changeset
1802 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1803
a61af66fc99e Initial load
duke
parents:
diff changeset
1804 // size of call stub, compiled java to interpretor
a61af66fc99e Initial load
duke
parents:
diff changeset
1805 uint size_java_to_interp()
a61af66fc99e Initial load
duke
parents:
diff changeset
1806 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1807 return 15; // movq (1+1+8); jmp (1+4)
a61af66fc99e Initial load
duke
parents:
diff changeset
1808 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1809
a61af66fc99e Initial load
duke
parents:
diff changeset
1810 // relocation entries for call stub, compiled java to interpretor
a61af66fc99e Initial load
duke
parents:
diff changeset
1811 uint reloc_java_to_interp()
a61af66fc99e Initial load
duke
parents:
diff changeset
1812 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1813 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
a61af66fc99e Initial load
duke
parents:
diff changeset
1814 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1815
a61af66fc99e Initial load
duke
parents:
diff changeset
1816 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1817 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1818 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1819 {
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1820 if (UseCompressedOops) {
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1821 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
1822 if (Universe::narrow_oop_shift() != 0) {
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1823 st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1");
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1824 }
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1825 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1826 } else {
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1827 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1828 "# Inline cache check");
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1829 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1830 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1831 st->print_cr("\tnop\t# nops to align entry point");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1832 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1833 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1834
a61af66fc99e Initial load
duke
parents:
diff changeset
1835 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1836 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1837 MacroAssembler masm(&cbuf);
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1838 uint insts_size = cbuf.insts_size();
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1839 if (UseCompressedOops) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1840 masm.load_klass(rscratch1, j_rarg0);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
1841 masm.cmpptr(rax, rscratch1);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1842 } else {
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
1843 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1844 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1845
a61af66fc99e Initial load
duke
parents:
diff changeset
1846 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
a61af66fc99e Initial load
duke
parents:
diff changeset
1847
a61af66fc99e Initial load
duke
parents:
diff changeset
1848 /* WARNING these NOPs are critical so that verified entry point is properly
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1849 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1850 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1851 if (OptoBreakpoint) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1852 // Leave space for int3
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1853 nops_cnt -= 1;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1854 }
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1855 nops_cnt &= 0x3; // Do not add nops if code is aligned.
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1856 if (nops_cnt > 0)
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1857 masm.nop(nops_cnt);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1858 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1859
a61af66fc99e Initial load
duke
parents:
diff changeset
1860 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1861 {
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1862 return MachNode::size(ra_); // too many variables; just compute it
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1863 // the hard way
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1864 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1865
a61af66fc99e Initial load
duke
parents:
diff changeset
1866
a61af66fc99e Initial load
duke
parents:
diff changeset
1867 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1868 uint size_exception_handler()
a61af66fc99e Initial load
duke
parents:
diff changeset
1869 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1870 // NativeCall instruction size is the same as NativeJump.
a61af66fc99e Initial load
duke
parents:
diff changeset
1871 // Note that this value is also credited (in output.cpp) to
a61af66fc99e Initial load
duke
parents:
diff changeset
1872 // the size of the code section.
a61af66fc99e Initial load
duke
parents:
diff changeset
1873 return NativeJump::instruction_size;
a61af66fc99e Initial load
duke
parents:
diff changeset
1874 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1875
a61af66fc99e Initial load
duke
parents:
diff changeset
1876 // Emit exception handler code.
a61af66fc99e Initial load
duke
parents:
diff changeset
1877 int emit_exception_handler(CodeBuffer& cbuf)
a61af66fc99e Initial load
duke
parents:
diff changeset
1878 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1879
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1880 // Note that the code buffer's insts_mark is always relative to insts.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1881 // That's why we must use the macroassembler to generate a handler.
a61af66fc99e Initial load
duke
parents:
diff changeset
1882 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
1883 address base =
a61af66fc99e Initial load
duke
parents:
diff changeset
1884 __ start_a_stub(size_exception_handler());
a61af66fc99e Initial load
duke
parents:
diff changeset
1885 if (base == NULL) return 0; // CodeBuffer::expand failed
a61af66fc99e Initial load
duke
parents:
diff changeset
1886 int offset = __ offset();
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1887 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1888 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
a61af66fc99e Initial load
duke
parents:
diff changeset
1889 __ end_a_stub();
a61af66fc99e Initial load
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parents:
diff changeset
1890 return offset;
a61af66fc99e Initial load
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parents:
diff changeset
1891 }
a61af66fc99e Initial load
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parents:
diff changeset
1892
a61af66fc99e Initial load
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parents:
diff changeset
1893 uint size_deopt_handler()
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parents:
diff changeset
1894 {
a61af66fc99e Initial load
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parents:
diff changeset
1895 // three 5 byte instructions
a61af66fc99e Initial load
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parents:
diff changeset
1896 return 15;
a61af66fc99e Initial load
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parents:
diff changeset
1897 }
a61af66fc99e Initial load
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parents:
diff changeset
1898
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parents:
diff changeset
1899 // Emit deopt handler code.
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parents:
diff changeset
1900 int emit_deopt_handler(CodeBuffer& cbuf)
a61af66fc99e Initial load
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parents:
diff changeset
1901 {
a61af66fc99e Initial load
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parents:
diff changeset
1902
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1903 // Note that the code buffer's insts_mark is always relative to insts.
0
a61af66fc99e Initial load
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parents:
diff changeset
1904 // That's why we must use the macroassembler to generate a handler.
a61af66fc99e Initial load
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parents:
diff changeset
1905 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
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parents:
diff changeset
1906 address base =
a61af66fc99e Initial load
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parents:
diff changeset
1907 __ start_a_stub(size_deopt_handler());
a61af66fc99e Initial load
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parents:
diff changeset
1908 if (base == NULL) return 0; // CodeBuffer::expand failed
a61af66fc99e Initial load
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parents:
diff changeset
1909 int offset = __ offset();
a61af66fc99e Initial load
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parents:
diff changeset
1910 address the_pc = (address) __ pc();
a61af66fc99e Initial load
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parents:
diff changeset
1911 Label next;
a61af66fc99e Initial load
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parents:
diff changeset
1912 // push a "the_pc" on the stack without destroying any registers
a61af66fc99e Initial load
duke
parents:
diff changeset
1913 // as they all may be live.
a61af66fc99e Initial load
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parents:
diff changeset
1914
a61af66fc99e Initial load
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parents:
diff changeset
1915 // push address of "next"
a61af66fc99e Initial load
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parents:
diff changeset
1916 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
a61af66fc99e Initial load
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parents:
diff changeset
1917 __ bind(next);
a61af66fc99e Initial load
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parents:
diff changeset
1918 // adjust it so it matches "the_pc"
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
1919 __ subptr(Address(rsp, 0), __ offset() - offset);
0
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parents:
diff changeset
1920 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
a61af66fc99e Initial load
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parents:
diff changeset
1921 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
a61af66fc99e Initial load
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parents:
diff changeset
1922 __ end_a_stub();
a61af66fc99e Initial load
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parents:
diff changeset
1923 return offset;
a61af66fc99e Initial load
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parents:
diff changeset
1924 }
a61af66fc99e Initial load
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parents:
diff changeset
1925
a61af66fc99e Initial load
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parents:
diff changeset
1926
775
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
1927 const bool Matcher::match_rule_supported(int opcode) {
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
1928 if (!has_match_rule(opcode))
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
1929 return false;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
1930
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
1931 return true; // Per default match rules are supported.
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
1932 }
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
1933
0
a61af66fc99e Initial load
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parents:
diff changeset
1934 int Matcher::regnum_to_fpu_offset(int regnum)
a61af66fc99e Initial load
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parents:
diff changeset
1935 {
a61af66fc99e Initial load
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parents:
diff changeset
1936 return regnum - 32; // The FP registers are in the second chunk
a61af66fc99e Initial load
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parents:
diff changeset
1937 }
a61af66fc99e Initial load
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parents:
diff changeset
1938
a61af66fc99e Initial load
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parents:
diff changeset
1939 // This is UltraSparc specific, true just means we have fast l2f conversion
a61af66fc99e Initial load
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parents:
diff changeset
1940 const bool Matcher::convL2FSupported(void) {
a61af66fc99e Initial load
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parents:
diff changeset
1941 return true;
a61af66fc99e Initial load
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parents:
diff changeset
1942 }
a61af66fc99e Initial load
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parents:
diff changeset
1943
a61af66fc99e Initial load
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parents:
diff changeset
1944 // Vector width in bytes
a61af66fc99e Initial load
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parents:
diff changeset
1945 const uint Matcher::vector_width_in_bytes(void) {
a61af66fc99e Initial load
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parents:
diff changeset
1946 return 8;
a61af66fc99e Initial load
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parents:
diff changeset
1947 }
a61af66fc99e Initial load
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parents:
diff changeset
1948
a61af66fc99e Initial load
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parents:
diff changeset
1949 // Vector ideal reg
a61af66fc99e Initial load
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parents:
diff changeset
1950 const uint Matcher::vector_ideal_reg(void) {
a61af66fc99e Initial load
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parents:
diff changeset
1951 return Op_RegD;
a61af66fc99e Initial load
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parents:
diff changeset
1952 }
a61af66fc99e Initial load
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parents:
diff changeset
1953
a61af66fc99e Initial load
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parents:
diff changeset
1954 // Is this branch offset short enough that a short branch can be used?
a61af66fc99e Initial load
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parents:
diff changeset
1955 //
a61af66fc99e Initial load
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parents:
diff changeset
1956 // NOTE: If the platform does not provide any short branch variants, then
a61af66fc99e Initial load
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parents:
diff changeset
1957 // this method should return false for offset 0.
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
1958 bool Matcher::is_short_branch_offset(int rule, int offset) {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
1959 // the short version of jmpConUCF2 contains multiple branches,
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
1960 // making the reach slightly less
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
1961 if (rule == jmpConUCF2_rule)
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
1962 return (-126 <= offset && offset <= 125);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
1963 return (-128 <= offset && offset <= 127);
0
a61af66fc99e Initial load
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parents:
diff changeset
1964 }
a61af66fc99e Initial load
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parents:
diff changeset
1965
a61af66fc99e Initial load
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parents:
diff changeset
1966 const bool Matcher::isSimpleConstant64(jlong value) {
a61af66fc99e Initial load
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parents:
diff changeset
1967 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
a61af66fc99e Initial load
duke
parents:
diff changeset
1968 //return value == (int) value; // Cf. storeImmL and immL32.
a61af66fc99e Initial load
duke
parents:
diff changeset
1969
a61af66fc99e Initial load
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parents:
diff changeset
1970 // Probably always true, even if a temp register is required.
a61af66fc99e Initial load
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parents:
diff changeset
1971 return true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1972 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1973
a61af66fc99e Initial load
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parents:
diff changeset
1974 // The ecx parameter to rep stosq for the ClearArray node is in words.
a61af66fc99e Initial load
duke
parents:
diff changeset
1975 const bool Matcher::init_array_count_is_in_bytes = false;
a61af66fc99e Initial load
duke
parents:
diff changeset
1976
a61af66fc99e Initial load
duke
parents:
diff changeset
1977 // Threshold size for cleararray.
a61af66fc99e Initial load
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parents:
diff changeset
1978 const int Matcher::init_array_short_size = 8 * BytesPerLong;
a61af66fc99e Initial load
duke
parents:
diff changeset
1979
a61af66fc99e Initial load
duke
parents:
diff changeset
1980 // Should the Matcher clone shifts on addressing modes, expecting them
a61af66fc99e Initial load
duke
parents:
diff changeset
1981 // to be subsumed into complex addressing expressions or compute them
a61af66fc99e Initial load
duke
parents:
diff changeset
1982 // into registers? True for Intel but false for most RISCs
a61af66fc99e Initial load
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parents:
diff changeset
1983 const bool Matcher::clone_shift_expressions = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1984
2401
7e88bdae86ec 7029017: Additional architecture support for c2 compiler
roland
parents: 2320
diff changeset
1985 // Do we need to mask the count passed to shift instructions or does
7e88bdae86ec 7029017: Additional architecture support for c2 compiler
roland
parents: 2320
diff changeset
1986 // the cpu only look at the lower 5/6 bits anyway?
7e88bdae86ec 7029017: Additional architecture support for c2 compiler
roland
parents: 2320
diff changeset
1987 const bool Matcher::need_masked_shift_count = false;
7e88bdae86ec 7029017: Additional architecture support for c2 compiler
roland
parents: 2320
diff changeset
1988
1575
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 1571
diff changeset
1989 bool Matcher::narrow_oop_use_complex_address() {
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 1571
diff changeset
1990 assert(UseCompressedOops, "only for compressed oops code");
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 1571
diff changeset
1991 return (LogMinObjAlignmentInBytes <= 3);
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 1571
diff changeset
1992 }
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 1571
diff changeset
1993
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1994 // Is it better to copy float constants, or load them directly from
a61af66fc99e Initial load
duke
parents:
diff changeset
1995 // memory? Intel can load a float constant from a direct address,
a61af66fc99e Initial load
duke
parents:
diff changeset
1996 // requiring no extra registers. Most RISCs will have to materialize
a61af66fc99e Initial load
duke
parents:
diff changeset
1997 // an address into a register first, so they would do better to copy
a61af66fc99e Initial load
duke
parents:
diff changeset
1998 // the constant from stack.
a61af66fc99e Initial load
duke
parents:
diff changeset
1999 const bool Matcher::rematerialize_float_constants = true; // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
2000
a61af66fc99e Initial load
duke
parents:
diff changeset
2001 // If CPU can load and store mis-aligned doubles directly then no
a61af66fc99e Initial load
duke
parents:
diff changeset
2002 // fixup is needed. Else we split the double into 2 integer pieces
a61af66fc99e Initial load
duke
parents:
diff changeset
2003 // and move it piece-by-piece. Only happens when passing doubles into
a61af66fc99e Initial load
duke
parents:
diff changeset
2004 // C code as the Java calling convention forces doubles to be aligned.
a61af66fc99e Initial load
duke
parents:
diff changeset
2005 const bool Matcher::misaligned_doubles_ok = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
2006
a61af66fc99e Initial load
duke
parents:
diff changeset
2007 // No-op on amd64
a61af66fc99e Initial load
duke
parents:
diff changeset
2008 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
a61af66fc99e Initial load
duke
parents:
diff changeset
2009
a61af66fc99e Initial load
duke
parents:
diff changeset
2010 // Advertise here if the CPU requires explicit rounding operations to
a61af66fc99e Initial load
duke
parents:
diff changeset
2011 // implement the UseStrictFP mode.
a61af66fc99e Initial load
duke
parents:
diff changeset
2012 const bool Matcher::strict_fp_requires_explicit_rounding = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
2013
1274
2883969d09e7 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents: 1137
diff changeset
2014 // Are floats conerted to double when stored to stack during deoptimization?
2883969d09e7 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents: 1137
diff changeset
2015 // On x64 it is stored without convertion so we can use normal access.
2883969d09e7 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents: 1137
diff changeset
2016 bool Matcher::float_in_double() { return false; }
2883969d09e7 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents: 1137
diff changeset
2017
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2018 // Do ints take an entire long register or just half?
a61af66fc99e Initial load
duke
parents:
diff changeset
2019 const bool Matcher::int_in_long = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
2020
a61af66fc99e Initial load
duke
parents:
diff changeset
2021 // Return whether or not this register is ever used as an argument.
a61af66fc99e Initial load
duke
parents:
diff changeset
2022 // This function is used on startup to build the trampoline stubs in
a61af66fc99e Initial load
duke
parents:
diff changeset
2023 // generateOptoStub. Registers not mentioned will be killed by the VM
a61af66fc99e Initial load
duke
parents:
diff changeset
2024 // call in the trampoline, and arguments in those registers not be
a61af66fc99e Initial load
duke
parents:
diff changeset
2025 // available to the callee.
a61af66fc99e Initial load
duke
parents:
diff changeset
2026 bool Matcher::can_be_java_arg(int reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
2027 {
a61af66fc99e Initial load
duke
parents:
diff changeset
2028 return
a61af66fc99e Initial load
duke
parents:
diff changeset
2029 reg == RDI_num || reg == RDI_H_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
2030 reg == RSI_num || reg == RSI_H_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
2031 reg == RDX_num || reg == RDX_H_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
2032 reg == RCX_num || reg == RCX_H_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
2033 reg == R8_num || reg == R8_H_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
2034 reg == R9_num || reg == R9_H_num ||
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2035 reg == R12_num || reg == R12_H_num ||
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2036 reg == XMM0_num || reg == XMM0_H_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
2037 reg == XMM1_num || reg == XMM1_H_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
2038 reg == XMM2_num || reg == XMM2_H_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
2039 reg == XMM3_num || reg == XMM3_H_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
2040 reg == XMM4_num || reg == XMM4_H_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
2041 reg == XMM5_num || reg == XMM5_H_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
2042 reg == XMM6_num || reg == XMM6_H_num ||
a61af66fc99e Initial load
duke
parents:
diff changeset
2043 reg == XMM7_num || reg == XMM7_H_num;
a61af66fc99e Initial load
duke
parents:
diff changeset
2044 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2045
a61af66fc99e Initial load
duke
parents:
diff changeset
2046 bool Matcher::is_spillable_arg(int reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
2047 {
a61af66fc99e Initial load
duke
parents:
diff changeset
2048 return can_be_java_arg(reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2049 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2050
1914
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
2051 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
2052 // In 64 bit mode a code which use multiply when
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
2053 // devisor is constant is faster than hardware
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
2054 // DIV instruction (it uses MulHiL).
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
2055 return false;
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
2056 }
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
2057
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2058 // Register for DIVI projection of divmodI
a61af66fc99e Initial load
duke
parents:
diff changeset
2059 RegMask Matcher::divI_proj_mask() {
a61af66fc99e Initial load
duke
parents:
diff changeset
2060 return INT_RAX_REG_mask;
a61af66fc99e Initial load
duke
parents:
diff changeset
2061 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2062
a61af66fc99e Initial load
duke
parents:
diff changeset
2063 // Register for MODI projection of divmodI
a61af66fc99e Initial load
duke
parents:
diff changeset
2064 RegMask Matcher::modI_proj_mask() {
a61af66fc99e Initial load
duke
parents:
diff changeset
2065 return INT_RDX_REG_mask;
a61af66fc99e Initial load
duke
parents:
diff changeset
2066 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2067
a61af66fc99e Initial load
duke
parents:
diff changeset
2068 // Register for DIVL projection of divmodL
a61af66fc99e Initial load
duke
parents:
diff changeset
2069 RegMask Matcher::divL_proj_mask() {
a61af66fc99e Initial load
duke
parents:
diff changeset
2070 return LONG_RAX_REG_mask;
a61af66fc99e Initial load
duke
parents:
diff changeset
2071 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2072
a61af66fc99e Initial load
duke
parents:
diff changeset
2073 // Register for MODL projection of divmodL
a61af66fc99e Initial load
duke
parents:
diff changeset
2074 RegMask Matcher::modL_proj_mask() {
a61af66fc99e Initial load
duke
parents:
diff changeset
2075 return LONG_RDX_REG_mask;
a61af66fc99e Initial load
duke
parents:
diff changeset
2076 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2077
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
2078 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
2079 return PTR_RBP_REG_mask;
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
2080 }
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
2081
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2082 static Address build_address(int b, int i, int s, int d) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2083 Register index = as_Register(i);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2084 Address::ScaleFactor scale = (Address::ScaleFactor)s;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2085 if (index == rsp) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2086 index = noreg;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2087 scale = Address::no_scale;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2088 }
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2089 Address addr(as_Register(b), index, scale, d);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2090 return addr;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2091 }
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2092
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2093 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2094
a61af66fc99e Initial load
duke
parents:
diff changeset
2095 //----------ENCODING BLOCK-----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
2096 // This block specifies the encoding classes used by the compiler to
a61af66fc99e Initial load
duke
parents:
diff changeset
2097 // output byte streams. Encoding classes are parameterized macros
a61af66fc99e Initial load
duke
parents:
diff changeset
2098 // used by Machine Instruction Nodes in order to generate the bit
a61af66fc99e Initial load
duke
parents:
diff changeset
2099 // encoding of the instruction. Operands specify their base encoding
a61af66fc99e Initial load
duke
parents:
diff changeset
2100 // interface with the interface keyword. There are currently
a61af66fc99e Initial load
duke
parents:
diff changeset
2101 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
a61af66fc99e Initial load
duke
parents:
diff changeset
2102 // COND_INTER. REG_INTER causes an operand to generate a function
a61af66fc99e Initial load
duke
parents:
diff changeset
2103 // which returns its register number when queried. CONST_INTER causes
a61af66fc99e Initial load
duke
parents:
diff changeset
2104 // an operand to generate a function which returns the value of the
a61af66fc99e Initial load
duke
parents:
diff changeset
2105 // constant when queried. MEMORY_INTER causes an operand to generate
a61af66fc99e Initial load
duke
parents:
diff changeset
2106 // four functions which return the Base Register, the Index Register,
a61af66fc99e Initial load
duke
parents:
diff changeset
2107 // the Scale Value, and the Offset Value of the operand when queried.
a61af66fc99e Initial load
duke
parents:
diff changeset
2108 // COND_INTER causes an operand to generate six functions which return
a61af66fc99e Initial load
duke
parents:
diff changeset
2109 // the encoding code (ie - encoding bits for the instruction)
a61af66fc99e Initial load
duke
parents:
diff changeset
2110 // associated with each basic boolean condition for a conditional
a61af66fc99e Initial load
duke
parents:
diff changeset
2111 // instruction.
a61af66fc99e Initial load
duke
parents:
diff changeset
2112 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2113 // Instructions specify two basic values for encoding. Again, a
a61af66fc99e Initial load
duke
parents:
diff changeset
2114 // function is available to check if the constant displacement is an
a61af66fc99e Initial load
duke
parents:
diff changeset
2115 // oop. They use the ins_encode keyword to specify their encoding
a61af66fc99e Initial load
duke
parents:
diff changeset
2116 // classes (which must be a sequence of enc_class names, and their
a61af66fc99e Initial load
duke
parents:
diff changeset
2117 // parameters, specified in the encoding block), and they use the
a61af66fc99e Initial load
duke
parents:
diff changeset
2118 // opcode keyword to specify, in order, their primary, secondary, and
a61af66fc99e Initial load
duke
parents:
diff changeset
2119 // tertiary opcode. Only the opcode sections which a particular
a61af66fc99e Initial load
duke
parents:
diff changeset
2120 // instruction needs for encoding need to be specified.
a61af66fc99e Initial load
duke
parents:
diff changeset
2121 encode %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2122 // Build emit functions for each basic byte or larger field in the
a61af66fc99e Initial load
duke
parents:
diff changeset
2123 // intel encoding scheme (opcode, rm, sib, immediate), and call them
a61af66fc99e Initial load
duke
parents:
diff changeset
2124 // from C++ code in the enc_class source block. Emit functions will
a61af66fc99e Initial load
duke
parents:
diff changeset
2125 // live in the main source block for now. In future, we can
a61af66fc99e Initial load
duke
parents:
diff changeset
2126 // generalize this by adding a syntax that specifies the sizes of
a61af66fc99e Initial load
duke
parents:
diff changeset
2127 // fields in an order, so that the adlc can build the emit functions
a61af66fc99e Initial load
duke
parents:
diff changeset
2128 // automagically
a61af66fc99e Initial load
duke
parents:
diff changeset
2129
a61af66fc99e Initial load
duke
parents:
diff changeset
2130 // Emit primary opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
2131 enc_class OpcP
a61af66fc99e Initial load
duke
parents:
diff changeset
2132 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2133 emit_opcode(cbuf, $primary);
a61af66fc99e Initial load
duke
parents:
diff changeset
2134 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2135
a61af66fc99e Initial load
duke
parents:
diff changeset
2136 // Emit secondary opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
2137 enc_class OpcS
a61af66fc99e Initial load
duke
parents:
diff changeset
2138 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2139 emit_opcode(cbuf, $secondary);
a61af66fc99e Initial load
duke
parents:
diff changeset
2140 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2141
a61af66fc99e Initial load
duke
parents:
diff changeset
2142 // Emit tertiary opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
2143 enc_class OpcT
a61af66fc99e Initial load
duke
parents:
diff changeset
2144 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2145 emit_opcode(cbuf, $tertiary);
a61af66fc99e Initial load
duke
parents:
diff changeset
2146 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2147
a61af66fc99e Initial load
duke
parents:
diff changeset
2148 // Emit opcode directly
a61af66fc99e Initial load
duke
parents:
diff changeset
2149 enc_class Opcode(immI d8)
a61af66fc99e Initial load
duke
parents:
diff changeset
2150 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2151 emit_opcode(cbuf, $d8$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
2152 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2153
a61af66fc99e Initial load
duke
parents:
diff changeset
2154 // Emit size prefix
a61af66fc99e Initial load
duke
parents:
diff changeset
2155 enc_class SizePrefix
a61af66fc99e Initial load
duke
parents:
diff changeset
2156 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2157 emit_opcode(cbuf, 0x66);
a61af66fc99e Initial load
duke
parents:
diff changeset
2158 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2159
a61af66fc99e Initial load
duke
parents:
diff changeset
2160 enc_class reg(rRegI reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
2161 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2162 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2163 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2164
a61af66fc99e Initial load
duke
parents:
diff changeset
2165 enc_class reg_reg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2166 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2167 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2168 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2169
a61af66fc99e Initial load
duke
parents:
diff changeset
2170 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2171 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2172 emit_opcode(cbuf, $opcode$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
2173 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2174 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2175
a61af66fc99e Initial load
duke
parents:
diff changeset
2176 enc_class cmpfp_fixup()
a61af66fc99e Initial load
duke
parents:
diff changeset
2177 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2178 // jnp,s exit
a61af66fc99e Initial load
duke
parents:
diff changeset
2179 emit_opcode(cbuf, 0x7B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2180 emit_d8(cbuf, 0x0A);
a61af66fc99e Initial load
duke
parents:
diff changeset
2181
a61af66fc99e Initial load
duke
parents:
diff changeset
2182 // pushfq
a61af66fc99e Initial load
duke
parents:
diff changeset
2183 emit_opcode(cbuf, 0x9C);
a61af66fc99e Initial load
duke
parents:
diff changeset
2184
a61af66fc99e Initial load
duke
parents:
diff changeset
2185 // andq $0xffffff2b, (%rsp)
a61af66fc99e Initial load
duke
parents:
diff changeset
2186 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2187 emit_opcode(cbuf, 0x81);
a61af66fc99e Initial load
duke
parents:
diff changeset
2188 emit_opcode(cbuf, 0x24);
a61af66fc99e Initial load
duke
parents:
diff changeset
2189 emit_opcode(cbuf, 0x24);
a61af66fc99e Initial load
duke
parents:
diff changeset
2190 emit_d32(cbuf, 0xffffff2b);
a61af66fc99e Initial load
duke
parents:
diff changeset
2191
a61af66fc99e Initial load
duke
parents:
diff changeset
2192 // popfq
a61af66fc99e Initial load
duke
parents:
diff changeset
2193 emit_opcode(cbuf, 0x9D);
a61af66fc99e Initial load
duke
parents:
diff changeset
2194
a61af66fc99e Initial load
duke
parents:
diff changeset
2195 // nop (target for branch to avoid branch to branch)
a61af66fc99e Initial load
duke
parents:
diff changeset
2196 emit_opcode(cbuf, 0x90);
a61af66fc99e Initial load
duke
parents:
diff changeset
2197 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2198
a61af66fc99e Initial load
duke
parents:
diff changeset
2199 enc_class cmpfp3(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
2200 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2201 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2202
a61af66fc99e Initial load
duke
parents:
diff changeset
2203 // movl $dst, -1
a61af66fc99e Initial load
duke
parents:
diff changeset
2204 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2205 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2206 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2207 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
a61af66fc99e Initial load
duke
parents:
diff changeset
2208 emit_d32(cbuf, -1);
a61af66fc99e Initial load
duke
parents:
diff changeset
2209
a61af66fc99e Initial load
duke
parents:
diff changeset
2210 // jp,s done
a61af66fc99e Initial load
duke
parents:
diff changeset
2211 emit_opcode(cbuf, 0x7A);
a61af66fc99e Initial load
duke
parents:
diff changeset
2212 emit_d8(cbuf, dstenc < 4 ? 0x08 : 0x0A);
a61af66fc99e Initial load
duke
parents:
diff changeset
2213
a61af66fc99e Initial load
duke
parents:
diff changeset
2214 // jb,s done
a61af66fc99e Initial load
duke
parents:
diff changeset
2215 emit_opcode(cbuf, 0x72);
a61af66fc99e Initial load
duke
parents:
diff changeset
2216 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
a61af66fc99e Initial load
duke
parents:
diff changeset
2217
a61af66fc99e Initial load
duke
parents:
diff changeset
2218 // setne $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2219 if (dstenc >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2220 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2221 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2222 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
2223 emit_opcode(cbuf, 0x95);
a61af66fc99e Initial load
duke
parents:
diff changeset
2224 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
a61af66fc99e Initial load
duke
parents:
diff changeset
2225
a61af66fc99e Initial load
duke
parents:
diff changeset
2226 // movzbl $dst, $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2227 if (dstenc >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2228 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2229 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2230 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
2231 emit_opcode(cbuf, 0xB6);
a61af66fc99e Initial load
duke
parents:
diff changeset
2232 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2233 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2234
a61af66fc99e Initial load
duke
parents:
diff changeset
2235 enc_class cdql_enc(no_rax_rdx_RegI div)
a61af66fc99e Initial load
duke
parents:
diff changeset
2236 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2237 // Full implementation of Java idiv and irem; checks for
a61af66fc99e Initial load
duke
parents:
diff changeset
2238 // special case as described in JVM spec., p.243 & p.271.
a61af66fc99e Initial load
duke
parents:
diff changeset
2239 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2240 // normal case special case
a61af66fc99e Initial load
duke
parents:
diff changeset
2241 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2242 // input : rax: dividend min_int
a61af66fc99e Initial load
duke
parents:
diff changeset
2243 // reg: divisor -1
a61af66fc99e Initial load
duke
parents:
diff changeset
2244 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2245 // output: rax: quotient (= rax idiv reg) min_int
a61af66fc99e Initial load
duke
parents:
diff changeset
2246 // rdx: remainder (= rax irem reg) 0
a61af66fc99e Initial load
duke
parents:
diff changeset
2247 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2248 // Code sequnce:
a61af66fc99e Initial load
duke
parents:
diff changeset
2249 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2250 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
a61af66fc99e Initial load
duke
parents:
diff changeset
2251 // 5: 75 07/08 jne e <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
2252 // 7: 33 d2 xor %edx,%edx
a61af66fc99e Initial load
duke
parents:
diff changeset
2253 // [div >= 8 -> offset + 1]
a61af66fc99e Initial load
duke
parents:
diff changeset
2254 // [REX_B]
a61af66fc99e Initial load
duke
parents:
diff changeset
2255 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
a61af66fc99e Initial load
duke
parents:
diff changeset
2256 // c: 74 03/04 je 11 <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
2257 // 000000000000000e <normal>:
a61af66fc99e Initial load
duke
parents:
diff changeset
2258 // e: 99 cltd
a61af66fc99e Initial load
duke
parents:
diff changeset
2259 // [div >= 8 -> offset + 1]
a61af66fc99e Initial load
duke
parents:
diff changeset
2260 // [REX_B]
a61af66fc99e Initial load
duke
parents:
diff changeset
2261 // f: f7 f9 idiv $div
a61af66fc99e Initial load
duke
parents:
diff changeset
2262 // 0000000000000011 <done>:
a61af66fc99e Initial load
duke
parents:
diff changeset
2263
a61af66fc99e Initial load
duke
parents:
diff changeset
2264 // cmp $0x80000000,%eax
a61af66fc99e Initial load
duke
parents:
diff changeset
2265 emit_opcode(cbuf, 0x3d);
a61af66fc99e Initial load
duke
parents:
diff changeset
2266 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
2267 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
2268 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
2269 emit_d8(cbuf, 0x80);
a61af66fc99e Initial load
duke
parents:
diff changeset
2270
a61af66fc99e Initial load
duke
parents:
diff changeset
2271 // jne e <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
2272 emit_opcode(cbuf, 0x75);
a61af66fc99e Initial load
duke
parents:
diff changeset
2273 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
a61af66fc99e Initial load
duke
parents:
diff changeset
2274
a61af66fc99e Initial load
duke
parents:
diff changeset
2275 // xor %edx,%edx
a61af66fc99e Initial load
duke
parents:
diff changeset
2276 emit_opcode(cbuf, 0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
2277 emit_d8(cbuf, 0xD2);
a61af66fc99e Initial load
duke
parents:
diff changeset
2278
a61af66fc99e Initial load
duke
parents:
diff changeset
2279 // cmp $0xffffffffffffffff,%ecx
a61af66fc99e Initial load
duke
parents:
diff changeset
2280 if ($div$$reg >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2281 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2282 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2283 emit_opcode(cbuf, 0x83);
a61af66fc99e Initial load
duke
parents:
diff changeset
2284 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2285 emit_d8(cbuf, 0xFF);
a61af66fc99e Initial load
duke
parents:
diff changeset
2286
a61af66fc99e Initial load
duke
parents:
diff changeset
2287 // je 11 <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
2288 emit_opcode(cbuf, 0x74);
a61af66fc99e Initial load
duke
parents:
diff changeset
2289 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
a61af66fc99e Initial load
duke
parents:
diff changeset
2290
a61af66fc99e Initial load
duke
parents:
diff changeset
2291 // <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
2292 // cltd
a61af66fc99e Initial load
duke
parents:
diff changeset
2293 emit_opcode(cbuf, 0x99);
a61af66fc99e Initial load
duke
parents:
diff changeset
2294
a61af66fc99e Initial load
duke
parents:
diff changeset
2295 // idivl (note: must be emitted by the user of this rule)
a61af66fc99e Initial load
duke
parents:
diff changeset
2296 // <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
2297 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2298
a61af66fc99e Initial load
duke
parents:
diff changeset
2299 enc_class cdqq_enc(no_rax_rdx_RegL div)
a61af66fc99e Initial load
duke
parents:
diff changeset
2300 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2301 // Full implementation of Java ldiv and lrem; checks for
a61af66fc99e Initial load
duke
parents:
diff changeset
2302 // special case as described in JVM spec., p.243 & p.271.
a61af66fc99e Initial load
duke
parents:
diff changeset
2303 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2304 // normal case special case
a61af66fc99e Initial load
duke
parents:
diff changeset
2305 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2306 // input : rax: dividend min_long
a61af66fc99e Initial load
duke
parents:
diff changeset
2307 // reg: divisor -1
a61af66fc99e Initial load
duke
parents:
diff changeset
2308 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2309 // output: rax: quotient (= rax idiv reg) min_long
a61af66fc99e Initial load
duke
parents:
diff changeset
2310 // rdx: remainder (= rax irem reg) 0
a61af66fc99e Initial load
duke
parents:
diff changeset
2311 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2312 // Code sequnce:
a61af66fc99e Initial load
duke
parents:
diff changeset
2313 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2314 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
a61af66fc99e Initial load
duke
parents:
diff changeset
2315 // 7: 00 00 80
a61af66fc99e Initial load
duke
parents:
diff changeset
2316 // a: 48 39 d0 cmp %rdx,%rax
a61af66fc99e Initial load
duke
parents:
diff changeset
2317 // d: 75 08 jne 17 <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
2318 // f: 33 d2 xor %edx,%edx
a61af66fc99e Initial load
duke
parents:
diff changeset
2319 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
a61af66fc99e Initial load
duke
parents:
diff changeset
2320 // 15: 74 05 je 1c <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
2321 // 0000000000000017 <normal>:
a61af66fc99e Initial load
duke
parents:
diff changeset
2322 // 17: 48 99 cqto
a61af66fc99e Initial load
duke
parents:
diff changeset
2323 // 19: 48 f7 f9 idiv $div
a61af66fc99e Initial load
duke
parents:
diff changeset
2324 // 000000000000001c <done>:
a61af66fc99e Initial load
duke
parents:
diff changeset
2325
a61af66fc99e Initial load
duke
parents:
diff changeset
2326 // mov $0x8000000000000000,%rdx
a61af66fc99e Initial load
duke
parents:
diff changeset
2327 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2328 emit_opcode(cbuf, 0xBA);
a61af66fc99e Initial load
duke
parents:
diff changeset
2329 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
2330 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
2331 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
2332 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
2333 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
2334 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
2335 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
2336 emit_d8(cbuf, 0x80);
a61af66fc99e Initial load
duke
parents:
diff changeset
2337
a61af66fc99e Initial load
duke
parents:
diff changeset
2338 // cmp %rdx,%rax
a61af66fc99e Initial load
duke
parents:
diff changeset
2339 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2340 emit_opcode(cbuf, 0x39);
a61af66fc99e Initial load
duke
parents:
diff changeset
2341 emit_d8(cbuf, 0xD0);
a61af66fc99e Initial load
duke
parents:
diff changeset
2342
a61af66fc99e Initial load
duke
parents:
diff changeset
2343 // jne 17 <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
2344 emit_opcode(cbuf, 0x75);
a61af66fc99e Initial load
duke
parents:
diff changeset
2345 emit_d8(cbuf, 0x08);
a61af66fc99e Initial load
duke
parents:
diff changeset
2346
a61af66fc99e Initial load
duke
parents:
diff changeset
2347 // xor %edx,%edx
a61af66fc99e Initial load
duke
parents:
diff changeset
2348 emit_opcode(cbuf, 0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
2349 emit_d8(cbuf, 0xD2);
a61af66fc99e Initial load
duke
parents:
diff changeset
2350
a61af66fc99e Initial load
duke
parents:
diff changeset
2351 // cmp $0xffffffffffffffff,$div
a61af66fc99e Initial load
duke
parents:
diff changeset
2352 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2353 emit_opcode(cbuf, 0x83);
a61af66fc99e Initial load
duke
parents:
diff changeset
2354 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2355 emit_d8(cbuf, 0xFF);
a61af66fc99e Initial load
duke
parents:
diff changeset
2356
a61af66fc99e Initial load
duke
parents:
diff changeset
2357 // je 1e <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
2358 emit_opcode(cbuf, 0x74);
a61af66fc99e Initial load
duke
parents:
diff changeset
2359 emit_d8(cbuf, 0x05);
a61af66fc99e Initial load
duke
parents:
diff changeset
2360
a61af66fc99e Initial load
duke
parents:
diff changeset
2361 // <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
2362 // cqto
a61af66fc99e Initial load
duke
parents:
diff changeset
2363 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2364 emit_opcode(cbuf, 0x99);
a61af66fc99e Initial load
duke
parents:
diff changeset
2365
a61af66fc99e Initial load
duke
parents:
diff changeset
2366 // idivq (note: must be emitted by the user of this rule)
a61af66fc99e Initial load
duke
parents:
diff changeset
2367 // <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
2368 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2369
a61af66fc99e Initial load
duke
parents:
diff changeset
2370 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
a61af66fc99e Initial load
duke
parents:
diff changeset
2371 enc_class OpcSE(immI imm)
a61af66fc99e Initial load
duke
parents:
diff changeset
2372 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2373 // Emit primary opcode and set sign-extend bit
a61af66fc99e Initial load
duke
parents:
diff changeset
2374 // Check for 8-bit immediate, and set sign extend bit in opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
2375 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2376 emit_opcode(cbuf, $primary | 0x02);
a61af66fc99e Initial load
duke
parents:
diff changeset
2377 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2378 // 32-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
2379 emit_opcode(cbuf, $primary);
a61af66fc99e Initial load
duke
parents:
diff changeset
2380 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2381 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2382
a61af66fc99e Initial load
duke
parents:
diff changeset
2383 enc_class OpcSErm(rRegI dst, immI imm)
a61af66fc99e Initial load
duke
parents:
diff changeset
2384 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2385 // OpcSEr/m
a61af66fc99e Initial load
duke
parents:
diff changeset
2386 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2387 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2388 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2389 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2390 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2391 // Emit primary opcode and set sign-extend bit
a61af66fc99e Initial load
duke
parents:
diff changeset
2392 // Check for 8-bit immediate, and set sign extend bit in opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
2393 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2394 emit_opcode(cbuf, $primary | 0x02);
a61af66fc99e Initial load
duke
parents:
diff changeset
2395 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2396 // 32-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
2397 emit_opcode(cbuf, $primary);
a61af66fc99e Initial load
duke
parents:
diff changeset
2398 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2399 // Emit r/m byte with secondary opcode, after primary opcode.
a61af66fc99e Initial load
duke
parents:
diff changeset
2400 emit_rm(cbuf, 0x3, $secondary, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2401 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2402
a61af66fc99e Initial load
duke
parents:
diff changeset
2403 enc_class OpcSErm_wide(rRegL dst, immI imm)
a61af66fc99e Initial load
duke
parents:
diff changeset
2404 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2405 // OpcSEr/m
a61af66fc99e Initial load
duke
parents:
diff changeset
2406 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2407 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2408 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2409 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2410 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2411 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2412 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2413 // Emit primary opcode and set sign-extend bit
a61af66fc99e Initial load
duke
parents:
diff changeset
2414 // Check for 8-bit immediate, and set sign extend bit in opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
2415 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2416 emit_opcode(cbuf, $primary | 0x02);
a61af66fc99e Initial load
duke
parents:
diff changeset
2417 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2418 // 32-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
2419 emit_opcode(cbuf, $primary);
a61af66fc99e Initial load
duke
parents:
diff changeset
2420 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2421 // Emit r/m byte with secondary opcode, after primary opcode.
a61af66fc99e Initial load
duke
parents:
diff changeset
2422 emit_rm(cbuf, 0x3, $secondary, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2423 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2424
a61af66fc99e Initial load
duke
parents:
diff changeset
2425 enc_class Con8or32(immI imm)
a61af66fc99e Initial load
duke
parents:
diff changeset
2426 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2427 // Check for 8-bit immediate, and set sign extend bit in opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
2428 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2429 $$$emit8$imm$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2430 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2431 // 32-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
2432 $$$emit32$imm$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2433 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2434 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2435
a61af66fc99e Initial load
duke
parents:
diff changeset
2436 enc_class Lbl(label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
2437 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2438 // JMP, CALL
a61af66fc99e Initial load
duke
parents:
diff changeset
2439 Label* l = $labl$$label;
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2440 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2441 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2442
a61af66fc99e Initial load
duke
parents:
diff changeset
2443 enc_class LblShort(label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
2444 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2445 // JMP, CALL
a61af66fc99e Initial load
duke
parents:
diff changeset
2446 Label* l = $labl$$label;
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2447 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2448 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
a61af66fc99e Initial load
duke
parents:
diff changeset
2449 emit_d8(cbuf, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
2450 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2451
a61af66fc99e Initial load
duke
parents:
diff changeset
2452 enc_class opc2_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
2453 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2454 // BSWAP
a61af66fc99e Initial load
duke
parents:
diff changeset
2455 emit_cc(cbuf, $secondary, $dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2456 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2457
a61af66fc99e Initial load
duke
parents:
diff changeset
2458 enc_class opc3_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
2459 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2460 // BSWAP
a61af66fc99e Initial load
duke
parents:
diff changeset
2461 emit_cc(cbuf, $tertiary, $dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2462 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2463
a61af66fc99e Initial load
duke
parents:
diff changeset
2464 enc_class reg_opc(rRegI div)
a61af66fc99e Initial load
duke
parents:
diff changeset
2465 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2466 // INC, DEC, IDIV, IMOD, JMP indirect, ...
a61af66fc99e Initial load
duke
parents:
diff changeset
2467 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2468 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2469
a61af66fc99e Initial load
duke
parents:
diff changeset
2470 enc_class Jcc(cmpOp cop, label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
2471 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2472 // JCC
a61af66fc99e Initial load
duke
parents:
diff changeset
2473 Label* l = $labl$$label;
a61af66fc99e Initial load
duke
parents:
diff changeset
2474 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2475 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2476 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2477 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2478
a61af66fc99e Initial load
duke
parents:
diff changeset
2479 enc_class JccShort (cmpOp cop, label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
2480 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2481 // JCC
a61af66fc99e Initial load
duke
parents:
diff changeset
2482 Label *l = $labl$$label;
a61af66fc99e Initial load
duke
parents:
diff changeset
2483 emit_cc(cbuf, $primary, $cop$$cmpcode);
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2484 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2485 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
a61af66fc99e Initial load
duke
parents:
diff changeset
2486 emit_d8(cbuf, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
2487 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2488
a61af66fc99e Initial load
duke
parents:
diff changeset
2489 enc_class enc_cmov(cmpOp cop)
a61af66fc99e Initial load
duke
parents:
diff changeset
2490 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2491 // CMOV
a61af66fc99e Initial load
duke
parents:
diff changeset
2492 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2493 emit_cc(cbuf, $secondary, $cop$$cmpcode);
a61af66fc99e Initial load
duke
parents:
diff changeset
2494 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2495
a61af66fc99e Initial load
duke
parents:
diff changeset
2496 enc_class enc_cmovf_branch(cmpOp cop, regF dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2497 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2498 // Invert sense of branch from sense of cmov
a61af66fc99e Initial load
duke
parents:
diff changeset
2499 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
a61af66fc99e Initial load
duke
parents:
diff changeset
2500 emit_d8(cbuf, ($dst$$reg < 8 && $src$$reg < 8)
a61af66fc99e Initial load
duke
parents:
diff changeset
2501 ? (UseXmmRegToRegMoveAll ? 3 : 4)
a61af66fc99e Initial load
duke
parents:
diff changeset
2502 : (UseXmmRegToRegMoveAll ? 4 : 5) ); // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
2503 // UseXmmRegToRegMoveAll ? movaps(dst, src) : movss(dst, src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2504 if (!UseXmmRegToRegMoveAll) emit_opcode(cbuf, 0xF3);
a61af66fc99e Initial load
duke
parents:
diff changeset
2505 if ($dst$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2506 if ($src$$reg >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2507 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2508 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2509 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2510 if ($src$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2511 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
2512 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2513 emit_opcode(cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2514 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2515 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2516 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
2517 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
a61af66fc99e Initial load
duke
parents:
diff changeset
2518 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2519 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2520
a61af66fc99e Initial load
duke
parents:
diff changeset
2521 enc_class enc_cmovd_branch(cmpOp cop, regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2522 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2523 // Invert sense of branch from sense of cmov
a61af66fc99e Initial load
duke
parents:
diff changeset
2524 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
a61af66fc99e Initial load
duke
parents:
diff changeset
2525 emit_d8(cbuf, $dst$$reg < 8 && $src$$reg < 8 ? 4 : 5); // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
2526
a61af66fc99e Initial load
duke
parents:
diff changeset
2527 // UseXmmRegToRegMoveAll ? movapd(dst, src) : movsd(dst, src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2528 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
a61af66fc99e Initial load
duke
parents:
diff changeset
2529 if ($dst$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2530 if ($src$$reg >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2531 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2532 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2533 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2534 if ($src$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2535 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
2536 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2537 emit_opcode(cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2538 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2539 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2540 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
2541 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
a61af66fc99e Initial load
duke
parents:
diff changeset
2542 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2543 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2544
a61af66fc99e Initial load
duke
parents:
diff changeset
2545 enc_class enc_PartialSubtypeCheck()
a61af66fc99e Initial load
duke
parents:
diff changeset
2546 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2547 Register Rrdi = as_Register(RDI_enc); // result register
a61af66fc99e Initial load
duke
parents:
diff changeset
2548 Register Rrax = as_Register(RAX_enc); // super class
a61af66fc99e Initial load
duke
parents:
diff changeset
2549 Register Rrcx = as_Register(RCX_enc); // killed
a61af66fc99e Initial load
duke
parents:
diff changeset
2550 Register Rrsi = as_Register(RSI_enc); // sub class
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 643
diff changeset
2551 Label miss;
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 643
diff changeset
2552 const bool set_cond_codes = true;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2553
a61af66fc99e Initial load
duke
parents:
diff changeset
2554 MacroAssembler _masm(&cbuf);
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 643
diff changeset
2555 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 643
diff changeset
2556 NULL, &miss,
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 643
diff changeset
2557 /*set_cond_codes:*/ true);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2558 if ($primary) {
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2559 __ xorptr(Rrdi, Rrdi);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2560 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2561 __ bind(miss);
a61af66fc99e Initial load
duke
parents:
diff changeset
2562 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2563
a61af66fc99e Initial load
duke
parents:
diff changeset
2564 enc_class Java_To_Interpreter(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
2565 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2566 // CALL Java_To_Interpreter
a61af66fc99e Initial load
duke
parents:
diff changeset
2567 // This is the instruction starting address for relocation info.
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2568 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2569 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2570 // CALL directly to the runtime
a61af66fc99e Initial load
duke
parents:
diff changeset
2571 emit_d32_reloc(cbuf,
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2572 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2573 runtime_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
2574 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2575 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2576
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
2577 enc_class preserve_SP %{
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2578 debug_only(int off0 = cbuf.insts_size());
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
2579 MacroAssembler _masm(&cbuf);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
2580 // RBP is preserved across all calls, even compiled calls.
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
2581 // Use it to preserve RSP in places where the callee might change the SP.
1567
110501f54a99 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 1396
diff changeset
2582 __ movptr(rbp_mh_SP_save, rsp);
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2583 debug_only(int off1 = cbuf.insts_size());
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
2584 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
2585 %}
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
2586
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
2587 enc_class restore_SP %{
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
2588 MacroAssembler _masm(&cbuf);
1567
110501f54a99 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 1396
diff changeset
2589 __ movptr(rsp, rbp_mh_SP_save);
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
2590 %}
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
2591
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2592 enc_class Java_Static_Call(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
2593 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2594 // JAVA STATIC CALL
a61af66fc99e Initial load
duke
parents:
diff changeset
2595 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
a61af66fc99e Initial load
duke
parents:
diff changeset
2596 // determine who we intended to call.
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2597 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2598 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2599
a61af66fc99e Initial load
duke
parents:
diff changeset
2600 if (!_method) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2601 emit_d32_reloc(cbuf,
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2602 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2603 runtime_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
2604 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2605 } else if (_optimized_virtual) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2606 emit_d32_reloc(cbuf,
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2607 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2608 opt_virtual_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
2609 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2610 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2611 emit_d32_reloc(cbuf,
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2612 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2613 static_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
2614 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2615 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2616 if (_method) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2617 // Emit stub for static call
a61af66fc99e Initial load
duke
parents:
diff changeset
2618 emit_java_to_interp(cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2619 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2620 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2621
a61af66fc99e Initial load
duke
parents:
diff changeset
2622 enc_class Java_Dynamic_Call(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
2623 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2624 // JAVA DYNAMIC CALL
a61af66fc99e Initial load
duke
parents:
diff changeset
2625 // !!!!!
a61af66fc99e Initial load
duke
parents:
diff changeset
2626 // Generate "movq rax, -1", placeholder instruction to load oop-info
a61af66fc99e Initial load
duke
parents:
diff changeset
2627 // emit_call_dynamic_prologue( cbuf );
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2628 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2629
a61af66fc99e Initial load
duke
parents:
diff changeset
2630 // movq rax, -1
a61af66fc99e Initial load
duke
parents:
diff changeset
2631 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2632 emit_opcode(cbuf, 0xB8 | RAX_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2633 emit_d64_reloc(cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
2634 (int64_t) Universe::non_oop_word(),
a61af66fc99e Initial load
duke
parents:
diff changeset
2635 oop_Relocation::spec_for_immediate(), RELOC_IMM64);
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2636 address virtual_call_oop_addr = cbuf.insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2637 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
a61af66fc99e Initial load
duke
parents:
diff changeset
2638 // who we intended to call.
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2639 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2640 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2641 emit_d32_reloc(cbuf,
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2642 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2643 virtual_call_Relocation::spec(virtual_call_oop_addr),
a61af66fc99e Initial load
duke
parents:
diff changeset
2644 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2645 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2646
a61af66fc99e Initial load
duke
parents:
diff changeset
2647 enc_class Java_Compiled_Call(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
2648 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2649 // JAVA COMPILED CALL
a61af66fc99e Initial load
duke
parents:
diff changeset
2650 int disp = in_bytes(methodOopDesc:: from_compiled_offset());
a61af66fc99e Initial load
duke
parents:
diff changeset
2651
a61af66fc99e Initial load
duke
parents:
diff changeset
2652 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
a61af66fc99e Initial load
duke
parents:
diff changeset
2653 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
a61af66fc99e Initial load
duke
parents:
diff changeset
2654
a61af66fc99e Initial load
duke
parents:
diff changeset
2655 // callq *disp(%rax)
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2656 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2657 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2658 if (disp < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2659 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
2660 emit_d8(cbuf, disp); // Displacement
a61af66fc99e Initial load
duke
parents:
diff changeset
2661 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2662 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
2663 emit_d32(cbuf, disp); // Displacement
a61af66fc99e Initial load
duke
parents:
diff changeset
2664 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2665 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2666
a61af66fc99e Initial load
duke
parents:
diff changeset
2667 enc_class reg_opc_imm(rRegI dst, immI8 shift)
a61af66fc99e Initial load
duke
parents:
diff changeset
2668 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2669 // SAL, SAR, SHR
a61af66fc99e Initial load
duke
parents:
diff changeset
2670 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2671 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2672 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2673 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2674 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2675 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2676 emit_rm(cbuf, 0x3, $secondary, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2677 $$$emit8$shift$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2678 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2679
a61af66fc99e Initial load
duke
parents:
diff changeset
2680 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
a61af66fc99e Initial load
duke
parents:
diff changeset
2681 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2682 // SAL, SAR, SHR
a61af66fc99e Initial load
duke
parents:
diff changeset
2683 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2684 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2685 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2686 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2687 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2688 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2689 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2690 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2691 emit_rm(cbuf, 0x3, $secondary, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2692 $$$emit8$shift$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2693 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2694
a61af66fc99e Initial load
duke
parents:
diff changeset
2695 enc_class load_immI(rRegI dst, immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2696 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2697 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2698 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2699 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2700 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2701 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2702 emit_opcode(cbuf, 0xB8 | dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2703 $$$emit32$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2704 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2705
a61af66fc99e Initial load
duke
parents:
diff changeset
2706 enc_class load_immL(rRegL dst, immL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2707 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2708 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2709 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2710 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2711 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2712 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2713 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2714 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2715 emit_opcode(cbuf, 0xB8 | dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2716 emit_d64(cbuf, $src$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
2717 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2718
a61af66fc99e Initial load
duke
parents:
diff changeset
2719 enc_class load_immUL32(rRegL dst, immUL32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2720 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2721 // same as load_immI, but this time we care about zeroes in the high word
a61af66fc99e Initial load
duke
parents:
diff changeset
2722 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2723 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2724 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2725 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2726 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2727 emit_opcode(cbuf, 0xB8 | dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2728 $$$emit32$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2729 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2730
a61af66fc99e Initial load
duke
parents:
diff changeset
2731 enc_class load_immL32(rRegL dst, immL32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2732 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2733 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2734 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2735 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2736 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2737 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2738 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2739 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2740 emit_opcode(cbuf, 0xC7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2741 emit_rm(cbuf, 0x03, 0x00, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2742 $$$emit32$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2743 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2744
a61af66fc99e Initial load
duke
parents:
diff changeset
2745 enc_class load_immP31(rRegP dst, immP32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2746 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2747 // same as load_immI, but this time we care about zeroes in the high word
a61af66fc99e Initial load
duke
parents:
diff changeset
2748 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2749 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2750 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2751 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2752 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2753 emit_opcode(cbuf, 0xB8 | dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2754 $$$emit32$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2755 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2756
a61af66fc99e Initial load
duke
parents:
diff changeset
2757 enc_class load_immP(rRegP dst, immP src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2758 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2759 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2760 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2761 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2762 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2763 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2764 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2765 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2766 emit_opcode(cbuf, 0xB8 | dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2767 // This next line should be generated from ADLC
a61af66fc99e Initial load
duke
parents:
diff changeset
2768 if ($src->constant_is_oop()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2769 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);
a61af66fc99e Initial load
duke
parents:
diff changeset
2770 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2771 emit_d64(cbuf, $src$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
2772 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2773 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2774
a61af66fc99e Initial load
duke
parents:
diff changeset
2775 // Encode a reg-reg copy. If it is useless, then empty encoding.
a61af66fc99e Initial load
duke
parents:
diff changeset
2776 enc_class enc_copy(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2777 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2778 encode_copy(cbuf, $dst$$reg, $src$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2779 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2780
a61af66fc99e Initial load
duke
parents:
diff changeset
2781 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
a61af66fc99e Initial load
duke
parents:
diff changeset
2782 enc_class enc_CopyXD( RegD dst, RegD src ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2783 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
2784 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2785
a61af66fc99e Initial load
duke
parents:
diff changeset
2786 enc_class enc_copy_always(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2787 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2788 int srcenc = $src$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2789 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2790
a61af66fc99e Initial load
duke
parents:
diff changeset
2791 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2792 if (srcenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2793 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2794 srcenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2795 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2796 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2797 if (srcenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2798 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
2799 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2800 emit_opcode(cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2801 srcenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2802 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2803 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2804 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2805
a61af66fc99e Initial load
duke
parents:
diff changeset
2806 emit_opcode(cbuf, 0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2807 emit_rm(cbuf, 0x3, dstenc, srcenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2808 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2809
a61af66fc99e Initial load
duke
parents:
diff changeset
2810 enc_class enc_copy_wide(rRegL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2811 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2812 int srcenc = $src$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2813 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2814
a61af66fc99e Initial load
duke
parents:
diff changeset
2815 if (dstenc != srcenc) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2816 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2817 if (srcenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2818 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2819 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2820 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2821 srcenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2822 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2823 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2824 if (srcenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2825 emit_opcode(cbuf, Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
2826 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2827 emit_opcode(cbuf, Assembler::REX_WRB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2828 srcenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2829 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2830 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2831 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2832 emit_opcode(cbuf, 0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2833 emit_rm(cbuf, 0x3, dstenc, srcenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2834 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2835 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2836
a61af66fc99e Initial load
duke
parents:
diff changeset
2837 enc_class Con32(immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2838 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2839 // Output immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
2840 $$$emit32$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2841 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2842
a61af66fc99e Initial load
duke
parents:
diff changeset
2843 enc_class Con64(immL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2844 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2845 // Output immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
2846 emit_d64($src$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
2847 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2848
a61af66fc99e Initial load
duke
parents:
diff changeset
2849 enc_class Con32F_as_bits(immF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2850 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2851 // Output Float immediate bits
a61af66fc99e Initial load
duke
parents:
diff changeset
2852 jfloat jf = $src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2853 jint jf_as_bits = jint_cast(jf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2854 emit_d32(cbuf, jf_as_bits);
a61af66fc99e Initial load
duke
parents:
diff changeset
2855 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2856
a61af66fc99e Initial load
duke
parents:
diff changeset
2857 enc_class Con16(immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2858 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2859 // Output immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
2860 $$$emit16$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2861 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2862
a61af66fc99e Initial load
duke
parents:
diff changeset
2863 // How is this different from Con32??? XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
2864 enc_class Con_d32(immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2865 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2866 emit_d32(cbuf,$src$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
2867 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2868
a61af66fc99e Initial load
duke
parents:
diff changeset
2869 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
a61af66fc99e Initial load
duke
parents:
diff changeset
2870 // Output immediate memory reference
a61af66fc99e Initial load
duke
parents:
diff changeset
2871 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2872 emit_d32(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
2873 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2874
a61af66fc99e Initial load
duke
parents:
diff changeset
2875 enc_class lock_prefix()
a61af66fc99e Initial load
duke
parents:
diff changeset
2876 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2877 if (os::is_MP()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2878 emit_opcode(cbuf, 0xF0); // lock
a61af66fc99e Initial load
duke
parents:
diff changeset
2879 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2880 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2881
a61af66fc99e Initial load
duke
parents:
diff changeset
2882 enc_class REX_mem(memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
2883 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2884 if ($mem$$base >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2885 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2886 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2887 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2888 emit_opcode(cbuf, Assembler::REX_XB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2889 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2890 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2891 if ($mem$$index >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2892 emit_opcode(cbuf, Assembler::REX_X);
a61af66fc99e Initial load
duke
parents:
diff changeset
2893 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2894 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2895 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2896
a61af66fc99e Initial load
duke
parents:
diff changeset
2897 enc_class REX_mem_wide(memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
2898 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2899 if ($mem$$base >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2900 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2901 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2902 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2903 emit_opcode(cbuf, Assembler::REX_WXB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2904 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2905 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2906 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2907 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2908 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2909 emit_opcode(cbuf, Assembler::REX_WX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2910 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2911 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2912 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2913
a61af66fc99e Initial load
duke
parents:
diff changeset
2914 // for byte regs
a61af66fc99e Initial load
duke
parents:
diff changeset
2915 enc_class REX_breg(rRegI reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
2916 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2917 if ($reg$$reg >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2918 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2919 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2920 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2921
a61af66fc99e Initial load
duke
parents:
diff changeset
2922 // for byte regs
a61af66fc99e Initial load
duke
parents:
diff changeset
2923 enc_class REX_reg_breg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2924 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2925 if ($dst$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2926 if ($src$$reg >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2927 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2928 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2929 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2930 if ($src$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2931 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
2932 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2933 emit_opcode(cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2934 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2935 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2936 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2937
a61af66fc99e Initial load
duke
parents:
diff changeset
2938 // for byte regs
a61af66fc99e Initial load
duke
parents:
diff changeset
2939 enc_class REX_breg_mem(rRegI reg, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
2940 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2941 if ($reg$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2942 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2943 if ($mem$$index >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2944 emit_opcode(cbuf, Assembler::REX_X);
a61af66fc99e Initial load
duke
parents:
diff changeset
2945 } else if ($reg$$reg >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2946 emit_opcode(cbuf, Assembler::REX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2947 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2948 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2949 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2950 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2951 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2952 emit_opcode(cbuf, Assembler::REX_XB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2953 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2954 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2955 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2956 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2957 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2958 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
2959 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2960 emit_opcode(cbuf, Assembler::REX_RX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2961 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2962 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2963 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2964 emit_opcode(cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2965 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2966 emit_opcode(cbuf, Assembler::REX_RXB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2967 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2968 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2969 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2970 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2971
a61af66fc99e Initial load
duke
parents:
diff changeset
2972 enc_class REX_reg(rRegI reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
2973 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2974 if ($reg$$reg >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2975 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2976 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2977 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2978
a61af66fc99e Initial load
duke
parents:
diff changeset
2979 enc_class REX_reg_wide(rRegI reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
2980 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2981 if ($reg$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2982 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2983 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2984 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2985 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2986 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2987
a61af66fc99e Initial load
duke
parents:
diff changeset
2988 enc_class REX_reg_reg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2989 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2990 if ($dst$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2991 if ($src$$reg >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2992 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2993 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2994 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2995 if ($src$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2996 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
2997 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2998 emit_opcode(cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2999 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3000 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3001 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3002
a61af66fc99e Initial load
duke
parents:
diff changeset
3003 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
3004 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3005 if ($dst$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3006 if ($src$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3007 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
3008 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3009 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
3010 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3011 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3012 if ($src$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3013 emit_opcode(cbuf, Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
3014 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3015 emit_opcode(cbuf, Assembler::REX_WRB);
a61af66fc99e Initial load
duke
parents:
diff changeset
3016 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3017 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3018 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3019
a61af66fc99e Initial load
duke
parents:
diff changeset
3020 enc_class REX_reg_mem(rRegI reg, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
3021 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3022 if ($reg$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3023 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3024 if ($mem$$index >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3025 emit_opcode(cbuf, Assembler::REX_X);
a61af66fc99e Initial load
duke
parents:
diff changeset
3026 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3027 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3028 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3029 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
3030 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3031 emit_opcode(cbuf, Assembler::REX_XB);
a61af66fc99e Initial load
duke
parents:
diff changeset
3032 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3033 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3034 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3035 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3036 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3037 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
3038 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3039 emit_opcode(cbuf, Assembler::REX_RX);
a61af66fc99e Initial load
duke
parents:
diff changeset
3040 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3041 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3042 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3043 emit_opcode(cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
3044 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3045 emit_opcode(cbuf, Assembler::REX_RXB);
a61af66fc99e Initial load
duke
parents:
diff changeset
3046 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3047 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3048 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3049 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3050
a61af66fc99e Initial load
duke
parents:
diff changeset
3051 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
3052 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3053 if ($reg$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3054 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3055 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3056 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
3057 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3058 emit_opcode(cbuf, Assembler::REX_WX);
a61af66fc99e Initial load
duke
parents:
diff changeset
3059 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3060 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3061 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3062 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
3063 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3064 emit_opcode(cbuf, Assembler::REX_WXB);
a61af66fc99e Initial load
duke
parents:
diff changeset
3065 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3066 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3067 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3068 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3069 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3070 emit_opcode(cbuf, Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
3071 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3072 emit_opcode(cbuf, Assembler::REX_WRX);
a61af66fc99e Initial load
duke
parents:
diff changeset
3073 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3074 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3075 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3076 emit_opcode(cbuf, Assembler::REX_WRB);
a61af66fc99e Initial load
duke
parents:
diff changeset
3077 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3078 emit_opcode(cbuf, Assembler::REX_WRXB);
a61af66fc99e Initial load
duke
parents:
diff changeset
3079 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3080 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3081 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3082 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3083
a61af66fc99e Initial load
duke
parents:
diff changeset
3084 enc_class reg_mem(rRegI ereg, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
3085 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3086 // High registers handle in encode_RegMem
a61af66fc99e Initial load
duke
parents:
diff changeset
3087 int reg = $ereg$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3088 int base = $mem$$base;
a61af66fc99e Initial load
duke
parents:
diff changeset
3089 int index = $mem$$index;
a61af66fc99e Initial load
duke
parents:
diff changeset
3090 int scale = $mem$$scale;
a61af66fc99e Initial load
duke
parents:
diff changeset
3091 int disp = $mem$$disp;
a61af66fc99e Initial load
duke
parents:
diff changeset
3092 bool disp_is_oop = $mem->disp_is_oop();
a61af66fc99e Initial load
duke
parents:
diff changeset
3093
a61af66fc99e Initial load
duke
parents:
diff changeset
3094 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop);
a61af66fc99e Initial load
duke
parents:
diff changeset
3095 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3096
a61af66fc99e Initial load
duke
parents:
diff changeset
3097 enc_class RM_opc_mem(immI rm_opcode, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
3098 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3099 int rm_byte_opcode = $rm_opcode$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
3100
a61af66fc99e Initial load
duke
parents:
diff changeset
3101 // High registers handle in encode_RegMem
a61af66fc99e Initial load
duke
parents:
diff changeset
3102 int base = $mem$$base;
a61af66fc99e Initial load
duke
parents:
diff changeset
3103 int index = $mem$$index;
a61af66fc99e Initial load
duke
parents:
diff changeset
3104 int scale = $mem$$scale;
a61af66fc99e Initial load
duke
parents:
diff changeset
3105 int displace = $mem$$disp;
a61af66fc99e Initial load
duke
parents:
diff changeset
3106
a61af66fc99e Initial load
duke
parents:
diff changeset
3107 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when
a61af66fc99e Initial load
duke
parents:
diff changeset
3108 // working with static
a61af66fc99e Initial load
duke
parents:
diff changeset
3109 // globals
a61af66fc99e Initial load
duke
parents:
diff changeset
3110 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
a61af66fc99e Initial load
duke
parents:
diff changeset
3111 disp_is_oop);
a61af66fc99e Initial load
duke
parents:
diff changeset
3112 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3113
a61af66fc99e Initial load
duke
parents:
diff changeset
3114 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
3115 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3116 int reg_encoding = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3117 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
a61af66fc99e Initial load
duke
parents:
diff changeset
3118 int index = 0x04; // 0x04 indicates no index
a61af66fc99e Initial load
duke
parents:
diff changeset
3119 int scale = 0x00; // 0x00 indicates no scale
a61af66fc99e Initial load
duke
parents:
diff changeset
3120 int displace = $src1$$constant; // 0x00 indicates no displacement
a61af66fc99e Initial load
duke
parents:
diff changeset
3121 bool disp_is_oop = false;
a61af66fc99e Initial load
duke
parents:
diff changeset
3122 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
a61af66fc99e Initial load
duke
parents:
diff changeset
3123 disp_is_oop);
a61af66fc99e Initial load
duke
parents:
diff changeset
3124 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3125
a61af66fc99e Initial load
duke
parents:
diff changeset
3126 enc_class neg_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
3127 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3128 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3129 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3130 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
3131 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
3132 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3133 // NEG $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
3134 emit_opcode(cbuf, 0xF7);
a61af66fc99e Initial load
duke
parents:
diff changeset
3135 emit_rm(cbuf, 0x3, 0x03, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
3136 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3137
a61af66fc99e Initial load
duke
parents:
diff changeset
3138 enc_class neg_reg_wide(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
3139 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3140 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3141 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3142 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
3143 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3144 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
3145 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
3146 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3147 // NEG $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
3148 emit_opcode(cbuf, 0xF7);
a61af66fc99e Initial load
duke
parents:
diff changeset
3149 emit_rm(cbuf, 0x3, 0x03, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
3150 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3151
a61af66fc99e Initial load
duke
parents:
diff changeset
3152 enc_class setLT_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
3153 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3154 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3155 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3156 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
3157 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
3158 } else if (dstenc >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3159 emit_opcode(cbuf, Assembler::REX);
a61af66fc99e Initial load
duke
parents:
diff changeset
3160 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3161 // SETLT $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
3162 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
3163 emit_opcode(cbuf, 0x9C);
a61af66fc99e Initial load
duke
parents:
diff changeset
3164 emit_rm(cbuf, 0x3, 0x0, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
3165 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3166
a61af66fc99e Initial load
duke
parents:
diff changeset
3167 enc_class setNZ_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
3168 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3169 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3170 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3171 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
3172 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
3173 } else if (dstenc >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3174 emit_opcode(cbuf, Assembler::REX);
a61af66fc99e Initial load
duke
parents:
diff changeset
3175 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3176 // SETNZ $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
3177 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
3178 emit_opcode(cbuf, 0x95);
a61af66fc99e Initial load
duke
parents:
diff changeset
3179 emit_rm(cbuf, 0x3, 0x0, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
3180 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3181
a61af66fc99e Initial load
duke
parents:
diff changeset
3182 enc_class enc_cmpLTP(no_rcx_RegI p, no_rcx_RegI q, no_rcx_RegI y,
a61af66fc99e Initial load
duke
parents:
diff changeset
3183 rcx_RegI tmp)
a61af66fc99e Initial load
duke
parents:
diff changeset
3184 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3185 // cadd_cmpLT
a61af66fc99e Initial load
duke
parents:
diff changeset
3186
a61af66fc99e Initial load
duke
parents:
diff changeset
3187 int tmpReg = $tmp$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3188
a61af66fc99e Initial load
duke
parents:
diff changeset
3189 int penc = $p$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3190 int qenc = $q$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3191 int yenc = $y$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3192
a61af66fc99e Initial load
duke
parents:
diff changeset
3193 // subl $p,$q
a61af66fc99e Initial load
duke
parents:
diff changeset
3194 if (penc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3195 if (qenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3196 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
3197 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3198 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3199 if (qenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3200 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
3201 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3202 emit_opcode(cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
3203 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3204 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3205 emit_opcode(cbuf, 0x2B);
a61af66fc99e Initial load
duke
parents:
diff changeset
3206 emit_rm(cbuf, 0x3, penc & 7, qenc & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
3207
a61af66fc99e Initial load
duke
parents:
diff changeset
3208 // sbbl $tmp, $tmp
a61af66fc99e Initial load
duke
parents:
diff changeset
3209 emit_opcode(cbuf, 0x1B);
a61af66fc99e Initial load
duke
parents:
diff changeset
3210 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3211
a61af66fc99e Initial load
duke
parents:
diff changeset
3212 // andl $tmp, $y
a61af66fc99e Initial load
duke
parents:
diff changeset
3213 if (yenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3214 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
3215 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3216 emit_opcode(cbuf, 0x23);
a61af66fc99e Initial load
duke
parents:
diff changeset
3217 emit_rm(cbuf, 0x3, tmpReg, yenc & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
3218
a61af66fc99e Initial load
duke
parents:
diff changeset
3219 // addl $p,$tmp
a61af66fc99e Initial load
duke
parents:
diff changeset
3220 if (penc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3221 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
3222 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3223 emit_opcode(cbuf, 0x03);
a61af66fc99e Initial load
duke
parents:
diff changeset
3224 emit_rm(cbuf, 0x3, penc & 7, tmpReg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3225 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3226
a61af66fc99e Initial load
duke
parents:
diff changeset
3227 // Compare the lonogs and set -1, 0, or 1 into dst
a61af66fc99e Initial load
duke
parents:
diff changeset
3228 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
3229 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3230 int src1enc = $src1$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3231 int src2enc = $src2$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3232 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3233
a61af66fc99e Initial load
duke
parents:
diff changeset
3234 // cmpq $src1, $src2
a61af66fc99e Initial load
duke
parents:
diff changeset
3235 if (src1enc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3236 if (src2enc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3237 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
3238 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3239 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
3240 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3241 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3242 if (src2enc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3243 emit_opcode(cbuf, Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
3244 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3245 emit_opcode(cbuf, Assembler::REX_WRB);
a61af66fc99e Initial load
duke
parents:
diff changeset
3246 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3247 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3248 emit_opcode(cbuf, 0x3B);
a61af66fc99e Initial load
duke
parents:
diff changeset
3249 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
3250
a61af66fc99e Initial load
duke
parents:
diff changeset
3251 // movl $dst, -1
a61af66fc99e Initial load
duke
parents:
diff changeset
3252 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3253 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
3254 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3255 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
a61af66fc99e Initial load
duke
parents:
diff changeset
3256 emit_d32(cbuf, -1);
a61af66fc99e Initial load
duke
parents:
diff changeset
3257
a61af66fc99e Initial load
duke
parents:
diff changeset
3258 // jl,s done
a61af66fc99e Initial load
duke
parents:
diff changeset
3259 emit_opcode(cbuf, 0x7C);
a61af66fc99e Initial load
duke
parents:
diff changeset
3260 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
a61af66fc99e Initial load
duke
parents:
diff changeset
3261
a61af66fc99e Initial load
duke
parents:
diff changeset
3262 // setne $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
3263 if (dstenc >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3264 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
3265 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3266 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
3267 emit_opcode(cbuf, 0x95);
a61af66fc99e Initial load
duke
parents:
diff changeset
3268 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
a61af66fc99e Initial load
duke
parents:
diff changeset
3269
a61af66fc99e Initial load
duke
parents:
diff changeset
3270 // movzbl $dst, $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
3271 if (dstenc >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3272 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
3273 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3274 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
3275 emit_opcode(cbuf, 0xB6);
a61af66fc99e Initial load
duke
parents:
diff changeset
3276 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
3277 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3278
a61af66fc99e Initial load
duke
parents:
diff changeset
3279 enc_class Push_ResultXD(regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3280 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3281
a61af66fc99e Initial load
duke
parents:
diff changeset
3282 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [RSP]
a61af66fc99e Initial load
duke
parents:
diff changeset
3283
a61af66fc99e Initial load
duke
parents:
diff changeset
3284 // UseXmmLoadAndClearUpper ? movsd dst,[rsp] : movlpd dst,[rsp]
a61af66fc99e Initial load
duke
parents:
diff changeset
3285 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
a61af66fc99e Initial load
duke
parents:
diff changeset
3286 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3287 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
3288 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3289 emit_opcode (cbuf, 0x0F );
a61af66fc99e Initial load
duke
parents:
diff changeset
3290 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12 );
a61af66fc99e Initial load
duke
parents:
diff changeset
3291 encode_RegMem(cbuf, dstenc, RSP_enc, 0x4, 0, 0, false);
a61af66fc99e Initial load
duke
parents:
diff changeset
3292
a61af66fc99e Initial load
duke
parents:
diff changeset
3293 // add rsp,8
a61af66fc99e Initial load
duke
parents:
diff changeset
3294 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
3295 emit_opcode(cbuf,0x83);
a61af66fc99e Initial load
duke
parents:
diff changeset
3296 emit_rm(cbuf,0x3, 0x0, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
3297 emit_d8(cbuf,0x08);
a61af66fc99e Initial load
duke
parents:
diff changeset
3298 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3299
a61af66fc99e Initial load
duke
parents:
diff changeset
3300 enc_class Push_SrcXD(regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3301 int srcenc = $src$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3302
a61af66fc99e Initial load
duke
parents:
diff changeset
3303 // subq rsp,#8
a61af66fc99e Initial load
duke
parents:
diff changeset
3304 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
3305 emit_opcode(cbuf, 0x83);
a61af66fc99e Initial load
duke
parents:
diff changeset
3306 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
3307 emit_d8(cbuf, 0x8);
a61af66fc99e Initial load
duke
parents:
diff changeset
3308
a61af66fc99e Initial load
duke
parents:
diff changeset
3309 // movsd [rsp],src
a61af66fc99e Initial load
duke
parents:
diff changeset
3310 emit_opcode(cbuf, 0xF2);
a61af66fc99e Initial load
duke
parents:
diff changeset
3311 if (srcenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3312 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
3313 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3314 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
3315 emit_opcode(cbuf, 0x11);
a61af66fc99e Initial load
duke
parents:
diff changeset
3316 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false);
a61af66fc99e Initial load
duke
parents:
diff changeset
3317
a61af66fc99e Initial load
duke
parents:
diff changeset
3318 // fldd [rsp]
a61af66fc99e Initial load
duke
parents:
diff changeset
3319 emit_opcode(cbuf, 0x66);
a61af66fc99e Initial load
duke
parents:
diff changeset
3320 emit_opcode(cbuf, 0xDD);
a61af66fc99e Initial load
duke
parents:
diff changeset
3321 encode_RegMem(cbuf, 0x0, RSP_enc, 0x4, 0, 0, false);
a61af66fc99e Initial load
duke
parents:
diff changeset
3322 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3323
a61af66fc99e Initial load
duke
parents:
diff changeset
3324
a61af66fc99e Initial load
duke
parents:
diff changeset
3325 enc_class movq_ld(regD dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3326 MacroAssembler _masm(&cbuf);
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
3327 __ movq($dst$$XMMRegister, $mem$$Address);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3328 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3329
a61af66fc99e Initial load
duke
parents:
diff changeset
3330 enc_class movq_st(memory mem, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3331 MacroAssembler _masm(&cbuf);
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
3332 __ movq($mem$$Address, $src$$XMMRegister);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3333 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3334
a61af66fc99e Initial load
duke
parents:
diff changeset
3335 enc_class pshufd_8x8(regF dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3336 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
3337
a61af66fc99e Initial load
duke
parents:
diff changeset
3338 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3339 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3340 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
3341 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3342
a61af66fc99e Initial load
duke
parents:
diff changeset
3343 enc_class pshufd_4x16(regF dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3344 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
3345
a61af66fc99e Initial load
duke
parents:
diff changeset
3346 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
3347 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3348
a61af66fc99e Initial load
duke
parents:
diff changeset
3349 enc_class pshufd(regD dst, regD src, int mode) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3350 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
3351
a61af66fc99e Initial load
duke
parents:
diff changeset
3352 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
a61af66fc99e Initial load
duke
parents:
diff changeset
3353 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3354
a61af66fc99e Initial load
duke
parents:
diff changeset
3355 enc_class pxor(regD dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3356 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
3357
a61af66fc99e Initial load
duke
parents:
diff changeset
3358 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3359 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3360
a61af66fc99e Initial load
duke
parents:
diff changeset
3361 enc_class mov_i2x(regD dst, rRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3362 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
3363
a61af66fc99e Initial load
duke
parents:
diff changeset
3364 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3365 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3366
a61af66fc99e Initial load
duke
parents:
diff changeset
3367 // obj: object to lock
a61af66fc99e Initial load
duke
parents:
diff changeset
3368 // box: box address (header location) -- killed
a61af66fc99e Initial load
duke
parents:
diff changeset
3369 // tmp: rax -- killed
a61af66fc99e Initial load
duke
parents:
diff changeset
3370 // scr: rbx -- killed
a61af66fc99e Initial load
duke
parents:
diff changeset
3371 //
a61af66fc99e Initial load
duke
parents:
diff changeset
3372 // What follows is a direct transliteration of fast_lock() and fast_unlock()
a61af66fc99e Initial load
duke
parents:
diff changeset
3373 // from i486.ad. See that file for comments.
a61af66fc99e Initial load
duke
parents:
diff changeset
3374 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
a61af66fc99e Initial load
duke
parents:
diff changeset
3375 // use the shorter encoding. (Movl clears the high-order 32-bits).
a61af66fc99e Initial load
duke
parents:
diff changeset
3376
a61af66fc99e Initial load
duke
parents:
diff changeset
3377
a61af66fc99e Initial load
duke
parents:
diff changeset
3378 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
a61af66fc99e Initial load
duke
parents:
diff changeset
3379 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3380 Register objReg = as_Register((int)$obj$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3381 Register boxReg = as_Register((int)$box$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3382 Register tmpReg = as_Register($tmp$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3383 Register scrReg = as_Register($scr$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3384 MacroAssembler masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
3385
a61af66fc99e Initial load
duke
parents:
diff changeset
3386 // Verify uniqueness of register assignments -- necessary but not sufficient
a61af66fc99e Initial load
duke
parents:
diff changeset
3387 assert (objReg != boxReg && objReg != tmpReg &&
a61af66fc99e Initial load
duke
parents:
diff changeset
3388 objReg != scrReg && tmpReg != scrReg, "invariant") ;
a61af66fc99e Initial load
duke
parents:
diff changeset
3389
a61af66fc99e Initial load
duke
parents:
diff changeset
3390 if (_counters != NULL) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3391 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
a61af66fc99e Initial load
duke
parents:
diff changeset
3392 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3393 if (EmitSync & 1) {
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3394 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3395 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3396 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3397 } else
a61af66fc99e Initial load
duke
parents:
diff changeset
3398 if (EmitSync & 2) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3399 Label DONE_LABEL;
a61af66fc99e Initial load
duke
parents:
diff changeset
3400 if (UseBiasedLocking) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3401 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
a61af66fc99e Initial load
duke
parents:
diff changeset
3402 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
a61af66fc99e Initial load
duke
parents:
diff changeset
3403 }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3404 // QQQ was movl...
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3405 masm.movptr(tmpReg, 0x1);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3406 masm.orptr(tmpReg, Address(objReg, 0));
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3407 masm.movptr(Address(boxReg, 0), tmpReg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3408 if (os::is_MP()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3409 masm.lock();
a61af66fc99e Initial load
duke
parents:
diff changeset
3410 }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3411 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3412 masm.jcc(Assembler::equal, DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3413
a61af66fc99e Initial load
duke
parents:
diff changeset
3414 // Recursive locking
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3415 masm.subptr(tmpReg, rsp);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3416 masm.andptr(tmpReg, 7 - os::vm_page_size());
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3417 masm.movptr(Address(boxReg, 0), tmpReg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3418
a61af66fc99e Initial load
duke
parents:
diff changeset
3419 masm.bind(DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3420 masm.nop(); // avoid branch to branch
a61af66fc99e Initial load
duke
parents:
diff changeset
3421 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3422 Label DONE_LABEL, IsInflated, Egress;
a61af66fc99e Initial load
duke
parents:
diff changeset
3423
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3424 masm.movptr(tmpReg, Address(objReg, 0)) ;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3425 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3426 masm.jcc (Assembler::notZero, IsInflated) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3427
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3428 // it's stack-locked, biased or neutral
a61af66fc99e Initial load
duke
parents:
diff changeset
3429 // TODO: optimize markword triage order to reduce the number of
a61af66fc99e Initial load
duke
parents:
diff changeset
3430 // conditional branches in the most common cases.
a61af66fc99e Initial load
duke
parents:
diff changeset
3431 // Beware -- there's a subtle invariant that fetch of the markword
a61af66fc99e Initial load
duke
parents:
diff changeset
3432 // at [FETCH], below, will never observe a biased encoding (*101b).
a61af66fc99e Initial load
duke
parents:
diff changeset
3433 // If this invariant is not held we'll suffer exclusion (safety) failure.
a61af66fc99e Initial load
duke
parents:
diff changeset
3434
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
3435 if (UseBiasedLocking && !UseOptoBiasInlining) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3436 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3437 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3438 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3439
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3440 // was q will it destroy high?
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3441 masm.orl (tmpReg, 1) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3442 masm.movptr(Address(boxReg, 0), tmpReg) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3443 if (os::is_MP()) { masm.lock(); }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3444 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3445 if (_counters != NULL) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3446 masm.cond_inc32(Assembler::equal,
a61af66fc99e Initial load
duke
parents:
diff changeset
3447 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
a61af66fc99e Initial load
duke
parents:
diff changeset
3448 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3449 masm.jcc (Assembler::equal, DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3450
a61af66fc99e Initial load
duke
parents:
diff changeset
3451 // Recursive locking
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3452 masm.subptr(tmpReg, rsp);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3453 masm.andptr(tmpReg, 7 - os::vm_page_size());
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3454 masm.movptr(Address(boxReg, 0), tmpReg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3455 if (_counters != NULL) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3456 masm.cond_inc32(Assembler::equal,
a61af66fc99e Initial load
duke
parents:
diff changeset
3457 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
a61af66fc99e Initial load
duke
parents:
diff changeset
3458 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3459 masm.jmp (DONE_LABEL) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
3460
a61af66fc99e Initial load
duke
parents:
diff changeset
3461 masm.bind (IsInflated) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
3462 // It's inflated
a61af66fc99e Initial load
duke
parents:
diff changeset
3463
a61af66fc99e Initial load
duke
parents:
diff changeset
3464 // TODO: someday avoid the ST-before-CAS penalty by
a61af66fc99e Initial load
duke
parents:
diff changeset
3465 // relocating (deferring) the following ST.
a61af66fc99e Initial load
duke
parents:
diff changeset
3466 // We should also think about trying a CAS without having
a61af66fc99e Initial load
duke
parents:
diff changeset
3467 // fetched _owner. If the CAS is successful we may
a61af66fc99e Initial load
duke
parents:
diff changeset
3468 // avoid an RTO->RTS upgrade on the $line.
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3469 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3470 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3471
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3472 masm.mov (boxReg, tmpReg) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3473 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3474 masm.testptr(tmpReg, tmpReg) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3475 masm.jcc (Assembler::notZero, DONE_LABEL) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3476
a61af66fc99e Initial load
duke
parents:
diff changeset
3477 // It's inflated and appears unlocked
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3478 if (os::is_MP()) { masm.lock(); }
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3479 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3480 // Intentional fall-through into DONE_LABEL ...
a61af66fc99e Initial load
duke
parents:
diff changeset
3481
a61af66fc99e Initial load
duke
parents:
diff changeset
3482 masm.bind (DONE_LABEL) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
3483 masm.nop () ; // avoid jmp to jmp
a61af66fc99e Initial load
duke
parents:
diff changeset
3484 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3485 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3486
a61af66fc99e Initial load
duke
parents:
diff changeset
3487 // obj: object to unlock
a61af66fc99e Initial load
duke
parents:
diff changeset
3488 // box: box address (displaced header location), killed
a61af66fc99e Initial load
duke
parents:
diff changeset
3489 // RBX: killed tmp; cannot be obj nor box
a61af66fc99e Initial load
duke
parents:
diff changeset
3490 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
a61af66fc99e Initial load
duke
parents:
diff changeset
3491 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3492
a61af66fc99e Initial load
duke
parents:
diff changeset
3493 Register objReg = as_Register($obj$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3494 Register boxReg = as_Register($box$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3495 Register tmpReg = as_Register($tmp$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3496 MacroAssembler masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
3497
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3498 if (EmitSync & 4) {
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3499 masm.cmpptr(rsp, 0) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3500 } else
a61af66fc99e Initial load
duke
parents:
diff changeset
3501 if (EmitSync & 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3502 Label DONE_LABEL;
a61af66fc99e Initial load
duke
parents:
diff changeset
3503 if (UseBiasedLocking) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3504 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3505 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3506
a61af66fc99e Initial load
duke
parents:
diff changeset
3507 // Check whether the displaced header is 0
a61af66fc99e Initial load
duke
parents:
diff changeset
3508 //(=> recursive unlock)
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3509 masm.movptr(tmpReg, Address(boxReg, 0));
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3510 masm.testptr(tmpReg, tmpReg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3511 masm.jcc(Assembler::zero, DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3512
a61af66fc99e Initial load
duke
parents:
diff changeset
3513 // If not recursive lock, reset the header to displaced header
a61af66fc99e Initial load
duke
parents:
diff changeset
3514 if (os::is_MP()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3515 masm.lock();
a61af66fc99e Initial load
duke
parents:
diff changeset
3516 }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3517 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3518 masm.bind(DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3519 masm.nop(); // avoid branch to branch
a61af66fc99e Initial load
duke
parents:
diff changeset
3520 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3521 Label DONE_LABEL, Stacked, CheckSucc ;
a61af66fc99e Initial load
duke
parents:
diff changeset
3522
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
3523 if (UseBiasedLocking && !UseOptoBiasInlining) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3524 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3525 }
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3526
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3527 masm.movptr(tmpReg, Address(objReg, 0)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3528 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3529 masm.jcc (Assembler::zero, DONE_LABEL) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3530 masm.testl (tmpReg, 0x02) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3531 masm.jcc (Assembler::zero, Stacked) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3532
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3533 // It's inflated
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3534 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3535 masm.xorptr(boxReg, r15_thread) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3536 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3537 masm.jcc (Assembler::notZero, DONE_LABEL) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3538 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3539 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3540 masm.jcc (Assembler::notZero, CheckSucc) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3541 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3542 masm.jmp (DONE_LABEL) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3543
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3544 if ((EmitSync & 65536) == 0) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3545 Label LSuccess, LGoSlowPath ;
a61af66fc99e Initial load
duke
parents:
diff changeset
3546 masm.bind (CheckSucc) ;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3547 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3548 masm.jcc (Assembler::zero, LGoSlowPath) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
3549
a61af66fc99e Initial load
duke
parents:
diff changeset
3550 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
a61af66fc99e Initial load
duke
parents:
diff changeset
3551 // the explicit ST;MEMBAR combination, but masm doesn't currently support
a61af66fc99e Initial load
duke
parents:
diff changeset
3552 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
a61af66fc99e Initial load
duke
parents:
diff changeset
3553 // are all faster when the write buffer is populated.
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3554 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3555 if (os::is_MP()) {
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3556 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3557 }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3558 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3559 masm.jcc (Assembler::notZero, LSuccess) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
3560
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3561 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3562 if (os::is_MP()) { masm.lock(); }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3563 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3564 masm.jcc (Assembler::notEqual, LSuccess) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
3565 // Intentional fall-through into slow-path
a61af66fc99e Initial load
duke
parents:
diff changeset
3566
a61af66fc99e Initial load
duke
parents:
diff changeset
3567 masm.bind (LGoSlowPath) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
3568 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
a61af66fc99e Initial load
duke
parents:
diff changeset
3569 masm.jmp (DONE_LABEL) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
3570
a61af66fc99e Initial load
duke
parents:
diff changeset
3571 masm.bind (LSuccess) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
3572 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
a61af66fc99e Initial load
duke
parents:
diff changeset
3573 masm.jmp (DONE_LABEL) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
3574 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3575
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3576 masm.bind (Stacked) ;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3577 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3578 if (os::is_MP()) { masm.lock(); }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3579 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3580
a61af66fc99e Initial load
duke
parents:
diff changeset
3581 if (EmitSync & 65536) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3582 masm.bind (CheckSucc) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
3583 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3584 masm.bind(DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3585 if (EmitSync & 32768) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3586 masm.nop(); // avoid branch to branch
a61af66fc99e Initial load
duke
parents:
diff changeset
3587 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3588 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3589 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3590
169
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
3591
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3592 enc_class enc_rethrow()
a61af66fc99e Initial load
duke
parents:
diff changeset
3593 %{
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
3594 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3595 emit_opcode(cbuf, 0xE9); // jmp entry
a61af66fc99e Initial load
duke
parents:
diff changeset
3596 emit_d32_reloc(cbuf,
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
3597 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3598 runtime_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
3599 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
3600 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3601
a61af66fc99e Initial load
duke
parents:
diff changeset
3602 enc_class absF_encoding(regF dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
3603 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3604 int dstenc = $dst$$reg;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3605 address signmask_address = (address) StubRoutines::x86::float_sign_mask();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3606
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
3607 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3608 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3609 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
3610 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
3611 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3612 // XXX reg_mem doesn't support RIP-relative addressing yet
a61af66fc99e Initial load
duke
parents:
diff changeset
3613 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
3614 emit_opcode(cbuf, 0x54);
a61af66fc99e Initial load
duke
parents:
diff changeset
3615 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
a61af66fc99e Initial load
duke
parents:
diff changeset
3616 emit_d32_reloc(cbuf, signmask_address);
a61af66fc99e Initial load
duke
parents:
diff changeset
3617 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3618
a61af66fc99e Initial load
duke
parents:
diff changeset
3619 enc_class absD_encoding(regD dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
3620 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3621 int dstenc = $dst$$reg;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3622 address signmask_address = (address) StubRoutines::x86::double_sign_mask();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3623
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
3624 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3625 emit_opcode(cbuf, 0x66);
a61af66fc99e Initial load
duke
parents:
diff changeset
3626 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3627 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
3628 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
3629 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3630 // XXX reg_mem doesn't support RIP-relative addressing yet
a61af66fc99e Initial load
duke
parents:
diff changeset
3631 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
3632 emit_opcode(cbuf, 0x54);
a61af66fc99e Initial load
duke
parents:
diff changeset
3633 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
a61af66fc99e Initial load
duke
parents:
diff changeset
3634 emit_d32_reloc(cbuf, signmask_address);
a61af66fc99e Initial load
duke
parents:
diff changeset
3635 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3636
a61af66fc99e Initial load
duke
parents:
diff changeset
3637 enc_class negF_encoding(regF dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
3638 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3639 int dstenc = $dst$$reg;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3640 address signflip_address = (address) StubRoutines::x86::float_sign_flip();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3641
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
3642 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3643 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3644 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
3645 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
3646 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3647 // XXX reg_mem doesn't support RIP-relative addressing yet
a61af66fc99e Initial load
duke
parents:
diff changeset
3648 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
3649 emit_opcode(cbuf, 0x57);
a61af66fc99e Initial load
duke
parents:
diff changeset
3650 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
a61af66fc99e Initial load
duke
parents:
diff changeset
3651 emit_d32_reloc(cbuf, signflip_address);
a61af66fc99e Initial load
duke
parents:
diff changeset
3652 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3653
a61af66fc99e Initial load
duke
parents:
diff changeset
3654 enc_class negD_encoding(regD dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
3655 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3656 int dstenc = $dst$$reg;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3657 address signflip_address = (address) StubRoutines::x86::double_sign_flip();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3658
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
3659 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3660 emit_opcode(cbuf, 0x66);
a61af66fc99e Initial load
duke
parents:
diff changeset
3661 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3662 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
3663 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
3664 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3665 // XXX reg_mem doesn't support RIP-relative addressing yet
a61af66fc99e Initial load
duke
parents:
diff changeset
3666 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
3667 emit_opcode(cbuf, 0x57);
a61af66fc99e Initial load
duke
parents:
diff changeset
3668 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
a61af66fc99e Initial load
duke
parents:
diff changeset
3669 emit_d32_reloc(cbuf, signflip_address);
a61af66fc99e Initial load
duke
parents:
diff changeset
3670 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3671
a61af66fc99e Initial load
duke
parents:
diff changeset
3672 enc_class f2i_fixup(rRegI dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
3673 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3674 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3675 int srcenc = $src$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3676
a61af66fc99e Initial load
duke
parents:
diff changeset
3677 // cmpl $dst, #0x80000000
a61af66fc99e Initial load
duke
parents:
diff changeset
3678 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3679 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
3680 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3681 emit_opcode(cbuf, 0x81);
a61af66fc99e Initial load
duke
parents:
diff changeset
3682 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
3683 emit_d32(cbuf, 0x80000000);
a61af66fc99e Initial load
duke
parents:
diff changeset
3684
a61af66fc99e Initial load
duke
parents:
diff changeset
3685 // jne,s done
a61af66fc99e Initial load
duke
parents:
diff changeset
3686 emit_opcode(cbuf, 0x75);
a61af66fc99e Initial load
duke
parents:
diff changeset
3687 if (srcenc < 8 && dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3688 emit_d8(cbuf, 0xF);
a61af66fc99e Initial load
duke
parents:
diff changeset
3689 } else if (srcenc >= 8 && dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3690 emit_d8(cbuf, 0x11);
a61af66fc99e Initial load
duke
parents:
diff changeset
3691 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3692 emit_d8(cbuf, 0x10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3693 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3694
a61af66fc99e Initial load
duke
parents:
diff changeset
3695 // subq rsp, #8
a61af66fc99e Initial load
duke
parents:
diff changeset
3696 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
3697 emit_opcode(cbuf, 0x83);
a61af66fc99e Initial load
duke
parents:
diff changeset
3698 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
3699 emit_d8(cbuf, 8);
a61af66fc99e Initial load
duke
parents:
diff changeset
3700
a61af66fc99e Initial load
duke
parents:
diff changeset
3701 // movss [rsp], $src
a61af66fc99e Initial load
duke
parents:
diff changeset
3702 emit_opcode(cbuf, 0xF3);
a61af66fc99e Initial load
duke
parents:
diff changeset
3703 if (srcenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3704 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
3705 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3706 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
3707 emit_opcode(cbuf, 0x11);
a61af66fc99e Initial load
duke
parents:
diff changeset
3708 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
a61af66fc99e Initial load
duke
parents:
diff changeset
3709
a61af66fc99e Initial load
duke
parents:
diff changeset
3710 // call f2i_fixup
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
3711 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3712 emit_opcode(cbuf, 0xE8);
a61af66fc99e Initial load
duke
parents:
diff changeset
3713 emit_d32_reloc(cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
3714 (int)
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
3715 (StubRoutines::x86::f2i_fixup() - cbuf.insts_end() - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3716 runtime_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
3717 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
3718
a61af66fc99e Initial load
duke
parents:
diff changeset
3719 // popq $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
3720 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3721 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
3722 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3723 emit_opcode(cbuf, 0x58 | (dstenc & 7));
a61af66fc99e Initial load
duke
parents:
diff changeset
3724
a61af66fc99e Initial load
duke
parents:
diff changeset
3725 // done:
a61af66fc99e Initial load
duke
parents:
diff changeset
3726 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3727
a61af66fc99e Initial load
duke
parents:
diff changeset
3728 enc_class f2l_fixup(rRegL dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
3729 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3730 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3731 int srcenc = $src$$reg;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3732 address const_address = (address) StubRoutines::x86::double_sign_flip();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3733
a61af66fc99e Initial load
duke
parents:
diff changeset
3734 // cmpq $dst, [0x8000000000000000]
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
3735 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3736 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
3737 emit_opcode(cbuf, 0x39);
a61af66fc99e Initial load
duke
parents:
diff changeset
3738 // XXX reg_mem doesn't support RIP-relative addressing yet
a61af66fc99e Initial load
duke
parents:
diff changeset
3739 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
a61af66fc99e Initial load
duke
parents:
diff changeset
3740 emit_d32_reloc(cbuf, const_address);
a61af66fc99e Initial load
duke
parents:
diff changeset
3741
a61af66fc99e Initial load
duke
parents:
diff changeset
3742
a61af66fc99e Initial load
duke
parents:
diff changeset
3743 // jne,s done
a61af66fc99e Initial load
duke
parents:
diff changeset
3744 emit_opcode(cbuf, 0x75);
a61af66fc99e Initial load
duke
parents:
diff changeset
3745 if (srcenc < 8 && dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3746 emit_d8(cbuf, 0xF);
a61af66fc99e Initial load
duke
parents:
diff changeset
3747 } else if (srcenc >= 8 && dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3748 emit_d8(cbuf, 0x11);
a61af66fc99e Initial load
duke
parents:
diff changeset
3749 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3750 emit_d8(cbuf, 0x10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3751 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3752
a61af66fc99e Initial load
duke
parents:
diff changeset
3753 // subq rsp, #8
a61af66fc99e Initial load
duke
parents:
diff changeset
3754 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
3755 emit_opcode(cbuf, 0x83);
a61af66fc99e Initial load
duke
parents:
diff changeset
3756 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
3757 emit_d8(cbuf, 8);
a61af66fc99e Initial load
duke
parents:
diff changeset
3758
a61af66fc99e Initial load
duke
parents:
diff changeset
3759 // movss [rsp], $src
a61af66fc99e Initial load
duke
parents:
diff changeset
3760 emit_opcode(cbuf, 0xF3);
a61af66fc99e Initial load
duke
parents:
diff changeset
3761 if (srcenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3762 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
3763 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3764 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
3765 emit_opcode(cbuf, 0x11);
a61af66fc99e Initial load
duke
parents:
diff changeset
3766 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
a61af66fc99e Initial load
duke
parents:
diff changeset
3767
a61af66fc99e Initial load
duke
parents:
diff changeset
3768 // call f2l_fixup
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
3769 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3770 emit_opcode(cbuf, 0xE8);
a61af66fc99e Initial load
duke
parents:
diff changeset
3771 emit_d32_reloc(cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
3772 (int)
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
3773 (StubRoutines::x86::f2l_fixup() - cbuf.insts_end() - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3774 runtime_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
3775 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
3776
a61af66fc99e Initial load
duke
parents:
diff changeset
3777 // popq $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
3778 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3779 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
3780 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3781 emit_opcode(cbuf, 0x58 | (dstenc & 7));
a61af66fc99e Initial load
duke
parents:
diff changeset
3782
a61af66fc99e Initial load
duke
parents:
diff changeset
3783 // done:
a61af66fc99e Initial load
duke
parents:
diff changeset
3784 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3785
a61af66fc99e Initial load
duke
parents:
diff changeset
3786 enc_class d2i_fixup(rRegI dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
3787 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3788 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3789 int srcenc = $src$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3790
a61af66fc99e Initial load
duke
parents:
diff changeset
3791 // cmpl $dst, #0x80000000
a61af66fc99e Initial load
duke
parents:
diff changeset
3792 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3793 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
3794 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3795 emit_opcode(cbuf, 0x81);
a61af66fc99e Initial load
duke
parents:
diff changeset
3796 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
3797 emit_d32(cbuf, 0x80000000);
a61af66fc99e Initial load
duke
parents:
diff changeset
3798
a61af66fc99e Initial load
duke
parents:
diff changeset
3799 // jne,s done
a61af66fc99e Initial load
duke
parents:
diff changeset
3800 emit_opcode(cbuf, 0x75);
a61af66fc99e Initial load
duke
parents:
diff changeset
3801 if (srcenc < 8 && dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3802 emit_d8(cbuf, 0xF);
a61af66fc99e Initial load
duke
parents:
diff changeset
3803 } else if (srcenc >= 8 && dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3804 emit_d8(cbuf, 0x11);
a61af66fc99e Initial load
duke
parents:
diff changeset
3805 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3806 emit_d8(cbuf, 0x10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3807 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3808
a61af66fc99e Initial load
duke
parents:
diff changeset
3809 // subq rsp, #8
a61af66fc99e Initial load
duke
parents:
diff changeset
3810 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
3811 emit_opcode(cbuf, 0x83);
a61af66fc99e Initial load
duke
parents:
diff changeset
3812 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
3813 emit_d8(cbuf, 8);
a61af66fc99e Initial load
duke
parents:
diff changeset
3814
a61af66fc99e Initial load
duke
parents:
diff changeset
3815 // movsd [rsp], $src
a61af66fc99e Initial load
duke
parents:
diff changeset
3816 emit_opcode(cbuf, 0xF2);
a61af66fc99e Initial load
duke
parents:
diff changeset
3817 if (srcenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3818 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
3819 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3820 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
3821 emit_opcode(cbuf, 0x11);
a61af66fc99e Initial load
duke
parents:
diff changeset
3822 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
a61af66fc99e Initial load
duke
parents:
diff changeset
3823
a61af66fc99e Initial load
duke
parents:
diff changeset
3824 // call d2i_fixup
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
3825 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3826 emit_opcode(cbuf, 0xE8);
a61af66fc99e Initial load
duke
parents:
diff changeset
3827 emit_d32_reloc(cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
3828 (int)
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
3829 (StubRoutines::x86::d2i_fixup() - cbuf.insts_end() - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3830 runtime_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
3831 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
3832
a61af66fc99e Initial load
duke
parents:
diff changeset
3833 // popq $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
3834 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3835 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
3836 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3837 emit_opcode(cbuf, 0x58 | (dstenc & 7));
a61af66fc99e Initial load
duke
parents:
diff changeset
3838
a61af66fc99e Initial load
duke
parents:
diff changeset
3839 // done:
a61af66fc99e Initial load
duke
parents:
diff changeset
3840 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3841
a61af66fc99e Initial load
duke
parents:
diff changeset
3842 enc_class d2l_fixup(rRegL dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
3843 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3844 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
3845 int srcenc = $src$$reg;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
3846 address const_address = (address) StubRoutines::x86::double_sign_flip();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3847
a61af66fc99e Initial load
duke
parents:
diff changeset
3848 // cmpq $dst, [0x8000000000000000]
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
3849 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3850 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
3851 emit_opcode(cbuf, 0x39);
a61af66fc99e Initial load
duke
parents:
diff changeset
3852 // XXX reg_mem doesn't support RIP-relative addressing yet
a61af66fc99e Initial load
duke
parents:
diff changeset
3853 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
a61af66fc99e Initial load
duke
parents:
diff changeset
3854 emit_d32_reloc(cbuf, const_address);
a61af66fc99e Initial load
duke
parents:
diff changeset
3855
a61af66fc99e Initial load
duke
parents:
diff changeset
3856
a61af66fc99e Initial load
duke
parents:
diff changeset
3857 // jne,s done
a61af66fc99e Initial load
duke
parents:
diff changeset
3858 emit_opcode(cbuf, 0x75);
a61af66fc99e Initial load
duke
parents:
diff changeset
3859 if (srcenc < 8 && dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3860 emit_d8(cbuf, 0xF);
a61af66fc99e Initial load
duke
parents:
diff changeset
3861 } else if (srcenc >= 8 && dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3862 emit_d8(cbuf, 0x11);
a61af66fc99e Initial load
duke
parents:
diff changeset
3863 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
3864 emit_d8(cbuf, 0x10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3865 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3866
a61af66fc99e Initial load
duke
parents:
diff changeset
3867 // subq rsp, #8
a61af66fc99e Initial load
duke
parents:
diff changeset
3868 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
3869 emit_opcode(cbuf, 0x83);
a61af66fc99e Initial load
duke
parents:
diff changeset
3870 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
3871 emit_d8(cbuf, 8);
a61af66fc99e Initial load
duke
parents:
diff changeset
3872
a61af66fc99e Initial load
duke
parents:
diff changeset
3873 // movsd [rsp], $src
a61af66fc99e Initial load
duke
parents:
diff changeset
3874 emit_opcode(cbuf, 0xF2);
a61af66fc99e Initial load
duke
parents:
diff changeset
3875 if (srcenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3876 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
3877 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3878 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
3879 emit_opcode(cbuf, 0x11);
a61af66fc99e Initial load
duke
parents:
diff changeset
3880 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
a61af66fc99e Initial load
duke
parents:
diff changeset
3881
a61af66fc99e Initial load
duke
parents:
diff changeset
3882 // call d2l_fixup
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
3883 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3884 emit_opcode(cbuf, 0xE8);
a61af66fc99e Initial load
duke
parents:
diff changeset
3885 emit_d32_reloc(cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
3886 (int)
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
3887 (StubRoutines::x86::d2l_fixup() - cbuf.insts_end() - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3888 runtime_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
3889 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
3890
a61af66fc99e Initial load
duke
parents:
diff changeset
3891 // popq $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
3892 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
3893 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
3894 }
a61af66fc99e Initial load
duke
parents:
diff changeset
3895 emit_opcode(cbuf, 0x58 | (dstenc & 7));
a61af66fc99e Initial load
duke
parents:
diff changeset
3896
a61af66fc99e Initial load
duke
parents:
diff changeset
3897 // done:
a61af66fc99e Initial load
duke
parents:
diff changeset
3898 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3899 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3900
a61af66fc99e Initial load
duke
parents:
diff changeset
3901
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3902
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3903 //----------FRAME--------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
3904 // Definition of frame structure and management information.
a61af66fc99e Initial load
duke
parents:
diff changeset
3905 //
a61af66fc99e Initial load
duke
parents:
diff changeset
3906 // S T A C K L A Y O U T Allocators stack-slot number
a61af66fc99e Initial load
duke
parents:
diff changeset
3907 // | (to get allocators register number
a61af66fc99e Initial load
duke
parents:
diff changeset
3908 // G Owned by | | v add OptoReg::stack0())
a61af66fc99e Initial load
duke
parents:
diff changeset
3909 // r CALLER | |
a61af66fc99e Initial load
duke
parents:
diff changeset
3910 // o | +--------+ pad to even-align allocators stack-slot
a61af66fc99e Initial load
duke
parents:
diff changeset
3911 // w V | pad0 | numbers; owned by CALLER
a61af66fc99e Initial load
duke
parents:
diff changeset
3912 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
a61af66fc99e Initial load
duke
parents:
diff changeset
3913 // h ^ | in | 5
a61af66fc99e Initial load
duke
parents:
diff changeset
3914 // | | args | 4 Holes in incoming args owned by SELF
a61af66fc99e Initial load
duke
parents:
diff changeset
3915 // | | | | 3
a61af66fc99e Initial load
duke
parents:
diff changeset
3916 // | | +--------+
a61af66fc99e Initial load
duke
parents:
diff changeset
3917 // V | | old out| Empty on Intel, window on Sparc
a61af66fc99e Initial load
duke
parents:
diff changeset
3918 // | old |preserve| Must be even aligned.
a61af66fc99e Initial load
duke
parents:
diff changeset
3919 // | SP-+--------+----> Matcher::_old_SP, even aligned
a61af66fc99e Initial load
duke
parents:
diff changeset
3920 // | | in | 3 area for Intel ret address
a61af66fc99e Initial load
duke
parents:
diff changeset
3921 // Owned by |preserve| Empty on Sparc.
a61af66fc99e Initial load
duke
parents:
diff changeset
3922 // SELF +--------+
a61af66fc99e Initial load
duke
parents:
diff changeset
3923 // | | pad2 | 2 pad to align old SP
a61af66fc99e Initial load
duke
parents:
diff changeset
3924 // | +--------+ 1
a61af66fc99e Initial load
duke
parents:
diff changeset
3925 // | | locks | 0
a61af66fc99e Initial load
duke
parents:
diff changeset
3926 // | +--------+----> OptoReg::stack0(), even aligned
a61af66fc99e Initial load
duke
parents:
diff changeset
3927 // | | pad1 | 11 pad to align new SP
a61af66fc99e Initial load
duke
parents:
diff changeset
3928 // | +--------+
a61af66fc99e Initial load
duke
parents:
diff changeset
3929 // | | | 10
a61af66fc99e Initial load
duke
parents:
diff changeset
3930 // | | spills | 9 spills
a61af66fc99e Initial load
duke
parents:
diff changeset
3931 // V | | 8 (pad0 slot for callee)
a61af66fc99e Initial load
duke
parents:
diff changeset
3932 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
a61af66fc99e Initial load
duke
parents:
diff changeset
3933 // ^ | out | 7
a61af66fc99e Initial load
duke
parents:
diff changeset
3934 // | | args | 6 Holes in outgoing args owned by CALLEE
a61af66fc99e Initial load
duke
parents:
diff changeset
3935 // Owned by +--------+
a61af66fc99e Initial load
duke
parents:
diff changeset
3936 // CALLEE | new out| 6 Empty on Intel, window on Sparc
a61af66fc99e Initial load
duke
parents:
diff changeset
3937 // | new |preserve| Must be even-aligned.
a61af66fc99e Initial load
duke
parents:
diff changeset
3938 // | SP-+--------+----> Matcher::_new_SP, even aligned
a61af66fc99e Initial load
duke
parents:
diff changeset
3939 // | | |
a61af66fc99e Initial load
duke
parents:
diff changeset
3940 //
a61af66fc99e Initial load
duke
parents:
diff changeset
3941 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
a61af66fc99e Initial load
duke
parents:
diff changeset
3942 // known from SELF's arguments and the Java calling convention.
a61af66fc99e Initial load
duke
parents:
diff changeset
3943 // Region 6-7 is determined per call site.
a61af66fc99e Initial load
duke
parents:
diff changeset
3944 // Note 2: If the calling convention leaves holes in the incoming argument
a61af66fc99e Initial load
duke
parents:
diff changeset
3945 // area, those holes are owned by SELF. Holes in the outgoing area
a61af66fc99e Initial load
duke
parents:
diff changeset
3946 // are owned by the CALLEE. Holes should not be nessecary in the
a61af66fc99e Initial load
duke
parents:
diff changeset
3947 // incoming area, as the Java calling convention is completely under
a61af66fc99e Initial load
duke
parents:
diff changeset
3948 // the control of the AD file. Doubles can be sorted and packed to
a61af66fc99e Initial load
duke
parents:
diff changeset
3949 // avoid holes. Holes in the outgoing arguments may be nessecary for
a61af66fc99e Initial load
duke
parents:
diff changeset
3950 // varargs C calling conventions.
a61af66fc99e Initial load
duke
parents:
diff changeset
3951 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
a61af66fc99e Initial load
duke
parents:
diff changeset
3952 // even aligned with pad0 as needed.
a61af66fc99e Initial load
duke
parents:
diff changeset
3953 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
a61af66fc99e Initial load
duke
parents:
diff changeset
3954 // region 6-11 is even aligned; it may be padded out more so that
a61af66fc99e Initial load
duke
parents:
diff changeset
3955 // the region from SP to FP meets the minimum stack alignment.
a61af66fc99e Initial load
duke
parents:
diff changeset
3956 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
a61af66fc99e Initial load
duke
parents:
diff changeset
3957 // alignment. Region 11, pad1, may be dynamically extended so that
a61af66fc99e Initial load
duke
parents:
diff changeset
3958 // SP meets the minimum alignment.
a61af66fc99e Initial load
duke
parents:
diff changeset
3959
a61af66fc99e Initial load
duke
parents:
diff changeset
3960 frame
a61af66fc99e Initial load
duke
parents:
diff changeset
3961 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3962 // What direction does stack grow in (assumed to be same for C & Java)
a61af66fc99e Initial load
duke
parents:
diff changeset
3963 stack_direction(TOWARDS_LOW);
a61af66fc99e Initial load
duke
parents:
diff changeset
3964
a61af66fc99e Initial load
duke
parents:
diff changeset
3965 // These three registers define part of the calling convention
a61af66fc99e Initial load
duke
parents:
diff changeset
3966 // between compiled code and the interpreter.
a61af66fc99e Initial load
duke
parents:
diff changeset
3967 inline_cache_reg(RAX); // Inline Cache Register
a61af66fc99e Initial load
duke
parents:
diff changeset
3968 interpreter_method_oop_reg(RBX); // Method Oop Register when
a61af66fc99e Initial load
duke
parents:
diff changeset
3969 // calling interpreter
a61af66fc99e Initial load
duke
parents:
diff changeset
3970
a61af66fc99e Initial load
duke
parents:
diff changeset
3971 // Optional: name the operand used by cisc-spilling to access
a61af66fc99e Initial load
duke
parents:
diff changeset
3972 // [stack_pointer + offset]
a61af66fc99e Initial load
duke
parents:
diff changeset
3973 cisc_spilling_operand_name(indOffset32);
a61af66fc99e Initial load
duke
parents:
diff changeset
3974
a61af66fc99e Initial load
duke
parents:
diff changeset
3975 // Number of stack slots consumed by locking an object
a61af66fc99e Initial load
duke
parents:
diff changeset
3976 sync_stack_slots(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
3977
a61af66fc99e Initial load
duke
parents:
diff changeset
3978 // Compiled code's Frame Pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
3979 frame_pointer(RSP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3980
a61af66fc99e Initial load
duke
parents:
diff changeset
3981 // Interpreter stores its frame pointer in a register which is
a61af66fc99e Initial load
duke
parents:
diff changeset
3982 // stored to the stack by I2CAdaptors.
a61af66fc99e Initial load
duke
parents:
diff changeset
3983 // I2CAdaptors convert from interpreted java to compiled java.
a61af66fc99e Initial load
duke
parents:
diff changeset
3984 interpreter_frame_pointer(RBP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3985
a61af66fc99e Initial load
duke
parents:
diff changeset
3986 // Stack alignment requirement
a61af66fc99e Initial load
duke
parents:
diff changeset
3987 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
a61af66fc99e Initial load
duke
parents:
diff changeset
3988
a61af66fc99e Initial load
duke
parents:
diff changeset
3989 // Number of stack slots between incoming argument block and the start of
a61af66fc99e Initial load
duke
parents:
diff changeset
3990 // a new frame. The PROLOG must add this many slots to the stack. The
a61af66fc99e Initial load
duke
parents:
diff changeset
3991 // EPILOG must remove this many slots. amd64 needs two slots for
a61af66fc99e Initial load
duke
parents:
diff changeset
3992 // return address.
a61af66fc99e Initial load
duke
parents:
diff changeset
3993 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
a61af66fc99e Initial load
duke
parents:
diff changeset
3994
a61af66fc99e Initial load
duke
parents:
diff changeset
3995 // Number of outgoing stack slots killed above the out_preserve_stack_slots
a61af66fc99e Initial load
duke
parents:
diff changeset
3996 // for calls to C. Supports the var-args backing area for register parms.
a61af66fc99e Initial load
duke
parents:
diff changeset
3997 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
a61af66fc99e Initial load
duke
parents:
diff changeset
3998
a61af66fc99e Initial load
duke
parents:
diff changeset
3999 // The after-PROLOG location of the return address. Location of
a61af66fc99e Initial load
duke
parents:
diff changeset
4000 // return address specifies a type (REG or STACK) and a number
a61af66fc99e Initial load
duke
parents:
diff changeset
4001 // representing the register number (i.e. - use a register name) or
a61af66fc99e Initial load
duke
parents:
diff changeset
4002 // stack slot.
a61af66fc99e Initial load
duke
parents:
diff changeset
4003 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
a61af66fc99e Initial load
duke
parents:
diff changeset
4004 // Otherwise, it is above the locks and verification slot and alignment word
a61af66fc99e Initial load
duke
parents:
diff changeset
4005 return_addr(STACK - 2 +
a61af66fc99e Initial load
duke
parents:
diff changeset
4006 round_to(2 + 2 * VerifyStackAtCalls +
a61af66fc99e Initial load
duke
parents:
diff changeset
4007 Compile::current()->fixed_slots(),
a61af66fc99e Initial load
duke
parents:
diff changeset
4008 WordsPerLong * 2));
a61af66fc99e Initial load
duke
parents:
diff changeset
4009
a61af66fc99e Initial load
duke
parents:
diff changeset
4010 // Body of function which returns an integer array locating
a61af66fc99e Initial load
duke
parents:
diff changeset
4011 // arguments either in registers or in stack slots. Passed an array
a61af66fc99e Initial load
duke
parents:
diff changeset
4012 // of ideal registers called "sig" and a "length" count. Stack-slot
a61af66fc99e Initial load
duke
parents:
diff changeset
4013 // offsets are based on outgoing arguments, i.e. a CALLER setting up
a61af66fc99e Initial load
duke
parents:
diff changeset
4014 // arguments for a CALLEE. Incoming stack arguments are
a61af66fc99e Initial load
duke
parents:
diff changeset
4015 // automatically biased by the preserve_stack_slots field above.
a61af66fc99e Initial load
duke
parents:
diff changeset
4016
a61af66fc99e Initial load
duke
parents:
diff changeset
4017 calling_convention
a61af66fc99e Initial load
duke
parents:
diff changeset
4018 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4019 // No difference between ingoing/outgoing just pass false
a61af66fc99e Initial load
duke
parents:
diff changeset
4020 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
a61af66fc99e Initial load
duke
parents:
diff changeset
4021 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4022
a61af66fc99e Initial load
duke
parents:
diff changeset
4023 c_calling_convention
a61af66fc99e Initial load
duke
parents:
diff changeset
4024 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4025 // This is obviously always outgoing
a61af66fc99e Initial load
duke
parents:
diff changeset
4026 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
a61af66fc99e Initial load
duke
parents:
diff changeset
4027 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4028
a61af66fc99e Initial load
duke
parents:
diff changeset
4029 // Location of compiled Java return values. Same as C for now.
a61af66fc99e Initial load
duke
parents:
diff changeset
4030 return_value
a61af66fc99e Initial load
duke
parents:
diff changeset
4031 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4032 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
a61af66fc99e Initial load
duke
parents:
diff changeset
4033 "only return normal values");
a61af66fc99e Initial load
duke
parents:
diff changeset
4034
a61af66fc99e Initial load
duke
parents:
diff changeset
4035 static const int lo[Op_RegL + 1] = {
a61af66fc99e Initial load
duke
parents:
diff changeset
4036 0,
a61af66fc99e Initial load
duke
parents:
diff changeset
4037 0,
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4038 RAX_num, // Op_RegN
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4039 RAX_num, // Op_RegI
a61af66fc99e Initial load
duke
parents:
diff changeset
4040 RAX_num, // Op_RegP
a61af66fc99e Initial load
duke
parents:
diff changeset
4041 XMM0_num, // Op_RegF
a61af66fc99e Initial load
duke
parents:
diff changeset
4042 XMM0_num, // Op_RegD
a61af66fc99e Initial load
duke
parents:
diff changeset
4043 RAX_num // Op_RegL
a61af66fc99e Initial load
duke
parents:
diff changeset
4044 };
a61af66fc99e Initial load
duke
parents:
diff changeset
4045 static const int hi[Op_RegL + 1] = {
a61af66fc99e Initial load
duke
parents:
diff changeset
4046 0,
a61af66fc99e Initial load
duke
parents:
diff changeset
4047 0,
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4048 OptoReg::Bad, // Op_RegN
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4049 OptoReg::Bad, // Op_RegI
a61af66fc99e Initial load
duke
parents:
diff changeset
4050 RAX_H_num, // Op_RegP
a61af66fc99e Initial load
duke
parents:
diff changeset
4051 OptoReg::Bad, // Op_RegF
a61af66fc99e Initial load
duke
parents:
diff changeset
4052 XMM0_H_num, // Op_RegD
a61af66fc99e Initial load
duke
parents:
diff changeset
4053 RAX_H_num // Op_RegL
a61af66fc99e Initial load
duke
parents:
diff changeset
4054 };
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4055 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 1, "missing type");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4056 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
a61af66fc99e Initial load
duke
parents:
diff changeset
4057 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4058 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4059
a61af66fc99e Initial load
duke
parents:
diff changeset
4060 //----------ATTRIBUTES---------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4061 //----------Operand Attributes-------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4062 op_attrib op_cost(0); // Required cost attribute
a61af66fc99e Initial load
duke
parents:
diff changeset
4063
a61af66fc99e Initial load
duke
parents:
diff changeset
4064 //----------Instruction Attributes---------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4065 ins_attrib ins_cost(100); // Required cost attribute
a61af66fc99e Initial load
duke
parents:
diff changeset
4066 ins_attrib ins_size(8); // Required size attribute (in bits)
a61af66fc99e Initial load
duke
parents:
diff changeset
4067 ins_attrib ins_pc_relative(0); // Required PC Relative flag
a61af66fc99e Initial load
duke
parents:
diff changeset
4068 ins_attrib ins_short_branch(0); // Required flag: is this instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
4069 // a non-matching short branch variant
a61af66fc99e Initial load
duke
parents:
diff changeset
4070 // of some long branch?
a61af66fc99e Initial load
duke
parents:
diff changeset
4071 ins_attrib ins_alignment(1); // Required alignment attribute (must
a61af66fc99e Initial load
duke
parents:
diff changeset
4072 // be a power of 2) specifies the
a61af66fc99e Initial load
duke
parents:
diff changeset
4073 // alignment that some part of the
a61af66fc99e Initial load
duke
parents:
diff changeset
4074 // instruction (not necessarily the
a61af66fc99e Initial load
duke
parents:
diff changeset
4075 // start) requires. If > 1, a
a61af66fc99e Initial load
duke
parents:
diff changeset
4076 // compute_padding() function must be
a61af66fc99e Initial load
duke
parents:
diff changeset
4077 // provided for the instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
4078
a61af66fc99e Initial load
duke
parents:
diff changeset
4079 //----------OPERANDS-----------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4080 // Operand definitions must precede instruction definitions for correct parsing
a61af66fc99e Initial load
duke
parents:
diff changeset
4081 // in the ADLC because operands constitute user defined types which are used in
a61af66fc99e Initial load
duke
parents:
diff changeset
4082 // instruction definitions.
a61af66fc99e Initial load
duke
parents:
diff changeset
4083
a61af66fc99e Initial load
duke
parents:
diff changeset
4084 //----------Simple Operands----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4085 // Immediate Operands
a61af66fc99e Initial load
duke
parents:
diff changeset
4086 // Integer Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
4087 operand immI()
a61af66fc99e Initial load
duke
parents:
diff changeset
4088 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4089 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4090
a61af66fc99e Initial load
duke
parents:
diff changeset
4091 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
4092 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4093 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4094 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4095
a61af66fc99e Initial load
duke
parents:
diff changeset
4096 // Constant for test vs zero
a61af66fc99e Initial load
duke
parents:
diff changeset
4097 operand immI0()
a61af66fc99e Initial load
duke
parents:
diff changeset
4098 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4099 predicate(n->get_int() == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4100 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4101
a61af66fc99e Initial load
duke
parents:
diff changeset
4102 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4103 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4104 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4105 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4106
a61af66fc99e Initial load
duke
parents:
diff changeset
4107 // Constant for increment
a61af66fc99e Initial load
duke
parents:
diff changeset
4108 operand immI1()
a61af66fc99e Initial load
duke
parents:
diff changeset
4109 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4110 predicate(n->get_int() == 1);
a61af66fc99e Initial load
duke
parents:
diff changeset
4111 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4112
a61af66fc99e Initial load
duke
parents:
diff changeset
4113 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4114 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4115 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4116 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4117
a61af66fc99e Initial load
duke
parents:
diff changeset
4118 // Constant for decrement
a61af66fc99e Initial load
duke
parents:
diff changeset
4119 operand immI_M1()
a61af66fc99e Initial load
duke
parents:
diff changeset
4120 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4121 predicate(n->get_int() == -1);
a61af66fc99e Initial load
duke
parents:
diff changeset
4122 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4123
a61af66fc99e Initial load
duke
parents:
diff changeset
4124 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4125 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4126 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4127 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4128
a61af66fc99e Initial load
duke
parents:
diff changeset
4129 // Valid scale values for addressing modes
a61af66fc99e Initial load
duke
parents:
diff changeset
4130 operand immI2()
a61af66fc99e Initial load
duke
parents:
diff changeset
4131 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4132 predicate(0 <= n->get_int() && (n->get_int() <= 3));
a61af66fc99e Initial load
duke
parents:
diff changeset
4133 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4134
a61af66fc99e Initial load
duke
parents:
diff changeset
4135 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4136 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4137 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4138
a61af66fc99e Initial load
duke
parents:
diff changeset
4139 operand immI8()
a61af66fc99e Initial load
duke
parents:
diff changeset
4140 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4141 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
a61af66fc99e Initial load
duke
parents:
diff changeset
4142 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4143
a61af66fc99e Initial load
duke
parents:
diff changeset
4144 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
4145 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4146 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4147 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4148
a61af66fc99e Initial load
duke
parents:
diff changeset
4149 operand immI16()
a61af66fc99e Initial load
duke
parents:
diff changeset
4150 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4151 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
a61af66fc99e Initial load
duke
parents:
diff changeset
4152 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4153
a61af66fc99e Initial load
duke
parents:
diff changeset
4154 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
4155 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4156 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4157 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4158
a61af66fc99e Initial load
duke
parents:
diff changeset
4159 // Constant for long shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
4160 operand immI_32()
a61af66fc99e Initial load
duke
parents:
diff changeset
4161 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4162 predicate( n->get_int() == 32 );
a61af66fc99e Initial load
duke
parents:
diff changeset
4163 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4164
a61af66fc99e Initial load
duke
parents:
diff changeset
4165 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4166 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4167 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4168 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4169
a61af66fc99e Initial load
duke
parents:
diff changeset
4170 // Constant for long shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
4171 operand immI_64()
a61af66fc99e Initial load
duke
parents:
diff changeset
4172 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4173 predicate( n->get_int() == 64 );
a61af66fc99e Initial load
duke
parents:
diff changeset
4174 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4175
a61af66fc99e Initial load
duke
parents:
diff changeset
4176 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4177 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4178 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4179 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4180
a61af66fc99e Initial load
duke
parents:
diff changeset
4181 // Pointer Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
4182 operand immP()
a61af66fc99e Initial load
duke
parents:
diff changeset
4183 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4184 match(ConP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4185
a61af66fc99e Initial load
duke
parents:
diff changeset
4186 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
4187 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4188 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4189 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4190
a61af66fc99e Initial load
duke
parents:
diff changeset
4191 // NULL Pointer Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
4192 operand immP0()
a61af66fc99e Initial load
duke
parents:
diff changeset
4193 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4194 predicate(n->get_ptr() == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4195 match(ConP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4196
a61af66fc99e Initial load
duke
parents:
diff changeset
4197 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
4198 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4199 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4200 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4201
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
4202 operand immP_poll() %{
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
4203 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
4204 match(ConP);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
4205
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
4206 // formats are generated automatically for constants and base registers
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
4207 format %{ %}
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
4208 interface(CONST_INTER);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
4209 %}
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
4210
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4211 // Pointer Immediate
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4212 operand immN() %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4213 match(ConN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4214
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4215 op_cost(10);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4216 format %{ %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4217 interface(CONST_INTER);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4218 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4219
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4220 // NULL Pointer Immediate
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4221 operand immN0() %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4222 predicate(n->get_narrowcon() == 0);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4223 match(ConN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4224
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4225 op_cost(5);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4226 format %{ %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4227 interface(CONST_INTER);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4228 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4229
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4230 operand immP31()
a61af66fc99e Initial load
duke
parents:
diff changeset
4231 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4232 predicate(!n->as_Type()->type()->isa_oopptr()
a61af66fc99e Initial load
duke
parents:
diff changeset
4233 && (n->get_ptr() >> 31) == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4234 match(ConP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4235
a61af66fc99e Initial load
duke
parents:
diff changeset
4236 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
4237 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4238 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4239 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4240
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4241
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4242 // Long Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
4243 operand immL()
a61af66fc99e Initial load
duke
parents:
diff changeset
4244 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4245 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4246
a61af66fc99e Initial load
duke
parents:
diff changeset
4247 op_cost(20);
a61af66fc99e Initial load
duke
parents:
diff changeset
4248 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4249 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4250 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4251
a61af66fc99e Initial load
duke
parents:
diff changeset
4252 // Long Immediate 8-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
4253 operand immL8()
a61af66fc99e Initial load
duke
parents:
diff changeset
4254 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4255 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
a61af66fc99e Initial load
duke
parents:
diff changeset
4256 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4257
a61af66fc99e Initial load
duke
parents:
diff changeset
4258 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
4259 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4260 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4261 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4262
a61af66fc99e Initial load
duke
parents:
diff changeset
4263 // Long Immediate 32-bit unsigned
a61af66fc99e Initial load
duke
parents:
diff changeset
4264 operand immUL32()
a61af66fc99e Initial load
duke
parents:
diff changeset
4265 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4266 predicate(n->get_long() == (unsigned int) (n->get_long()));
a61af66fc99e Initial load
duke
parents:
diff changeset
4267 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4268
a61af66fc99e Initial load
duke
parents:
diff changeset
4269 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
4270 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4271 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4272 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4273
a61af66fc99e Initial load
duke
parents:
diff changeset
4274 // Long Immediate 32-bit signed
a61af66fc99e Initial load
duke
parents:
diff changeset
4275 operand immL32()
a61af66fc99e Initial load
duke
parents:
diff changeset
4276 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4277 predicate(n->get_long() == (int) (n->get_long()));
a61af66fc99e Initial load
duke
parents:
diff changeset
4278 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4279
a61af66fc99e Initial load
duke
parents:
diff changeset
4280 op_cost(15);
a61af66fc99e Initial load
duke
parents:
diff changeset
4281 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4282 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4283 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4284
a61af66fc99e Initial load
duke
parents:
diff changeset
4285 // Long Immediate zero
a61af66fc99e Initial load
duke
parents:
diff changeset
4286 operand immL0()
a61af66fc99e Initial load
duke
parents:
diff changeset
4287 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4288 predicate(n->get_long() == 0L);
a61af66fc99e Initial load
duke
parents:
diff changeset
4289 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4290
a61af66fc99e Initial load
duke
parents:
diff changeset
4291 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
4292 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4293 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4294 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4295
a61af66fc99e Initial load
duke
parents:
diff changeset
4296 // Constant for increment
a61af66fc99e Initial load
duke
parents:
diff changeset
4297 operand immL1()
a61af66fc99e Initial load
duke
parents:
diff changeset
4298 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4299 predicate(n->get_long() == 1);
a61af66fc99e Initial load
duke
parents:
diff changeset
4300 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4301
a61af66fc99e Initial load
duke
parents:
diff changeset
4302 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4303 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4304 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4305
a61af66fc99e Initial load
duke
parents:
diff changeset
4306 // Constant for decrement
a61af66fc99e Initial load
duke
parents:
diff changeset
4307 operand immL_M1()
a61af66fc99e Initial load
duke
parents:
diff changeset
4308 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4309 predicate(n->get_long() == -1);
a61af66fc99e Initial load
duke
parents:
diff changeset
4310 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4311
a61af66fc99e Initial load
duke
parents:
diff changeset
4312 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4313 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4314 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4315
a61af66fc99e Initial load
duke
parents:
diff changeset
4316 // Long Immediate: the value 10
a61af66fc99e Initial load
duke
parents:
diff changeset
4317 operand immL10()
a61af66fc99e Initial load
duke
parents:
diff changeset
4318 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4319 predicate(n->get_long() == 10);
a61af66fc99e Initial load
duke
parents:
diff changeset
4320 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4321
a61af66fc99e Initial load
duke
parents:
diff changeset
4322 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4323 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4324 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4325
a61af66fc99e Initial load
duke
parents:
diff changeset
4326 // Long immediate from 0 to 127.
a61af66fc99e Initial load
duke
parents:
diff changeset
4327 // Used for a shorter form of long mul by 10.
a61af66fc99e Initial load
duke
parents:
diff changeset
4328 operand immL_127()
a61af66fc99e Initial load
duke
parents:
diff changeset
4329 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4330 predicate(0 <= n->get_long() && n->get_long() < 0x80);
a61af66fc99e Initial load
duke
parents:
diff changeset
4331 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4332
a61af66fc99e Initial load
duke
parents:
diff changeset
4333 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
4334 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4335 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4336 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4337
a61af66fc99e Initial load
duke
parents:
diff changeset
4338 // Long Immediate: low 32-bit mask
a61af66fc99e Initial load
duke
parents:
diff changeset
4339 operand immL_32bits()
a61af66fc99e Initial load
duke
parents:
diff changeset
4340 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4341 predicate(n->get_long() == 0xFFFFFFFFL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4342 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4343 op_cost(20);
a61af66fc99e Initial load
duke
parents:
diff changeset
4344
a61af66fc99e Initial load
duke
parents:
diff changeset
4345 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4346 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4347 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4348
a61af66fc99e Initial load
duke
parents:
diff changeset
4349 // Float Immediate zero
a61af66fc99e Initial load
duke
parents:
diff changeset
4350 operand immF0()
a61af66fc99e Initial load
duke
parents:
diff changeset
4351 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4352 predicate(jint_cast(n->getf()) == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4353 match(ConF);
a61af66fc99e Initial load
duke
parents:
diff changeset
4354
a61af66fc99e Initial load
duke
parents:
diff changeset
4355 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
4356 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4357 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4358 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4359
a61af66fc99e Initial load
duke
parents:
diff changeset
4360 // Float Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
4361 operand immF()
a61af66fc99e Initial load
duke
parents:
diff changeset
4362 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4363 match(ConF);
a61af66fc99e Initial load
duke
parents:
diff changeset
4364
a61af66fc99e Initial load
duke
parents:
diff changeset
4365 op_cost(15);
a61af66fc99e Initial load
duke
parents:
diff changeset
4366 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4367 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4368 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4369
a61af66fc99e Initial load
duke
parents:
diff changeset
4370 // Double Immediate zero
a61af66fc99e Initial load
duke
parents:
diff changeset
4371 operand immD0()
a61af66fc99e Initial load
duke
parents:
diff changeset
4372 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4373 predicate(jlong_cast(n->getd()) == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4374 match(ConD);
a61af66fc99e Initial load
duke
parents:
diff changeset
4375
a61af66fc99e Initial load
duke
parents:
diff changeset
4376 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
4377 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4378 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4379 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4380
a61af66fc99e Initial load
duke
parents:
diff changeset
4381 // Double Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
4382 operand immD()
a61af66fc99e Initial load
duke
parents:
diff changeset
4383 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4384 match(ConD);
a61af66fc99e Initial load
duke
parents:
diff changeset
4385
a61af66fc99e Initial load
duke
parents:
diff changeset
4386 op_cost(15);
a61af66fc99e Initial load
duke
parents:
diff changeset
4387 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4388 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4389 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4390
a61af66fc99e Initial load
duke
parents:
diff changeset
4391 // Immediates for special shifts (sign extend)
a61af66fc99e Initial load
duke
parents:
diff changeset
4392
a61af66fc99e Initial load
duke
parents:
diff changeset
4393 // Constants for increment
a61af66fc99e Initial load
duke
parents:
diff changeset
4394 operand immI_16()
a61af66fc99e Initial load
duke
parents:
diff changeset
4395 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4396 predicate(n->get_int() == 16);
a61af66fc99e Initial load
duke
parents:
diff changeset
4397 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4398
a61af66fc99e Initial load
duke
parents:
diff changeset
4399 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4400 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4401 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4402
a61af66fc99e Initial load
duke
parents:
diff changeset
4403 operand immI_24()
a61af66fc99e Initial load
duke
parents:
diff changeset
4404 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4405 predicate(n->get_int() == 24);
a61af66fc99e Initial load
duke
parents:
diff changeset
4406 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4407
a61af66fc99e Initial load
duke
parents:
diff changeset
4408 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4409 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4410 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4411
a61af66fc99e Initial load
duke
parents:
diff changeset
4412 // Constant for byte-wide masking
a61af66fc99e Initial load
duke
parents:
diff changeset
4413 operand immI_255()
a61af66fc99e Initial load
duke
parents:
diff changeset
4414 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4415 predicate(n->get_int() == 255);
a61af66fc99e Initial load
duke
parents:
diff changeset
4416 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4417
a61af66fc99e Initial load
duke
parents:
diff changeset
4418 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4419 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4420 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4421
a61af66fc99e Initial load
duke
parents:
diff changeset
4422 // Constant for short-wide masking
a61af66fc99e Initial load
duke
parents:
diff changeset
4423 operand immI_65535()
a61af66fc99e Initial load
duke
parents:
diff changeset
4424 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4425 predicate(n->get_int() == 65535);
a61af66fc99e Initial load
duke
parents:
diff changeset
4426 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4427
a61af66fc99e Initial load
duke
parents:
diff changeset
4428 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4429 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4430 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4431
a61af66fc99e Initial load
duke
parents:
diff changeset
4432 // Constant for byte-wide masking
a61af66fc99e Initial load
duke
parents:
diff changeset
4433 operand immL_255()
a61af66fc99e Initial load
duke
parents:
diff changeset
4434 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4435 predicate(n->get_long() == 255);
a61af66fc99e Initial load
duke
parents:
diff changeset
4436 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4437
a61af66fc99e Initial load
duke
parents:
diff changeset
4438 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4439 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4440 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4441
a61af66fc99e Initial load
duke
parents:
diff changeset
4442 // Constant for short-wide masking
a61af66fc99e Initial load
duke
parents:
diff changeset
4443 operand immL_65535()
a61af66fc99e Initial load
duke
parents:
diff changeset
4444 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4445 predicate(n->get_long() == 65535);
a61af66fc99e Initial load
duke
parents:
diff changeset
4446 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4447
a61af66fc99e Initial load
duke
parents:
diff changeset
4448 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4449 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4450 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4451
a61af66fc99e Initial load
duke
parents:
diff changeset
4452 // Register Operands
a61af66fc99e Initial load
duke
parents:
diff changeset
4453 // Integer Register
a61af66fc99e Initial load
duke
parents:
diff changeset
4454 operand rRegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
4455 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4456 constraint(ALLOC_IN_RC(int_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4457 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4458
a61af66fc99e Initial load
duke
parents:
diff changeset
4459 match(rax_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4460 match(rbx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4461 match(rcx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4462 match(rdx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4463 match(rdi_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4464
a61af66fc99e Initial load
duke
parents:
diff changeset
4465 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4466 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4467 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4468
a61af66fc99e Initial load
duke
parents:
diff changeset
4469 // Special Registers
a61af66fc99e Initial load
duke
parents:
diff changeset
4470 operand rax_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
4471 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4472 constraint(ALLOC_IN_RC(int_rax_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4473 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4474 match(rRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4475
a61af66fc99e Initial load
duke
parents:
diff changeset
4476 format %{ "RAX" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4477 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4478 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4479
a61af66fc99e Initial load
duke
parents:
diff changeset
4480 // Special Registers
a61af66fc99e Initial load
duke
parents:
diff changeset
4481 operand rbx_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
4482 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4483 constraint(ALLOC_IN_RC(int_rbx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4484 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4485 match(rRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4486
a61af66fc99e Initial load
duke
parents:
diff changeset
4487 format %{ "RBX" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4488 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4489 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4490
a61af66fc99e Initial load
duke
parents:
diff changeset
4491 operand rcx_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
4492 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4493 constraint(ALLOC_IN_RC(int_rcx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4494 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4495 match(rRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4496
a61af66fc99e Initial load
duke
parents:
diff changeset
4497 format %{ "RCX" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4498 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4499 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4500
a61af66fc99e Initial load
duke
parents:
diff changeset
4501 operand rdx_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
4502 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4503 constraint(ALLOC_IN_RC(int_rdx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4504 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4505 match(rRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4506
a61af66fc99e Initial load
duke
parents:
diff changeset
4507 format %{ "RDX" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4508 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4509 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4510
a61af66fc99e Initial load
duke
parents:
diff changeset
4511 operand rdi_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
4512 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4513 constraint(ALLOC_IN_RC(int_rdi_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4514 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4515 match(rRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4516
a61af66fc99e Initial load
duke
parents:
diff changeset
4517 format %{ "RDI" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4518 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4519 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4520
a61af66fc99e Initial load
duke
parents:
diff changeset
4521 operand no_rcx_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
4522 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4523 constraint(ALLOC_IN_RC(int_no_rcx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4524 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4525 match(rax_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4526 match(rbx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4527 match(rdx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4528 match(rdi_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4529
a61af66fc99e Initial load
duke
parents:
diff changeset
4530 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4531 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4532 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4533
a61af66fc99e Initial load
duke
parents:
diff changeset
4534 operand no_rax_rdx_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
4535 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4536 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4537 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4538 match(rbx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4539 match(rcx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4540 match(rdi_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
4541
a61af66fc99e Initial load
duke
parents:
diff changeset
4542 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4543 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4544 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4545
a61af66fc99e Initial load
duke
parents:
diff changeset
4546 // Pointer Register
a61af66fc99e Initial load
duke
parents:
diff changeset
4547 operand any_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
4548 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4549 constraint(ALLOC_IN_RC(any_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4550 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4551 match(rax_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4552 match(rbx_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4553 match(rdi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4554 match(rsi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4555 match(rbp_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4556 match(r15_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4557 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4558
a61af66fc99e Initial load
duke
parents:
diff changeset
4559 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4560 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4561 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4562
a61af66fc99e Initial load
duke
parents:
diff changeset
4563 operand rRegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
4564 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4565 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4566 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4567 match(rax_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4568 match(rbx_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4569 match(rdi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4570 match(rsi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4571 match(rbp_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4572 match(r15_RegP); // See Q&A below about r15_RegP.
a61af66fc99e Initial load
duke
parents:
diff changeset
4573
a61af66fc99e Initial load
duke
parents:
diff changeset
4574 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4575 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4576 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4577
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4578 operand rRegN() %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4579 constraint(ALLOC_IN_RC(int_reg));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4580 match(RegN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4581
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4582 format %{ %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4583 interface(REG_INTER);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4584 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4585
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4586 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
a61af66fc99e Initial load
duke
parents:
diff changeset
4587 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
a61af66fc99e Initial load
duke
parents:
diff changeset
4588 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
a61af66fc99e Initial load
duke
parents:
diff changeset
4589 // The output of an instruction is controlled by the allocator, which respects
a61af66fc99e Initial load
duke
parents:
diff changeset
4590 // register class masks, not match rules. Unless an instruction mentions
a61af66fc99e Initial load
duke
parents:
diff changeset
4591 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
a61af66fc99e Initial load
duke
parents:
diff changeset
4592 // by the allocator as an input.
a61af66fc99e Initial load
duke
parents:
diff changeset
4593
a61af66fc99e Initial load
duke
parents:
diff changeset
4594 operand no_rax_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
4595 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4596 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4597 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4598 match(rbx_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4599 match(rsi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4600 match(rdi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4601
a61af66fc99e Initial load
duke
parents:
diff changeset
4602 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4603 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4604 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4605
a61af66fc99e Initial load
duke
parents:
diff changeset
4606 operand no_rbp_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
4607 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4608 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4609 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4610 match(rbx_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4611 match(rsi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4612 match(rdi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4613
a61af66fc99e Initial load
duke
parents:
diff changeset
4614 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4615 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4616 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4617
a61af66fc99e Initial load
duke
parents:
diff changeset
4618 operand no_rax_rbx_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
4619 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4620 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4621 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4622 match(rsi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4623 match(rdi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4624
a61af66fc99e Initial load
duke
parents:
diff changeset
4625 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4626 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4627 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4628
a61af66fc99e Initial load
duke
parents:
diff changeset
4629 // Special Registers
a61af66fc99e Initial load
duke
parents:
diff changeset
4630 // Return a pointer value
a61af66fc99e Initial load
duke
parents:
diff changeset
4631 operand rax_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
4632 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4633 constraint(ALLOC_IN_RC(ptr_rax_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4634 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4635 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4636
a61af66fc99e Initial load
duke
parents:
diff changeset
4637 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4638 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4639 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4640
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4641 // Special Registers
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4642 // Return a compressed pointer value
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4643 operand rax_RegN()
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4644 %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4645 constraint(ALLOC_IN_RC(int_rax_reg));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4646 match(RegN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4647 match(rRegN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4648
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4649 format %{ %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4650 interface(REG_INTER);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4651 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4652
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4653 // Used in AtomicAdd
a61af66fc99e Initial load
duke
parents:
diff changeset
4654 operand rbx_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
4655 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4656 constraint(ALLOC_IN_RC(ptr_rbx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4657 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4658 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4659
a61af66fc99e Initial load
duke
parents:
diff changeset
4660 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4661 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4662 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4663
a61af66fc99e Initial load
duke
parents:
diff changeset
4664 operand rsi_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
4665 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4666 constraint(ALLOC_IN_RC(ptr_rsi_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4667 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4668 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4669
a61af66fc99e Initial load
duke
parents:
diff changeset
4670 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4671 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4672 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4673
a61af66fc99e Initial load
duke
parents:
diff changeset
4674 // Used in rep stosq
a61af66fc99e Initial load
duke
parents:
diff changeset
4675 operand rdi_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
4676 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4677 constraint(ALLOC_IN_RC(ptr_rdi_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4678 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4679 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4680
a61af66fc99e Initial load
duke
parents:
diff changeset
4681 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4682 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4683 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4684
a61af66fc99e Initial load
duke
parents:
diff changeset
4685 operand rbp_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
4686 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4687 constraint(ALLOC_IN_RC(ptr_rbp_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4688 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4689 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4690
a61af66fc99e Initial load
duke
parents:
diff changeset
4691 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4692 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4693 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4694
a61af66fc99e Initial load
duke
parents:
diff changeset
4695 operand r15_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
4696 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4697 constraint(ALLOC_IN_RC(ptr_r15_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4698 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4699 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
4700
a61af66fc99e Initial load
duke
parents:
diff changeset
4701 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4702 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4703 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4704
a61af66fc99e Initial load
duke
parents:
diff changeset
4705 operand rRegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
4706 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4707 constraint(ALLOC_IN_RC(long_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4708 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4709 match(rax_RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4710 match(rdx_RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4711
a61af66fc99e Initial load
duke
parents:
diff changeset
4712 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4713 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4714 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4715
a61af66fc99e Initial load
duke
parents:
diff changeset
4716 // Special Registers
a61af66fc99e Initial load
duke
parents:
diff changeset
4717 operand no_rax_rdx_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
4718 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4719 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4720 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4721 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4722
a61af66fc99e Initial load
duke
parents:
diff changeset
4723 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4724 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4725 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4726
a61af66fc99e Initial load
duke
parents:
diff changeset
4727 operand no_rax_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
4728 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4729 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4730 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4731 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4732 match(rdx_RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4733
a61af66fc99e Initial load
duke
parents:
diff changeset
4734 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4735 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4736 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4737
a61af66fc99e Initial load
duke
parents:
diff changeset
4738 operand no_rcx_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
4739 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4740 constraint(ALLOC_IN_RC(long_no_rcx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4741 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4742 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4743
a61af66fc99e Initial load
duke
parents:
diff changeset
4744 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4745 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4746 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4747
a61af66fc99e Initial load
duke
parents:
diff changeset
4748 operand rax_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
4749 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4750 constraint(ALLOC_IN_RC(long_rax_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4751 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4752 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4753
a61af66fc99e Initial load
duke
parents:
diff changeset
4754 format %{ "RAX" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4755 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4756 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4757
a61af66fc99e Initial load
duke
parents:
diff changeset
4758 operand rcx_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
4759 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4760 constraint(ALLOC_IN_RC(long_rcx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4761 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4762 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4763
a61af66fc99e Initial load
duke
parents:
diff changeset
4764 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4765 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4766 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4767
a61af66fc99e Initial load
duke
parents:
diff changeset
4768 operand rdx_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
4769 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4770 constraint(ALLOC_IN_RC(long_rdx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4771 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4772 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
4773
a61af66fc99e Initial load
duke
parents:
diff changeset
4774 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4775 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4776 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4777
a61af66fc99e Initial load
duke
parents:
diff changeset
4778 // Flags register, used as output of compare instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
4779 operand rFlagsReg()
a61af66fc99e Initial load
duke
parents:
diff changeset
4780 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4781 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load
duke
parents:
diff changeset
4782 match(RegFlags);
a61af66fc99e Initial load
duke
parents:
diff changeset
4783
a61af66fc99e Initial load
duke
parents:
diff changeset
4784 format %{ "RFLAGS" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4785 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4786 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4787
a61af66fc99e Initial load
duke
parents:
diff changeset
4788 // Flags register, used as output of FLOATING POINT compare instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
4789 operand rFlagsRegU()
a61af66fc99e Initial load
duke
parents:
diff changeset
4790 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4791 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load
duke
parents:
diff changeset
4792 match(RegFlags);
a61af66fc99e Initial load
duke
parents:
diff changeset
4793
a61af66fc99e Initial load
duke
parents:
diff changeset
4794 format %{ "RFLAGS_U" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4795 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4796 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4797
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4798 operand rFlagsRegUCF() %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4799 constraint(ALLOC_IN_RC(int_flags));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4800 match(RegFlags);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4801 predicate(false);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4802
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4803 format %{ "RFLAGS_U_CF" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4804 interface(REG_INTER);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4805 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4806
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4807 // Float register operands
a61af66fc99e Initial load
duke
parents:
diff changeset
4808 operand regF()
a61af66fc99e Initial load
duke
parents:
diff changeset
4809 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4810 constraint(ALLOC_IN_RC(float_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4811 match(RegF);
a61af66fc99e Initial load
duke
parents:
diff changeset
4812
a61af66fc99e Initial load
duke
parents:
diff changeset
4813 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4814 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4815 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4816
a61af66fc99e Initial load
duke
parents:
diff changeset
4817 // Double register operands
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
4818 operand regD()
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4819 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4820 constraint(ALLOC_IN_RC(double_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4821 match(RegD);
a61af66fc99e Initial load
duke
parents:
diff changeset
4822
a61af66fc99e Initial load
duke
parents:
diff changeset
4823 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4824 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
4825 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4826
a61af66fc99e Initial load
duke
parents:
diff changeset
4827
a61af66fc99e Initial load
duke
parents:
diff changeset
4828 //----------Memory Operands----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4829 // Direct Memory Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
4830 // operand direct(immP addr)
a61af66fc99e Initial load
duke
parents:
diff changeset
4831 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4832 // match(addr);
a61af66fc99e Initial load
duke
parents:
diff changeset
4833
a61af66fc99e Initial load
duke
parents:
diff changeset
4834 // format %{ "[$addr]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4835 // interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4836 // base(0xFFFFFFFF);
a61af66fc99e Initial load
duke
parents:
diff changeset
4837 // index(0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
4838 // scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4839 // disp($addr);
a61af66fc99e Initial load
duke
parents:
diff changeset
4840 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4841 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4842
a61af66fc99e Initial load
duke
parents:
diff changeset
4843 // Indirect Memory Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
4844 operand indirect(any_RegP reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
4845 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4846 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4847 match(reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4848
a61af66fc99e Initial load
duke
parents:
diff changeset
4849 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4850 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4851 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4852 index(0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
4853 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4854 disp(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4855 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4856 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4857
a61af66fc99e Initial load
duke
parents:
diff changeset
4858 // Indirect Memory Plus Short Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
4859 operand indOffset8(any_RegP reg, immL8 off)
a61af66fc99e Initial load
duke
parents:
diff changeset
4860 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4861 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4862 match(AddP reg off);
a61af66fc99e Initial load
duke
parents:
diff changeset
4863
a61af66fc99e Initial load
duke
parents:
diff changeset
4864 format %{ "[$reg + $off (8-bit)]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4865 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4866 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4867 index(0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
4868 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4869 disp($off);
a61af66fc99e Initial load
duke
parents:
diff changeset
4870 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4871 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4872
a61af66fc99e Initial load
duke
parents:
diff changeset
4873 // Indirect Memory Plus Long Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
4874 operand indOffset32(any_RegP reg, immL32 off)
a61af66fc99e Initial load
duke
parents:
diff changeset
4875 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4876 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4877 match(AddP reg off);
a61af66fc99e Initial load
duke
parents:
diff changeset
4878
a61af66fc99e Initial load
duke
parents:
diff changeset
4879 format %{ "[$reg + $off (32-bit)]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4880 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4881 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4882 index(0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
4883 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4884 disp($off);
a61af66fc99e Initial load
duke
parents:
diff changeset
4885 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4886 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4887
a61af66fc99e Initial load
duke
parents:
diff changeset
4888 // Indirect Memory Plus Index Register Plus Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
4889 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
a61af66fc99e Initial load
duke
parents:
diff changeset
4890 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4891 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4892 match(AddP (AddP reg lreg) off);
a61af66fc99e Initial load
duke
parents:
diff changeset
4893
a61af66fc99e Initial load
duke
parents:
diff changeset
4894 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
4895 format %{"[$reg + $off + $lreg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4896 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4897 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4898 index($lreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4899 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4900 disp($off);
a61af66fc99e Initial load
duke
parents:
diff changeset
4901 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4902 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4903
a61af66fc99e Initial load
duke
parents:
diff changeset
4904 // Indirect Memory Plus Index Register Plus Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
4905 operand indIndex(any_RegP reg, rRegL lreg)
a61af66fc99e Initial load
duke
parents:
diff changeset
4906 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4907 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4908 match(AddP reg lreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4909
a61af66fc99e Initial load
duke
parents:
diff changeset
4910 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
4911 format %{"[$reg + $lreg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4912 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4913 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4914 index($lreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4915 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4916 disp(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4917 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4918 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4919
a61af66fc99e Initial load
duke
parents:
diff changeset
4920 // Indirect Memory Times Scale Plus Index Register
a61af66fc99e Initial load
duke
parents:
diff changeset
4921 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
a61af66fc99e Initial load
duke
parents:
diff changeset
4922 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4923 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4924 match(AddP reg (LShiftL lreg scale));
a61af66fc99e Initial load
duke
parents:
diff changeset
4925
a61af66fc99e Initial load
duke
parents:
diff changeset
4926 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
4927 format %{"[$reg + $lreg << $scale]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4928 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4929 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4930 index($lreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4931 scale($scale);
a61af66fc99e Initial load
duke
parents:
diff changeset
4932 disp(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4933 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4934 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4935
a61af66fc99e Initial load
duke
parents:
diff changeset
4936 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
4937 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
a61af66fc99e Initial load
duke
parents:
diff changeset
4938 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4939 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4940 match(AddP (AddP reg (LShiftL lreg scale)) off);
a61af66fc99e Initial load
duke
parents:
diff changeset
4941
a61af66fc99e Initial load
duke
parents:
diff changeset
4942 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
4943 format %{"[$reg + $off + $lreg << $scale]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4944 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4945 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4946 index($lreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4947 scale($scale);
a61af66fc99e Initial load
duke
parents:
diff changeset
4948 disp($off);
a61af66fc99e Initial load
duke
parents:
diff changeset
4949 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4950 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4951
a61af66fc99e Initial load
duke
parents:
diff changeset
4952 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
4953 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
a61af66fc99e Initial load
duke
parents:
diff changeset
4954 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4955 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
4956 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4957 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
a61af66fc99e Initial load
duke
parents:
diff changeset
4958
a61af66fc99e Initial load
duke
parents:
diff changeset
4959 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
4960 format %{"[$reg + $off + $idx << $scale]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4961 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4962 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
4963 index($idx);
a61af66fc99e Initial load
duke
parents:
diff changeset
4964 scale($scale);
a61af66fc99e Initial load
duke
parents:
diff changeset
4965 disp($off);
a61af66fc99e Initial load
duke
parents:
diff changeset
4966 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4967 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4968
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4969 // Indirect Narrow Oop Plus Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4970 // Note: x86 architecture doesn't support "scale * index + offset" without a base
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4971 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4972 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
4973 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4974 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4975 match(AddP (DecodeN reg) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4976
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4977 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4978 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4979 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4980 base(0xc); // R12
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4981 index($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4982 scale(0x3);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4983 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4984 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4985 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4986
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4987 // Indirect Memory Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4988 operand indirectNarrow(rRegN reg)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4989 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4990 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4991 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4992 match(DecodeN reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4993
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4994 format %{ "[$reg]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4995 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4996 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4997 index(0x4);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4998 scale(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4999 disp(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5000 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5001 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5002
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5003 // Indirect Memory Plus Short Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5004 operand indOffset8Narrow(rRegN reg, immL8 off)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5005 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5006 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5007 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5008 match(AddP (DecodeN reg) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5009
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5010 format %{ "[$reg + $off (8-bit)]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5011 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5012 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5013 index(0x4);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5014 scale(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5015 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5016 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5017 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5018
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5019 // Indirect Memory Plus Long Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5020 operand indOffset32Narrow(rRegN reg, immL32 off)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5021 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5022 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5023 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5024 match(AddP (DecodeN reg) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5025
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5026 format %{ "[$reg + $off (32-bit)]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5027 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5028 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5029 index(0x4);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5030 scale(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5031 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5032 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5033 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5034
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5035 // Indirect Memory Plus Index Register Plus Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5036 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5037 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5038 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5039 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5040 match(AddP (AddP (DecodeN reg) lreg) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5041
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5042 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5043 format %{"[$reg + $off + $lreg]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5044 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5045 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5046 index($lreg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5047 scale(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5048 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5049 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5050 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5051
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5052 // Indirect Memory Plus Index Register Plus Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5053 operand indIndexNarrow(rRegN reg, rRegL lreg)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5054 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5055 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5056 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5057 match(AddP (DecodeN reg) lreg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5058
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5059 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5060 format %{"[$reg + $lreg]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5061 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5062 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5063 index($lreg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5064 scale(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5065 disp(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5066 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5067 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5068
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5069 // Indirect Memory Times Scale Plus Index Register
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5070 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5071 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5072 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5073 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5074 match(AddP (DecodeN reg) (LShiftL lreg scale));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5075
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5076 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5077 format %{"[$reg + $lreg << $scale]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5078 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5079 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5080 index($lreg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5081 scale($scale);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5082 disp(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5083 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5084 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5085
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5086 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5087 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5088 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5089 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5090 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5091 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5092
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5093 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5094 format %{"[$reg + $off + $lreg << $scale]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5095 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5096 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5097 index($lreg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5098 scale($scale);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5099 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5100 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5101 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5102
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5103 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5104 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5105 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5106 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5107 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5108 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5109
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5110 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5111 format %{"[$reg + $off + $idx << $scale]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5112 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5113 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5114 index($idx);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5115 scale($scale);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5116 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5117 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5118 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5119
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5120
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5121 //----------Special Memory Operands--------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5122 // Stack Slot Operand - This operand is used for loading and storing temporary
a61af66fc99e Initial load
duke
parents:
diff changeset
5123 // values on the stack where a match requires a value to
a61af66fc99e Initial load
duke
parents:
diff changeset
5124 // flow through memory.
a61af66fc99e Initial load
duke
parents:
diff changeset
5125 operand stackSlotP(sRegP reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
5126 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5127 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
5128 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load
duke
parents:
diff changeset
5129
a61af66fc99e Initial load
duke
parents:
diff changeset
5130 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5131 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5132 base(0x4); // RSP
a61af66fc99e Initial load
duke
parents:
diff changeset
5133 index(0x4); // No Index
a61af66fc99e Initial load
duke
parents:
diff changeset
5134 scale(0x0); // No Scale
a61af66fc99e Initial load
duke
parents:
diff changeset
5135 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
5136 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5137 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5138
a61af66fc99e Initial load
duke
parents:
diff changeset
5139 operand stackSlotI(sRegI reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
5140 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5141 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
5142 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load
duke
parents:
diff changeset
5143
a61af66fc99e Initial load
duke
parents:
diff changeset
5144 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5145 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5146 base(0x4); // RSP
a61af66fc99e Initial load
duke
parents:
diff changeset
5147 index(0x4); // No Index
a61af66fc99e Initial load
duke
parents:
diff changeset
5148 scale(0x0); // No Scale
a61af66fc99e Initial load
duke
parents:
diff changeset
5149 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
5150 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5151 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5152
a61af66fc99e Initial load
duke
parents:
diff changeset
5153 operand stackSlotF(sRegF reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
5154 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5155 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
5156 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load
duke
parents:
diff changeset
5157
a61af66fc99e Initial load
duke
parents:
diff changeset
5158 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5159 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5160 base(0x4); // RSP
a61af66fc99e Initial load
duke
parents:
diff changeset
5161 index(0x4); // No Index
a61af66fc99e Initial load
duke
parents:
diff changeset
5162 scale(0x0); // No Scale
a61af66fc99e Initial load
duke
parents:
diff changeset
5163 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
5164 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5165 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5166
a61af66fc99e Initial load
duke
parents:
diff changeset
5167 operand stackSlotD(sRegD reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
5168 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5169 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
5170 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load
duke
parents:
diff changeset
5171
a61af66fc99e Initial load
duke
parents:
diff changeset
5172 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5173 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5174 base(0x4); // RSP
a61af66fc99e Initial load
duke
parents:
diff changeset
5175 index(0x4); // No Index
a61af66fc99e Initial load
duke
parents:
diff changeset
5176 scale(0x0); // No Scale
a61af66fc99e Initial load
duke
parents:
diff changeset
5177 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
5178 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5179 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5180 operand stackSlotL(sRegL reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
5181 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5182 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
5183 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load
duke
parents:
diff changeset
5184
a61af66fc99e Initial load
duke
parents:
diff changeset
5185 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5186 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5187 base(0x4); // RSP
a61af66fc99e Initial load
duke
parents:
diff changeset
5188 index(0x4); // No Index
a61af66fc99e Initial load
duke
parents:
diff changeset
5189 scale(0x0); // No Scale
a61af66fc99e Initial load
duke
parents:
diff changeset
5190 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
5191 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5192 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5193
a61af66fc99e Initial load
duke
parents:
diff changeset
5194 //----------Conditional Branch Operands----------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5195 // Comparison Op - This is the operation of the comparison, and is limited to
a61af66fc99e Initial load
duke
parents:
diff changeset
5196 // the following set of codes:
a61af66fc99e Initial load
duke
parents:
diff changeset
5197 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
a61af66fc99e Initial load
duke
parents:
diff changeset
5198 //
a61af66fc99e Initial load
duke
parents:
diff changeset
5199 // Other attributes of the comparison, such as unsignedness, are specified
a61af66fc99e Initial load
duke
parents:
diff changeset
5200 // by the comparison instruction that sets a condition code flags register.
a61af66fc99e Initial load
duke
parents:
diff changeset
5201 // That result is represented by a flags operand whose subtype is appropriate
a61af66fc99e Initial load
duke
parents:
diff changeset
5202 // to the unsignedness (etc.) of the comparison.
a61af66fc99e Initial load
duke
parents:
diff changeset
5203 //
a61af66fc99e Initial load
duke
parents:
diff changeset
5204 // Later, the instruction which matches both the Comparison Op (a Bool) and
a61af66fc99e Initial load
duke
parents:
diff changeset
5205 // the flags (produced by the Cmp) specifies the coding of the comparison op
a61af66fc99e Initial load
duke
parents:
diff changeset
5206 // by matching a specific subtype of Bool operand below, such as cmpOpU.
a61af66fc99e Initial load
duke
parents:
diff changeset
5207
a61af66fc99e Initial load
duke
parents:
diff changeset
5208 // Comparision Code
a61af66fc99e Initial load
duke
parents:
diff changeset
5209 operand cmpOp()
a61af66fc99e Initial load
duke
parents:
diff changeset
5210 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5211 match(Bool);
a61af66fc99e Initial load
duke
parents:
diff changeset
5212
a61af66fc99e Initial load
duke
parents:
diff changeset
5213 format %{ "" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5214 interface(COND_INTER) %{
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5215 equal(0x4, "e");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5216 not_equal(0x5, "ne");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5217 less(0xC, "l");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5218 greater_equal(0xD, "ge");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5219 less_equal(0xE, "le");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5220 greater(0xF, "g");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5221 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5222 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5223
a61af66fc99e Initial load
duke
parents:
diff changeset
5224 // Comparison Code, unsigned compare. Used by FP also, with
a61af66fc99e Initial load
duke
parents:
diff changeset
5225 // C2 (unordered) turned into GT or LT already. The other bits
a61af66fc99e Initial load
duke
parents:
diff changeset
5226 // C0 and C3 are turned into Carry & Zero flags.
a61af66fc99e Initial load
duke
parents:
diff changeset
5227 operand cmpOpU()
a61af66fc99e Initial load
duke
parents:
diff changeset
5228 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5229 match(Bool);
a61af66fc99e Initial load
duke
parents:
diff changeset
5230
a61af66fc99e Initial load
duke
parents:
diff changeset
5231 format %{ "" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5232 interface(COND_INTER) %{
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5233 equal(0x4, "e");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5234 not_equal(0x5, "ne");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5235 less(0x2, "b");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5236 greater_equal(0x3, "nb");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5237 less_equal(0x6, "be");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5238 greater(0x7, "nbe");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5239 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5240 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5241
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5242
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5243 // Floating comparisons that don't require any fixup for the unordered case
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5244 operand cmpOpUCF() %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5245 match(Bool);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5246 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5247 n->as_Bool()->_test._test == BoolTest::ge ||
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5248 n->as_Bool()->_test._test == BoolTest::le ||
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5249 n->as_Bool()->_test._test == BoolTest::gt);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5250 format %{ "" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5251 interface(COND_INTER) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5252 equal(0x4, "e");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5253 not_equal(0x5, "ne");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5254 less(0x2, "b");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5255 greater_equal(0x3, "nb");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5256 less_equal(0x6, "be");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5257 greater(0x7, "nbe");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5258 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5259 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5260
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5261
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5262 // Floating comparisons that can be fixed up with extra conditional jumps
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5263 operand cmpOpUCF2() %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5264 match(Bool);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5265 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5266 n->as_Bool()->_test._test == BoolTest::eq);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5267 format %{ "" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5268 interface(COND_INTER) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5269 equal(0x4, "e");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5270 not_equal(0x5, "ne");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5271 less(0x2, "b");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5272 greater_equal(0x3, "nb");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5273 less_equal(0x6, "be");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
5274 greater(0x7, "nbe");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5275 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5276 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5277
a61af66fc99e Initial load
duke
parents:
diff changeset
5278
a61af66fc99e Initial load
duke
parents:
diff changeset
5279 //----------OPERAND CLASSES----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5280 // Operand Classes are groups of operands that are used as to simplify
605
98cb887364d3 6810672: Comment typos
twisti
parents: 569
diff changeset
5281 // instruction definitions by not requiring the AD writer to specify separate
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5282 // instructions for every form of operand when the instruction accepts
a61af66fc99e Initial load
duke
parents:
diff changeset
5283 // multiple operand types with the same basic encoding and format. The classic
a61af66fc99e Initial load
duke
parents:
diff changeset
5284 // case of this is memory operands.
a61af66fc99e Initial load
duke
parents:
diff changeset
5285
a61af66fc99e Initial load
duke
parents:
diff changeset
5286 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5287 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5288 indCompressedOopOffset,
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5289 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5290 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5291 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5292
a61af66fc99e Initial load
duke
parents:
diff changeset
5293 //----------PIPELINE-----------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5294 // Rules which define the behavior of the target architectures pipeline.
a61af66fc99e Initial load
duke
parents:
diff changeset
5295 pipeline %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5296
a61af66fc99e Initial load
duke
parents:
diff changeset
5297 //----------ATTRIBUTES---------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5298 attributes %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5299 variable_size_instructions; // Fixed size instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
5300 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
a61af66fc99e Initial load
duke
parents:
diff changeset
5301 instruction_unit_size = 1; // An instruction is 1 bytes long
a61af66fc99e Initial load
duke
parents:
diff changeset
5302 instruction_fetch_unit_size = 16; // The processor fetches one line
a61af66fc99e Initial load
duke
parents:
diff changeset
5303 instruction_fetch_units = 1; // of 16 bytes
a61af66fc99e Initial load
duke
parents:
diff changeset
5304
a61af66fc99e Initial load
duke
parents:
diff changeset
5305 // List of nop instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
5306 nops( MachNop );
a61af66fc99e Initial load
duke
parents:
diff changeset
5307 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5308
a61af66fc99e Initial load
duke
parents:
diff changeset
5309 //----------RESOURCES----------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5310 // Resources are the functional units available to the machine
a61af66fc99e Initial load
duke
parents:
diff changeset
5311
a61af66fc99e Initial load
duke
parents:
diff changeset
5312 // Generic P2/P3 pipeline
a61af66fc99e Initial load
duke
parents:
diff changeset
5313 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
a61af66fc99e Initial load
duke
parents:
diff changeset
5314 // 3 instructions decoded per cycle.
a61af66fc99e Initial load
duke
parents:
diff changeset
5315 // 2 load/store ops per cycle, 1 branch, 1 FPU,
a61af66fc99e Initial load
duke
parents:
diff changeset
5316 // 3 ALU op, only ALU0 handles mul instructions.
a61af66fc99e Initial load
duke
parents:
diff changeset
5317 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
a61af66fc99e Initial load
duke
parents:
diff changeset
5318 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
a61af66fc99e Initial load
duke
parents:
diff changeset
5319 BR, FPU,
a61af66fc99e Initial load
duke
parents:
diff changeset
5320 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5321
a61af66fc99e Initial load
duke
parents:
diff changeset
5322 //----------PIPELINE DESCRIPTION-----------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5323 // Pipeline Description specifies the stages in the machine's pipeline
a61af66fc99e Initial load
duke
parents:
diff changeset
5324
a61af66fc99e Initial load
duke
parents:
diff changeset
5325 // Generic P2/P3 pipeline
a61af66fc99e Initial load
duke
parents:
diff changeset
5326 pipe_desc(S0, S1, S2, S3, S4, S5);
a61af66fc99e Initial load
duke
parents:
diff changeset
5327
a61af66fc99e Initial load
duke
parents:
diff changeset
5328 //----------PIPELINE CLASSES---------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5329 // Pipeline Classes describe the stages in which input and output are
a61af66fc99e Initial load
duke
parents:
diff changeset
5330 // referenced by the hardware pipeline.
a61af66fc99e Initial load
duke
parents:
diff changeset
5331
a61af66fc99e Initial load
duke
parents:
diff changeset
5332 // Naming convention: ialu or fpu
a61af66fc99e Initial load
duke
parents:
diff changeset
5333 // Then: _reg
a61af66fc99e Initial load
duke
parents:
diff changeset
5334 // Then: _reg if there is a 2nd register
a61af66fc99e Initial load
duke
parents:
diff changeset
5335 // Then: _long if it's a pair of instructions implementing a long
a61af66fc99e Initial load
duke
parents:
diff changeset
5336 // Then: _fat if it requires the big decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
5337 // Or: _mem if it requires the big decoder and a memory unit.
a61af66fc99e Initial load
duke
parents:
diff changeset
5338
a61af66fc99e Initial load
duke
parents:
diff changeset
5339 // Integer ALU reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5340 pipe_class ialu_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
5341 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5342 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5343 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5344 dst : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5345 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
5346 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
5347 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5348
a61af66fc99e Initial load
duke
parents:
diff changeset
5349 // Long ALU reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5350 pipe_class ialu_reg_long(rRegL dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
5351 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5352 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5353 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5354 dst : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5355 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
5356 ALU : S3(2); // both alus
a61af66fc99e Initial load
duke
parents:
diff changeset
5357 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5358
a61af66fc99e Initial load
duke
parents:
diff changeset
5359 // Integer ALU reg operation using big decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
5360 pipe_class ialu_reg_fat(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
5361 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5362 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5363 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5364 dst : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5365 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5366 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
5367 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5368
a61af66fc99e Initial load
duke
parents:
diff changeset
5369 // Long ALU reg operation using big decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
5370 pipe_class ialu_reg_long_fat(rRegL dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
5371 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5372 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5373 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5374 dst : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5375 D0 : S0(2); // big decoder only; twice
a61af66fc99e Initial load
duke
parents:
diff changeset
5376 ALU : S3(2); // any 2 alus
a61af66fc99e Initial load
duke
parents:
diff changeset
5377 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5378
a61af66fc99e Initial load
duke
parents:
diff changeset
5379 // Integer ALU reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5380 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5381 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5382 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5383 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5384 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5385 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
5386 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
5387 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5388
a61af66fc99e Initial load
duke
parents:
diff changeset
5389 // Long ALU reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5390 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5391 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5392 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5393 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5394 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5395 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
5396 ALU : S3(2); // both alus
a61af66fc99e Initial load
duke
parents:
diff changeset
5397 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5398
a61af66fc99e Initial load
duke
parents:
diff changeset
5399 // Integer ALU reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5400 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5401 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5402 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5403 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5404 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5405 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5406 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
5407 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5408
a61af66fc99e Initial load
duke
parents:
diff changeset
5409 // Long ALU reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5410 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5411 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5412 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5413 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5414 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5415 D0 : S0(2); // big decoder only; twice
a61af66fc99e Initial load
duke
parents:
diff changeset
5416 ALU : S3(2); // both alus
a61af66fc99e Initial load
duke
parents:
diff changeset
5417 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5418
a61af66fc99e Initial load
duke
parents:
diff changeset
5419 // Integer ALU reg-mem operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5420 pipe_class ialu_reg_mem(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5421 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5422 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5423 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5424 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5425 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5426 ALU : S4; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
5427 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
5428 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5429
a61af66fc99e Initial load
duke
parents:
diff changeset
5430 // Integer mem operation (prefetch)
a61af66fc99e Initial load
duke
parents:
diff changeset
5431 pipe_class ialu_mem(memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5432 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5433 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5434 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5435 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5436 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
5437 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5438
a61af66fc99e Initial load
duke
parents:
diff changeset
5439 // Integer Store to Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
5440 pipe_class ialu_mem_reg(memory mem, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5441 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5442 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5443 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5444 src : S5(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5445 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5446 ALU : S4; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
5447 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
5448 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5449
a61af66fc99e Initial load
duke
parents:
diff changeset
5450 // // Long Store to Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
5451 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5452 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5453 // instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5454 // mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5455 // src : S5(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5456 // D0 : S0(2); // big decoder only; twice
a61af66fc99e Initial load
duke
parents:
diff changeset
5457 // ALU : S4(2); // any 2 alus
a61af66fc99e Initial load
duke
parents:
diff changeset
5458 // MEM : S3(2); // Both mems
a61af66fc99e Initial load
duke
parents:
diff changeset
5459 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5460
a61af66fc99e Initial load
duke
parents:
diff changeset
5461 // Integer Store to Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
5462 pipe_class ialu_mem_imm(memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5463 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5464 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5465 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5466 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5467 ALU : S4; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
5468 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
5469 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5470
a61af66fc99e Initial load
duke
parents:
diff changeset
5471 // Integer ALU0 reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5472 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5473 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5474 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5475 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5476 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5477 D0 : S0; // Big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5478 ALU0 : S3; // only alu0
a61af66fc99e Initial load
duke
parents:
diff changeset
5479 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5480
a61af66fc99e Initial load
duke
parents:
diff changeset
5481 // Integer ALU0 reg-mem operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5482 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5483 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5484 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5485 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5486 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5487 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5488 ALU0 : S4; // ALU0 only
a61af66fc99e Initial load
duke
parents:
diff changeset
5489 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
5490 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5491
a61af66fc99e Initial load
duke
parents:
diff changeset
5492 // Integer ALU reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5493 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
5494 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5495 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5496 cr : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5497 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5498 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5499 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
5500 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
5501 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5502
a61af66fc99e Initial load
duke
parents:
diff changeset
5503 // Integer ALU reg-imm operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5504 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
5505 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5506 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5507 cr : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5508 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5509 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
5510 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
5511 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5512
a61af66fc99e Initial load
duke
parents:
diff changeset
5513 // Integer ALU reg-mem operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5514 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
5515 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5516 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5517 cr : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5518 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5519 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5520 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5521 ALU : S4; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
5522 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
5523 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5524
a61af66fc99e Initial load
duke
parents:
diff changeset
5525 // Conditional move reg-reg
a61af66fc99e Initial load
duke
parents:
diff changeset
5526 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
a61af66fc99e Initial load
duke
parents:
diff changeset
5527 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5528 instruction_count(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5529 y : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5530 q : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5531 p : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5532 DECODE : S0(4); // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
5533 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5534
a61af66fc99e Initial load
duke
parents:
diff changeset
5535 // Conditional move reg-reg
a61af66fc99e Initial load
duke
parents:
diff changeset
5536 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
5537 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5538 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5539 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5540 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5541 cr : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5542 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
5543 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5544
a61af66fc99e Initial load
duke
parents:
diff changeset
5545 // Conditional move reg-mem
a61af66fc99e Initial load
duke
parents:
diff changeset
5546 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5547 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5548 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5549 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5550 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5551 cr : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5552 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
5553 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
5554 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5555
a61af66fc99e Initial load
duke
parents:
diff changeset
5556 // Conditional move reg-reg long
a61af66fc99e Initial load
duke
parents:
diff changeset
5557 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5558 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5559 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5560 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5561 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5562 cr : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5563 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
5564 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5565
a61af66fc99e Initial load
duke
parents:
diff changeset
5566 // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5567 // // Conditional move double reg-reg
a61af66fc99e Initial load
duke
parents:
diff changeset
5568 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5569 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5570 // single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5571 // dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5572 // src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5573 // cr : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5574 // DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
5575 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5576
a61af66fc99e Initial load
duke
parents:
diff changeset
5577 // Float reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5578 pipe_class fpu_reg(regD dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
5579 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5580 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5581 dst : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5582 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
5583 FPU : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
5584 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5585
a61af66fc99e Initial load
duke
parents:
diff changeset
5586 // Float reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5587 pipe_class fpu_reg_reg(regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5588 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5589 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5590 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5591 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5592 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
5593 FPU : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
5594 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5595
a61af66fc99e Initial load
duke
parents:
diff changeset
5596 // Float reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5597 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
5598 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5599 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
5600 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5601 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5602 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5603 DECODE : S0(3); // any 3 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
5604 FPU : S3(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5605 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5606
a61af66fc99e Initial load
duke
parents:
diff changeset
5607 // Float reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5608 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
a61af66fc99e Initial load
duke
parents:
diff changeset
5609 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5610 instruction_count(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5611 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5612 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5613 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5614 src3 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5615 DECODE : S0(4); // any 3 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
5616 FPU : S3(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5617 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5618
a61af66fc99e Initial load
duke
parents:
diff changeset
5619 // Float reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5620 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
a61af66fc99e Initial load
duke
parents:
diff changeset
5621 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5622 instruction_count(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
5623 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5624 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5625 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5626 src3 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5627 DECODE : S1(3); // any 3 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
5628 D0 : S0; // Big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5629 FPU : S3(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5630 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
5631 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5632
a61af66fc99e Initial load
duke
parents:
diff changeset
5633 // Float reg-mem operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5634 pipe_class fpu_reg_mem(regD dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5635 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5636 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5637 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5638 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5639 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5640 DECODE : S1; // any decoder for FPU POP
a61af66fc99e Initial load
duke
parents:
diff changeset
5641 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
5642 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
5643 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5644
a61af66fc99e Initial load
duke
parents:
diff changeset
5645 // Float reg-mem operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5646 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5647 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5648 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
5649 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5650 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5651 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5652 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5653 DECODE : S1(2); // any decoder for FPU POP
a61af66fc99e Initial load
duke
parents:
diff changeset
5654 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
5655 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
5656 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5657
a61af66fc99e Initial load
duke
parents:
diff changeset
5658 // Float mem-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
5659 pipe_class fpu_mem_reg(memory mem, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5660 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5661 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5662 src : S5(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5663 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5664 DECODE : S0; // any decoder for FPU PUSH
a61af66fc99e Initial load
duke
parents:
diff changeset
5665 D0 : S1; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5666 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
5667 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
5668 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5669
a61af66fc99e Initial load
duke
parents:
diff changeset
5670 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
5671 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5672 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
5673 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5674 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5675 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5676 DECODE : S0(2); // any decoder for FPU PUSH
a61af66fc99e Initial load
duke
parents:
diff changeset
5677 D0 : S1; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5678 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
5679 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
5680 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5681
a61af66fc99e Initial load
duke
parents:
diff changeset
5682 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
5683 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5684 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
5685 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5686 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5687 mem : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5688 DECODE : S0; // any decoder for FPU PUSH
a61af66fc99e Initial load
duke
parents:
diff changeset
5689 D0 : S0(2); // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5690 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
5691 MEM : S3(2); // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
5692 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5693
a61af66fc99e Initial load
duke
parents:
diff changeset
5694 pipe_class fpu_mem_mem(memory dst, memory src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
5695 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5696 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5697 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5698 dst : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5699 D0 : S0(2); // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5700 MEM : S3(2); // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
5701 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5702
a61af66fc99e Initial load
duke
parents:
diff changeset
5703 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
5704 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5705 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
5706 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5707 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5708 dst : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5709 D0 : S0(3); // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5710 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
5711 MEM : S3(3); // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
5712 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5713
a61af66fc99e Initial load
duke
parents:
diff changeset
5714 pipe_class fpu_mem_reg_con(memory mem, regD src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
5715 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5716 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
5717 src1 : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5718 mem : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5719 DECODE : S0; // any decoder for FPU PUSH
a61af66fc99e Initial load
duke
parents:
diff changeset
5720 D0 : S0(2); // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
5721 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
5722 MEM : S3(2); // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
5723 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5724
a61af66fc99e Initial load
duke
parents:
diff changeset
5725 // Float load constant
a61af66fc99e Initial load
duke
parents:
diff changeset
5726 pipe_class fpu_reg_con(regD dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
5727 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5728 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5729 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5730 D0 : S0; // big decoder only for the load
a61af66fc99e Initial load
duke
parents:
diff changeset
5731 DECODE : S1; // any decoder for FPU POP
a61af66fc99e Initial load
duke
parents:
diff changeset
5732 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
5733 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
5734 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5735
a61af66fc99e Initial load
duke
parents:
diff changeset
5736 // Float load constant
a61af66fc99e Initial load
duke
parents:
diff changeset
5737 pipe_class fpu_reg_reg_con(regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5738 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5739 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
5740 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5741 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5742 D0 : S0; // big decoder only for the load
a61af66fc99e Initial load
duke
parents:
diff changeset
5743 DECODE : S1(2); // any decoder for FPU POP
a61af66fc99e Initial load
duke
parents:
diff changeset
5744 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
5745 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
5746 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5747
a61af66fc99e Initial load
duke
parents:
diff changeset
5748 // UnConditional branch
a61af66fc99e Initial load
duke
parents:
diff changeset
5749 pipe_class pipe_jmp(label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
5750 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5751 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5752 BR : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
5753 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5754
a61af66fc99e Initial load
duke
parents:
diff changeset
5755 // Conditional branch
a61af66fc99e Initial load
duke
parents:
diff changeset
5756 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
5757 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5758 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
5759 cr : S1(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5760 BR : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
5761 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5762
a61af66fc99e Initial load
duke
parents:
diff changeset
5763 // Allocation idiom
a61af66fc99e Initial load
duke
parents:
diff changeset
5764 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
a61af66fc99e Initial load
duke
parents:
diff changeset
5765 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5766 instruction_count(1); force_serialization;
a61af66fc99e Initial load
duke
parents:
diff changeset
5767 fixed_latency(6);
a61af66fc99e Initial load
duke
parents:
diff changeset
5768 heap_ptr : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
5769 DECODE : S0(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
5770 D0 : S2;
a61af66fc99e Initial load
duke
parents:
diff changeset
5771 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
5772 ALU : S3(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5773 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
5774 BR : S5;
a61af66fc99e Initial load
duke
parents:
diff changeset
5775 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5776
a61af66fc99e Initial load
duke
parents:
diff changeset
5777 // Generic big/slow expanded idiom
a61af66fc99e Initial load
duke
parents:
diff changeset
5778 pipe_class pipe_slow()
a61af66fc99e Initial load
duke
parents:
diff changeset
5779 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5780 instruction_count(10); multiple_bundles; force_serialization;
a61af66fc99e Initial load
duke
parents:
diff changeset
5781 fixed_latency(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
5782 D0 : S0(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5783 MEM : S3(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5784 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5785
a61af66fc99e Initial load
duke
parents:
diff changeset
5786 // The real do-nothing guy
a61af66fc99e Initial load
duke
parents:
diff changeset
5787 pipe_class empty()
a61af66fc99e Initial load
duke
parents:
diff changeset
5788 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5789 instruction_count(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
5790 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5791
a61af66fc99e Initial load
duke
parents:
diff changeset
5792 // Define the class for the Nop node
a61af66fc99e Initial load
duke
parents:
diff changeset
5793 define
a61af66fc99e Initial load
duke
parents:
diff changeset
5794 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5795 MachNop = empty;
a61af66fc99e Initial load
duke
parents:
diff changeset
5796 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5797
a61af66fc99e Initial load
duke
parents:
diff changeset
5798 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5799
a61af66fc99e Initial load
duke
parents:
diff changeset
5800 //----------INSTRUCTIONS-------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5801 //
a61af66fc99e Initial load
duke
parents:
diff changeset
5802 // match -- States which machine-independent subtree may be replaced
a61af66fc99e Initial load
duke
parents:
diff changeset
5803 // by this instruction.
a61af66fc99e Initial load
duke
parents:
diff changeset
5804 // ins_cost -- The estimated cost of this instruction is used by instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
5805 // selection to identify a minimum cost tree of machine
a61af66fc99e Initial load
duke
parents:
diff changeset
5806 // instructions that matches a tree of machine-independent
a61af66fc99e Initial load
duke
parents:
diff changeset
5807 // instructions.
a61af66fc99e Initial load
duke
parents:
diff changeset
5808 // format -- A string providing the disassembly for this instruction.
a61af66fc99e Initial load
duke
parents:
diff changeset
5809 // The value of an instruction's operand may be inserted
a61af66fc99e Initial load
duke
parents:
diff changeset
5810 // by referring to it with a '$' prefix.
a61af66fc99e Initial load
duke
parents:
diff changeset
5811 // opcode -- Three instruction opcodes may be provided. These are referred
a61af66fc99e Initial load
duke
parents:
diff changeset
5812 // to within an encode class as $primary, $secondary, and $tertiary
a61af66fc99e Initial load
duke
parents:
diff changeset
5813 // rrspectively. The primary opcode is commonly used to
a61af66fc99e Initial load
duke
parents:
diff changeset
5814 // indicate the type of machine instruction, while secondary
a61af66fc99e Initial load
duke
parents:
diff changeset
5815 // and tertiary are often used for prefix options or addressing
a61af66fc99e Initial load
duke
parents:
diff changeset
5816 // modes.
a61af66fc99e Initial load
duke
parents:
diff changeset
5817 // ins_encode -- A list of encode classes with parameters. The encode class
a61af66fc99e Initial load
duke
parents:
diff changeset
5818 // name must have been defined in an 'enc_class' specification
a61af66fc99e Initial load
duke
parents:
diff changeset
5819 // in the encode section of the architecture description.
a61af66fc99e Initial load
duke
parents:
diff changeset
5820
a61af66fc99e Initial load
duke
parents:
diff changeset
5821
a61af66fc99e Initial load
duke
parents:
diff changeset
5822 //----------Load/Store/Move Instructions---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5823 //----------Load Instructions--------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5824
a61af66fc99e Initial load
duke
parents:
diff changeset
5825 // Load Byte (8 bit signed)
a61af66fc99e Initial load
duke
parents:
diff changeset
5826 instruct loadB(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5827 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5828 match(Set dst (LoadB mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5829
a61af66fc99e Initial load
duke
parents:
diff changeset
5830 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5831 format %{ "movsbl $dst, $mem\t# byte" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5832
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5833 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5834 __ movsbl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5835 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5836
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5837 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5838 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5839
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5840 // Load Byte (8 bit signed) into Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5841 instruct loadB2L(rRegL dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5842 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5843 match(Set dst (ConvI2L (LoadB mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5844
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5845 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5846 format %{ "movsbq $dst, $mem\t# byte -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5847
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5848 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5849 __ movsbq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5850 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5851
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5852 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5853 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5854
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5855 // Load Unsigned Byte (8 bit UNsigned)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5856 instruct loadUB(rRegI dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5857 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5858 match(Set dst (LoadUB mem));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5859
a61af66fc99e Initial load
duke
parents:
diff changeset
5860 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5861 format %{ "movzbl $dst, $mem\t# ubyte" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5862
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5863 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5864 __ movzbl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5865 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5866
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5867 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5868 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5869
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5870 // Load Unsigned Byte (8 bit UNsigned) into Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5871 instruct loadUB2L(rRegL dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5872 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5873 match(Set dst (ConvI2L (LoadUB mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5874
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5875 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5876 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5877
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5878 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5879 __ movzbq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5880 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5881
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5882 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5883 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5884
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5885 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5886 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5887 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5888 effect(KILL cr);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5889
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5890 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t"
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5891 "andl $dst, $mask" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5892 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5893 Register Rdst = $dst$$Register;
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5894 __ movzbq(Rdst, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5895 __ andl(Rdst, $mask$$constant);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5896 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5897 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5898 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5899
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5900 // Load Short (16 bit signed)
a61af66fc99e Initial load
duke
parents:
diff changeset
5901 instruct loadS(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5902 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5903 match(Set dst (LoadS mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5904
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5905 ins_cost(125);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5906 format %{ "movswl $dst, $mem\t# short" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5907
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5908 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5909 __ movswl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5910 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5911
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5912 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5913 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5914
785
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5915 // Load Short (16 bit signed) to Byte (8 bit signed)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5916 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5917 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5918
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5919 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5920 format %{ "movsbl $dst, $mem\t# short -> byte" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5921 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5922 __ movsbl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5923 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5924 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5925 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5926
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5927 // Load Short (16 bit signed) into Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5928 instruct loadS2L(rRegL dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5929 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5930 match(Set dst (ConvI2L (LoadS mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5931
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5932 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5933 format %{ "movswq $dst, $mem\t# short -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5934
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5935 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5936 __ movswq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5937 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5938
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5939 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5940 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5941
558
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 420
diff changeset
5942 // Load Unsigned Short/Char (16 bit UNsigned)
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 420
diff changeset
5943 instruct loadUS(rRegI dst, memory mem)
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 420
diff changeset
5944 %{
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 420
diff changeset
5945 match(Set dst (LoadUS mem));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5946
a61af66fc99e Initial load
duke
parents:
diff changeset
5947 ins_cost(125);
558
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 420
diff changeset
5948 format %{ "movzwl $dst, $mem\t# ushort/char" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5949
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5950 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5951 __ movzwl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5952 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5953
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5954 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5955 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5956
785
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5957 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5958 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5959 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5960
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5961 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5962 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5963 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5964 __ movsbl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5965 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5966 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5967 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5968
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5969 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5970 instruct loadUS2L(rRegL dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5971 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5972 match(Set dst (ConvI2L (LoadUS mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5973
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5974 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5975 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5976
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5977 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5978 __ movzwq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5979 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5980
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5981 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5982 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5983
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5984 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5985 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5986 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5987
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5988 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5989 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5990 __ movzbq($dst$$Register, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5991 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5992 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5993 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5994
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5995 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5996 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5997 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5998 effect(KILL cr);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5999
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6000 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t"
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6001 "andl $dst, $mask" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6002 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6003 Register Rdst = $dst$$Register;
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6004 __ movzwq(Rdst, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6005 __ andl(Rdst, $mask$$constant);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6006 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6007 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6008 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6009
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6010 // Load Integer
a61af66fc99e Initial load
duke
parents:
diff changeset
6011 instruct loadI(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
6012 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6013 match(Set dst (LoadI mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6014
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6015 ins_cost(125);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6016 format %{ "movl $dst, $mem\t# int" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6017
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6018 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6019 __ movl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6020 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6021
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6022 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6023 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6024
785
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6025 // Load Integer (32 bit signed) to Byte (8 bit signed)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6026 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6027 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6028
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6029 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6030 format %{ "movsbl $dst, $mem\t# int -> byte" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6031 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6032 __ movsbl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6033 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6034 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6035 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6036
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6037 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6038 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6039 match(Set dst (AndI (LoadI mem) mask));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6040
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6041 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6042 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6043 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6044 __ movzbl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6045 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6046 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6047 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6048
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6049 // Load Integer (32 bit signed) to Short (16 bit signed)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6050 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6051 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6052
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6053 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6054 format %{ "movswl $dst, $mem\t# int -> short" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6055 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6056 __ movswl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6057 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6058 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6059 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6060
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6061 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6062 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6063 match(Set dst (AndI (LoadI mem) mask));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6064
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6065 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6066 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6067 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6068 __ movzwl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6069 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6070 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6071 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
6072
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6073 // Load Integer into Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6074 instruct loadI2L(rRegL dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6075 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6076 match(Set dst (ConvI2L (LoadI mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6077
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6078 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6079 format %{ "movslq $dst, $mem\t# int -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6080
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6081 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6082 __ movslq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6083 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6084
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6085 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6086 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6087
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6088 // Load Integer with mask 0xFF into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6089 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6090 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6091
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6092 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6093 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6094 __ movzbq($dst$$Register, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6095 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6096 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6097 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6098
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6099 // Load Integer with mask 0xFFFF into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6100 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6101 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6102
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6103 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6104 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6105 __ movzwq($dst$$Register, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6106 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6107 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6108 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6109
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6110 // Load Integer with a 32-bit mask into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6111 instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6112 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6113 effect(KILL cr);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6114
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6115 format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t"
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6116 "andl $dst, $mask" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6117 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6118 Register Rdst = $dst$$Register;
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6119 __ movl(Rdst, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6120 __ andl(Rdst, $mask$$constant);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6121 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6122 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6123 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
6124
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6125 // Load Unsigned Integer into Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6126 instruct loadUI2L(rRegL dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6127 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6128 match(Set dst (LoadUI2L mem));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6129
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6130 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6131 format %{ "movl $dst, $mem\t# uint -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6132
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6133 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6134 __ movl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6135 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6136
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6137 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6138 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6139
a61af66fc99e Initial load
duke
parents:
diff changeset
6140 // Load Long
a61af66fc99e Initial load
duke
parents:
diff changeset
6141 instruct loadL(rRegL dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
6142 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6143 match(Set dst (LoadL mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6144
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6145 ins_cost(125);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6146 format %{ "movq $dst, $mem\t# long" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6147
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6148 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6149 __ movq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6150 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
6151
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6152 ins_pipe(ialu_reg_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6153 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6154
a61af66fc99e Initial load
duke
parents:
diff changeset
6155 // Load Range
a61af66fc99e Initial load
duke
parents:
diff changeset
6156 instruct loadRange(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
6157 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6158 match(Set dst (LoadRange mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6159
a61af66fc99e Initial load
duke
parents:
diff changeset
6160 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6161 format %{ "movl $dst, $mem\t# range" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6162 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
6163 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6164 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6165 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6166
a61af66fc99e Initial load
duke
parents:
diff changeset
6167 // Load Pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
6168 instruct loadP(rRegP dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
6169 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6170 match(Set dst (LoadP mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6171
a61af66fc99e Initial load
duke
parents:
diff changeset
6172 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6173 format %{ "movq $dst, $mem\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6174 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
6175 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6176 ins_pipe(ialu_reg_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6177 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6178
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6179 // Load Compressed Pointer
163
885ed790ecf0 6695810: null oop passed to encode_heap_oop_not_null
kvn
parents: 145
diff changeset
6180 instruct loadN(rRegN dst, memory mem)
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6181 %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6182 match(Set dst (LoadN mem));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6183
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6184 ins_cost(125); // XXX
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6185 format %{ "movl $dst, $mem\t# compressed ptr" %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6186 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6187 __ movl($dst$$Register, $mem$$Address);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6188 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6189 ins_pipe(ialu_reg_mem); // XXX
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6190 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6191
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6192
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6193 // Load Klass Pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
6194 instruct loadKlass(rRegP dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
6195 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6196 match(Set dst (LoadKlass mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6197
a61af66fc99e Initial load
duke
parents:
diff changeset
6198 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6199 format %{ "movq $dst, $mem\t# class" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6200 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
6201 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6202 ins_pipe(ialu_reg_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6203 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6204
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6205 // Load narrow Klass Pointer
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6206 instruct loadNKlass(rRegN dst, memory mem)
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6207 %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6208 match(Set dst (LoadNKlass mem));
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6209
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6210 ins_cost(125); // XXX
182
44abbb0d4c18 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 169
diff changeset
6211 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6212 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6213 __ movl($dst$$Register, $mem$$Address);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6214 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6215 ins_pipe(ialu_reg_mem); // XXX
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6216 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6217
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6218 // Load Float
a61af66fc99e Initial load
duke
parents:
diff changeset
6219 instruct loadF(regF dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
6220 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6221 match(Set dst (LoadF mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6222
a61af66fc99e Initial load
duke
parents:
diff changeset
6223 ins_cost(145); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6224 format %{ "movss $dst, $mem\t# float" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6225 opcode(0xF3, 0x0F, 0x10);
a61af66fc99e Initial load
duke
parents:
diff changeset
6226 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6227 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6228 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6229
a61af66fc99e Initial load
duke
parents:
diff changeset
6230 // Load Double
a61af66fc99e Initial load
duke
parents:
diff changeset
6231 instruct loadD_partial(regD dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
6232 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6233 predicate(!UseXmmLoadAndClearUpper);
a61af66fc99e Initial load
duke
parents:
diff changeset
6234 match(Set dst (LoadD mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6235
a61af66fc99e Initial load
duke
parents:
diff changeset
6236 ins_cost(145); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6237 format %{ "movlpd $dst, $mem\t# double" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6238 opcode(0x66, 0x0F, 0x12);
a61af66fc99e Initial load
duke
parents:
diff changeset
6239 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6240 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6241 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6242
a61af66fc99e Initial load
duke
parents:
diff changeset
6243 instruct loadD(regD dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
6244 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6245 predicate(UseXmmLoadAndClearUpper);
a61af66fc99e Initial load
duke
parents:
diff changeset
6246 match(Set dst (LoadD mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6247
a61af66fc99e Initial load
duke
parents:
diff changeset
6248 ins_cost(145); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6249 format %{ "movsd $dst, $mem\t# double" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6250 opcode(0xF2, 0x0F, 0x10);
a61af66fc99e Initial load
duke
parents:
diff changeset
6251 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6252 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6253 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6254
a61af66fc99e Initial load
duke
parents:
diff changeset
6255 // Load Aligned Packed Byte to XMM register
a61af66fc99e Initial load
duke
parents:
diff changeset
6256 instruct loadA8B(regD dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6257 match(Set dst (Load8B mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6258 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
6259 format %{ "MOVQ $dst,$mem\t! packed8B" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6260 ins_encode( movq_ld(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6261 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
6262 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6263
a61af66fc99e Initial load
duke
parents:
diff changeset
6264 // Load Aligned Packed Short to XMM register
a61af66fc99e Initial load
duke
parents:
diff changeset
6265 instruct loadA4S(regD dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6266 match(Set dst (Load4S mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6267 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
6268 format %{ "MOVQ $dst,$mem\t! packed4S" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6269 ins_encode( movq_ld(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6270 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
6271 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6272
a61af66fc99e Initial load
duke
parents:
diff changeset
6273 // Load Aligned Packed Char to XMM register
a61af66fc99e Initial load
duke
parents:
diff changeset
6274 instruct loadA4C(regD dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6275 match(Set dst (Load4C mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6276 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
6277 format %{ "MOVQ $dst,$mem\t! packed4C" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6278 ins_encode( movq_ld(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6279 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
6280 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6281
a61af66fc99e Initial load
duke
parents:
diff changeset
6282 // Load Aligned Packed Integer to XMM register
a61af66fc99e Initial load
duke
parents:
diff changeset
6283 instruct load2IU(regD dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6284 match(Set dst (Load2I mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6285 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
6286 format %{ "MOVQ $dst,$mem\t! packed2I" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6287 ins_encode( movq_ld(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6288 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
6289 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6290
a61af66fc99e Initial load
duke
parents:
diff changeset
6291 // Load Aligned Packed Single to XMM
a61af66fc99e Initial load
duke
parents:
diff changeset
6292 instruct loadA2F(regD dst, memory mem) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6293 match(Set dst (Load2F mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6294 ins_cost(145);
a61af66fc99e Initial load
duke
parents:
diff changeset
6295 format %{ "MOVQ $dst,$mem\t! packed2F" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6296 ins_encode( movq_ld(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6297 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
6298 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6299
a61af66fc99e Initial load
duke
parents:
diff changeset
6300 // Load Effective Address
a61af66fc99e Initial load
duke
parents:
diff changeset
6301 instruct leaP8(rRegP dst, indOffset8 mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
6302 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6303 match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6304
a61af66fc99e Initial load
duke
parents:
diff changeset
6305 ins_cost(110); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6306 format %{ "leaq $dst, $mem\t# ptr 8" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6307 opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
6308 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6309 ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
6310 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6311
a61af66fc99e Initial load
duke
parents:
diff changeset
6312 instruct leaP32(rRegP dst, indOffset32 mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
6313 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6314 match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6315
a61af66fc99e Initial load
duke
parents:
diff changeset
6316 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
6317 format %{ "leaq $dst, $mem\t# ptr 32" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6318 opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
6319 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6320 ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
6321 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6322
a61af66fc99e Initial load
duke
parents:
diff changeset
6323 // instruct leaPIdx(rRegP dst, indIndex mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
6324 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6325 // match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6326
a61af66fc99e Initial load
duke
parents:
diff changeset
6327 // ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
6328 // format %{ "leaq $dst, $mem\t# ptr idx" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6329 // opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
6330 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6331 // ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
6332 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6333
a61af66fc99e Initial load
duke
parents:
diff changeset
6334 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
6335 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6336 match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6337
a61af66fc99e Initial load
duke
parents:
diff changeset
6338 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
6339 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6340 opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
6341 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6342 ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
6343 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6344
a61af66fc99e Initial load
duke
parents:
diff changeset
6345 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
6346 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6347 match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6348
a61af66fc99e Initial load
duke
parents:
diff changeset
6349 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
6350 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6351 opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
6352 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6353 ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
6354 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6355
a61af66fc99e Initial load
duke
parents:
diff changeset
6356 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
6357 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6358 match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6359
a61af66fc99e Initial load
duke
parents:
diff changeset
6360 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
6361 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6362 opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
6363 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6364 ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
6365 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6366
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6367 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6368 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6369 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6370
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6371 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6372 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6373 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6374 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6375 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6376 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6377
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6378 // Load Effective Address which uses Narrow (32-bits) oop
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6379 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6380 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6381 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6382 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6383
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6384 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6385 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6386 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6387 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6388 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6389 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6390
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6391 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6392 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6393 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6394 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6395
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6396 ins_cost(110); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6397 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6398 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6399 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6400 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6401 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6402
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6403 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6404 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6405 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6406 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6407
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6408 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6409 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6410 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6411 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6412 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6413 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6414
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6415 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6416 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6417 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6418 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6419
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6420 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6421 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6422 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6423 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6424 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6425 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6426
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6427 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6428 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6429 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6430 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6431
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6432 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6433 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6434 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6435 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6436 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6437 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6438
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6439 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6440 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6441 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6442 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6443
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6444 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6445 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6446 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6447 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6448 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6449 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6450
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6451 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6452 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6453 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6454 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6455
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6456 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6457 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6458 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6459 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6460 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6461 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6462
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6463 instruct loadConI(rRegI dst, immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6464 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6465 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6466
a61af66fc99e Initial load
duke
parents:
diff changeset
6467 format %{ "movl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6468 ins_encode(load_immI(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6469 ins_pipe(ialu_reg_fat); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6470 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6471
a61af66fc99e Initial load
duke
parents:
diff changeset
6472 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
6473 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6474 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6475 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
6476
a61af66fc99e Initial load
duke
parents:
diff changeset
6477 ins_cost(50);
a61af66fc99e Initial load
duke
parents:
diff changeset
6478 format %{ "xorl $dst, $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6479 opcode(0x33); /* + rd */
a61af66fc99e Initial load
duke
parents:
diff changeset
6480 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6481 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6482 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6483
a61af66fc99e Initial load
duke
parents:
diff changeset
6484 instruct loadConL(rRegL dst, immL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6485 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6486 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6487
a61af66fc99e Initial load
duke
parents:
diff changeset
6488 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6489 format %{ "movq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6490 ins_encode(load_immL(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6491 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6492 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6493
a61af66fc99e Initial load
duke
parents:
diff changeset
6494 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
6495 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6496 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6497 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
6498
a61af66fc99e Initial load
duke
parents:
diff changeset
6499 ins_cost(50);
a61af66fc99e Initial load
duke
parents:
diff changeset
6500 format %{ "xorl $dst, $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6501 opcode(0x33); /* + rd */
a61af66fc99e Initial load
duke
parents:
diff changeset
6502 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6503 ins_pipe(ialu_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6504 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6505
a61af66fc99e Initial load
duke
parents:
diff changeset
6506 instruct loadConUL32(rRegL dst, immUL32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6507 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6508 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6509
a61af66fc99e Initial load
duke
parents:
diff changeset
6510 ins_cost(60);
a61af66fc99e Initial load
duke
parents:
diff changeset
6511 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6512 ins_encode(load_immUL32(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6513 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6514 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6515
a61af66fc99e Initial load
duke
parents:
diff changeset
6516 instruct loadConL32(rRegL dst, immL32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6517 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6518 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6519
a61af66fc99e Initial load
duke
parents:
diff changeset
6520 ins_cost(70);
a61af66fc99e Initial load
duke
parents:
diff changeset
6521 format %{ "movq $dst, $src\t# long (32-bit)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6522 ins_encode(load_immL32(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6523 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6524 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6525
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6526 instruct loadConP(rRegP dst, immP con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6527 match(Set dst con);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6528
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6529 format %{ "movq $dst, $con\t# ptr" %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6530 ins_encode(load_immP(dst, con));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6531 ins_pipe(ialu_reg_fat); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6532 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6533
a61af66fc99e Initial load
duke
parents:
diff changeset
6534 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
6535 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6536 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6537 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
6538
a61af66fc99e Initial load
duke
parents:
diff changeset
6539 ins_cost(50);
a61af66fc99e Initial load
duke
parents:
diff changeset
6540 format %{ "xorl $dst, $dst\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6541 opcode(0x33); /* + rd */
a61af66fc99e Initial load
duke
parents:
diff changeset
6542 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6543 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6544 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6545
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6546 instruct loadConP_poll(rRegP dst, immP_poll src) %{
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6547 match(Set dst src);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6548 format %{ "movq $dst, $src\t!ptr" %}
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6549 ins_encode %{
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6550 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6551 __ lea($dst$$Register, polling_page);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6552 %}
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6553 ins_pipe(ialu_reg_fat);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6554 %}
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6555
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6556 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
6557 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6558 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6559 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
6560
a61af66fc99e Initial load
duke
parents:
diff changeset
6561 ins_cost(60);
a61af66fc99e Initial load
duke
parents:
diff changeset
6562 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6563 ins_encode(load_immP31(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6564 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6565 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6566
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6567 instruct loadConF(regF dst, immF con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6568 match(Set dst con);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6569 ins_cost(125);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6570 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6571 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6572 __ movflt($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6573 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6574 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
6575 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6576
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6577 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6578 match(Set dst src);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6579 effect(KILL cr);
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6580 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6581 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6582 __ xorq($dst$$Register, $dst$$Register);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6583 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6584 ins_pipe(ialu_reg);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6585 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6586
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6587 instruct loadConN(rRegN dst, immN src) %{
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6588 match(Set dst src);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6589
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6590 ins_cost(125);
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6591 format %{ "movl $dst, $src\t# compressed ptr" %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6592 ins_encode %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6593 address con = (address)$src$$constant;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6594 if (con == NULL) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6595 ShouldNotReachHere();
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6596 } else {
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6597 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6598 }
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6599 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6600 ins_pipe(ialu_reg_fat); // XXX
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6601 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6602
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6603 instruct loadConF0(regF dst, immF0 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6604 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6605 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6606 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
6607
a61af66fc99e Initial load
duke
parents:
diff changeset
6608 format %{ "xorps $dst, $dst\t# float 0.0" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6609 opcode(0x0F, 0x57);
a61af66fc99e Initial load
duke
parents:
diff changeset
6610 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6611 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
6612 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6613
a61af66fc99e Initial load
duke
parents:
diff changeset
6614 // Use the same format since predicate() can not be used here.
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6615 instruct loadConD(regD dst, immD con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6616 match(Set dst con);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6617 ins_cost(125);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6618 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6619 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6620 __ movdbl($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6621 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6622 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
6623 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6624
a61af66fc99e Initial load
duke
parents:
diff changeset
6625 instruct loadConD0(regD dst, immD0 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6626 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6627 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6628 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
6629
a61af66fc99e Initial load
duke
parents:
diff changeset
6630 format %{ "xorpd $dst, $dst\t# double 0.0" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6631 opcode(0x66, 0x0F, 0x57);
a61af66fc99e Initial load
duke
parents:
diff changeset
6632 ins_encode(OpcP, REX_reg_reg(dst, dst), OpcS, OpcT, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6633 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
6634 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6635
a61af66fc99e Initial load
duke
parents:
diff changeset
6636 instruct loadSSI(rRegI dst, stackSlotI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6637 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6638 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6639
a61af66fc99e Initial load
duke
parents:
diff changeset
6640 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
6641 format %{ "movl $dst, $src\t# int stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6642 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
6643 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6644 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6645 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6646
a61af66fc99e Initial load
duke
parents:
diff changeset
6647 instruct loadSSL(rRegL dst, stackSlotL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6648 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6649 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6650
a61af66fc99e Initial load
duke
parents:
diff changeset
6651 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
6652 format %{ "movq $dst, $src\t# long stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6653 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
6654 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6655 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6656 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6657
a61af66fc99e Initial load
duke
parents:
diff changeset
6658 instruct loadSSP(rRegP dst, stackSlotP src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6659 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6660 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6661
a61af66fc99e Initial load
duke
parents:
diff changeset
6662 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
6663 format %{ "movq $dst, $src\t# ptr stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6664 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
6665 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6666 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6667 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6668
a61af66fc99e Initial load
duke
parents:
diff changeset
6669 instruct loadSSF(regF dst, stackSlotF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6670 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6671 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6672
a61af66fc99e Initial load
duke
parents:
diff changeset
6673 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
6674 format %{ "movss $dst, $src\t# float stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6675 opcode(0xF3, 0x0F, 0x10);
a61af66fc99e Initial load
duke
parents:
diff changeset
6676 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6677 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6678 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6679
a61af66fc99e Initial load
duke
parents:
diff changeset
6680 // Use the same format since predicate() can not be used here.
a61af66fc99e Initial load
duke
parents:
diff changeset
6681 instruct loadSSD(regD dst, stackSlotD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6682 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6683 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6684
a61af66fc99e Initial load
duke
parents:
diff changeset
6685 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
6686 format %{ "movsd $dst, $src\t# double stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6687 ins_encode %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6688 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
a61af66fc99e Initial load
duke
parents:
diff changeset
6689 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6690 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6691 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6692
a61af66fc99e Initial load
duke
parents:
diff changeset
6693 // Prefetch instructions.
a61af66fc99e Initial load
duke
parents:
diff changeset
6694 // Must be safe to execute with invalid address (cannot fault).
a61af66fc99e Initial load
duke
parents:
diff changeset
6695
a61af66fc99e Initial load
duke
parents:
diff changeset
6696 instruct prefetchr( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6697 predicate(ReadPrefetchInstr==3);
a61af66fc99e Initial load
duke
parents:
diff changeset
6698 match(PrefetchRead mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6699 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
6700
a61af66fc99e Initial load
duke
parents:
diff changeset
6701 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6702 opcode(0x0F, 0x0D); /* Opcode 0F 0D /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6703 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6704 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6705 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6706
a61af66fc99e Initial load
duke
parents:
diff changeset
6707 instruct prefetchrNTA( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6708 predicate(ReadPrefetchInstr==0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6709 match(PrefetchRead mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6710 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
6711
a61af66fc99e Initial load
duke
parents:
diff changeset
6712 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6713 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6714 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6715 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6716 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6717
a61af66fc99e Initial load
duke
parents:
diff changeset
6718 instruct prefetchrT0( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6719 predicate(ReadPrefetchInstr==1);
a61af66fc99e Initial load
duke
parents:
diff changeset
6720 match(PrefetchRead mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6721 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
6722
a61af66fc99e Initial load
duke
parents:
diff changeset
6723 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6724 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6725 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6726 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6727 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6728
a61af66fc99e Initial load
duke
parents:
diff changeset
6729 instruct prefetchrT2( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6730 predicate(ReadPrefetchInstr==2);
a61af66fc99e Initial load
duke
parents:
diff changeset
6731 match(PrefetchRead mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6732 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
6733
a61af66fc99e Initial load
duke
parents:
diff changeset
6734 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6735 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6736 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6737 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6738 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6739
a61af66fc99e Initial load
duke
parents:
diff changeset
6740 instruct prefetchw( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6741 predicate(AllocatePrefetchInstr==3);
a61af66fc99e Initial load
duke
parents:
diff changeset
6742 match(PrefetchWrite mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6743 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
6744
a61af66fc99e Initial load
duke
parents:
diff changeset
6745 format %{ "PREFETCHW $mem\t# Prefetch into level 1 cache and mark modified" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6746 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6747 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6748 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6749 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6750
a61af66fc99e Initial load
duke
parents:
diff changeset
6751 instruct prefetchwNTA( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6752 predicate(AllocatePrefetchInstr==0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6753 match(PrefetchWrite mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6754 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
6755
a61af66fc99e Initial load
duke
parents:
diff changeset
6756 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6757 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6758 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6759 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6760 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6761
a61af66fc99e Initial load
duke
parents:
diff changeset
6762 instruct prefetchwT0( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6763 predicate(AllocatePrefetchInstr==1);
a61af66fc99e Initial load
duke
parents:
diff changeset
6764 match(PrefetchWrite mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6765 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
6766
a61af66fc99e Initial load
duke
parents:
diff changeset
6767 format %{ "PREFETCHT0 $mem\t# Prefetch to level 1 and 2 caches for write" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6768 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6769 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6770 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6771 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6772
a61af66fc99e Initial load
duke
parents:
diff changeset
6773 instruct prefetchwT2( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6774 predicate(AllocatePrefetchInstr==2);
a61af66fc99e Initial load
duke
parents:
diff changeset
6775 match(PrefetchWrite mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6776 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
6777
a61af66fc99e Initial load
duke
parents:
diff changeset
6778 format %{ "PREFETCHT2 $mem\t# Prefetch to level 2 cache for write" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6779 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6780 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6781 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6782 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6783
a61af66fc99e Initial load
duke
parents:
diff changeset
6784 //----------Store Instructions-------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6785
a61af66fc99e Initial load
duke
parents:
diff changeset
6786 // Store Byte
a61af66fc99e Initial load
duke
parents:
diff changeset
6787 instruct storeB(memory mem, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6788 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6789 match(Set mem (StoreB mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6790
a61af66fc99e Initial load
duke
parents:
diff changeset
6791 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6792 format %{ "movb $mem, $src\t# byte" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6793 opcode(0x88);
a61af66fc99e Initial load
duke
parents:
diff changeset
6794 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6795 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6796 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6797
a61af66fc99e Initial load
duke
parents:
diff changeset
6798 // Store Char/Short
a61af66fc99e Initial load
duke
parents:
diff changeset
6799 instruct storeC(memory mem, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6800 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6801 match(Set mem (StoreC mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6802
a61af66fc99e Initial load
duke
parents:
diff changeset
6803 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6804 format %{ "movw $mem, $src\t# char/short" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6805 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
6806 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6807 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6808 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6809
a61af66fc99e Initial load
duke
parents:
diff changeset
6810 // Store Integer
a61af66fc99e Initial load
duke
parents:
diff changeset
6811 instruct storeI(memory mem, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6812 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6813 match(Set mem (StoreI mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6814
a61af66fc99e Initial load
duke
parents:
diff changeset
6815 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6816 format %{ "movl $mem, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6817 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
6818 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6819 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6820 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6821
a61af66fc99e Initial load
duke
parents:
diff changeset
6822 // Store Long
a61af66fc99e Initial load
duke
parents:
diff changeset
6823 instruct storeL(memory mem, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6824 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6825 match(Set mem (StoreL mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6826
a61af66fc99e Initial load
duke
parents:
diff changeset
6827 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6828 format %{ "movq $mem, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6829 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
6830 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6831 ins_pipe(ialu_mem_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6832 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6833
a61af66fc99e Initial load
duke
parents:
diff changeset
6834 // Store Pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
6835 instruct storeP(memory mem, any_RegP src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6836 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6837 match(Set mem (StoreP mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6838
a61af66fc99e Initial load
duke
parents:
diff changeset
6839 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6840 format %{ "movq $mem, $src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6841 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
6842 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
6843 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6844 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6845
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6846 instruct storeImmP0(memory mem, immP0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6847 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6848 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6849 match(Set mem (StoreP mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6850
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6851 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6852 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6853 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6854 __ movq($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6855 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6856 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6857 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6858
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6859 // Store NULL Pointer, mark word, or other simple pointer constant.
a61af66fc99e Initial load
duke
parents:
diff changeset
6860 instruct storeImmP(memory mem, immP31 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6861 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6862 match(Set mem (StoreP mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6863
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6864 ins_cost(150); // XXX
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6865 format %{ "movq $mem, $src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6866 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6867 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6868 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6869 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6870
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6871 // Store Compressed Pointer
163
885ed790ecf0 6695810: null oop passed to encode_heap_oop_not_null
kvn
parents: 145
diff changeset
6872 instruct storeN(memory mem, rRegN src)
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6873 %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6874 match(Set mem (StoreN mem src));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6875
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6876 ins_cost(125); // XXX
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6877 format %{ "movl $mem, $src\t# compressed ptr" %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6878 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6879 __ movl($mem$$Address, $src$$Register);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6880 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6881 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6882 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6883
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6884 instruct storeImmN0(memory mem, immN0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6885 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6886 predicate(Universe::narrow_oop_base() == NULL);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6887 match(Set mem (StoreN mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6888
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6889 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6890 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6891 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6892 __ movl($mem$$Address, r12);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6893 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6894 ins_pipe(ialu_mem_reg);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6895 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6896
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6897 instruct storeImmN(memory mem, immN src)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6898 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6899 match(Set mem (StoreN mem src));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6900
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6901 ins_cost(150); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6902 format %{ "movl $mem, $src\t# compressed ptr" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6903 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6904 address con = (address)$src$$constant;
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6905 if (con == NULL) {
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6906 __ movl($mem$$Address, (int32_t)0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6907 } else {
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6908 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6909 }
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6910 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6911 ins_pipe(ialu_mem_imm);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6912 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6913
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6914 // Store Integer Immediate
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6915 instruct storeImmI0(memory mem, immI0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6916 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6917 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6918 match(Set mem (StoreI mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6919
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6920 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6921 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6922 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6923 __ movl($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6924 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6925 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6926 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6927
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6928 instruct storeImmI(memory mem, immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6929 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6930 match(Set mem (StoreI mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6931
a61af66fc99e Initial load
duke
parents:
diff changeset
6932 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6933 format %{ "movl $mem, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6934 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6935 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6936 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6937 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6938
a61af66fc99e Initial load
duke
parents:
diff changeset
6939 // Store Long Immediate
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6940 instruct storeImmL0(memory mem, immL0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6941 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6942 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6943 match(Set mem (StoreL mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6944
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6945 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6946 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6947 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6948 __ movq($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6949 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6950 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6951 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6952
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6953 instruct storeImmL(memory mem, immL32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6954 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6955 match(Set mem (StoreL mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6956
a61af66fc99e Initial load
duke
parents:
diff changeset
6957 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6958 format %{ "movq $mem, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6959 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6960 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6961 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6962 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6963
a61af66fc99e Initial load
duke
parents:
diff changeset
6964 // Store Short/Char Immediate
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6965 instruct storeImmC0(memory mem, immI0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6966 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6967 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6968 match(Set mem (StoreC mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6969
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6970 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6971 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6972 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6973 __ movw($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6974 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6975 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6976 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6977
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6978 instruct storeImmI16(memory mem, immI16 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6979 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6980 predicate(UseStoreImmI16);
a61af66fc99e Initial load
duke
parents:
diff changeset
6981 match(Set mem (StoreC mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6982
a61af66fc99e Initial load
duke
parents:
diff changeset
6983 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6984 format %{ "movw $mem, $src\t# short/char" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6985 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
a61af66fc99e Initial load
duke
parents:
diff changeset
6986 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6987 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6988 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6989
a61af66fc99e Initial load
duke
parents:
diff changeset
6990 // Store Byte Immediate
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6991 instruct storeImmB0(memory mem, immI0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6992 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6993 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6994 match(Set mem (StoreB mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6995
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6996 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6997 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6998 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6999 __ movb($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7000 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7001 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7002 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7003
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7004 instruct storeImmB(memory mem, immI8 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7005 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7006 match(Set mem (StoreB mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7007
a61af66fc99e Initial load
duke
parents:
diff changeset
7008 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7009 format %{ "movb $mem, $src\t# byte" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7010 opcode(0xC6); /* C6 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7011 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7012 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7013 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7014
a61af66fc99e Initial load
duke
parents:
diff changeset
7015 // Store Aligned Packed Byte XMM register to memory
a61af66fc99e Initial load
duke
parents:
diff changeset
7016 instruct storeA8B(memory mem, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7017 match(Set mem (Store8B mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7018 ins_cost(145);
a61af66fc99e Initial load
duke
parents:
diff changeset
7019 format %{ "MOVQ $mem,$src\t! packed8B" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7020 ins_encode( movq_st(mem, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7021 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
7022 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7023
a61af66fc99e Initial load
duke
parents:
diff changeset
7024 // Store Aligned Packed Char/Short XMM register to memory
a61af66fc99e Initial load
duke
parents:
diff changeset
7025 instruct storeA4C(memory mem, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7026 match(Set mem (Store4C mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7027 ins_cost(145);
a61af66fc99e Initial load
duke
parents:
diff changeset
7028 format %{ "MOVQ $mem,$src\t! packed4C" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7029 ins_encode( movq_st(mem, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7030 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
7031 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7032
a61af66fc99e Initial load
duke
parents:
diff changeset
7033 // Store Aligned Packed Integer XMM register to memory
a61af66fc99e Initial load
duke
parents:
diff changeset
7034 instruct storeA2I(memory mem, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7035 match(Set mem (Store2I mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7036 ins_cost(145);
a61af66fc99e Initial load
duke
parents:
diff changeset
7037 format %{ "MOVQ $mem,$src\t! packed2I" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7038 ins_encode( movq_st(mem, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7039 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
7040 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7041
a61af66fc99e Initial load
duke
parents:
diff changeset
7042 // Store CMS card-mark Immediate
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7043 instruct storeImmCM0_reg(memory mem, immI0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7044 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7045 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7046 match(Set mem (StoreCM mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7047
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7048 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7049 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7050 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7051 __ movb($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7052 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7053 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7054 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7055
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7056 instruct storeImmCM0(memory mem, immI0 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7057 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7058 match(Set mem (StoreCM mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7059
a61af66fc99e Initial load
duke
parents:
diff changeset
7060 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7061 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7062 opcode(0xC6); /* C6 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7063 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7064 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7065 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7066
a61af66fc99e Initial load
duke
parents:
diff changeset
7067 // Store Aligned Packed Single Float XMM register to memory
a61af66fc99e Initial load
duke
parents:
diff changeset
7068 instruct storeA2F(memory mem, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7069 match(Set mem (Store2F mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7070 ins_cost(145);
a61af66fc99e Initial load
duke
parents:
diff changeset
7071 format %{ "MOVQ $mem,$src\t! packed2F" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7072 ins_encode( movq_st(mem, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7073 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
7074 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7075
a61af66fc99e Initial load
duke
parents:
diff changeset
7076 // Store Float
a61af66fc99e Initial load
duke
parents:
diff changeset
7077 instruct storeF(memory mem, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7078 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7079 match(Set mem (StoreF mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7080
a61af66fc99e Initial load
duke
parents:
diff changeset
7081 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7082 format %{ "movss $mem, $src\t# float" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7083 opcode(0xF3, 0x0F, 0x11);
a61af66fc99e Initial load
duke
parents:
diff changeset
7084 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
7085 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7086 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7087
a61af66fc99e Initial load
duke
parents:
diff changeset
7088 // Store immediate Float value (it is faster than store from XMM register)
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7089 instruct storeF0(memory mem, immF0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7090 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7091 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7092 match(Set mem (StoreF mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7093
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7094 ins_cost(25); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7095 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7096 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7097 __ movl($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7098 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7099 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7100 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7101
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7102 instruct storeF_imm(memory mem, immF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7103 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7104 match(Set mem (StoreF mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7105
a61af66fc99e Initial load
duke
parents:
diff changeset
7106 ins_cost(50);
a61af66fc99e Initial load
duke
parents:
diff changeset
7107 format %{ "movl $mem, $src\t# float" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7108 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7109 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7110 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7111 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7112
a61af66fc99e Initial load
duke
parents:
diff changeset
7113 // Store Double
a61af66fc99e Initial load
duke
parents:
diff changeset
7114 instruct storeD(memory mem, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7115 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7116 match(Set mem (StoreD mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7117
a61af66fc99e Initial load
duke
parents:
diff changeset
7118 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7119 format %{ "movsd $mem, $src\t# double" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7120 opcode(0xF2, 0x0F, 0x11);
a61af66fc99e Initial load
duke
parents:
diff changeset
7121 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
7122 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7123 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7124
a61af66fc99e Initial load
duke
parents:
diff changeset
7125 // Store immediate double 0.0 (it is faster than store from XMM register)
a61af66fc99e Initial load
duke
parents:
diff changeset
7126 instruct storeD0_imm(memory mem, immD0 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7127 %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7128 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7129 match(Set mem (StoreD mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7130
a61af66fc99e Initial load
duke
parents:
diff changeset
7131 ins_cost(50);
a61af66fc99e Initial load
duke
parents:
diff changeset
7132 format %{ "movq $mem, $src\t# double 0." %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7133 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7134 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7135 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7136 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7137
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7138 instruct storeD0(memory mem, immD0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7139 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7140 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7141 match(Set mem (StoreD mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7142
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7143 ins_cost(25); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7144 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7145 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7146 __ movq($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7147 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7148 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7149 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7150
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7151 instruct storeSSI(stackSlotI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7152 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7153 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
7154
a61af66fc99e Initial load
duke
parents:
diff changeset
7155 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
7156 format %{ "movl $dst, $src\t# int stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7157 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
7158 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7159 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
7160 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7161
a61af66fc99e Initial load
duke
parents:
diff changeset
7162 instruct storeSSL(stackSlotL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7163 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7164 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
7165
a61af66fc99e Initial load
duke
parents:
diff changeset
7166 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
7167 format %{ "movq $dst, $src\t# long stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7168 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
7169 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7170 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7171 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7172
a61af66fc99e Initial load
duke
parents:
diff changeset
7173 instruct storeSSP(stackSlotP dst, rRegP src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7174 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7175 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
7176
a61af66fc99e Initial load
duke
parents:
diff changeset
7177 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
7178 format %{ "movq $dst, $src\t# ptr stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7179 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
7180 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7181 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7182 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7183
a61af66fc99e Initial load
duke
parents:
diff changeset
7184 instruct storeSSF(stackSlotF dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7185 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7186 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
7187
a61af66fc99e Initial load
duke
parents:
diff changeset
7188 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7189 format %{ "movss $dst, $src\t# float stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7190 opcode(0xF3, 0x0F, 0x11);
a61af66fc99e Initial load
duke
parents:
diff changeset
7191 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7192 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7193 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7194
a61af66fc99e Initial load
duke
parents:
diff changeset
7195 instruct storeSSD(stackSlotD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7196 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7197 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
7198
a61af66fc99e Initial load
duke
parents:
diff changeset
7199 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7200 format %{ "movsd $dst, $src\t# double stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7201 opcode(0xF2, 0x0F, 0x11);
a61af66fc99e Initial load
duke
parents:
diff changeset
7202 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7203 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7204 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7205
a61af66fc99e Initial load
duke
parents:
diff changeset
7206 //----------BSWAP Instructions-------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7207 instruct bytes_reverse_int(rRegI dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7208 match(Set dst (ReverseBytesI dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7209
a61af66fc99e Initial load
duke
parents:
diff changeset
7210 format %{ "bswapl $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7211 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7212 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7213 ins_pipe( ialu_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
7214 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7215
a61af66fc99e Initial load
duke
parents:
diff changeset
7216 instruct bytes_reverse_long(rRegL dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7217 match(Set dst (ReverseBytesL dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7218
a61af66fc99e Initial load
duke
parents:
diff changeset
7219 format %{ "bswapq $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7220
a61af66fc99e Initial load
duke
parents:
diff changeset
7221 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7222 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7223 ins_pipe( ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7224 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7225
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7226 instruct bytes_reverse_unsigned_short(rRegI dst) %{
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7227 match(Set dst (ReverseBytesUS dst));
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7228
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
7229 format %{ "bswapl $dst\n\t"
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7230 "shrl $dst,16\n\t" %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7231 ins_encode %{
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7232 __ bswapl($dst$$Register);
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
7233 __ shrl($dst$$Register, 16);
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7234 %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7235 ins_pipe( ialu_reg );
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7236 %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7237
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7238 instruct bytes_reverse_short(rRegI dst) %{
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7239 match(Set dst (ReverseBytesS dst));
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7240
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
7241 format %{ "bswapl $dst\n\t"
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7242 "sar $dst,16\n\t" %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7243 ins_encode %{
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7244 __ bswapl($dst$$Register);
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
7245 __ sarl($dst$$Register, 16);
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7246 %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7247 ins_pipe( ialu_reg );
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7248 %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
7249
775
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7250 //---------- Zeros Count Instructions ------------------------------------------
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7251
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7252 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7253 predicate(UseCountLeadingZerosInstruction);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7254 match(Set dst (CountLeadingZerosI src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7255 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7256
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7257 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7258 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7259 __ lzcntl($dst$$Register, $src$$Register);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7260 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7261 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7262 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7263
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7264 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7265 predicate(!UseCountLeadingZerosInstruction);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7266 match(Set dst (CountLeadingZerosI src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7267 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7268
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7269 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7270 "jnz skip\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7271 "movl $dst, -1\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7272 "skip:\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7273 "negl $dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7274 "addl $dst, 31" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7275 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7276 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7277 Register Rsrc = $src$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7278 Label skip;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7279 __ bsrl(Rdst, Rsrc);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7280 __ jccb(Assembler::notZero, skip);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7281 __ movl(Rdst, -1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7282 __ bind(skip);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7283 __ negl(Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7284 __ addl(Rdst, BitsPerInt - 1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7285 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7286 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7287 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7288
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7289 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7290 predicate(UseCountLeadingZerosInstruction);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7291 match(Set dst (CountLeadingZerosL src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7292 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7293
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7294 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7295 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7296 __ lzcntq($dst$$Register, $src$$Register);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7297 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7298 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7299 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7300
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7301 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7302 predicate(!UseCountLeadingZerosInstruction);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7303 match(Set dst (CountLeadingZerosL src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7304 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7305
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7306 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7307 "jnz skip\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7308 "movl $dst, -1\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7309 "skip:\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7310 "negl $dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7311 "addl $dst, 63" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7312 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7313 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7314 Register Rsrc = $src$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7315 Label skip;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7316 __ bsrq(Rdst, Rsrc);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7317 __ jccb(Assembler::notZero, skip);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7318 __ movl(Rdst, -1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7319 __ bind(skip);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7320 __ negl(Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7321 __ addl(Rdst, BitsPerLong - 1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7322 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7323 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7324 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7325
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7326 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7327 match(Set dst (CountTrailingZerosI src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7328 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7329
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7330 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7331 "jnz done\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7332 "movl $dst, 32\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7333 "done:" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7334 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7335 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7336 Label done;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7337 __ bsfl(Rdst, $src$$Register);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7338 __ jccb(Assembler::notZero, done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7339 __ movl(Rdst, BitsPerInt);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7340 __ bind(done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7341 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7342 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7343 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7344
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7345 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7346 match(Set dst (CountTrailingZerosL src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7347 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7348
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7349 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7350 "jnz done\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7351 "movl $dst, 64\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7352 "done:" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7353 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7354 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7355 Label done;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7356 __ bsfq(Rdst, $src$$Register);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7357 __ jccb(Assembler::notZero, done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7358 __ movl(Rdst, BitsPerLong);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7359 __ bind(done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7360 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7361 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7362 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7363
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
7364
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7365 //---------- Population Count Instructions -------------------------------------
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7366
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7367 instruct popCountI(rRegI dst, rRegI src) %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7368 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7369 match(Set dst (PopCountI src));
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7370
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7371 format %{ "popcnt $dst, $src" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7372 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7373 __ popcntl($dst$$Register, $src$$Register);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7374 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7375 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7376 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7377
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7378 instruct popCountI_mem(rRegI dst, memory mem) %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7379 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7380 match(Set dst (PopCountI (LoadI mem)));
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7381
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7382 format %{ "popcnt $dst, $mem" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7383 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7384 __ popcntl($dst$$Register, $mem$$Address);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7385 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7386 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7387 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7388
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7389 // Note: Long.bitCount(long) returns an int.
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7390 instruct popCountL(rRegI dst, rRegL src) %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7391 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7392 match(Set dst (PopCountL src));
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7393
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7394 format %{ "popcnt $dst, $src" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7395 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7396 __ popcntq($dst$$Register, $src$$Register);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7397 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7398 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7399 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7400
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7401 // Note: Long.bitCount(long) returns an int.
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7402 instruct popCountL_mem(rRegI dst, memory mem) %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7403 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7404 match(Set dst (PopCountL (LoadL mem)));
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7405
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7406 format %{ "popcnt $dst, $mem" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7407 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7408 __ popcntq($dst$$Register, $mem$$Address);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7409 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7410 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7411 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7412
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
7413
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7414 //----------MemBar Instructions-----------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7415 // Memory barrier flavors
a61af66fc99e Initial load
duke
parents:
diff changeset
7416
a61af66fc99e Initial load
duke
parents:
diff changeset
7417 instruct membar_acquire()
a61af66fc99e Initial load
duke
parents:
diff changeset
7418 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7419 match(MemBarAcquire);
a61af66fc99e Initial load
duke
parents:
diff changeset
7420 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7421
a61af66fc99e Initial load
duke
parents:
diff changeset
7422 size(0);
671
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
7423 format %{ "MEMBAR-acquire ! (empty encoding)" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7424 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
7425 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
7426 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7427
a61af66fc99e Initial load
duke
parents:
diff changeset
7428 instruct membar_acquire_lock()
a61af66fc99e Initial load
duke
parents:
diff changeset
7429 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7430 match(MemBarAcquire);
a61af66fc99e Initial load
duke
parents:
diff changeset
7431 predicate(Matcher::prior_fast_lock(n));
a61af66fc99e Initial load
duke
parents:
diff changeset
7432 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7433
a61af66fc99e Initial load
duke
parents:
diff changeset
7434 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7435 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7436 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
7437 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
7438 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7439
a61af66fc99e Initial load
duke
parents:
diff changeset
7440 instruct membar_release()
a61af66fc99e Initial load
duke
parents:
diff changeset
7441 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7442 match(MemBarRelease);
a61af66fc99e Initial load
duke
parents:
diff changeset
7443 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7444
a61af66fc99e Initial load
duke
parents:
diff changeset
7445 size(0);
671
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
7446 format %{ "MEMBAR-release ! (empty encoding)" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7447 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
7448 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
7449 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7450
a61af66fc99e Initial load
duke
parents:
diff changeset
7451 instruct membar_release_lock()
a61af66fc99e Initial load
duke
parents:
diff changeset
7452 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7453 match(MemBarRelease);
a61af66fc99e Initial load
duke
parents:
diff changeset
7454 predicate(Matcher::post_fast_unlock(n));
a61af66fc99e Initial load
duke
parents:
diff changeset
7455 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7456
a61af66fc99e Initial load
duke
parents:
diff changeset
7457 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7458 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7459 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
7460 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
7461 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7462
671
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
7463 instruct membar_volatile(rFlagsReg cr) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7464 match(MemBarVolatile);
671
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
7465 effect(KILL cr);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7466 ins_cost(400);
a61af66fc99e Initial load
duke
parents:
diff changeset
7467
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
7468 format %{
671
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
7469 $$template
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
7470 if (os::is_MP()) {
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
7471 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
7472 } else {
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
7473 $$emit$$"MEMBAR-volatile ! (empty encoding)"
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
7474 }
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
7475 %}
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
7476 ins_encode %{
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
7477 __ membar(Assembler::StoreLoad);
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
7478 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7479 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
7480 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7481
a61af66fc99e Initial load
duke
parents:
diff changeset
7482 instruct unnecessary_membar_volatile()
a61af66fc99e Initial load
duke
parents:
diff changeset
7483 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7484 match(MemBarVolatile);
a61af66fc99e Initial load
duke
parents:
diff changeset
7485 predicate(Matcher::post_store_load_barrier(n));
a61af66fc99e Initial load
duke
parents:
diff changeset
7486 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7487
a61af66fc99e Initial load
duke
parents:
diff changeset
7488 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7489 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7490 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
7491 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
7492 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7493
a61af66fc99e Initial load
duke
parents:
diff changeset
7494 //----------Move Instructions--------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7495
a61af66fc99e Initial load
duke
parents:
diff changeset
7496 instruct castX2P(rRegP dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7497 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7498 match(Set dst (CastX2P src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7499
a61af66fc99e Initial load
duke
parents:
diff changeset
7500 format %{ "movq $dst, $src\t# long->ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7501 ins_encode(enc_copy_wide(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7502 ins_pipe(ialu_reg_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7503 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7504
a61af66fc99e Initial load
duke
parents:
diff changeset
7505 instruct castP2X(rRegL dst, rRegP src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7506 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7507 match(Set dst (CastP2X src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7508
a61af66fc99e Initial load
duke
parents:
diff changeset
7509 format %{ "movq $dst, $src\t# ptr -> long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7510 ins_encode(enc_copy_wide(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7511 ins_pipe(ialu_reg_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7512 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7513
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7514
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7515 // Convert oop pointer into compressed form
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7516 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
221
1e026f8da827 6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents: 182
diff changeset
7517 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7518 match(Set dst (EncodeP src));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7519 effect(KILL cr);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7520 format %{ "encode_heap_oop $dst,$src" %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7521 ins_encode %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7522 Register s = $src$$Register;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7523 Register d = $dst$$Register;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7524 if (s != d) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7525 __ movq(d, s);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7526 }
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7527 __ encode_heap_oop(d);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7528 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7529 ins_pipe(ialu_reg_long);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7530 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7531
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7532 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
221
1e026f8da827 6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents: 182
diff changeset
7533 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7534 match(Set dst (EncodeP src));
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7535 effect(KILL cr);
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7536 format %{ "encode_heap_oop_not_null $dst,$src" %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7537 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7538 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7539 %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7540 ins_pipe(ialu_reg_long);
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7541 %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7542
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7543 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
182
44abbb0d4c18 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 169
diff changeset
7544 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
44abbb0d4c18 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 169
diff changeset
7545 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7546 match(Set dst (DecodeN src));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7547 effect(KILL cr);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7548 format %{ "decode_heap_oop $dst,$src" %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7549 ins_encode %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7550 Register s = $src$$Register;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7551 Register d = $dst$$Register;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7552 if (s != d) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7553 __ movq(d, s);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7554 }
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7555 __ decode_heap_oop(d);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7556 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7557 ins_pipe(ialu_reg_long);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7558 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7559
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
7560 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
182
44abbb0d4c18 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 169
diff changeset
7561 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
44abbb0d4c18 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 169
diff changeset
7562 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7563 match(Set dst (DecodeN src));
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
7564 effect(KILL cr);
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7565 format %{ "decode_heap_oop_not_null $dst,$src" %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7566 ins_encode %{
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7567 Register s = $src$$Register;
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7568 Register d = $dst$$Register;
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7569 if (s != d) {
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7570 __ decode_heap_oop_not_null(d, s);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7571 } else {
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7572 __ decode_heap_oop_not_null(d);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
7573 }
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7574 %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7575 ins_pipe(ialu_reg_long);
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7576 %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
7577
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7578
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7579 //----------Conditional Move---------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7580 // Jump
a61af66fc99e Initial load
duke
parents:
diff changeset
7581 // dummy instruction for generating temp registers
a61af66fc99e Initial load
duke
parents:
diff changeset
7582 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7583 match(Jump (LShiftL switch_val shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
7584 ins_cost(350);
a61af66fc99e Initial load
duke
parents:
diff changeset
7585 predicate(false);
a61af66fc99e Initial load
duke
parents:
diff changeset
7586 effect(TEMP dest);
a61af66fc99e Initial load
duke
parents:
diff changeset
7587
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7588 format %{ "leaq $dest, [$constantaddress]\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7589 "jmp [$dest + $switch_val << $shift]\n\t" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7590 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7591 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7592 // to do that and the compiler is using that register as one it can allocate.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7593 // So we build it all by hand.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7594 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7595 // ArrayAddress dispatch(table, index);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7596 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7597 __ lea($dest$$Register, $constantaddress);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7598 __ jmp(dispatch);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7599 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7600 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
7601 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
7602 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7603
a61af66fc99e Initial load
duke
parents:
diff changeset
7604 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7605 match(Jump (AddL (LShiftL switch_val shift) offset));
a61af66fc99e Initial load
duke
parents:
diff changeset
7606 ins_cost(350);
a61af66fc99e Initial load
duke
parents:
diff changeset
7607 effect(TEMP dest);
a61af66fc99e Initial load
duke
parents:
diff changeset
7608
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7609 format %{ "leaq $dest, [$constantaddress]\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7610 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7611 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7612 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7613 // to do that and the compiler is using that register as one it can allocate.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7614 // So we build it all by hand.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7615 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7616 // ArrayAddress dispatch(table, index);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7617 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7618 __ lea($dest$$Register, $constantaddress);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7619 __ jmp(dispatch);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7620 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7621 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
7622 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
7623 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7624
a61af66fc99e Initial load
duke
parents:
diff changeset
7625 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7626 match(Jump switch_val);
a61af66fc99e Initial load
duke
parents:
diff changeset
7627 ins_cost(350);
a61af66fc99e Initial load
duke
parents:
diff changeset
7628 effect(TEMP dest);
a61af66fc99e Initial load
duke
parents:
diff changeset
7629
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7630 format %{ "leaq $dest, [$constantaddress]\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7631 "jmp [$dest + $switch_val]\n\t" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7632 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7633 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7634 // to do that and the compiler is using that register as one it can allocate.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7635 // So we build it all by hand.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7636 // Address index(noreg, switch_reg, Address::times_1);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7637 // ArrayAddress dispatch(table, index);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7638 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7639 __ lea($dest$$Register, $constantaddress);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7640 __ jmp(dispatch);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
7641 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7642 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
7643 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
7644 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7645
a61af66fc99e Initial load
duke
parents:
diff changeset
7646 // Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
7647 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
a61af66fc99e Initial load
duke
parents:
diff changeset
7648 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7649 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7650
a61af66fc99e Initial load
duke
parents:
diff changeset
7651 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7652 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7653 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
7654 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7655 ins_pipe(pipe_cmov_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7656 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7657
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7658 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7659 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7660
a61af66fc99e Initial load
duke
parents:
diff changeset
7661 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7662 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7663 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
7664 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7665 ins_pipe(pipe_cmov_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7666 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7667
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7668 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7669 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7670 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7671 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7672 cmovI_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7673 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7674 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7675
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7676 // Conditional move
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7677 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7678 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
7679
a61af66fc99e Initial load
duke
parents:
diff changeset
7680 ins_cost(250); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7681 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7682 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
7683 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7684 ins_pipe(pipe_cmov_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
7685 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7686
a61af66fc99e Initial load
duke
parents:
diff changeset
7687 // Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
7688 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7689 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7690 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
7691
a61af66fc99e Initial load
duke
parents:
diff changeset
7692 ins_cost(250); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7693 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7694 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
7695 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7696 ins_pipe(pipe_cmov_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
7697 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7698
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7699 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7700 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7701 ins_cost(250);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7702 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7703 cmovI_memU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7704 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7705 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7706
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7707 // Conditional move
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7708 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7709 %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7710 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7711
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7712 ins_cost(200); // XXX
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7713 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7714 opcode(0x0F, 0x40);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7715 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7716 ins_pipe(pipe_cmov_reg);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7717 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7718
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7719 // Conditional move
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7720 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7721 %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7722 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7723
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7724 ins_cost(200); // XXX
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7725 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7726 opcode(0x0F, 0x40);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7727 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7728 ins_pipe(pipe_cmov_reg);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7729 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7730
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7731 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7732 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7733 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7734 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7735 cmovN_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7736 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7737 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7738
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
7739 // Conditional move
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7740 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
a61af66fc99e Initial load
duke
parents:
diff changeset
7741 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7742 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7743
a61af66fc99e Initial load
duke
parents:
diff changeset
7744 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7745 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7746 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
7747 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7748 ins_pipe(pipe_cmov_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7749 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7750
a61af66fc99e Initial load
duke
parents:
diff changeset
7751 // Conditional move
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7752 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7753 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7754 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7755
a61af66fc99e Initial load
duke
parents:
diff changeset
7756 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7757 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7758 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
7759 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7760 ins_pipe(pipe_cmov_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7761 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7762
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7763 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7764 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7765 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7766 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7767 cmovP_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7768 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7769 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7770
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7771 // DISABLED: Requires the ADLC to emit a bottom_type call that
a61af66fc99e Initial load
duke
parents:
diff changeset
7772 // correctly meets the two pointer arguments; one is an incoming
a61af66fc99e Initial load
duke
parents:
diff changeset
7773 // register but the other is a memory operand. ALSO appears to
a61af66fc99e Initial load
duke
parents:
diff changeset
7774 // be buggy with implicit null checks.
a61af66fc99e Initial load
duke
parents:
diff changeset
7775 //
a61af66fc99e Initial load
duke
parents:
diff changeset
7776 //// Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
7777 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7778 //%{
a61af66fc99e Initial load
duke
parents:
diff changeset
7779 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
7780 // ins_cost(250);
a61af66fc99e Initial load
duke
parents:
diff changeset
7781 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7782 // opcode(0x0F,0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
7783 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7784 // ins_pipe( pipe_cmov_mem );
a61af66fc99e Initial load
duke
parents:
diff changeset
7785 //%}
a61af66fc99e Initial load
duke
parents:
diff changeset
7786 //
a61af66fc99e Initial load
duke
parents:
diff changeset
7787 //// Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
7788 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7789 //%{
a61af66fc99e Initial load
duke
parents:
diff changeset
7790 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
7791 // ins_cost(250);
a61af66fc99e Initial load
duke
parents:
diff changeset
7792 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7793 // opcode(0x0F,0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
7794 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
7795 // ins_pipe( pipe_cmov_mem );
a61af66fc99e Initial load
duke
parents:
diff changeset
7796 //%}
a61af66fc99e Initial load
duke
parents:
diff changeset
7797
a61af66fc99e Initial load
duke
parents:
diff changeset
7798 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7799 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7800 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7801
a61af66fc99e Initial load
duke
parents:
diff changeset
7802 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7803 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7804 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
7805 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7806 ins_pipe(pipe_cmov_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7807 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7808
a61af66fc99e Initial load
duke
parents:
diff changeset
7809 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7810 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7811 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
7812
a61af66fc99e Initial load
duke
parents:
diff changeset
7813 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7814 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7815 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
7816 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7817 ins_pipe(pipe_cmov_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7818 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7819
a61af66fc99e Initial load
duke
parents:
diff changeset
7820 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7821 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7822 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7823
a61af66fc99e Initial load
duke
parents:
diff changeset
7824 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7825 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7826 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
7827 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7828 ins_pipe(pipe_cmov_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7829 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7830
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7831 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7832 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7833 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7834 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7835 cmovL_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7836 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7837 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7838
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7839 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7840 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7841 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
7842
a61af66fc99e Initial load
duke
parents:
diff changeset
7843 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7844 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7845 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
7846 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7847 ins_pipe(pipe_cmov_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7848 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7849
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7850 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7851 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7852 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7853 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7854 cmovL_memU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7855 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7856 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7857
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7858 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7859 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7860 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7861
a61af66fc99e Initial load
duke
parents:
diff changeset
7862 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7863 format %{ "jn$cop skip\t# signed cmove float\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7864 "movss $dst, $src\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7865 "skip:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7866 ins_encode(enc_cmovf_branch(cop, dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7867 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
7868 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7869
a61af66fc99e Initial load
duke
parents:
diff changeset
7870 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7871 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7872 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
7873
a61af66fc99e Initial load
duke
parents:
diff changeset
7874 // ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7875 // format %{ "jn$cop skip\t# signed cmove float\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7876 // "movss $dst, $src\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7877 // "skip:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7878 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7879 // ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
7880 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7881
a61af66fc99e Initial load
duke
parents:
diff changeset
7882 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7883 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7884 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7885
a61af66fc99e Initial load
duke
parents:
diff changeset
7886 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7887 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7888 "movss $dst, $src\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7889 "skip:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7890 ins_encode(enc_cmovf_branch(cop, dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7891 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
7892 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7893
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7894 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7895 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7896 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7897 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7898 cmovF_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7899 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7900 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7901
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7902 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7903 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7904 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7905
a61af66fc99e Initial load
duke
parents:
diff changeset
7906 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7907 format %{ "jn$cop skip\t# signed cmove double\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7908 "movsd $dst, $src\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7909 "skip:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7910 ins_encode(enc_cmovd_branch(cop, dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7911 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
7912 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7913
a61af66fc99e Initial load
duke
parents:
diff changeset
7914 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7915 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7916 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7917
a61af66fc99e Initial load
duke
parents:
diff changeset
7918 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7919 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7920 "movsd $dst, $src\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7921 "skip:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7922 ins_encode(enc_cmovd_branch(cop, dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7923 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
7924 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7925
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7926 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7927 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7928 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7929 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7930 cmovD_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7931 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7932 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7933
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7934 //----------Arithmetic Instructions--------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7935 //----------Addition Instructions----------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7936
a61af66fc99e Initial load
duke
parents:
diff changeset
7937 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7938 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7939 match(Set dst (AddI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7940 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7941
a61af66fc99e Initial load
duke
parents:
diff changeset
7942 format %{ "addl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7943 opcode(0x03);
a61af66fc99e Initial load
duke
parents:
diff changeset
7944 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7945 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7946 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7947
a61af66fc99e Initial load
duke
parents:
diff changeset
7948 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7949 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7950 match(Set dst (AddI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7951 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7952
a61af66fc99e Initial load
duke
parents:
diff changeset
7953 format %{ "addl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7954 opcode(0x81, 0x00); /* /0 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7955 ins_encode(OpcSErm(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7956 ins_pipe( ialu_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
7957 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7958
a61af66fc99e Initial load
duke
parents:
diff changeset
7959 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7960 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7961 match(Set dst (AddI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7962 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7963
a61af66fc99e Initial load
duke
parents:
diff changeset
7964 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7965 format %{ "addl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7966 opcode(0x03);
a61af66fc99e Initial load
duke
parents:
diff changeset
7967 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7968 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
7969 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7970
a61af66fc99e Initial load
duke
parents:
diff changeset
7971 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7972 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7973 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7974 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7975
a61af66fc99e Initial load
duke
parents:
diff changeset
7976 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7977 format %{ "addl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7978 opcode(0x01); /* Opcode 01 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
7979 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7980 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7981 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7982
a61af66fc99e Initial load
duke
parents:
diff changeset
7983 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7984 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7985 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7986 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7987
a61af66fc99e Initial load
duke
parents:
diff changeset
7988 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7989 format %{ "addl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7990 opcode(0x81); /* Opcode 81 /0 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7991 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7992 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7993 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7994
a61af66fc99e Initial load
duke
parents:
diff changeset
7995 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7996 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7997 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
7998 match(Set dst (AddI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7999 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8000
a61af66fc99e Initial load
duke
parents:
diff changeset
8001 format %{ "incl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8002 opcode(0xFF, 0x00); // FF /0
a61af66fc99e Initial load
duke
parents:
diff changeset
8003 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8004 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8005 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8006
a61af66fc99e Initial load
duke
parents:
diff changeset
8007 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8008 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8009 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
8010 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8011 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8012
a61af66fc99e Initial load
duke
parents:
diff changeset
8013 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8014 format %{ "incl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8015 opcode(0xFF); /* Opcode FF /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8016 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8017 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8018 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8019
a61af66fc99e Initial load
duke
parents:
diff changeset
8020 // XXX why does that use AddI
a61af66fc99e Initial load
duke
parents:
diff changeset
8021 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8022 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8023 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
8024 match(Set dst (AddI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8025 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8026
a61af66fc99e Initial load
duke
parents:
diff changeset
8027 format %{ "decl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8028 opcode(0xFF, 0x01); // FF /1
a61af66fc99e Initial load
duke
parents:
diff changeset
8029 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8030 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8031 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8032
a61af66fc99e Initial load
duke
parents:
diff changeset
8033 // XXX why does that use AddI
a61af66fc99e Initial load
duke
parents:
diff changeset
8034 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8035 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8036 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
8037 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8038 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8039
a61af66fc99e Initial load
duke
parents:
diff changeset
8040 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8041 format %{ "decl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8042 opcode(0xFF); /* Opcode FF /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8043 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8044 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8045 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8046
a61af66fc99e Initial load
duke
parents:
diff changeset
8047 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
8048 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8049 match(Set dst (AddI src0 src1));
a61af66fc99e Initial load
duke
parents:
diff changeset
8050
a61af66fc99e Initial load
duke
parents:
diff changeset
8051 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
8052 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8053 opcode(0x8D); /* 0x8D /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
8054 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8055 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8056 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8057
a61af66fc99e Initial load
duke
parents:
diff changeset
8058 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8059 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8060 match(Set dst (AddL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8061 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8062
a61af66fc99e Initial load
duke
parents:
diff changeset
8063 format %{ "addq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8064 opcode(0x03);
a61af66fc99e Initial load
duke
parents:
diff changeset
8065 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8066 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8067 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8068
a61af66fc99e Initial load
duke
parents:
diff changeset
8069 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8070 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8071 match(Set dst (AddL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8072 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8073
a61af66fc99e Initial load
duke
parents:
diff changeset
8074 format %{ "addq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8075 opcode(0x81, 0x00); /* /0 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8076 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8077 ins_pipe( ialu_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
8078 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8079
a61af66fc99e Initial load
duke
parents:
diff changeset
8080 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8081 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8082 match(Set dst (AddL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8083 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8084
a61af66fc99e Initial load
duke
parents:
diff changeset
8085 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8086 format %{ "addq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8087 opcode(0x03);
a61af66fc99e Initial load
duke
parents:
diff changeset
8088 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8089 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
8090 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8091
a61af66fc99e Initial load
duke
parents:
diff changeset
8092 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8093 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8094 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8095 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8096
a61af66fc99e Initial load
duke
parents:
diff changeset
8097 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8098 format %{ "addq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8099 opcode(0x01); /* Opcode 01 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
8100 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8101 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8102 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8103
a61af66fc99e Initial load
duke
parents:
diff changeset
8104 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8105 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8106 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8107 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8108
a61af66fc99e Initial load
duke
parents:
diff changeset
8109 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8110 format %{ "addq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8111 opcode(0x81); /* Opcode 81 /0 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8112 ins_encode(REX_mem_wide(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
8113 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8114 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8115 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8116
a61af66fc99e Initial load
duke
parents:
diff changeset
8117 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8118 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8119 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
8120 match(Set dst (AddL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8121 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8122
a61af66fc99e Initial load
duke
parents:
diff changeset
8123 format %{ "incq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8124 opcode(0xFF, 0x00); // FF /0
a61af66fc99e Initial load
duke
parents:
diff changeset
8125 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8126 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8127 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8128
a61af66fc99e Initial load
duke
parents:
diff changeset
8129 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8130 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8131 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
8132 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8133 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8134
a61af66fc99e Initial load
duke
parents:
diff changeset
8135 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8136 format %{ "incq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8137 opcode(0xFF); /* Opcode FF /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8138 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8139 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8140 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8141
a61af66fc99e Initial load
duke
parents:
diff changeset
8142 // XXX why does that use AddL
a61af66fc99e Initial load
duke
parents:
diff changeset
8143 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8144 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8145 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
8146 match(Set dst (AddL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8147 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8148
a61af66fc99e Initial load
duke
parents:
diff changeset
8149 format %{ "decq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8150 opcode(0xFF, 0x01); // FF /1
a61af66fc99e Initial load
duke
parents:
diff changeset
8151 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8152 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8153 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8154
a61af66fc99e Initial load
duke
parents:
diff changeset
8155 // XXX why does that use AddL
a61af66fc99e Initial load
duke
parents:
diff changeset
8156 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8157 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8158 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
8159 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8160 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8161
a61af66fc99e Initial load
duke
parents:
diff changeset
8162 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8163 format %{ "decq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8164 opcode(0xFF); /* Opcode FF /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8165 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8166 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8167 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8168
a61af66fc99e Initial load
duke
parents:
diff changeset
8169 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
8170 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8171 match(Set dst (AddL src0 src1));
a61af66fc99e Initial load
duke
parents:
diff changeset
8172
a61af66fc99e Initial load
duke
parents:
diff changeset
8173 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
8174 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8175 opcode(0x8D); /* 0x8D /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
8176 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8177 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8178 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8179
a61af66fc99e Initial load
duke
parents:
diff changeset
8180 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8181 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8182 match(Set dst (AddP dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8183 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8184
a61af66fc99e Initial load
duke
parents:
diff changeset
8185 format %{ "addq $dst, $src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8186 opcode(0x03);
a61af66fc99e Initial load
duke
parents:
diff changeset
8187 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8188 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8189 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8190
a61af66fc99e Initial load
duke
parents:
diff changeset
8191 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8192 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8193 match(Set dst (AddP dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8194 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8195
a61af66fc99e Initial load
duke
parents:
diff changeset
8196 format %{ "addq $dst, $src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8197 opcode(0x81, 0x00); /* /0 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8198 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8199 ins_pipe( ialu_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
8200 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8201
a61af66fc99e Initial load
duke
parents:
diff changeset
8202 // XXX addP mem ops ????
a61af66fc99e Initial load
duke
parents:
diff changeset
8203
a61af66fc99e Initial load
duke
parents:
diff changeset
8204 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
8205 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8206 match(Set dst (AddP src0 src1));
a61af66fc99e Initial load
duke
parents:
diff changeset
8207
a61af66fc99e Initial load
duke
parents:
diff changeset
8208 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
8209 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8210 opcode(0x8D); /* 0x8D /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
8211 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8212 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8213 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8214
a61af66fc99e Initial load
duke
parents:
diff changeset
8215 instruct checkCastPP(rRegP dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
8216 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8217 match(Set dst (CheckCastPP dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8218
a61af66fc99e Initial load
duke
parents:
diff changeset
8219 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8220 format %{ "# checkcastPP of $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8221 ins_encode(/* empty encoding */);
a61af66fc99e Initial load
duke
parents:
diff changeset
8222 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
8223 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8224
a61af66fc99e Initial load
duke
parents:
diff changeset
8225 instruct castPP(rRegP dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
8226 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8227 match(Set dst (CastPP dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8228
a61af66fc99e Initial load
duke
parents:
diff changeset
8229 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8230 format %{ "# castPP of $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8231 ins_encode(/* empty encoding */);
a61af66fc99e Initial load
duke
parents:
diff changeset
8232 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
8233 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8234
a61af66fc99e Initial load
duke
parents:
diff changeset
8235 instruct castII(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
8236 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8237 match(Set dst (CastII dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8238
a61af66fc99e Initial load
duke
parents:
diff changeset
8239 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8240 format %{ "# castII of $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8241 ins_encode(/* empty encoding */);
a61af66fc99e Initial load
duke
parents:
diff changeset
8242 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8243 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
8244 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8245
a61af66fc99e Initial load
duke
parents:
diff changeset
8246 // LoadP-locked same as a regular LoadP when used with compare-swap
a61af66fc99e Initial load
duke
parents:
diff changeset
8247 instruct loadPLocked(rRegP dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
8248 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8249 match(Set dst (LoadPLocked mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
8250
a61af66fc99e Initial load
duke
parents:
diff changeset
8251 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8252 format %{ "movq $dst, $mem\t# ptr locked" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8253 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
8254 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
8255 ins_pipe(ialu_reg_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8256 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8257
a61af66fc99e Initial load
duke
parents:
diff changeset
8258 // LoadL-locked - same as a regular LoadL when used with compare-swap
a61af66fc99e Initial load
duke
parents:
diff changeset
8259 instruct loadLLocked(rRegL dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
8260 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8261 match(Set dst (LoadLLocked mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
8262
a61af66fc99e Initial load
duke
parents:
diff changeset
8263 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8264 format %{ "movq $dst, $mem\t# long locked" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8265 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
8266 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
8267 ins_pipe(ialu_reg_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8268 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8269
a61af66fc99e Initial load
duke
parents:
diff changeset
8270 // Conditional-store of the updated heap-top.
a61af66fc99e Initial load
duke
parents:
diff changeset
8271 // Used during allocation of the shared heap.
a61af66fc99e Initial load
duke
parents:
diff changeset
8272 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
a61af66fc99e Initial load
duke
parents:
diff changeset
8273
a61af66fc99e Initial load
duke
parents:
diff changeset
8274 instruct storePConditional(memory heap_top_ptr,
a61af66fc99e Initial load
duke
parents:
diff changeset
8275 rax_RegP oldval, rRegP newval,
a61af66fc99e Initial load
duke
parents:
diff changeset
8276 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8277 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8278 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
8279
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8280 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
a61af66fc99e Initial load
duke
parents:
diff changeset
8281 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8282 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8283 ins_encode(lock_prefix,
a61af66fc99e Initial load
duke
parents:
diff changeset
8284 REX_reg_mem_wide(newval, heap_top_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
8285 OpcP, OpcS,
a61af66fc99e Initial load
duke
parents:
diff changeset
8286 reg_mem(newval, heap_top_ptr));
a61af66fc99e Initial load
duke
parents:
diff changeset
8287 ins_pipe(pipe_cmpxchg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8288 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8289
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8290 // Conditional-store of an int value.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8291 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8292 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8293 %{
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8294 match(Set cr (StoreIConditional mem (Binary oldval newval)));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8295 effect(KILL oldval);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8296
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8297 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8298 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8299 ins_encode(lock_prefix,
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8300 REX_reg_mem(newval, mem),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8301 OpcP, OpcS,
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8302 reg_mem(newval, mem));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8303 ins_pipe(pipe_cmpxchg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8304 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8305
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8306 // Conditional-store of a long value.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8307 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8308 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8309 %{
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8310 match(Set cr (StoreLConditional mem (Binary oldval newval)));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8311 effect(KILL oldval);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8312
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8313 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8314 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8315 ins_encode(lock_prefix,
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8316 REX_reg_mem_wide(newval, mem),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8317 OpcP, OpcS,
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8318 reg_mem(newval, mem));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8319 ins_pipe(pipe_cmpxchg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8320 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8321
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8322
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8323 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8324 instruct compareAndSwapP(rRegI res,
a61af66fc99e Initial load
duke
parents:
diff changeset
8325 memory mem_ptr,
a61af66fc99e Initial load
duke
parents:
diff changeset
8326 rax_RegP oldval, rRegP newval,
a61af66fc99e Initial load
duke
parents:
diff changeset
8327 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8328 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8329 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8330 effect(KILL cr, KILL oldval);
a61af66fc99e Initial load
duke
parents:
diff changeset
8331
a61af66fc99e Initial load
duke
parents:
diff changeset
8332 format %{ "cmpxchgq $mem_ptr,$newval\t# "
a61af66fc99e Initial load
duke
parents:
diff changeset
8333 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8334 "sete $res\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8335 "movzbl $res, $res" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8336 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8337 ins_encode(lock_prefix,
a61af66fc99e Initial load
duke
parents:
diff changeset
8338 REX_reg_mem_wide(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
8339 OpcP, OpcS,
a61af66fc99e Initial load
duke
parents:
diff changeset
8340 reg_mem(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
8341 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
a61af66fc99e Initial load
duke
parents:
diff changeset
8342 REX_reg_breg(res, res), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
8343 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
a61af66fc99e Initial load
duke
parents:
diff changeset
8344 ins_pipe( pipe_cmpxchg );
a61af66fc99e Initial load
duke
parents:
diff changeset
8345 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8346
a61af66fc99e Initial load
duke
parents:
diff changeset
8347 instruct compareAndSwapL(rRegI res,
a61af66fc99e Initial load
duke
parents:
diff changeset
8348 memory mem_ptr,
a61af66fc99e Initial load
duke
parents:
diff changeset
8349 rax_RegL oldval, rRegL newval,
a61af66fc99e Initial load
duke
parents:
diff changeset
8350 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8351 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8352 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8353 effect(KILL cr, KILL oldval);
a61af66fc99e Initial load
duke
parents:
diff changeset
8354
a61af66fc99e Initial load
duke
parents:
diff changeset
8355 format %{ "cmpxchgq $mem_ptr,$newval\t# "
a61af66fc99e Initial load
duke
parents:
diff changeset
8356 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8357 "sete $res\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8358 "movzbl $res, $res" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8359 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8360 ins_encode(lock_prefix,
a61af66fc99e Initial load
duke
parents:
diff changeset
8361 REX_reg_mem_wide(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
8362 OpcP, OpcS,
a61af66fc99e Initial load
duke
parents:
diff changeset
8363 reg_mem(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
8364 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
a61af66fc99e Initial load
duke
parents:
diff changeset
8365 REX_reg_breg(res, res), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
8366 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
a61af66fc99e Initial load
duke
parents:
diff changeset
8367 ins_pipe( pipe_cmpxchg );
a61af66fc99e Initial load
duke
parents:
diff changeset
8368 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8369
a61af66fc99e Initial load
duke
parents:
diff changeset
8370 instruct compareAndSwapI(rRegI res,
a61af66fc99e Initial load
duke
parents:
diff changeset
8371 memory mem_ptr,
a61af66fc99e Initial load
duke
parents:
diff changeset
8372 rax_RegI oldval, rRegI newval,
a61af66fc99e Initial load
duke
parents:
diff changeset
8373 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8374 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8375 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8376 effect(KILL cr, KILL oldval);
a61af66fc99e Initial load
duke
parents:
diff changeset
8377
a61af66fc99e Initial load
duke
parents:
diff changeset
8378 format %{ "cmpxchgl $mem_ptr,$newval\t# "
a61af66fc99e Initial load
duke
parents:
diff changeset
8379 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8380 "sete $res\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8381 "movzbl $res, $res" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8382 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
8383 ins_encode(lock_prefix,
a61af66fc99e Initial load
duke
parents:
diff changeset
8384 REX_reg_mem(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
8385 OpcP, OpcS,
a61af66fc99e Initial load
duke
parents:
diff changeset
8386 reg_mem(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
8387 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
a61af66fc99e Initial load
duke
parents:
diff changeset
8388 REX_reg_breg(res, res), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
8389 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
a61af66fc99e Initial load
duke
parents:
diff changeset
8390 ins_pipe( pipe_cmpxchg );
a61af66fc99e Initial load
duke
parents:
diff changeset
8391 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8392
a61af66fc99e Initial load
duke
parents:
diff changeset
8393
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8394 instruct compareAndSwapN(rRegI res,
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8395 memory mem_ptr,
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8396 rax_RegN oldval, rRegN newval,
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8397 rFlagsReg cr) %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8398 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8399 effect(KILL cr, KILL oldval);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8400
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8401 format %{ "cmpxchgl $mem_ptr,$newval\t# "
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8402 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8403 "sete $res\n\t"
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8404 "movzbl $res, $res" %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8405 opcode(0x0F, 0xB1);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8406 ins_encode(lock_prefix,
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8407 REX_reg_mem(newval, mem_ptr),
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8408 OpcP, OpcS,
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8409 reg_mem(newval, mem_ptr),
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8410 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8411 REX_reg_breg(res, res), // movzbl
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8412 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8413 ins_pipe( pipe_cmpxchg );
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8414 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
8415
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8416 //----------Subtraction Instructions-------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
8417
a61af66fc99e Initial load
duke
parents:
diff changeset
8418 // Integer Subtraction Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8419 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8420 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8421 match(Set dst (SubI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8422 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8423
a61af66fc99e Initial load
duke
parents:
diff changeset
8424 format %{ "subl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8425 opcode(0x2B);
a61af66fc99e Initial load
duke
parents:
diff changeset
8426 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8427 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8428 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8429
a61af66fc99e Initial load
duke
parents:
diff changeset
8430 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8431 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8432 match(Set dst (SubI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8433 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8434
a61af66fc99e Initial load
duke
parents:
diff changeset
8435 format %{ "subl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8436 opcode(0x81, 0x05); /* Opcode 81 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8437 ins_encode(OpcSErm(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8438 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8439 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8440
a61af66fc99e Initial load
duke
parents:
diff changeset
8441 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8442 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8443 match(Set dst (SubI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8444 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8445
a61af66fc99e Initial load
duke
parents:
diff changeset
8446 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
8447 format %{ "subl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8448 opcode(0x2B);
a61af66fc99e Initial load
duke
parents:
diff changeset
8449 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8450 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
8451 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8452
a61af66fc99e Initial load
duke
parents:
diff changeset
8453 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8454 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8455 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8456 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8457
a61af66fc99e Initial load
duke
parents:
diff changeset
8458 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
8459 format %{ "subl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8460 opcode(0x29); /* Opcode 29 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
8461 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8462 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8463 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8464
a61af66fc99e Initial load
duke
parents:
diff changeset
8465 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8466 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8467 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8468 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8469
a61af66fc99e Initial load
duke
parents:
diff changeset
8470 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8471 format %{ "subl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8472 opcode(0x81); /* Opcode 81 /5 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8473 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8474 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8475 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8476
a61af66fc99e Initial load
duke
parents:
diff changeset
8477 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8478 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8479 match(Set dst (SubL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8480 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8481
a61af66fc99e Initial load
duke
parents:
diff changeset
8482 format %{ "subq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8483 opcode(0x2B);
a61af66fc99e Initial load
duke
parents:
diff changeset
8484 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8485 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8486 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8487
a61af66fc99e Initial load
duke
parents:
diff changeset
8488 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8489 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8490 match(Set dst (SubL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8491 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8492
a61af66fc99e Initial load
duke
parents:
diff changeset
8493 format %{ "subq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8494 opcode(0x81, 0x05); /* Opcode 81 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8495 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8496 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8497 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8498
a61af66fc99e Initial load
duke
parents:
diff changeset
8499 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8500 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8501 match(Set dst (SubL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8502 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8503
a61af66fc99e Initial load
duke
parents:
diff changeset
8504 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
8505 format %{ "subq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8506 opcode(0x2B);
a61af66fc99e Initial load
duke
parents:
diff changeset
8507 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8508 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
8509 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8510
a61af66fc99e Initial load
duke
parents:
diff changeset
8511 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8512 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8513 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8514 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8515
a61af66fc99e Initial load
duke
parents:
diff changeset
8516 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
8517 format %{ "subq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8518 opcode(0x29); /* Opcode 29 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
8519 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8520 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8521 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8522
a61af66fc99e Initial load
duke
parents:
diff changeset
8523 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8524 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8525 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8526 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8527
a61af66fc99e Initial load
duke
parents:
diff changeset
8528 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8529 format %{ "subq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8530 opcode(0x81); /* Opcode 81 /5 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8531 ins_encode(REX_mem_wide(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
8532 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8533 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8534 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8535
a61af66fc99e Initial load
duke
parents:
diff changeset
8536 // Subtract from a pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
8537 // XXX hmpf???
a61af66fc99e Initial load
duke
parents:
diff changeset
8538 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8539 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8540 match(Set dst (AddP dst (SubI zero src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8541 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8542
a61af66fc99e Initial load
duke
parents:
diff changeset
8543 format %{ "subq $dst, $src\t# ptr - int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8544 opcode(0x2B);
a61af66fc99e Initial load
duke
parents:
diff changeset
8545 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8546 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8547 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8548
a61af66fc99e Initial load
duke
parents:
diff changeset
8549 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8550 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8551 match(Set dst (SubI zero dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8552 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8553
a61af66fc99e Initial load
duke
parents:
diff changeset
8554 format %{ "negl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8555 opcode(0xF7, 0x03); // Opcode F7 /3
a61af66fc99e Initial load
duke
parents:
diff changeset
8556 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8557 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8558 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8559
a61af66fc99e Initial load
duke
parents:
diff changeset
8560 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8561 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8562 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8563 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8564
a61af66fc99e Initial load
duke
parents:
diff changeset
8565 format %{ "negl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8566 opcode(0xF7, 0x03); // Opcode F7 /3
a61af66fc99e Initial load
duke
parents:
diff changeset
8567 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8568 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8569 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8570
a61af66fc99e Initial load
duke
parents:
diff changeset
8571 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8572 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8573 match(Set dst (SubL zero dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8574 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8575
a61af66fc99e Initial load
duke
parents:
diff changeset
8576 format %{ "negq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8577 opcode(0xF7, 0x03); // Opcode F7 /3
a61af66fc99e Initial load
duke
parents:
diff changeset
8578 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8579 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8580 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8581
a61af66fc99e Initial load
duke
parents:
diff changeset
8582 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8583 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8584 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8585 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8586
a61af66fc99e Initial load
duke
parents:
diff changeset
8587 format %{ "negq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8588 opcode(0xF7, 0x03); // Opcode F7 /3
a61af66fc99e Initial load
duke
parents:
diff changeset
8589 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8590 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8591 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8592
a61af66fc99e Initial load
duke
parents:
diff changeset
8593
a61af66fc99e Initial load
duke
parents:
diff changeset
8594 //----------Multiplication/Division Instructions-------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
8595 // Integer Multiplication Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8596 // Multiply Register
a61af66fc99e Initial load
duke
parents:
diff changeset
8597
a61af66fc99e Initial load
duke
parents:
diff changeset
8598 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8599 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8600 match(Set dst (MulI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8601 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8602
a61af66fc99e Initial load
duke
parents:
diff changeset
8603 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
8604 format %{ "imull $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8605 opcode(0x0F, 0xAF);
a61af66fc99e Initial load
duke
parents:
diff changeset
8606 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8607 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8608 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8609
a61af66fc99e Initial load
duke
parents:
diff changeset
8610 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8611 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8612 match(Set dst (MulI src imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
8613 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8614
a61af66fc99e Initial load
duke
parents:
diff changeset
8615 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
8616 format %{ "imull $dst, $src, $imm\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8617 opcode(0x69); /* 69 /r id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8618 ins_encode(REX_reg_reg(dst, src),
a61af66fc99e Initial load
duke
parents:
diff changeset
8619 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
8620 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8621 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8622
a61af66fc99e Initial load
duke
parents:
diff changeset
8623 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8624 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8625 match(Set dst (MulI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8626 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8627
a61af66fc99e Initial load
duke
parents:
diff changeset
8628 ins_cost(350);
a61af66fc99e Initial load
duke
parents:
diff changeset
8629 format %{ "imull $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8630 opcode(0x0F, 0xAF);
a61af66fc99e Initial load
duke
parents:
diff changeset
8631 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8632 ins_pipe(ialu_reg_mem_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8633 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8634
a61af66fc99e Initial load
duke
parents:
diff changeset
8635 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8636 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8637 match(Set dst (MulI (LoadI src) imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
8638 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8639
a61af66fc99e Initial load
duke
parents:
diff changeset
8640 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
8641 format %{ "imull $dst, $src, $imm\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8642 opcode(0x69); /* 69 /r id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8643 ins_encode(REX_reg_mem(dst, src),
a61af66fc99e Initial load
duke
parents:
diff changeset
8644 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
8645 ins_pipe(ialu_reg_mem_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8646 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8647
a61af66fc99e Initial load
duke
parents:
diff changeset
8648 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8649 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8650 match(Set dst (MulL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8651 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8652
a61af66fc99e Initial load
duke
parents:
diff changeset
8653 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
8654 format %{ "imulq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8655 opcode(0x0F, 0xAF);
a61af66fc99e Initial load
duke
parents:
diff changeset
8656 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8657 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8658 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8659
a61af66fc99e Initial load
duke
parents:
diff changeset
8660 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8661 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8662 match(Set dst (MulL src imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
8663 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8664
a61af66fc99e Initial load
duke
parents:
diff changeset
8665 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
8666 format %{ "imulq $dst, $src, $imm\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8667 opcode(0x69); /* 69 /r id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8668 ins_encode(REX_reg_reg_wide(dst, src),
a61af66fc99e Initial load
duke
parents:
diff changeset
8669 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
8670 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8671 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8672
a61af66fc99e Initial load
duke
parents:
diff changeset
8673 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8674 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8675 match(Set dst (MulL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8676 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8677
a61af66fc99e Initial load
duke
parents:
diff changeset
8678 ins_cost(350);
a61af66fc99e Initial load
duke
parents:
diff changeset
8679 format %{ "imulq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8680 opcode(0x0F, 0xAF);
a61af66fc99e Initial load
duke
parents:
diff changeset
8681 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8682 ins_pipe(ialu_reg_mem_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8683 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8684
a61af66fc99e Initial load
duke
parents:
diff changeset
8685 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8686 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8687 match(Set dst (MulL (LoadL src) imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
8688 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8689
a61af66fc99e Initial load
duke
parents:
diff changeset
8690 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
8691 format %{ "imulq $dst, $src, $imm\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8692 opcode(0x69); /* 69 /r id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8693 ins_encode(REX_reg_mem_wide(dst, src),
a61af66fc99e Initial load
duke
parents:
diff changeset
8694 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
8695 ins_pipe(ialu_reg_mem_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8696 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8697
145
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
8698 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
8699 %{
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
8700 match(Set dst (MulHiL src rax));
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
8701 effect(USE_KILL rax, KILL cr);
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
8702
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
8703 ins_cost(300);
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
8704 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
8705 opcode(0xF7, 0x5); /* Opcode F7 /5 */
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
8706 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
8707 ins_pipe(ialu_reg_reg_alu0);
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
8708 %}
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
8709
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8710 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
a61af66fc99e Initial load
duke
parents:
diff changeset
8711 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8712 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8713 match(Set rax (DivI rax div));
a61af66fc99e Initial load
duke
parents:
diff changeset
8714 effect(KILL rdx, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8715
a61af66fc99e Initial load
duke
parents:
diff changeset
8716 ins_cost(30*100+10*100); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8717 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8718 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8719 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8720 "cmpl $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8721 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8722 "normal: cdql\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8723 "idivl $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8724 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8725 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8726 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
8727 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8728 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8729
a61af66fc99e Initial load
duke
parents:
diff changeset
8730 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
a61af66fc99e Initial load
duke
parents:
diff changeset
8731 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8732 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8733 match(Set rax (DivL rax div));
a61af66fc99e Initial load
duke
parents:
diff changeset
8734 effect(KILL rdx, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8735
a61af66fc99e Initial load
duke
parents:
diff changeset
8736 ins_cost(30*100+10*100); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8737 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8738 "cmpq rax, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8739 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8740 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8741 "cmpq $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8742 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8743 "normal: cdqq\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8744 "idivq $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8745 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8746 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8747 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
8748 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8749 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8750
a61af66fc99e Initial load
duke
parents:
diff changeset
8751 // Integer DIVMOD with Register, both quotient and mod results
a61af66fc99e Initial load
duke
parents:
diff changeset
8752 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
a61af66fc99e Initial load
duke
parents:
diff changeset
8753 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8754 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8755 match(DivModI rax div);
a61af66fc99e Initial load
duke
parents:
diff changeset
8756 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8757
a61af66fc99e Initial load
duke
parents:
diff changeset
8758 ins_cost(30*100+10*100); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8759 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8760 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8761 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8762 "cmpl $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8763 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8764 "normal: cdql\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8765 "idivl $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8766 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8767 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8768 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
8769 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
8770 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8771
a61af66fc99e Initial load
duke
parents:
diff changeset
8772 // Long DIVMOD with Register, both quotient and mod results
a61af66fc99e Initial load
duke
parents:
diff changeset
8773 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
a61af66fc99e Initial load
duke
parents:
diff changeset
8774 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8775 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8776 match(DivModL rax div);
a61af66fc99e Initial load
duke
parents:
diff changeset
8777 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8778
a61af66fc99e Initial load
duke
parents:
diff changeset
8779 ins_cost(30*100+10*100); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8780 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8781 "cmpq rax, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8782 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8783 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8784 "cmpq $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8785 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8786 "normal: cdqq\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8787 "idivq $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8788 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8789 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8790 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
8791 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
8792 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8793
a61af66fc99e Initial load
duke
parents:
diff changeset
8794 //----------- DivL-By-Constant-Expansions--------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
8795 // DivI cases are handled by the compiler
a61af66fc99e Initial load
duke
parents:
diff changeset
8796
605
98cb887364d3 6810672: Comment typos
twisti
parents: 569
diff changeset
8797 // Magic constant, reciprocal of 10
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8798 instruct loadConL_0x6666666666666667(rRegL dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
8799 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8800 effect(DEF dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
8801
a61af66fc99e Initial load
duke
parents:
diff changeset
8802 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8803 ins_encode(load_immL(dst, 0x6666666666666667));
a61af66fc99e Initial load
duke
parents:
diff changeset
8804 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8805 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8806
a61af66fc99e Initial load
duke
parents:
diff changeset
8807 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8808 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8809 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8810
a61af66fc99e Initial load
duke
parents:
diff changeset
8811 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8812 opcode(0xF7, 0x5); /* Opcode F7 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8813 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8814 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8815 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8816
a61af66fc99e Initial load
duke
parents:
diff changeset
8817 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8818 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8819 effect(USE_DEF dst, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8820
a61af66fc99e Initial load
duke
parents:
diff changeset
8821 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8822 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8823 ins_encode(reg_opc_imm_wide(dst, 0x3F));
a61af66fc99e Initial load
duke
parents:
diff changeset
8824 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8825 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8826
a61af66fc99e Initial load
duke
parents:
diff changeset
8827 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8828 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8829 effect(USE_DEF dst, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8830
a61af66fc99e Initial load
duke
parents:
diff changeset
8831 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8832 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8833 ins_encode(reg_opc_imm_wide(dst, 0x2));
a61af66fc99e Initial load
duke
parents:
diff changeset
8834 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8835 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8836
a61af66fc99e Initial load
duke
parents:
diff changeset
8837 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
a61af66fc99e Initial load
duke
parents:
diff changeset
8838 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8839 match(Set dst (DivL src div));
a61af66fc99e Initial load
duke
parents:
diff changeset
8840
a61af66fc99e Initial load
duke
parents:
diff changeset
8841 ins_cost((5+8)*100);
a61af66fc99e Initial load
duke
parents:
diff changeset
8842 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8843 rax_RegL rax; // Killed temp
a61af66fc99e Initial load
duke
parents:
diff changeset
8844 rFlagsReg cr; // Killed
a61af66fc99e Initial load
duke
parents:
diff changeset
8845 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
a61af66fc99e Initial load
duke
parents:
diff changeset
8846 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
a61af66fc99e Initial load
duke
parents:
diff changeset
8847 sarL_rReg_63(src, cr); // sarq src, 63
a61af66fc99e Initial load
duke
parents:
diff changeset
8848 sarL_rReg_2(dst, cr); // sarq rdx, 2
a61af66fc99e Initial load
duke
parents:
diff changeset
8849 subL_rReg(dst, src, cr); // subl rdx, src
a61af66fc99e Initial load
duke
parents:
diff changeset
8850 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8851 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8852
a61af66fc99e Initial load
duke
parents:
diff changeset
8853 //-----------------------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
8854
a61af66fc99e Initial load
duke
parents:
diff changeset
8855 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
a61af66fc99e Initial load
duke
parents:
diff changeset
8856 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8857 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8858 match(Set rdx (ModI rax div));
a61af66fc99e Initial load
duke
parents:
diff changeset
8859 effect(KILL rax, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8860
a61af66fc99e Initial load
duke
parents:
diff changeset
8861 ins_cost(300); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8862 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8863 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8864 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8865 "cmpl $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8866 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8867 "normal: cdql\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8868 "idivl $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8869 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8870 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8871 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
8872 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8873 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8874
a61af66fc99e Initial load
duke
parents:
diff changeset
8875 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
a61af66fc99e Initial load
duke
parents:
diff changeset
8876 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8877 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8878 match(Set rdx (ModL rax div));
a61af66fc99e Initial load
duke
parents:
diff changeset
8879 effect(KILL rax, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8880
a61af66fc99e Initial load
duke
parents:
diff changeset
8881 ins_cost(300); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8882 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8883 "cmpq rax, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8884 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8885 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8886 "cmpq $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8887 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8888 "normal: cdqq\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8889 "idivq $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8890 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8891 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8892 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
8893 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8894 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8895
a61af66fc99e Initial load
duke
parents:
diff changeset
8896 // Integer Shift Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8897 // Shift Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8898 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8899 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8900 match(Set dst (LShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8901 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8902
a61af66fc99e Initial load
duke
parents:
diff changeset
8903 format %{ "sall $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8904 opcode(0xD1, 0x4); /* D1 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8905 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8906 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8907 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8908
a61af66fc99e Initial load
duke
parents:
diff changeset
8909 // Shift Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8910 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8911 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8912 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8913 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8914
a61af66fc99e Initial load
duke
parents:
diff changeset
8915 format %{ "sall $dst, $shift\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8916 opcode(0xD1, 0x4); /* D1 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8917 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8918 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8919 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8920
a61af66fc99e Initial load
duke
parents:
diff changeset
8921 // Shift Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8922 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8923 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8924 match(Set dst (LShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8925 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8926
a61af66fc99e Initial load
duke
parents:
diff changeset
8927 format %{ "sall $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8928 opcode(0xC1, 0x4); /* C1 /4 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8929 ins_encode(reg_opc_imm(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8930 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8931 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8932
a61af66fc99e Initial load
duke
parents:
diff changeset
8933 // Shift Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8934 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8935 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8936 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8937 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8938
a61af66fc99e Initial load
duke
parents:
diff changeset
8939 format %{ "sall $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8940 opcode(0xC1, 0x4); /* C1 /4 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8941 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8942 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8943 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8944
a61af66fc99e Initial load
duke
parents:
diff changeset
8945 // Shift Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8946 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8947 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8948 match(Set dst (LShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8949 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8950
a61af66fc99e Initial load
duke
parents:
diff changeset
8951 format %{ "sall $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8952 opcode(0xD3, 0x4); /* D3 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8953 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8954 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8955 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8956
a61af66fc99e Initial load
duke
parents:
diff changeset
8957 // Shift Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8958 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8959 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8960 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8961 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8962
a61af66fc99e Initial load
duke
parents:
diff changeset
8963 format %{ "sall $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8964 opcode(0xD3, 0x4); /* D3 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8965 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8966 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8967 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8968
a61af66fc99e Initial load
duke
parents:
diff changeset
8969 // Arithmetic shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8970 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8971 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8972 match(Set dst (RShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8973 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8974
a61af66fc99e Initial load
duke
parents:
diff changeset
8975 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8976 opcode(0xD1, 0x7); /* D1 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8977 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8978 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8979 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8980
a61af66fc99e Initial load
duke
parents:
diff changeset
8981 // Arithmetic shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8982 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8983 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8984 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8985 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8986
a61af66fc99e Initial load
duke
parents:
diff changeset
8987 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8988 opcode(0xD1, 0x7); /* D1 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8989 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8990 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8991 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8992
a61af66fc99e Initial load
duke
parents:
diff changeset
8993 // Arithmetic Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8994 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8995 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8996 match(Set dst (RShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8997 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8998
a61af66fc99e Initial load
duke
parents:
diff changeset
8999 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9000 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
9001 ins_encode(reg_opc_imm(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9002 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9003 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9004
a61af66fc99e Initial load
duke
parents:
diff changeset
9005 // Arithmetic Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9006 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9007 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9008 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9009 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9010
a61af66fc99e Initial load
duke
parents:
diff changeset
9011 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9012 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
9013 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9014 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9015 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9016
a61af66fc99e Initial load
duke
parents:
diff changeset
9017 // Arithmetic Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9018 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9019 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9020 match(Set dst (RShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9021 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9022
a61af66fc99e Initial load
duke
parents:
diff changeset
9023 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9024 opcode(0xD3, 0x7); /* D3 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9025 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9026 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9027 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9028
a61af66fc99e Initial load
duke
parents:
diff changeset
9029 // Arithmetic Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9030 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9031 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9032 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9033 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9034
a61af66fc99e Initial load
duke
parents:
diff changeset
9035 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9036 opcode(0xD3, 0x7); /* D3 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9037 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9038 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9039 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9040
a61af66fc99e Initial load
duke
parents:
diff changeset
9041 // Logical shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
9042 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9043 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9044 match(Set dst (URShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9045 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9046
a61af66fc99e Initial load
duke
parents:
diff changeset
9047 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9048 opcode(0xD1, 0x5); /* D1 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9049 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9050 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9051 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9052
a61af66fc99e Initial load
duke
parents:
diff changeset
9053 // Logical shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
9054 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9055 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9056 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9057 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9058
a61af66fc99e Initial load
duke
parents:
diff changeset
9059 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9060 opcode(0xD1, 0x5); /* D1 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9061 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9062 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9063 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9064
a61af66fc99e Initial load
duke
parents:
diff changeset
9065 // Logical Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9066 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9067 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9068 match(Set dst (URShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9069 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9070
a61af66fc99e Initial load
duke
parents:
diff changeset
9071 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9072 opcode(0xC1, 0x5); /* C1 /5 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
9073 ins_encode(reg_opc_imm(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9074 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9075 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9076
a61af66fc99e Initial load
duke
parents:
diff changeset
9077 // Logical Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9078 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9079 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9080 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9081 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9082
a61af66fc99e Initial load
duke
parents:
diff changeset
9083 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9084 opcode(0xC1, 0x5); /* C1 /5 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
9085 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9086 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9087 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9088
a61af66fc99e Initial load
duke
parents:
diff changeset
9089 // Logical Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9090 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9091 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9092 match(Set dst (URShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9093 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9094
a61af66fc99e Initial load
duke
parents:
diff changeset
9095 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9096 opcode(0xD3, 0x5); /* D3 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9097 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9098 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9099 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9100
a61af66fc99e Initial load
duke
parents:
diff changeset
9101 // Logical Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9102 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9103 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9104 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9105 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9106
a61af66fc99e Initial load
duke
parents:
diff changeset
9107 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9108 opcode(0xD3, 0x5); /* D3 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9109 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9110 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9111 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9112
a61af66fc99e Initial load
duke
parents:
diff changeset
9113 // Long Shift Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
9114 // Shift Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
9115 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9116 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9117 match(Set dst (LShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9118 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9119
a61af66fc99e Initial load
duke
parents:
diff changeset
9120 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9121 opcode(0xD1, 0x4); /* D1 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9122 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9123 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9124 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9125
a61af66fc99e Initial load
duke
parents:
diff changeset
9126 // Shift Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
9127 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9128 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9129 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9130 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9131
a61af66fc99e Initial load
duke
parents:
diff changeset
9132 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9133 opcode(0xD1, 0x4); /* D1 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9134 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9135 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9136 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9137
a61af66fc99e Initial load
duke
parents:
diff changeset
9138 // Shift Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9139 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9140 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9141 match(Set dst (LShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9142 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9143
a61af66fc99e Initial load
duke
parents:
diff changeset
9144 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9145 opcode(0xC1, 0x4); /* C1 /4 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
9146 ins_encode(reg_opc_imm_wide(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9147 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9148 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9149
a61af66fc99e Initial load
duke
parents:
diff changeset
9150 // Shift Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9151 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9152 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9153 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9154 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9155
a61af66fc99e Initial load
duke
parents:
diff changeset
9156 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9157 opcode(0xC1, 0x4); /* C1 /4 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
9158 ins_encode(REX_mem_wide(dst), OpcP,
a61af66fc99e Initial load
duke
parents:
diff changeset
9159 RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9160 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9161 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9162
a61af66fc99e Initial load
duke
parents:
diff changeset
9163 // Shift Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9164 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9165 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9166 match(Set dst (LShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9167 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9168
a61af66fc99e Initial load
duke
parents:
diff changeset
9169 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9170 opcode(0xD3, 0x4); /* D3 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9171 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9172 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9173 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9174
a61af66fc99e Initial load
duke
parents:
diff changeset
9175 // Shift Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9176 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9177 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9178 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9179 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9180
a61af66fc99e Initial load
duke
parents:
diff changeset
9181 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9182 opcode(0xD3, 0x4); /* D3 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9183 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9184 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9185 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9186
a61af66fc99e Initial load
duke
parents:
diff changeset
9187 // Arithmetic shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
9188 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9189 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9190 match(Set dst (RShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9191 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9192
a61af66fc99e Initial load
duke
parents:
diff changeset
9193 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9194 opcode(0xD1, 0x7); /* D1 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9195 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9196 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9197 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9198
a61af66fc99e Initial load
duke
parents:
diff changeset
9199 // Arithmetic shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
9200 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9201 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9202 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9203 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9204
a61af66fc99e Initial load
duke
parents:
diff changeset
9205 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9206 opcode(0xD1, 0x7); /* D1 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9207 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9208 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9209 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9210
a61af66fc99e Initial load
duke
parents:
diff changeset
9211 // Arithmetic Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9212 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9213 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9214 match(Set dst (RShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9215 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9216
a61af66fc99e Initial load
duke
parents:
diff changeset
9217 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9218 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
9219 ins_encode(reg_opc_imm_wide(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9220 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9221 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9222
a61af66fc99e Initial load
duke
parents:
diff changeset
9223 // Arithmetic Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9224 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9225 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9226 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9227 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9228
a61af66fc99e Initial load
duke
parents:
diff changeset
9229 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9230 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
9231 ins_encode(REX_mem_wide(dst), OpcP,
a61af66fc99e Initial load
duke
parents:
diff changeset
9232 RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9233 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9234 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9235
a61af66fc99e Initial load
duke
parents:
diff changeset
9236 // Arithmetic Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9237 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9238 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9239 match(Set dst (RShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9240 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9241
a61af66fc99e Initial load
duke
parents:
diff changeset
9242 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9243 opcode(0xD3, 0x7); /* D3 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9244 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9245 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9246 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9247
a61af66fc99e Initial load
duke
parents:
diff changeset
9248 // Arithmetic Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9249 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9250 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9251 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9252 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9253
a61af66fc99e Initial load
duke
parents:
diff changeset
9254 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9255 opcode(0xD3, 0x7); /* D3 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9256 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9257 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9258 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9259
a61af66fc99e Initial load
duke
parents:
diff changeset
9260 // Logical shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
9261 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9262 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9263 match(Set dst (URShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9264 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9265
a61af66fc99e Initial load
duke
parents:
diff changeset
9266 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9267 opcode(0xD1, 0x5); /* D1 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9268 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
a61af66fc99e Initial load
duke
parents:
diff changeset
9269 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9270 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9271
a61af66fc99e Initial load
duke
parents:
diff changeset
9272 // Logical shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
9273 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9274 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9275 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9276 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9277
a61af66fc99e Initial load
duke
parents:
diff changeset
9278 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9279 opcode(0xD1, 0x5); /* D1 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9280 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9281 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9282 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9283
a61af66fc99e Initial load
duke
parents:
diff changeset
9284 // Logical Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9285 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9286 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9287 match(Set dst (URShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9288 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9289
a61af66fc99e Initial load
duke
parents:
diff changeset
9290 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9291 opcode(0xC1, 0x5); /* C1 /5 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
9292 ins_encode(reg_opc_imm_wide(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9293 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9294 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9295
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
9296
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9297 // Logical Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9298 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9299 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9300 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9301 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9302
a61af66fc99e Initial load
duke
parents:
diff changeset
9303 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9304 opcode(0xC1, 0x5); /* C1 /5 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
9305 ins_encode(REX_mem_wide(dst), OpcP,
a61af66fc99e Initial load
duke
parents:
diff changeset
9306 RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9307 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9308 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9309
a61af66fc99e Initial load
duke
parents:
diff changeset
9310 // Logical Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9311 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9312 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9313 match(Set dst (URShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9314 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9315
a61af66fc99e Initial load
duke
parents:
diff changeset
9316 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9317 opcode(0xD3, 0x5); /* D3 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9318 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9319 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9320 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9321
a61af66fc99e Initial load
duke
parents:
diff changeset
9322 // Logical Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9323 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9324 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9325 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9326 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9327
a61af66fc99e Initial load
duke
parents:
diff changeset
9328 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9329 opcode(0xD3, 0x5); /* D3 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9330 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9331 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9332 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9333
a61af66fc99e Initial load
duke
parents:
diff changeset
9334 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
a61af66fc99e Initial load
duke
parents:
diff changeset
9335 // This idiom is used by the compiler for the i2b bytecode.
a61af66fc99e Initial load
duke
parents:
diff changeset
9336 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
a61af66fc99e Initial load
duke
parents:
diff changeset
9337 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9338 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
a61af66fc99e Initial load
duke
parents:
diff changeset
9339
a61af66fc99e Initial load
duke
parents:
diff changeset
9340 format %{ "movsbl $dst, $src\t# i2b" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9341 opcode(0x0F, 0xBE);
a61af66fc99e Initial load
duke
parents:
diff changeset
9342 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9343 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9344 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9345
a61af66fc99e Initial load
duke
parents:
diff changeset
9346 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
a61af66fc99e Initial load
duke
parents:
diff changeset
9347 // This idiom is used by the compiler the i2s bytecode.
a61af66fc99e Initial load
duke
parents:
diff changeset
9348 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
a61af66fc99e Initial load
duke
parents:
diff changeset
9349 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9350 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
a61af66fc99e Initial load
duke
parents:
diff changeset
9351
a61af66fc99e Initial load
duke
parents:
diff changeset
9352 format %{ "movswl $dst, $src\t# i2s" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9353 opcode(0x0F, 0xBF);
a61af66fc99e Initial load
duke
parents:
diff changeset
9354 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9355 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9356 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9357
a61af66fc99e Initial load
duke
parents:
diff changeset
9358 // ROL/ROR instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
9359
a61af66fc99e Initial load
duke
parents:
diff changeset
9360 // ROL expand
a61af66fc99e Initial load
duke
parents:
diff changeset
9361 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9362 effect(KILL cr, USE_DEF dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
9363
a61af66fc99e Initial load
duke
parents:
diff changeset
9364 format %{ "roll $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9365 opcode(0xD1, 0x0); /* Opcode D1 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9366 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9367 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9368 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9369
a61af66fc99e Initial load
duke
parents:
diff changeset
9370 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9371 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9372
a61af66fc99e Initial load
duke
parents:
diff changeset
9373 format %{ "roll $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9374 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
9375 ins_encode( reg_opc_imm(dst, shift) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9376 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9377 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9378
a61af66fc99e Initial load
duke
parents:
diff changeset
9379 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9380 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9381 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9382
a61af66fc99e Initial load
duke
parents:
diff changeset
9383 format %{ "roll $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9384 opcode(0xD3, 0x0); /* Opcode D3 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9385 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9386 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9387 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9388 // end of ROL expand
a61af66fc99e Initial load
duke
parents:
diff changeset
9389
a61af66fc99e Initial load
duke
parents:
diff changeset
9390 // Rotate Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
9391 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9392 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9393 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9394
a61af66fc99e Initial load
duke
parents:
diff changeset
9395 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9396 rolI_rReg_imm1(dst, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9397 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9398 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9399
a61af66fc99e Initial load
duke
parents:
diff changeset
9400 // Rotate Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9401 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9402 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9403 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
a61af66fc99e Initial load
duke
parents:
diff changeset
9404 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9405
a61af66fc99e Initial load
duke
parents:
diff changeset
9406 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9407 rolI_rReg_imm8(dst, lshift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9408 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9409 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9410
a61af66fc99e Initial load
duke
parents:
diff changeset
9411 // Rotate Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9412 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9413 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9414 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
9415
a61af66fc99e Initial load
duke
parents:
diff changeset
9416 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9417 rolI_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9418 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9419 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9420
a61af66fc99e Initial load
duke
parents:
diff changeset
9421 // Rotate Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9422 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9423 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9424 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
9425
a61af66fc99e Initial load
duke
parents:
diff changeset
9426 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9427 rolI_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9428 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9429 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9430
a61af66fc99e Initial load
duke
parents:
diff changeset
9431 // ROR expand
a61af66fc99e Initial load
duke
parents:
diff changeset
9432 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9433 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9434 effect(USE_DEF dst, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9435
a61af66fc99e Initial load
duke
parents:
diff changeset
9436 format %{ "rorl $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9437 opcode(0xD1, 0x1); /* D1 /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9438 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9439 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9440 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9441
a61af66fc99e Initial load
duke
parents:
diff changeset
9442 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9443 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9444 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9445
a61af66fc99e Initial load
duke
parents:
diff changeset
9446 format %{ "rorl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9447 opcode(0xC1, 0x1); /* C1 /1 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
9448 ins_encode(reg_opc_imm(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9449 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9450 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9451
a61af66fc99e Initial load
duke
parents:
diff changeset
9452 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9453 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9454 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9455
a61af66fc99e Initial load
duke
parents:
diff changeset
9456 format %{ "rorl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9457 opcode(0xD3, 0x1); /* D3 /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9458 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9459 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9460 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9461 // end of ROR expand
a61af66fc99e Initial load
duke
parents:
diff changeset
9462
a61af66fc99e Initial load
duke
parents:
diff changeset
9463 // Rotate Right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
9464 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9465 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9466 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9467
a61af66fc99e Initial load
duke
parents:
diff changeset
9468 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9469 rorI_rReg_imm1(dst, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9470 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9471 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9472
a61af66fc99e Initial load
duke
parents:
diff changeset
9473 // Rotate Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9474 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9475 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9476 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
a61af66fc99e Initial load
duke
parents:
diff changeset
9477 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9478
a61af66fc99e Initial load
duke
parents:
diff changeset
9479 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9480 rorI_rReg_imm8(dst, rshift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9481 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9482 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9483
a61af66fc99e Initial load
duke
parents:
diff changeset
9484 // Rotate Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9485 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9486 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9487 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
9488
a61af66fc99e Initial load
duke
parents:
diff changeset
9489 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9490 rorI_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9491 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9492 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9493
a61af66fc99e Initial load
duke
parents:
diff changeset
9494 // Rotate Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9495 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9496 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9497 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
9498
a61af66fc99e Initial load
duke
parents:
diff changeset
9499 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9500 rorI_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9501 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9502 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9503
a61af66fc99e Initial load
duke
parents:
diff changeset
9504 // for long rotate
a61af66fc99e Initial load
duke
parents:
diff changeset
9505 // ROL expand
a61af66fc99e Initial load
duke
parents:
diff changeset
9506 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9507 effect(USE_DEF dst, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9508
a61af66fc99e Initial load
duke
parents:
diff changeset
9509 format %{ "rolq $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9510 opcode(0xD1, 0x0); /* Opcode D1 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9511 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9512 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9513 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9514
a61af66fc99e Initial load
duke
parents:
diff changeset
9515 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9516 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9517
a61af66fc99e Initial load
duke
parents:
diff changeset
9518 format %{ "rolq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9519 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
9520 ins_encode( reg_opc_imm_wide(dst, shift) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9521 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9522 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9523
a61af66fc99e Initial load
duke
parents:
diff changeset
9524 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9525 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9526 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9527
a61af66fc99e Initial load
duke
parents:
diff changeset
9528 format %{ "rolq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9529 opcode(0xD3, 0x0); /* Opcode D3 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9530 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9531 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9532 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9533 // end of ROL expand
a61af66fc99e Initial load
duke
parents:
diff changeset
9534
a61af66fc99e Initial load
duke
parents:
diff changeset
9535 // Rotate Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
9536 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9537 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9538 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9539
a61af66fc99e Initial load
duke
parents:
diff changeset
9540 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9541 rolL_rReg_imm1(dst, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9542 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9543 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9544
a61af66fc99e Initial load
duke
parents:
diff changeset
9545 // Rotate Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9546 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9547 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9548 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
a61af66fc99e Initial load
duke
parents:
diff changeset
9549 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9550
a61af66fc99e Initial load
duke
parents:
diff changeset
9551 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9552 rolL_rReg_imm8(dst, lshift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9553 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9554 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9555
a61af66fc99e Initial load
duke
parents:
diff changeset
9556 // Rotate Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9557 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9558 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9559 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
9560
a61af66fc99e Initial load
duke
parents:
diff changeset
9561 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9562 rolL_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9563 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9564 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9565
a61af66fc99e Initial load
duke
parents:
diff changeset
9566 // Rotate Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9567 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9568 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9569 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
9570
a61af66fc99e Initial load
duke
parents:
diff changeset
9571 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9572 rolL_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9573 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9574 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9575
a61af66fc99e Initial load
duke
parents:
diff changeset
9576 // ROR expand
a61af66fc99e Initial load
duke
parents:
diff changeset
9577 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9578 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9579 effect(USE_DEF dst, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9580
a61af66fc99e Initial load
duke
parents:
diff changeset
9581 format %{ "rorq $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9582 opcode(0xD1, 0x1); /* D1 /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9583 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9584 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9585 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9586
a61af66fc99e Initial load
duke
parents:
diff changeset
9587 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9588 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9589 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9590
a61af66fc99e Initial load
duke
parents:
diff changeset
9591 format %{ "rorq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9592 opcode(0xC1, 0x1); /* C1 /1 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
9593 ins_encode(reg_opc_imm_wide(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
9594 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9595 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9596
a61af66fc99e Initial load
duke
parents:
diff changeset
9597 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9598 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9599 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9600
a61af66fc99e Initial load
duke
parents:
diff changeset
9601 format %{ "rorq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9602 opcode(0xD3, 0x1); /* D3 /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9603 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9604 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9605 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9606 // end of ROR expand
a61af66fc99e Initial load
duke
parents:
diff changeset
9607
a61af66fc99e Initial load
duke
parents:
diff changeset
9608 // Rotate Right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
9609 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9610 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9611 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9612
a61af66fc99e Initial load
duke
parents:
diff changeset
9613 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9614 rorL_rReg_imm1(dst, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9615 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9616 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9617
a61af66fc99e Initial load
duke
parents:
diff changeset
9618 // Rotate Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9619 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9620 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9621 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
a61af66fc99e Initial load
duke
parents:
diff changeset
9622 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9623
a61af66fc99e Initial load
duke
parents:
diff changeset
9624 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9625 rorL_rReg_imm8(dst, rshift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9626 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9627 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9628
a61af66fc99e Initial load
duke
parents:
diff changeset
9629 // Rotate Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9630 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9631 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9632 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
9633
a61af66fc99e Initial load
duke
parents:
diff changeset
9634 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9635 rorL_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9636 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9637 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9638
a61af66fc99e Initial load
duke
parents:
diff changeset
9639 // Rotate Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
9640 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9641 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9642 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
9643
a61af66fc99e Initial load
duke
parents:
diff changeset
9644 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9645 rorL_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9646 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9647 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9648
a61af66fc99e Initial load
duke
parents:
diff changeset
9649 // Logical Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
9650
a61af66fc99e Initial load
duke
parents:
diff changeset
9651 // Integer Logical Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
9652
a61af66fc99e Initial load
duke
parents:
diff changeset
9653 // And Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
9654 // And Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9655 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9656 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9657 match(Set dst (AndI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9658 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9659
a61af66fc99e Initial load
duke
parents:
diff changeset
9660 format %{ "andl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9661 opcode(0x23);
a61af66fc99e Initial load
duke
parents:
diff changeset
9662 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9663 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9664 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9665
a61af66fc99e Initial load
duke
parents:
diff changeset
9666 // And Register with Immediate 255
a61af66fc99e Initial load
duke
parents:
diff changeset
9667 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9668 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9669 match(Set dst (AndI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9670
a61af66fc99e Initial load
duke
parents:
diff changeset
9671 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9672 opcode(0x0F, 0xB6);
a61af66fc99e Initial load
duke
parents:
diff changeset
9673 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9674 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9675 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9676
a61af66fc99e Initial load
duke
parents:
diff changeset
9677 // And Register with Immediate 255 and promote to long
a61af66fc99e Initial load
duke
parents:
diff changeset
9678 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
a61af66fc99e Initial load
duke
parents:
diff changeset
9679 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9680 match(Set dst (ConvI2L (AndI src mask)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9681
a61af66fc99e Initial load
duke
parents:
diff changeset
9682 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9683 opcode(0x0F, 0xB6);
a61af66fc99e Initial load
duke
parents:
diff changeset
9684 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9685 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9686 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9687
a61af66fc99e Initial load
duke
parents:
diff changeset
9688 // And Register with Immediate 65535
a61af66fc99e Initial load
duke
parents:
diff changeset
9689 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9690 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9691 match(Set dst (AndI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9692
a61af66fc99e Initial load
duke
parents:
diff changeset
9693 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9694 opcode(0x0F, 0xB7);
a61af66fc99e Initial load
duke
parents:
diff changeset
9695 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9696 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9697 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9698
a61af66fc99e Initial load
duke
parents:
diff changeset
9699 // And Register with Immediate 65535 and promote to long
a61af66fc99e Initial load
duke
parents:
diff changeset
9700 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
a61af66fc99e Initial load
duke
parents:
diff changeset
9701 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9702 match(Set dst (ConvI2L (AndI src mask)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9703
a61af66fc99e Initial load
duke
parents:
diff changeset
9704 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9705 opcode(0x0F, 0xB7);
a61af66fc99e Initial load
duke
parents:
diff changeset
9706 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9707 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9708 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9709
a61af66fc99e Initial load
duke
parents:
diff changeset
9710 // And Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9711 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9712 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9713 match(Set dst (AndI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9714 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9715
a61af66fc99e Initial load
duke
parents:
diff changeset
9716 format %{ "andl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9717 opcode(0x81, 0x04); /* Opcode 81 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9718 ins_encode(OpcSErm(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9719 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9720 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9721
a61af66fc99e Initial load
duke
parents:
diff changeset
9722 // And Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
9723 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9724 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9725 match(Set dst (AndI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9726 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9727
a61af66fc99e Initial load
duke
parents:
diff changeset
9728 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9729 format %{ "andl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9730 opcode(0x23);
a61af66fc99e Initial load
duke
parents:
diff changeset
9731 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9732 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
9733 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9734
a61af66fc99e Initial load
duke
parents:
diff changeset
9735 // And Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9736 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9737 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9738 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9739 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9740
a61af66fc99e Initial load
duke
parents:
diff changeset
9741 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
9742 format %{ "andl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9743 opcode(0x21); /* Opcode 21 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
9744 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9745 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9746 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9747
a61af66fc99e Initial load
duke
parents:
diff changeset
9748 // And Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9749 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9750 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9751 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9752 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9753
a61af66fc99e Initial load
duke
parents:
diff changeset
9754 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9755 format %{ "andl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9756 opcode(0x81, 0x4); /* Opcode 81 /4 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
9757 ins_encode(REX_mem(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
9758 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9759 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9760 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9761
a61af66fc99e Initial load
duke
parents:
diff changeset
9762 // Or Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
9763 // Or Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9764 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9765 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9766 match(Set dst (OrI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9767 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9768
a61af66fc99e Initial load
duke
parents:
diff changeset
9769 format %{ "orl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9770 opcode(0x0B);
a61af66fc99e Initial load
duke
parents:
diff changeset
9771 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9772 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9773 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9774
a61af66fc99e Initial load
duke
parents:
diff changeset
9775 // Or Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9776 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9777 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9778 match(Set dst (OrI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9779 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9780
a61af66fc99e Initial load
duke
parents:
diff changeset
9781 format %{ "orl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9782 opcode(0x81, 0x01); /* Opcode 81 /1 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
9783 ins_encode(OpcSErm(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9784 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9785 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9786
a61af66fc99e Initial load
duke
parents:
diff changeset
9787 // Or Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
9788 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9789 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9790 match(Set dst (OrI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9791 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9792
a61af66fc99e Initial load
duke
parents:
diff changeset
9793 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9794 format %{ "orl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9795 opcode(0x0B);
a61af66fc99e Initial load
duke
parents:
diff changeset
9796 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9797 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
9798 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9799
a61af66fc99e Initial load
duke
parents:
diff changeset
9800 // Or Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9801 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9802 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9803 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9804 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9805
a61af66fc99e Initial load
duke
parents:
diff changeset
9806 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
9807 format %{ "orl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9808 opcode(0x09); /* Opcode 09 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
9809 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9810 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9811 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9812
a61af66fc99e Initial load
duke
parents:
diff changeset
9813 // Or Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9814 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9815 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9816 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9817 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9818
a61af66fc99e Initial load
duke
parents:
diff changeset
9819 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9820 format %{ "orl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9821 opcode(0x81, 0x1); /* Opcode 81 /1 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
9822 ins_encode(REX_mem(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
9823 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9824 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9825 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9826
a61af66fc99e Initial load
duke
parents:
diff changeset
9827 // Xor Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
9828 // Xor Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9829 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9830 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9831 match(Set dst (XorI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9832 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9833
a61af66fc99e Initial load
duke
parents:
diff changeset
9834 format %{ "xorl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9835 opcode(0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
9836 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9837 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9838 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9839
403
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9840 // Xor Register with Immediate -1
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9841 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
9842 match(Set dst (XorI dst imm));
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
9843
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
9844 format %{ "not $dst" %}
403
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9845 ins_encode %{
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9846 __ notl($dst$$Register);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9847 %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9848 ins_pipe(ialu_reg);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9849 %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9850
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9851 // Xor Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9852 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9853 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9854 match(Set dst (XorI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9855 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9856
a61af66fc99e Initial load
duke
parents:
diff changeset
9857 format %{ "xorl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9858 opcode(0x81, 0x06); /* Opcode 81 /6 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
9859 ins_encode(OpcSErm(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9860 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9861 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9862
a61af66fc99e Initial load
duke
parents:
diff changeset
9863 // Xor Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
9864 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9865 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9866 match(Set dst (XorI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9867 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9868
a61af66fc99e Initial load
duke
parents:
diff changeset
9869 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9870 format %{ "xorl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9871 opcode(0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
9872 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9873 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
9874 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9875
a61af66fc99e Initial load
duke
parents:
diff changeset
9876 // Xor Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9877 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9878 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9879 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9880 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9881
a61af66fc99e Initial load
duke
parents:
diff changeset
9882 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
9883 format %{ "xorl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9884 opcode(0x31); /* Opcode 31 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
9885 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9886 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9887 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9888
a61af66fc99e Initial load
duke
parents:
diff changeset
9889 // Xor Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9890 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9891 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9892 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9893 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9894
a61af66fc99e Initial load
duke
parents:
diff changeset
9895 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9896 format %{ "xorl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9897 opcode(0x81, 0x6); /* Opcode 81 /6 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
9898 ins_encode(REX_mem(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
9899 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9900 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9901 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9902
a61af66fc99e Initial load
duke
parents:
diff changeset
9903
a61af66fc99e Initial load
duke
parents:
diff changeset
9904 // Long Logical Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
9905
a61af66fc99e Initial load
duke
parents:
diff changeset
9906 // And Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
9907 // And Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9908 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9909 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9910 match(Set dst (AndL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9911 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9912
a61af66fc99e Initial load
duke
parents:
diff changeset
9913 format %{ "andq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9914 opcode(0x23);
a61af66fc99e Initial load
duke
parents:
diff changeset
9915 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9916 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9917 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9918
a61af66fc99e Initial load
duke
parents:
diff changeset
9919 // And Register with Immediate 255
a61af66fc99e Initial load
duke
parents:
diff changeset
9920 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9921 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9922 match(Set dst (AndL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9923
569
2cacccded90f 6805950: Typos in andL_rReg_imm instructions in x86_64.ad
twisti
parents: 558
diff changeset
9924 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9925 opcode(0x0F, 0xB6);
a61af66fc99e Initial load
duke
parents:
diff changeset
9926 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9927 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9928 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9929
a61af66fc99e Initial load
duke
parents:
diff changeset
9930 // And Register with Immediate 65535
569
2cacccded90f 6805950: Typos in andL_rReg_imm instructions in x86_64.ad
twisti
parents: 558
diff changeset
9931 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9932 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9933 match(Set dst (AndL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9934
a61af66fc99e Initial load
duke
parents:
diff changeset
9935 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9936 opcode(0x0F, 0xB7);
a61af66fc99e Initial load
duke
parents:
diff changeset
9937 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9938 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9939 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9940
a61af66fc99e Initial load
duke
parents:
diff changeset
9941 // And Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9942 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9943 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9944 match(Set dst (AndL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9945 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9946
a61af66fc99e Initial load
duke
parents:
diff changeset
9947 format %{ "andq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9948 opcode(0x81, 0x04); /* Opcode 81 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9949 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9950 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9951 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9952
a61af66fc99e Initial load
duke
parents:
diff changeset
9953 // And Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
9954 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9955 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9956 match(Set dst (AndL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9957 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9958
a61af66fc99e Initial load
duke
parents:
diff changeset
9959 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9960 format %{ "andq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9961 opcode(0x23);
a61af66fc99e Initial load
duke
parents:
diff changeset
9962 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9963 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
9964 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9965
a61af66fc99e Initial load
duke
parents:
diff changeset
9966 // And Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9967 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9968 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9969 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9970 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9971
a61af66fc99e Initial load
duke
parents:
diff changeset
9972 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
9973 format %{ "andq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9974 opcode(0x21); /* Opcode 21 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
9975 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9976 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9977 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9978
a61af66fc99e Initial load
duke
parents:
diff changeset
9979 // And Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9980 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9981 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9982 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9983 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9984
a61af66fc99e Initial load
duke
parents:
diff changeset
9985 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9986 format %{ "andq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9987 opcode(0x81, 0x4); /* Opcode 81 /4 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
9988 ins_encode(REX_mem_wide(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
9989 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9990 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9991 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9992
a61af66fc99e Initial load
duke
parents:
diff changeset
9993 // Or Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
9994 // Or Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9995 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9996 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9997 match(Set dst (OrL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9998 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9999
a61af66fc99e Initial load
duke
parents:
diff changeset
10000 format %{ "orq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10001 opcode(0x0B);
a61af66fc99e Initial load
duke
parents:
diff changeset
10002 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10003 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10004 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10005
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
10006 // Use any_RegP to match R15 (TLS register) without spilling.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
10007 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
10008 match(Set dst (OrL dst (CastP2X src)));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
10009 effect(KILL cr);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
10010
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
10011 format %{ "orq $dst, $src\t# long" %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
10012 opcode(0x0B);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
10013 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
10014 ins_pipe(ialu_reg_reg);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
10015 %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
10016
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
10017
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10018 // Or Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
10019 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10020 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10021 match(Set dst (OrL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10022 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10023
a61af66fc99e Initial load
duke
parents:
diff changeset
10024 format %{ "orq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10025 opcode(0x81, 0x01); /* Opcode 81 /1 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
10026 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10027 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10028 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10029
a61af66fc99e Initial load
duke
parents:
diff changeset
10030 // Or Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
10031 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10032 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10033 match(Set dst (OrL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10034 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10035
a61af66fc99e Initial load
duke
parents:
diff changeset
10036 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
10037 format %{ "orq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10038 opcode(0x0B);
a61af66fc99e Initial load
duke
parents:
diff changeset
10039 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10040 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10041 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10042
a61af66fc99e Initial load
duke
parents:
diff changeset
10043 // Or Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
10044 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10045 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10046 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10047 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10048
a61af66fc99e Initial load
duke
parents:
diff changeset
10049 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
10050 format %{ "orq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10051 opcode(0x09); /* Opcode 09 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10052 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10053 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10054 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10055
a61af66fc99e Initial load
duke
parents:
diff changeset
10056 // Or Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
10057 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10058 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10059 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10060 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10061
a61af66fc99e Initial load
duke
parents:
diff changeset
10062 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
10063 format %{ "orq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10064 opcode(0x81, 0x1); /* Opcode 81 /1 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
10065 ins_encode(REX_mem_wide(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
10066 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10067 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10068 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10069
a61af66fc99e Initial load
duke
parents:
diff changeset
10070 // Xor Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
10071 // Xor Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
10072 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10073 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10074 match(Set dst (XorL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10075 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10076
a61af66fc99e Initial load
duke
parents:
diff changeset
10077 format %{ "xorq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10078 opcode(0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
10079 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10080 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10081 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10082
403
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
10083 // Xor Register with Immediate -1
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
10084 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
10085 match(Set dst (XorL dst imm));
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
10086
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
10087 format %{ "notq $dst" %}
403
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
10088 ins_encode %{
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
10089 __ notq($dst$$Register);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
10090 %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
10091 ins_pipe(ialu_reg);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
10092 %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
10093
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10094 // Xor Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
10095 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10096 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10097 match(Set dst (XorL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10098 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10099
a61af66fc99e Initial load
duke
parents:
diff changeset
10100 format %{ "xorq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10101 opcode(0x81, 0x06); /* Opcode 81 /6 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
10102 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10103 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10104 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10105
a61af66fc99e Initial load
duke
parents:
diff changeset
10106 // Xor Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
10107 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10108 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10109 match(Set dst (XorL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10110 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10111
a61af66fc99e Initial load
duke
parents:
diff changeset
10112 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
10113 format %{ "xorq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10114 opcode(0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
10115 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10116 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10117 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10118
a61af66fc99e Initial load
duke
parents:
diff changeset
10119 // Xor Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
10120 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10121 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10122 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10123 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10124
a61af66fc99e Initial load
duke
parents:
diff changeset
10125 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
10126 format %{ "xorq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10127 opcode(0x31); /* Opcode 31 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10128 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10129 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10130 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10131
a61af66fc99e Initial load
duke
parents:
diff changeset
10132 // Xor Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
10133 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10134 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10135 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10136 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10137
a61af66fc99e Initial load
duke
parents:
diff changeset
10138 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
10139 format %{ "xorq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10140 opcode(0x81, 0x6); /* Opcode 81 /6 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
10141 ins_encode(REX_mem_wide(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
10142 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10143 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10144 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10145
a61af66fc99e Initial load
duke
parents:
diff changeset
10146 // Convert Int to Boolean
a61af66fc99e Initial load
duke
parents:
diff changeset
10147 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10148 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10149 match(Set dst (Conv2B src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10150 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10151
a61af66fc99e Initial load
duke
parents:
diff changeset
10152 format %{ "testl $src, $src\t# ci2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10153 "setnz $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10154 "movzbl $dst, $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10155 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
a61af66fc99e Initial load
duke
parents:
diff changeset
10156 setNZ_reg(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
10157 REX_reg_breg(dst, dst), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
10158 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10159 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10160 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10161
a61af66fc99e Initial load
duke
parents:
diff changeset
10162 // Convert Pointer to Boolean
a61af66fc99e Initial load
duke
parents:
diff changeset
10163 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10164 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10165 match(Set dst (Conv2B src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10166 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10167
a61af66fc99e Initial load
duke
parents:
diff changeset
10168 format %{ "testq $src, $src\t# cp2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10169 "setnz $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10170 "movzbl $dst, $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10171 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
a61af66fc99e Initial load
duke
parents:
diff changeset
10172 setNZ_reg(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
10173 REX_reg_breg(dst, dst), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
10174 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10175 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10176 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10177
a61af66fc99e Initial load
duke
parents:
diff changeset
10178 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10179 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10180 match(Set dst (CmpLTMask p q));
a61af66fc99e Initial load
duke
parents:
diff changeset
10181 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10182
a61af66fc99e Initial load
duke
parents:
diff changeset
10183 ins_cost(400); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10184 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10185 "setlt $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10186 "movzbl $dst, $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10187 "negl $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10188 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
a61af66fc99e Initial load
duke
parents:
diff changeset
10189 setLT_reg(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
10190 REX_reg_breg(dst, dst), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
10191 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
10192 neg_reg(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10193 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10194 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10195
a61af66fc99e Initial load
duke
parents:
diff changeset
10196 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10197 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10198 match(Set dst (CmpLTMask dst zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10199 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10200
a61af66fc99e Initial load
duke
parents:
diff changeset
10201 ins_cost(100); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10202 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10203 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
10204 ins_encode(reg_opc_imm(dst, 0x1F));
a61af66fc99e Initial load
duke
parents:
diff changeset
10205 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10206 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10207
a61af66fc99e Initial load
duke
parents:
diff changeset
10208
a61af66fc99e Initial load
duke
parents:
diff changeset
10209 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y,
a61af66fc99e Initial load
duke
parents:
diff changeset
10210 rRegI tmp,
a61af66fc99e Initial load
duke
parents:
diff changeset
10211 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10212 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10213 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10214 effect(TEMP tmp, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10215
a61af66fc99e Initial load
duke
parents:
diff changeset
10216 ins_cost(400); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10217 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10218 "sbbl $tmp, $tmp\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10219 "andl $tmp, $y\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10220 "addl $p, $tmp" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10221 ins_encode(enc_cmpLTP(p, q, y, tmp));
a61af66fc99e Initial load
duke
parents:
diff changeset
10222 ins_pipe(pipe_cmplt);
a61af66fc99e Initial load
duke
parents:
diff changeset
10223 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10224
a61af66fc99e Initial load
duke
parents:
diff changeset
10225 /* If I enable this, I encourage spilling in the inner loop of compress.
a61af66fc99e Initial load
duke
parents:
diff changeset
10226 instruct cadd_cmpLTMask_mem( rRegI p, rRegI q, memory y, rRegI tmp, rFlagsReg cr )
a61af66fc99e Initial load
duke
parents:
diff changeset
10227 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10228 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10229 effect( TEMP tmp, KILL cr );
a61af66fc99e Initial load
duke
parents:
diff changeset
10230 ins_cost(400);
a61af66fc99e Initial load
duke
parents:
diff changeset
10231
a61af66fc99e Initial load
duke
parents:
diff changeset
10232 format %{ "SUB $p,$q\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10233 "SBB RCX,RCX\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10234 "AND RCX,$y\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10235 "ADD $p,RCX" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10236 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
a61af66fc99e Initial load
duke
parents:
diff changeset
10237 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10238 */
a61af66fc99e Initial load
duke
parents:
diff changeset
10239
a61af66fc99e Initial load
duke
parents:
diff changeset
10240 //---------- FP Instructions------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
10241
a61af66fc99e Initial load
duke
parents:
diff changeset
10242 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10243 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10244 match(Set cr (CmpF src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10245
a61af66fc99e Initial load
duke
parents:
diff changeset
10246 ins_cost(145);
a61af66fc99e Initial load
duke
parents:
diff changeset
10247 format %{ "ucomiss $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10248 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10249 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10250 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10251 "popfq\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
10252 "exit: nop\t# avoid branch to branch" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10253 opcode(0x0F, 0x2E);
a61af66fc99e Initial load
duke
parents:
diff changeset
10254 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2),
a61af66fc99e Initial load
duke
parents:
diff changeset
10255 cmpfp_fixup);
a61af66fc99e Initial load
duke
parents:
diff changeset
10256 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10257 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10258
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10259 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10260 match(Set cr (CmpF src1 src2));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10261
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10262 ins_cost(145);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10263 format %{ "ucomiss $src1, $src2" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10264 ins_encode %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10265 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10266 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10267 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10268 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10269
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10270 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10271 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10272 match(Set cr (CmpF src1 (LoadF src2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10273
a61af66fc99e Initial load
duke
parents:
diff changeset
10274 ins_cost(145);
a61af66fc99e Initial load
duke
parents:
diff changeset
10275 format %{ "ucomiss $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10276 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10277 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10278 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10279 "popfq\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
10280 "exit: nop\t# avoid branch to branch" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10281 opcode(0x0F, 0x2E);
a61af66fc99e Initial load
duke
parents:
diff changeset
10282 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2),
a61af66fc99e Initial load
duke
parents:
diff changeset
10283 cmpfp_fixup);
a61af66fc99e Initial load
duke
parents:
diff changeset
10284 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10285 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10286
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10287 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10288 match(Set cr (CmpF src1 (LoadF src2)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10289
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10290 ins_cost(100);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10291 format %{ "ucomiss $src1, $src2" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10292 opcode(0x0F, 0x2E);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10293 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10294 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10295 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10296
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10297 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10298 match(Set cr (CmpF src con));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10299
a61af66fc99e Initial load
duke
parents:
diff changeset
10300 ins_cost(145);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10301 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10302 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10303 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10304 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10305 "popfq\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
10306 "exit: nop\t# avoid branch to branch" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10307 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10308 Label L_exit;
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10309 __ ucomiss($src$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10310 __ jcc(Assembler::noParity, L_exit);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10311 __ pushf();
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10312 __ andq(rsp, 0xffffff2b);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10313 __ popf();
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10314 __ bind(L_exit);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10315 __ nop();
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10316 %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10317 ins_pipe(pipe_slow);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10318 %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10319
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10320 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10321 match(Set cr (CmpF src con));
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10322 ins_cost(100);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10323 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10324 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10325 __ ucomiss($src$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10326 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10327 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10328 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10329
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10330 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10331 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10332 match(Set cr (CmpD src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10333
a61af66fc99e Initial load
duke
parents:
diff changeset
10334 ins_cost(145);
a61af66fc99e Initial load
duke
parents:
diff changeset
10335 format %{ "ucomisd $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10336 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10337 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10338 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10339 "popfq\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
10340 "exit: nop\t# avoid branch to branch" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10341 opcode(0x66, 0x0F, 0x2E);
a61af66fc99e Initial load
duke
parents:
diff changeset
10342 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2),
a61af66fc99e Initial load
duke
parents:
diff changeset
10343 cmpfp_fixup);
a61af66fc99e Initial load
duke
parents:
diff changeset
10344 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10345 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10346
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10347 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10348 match(Set cr (CmpD src1 src2));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10349
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10350 ins_cost(100);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10351 format %{ "ucomisd $src1, $src2 test" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10352 ins_encode %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10353 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10354 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10355 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10356 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10357
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10358 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10359 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10360 match(Set cr (CmpD src1 (LoadD src2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10361
a61af66fc99e Initial load
duke
parents:
diff changeset
10362 ins_cost(145);
a61af66fc99e Initial load
duke
parents:
diff changeset
10363 format %{ "ucomisd $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10364 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10365 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10366 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10367 "popfq\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
10368 "exit: nop\t# avoid branch to branch" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10369 opcode(0x66, 0x0F, 0x2E);
a61af66fc99e Initial load
duke
parents:
diff changeset
10370 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2),
a61af66fc99e Initial load
duke
parents:
diff changeset
10371 cmpfp_fixup);
a61af66fc99e Initial load
duke
parents:
diff changeset
10372 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10373 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10374
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10375 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10376 match(Set cr (CmpD src1 (LoadD src2)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10377
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10378 ins_cost(100);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10379 format %{ "ucomisd $src1, $src2" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10380 opcode(0x66, 0x0F, 0x2E);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10381 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10382 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10383 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10384
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10385 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10386 match(Set cr (CmpD src con));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10387
a61af66fc99e Initial load
duke
parents:
diff changeset
10388 ins_cost(145);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10389 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10390 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10391 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10392 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10393 "popfq\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
10394 "exit: nop\t# avoid branch to branch" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10395 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10396 Label L_exit;
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10397 __ ucomisd($src$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10398 __ jcc(Assembler::noParity, L_exit);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10399 __ pushf();
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10400 __ andq(rsp, 0xffffff2b);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10401 __ popf();
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10402 __ bind(L_exit);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10403 __ nop();
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10404 %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10405 ins_pipe(pipe_slow);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10406 %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10407
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10408 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10409 match(Set cr (CmpD src con));
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10410 ins_cost(100);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10411 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10412 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10413 __ ucomisd($src$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10414 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10415 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10416 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10417
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10418 // Compare into -1,0,1
a61af66fc99e Initial load
duke
parents:
diff changeset
10419 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10420 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10421 match(Set dst (CmpF3 src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10422 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10423
a61af66fc99e Initial load
duke
parents:
diff changeset
10424 ins_cost(275);
a61af66fc99e Initial load
duke
parents:
diff changeset
10425 format %{ "ucomiss $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10426 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10427 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10428 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10429 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10430 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
10431 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10432
a61af66fc99e Initial load
duke
parents:
diff changeset
10433 opcode(0x0F, 0x2E);
a61af66fc99e Initial load
duke
parents:
diff changeset
10434 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2),
a61af66fc99e Initial load
duke
parents:
diff changeset
10435 cmpfp3(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10436 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10437 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10438
a61af66fc99e Initial load
duke
parents:
diff changeset
10439 // Compare into -1,0,1
a61af66fc99e Initial load
duke
parents:
diff changeset
10440 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10441 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10442 match(Set dst (CmpF3 src1 (LoadF src2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10443 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10444
a61af66fc99e Initial load
duke
parents:
diff changeset
10445 ins_cost(275);
a61af66fc99e Initial load
duke
parents:
diff changeset
10446 format %{ "ucomiss $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10447 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10448 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10449 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10450 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10451 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
10452 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10453
a61af66fc99e Initial load
duke
parents:
diff changeset
10454 opcode(0x0F, 0x2E);
a61af66fc99e Initial load
duke
parents:
diff changeset
10455 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2),
a61af66fc99e Initial load
duke
parents:
diff changeset
10456 cmpfp3(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10457 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10458 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10459
a61af66fc99e Initial load
duke
parents:
diff changeset
10460 // Compare into -1,0,1
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10461 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10462 match(Set dst (CmpF3 src con));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10463 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10464
a61af66fc99e Initial load
duke
parents:
diff changeset
10465 ins_cost(275);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10466 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10467 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10468 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10469 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10470 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10471 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
10472 "done:" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10473 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10474 Label L_done;
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10475 Register Rdst = $dst$$Register;
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10476 __ ucomiss($src$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10477 __ movl(Rdst, -1);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10478 __ jcc(Assembler::parity, L_done);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10479 __ jcc(Assembler::below, L_done);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10480 __ setb(Assembler::notEqual, Rdst);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10481 __ movzbl(Rdst, Rdst);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10482 __ bind(L_done);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10483 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10484 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10485 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10486
a61af66fc99e Initial load
duke
parents:
diff changeset
10487 // Compare into -1,0,1
a61af66fc99e Initial load
duke
parents:
diff changeset
10488 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10489 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10490 match(Set dst (CmpD3 src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10491 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10492
a61af66fc99e Initial load
duke
parents:
diff changeset
10493 ins_cost(275);
a61af66fc99e Initial load
duke
parents:
diff changeset
10494 format %{ "ucomisd $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10495 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10496 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10497 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10498 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10499 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
10500 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10501
a61af66fc99e Initial load
duke
parents:
diff changeset
10502 opcode(0x66, 0x0F, 0x2E);
a61af66fc99e Initial load
duke
parents:
diff changeset
10503 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2),
a61af66fc99e Initial load
duke
parents:
diff changeset
10504 cmpfp3(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10505 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10506 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10507
a61af66fc99e Initial load
duke
parents:
diff changeset
10508 // Compare into -1,0,1
a61af66fc99e Initial load
duke
parents:
diff changeset
10509 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10510 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10511 match(Set dst (CmpD3 src1 (LoadD src2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10512 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10513
a61af66fc99e Initial load
duke
parents:
diff changeset
10514 ins_cost(275);
a61af66fc99e Initial load
duke
parents:
diff changeset
10515 format %{ "ucomisd $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10516 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10517 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10518 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10519 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10520 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
10521 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10522
a61af66fc99e Initial load
duke
parents:
diff changeset
10523 opcode(0x66, 0x0F, 0x2E);
a61af66fc99e Initial load
duke
parents:
diff changeset
10524 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2),
a61af66fc99e Initial load
duke
parents:
diff changeset
10525 cmpfp3(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10526 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10527 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10528
a61af66fc99e Initial load
duke
parents:
diff changeset
10529 // Compare into -1,0,1
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10530 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10531 match(Set dst (CmpD3 src con));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10532 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10533
a61af66fc99e Initial load
duke
parents:
diff changeset
10534 ins_cost(275);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10535 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10536 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10537 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10538 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10539 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10540 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
10541 "done:" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10542 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10543 Register Rdst = $dst$$Register;
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10544 Label L_done;
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10545 __ ucomisd($src$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10546 __ movl(Rdst, -1);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10547 __ jcc(Assembler::parity, L_done);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10548 __ jcc(Assembler::below, L_done);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10549 __ setb(Assembler::notEqual, Rdst);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10550 __ movzbl(Rdst, Rdst);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10551 __ bind(L_done);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10552 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10553 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10554 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10555
a61af66fc99e Initial load
duke
parents:
diff changeset
10556 instruct addF_reg(regF dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10557 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10558 match(Set dst (AddF dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10559
a61af66fc99e Initial load
duke
parents:
diff changeset
10560 format %{ "addss $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10561 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10562 opcode(0xF3, 0x0F, 0x58);
a61af66fc99e Initial load
duke
parents:
diff changeset
10563 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10564 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10565 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10566
a61af66fc99e Initial load
duke
parents:
diff changeset
10567 instruct addF_mem(regF dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10568 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10569 match(Set dst (AddF dst (LoadF src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10570
a61af66fc99e Initial load
duke
parents:
diff changeset
10571 format %{ "addss $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10572 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10573 opcode(0xF3, 0x0F, 0x58);
a61af66fc99e Initial load
duke
parents:
diff changeset
10574 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10575 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10576 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10577
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10578 instruct addF_imm(regF dst, immF con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10579 match(Set dst (AddF dst con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10580 format %{ "addss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10581 ins_cost(150); // XXX
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10582 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10583 __ addss($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10584 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10585 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10586 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10587
a61af66fc99e Initial load
duke
parents:
diff changeset
10588 instruct addD_reg(regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10589 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10590 match(Set dst (AddD dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10591
a61af66fc99e Initial load
duke
parents:
diff changeset
10592 format %{ "addsd $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10593 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10594 opcode(0xF2, 0x0F, 0x58);
a61af66fc99e Initial load
duke
parents:
diff changeset
10595 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10596 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10597 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10598
a61af66fc99e Initial load
duke
parents:
diff changeset
10599 instruct addD_mem(regD dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10600 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10601 match(Set dst (AddD dst (LoadD src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10602
a61af66fc99e Initial load
duke
parents:
diff changeset
10603 format %{ "addsd $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10604 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10605 opcode(0xF2, 0x0F, 0x58);
a61af66fc99e Initial load
duke
parents:
diff changeset
10606 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10607 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10608 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10609
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10610 instruct addD_imm(regD dst, immD con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10611 match(Set dst (AddD dst con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10612 format %{ "addsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10613 ins_cost(150); // XXX
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10614 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10615 __ addsd($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10616 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10617 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10618 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10619
a61af66fc99e Initial load
duke
parents:
diff changeset
10620 instruct subF_reg(regF dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10621 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10622 match(Set dst (SubF dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10623
a61af66fc99e Initial load
duke
parents:
diff changeset
10624 format %{ "subss $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10625 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10626 opcode(0xF3, 0x0F, 0x5C);
a61af66fc99e Initial load
duke
parents:
diff changeset
10627 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10628 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10629 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10630
a61af66fc99e Initial load
duke
parents:
diff changeset
10631 instruct subF_mem(regF dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10632 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10633 match(Set dst (SubF dst (LoadF src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10634
a61af66fc99e Initial load
duke
parents:
diff changeset
10635 format %{ "subss $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10636 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10637 opcode(0xF3, 0x0F, 0x5C);
a61af66fc99e Initial load
duke
parents:
diff changeset
10638 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10639 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10640 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10641
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10642 instruct subF_imm(regF dst, immF con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10643 match(Set dst (SubF dst con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10644 format %{ "subss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10645 ins_cost(150); // XXX
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10646 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10647 __ subss($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10648 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10649 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10650 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10651
a61af66fc99e Initial load
duke
parents:
diff changeset
10652 instruct subD_reg(regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10653 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10654 match(Set dst (SubD dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10655
a61af66fc99e Initial load
duke
parents:
diff changeset
10656 format %{ "subsd $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10657 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10658 opcode(0xF2, 0x0F, 0x5C);
a61af66fc99e Initial load
duke
parents:
diff changeset
10659 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10660 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10661 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10662
a61af66fc99e Initial load
duke
parents:
diff changeset
10663 instruct subD_mem(regD dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10664 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10665 match(Set dst (SubD dst (LoadD src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10666
a61af66fc99e Initial load
duke
parents:
diff changeset
10667 format %{ "subsd $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10668 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10669 opcode(0xF2, 0x0F, 0x5C);
a61af66fc99e Initial load
duke
parents:
diff changeset
10670 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10671 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10672 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10673
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10674 instruct subD_imm(regD dst, immD con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10675 match(Set dst (SubD dst con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10676 format %{ "subsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10677 ins_cost(150); // XXX
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10678 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10679 __ subsd($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10680 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10681 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10682 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10683
a61af66fc99e Initial load
duke
parents:
diff changeset
10684 instruct mulF_reg(regF dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10685 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10686 match(Set dst (MulF dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10687
a61af66fc99e Initial load
duke
parents:
diff changeset
10688 format %{ "mulss $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10689 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10690 opcode(0xF3, 0x0F, 0x59);
a61af66fc99e Initial load
duke
parents:
diff changeset
10691 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10692 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10693 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10694
a61af66fc99e Initial load
duke
parents:
diff changeset
10695 instruct mulF_mem(regF dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10696 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10697 match(Set dst (MulF dst (LoadF src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10698
a61af66fc99e Initial load
duke
parents:
diff changeset
10699 format %{ "mulss $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10700 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10701 opcode(0xF3, 0x0F, 0x59);
a61af66fc99e Initial load
duke
parents:
diff changeset
10702 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10703 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10704 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10705
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10706 instruct mulF_imm(regF dst, immF con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10707 match(Set dst (MulF dst con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10708 format %{ "mulss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10709 ins_cost(150); // XXX
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10710 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10711 __ mulss($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10712 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10713 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10714 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10715
a61af66fc99e Initial load
duke
parents:
diff changeset
10716 instruct mulD_reg(regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10717 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10718 match(Set dst (MulD dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10719
a61af66fc99e Initial load
duke
parents:
diff changeset
10720 format %{ "mulsd $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10721 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10722 opcode(0xF2, 0x0F, 0x59);
a61af66fc99e Initial load
duke
parents:
diff changeset
10723 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10724 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10725 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10726
a61af66fc99e Initial load
duke
parents:
diff changeset
10727 instruct mulD_mem(regD dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10728 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10729 match(Set dst (MulD dst (LoadD src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10730
a61af66fc99e Initial load
duke
parents:
diff changeset
10731 format %{ "mulsd $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10732 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10733 opcode(0xF2, 0x0F, 0x59);
a61af66fc99e Initial load
duke
parents:
diff changeset
10734 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10735 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10736 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10737
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10738 instruct mulD_imm(regD dst, immD con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10739 match(Set dst (MulD dst con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10740 format %{ "mulsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10741 ins_cost(150); // XXX
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10742 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10743 __ mulsd($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10744 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10745 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10746 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10747
a61af66fc99e Initial load
duke
parents:
diff changeset
10748 instruct divF_reg(regF dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10749 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10750 match(Set dst (DivF dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10751
a61af66fc99e Initial load
duke
parents:
diff changeset
10752 format %{ "divss $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10753 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10754 opcode(0xF3, 0x0F, 0x5E);
a61af66fc99e Initial load
duke
parents:
diff changeset
10755 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10756 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10757 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10758
a61af66fc99e Initial load
duke
parents:
diff changeset
10759 instruct divF_mem(regF dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10760 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10761 match(Set dst (DivF dst (LoadF src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10762
a61af66fc99e Initial load
duke
parents:
diff changeset
10763 format %{ "divss $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10764 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10765 opcode(0xF3, 0x0F, 0x5E);
a61af66fc99e Initial load
duke
parents:
diff changeset
10766 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10767 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10768 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10769
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10770 instruct divF_imm(regF dst, immF con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10771 match(Set dst (DivF dst con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10772 format %{ "divss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10773 ins_cost(150); // XXX
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10774 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10775 __ divss($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10776 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10777 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10778 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10779
a61af66fc99e Initial load
duke
parents:
diff changeset
10780 instruct divD_reg(regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10781 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10782 match(Set dst (DivD dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10783
a61af66fc99e Initial load
duke
parents:
diff changeset
10784 format %{ "divsd $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10785 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10786 opcode(0xF2, 0x0F, 0x5E);
a61af66fc99e Initial load
duke
parents:
diff changeset
10787 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10788 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10789 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10790
a61af66fc99e Initial load
duke
parents:
diff changeset
10791 instruct divD_mem(regD dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10792 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10793 match(Set dst (DivD dst (LoadD src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10794
a61af66fc99e Initial load
duke
parents:
diff changeset
10795 format %{ "divsd $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10796 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10797 opcode(0xF2, 0x0F, 0x5E);
a61af66fc99e Initial load
duke
parents:
diff changeset
10798 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10799 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10800 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10801
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10802 instruct divD_imm(regD dst, immD con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10803 match(Set dst (DivD dst con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10804 format %{ "divsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10805 ins_cost(150); // XXX
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10806 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10807 __ divsd($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10808 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10809 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10810 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10811
a61af66fc99e Initial load
duke
parents:
diff changeset
10812 instruct sqrtF_reg(regF dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10813 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10814 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
10815
a61af66fc99e Initial load
duke
parents:
diff changeset
10816 format %{ "sqrtss $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10817 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10818 opcode(0xF3, 0x0F, 0x51);
a61af66fc99e Initial load
duke
parents:
diff changeset
10819 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10820 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10821 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10822
a61af66fc99e Initial load
duke
parents:
diff changeset
10823 instruct sqrtF_mem(regF dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10824 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10825 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src)))));
a61af66fc99e Initial load
duke
parents:
diff changeset
10826
a61af66fc99e Initial load
duke
parents:
diff changeset
10827 format %{ "sqrtss $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10828 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10829 opcode(0xF3, 0x0F, 0x51);
a61af66fc99e Initial load
duke
parents:
diff changeset
10830 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10831 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10832 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10833
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10834 instruct sqrtF_imm(regF dst, immF con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10835 match(Set dst (ConvD2F (SqrtD (ConvF2D con))));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10836 format %{ "sqrtss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10837 ins_cost(150); // XXX
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10838 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10839 __ sqrtss($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10840 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10841 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10842 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10843
a61af66fc99e Initial load
duke
parents:
diff changeset
10844 instruct sqrtD_reg(regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10845 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10846 match(Set dst (SqrtD src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10847
a61af66fc99e Initial load
duke
parents:
diff changeset
10848 format %{ "sqrtsd $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10849 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10850 opcode(0xF2, 0x0F, 0x51);
a61af66fc99e Initial load
duke
parents:
diff changeset
10851 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10852 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10853 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10854
a61af66fc99e Initial load
duke
parents:
diff changeset
10855 instruct sqrtD_mem(regD dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10856 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10857 match(Set dst (SqrtD (LoadD src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10858
a61af66fc99e Initial load
duke
parents:
diff changeset
10859 format %{ "sqrtsd $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10860 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10861 opcode(0xF2, 0x0F, 0x51);
a61af66fc99e Initial load
duke
parents:
diff changeset
10862 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10863 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10864 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10865
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10866 instruct sqrtD_imm(regD dst, immD con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10867 match(Set dst (SqrtD con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10868 format %{ "sqrtsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10869 ins_cost(150); // XXX
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10870 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10871 __ sqrtsd($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
10872 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10873 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10874 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10875
a61af66fc99e Initial load
duke
parents:
diff changeset
10876 instruct absF_reg(regF dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
10877 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10878 match(Set dst (AbsF dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10879
a61af66fc99e Initial load
duke
parents:
diff changeset
10880 format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10881 ins_encode(absF_encoding(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10882 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10883 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10884
a61af66fc99e Initial load
duke
parents:
diff changeset
10885 instruct absD_reg(regD dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
10886 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10887 match(Set dst (AbsD dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10888
a61af66fc99e Initial load
duke
parents:
diff changeset
10889 format %{ "andpd $dst, [0x7fffffffffffffff]\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10890 "# abs double by sign masking" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10891 ins_encode(absD_encoding(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10892 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10893 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10894
a61af66fc99e Initial load
duke
parents:
diff changeset
10895 instruct negF_reg(regF dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
10896 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10897 match(Set dst (NegF dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10898
a61af66fc99e Initial load
duke
parents:
diff changeset
10899 format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10900 ins_encode(negF_encoding(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10901 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10902 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10903
a61af66fc99e Initial load
duke
parents:
diff changeset
10904 instruct negD_reg(regD dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
10905 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10906 match(Set dst (NegD dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10907
a61af66fc99e Initial load
duke
parents:
diff changeset
10908 format %{ "xorpd $dst, [0x8000000000000000]\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10909 "# neg double by sign flipping" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10910 ins_encode(negD_encoding(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10911 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10912 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10913
a61af66fc99e Initial load
duke
parents:
diff changeset
10914 // -----------Trig and Trancendental Instructions------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
10915 instruct cosD_reg(regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10916 match(Set dst (CosD dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10917
a61af66fc99e Initial load
duke
parents:
diff changeset
10918 format %{ "dcos $dst\n\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10919 opcode(0xD9, 0xFF);
a61af66fc99e Initial load
duke
parents:
diff changeset
10920 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
10921 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
10922 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10923
a61af66fc99e Initial load
duke
parents:
diff changeset
10924 instruct sinD_reg(regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10925 match(Set dst (SinD dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10926
a61af66fc99e Initial load
duke
parents:
diff changeset
10927 format %{ "dsin $dst\n\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10928 opcode(0xD9, 0xFE);
a61af66fc99e Initial load
duke
parents:
diff changeset
10929 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
10930 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
10931 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10932
a61af66fc99e Initial load
duke
parents:
diff changeset
10933 instruct tanD_reg(regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10934 match(Set dst (TanD dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10935
a61af66fc99e Initial load
duke
parents:
diff changeset
10936 format %{ "dtan $dst\n\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10937 ins_encode( Push_SrcXD(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
10938 Opcode(0xD9), Opcode(0xF2), //fptan
a61af66fc99e Initial load
duke
parents:
diff changeset
10939 Opcode(0xDD), Opcode(0xD8), //fstp st
a61af66fc99e Initial load
duke
parents:
diff changeset
10940 Push_ResultXD(dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
10941 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
10942 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10943
a61af66fc99e Initial load
duke
parents:
diff changeset
10944 instruct log10D_reg(regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10945 // The source and result Double operands in XMM registers
a61af66fc99e Initial load
duke
parents:
diff changeset
10946 match(Set dst (Log10D dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10947 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
a61af66fc99e Initial load
duke
parents:
diff changeset
10948 // fyl2x ; compute log_10(2) * log_2(x)
a61af66fc99e Initial load
duke
parents:
diff changeset
10949 format %{ "fldlg2\t\t\t#Log10\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10950 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10951 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10952 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
a61af66fc99e Initial load
duke
parents:
diff changeset
10953 Push_SrcXD(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
10954 Opcode(0xD9), Opcode(0xF1), // fyl2x
a61af66fc99e Initial load
duke
parents:
diff changeset
10955 Push_ResultXD(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10956
a61af66fc99e Initial load
duke
parents:
diff changeset
10957 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
10958 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10959
a61af66fc99e Initial load
duke
parents:
diff changeset
10960 instruct logD_reg(regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10961 // The source and result Double operands in XMM registers
a61af66fc99e Initial load
duke
parents:
diff changeset
10962 match(Set dst (LogD dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10963 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
a61af66fc99e Initial load
duke
parents:
diff changeset
10964 // fyl2x ; compute log_e(2) * log_2(x)
a61af66fc99e Initial load
duke
parents:
diff changeset
10965 format %{ "fldln2\t\t\t#Log_e\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10966 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10967 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10968 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
a61af66fc99e Initial load
duke
parents:
diff changeset
10969 Push_SrcXD(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
10970 Opcode(0xD9), Opcode(0xF1), // fyl2x
a61af66fc99e Initial load
duke
parents:
diff changeset
10971 Push_ResultXD(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10972 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
10973 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10974
a61af66fc99e Initial load
duke
parents:
diff changeset
10975
a61af66fc99e Initial load
duke
parents:
diff changeset
10976
a61af66fc99e Initial load
duke
parents:
diff changeset
10977 //----------Arithmetic Conversion Instructions---------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
10978
a61af66fc99e Initial load
duke
parents:
diff changeset
10979 instruct roundFloat_nop(regF dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
10980 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10981 match(Set dst (RoundFloat dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10982
a61af66fc99e Initial load
duke
parents:
diff changeset
10983 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
10984 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
10985 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
10986 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10987
a61af66fc99e Initial load
duke
parents:
diff changeset
10988 instruct roundDouble_nop(regD dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
10989 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10990 match(Set dst (RoundDouble dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10991
a61af66fc99e Initial load
duke
parents:
diff changeset
10992 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
10993 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
10994 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
10995 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10996
a61af66fc99e Initial load
duke
parents:
diff changeset
10997 instruct convF2D_reg_reg(regD dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10998 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10999 match(Set dst (ConvF2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11000
a61af66fc99e Initial load
duke
parents:
diff changeset
11001 format %{ "cvtss2sd $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11002 opcode(0xF3, 0x0F, 0x5A);
a61af66fc99e Initial load
duke
parents:
diff changeset
11003 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11004 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11005 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11006
a61af66fc99e Initial load
duke
parents:
diff changeset
11007 instruct convF2D_reg_mem(regD dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11008 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11009 match(Set dst (ConvF2D (LoadF src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
11010
a61af66fc99e Initial load
duke
parents:
diff changeset
11011 format %{ "cvtss2sd $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11012 opcode(0xF3, 0x0F, 0x5A);
a61af66fc99e Initial load
duke
parents:
diff changeset
11013 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11014 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11015 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11016
a61af66fc99e Initial load
duke
parents:
diff changeset
11017 instruct convD2F_reg_reg(regF dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11018 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11019 match(Set dst (ConvD2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11020
a61af66fc99e Initial load
duke
parents:
diff changeset
11021 format %{ "cvtsd2ss $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11022 opcode(0xF2, 0x0F, 0x5A);
a61af66fc99e Initial load
duke
parents:
diff changeset
11023 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11024 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11025 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11026
a61af66fc99e Initial load
duke
parents:
diff changeset
11027 instruct convD2F_reg_mem(regF dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11028 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11029 match(Set dst (ConvD2F (LoadD src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
11030
a61af66fc99e Initial load
duke
parents:
diff changeset
11031 format %{ "cvtsd2ss $dst, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11032 opcode(0xF2, 0x0F, 0x5A);
a61af66fc99e Initial load
duke
parents:
diff changeset
11033 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11034 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11035 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11036
a61af66fc99e Initial load
duke
parents:
diff changeset
11037 // XXX do mem variants
a61af66fc99e Initial load
duke
parents:
diff changeset
11038 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
11039 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11040 match(Set dst (ConvF2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11041 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
11042
a61af66fc99e Initial load
duke
parents:
diff changeset
11043 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11044 "cmpl $dst, #0x80000000\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11045 "jne,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11046 "subq rsp, #8\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11047 "movss [rsp], $src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11048 "call f2i_fixup\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11049 "popq $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
11050 "done: "%}
a61af66fc99e Initial load
duke
parents:
diff changeset
11051 opcode(0xF3, 0x0F, 0x2C);
a61af66fc99e Initial load
duke
parents:
diff changeset
11052 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src),
a61af66fc99e Initial load
duke
parents:
diff changeset
11053 f2i_fixup(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11054 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11055 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11056
a61af66fc99e Initial load
duke
parents:
diff changeset
11057 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
11058 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11059 match(Set dst (ConvF2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11060 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
11061
a61af66fc99e Initial load
duke
parents:
diff changeset
11062 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11063 "cmpq $dst, [0x8000000000000000]\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11064 "jne,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11065 "subq rsp, #8\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11066 "movss [rsp], $src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11067 "call f2l_fixup\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11068 "popq $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
11069 "done: "%}
a61af66fc99e Initial load
duke
parents:
diff changeset
11070 opcode(0xF3, 0x0F, 0x2C);
a61af66fc99e Initial load
duke
parents:
diff changeset
11071 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src),
a61af66fc99e Initial load
duke
parents:
diff changeset
11072 f2l_fixup(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11073 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11074 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11075
a61af66fc99e Initial load
duke
parents:
diff changeset
11076 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
11077 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11078 match(Set dst (ConvD2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11079 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
11080
a61af66fc99e Initial load
duke
parents:
diff changeset
11081 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11082 "cmpl $dst, #0x80000000\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11083 "jne,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11084 "subq rsp, #8\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11085 "movsd [rsp], $src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11086 "call d2i_fixup\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11087 "popq $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
11088 "done: "%}
a61af66fc99e Initial load
duke
parents:
diff changeset
11089 opcode(0xF2, 0x0F, 0x2C);
a61af66fc99e Initial load
duke
parents:
diff changeset
11090 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src),
a61af66fc99e Initial load
duke
parents:
diff changeset
11091 d2i_fixup(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11092 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11093 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11094
a61af66fc99e Initial load
duke
parents:
diff changeset
11095 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
11096 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11097 match(Set dst (ConvD2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11098 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
11099
a61af66fc99e Initial load
duke
parents:
diff changeset
11100 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11101 "cmpq $dst, [0x8000000000000000]\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11102 "jne,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11103 "subq rsp, #8\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11104 "movsd [rsp], $src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11105 "call d2l_fixup\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11106 "popq $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
11107 "done: "%}
a61af66fc99e Initial load
duke
parents:
diff changeset
11108 opcode(0xF2, 0x0F, 0x2C);
a61af66fc99e Initial load
duke
parents:
diff changeset
11109 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src),
a61af66fc99e Initial load
duke
parents:
diff changeset
11110 d2l_fixup(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11111 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11112 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11113
a61af66fc99e Initial load
duke
parents:
diff changeset
11114 instruct convI2F_reg_reg(regF dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11115 %{
71
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11116 predicate(!UseXmmI2F);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11117 match(Set dst (ConvI2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11118
a61af66fc99e Initial load
duke
parents:
diff changeset
11119 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11120 opcode(0xF3, 0x0F, 0x2A);
a61af66fc99e Initial load
duke
parents:
diff changeset
11121 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11122 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11123 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11124
a61af66fc99e Initial load
duke
parents:
diff changeset
11125 instruct convI2F_reg_mem(regF dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11126 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11127 match(Set dst (ConvI2F (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
11128
a61af66fc99e Initial load
duke
parents:
diff changeset
11129 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11130 opcode(0xF3, 0x0F, 0x2A);
a61af66fc99e Initial load
duke
parents:
diff changeset
11131 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11132 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11133 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11134
a61af66fc99e Initial load
duke
parents:
diff changeset
11135 instruct convI2D_reg_reg(regD dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11136 %{
71
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11137 predicate(!UseXmmI2D);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11138 match(Set dst (ConvI2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11139
a61af66fc99e Initial load
duke
parents:
diff changeset
11140 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11141 opcode(0xF2, 0x0F, 0x2A);
a61af66fc99e Initial load
duke
parents:
diff changeset
11142 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11143 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11144 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11145
a61af66fc99e Initial load
duke
parents:
diff changeset
11146 instruct convI2D_reg_mem(regD dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11147 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11148 match(Set dst (ConvI2D (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
11149
a61af66fc99e Initial load
duke
parents:
diff changeset
11150 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11151 opcode(0xF2, 0x0F, 0x2A);
a61af66fc99e Initial load
duke
parents:
diff changeset
11152 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11153 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11154 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11155
71
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11156 instruct convXI2F_reg(regF dst, rRegI src)
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11157 %{
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11158 predicate(UseXmmI2F);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11159 match(Set dst (ConvI2F src));
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11160
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11161 format %{ "movdl $dst, $src\n\t"
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11162 "cvtdq2psl $dst, $dst\t# i2f" %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11163 ins_encode %{
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11164 __ movdl($dst$$XMMRegister, $src$$Register);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11165 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11166 %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11167 ins_pipe(pipe_slow); // XXX
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11168 %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11169
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11170 instruct convXI2D_reg(regD dst, rRegI src)
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11171 %{
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11172 predicate(UseXmmI2D);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11173 match(Set dst (ConvI2D src));
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11174
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11175 format %{ "movdl $dst, $src\n\t"
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11176 "cvtdq2pdl $dst, $dst\t# i2d" %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11177 ins_encode %{
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11178 __ movdl($dst$$XMMRegister, $src$$Register);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11179 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11180 %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11181 ins_pipe(pipe_slow); // XXX
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11182 %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
11183
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11184 instruct convL2F_reg_reg(regF dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11185 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11186 match(Set dst (ConvL2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11187
a61af66fc99e Initial load
duke
parents:
diff changeset
11188 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11189 opcode(0xF3, 0x0F, 0x2A);
a61af66fc99e Initial load
duke
parents:
diff changeset
11190 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11191 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11192 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11193
a61af66fc99e Initial load
duke
parents:
diff changeset
11194 instruct convL2F_reg_mem(regF dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11195 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11196 match(Set dst (ConvL2F (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
11197
a61af66fc99e Initial load
duke
parents:
diff changeset
11198 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11199 opcode(0xF3, 0x0F, 0x2A);
a61af66fc99e Initial load
duke
parents:
diff changeset
11200 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11201 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11202 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11203
a61af66fc99e Initial load
duke
parents:
diff changeset
11204 instruct convL2D_reg_reg(regD dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11205 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11206 match(Set dst (ConvL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11207
a61af66fc99e Initial load
duke
parents:
diff changeset
11208 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11209 opcode(0xF2, 0x0F, 0x2A);
a61af66fc99e Initial load
duke
parents:
diff changeset
11210 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11211 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11212 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11213
a61af66fc99e Initial load
duke
parents:
diff changeset
11214 instruct convL2D_reg_mem(regD dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11215 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11216 match(Set dst (ConvL2D (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
11217
a61af66fc99e Initial load
duke
parents:
diff changeset
11218 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11219 opcode(0xF2, 0x0F, 0x2A);
a61af66fc99e Initial load
duke
parents:
diff changeset
11220 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11221 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11222 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11223
a61af66fc99e Initial load
duke
parents:
diff changeset
11224 instruct convI2L_reg_reg(rRegL dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11225 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11226 match(Set dst (ConvI2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11227
a61af66fc99e Initial load
duke
parents:
diff changeset
11228 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
11229 format %{ "movslq $dst, $src\t# i2l" %}
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
11230 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
11231 __ movslq($dst$$Register, $src$$Register);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
11232 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11233 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
11234 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11235
a61af66fc99e Initial load
duke
parents:
diff changeset
11236 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11237 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11238 // match(Set dst (ConvI2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11239 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
a61af66fc99e Initial load
duke
parents:
diff changeset
11240 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
11241 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
a61af66fc99e Initial load
duke
parents:
diff changeset
11242 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
a61af66fc99e Initial load
duke
parents:
diff changeset
11243 // ((const TypeNode*) n)->type()->is_long()->_lo ==
a61af66fc99e Initial load
duke
parents:
diff changeset
11244 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
a61af66fc99e Initial load
duke
parents:
diff changeset
11245
a61af66fc99e Initial load
duke
parents:
diff changeset
11246 // format %{ "movl $dst, $src\t# unsigned i2l" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11247 // ins_encode(enc_copy(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11248 // // opcode(0x63); // needs REX.W
a61af66fc99e Initial load
duke
parents:
diff changeset
11249 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11250 // ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
11251 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11252
a61af66fc99e Initial load
duke
parents:
diff changeset
11253 // Zero-extend convert int to long
a61af66fc99e Initial load
duke
parents:
diff changeset
11254 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
a61af66fc99e Initial load
duke
parents:
diff changeset
11255 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11256 match(Set dst (AndL (ConvI2L src) mask));
a61af66fc99e Initial load
duke
parents:
diff changeset
11257
a61af66fc99e Initial load
duke
parents:
diff changeset
11258 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11259 ins_encode(enc_copy(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11260 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
11261 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11262
a61af66fc99e Initial load
duke
parents:
diff changeset
11263 // Zero-extend convert int to long
a61af66fc99e Initial load
duke
parents:
diff changeset
11264 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
a61af66fc99e Initial load
duke
parents:
diff changeset
11265 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11266 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
a61af66fc99e Initial load
duke
parents:
diff changeset
11267
a61af66fc99e Initial load
duke
parents:
diff changeset
11268 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11269 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
11270 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11271 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
11272 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11273
a61af66fc99e Initial load
duke
parents:
diff changeset
11274 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
a61af66fc99e Initial load
duke
parents:
diff changeset
11275 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11276 match(Set dst (AndL src mask));
a61af66fc99e Initial load
duke
parents:
diff changeset
11277
a61af66fc99e Initial load
duke
parents:
diff changeset
11278 format %{ "movl $dst, $src\t# zero-extend long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11279 ins_encode(enc_copy_always(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11280 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
11281 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11282
a61af66fc99e Initial load
duke
parents:
diff changeset
11283 instruct convL2I_reg_reg(rRegI dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11284 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11285 match(Set dst (ConvL2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11286
a61af66fc99e Initial load
duke
parents:
diff changeset
11287 format %{ "movl $dst, $src\t# l2i" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11288 ins_encode(enc_copy_always(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11289 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
11290 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11291
a61af66fc99e Initial load
duke
parents:
diff changeset
11292
a61af66fc99e Initial load
duke
parents:
diff changeset
11293 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11294 match(Set dst (MoveF2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11295 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
11296
a61af66fc99e Initial load
duke
parents:
diff changeset
11297 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
11298 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11299 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
11300 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11301 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
11302 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11303
a61af66fc99e Initial load
duke
parents:
diff changeset
11304 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11305 match(Set dst (MoveI2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11306 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
11307
a61af66fc99e Initial load
duke
parents:
diff changeset
11308 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
11309 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11310 opcode(0xF3, 0x0F, 0x10);
a61af66fc99e Initial load
duke
parents:
diff changeset
11311 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11312 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11313 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11314
a61af66fc99e Initial load
duke
parents:
diff changeset
11315 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11316 match(Set dst (MoveD2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11317 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
11318
a61af66fc99e Initial load
duke
parents:
diff changeset
11319 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
11320 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11321 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
11322 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11323 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
11324 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11325
a61af66fc99e Initial load
duke
parents:
diff changeset
11326 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11327 predicate(!UseXmmLoadAndClearUpper);
a61af66fc99e Initial load
duke
parents:
diff changeset
11328 match(Set dst (MoveL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11329 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
11330
a61af66fc99e Initial load
duke
parents:
diff changeset
11331 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
11332 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11333 opcode(0x66, 0x0F, 0x12);
a61af66fc99e Initial load
duke
parents:
diff changeset
11334 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11335 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11336 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11337
a61af66fc99e Initial load
duke
parents:
diff changeset
11338 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11339 predicate(UseXmmLoadAndClearUpper);
a61af66fc99e Initial load
duke
parents:
diff changeset
11340 match(Set dst (MoveL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11341 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
11342
a61af66fc99e Initial load
duke
parents:
diff changeset
11343 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
11344 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11345 opcode(0xF2, 0x0F, 0x10);
a61af66fc99e Initial load
duke
parents:
diff changeset
11346 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11347 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11348 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11349
a61af66fc99e Initial load
duke
parents:
diff changeset
11350
a61af66fc99e Initial load
duke
parents:
diff changeset
11351 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11352 match(Set dst (MoveF2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11353 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
11354
a61af66fc99e Initial load
duke
parents:
diff changeset
11355 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11356 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11357 opcode(0xF3, 0x0F, 0x11);
a61af66fc99e Initial load
duke
parents:
diff changeset
11358 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
11359 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11360 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11361
a61af66fc99e Initial load
duke
parents:
diff changeset
11362 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11363 match(Set dst (MoveI2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11364 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
11365
a61af66fc99e Initial load
duke
parents:
diff changeset
11366 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
11367 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11368 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
11369 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
11370 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
11371 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11372
a61af66fc99e Initial load
duke
parents:
diff changeset
11373 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11374 match(Set dst (MoveD2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11375 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
11376
a61af66fc99e Initial load
duke
parents:
diff changeset
11377 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11378 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11379 opcode(0xF2, 0x0F, 0x11);
a61af66fc99e Initial load
duke
parents:
diff changeset
11380 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
11381 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11382 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11383
a61af66fc99e Initial load
duke
parents:
diff changeset
11384 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11385 match(Set dst (MoveL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11386 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
11387
a61af66fc99e Initial load
duke
parents:
diff changeset
11388 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
11389 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11390 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
11391 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
11392 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
11393 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11394
a61af66fc99e Initial load
duke
parents:
diff changeset
11395 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11396 match(Set dst (MoveF2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11397 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
11398 ins_cost(85);
a61af66fc99e Initial load
duke
parents:
diff changeset
11399 format %{ "movd $dst,$src\t# MoveF2I" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11400 ins_encode %{ __ movdl($dst$$Register, $src$$XMMRegister); %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11401 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
11402 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11403
a61af66fc99e Initial load
duke
parents:
diff changeset
11404 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11405 match(Set dst (MoveD2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11406 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
11407 ins_cost(85);
a61af66fc99e Initial load
duke
parents:
diff changeset
11408 format %{ "movd $dst,$src\t# MoveD2L" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11409 ins_encode %{ __ movdq($dst$$Register, $src$$XMMRegister); %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11410 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
11411 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11412
a61af66fc99e Initial load
duke
parents:
diff changeset
11413 // The next instructions have long latency and use Int unit. Set high cost.
a61af66fc99e Initial load
duke
parents:
diff changeset
11414 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11415 match(Set dst (MoveI2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11416 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
11417 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11418 format %{ "movd $dst,$src\t# MoveI2F" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11419 ins_encode %{ __ movdl($dst$$XMMRegister, $src$$Register); %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11420 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
11421 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11422
a61af66fc99e Initial load
duke
parents:
diff changeset
11423 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11424 match(Set dst (MoveL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11425 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
11426 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11427 format %{ "movd $dst,$src\t# MoveL2D" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11428 ins_encode %{ __ movdq($dst$$XMMRegister, $src$$Register); %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11429 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
11430 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11431
a61af66fc99e Initial load
duke
parents:
diff changeset
11432 // Replicate scalar to packed byte (1 byte) values in xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
11433 instruct Repl8B_reg(regD dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11434 match(Set dst (Replicate8B src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11435 format %{ "MOVDQA $dst,$src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11436 "PUNPCKLBW $dst,$dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11437 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11438 ins_encode( pshufd_8x8(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11439 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
11440 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11441
a61af66fc99e Initial load
duke
parents:
diff changeset
11442 // Replicate scalar to packed byte (1 byte) values in xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
11443 instruct Repl8B_rRegI(regD dst, rRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11444 match(Set dst (Replicate8B src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11445 format %{ "MOVD $dst,$src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11446 "PUNPCKLBW $dst,$dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11447 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11448 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
11449 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
11450 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11451
a61af66fc99e Initial load
duke
parents:
diff changeset
11452 // Replicate scalar zero to packed byte (1 byte) values in xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
11453 instruct Repl8B_immI0(regD dst, immI0 zero) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11454 match(Set dst (Replicate8B zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
11455 format %{ "PXOR $dst,$dst\t! replicate8B" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11456 ins_encode( pxor(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
11457 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
11458 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11459
a61af66fc99e Initial load
duke
parents:
diff changeset
11460 // Replicate scalar to packed shore (2 byte) values in xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
11461 instruct Repl4S_reg(regD dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11462 match(Set dst (Replicate4S src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11463 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11464 ins_encode( pshufd_4x16(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11465 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
11466 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11467
a61af66fc99e Initial load
duke
parents:
diff changeset
11468 // Replicate scalar to packed shore (2 byte) values in xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
11469 instruct Repl4S_rRegI(regD dst, rRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11470 match(Set dst (Replicate4S src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11471 format %{ "MOVD $dst,$src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11472 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11473 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
11474 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
11475 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11476
a61af66fc99e Initial load
duke
parents:
diff changeset
11477 // Replicate scalar zero to packed short (2 byte) values in xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
11478 instruct Repl4S_immI0(regD dst, immI0 zero) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11479 match(Set dst (Replicate4S zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
11480 format %{ "PXOR $dst,$dst\t! replicate4S" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11481 ins_encode( pxor(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
11482 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
11483 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11484
a61af66fc99e Initial load
duke
parents:
diff changeset
11485 // Replicate scalar to packed char (2 byte) values in xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
11486 instruct Repl4C_reg(regD dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11487 match(Set dst (Replicate4C src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11488 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11489 ins_encode( pshufd_4x16(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11490 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
11491 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11492
a61af66fc99e Initial load
duke
parents:
diff changeset
11493 // Replicate scalar to packed char (2 byte) values in xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
11494 instruct Repl4C_rRegI(regD dst, rRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11495 match(Set dst (Replicate4C src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11496 format %{ "MOVD $dst,$src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11497 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11498 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
11499 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
11500 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11501
a61af66fc99e Initial load
duke
parents:
diff changeset
11502 // Replicate scalar zero to packed char (2 byte) values in xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
11503 instruct Repl4C_immI0(regD dst, immI0 zero) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11504 match(Set dst (Replicate4C zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
11505 format %{ "PXOR $dst,$dst\t! replicate4C" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11506 ins_encode( pxor(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
11507 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
11508 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11509
a61af66fc99e Initial load
duke
parents:
diff changeset
11510 // Replicate scalar to packed integer (4 byte) values in xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
11511 instruct Repl2I_reg(regD dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11512 match(Set dst (Replicate2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11513 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11514 ins_encode( pshufd(dst, src, 0x00));
a61af66fc99e Initial load
duke
parents:
diff changeset
11515 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
11516 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11517
a61af66fc99e Initial load
duke
parents:
diff changeset
11518 // Replicate scalar to packed integer (4 byte) values in xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
11519 instruct Repl2I_rRegI(regD dst, rRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11520 match(Set dst (Replicate2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11521 format %{ "MOVD $dst,$src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11522 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11523 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
a61af66fc99e Initial load
duke
parents:
diff changeset
11524 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
11525 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11526
a61af66fc99e Initial load
duke
parents:
diff changeset
11527 // Replicate scalar zero to packed integer (2 byte) values in xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
11528 instruct Repl2I_immI0(regD dst, immI0 zero) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11529 match(Set dst (Replicate2I zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
11530 format %{ "PXOR $dst,$dst\t! replicate2I" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11531 ins_encode( pxor(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
11532 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
11533 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11534
a61af66fc99e Initial load
duke
parents:
diff changeset
11535 // Replicate scalar to packed single precision floating point values in xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
11536 instruct Repl2F_reg(regD dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11537 match(Set dst (Replicate2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11538 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11539 ins_encode( pshufd(dst, src, 0xe0));
a61af66fc99e Initial load
duke
parents:
diff changeset
11540 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
11541 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11542
a61af66fc99e Initial load
duke
parents:
diff changeset
11543 // Replicate scalar to packed single precision floating point values in xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
11544 instruct Repl2F_regF(regD dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11545 match(Set dst (Replicate2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11546 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11547 ins_encode( pshufd(dst, src, 0xe0));
a61af66fc99e Initial load
duke
parents:
diff changeset
11548 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
11549 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11550
a61af66fc99e Initial load
duke
parents:
diff changeset
11551 // Replicate scalar to packed single precision floating point values in xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
11552 instruct Repl2F_immF0(regD dst, immF0 zero) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11553 match(Set dst (Replicate2F zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
11554 format %{ "PXOR $dst,$dst\t! replicate2F" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11555 ins_encode( pxor(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
11556 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
11557 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11558
a61af66fc99e Initial load
duke
parents:
diff changeset
11559
a61af66fc99e Initial load
duke
parents:
diff changeset
11560 // =======================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
11561 // fast clearing of an array
a61af66fc99e Initial load
duke
parents:
diff changeset
11562 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
a61af66fc99e Initial load
duke
parents:
diff changeset
11563 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
11564 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11565 match(Set dummy (ClearArray cnt base));
a61af66fc99e Initial load
duke
parents:
diff changeset
11566 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
11567
a61af66fc99e Initial load
duke
parents:
diff changeset
11568 format %{ "xorl rax, rax\t# ClearArray:\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11569 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11570 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax
a61af66fc99e Initial load
duke
parents:
diff changeset
11571 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos
a61af66fc99e Initial load
duke
parents:
diff changeset
11572 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11573 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11574
2262
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
11575 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
11576 rax_RegI result, regD tmp1, rFlagsReg cr)
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11577 %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11578 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
2262
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
11579 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
11580
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
11581 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11582 ins_encode %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11583 __ string_compare($str1$$Register, $str2$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11584 $cnt1$$Register, $cnt2$$Register, $result$$Register,
2262
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
11585 $tmp1$$XMMRegister);
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11586 %}
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
11587 ins_pipe( pipe_slow );
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
11588 %}
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
11589
2320
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11590 // fast search of substring with known size.
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11591 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11592 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11593 %{
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11594 predicate(UseSSE42Intrinsics);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11595 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11596 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11597
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11598 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11599 ins_encode %{
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11600 int icnt2 = (int)$int_cnt2$$constant;
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11601 if (icnt2 >= 8) {
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11602 // IndexOf for constant substrings with size >= 8 elements
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11603 // which don't need to be loaded through stack.
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11604 __ string_indexofC8($str1$$Register, $str2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11605 $cnt1$$Register, $cnt2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11606 icnt2, $result$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11607 $vec$$XMMRegister, $tmp$$Register);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11608 } else {
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11609 // Small strings are loaded through stack if they cross page boundary.
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11610 __ string_indexof($str1$$Register, $str2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11611 $cnt1$$Register, $cnt2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11612 icnt2, $result$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11613 $vec$$XMMRegister, $tmp$$Register);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11614 }
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11615 %}
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11616 ins_pipe( pipe_slow );
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11617 %}
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11618
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11619 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
2320
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11620 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
11621 %{
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
11622 predicate(UseSSE42Intrinsics);
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11623 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
2320
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11624 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11625
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11626 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11627 ins_encode %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11628 __ string_indexof($str1$$Register, $str2$$Register,
2320
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11629 $cnt1$$Register, $cnt2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11630 (-1), $result$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
11631 $vec$$XMMRegister, $tmp$$Register);
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11632 %}
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
11633 ins_pipe( pipe_slow );
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
11634 %}
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
11635
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
11636 // fast string equals
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11637 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11638 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11639 %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11640 match(Set result (StrEquals (Binary str1 str2) cnt));
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11641 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11642
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11643 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11644 ins_encode %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11645 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11646 $cnt$$Register, $result$$Register, $tmp3$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11647 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11648 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11649 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
11650 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11651
169
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
11652 // fast array equals
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11653 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11654 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
11655 %{
169
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
11656 match(Set result (AryEq ary1 ary2));
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
11657 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
169
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
11658 //ins_cost(300);
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
11659
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11660 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11661 ins_encode %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11662 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11663 $tmp3$$Register, $result$$Register, $tmp4$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11664 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
11665 %}
169
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
11666 ins_pipe( pipe_slow );
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
11667 %}
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
11668
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11669 //----------Control Flow Instructions------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
11670 // Signed compare Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
11671
a61af66fc99e Initial load
duke
parents:
diff changeset
11672 // XXX more variants!!
a61af66fc99e Initial load
duke
parents:
diff changeset
11673 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
11674 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11675 match(Set cr (CmpI op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11676 effect(DEF cr, USE op1, USE op2);
a61af66fc99e Initial load
duke
parents:
diff changeset
11677
a61af66fc99e Initial load
duke
parents:
diff changeset
11678 format %{ "cmpl $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11679 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
11680 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11681 ins_pipe(ialu_cr_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
11682 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11683
a61af66fc99e Initial load
duke
parents:
diff changeset
11684 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
11685 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11686 match(Set cr (CmpI op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11687
a61af66fc99e Initial load
duke
parents:
diff changeset
11688 format %{ "cmpl $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11689 opcode(0x81, 0x07); /* Opcode 81 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
11690 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11691 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
11692 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11693
a61af66fc99e Initial load
duke
parents:
diff changeset
11694 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
11695 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11696 match(Set cr (CmpI op1 (LoadI op2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
11697
a61af66fc99e Initial load
duke
parents:
diff changeset
11698 ins_cost(500); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11699 format %{ "cmpl $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11700 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
11701 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11702 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
11703 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11704
a61af66fc99e Initial load
duke
parents:
diff changeset
11705 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
11706 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11707 match(Set cr (CmpI src zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
11708
a61af66fc99e Initial load
duke
parents:
diff changeset
11709 format %{ "testl $src, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11710 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
11711 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11712 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
11713 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11714
a61af66fc99e Initial load
duke
parents:
diff changeset
11715 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
11716 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11717 match(Set cr (CmpI (AndI src con) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
11718
a61af66fc99e Initial load
duke
parents:
diff changeset
11719 format %{ "testl $src, $con" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11720 opcode(0xF7, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
11721 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
a61af66fc99e Initial load
duke
parents:
diff changeset
11722 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
11723 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11724
a61af66fc99e Initial load
duke
parents:
diff changeset
11725 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
11726 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11727 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
11728
a61af66fc99e Initial load
duke
parents:
diff changeset
11729 format %{ "testl $src, $mem" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11730 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
11731 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
11732 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
11733 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11734
a61af66fc99e Initial load
duke
parents:
diff changeset
11735 // Unsigned compare Instructions; really, same as signed except they
a61af66fc99e Initial load
duke
parents:
diff changeset
11736 // produce an rFlagsRegU instead of rFlagsReg.
a61af66fc99e Initial load
duke
parents:
diff changeset
11737 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
11738 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11739 match(Set cr (CmpU op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11740
a61af66fc99e Initial load
duke
parents:
diff changeset
11741 format %{ "cmpl $op1, $op2\t# unsigned" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11742 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
11743 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11744 ins_pipe(ialu_cr_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
11745 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11746
a61af66fc99e Initial load
duke
parents:
diff changeset
11747 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
11748 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11749 match(Set cr (CmpU op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11750
a61af66fc99e Initial load
duke
parents:
diff changeset
11751 format %{ "cmpl $op1, $op2\t# unsigned" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11752 opcode(0x81,0x07); /* Opcode 81 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
11753 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11754 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
11755 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11756
a61af66fc99e Initial load
duke
parents:
diff changeset
11757 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
11758 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11759 match(Set cr (CmpU op1 (LoadI op2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
11760
a61af66fc99e Initial load
duke
parents:
diff changeset
11761 ins_cost(500); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11762 format %{ "cmpl $op1, $op2\t# unsigned" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11763 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
11764 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11765 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
11766 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11767
a61af66fc99e Initial load
duke
parents:
diff changeset
11768 // // // Cisc-spilled version of cmpU_rReg
a61af66fc99e Initial load
duke
parents:
diff changeset
11769 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
11770 // //%{
a61af66fc99e Initial load
duke
parents:
diff changeset
11771 // // match(Set cr (CmpU (LoadI op1) op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11772 // //
a61af66fc99e Initial load
duke
parents:
diff changeset
11773 // // format %{ "CMPu $op1,$op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11774 // // ins_cost(500);
a61af66fc99e Initial load
duke
parents:
diff changeset
11775 // // opcode(0x39); /* Opcode 39 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
11776 // // ins_encode( OpcP, reg_mem( op1, op2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
11777 // //%}
a61af66fc99e Initial load
duke
parents:
diff changeset
11778
a61af66fc99e Initial load
duke
parents:
diff changeset
11779 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
11780 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11781 match(Set cr (CmpU src zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
11782
a61af66fc99e Initial load
duke
parents:
diff changeset
11783 format %{ "testl $src, $src\t# unsigned" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11784 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
11785 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11786 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
11787 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11788
a61af66fc99e Initial load
duke
parents:
diff changeset
11789 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
11790 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11791 match(Set cr (CmpP op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11792
a61af66fc99e Initial load
duke
parents:
diff changeset
11793 format %{ "cmpq $op1, $op2\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11794 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
11795 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11796 ins_pipe(ialu_cr_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
11797 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11798
a61af66fc99e Initial load
duke
parents:
diff changeset
11799 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
11800 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11801 match(Set cr (CmpP op1 (LoadP op2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
11802
a61af66fc99e Initial load
duke
parents:
diff changeset
11803 ins_cost(500); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11804 format %{ "cmpq $op1, $op2\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11805 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
11806 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11807 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
11808 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11809
a61af66fc99e Initial load
duke
parents:
diff changeset
11810 // // // Cisc-spilled version of cmpP_rReg
a61af66fc99e Initial load
duke
parents:
diff changeset
11811 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
11812 // //%{
a61af66fc99e Initial load
duke
parents:
diff changeset
11813 // // match(Set cr (CmpP (LoadP op1) op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11814 // //
a61af66fc99e Initial load
duke
parents:
diff changeset
11815 // // format %{ "CMPu $op1,$op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11816 // // ins_cost(500);
a61af66fc99e Initial load
duke
parents:
diff changeset
11817 // // opcode(0x39); /* Opcode 39 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
11818 // // ins_encode( OpcP, reg_mem( op1, op2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
11819 // //%}
a61af66fc99e Initial load
duke
parents:
diff changeset
11820
a61af66fc99e Initial load
duke
parents:
diff changeset
11821 // XXX this is generalized by compP_rReg_mem???
a61af66fc99e Initial load
duke
parents:
diff changeset
11822 // Compare raw pointer (used in out-of-heap check).
a61af66fc99e Initial load
duke
parents:
diff changeset
11823 // Only works because non-oop pointers must be raw pointers
a61af66fc99e Initial load
duke
parents:
diff changeset
11824 // and raw pointers have no anti-dependencies.
a61af66fc99e Initial load
duke
parents:
diff changeset
11825 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
11826 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11827 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr());
a61af66fc99e Initial load
duke
parents:
diff changeset
11828 match(Set cr (CmpP op1 (LoadP op2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
11829
a61af66fc99e Initial load
duke
parents:
diff changeset
11830 format %{ "cmpq $op1, $op2\t# raw ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11831 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
11832 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11833 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
11834 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11835
a61af66fc99e Initial load
duke
parents:
diff changeset
11836 // This will generate a signed flags result. This should be OK since
a61af66fc99e Initial load
duke
parents:
diff changeset
11837 // any compare to a zero should be eq/neq.
a61af66fc99e Initial load
duke
parents:
diff changeset
11838 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
11839 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11840 match(Set cr (CmpP src zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
11841
a61af66fc99e Initial load
duke
parents:
diff changeset
11842 format %{ "testq $src, $src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11843 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
11844 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11845 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
11846 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11847
a61af66fc99e Initial load
duke
parents:
diff changeset
11848 // This will generate a signed flags result. This should be OK since
a61af66fc99e Initial load
duke
parents:
diff changeset
11849 // any compare to a zero should be eq/neq.
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11850 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11851 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11852 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11853 match(Set cr (CmpP (LoadP op) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
11854
a61af66fc99e Initial load
duke
parents:
diff changeset
11855 ins_cost(500); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
11856 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11857 opcode(0xF7); /* Opcode F7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
11858 ins_encode(REX_mem_wide(op),
a61af66fc99e Initial load
duke
parents:
diff changeset
11859 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
a61af66fc99e Initial load
duke
parents:
diff changeset
11860 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
11861 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11862
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11863 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11864 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11865 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11866 match(Set cr (CmpP (LoadP mem) zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11867
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11868 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11869 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11870 __ cmpq(r12, $mem$$Address);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11871 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11872 ins_pipe(ialu_cr_reg_mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11873 %}
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11874
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11875 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11876 %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11877 match(Set cr (CmpN op1 op2));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11878
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11879 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11880 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11881 ins_pipe(ialu_cr_reg_reg);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11882 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11883
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11884 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11885 %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11886 match(Set cr (CmpN src (LoadN mem)));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11887
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11888 format %{ "cmpl $src, $mem\t# compressed ptr" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11889 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11890 __ cmpl($src$$Register, $mem$$Address);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11891 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11892 ins_pipe(ialu_cr_reg_mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11893 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11894
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11895 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11896 match(Set cr (CmpN op1 op2));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11897
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11898 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11899 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11900 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11901 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11902 ins_pipe(ialu_cr_reg_imm);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11903 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11904
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11905 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11906 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11907 match(Set cr (CmpN src (LoadN mem)));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11908
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11909 format %{ "cmpl $mem, $src\t# compressed ptr" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11910 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11911 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11912 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11913 ins_pipe(ialu_cr_reg_mem);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11914 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11915
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
11916 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
11917 match(Set cr (CmpN src zero));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
11918
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11919 format %{ "testl $src, $src\t# compressed ptr" %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
11920 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
11921 ins_pipe(ialu_cr_reg_imm);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
11922 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
11923
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11924 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11925 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11926 predicate(Universe::narrow_oop_base() != NULL);
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11927 match(Set cr (CmpN (LoadN mem) zero));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11928
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11929 ins_cost(500); // XXX
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11930 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11931 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11932 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11933 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11934 ins_pipe(ialu_cr_reg_mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11935 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11936
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11937 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11938 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11939 predicate(Universe::narrow_oop_base() == NULL);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11940 match(Set cr (CmpN (LoadN mem) zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11941
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11942 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11943 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
11944 __ cmpl(r12, $mem$$Address);
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11945 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11946 ins_pipe(ialu_cr_reg_mem);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11947 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
11948
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11949 // Yanked all unsigned pointer compare operations.
a61af66fc99e Initial load
duke
parents:
diff changeset
11950 // Pointer compares are done with CmpP which is already unsigned.
a61af66fc99e Initial load
duke
parents:
diff changeset
11951
a61af66fc99e Initial load
duke
parents:
diff changeset
11952 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
11953 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11954 match(Set cr (CmpL op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11955
a61af66fc99e Initial load
duke
parents:
diff changeset
11956 format %{ "cmpq $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11957 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
11958 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11959 ins_pipe(ialu_cr_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
11960 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11961
a61af66fc99e Initial load
duke
parents:
diff changeset
11962 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
11963 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11964 match(Set cr (CmpL op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11965
a61af66fc99e Initial load
duke
parents:
diff changeset
11966 format %{ "cmpq $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11967 opcode(0x81, 0x07); /* Opcode 81 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
11968 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11969 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
11970 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11971
a61af66fc99e Initial load
duke
parents:
diff changeset
11972 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
11973 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11974 match(Set cr (CmpL op1 (LoadL op2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
11975
a61af66fc99e Initial load
duke
parents:
diff changeset
11976 format %{ "cmpq $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11977 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
11978 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
11979 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
11980 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11981
a61af66fc99e Initial load
duke
parents:
diff changeset
11982 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
11983 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11984 match(Set cr (CmpL src zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
11985
a61af66fc99e Initial load
duke
parents:
diff changeset
11986 format %{ "testq $src, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11987 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
11988 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11989 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
11990 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11991
a61af66fc99e Initial load
duke
parents:
diff changeset
11992 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
11993 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11994 match(Set cr (CmpL (AndL src con) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
11995
a61af66fc99e Initial load
duke
parents:
diff changeset
11996 format %{ "testq $src, $con\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11997 opcode(0xF7, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
11998 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
a61af66fc99e Initial load
duke
parents:
diff changeset
11999 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
12000 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12001
a61af66fc99e Initial load
duke
parents:
diff changeset
12002 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
12003 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12004 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
12005
a61af66fc99e Initial load
duke
parents:
diff changeset
12006 format %{ "testq $src, $mem" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12007 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
12008 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
12009 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
12010 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12011
a61af66fc99e Initial load
duke
parents:
diff changeset
12012 // Manifest a CmpL result in an integer register. Very painful.
a61af66fc99e Initial load
duke
parents:
diff changeset
12013 // This is the test to avoid.
a61af66fc99e Initial load
duke
parents:
diff changeset
12014 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
a61af66fc99e Initial load
duke
parents:
diff changeset
12015 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12016 match(Set dst (CmpL3 src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
12017 effect(KILL flags);
a61af66fc99e Initial load
duke
parents:
diff changeset
12018
a61af66fc99e Initial load
duke
parents:
diff changeset
12019 ins_cost(275); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
12020 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12021 "movl $dst, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12022 "jl,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12023 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12024 "movzbl $dst, $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12025 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12026 ins_encode(cmpl3_flag(src1, src2, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
12027 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
12028 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12029
a61af66fc99e Initial load
duke
parents:
diff changeset
12030 //----------Max and Min--------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
12031 // Min Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
12032
a61af66fc99e Initial load
duke
parents:
diff changeset
12033 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
12034 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12035 effect(USE_DEF dst, USE src, USE cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
12036
a61af66fc99e Initial load
duke
parents:
diff changeset
12037 format %{ "cmovlgt $dst, $src\t# min" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12038 opcode(0x0F, 0x4F);
a61af66fc99e Initial load
duke
parents:
diff changeset
12039 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
12040 ins_pipe(pipe_cmov_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
12041 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12042
a61af66fc99e Initial load
duke
parents:
diff changeset
12043
a61af66fc99e Initial load
duke
parents:
diff changeset
12044 instruct minI_rReg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
12045 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12046 match(Set dst (MinI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
12047
a61af66fc99e Initial load
duke
parents:
diff changeset
12048 ins_cost(200);
a61af66fc99e Initial load
duke
parents:
diff changeset
12049 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12050 rFlagsReg cr;
a61af66fc99e Initial load
duke
parents:
diff changeset
12051 compI_rReg(cr, dst, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
12052 cmovI_reg_g(dst, src, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
12053 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12054 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12055
a61af66fc99e Initial load
duke
parents:
diff changeset
12056 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
12057 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12058 effect(USE_DEF dst, USE src, USE cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
12059
a61af66fc99e Initial load
duke
parents:
diff changeset
12060 format %{ "cmovllt $dst, $src\t# max" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12061 opcode(0x0F, 0x4C);
a61af66fc99e Initial load
duke
parents:
diff changeset
12062 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
12063 ins_pipe(pipe_cmov_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
12064 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12065
a61af66fc99e Initial load
duke
parents:
diff changeset
12066
a61af66fc99e Initial load
duke
parents:
diff changeset
12067 instruct maxI_rReg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
12068 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12069 match(Set dst (MaxI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
12070
a61af66fc99e Initial load
duke
parents:
diff changeset
12071 ins_cost(200);
a61af66fc99e Initial load
duke
parents:
diff changeset
12072 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12073 rFlagsReg cr;
a61af66fc99e Initial load
duke
parents:
diff changeset
12074 compI_rReg(cr, dst, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
12075 cmovI_reg_l(dst, src, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
12076 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12077 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12078
a61af66fc99e Initial load
duke
parents:
diff changeset
12079 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
12080 // Branch Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
12081
a61af66fc99e Initial load
duke
parents:
diff changeset
12082 // Jump Direct - Label defines a relative address from JMP+1
a61af66fc99e Initial load
duke
parents:
diff changeset
12083 instruct jmpDir(label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
12084 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12085 match(Goto);
a61af66fc99e Initial load
duke
parents:
diff changeset
12086 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
12087
a61af66fc99e Initial load
duke
parents:
diff changeset
12088 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
12089 format %{ "jmp $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12090 size(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
12091 opcode(0xE9);
a61af66fc99e Initial load
duke
parents:
diff changeset
12092 ins_encode(OpcP, Lbl(labl));
a61af66fc99e Initial load
duke
parents:
diff changeset
12093 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
12094 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12095 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12096
a61af66fc99e Initial load
duke
parents:
diff changeset
12097 // Jump Direct Conditional - Label defines a relative address from Jcc+1
a61af66fc99e Initial load
duke
parents:
diff changeset
12098 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
12099 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12100 match(If cop cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
12101 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
12102
a61af66fc99e Initial load
duke
parents:
diff changeset
12103 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
12104 format %{ "j$cop $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12105 size(6);
a61af66fc99e Initial load
duke
parents:
diff changeset
12106 opcode(0x0F, 0x80);
a61af66fc99e Initial load
duke
parents:
diff changeset
12107 ins_encode(Jcc(cop, labl));
a61af66fc99e Initial load
duke
parents:
diff changeset
12108 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
12109 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12110 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12111
a61af66fc99e Initial load
duke
parents:
diff changeset
12112 // Jump Direct Conditional - Label defines a relative address from Jcc+1
a61af66fc99e Initial load
duke
parents:
diff changeset
12113 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
12114 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12115 match(CountedLoopEnd cop cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
12116 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
12117
a61af66fc99e Initial load
duke
parents:
diff changeset
12118 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
12119 format %{ "j$cop $labl\t# loop end" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12120 size(6);
a61af66fc99e Initial load
duke
parents:
diff changeset
12121 opcode(0x0F, 0x80);
a61af66fc99e Initial load
duke
parents:
diff changeset
12122 ins_encode(Jcc(cop, labl));
a61af66fc99e Initial load
duke
parents:
diff changeset
12123 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
12124 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12125 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12126
a61af66fc99e Initial load
duke
parents:
diff changeset
12127 // Jump Direct Conditional - Label defines a relative address from Jcc+1
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12128 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12129 match(CountedLoopEnd cop cmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
12130 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
12131
a61af66fc99e Initial load
duke
parents:
diff changeset
12132 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
12133 format %{ "j$cop,u $labl\t# loop end" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12134 size(6);
a61af66fc99e Initial load
duke
parents:
diff changeset
12135 opcode(0x0F, 0x80);
a61af66fc99e Initial load
duke
parents:
diff changeset
12136 ins_encode(Jcc(cop, labl));
a61af66fc99e Initial load
duke
parents:
diff changeset
12137 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
12138 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12139 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12140
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12141 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12142 match(CountedLoopEnd cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12143 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12144
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12145 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12146 format %{ "j$cop,u $labl\t# loop end" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12147 size(6);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12148 opcode(0x0F, 0x80);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12149 ins_encode(Jcc(cop, labl));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12150 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12151 ins_pc_relative(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12152 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12153
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12154 // Jump Direct Conditional - using unsigned comparison
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12155 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12156 match(If cop cmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
12157 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
12158
a61af66fc99e Initial load
duke
parents:
diff changeset
12159 ins_cost(300);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12160 format %{ "j$cop,u $labl" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12161 size(6);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12162 opcode(0x0F, 0x80);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12163 ins_encode(Jcc(cop, labl));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12164 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12165 ins_pc_relative(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12166 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12167
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12168 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12169 match(If cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12170 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12171
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12172 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12173 format %{ "j$cop,u $labl" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12174 size(6);
a61af66fc99e Initial load
duke
parents:
diff changeset
12175 opcode(0x0F, 0x80);
a61af66fc99e Initial load
duke
parents:
diff changeset
12176 ins_encode(Jcc(cop, labl));
a61af66fc99e Initial load
duke
parents:
diff changeset
12177 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
12178 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12179 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12180
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12181 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12182 match(If cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12183 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12184
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12185 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12186 format %{ $$template
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12187 if ($cop$$cmpcode == Assembler::notEqual) {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12188 $$emit$$"jp,u $labl\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12189 $$emit$$"j$cop,u $labl"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12190 } else {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12191 $$emit$$"jp,u done\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12192 $$emit$$"j$cop,u $labl\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12193 $$emit$$"done:"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12194 }
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12195 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12196 size(12);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12197 opcode(0x0F, 0x80);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12198 ins_encode %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12199 Label* l = $labl$$label;
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12200 $$$emit8$primary;
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12201 emit_cc(cbuf, $secondary, Assembler::parity);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12202 int parity_disp = -1;
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12203 if ($cop$$cmpcode == Assembler::notEqual) {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12204 // the two jumps 6 bytes apart so the jump distances are too
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
12205 parity_disp = l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0;
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12206 } else if ($cop$$cmpcode == Assembler::equal) {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12207 parity_disp = 6;
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12208 } else {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12209 ShouldNotReachHere();
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12210 }
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12211 emit_d32(cbuf, parity_disp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12212 $$$emit8$primary;
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12213 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
12214 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0;
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12215 emit_d32(cbuf, disp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12216 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12217 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12218 ins_pc_relative(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12219 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12220
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12221 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
12222 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
a61af66fc99e Initial load
duke
parents:
diff changeset
12223 // superklass array for an instance of the superklass. Set a hidden
a61af66fc99e Initial load
duke
parents:
diff changeset
12224 // internal cache on a hit (cache is checked with exposed code in
a61af66fc99e Initial load
duke
parents:
diff changeset
12225 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
a61af66fc99e Initial load
duke
parents:
diff changeset
12226 // encoding ALSO sets flags.
a61af66fc99e Initial load
duke
parents:
diff changeset
12227
a61af66fc99e Initial load
duke
parents:
diff changeset
12228 instruct partialSubtypeCheck(rdi_RegP result,
a61af66fc99e Initial load
duke
parents:
diff changeset
12229 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
a61af66fc99e Initial load
duke
parents:
diff changeset
12230 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
12231 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12232 match(Set result (PartialSubtypeCheck sub super));
a61af66fc99e Initial load
duke
parents:
diff changeset
12233 effect(KILL rcx, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
12234
a61af66fc99e Initial load
duke
parents:
diff changeset
12235 ins_cost(1100); // slightly larger than the next version
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 643
diff changeset
12236 format %{ "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12237 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12238 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12239 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12240 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12241 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12242 "xorq $result, $result\t\t Hit: rdi zero\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12243 "miss:\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12244
a61af66fc99e Initial load
duke
parents:
diff changeset
12245 opcode(0x1); // Force a XOR of RDI
a61af66fc99e Initial load
duke
parents:
diff changeset
12246 ins_encode(enc_PartialSubtypeCheck());
a61af66fc99e Initial load
duke
parents:
diff changeset
12247 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
12248 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12249
a61af66fc99e Initial load
duke
parents:
diff changeset
12250 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
a61af66fc99e Initial load
duke
parents:
diff changeset
12251 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
a61af66fc99e Initial load
duke
parents:
diff changeset
12252 immP0 zero,
a61af66fc99e Initial load
duke
parents:
diff changeset
12253 rdi_RegP result)
a61af66fc99e Initial load
duke
parents:
diff changeset
12254 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12255 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
12256 effect(KILL rcx, KILL result);
a61af66fc99e Initial load
duke
parents:
diff changeset
12257
a61af66fc99e Initial load
duke
parents:
diff changeset
12258 ins_cost(1000);
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 643
diff changeset
12259 format %{ "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12260 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12261 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12262 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12263 "jne,s miss\t\t# Missed: flags nz\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12264 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12265 "miss:\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12266
a61af66fc99e Initial load
duke
parents:
diff changeset
12267 opcode(0x0); // No need to XOR RDI
a61af66fc99e Initial load
duke
parents:
diff changeset
12268 ins_encode(enc_PartialSubtypeCheck());
a61af66fc99e Initial load
duke
parents:
diff changeset
12269 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
12270 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12271
a61af66fc99e Initial load
duke
parents:
diff changeset
12272 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
12273 // Branch Instructions -- short offset versions
a61af66fc99e Initial load
duke
parents:
diff changeset
12274 //
a61af66fc99e Initial load
duke
parents:
diff changeset
12275 // These instructions are used to replace jumps of a long offset (the default
a61af66fc99e Initial load
duke
parents:
diff changeset
12276 // match) with jumps of a shorter offset. These instructions are all tagged
a61af66fc99e Initial load
duke
parents:
diff changeset
12277 // with the ins_short_branch attribute, which causes the ADLC to suppress the
a61af66fc99e Initial load
duke
parents:
diff changeset
12278 // match rules in general matching. Instead, the ADLC generates a conversion
a61af66fc99e Initial load
duke
parents:
diff changeset
12279 // method in the MachNode which can be used to do in-place replacement of the
a61af66fc99e Initial load
duke
parents:
diff changeset
12280 // long variant with the shorter variant. The compiler will determine if a
a61af66fc99e Initial load
duke
parents:
diff changeset
12281 // branch can be taken by the is_short_branch_offset() predicate in the machine
a61af66fc99e Initial load
duke
parents:
diff changeset
12282 // specific code section of the file.
a61af66fc99e Initial load
duke
parents:
diff changeset
12283
a61af66fc99e Initial load
duke
parents:
diff changeset
12284 // Jump Direct - Label defines a relative address from JMP+1
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12285 instruct jmpDir_short(label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12286 match(Goto);
a61af66fc99e Initial load
duke
parents:
diff changeset
12287 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
12288
a61af66fc99e Initial load
duke
parents:
diff changeset
12289 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
12290 format %{ "jmp,s $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12291 size(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
12292 opcode(0xEB);
a61af66fc99e Initial load
duke
parents:
diff changeset
12293 ins_encode(OpcP, LblShort(labl));
a61af66fc99e Initial load
duke
parents:
diff changeset
12294 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
12295 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12296 ins_short_branch(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12297 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12298
a61af66fc99e Initial load
duke
parents:
diff changeset
12299 // Jump Direct Conditional - Label defines a relative address from Jcc+1
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12300 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12301 match(If cop cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
12302 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
12303
a61af66fc99e Initial load
duke
parents:
diff changeset
12304 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
12305 format %{ "j$cop,s $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12306 size(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
12307 opcode(0x70);
a61af66fc99e Initial load
duke
parents:
diff changeset
12308 ins_encode(JccShort(cop, labl));
a61af66fc99e Initial load
duke
parents:
diff changeset
12309 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
12310 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12311 ins_short_branch(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12312 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12313
a61af66fc99e Initial load
duke
parents:
diff changeset
12314 // Jump Direct Conditional - Label defines a relative address from Jcc+1
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12315 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12316 match(CountedLoopEnd cop cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
12317 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
12318
a61af66fc99e Initial load
duke
parents:
diff changeset
12319 ins_cost(300);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12320 format %{ "j$cop,s $labl\t# loop end" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12321 size(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
12322 opcode(0x70);
a61af66fc99e Initial load
duke
parents:
diff changeset
12323 ins_encode(JccShort(cop, labl));
a61af66fc99e Initial load
duke
parents:
diff changeset
12324 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
12325 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12326 ins_short_branch(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12327 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12328
a61af66fc99e Initial load
duke
parents:
diff changeset
12329 // Jump Direct Conditional - Label defines a relative address from Jcc+1
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12330 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12331 match(CountedLoopEnd cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12332 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12333
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12334 ins_cost(300);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12335 format %{ "j$cop,us $labl\t# loop end" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12336 size(2);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12337 opcode(0x70);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12338 ins_encode(JccShort(cop, labl));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12339 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12340 ins_pc_relative(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12341 ins_short_branch(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12342 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12343
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12344 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12345 match(CountedLoopEnd cop cmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
12346 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
12347
a61af66fc99e Initial load
duke
parents:
diff changeset
12348 ins_cost(300);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12349 format %{ "j$cop,us $labl\t# loop end" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12350 size(2);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12351 opcode(0x70);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12352 ins_encode(JccShort(cop, labl));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12353 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12354 ins_pc_relative(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12355 ins_short_branch(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12356 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12357
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12358 // Jump Direct Conditional - using unsigned comparison
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12359 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12360 match(If cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12361 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12362
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12363 ins_cost(300);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12364 format %{ "j$cop,us $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12365 size(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
12366 opcode(0x70);
a61af66fc99e Initial load
duke
parents:
diff changeset
12367 ins_encode(JccShort(cop, labl));
a61af66fc99e Initial load
duke
parents:
diff changeset
12368 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
12369 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12370 ins_short_branch(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12371 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12372
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12373 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12374 match(If cop cmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
12375 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
12376
a61af66fc99e Initial load
duke
parents:
diff changeset
12377 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
12378 format %{ "j$cop,us $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12379 size(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
12380 opcode(0x70);
a61af66fc99e Initial load
duke
parents:
diff changeset
12381 ins_encode(JccShort(cop, labl));
a61af66fc99e Initial load
duke
parents:
diff changeset
12382 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
12383 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12384 ins_short_branch(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12385 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12386
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12387 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12388 match(If cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12389 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12390
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12391 ins_cost(300);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12392 format %{ $$template
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12393 if ($cop$$cmpcode == Assembler::notEqual) {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12394 $$emit$$"jp,u,s $labl\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12395 $$emit$$"j$cop,u,s $labl"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12396 } else {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12397 $$emit$$"jp,u,s done\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12398 $$emit$$"j$cop,u,s $labl\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12399 $$emit$$"done:"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12400 }
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12401 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12402 size(4);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12403 opcode(0x70);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12404 ins_encode %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12405 Label* l = $labl$$label;
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12406 emit_cc(cbuf, $primary, Assembler::parity);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12407 int parity_disp = -1;
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12408 if ($cop$$cmpcode == Assembler::notEqual) {
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
12409 parity_disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0;
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12410 } else if ($cop$$cmpcode == Assembler::equal) {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12411 parity_disp = 2;
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12412 } else {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12413 ShouldNotReachHere();
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12414 }
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12415 emit_d8(cbuf, parity_disp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12416 emit_cc(cbuf, $primary, $cop$$cmpcode);
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
12417 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0;
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12418 emit_d8(cbuf, disp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12419 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12420 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12421 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12422 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12423 ins_pc_relative(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12424 ins_short_branch(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12425 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
12426
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12427 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
12428 // inlined locking and unlocking
a61af66fc99e Initial load
duke
parents:
diff changeset
12429
a61af66fc99e Initial load
duke
parents:
diff changeset
12430 instruct cmpFastLock(rFlagsReg cr,
a61af66fc99e Initial load
duke
parents:
diff changeset
12431 rRegP object, rRegP box, rax_RegI tmp, rRegP scr)
a61af66fc99e Initial load
duke
parents:
diff changeset
12432 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12433 match(Set cr (FastLock object box));
a61af66fc99e Initial load
duke
parents:
diff changeset
12434 effect(TEMP tmp, TEMP scr);
a61af66fc99e Initial load
duke
parents:
diff changeset
12435
a61af66fc99e Initial load
duke
parents:
diff changeset
12436 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
12437 format %{ "fastlock $object,$box,$tmp,$scr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12438 ins_encode(Fast_Lock(object, box, tmp, scr));
a61af66fc99e Initial load
duke
parents:
diff changeset
12439 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
12440 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12441 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12442
a61af66fc99e Initial load
duke
parents:
diff changeset
12443 instruct cmpFastUnlock(rFlagsReg cr,
a61af66fc99e Initial load
duke
parents:
diff changeset
12444 rRegP object, rax_RegP box, rRegP tmp)
a61af66fc99e Initial load
duke
parents:
diff changeset
12445 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12446 match(Set cr (FastUnlock object box));
a61af66fc99e Initial load
duke
parents:
diff changeset
12447 effect(TEMP tmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
12448
a61af66fc99e Initial load
duke
parents:
diff changeset
12449 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
12450 format %{ "fastunlock $object, $box, $tmp" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12451 ins_encode(Fast_Unlock(object, box, tmp));
a61af66fc99e Initial load
duke
parents:
diff changeset
12452 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
12453 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12454 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12455
a61af66fc99e Initial load
duke
parents:
diff changeset
12456
a61af66fc99e Initial load
duke
parents:
diff changeset
12457 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
12458 // Safepoint Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
12459 instruct safePoint_poll(rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
12460 %{
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12461 predicate(!Assembler::is_polling_page_far());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12462 match(SafePoint);
a61af66fc99e Initial load
duke
parents:
diff changeset
12463 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
12464
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12465 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12466 "# Safepoint: poll for GC" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12467 ins_cost(125);
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12468 ins_encode %{
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12469 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12470 __ testl(rax, addr);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12471 %}
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12472 ins_pipe(ialu_reg_mem);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12473 %}
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12474
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12475 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12476 %{
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12477 predicate(Assembler::is_polling_page_far());
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12478 match(SafePoint poll);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12479 effect(KILL cr, USE poll);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12480
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12481 format %{ "testl rax, [$poll]\t"
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12482 "# Safepoint: poll for GC" %}
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12483 ins_cost(125);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12484 ins_encode %{
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12485 __ relocate(relocInfo::poll_type);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12486 __ testl(rax, Address($poll$$Register, 0));
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
12487 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12488 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
12489 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12490
a61af66fc99e Initial load
duke
parents:
diff changeset
12491 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
12492 // Procedure Call/Return Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
12493 // Call Java Static Instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
12494 // Note: If this code changes, the corresponding ret_addr_offset() and
a61af66fc99e Initial load
duke
parents:
diff changeset
12495 // compute_padding() functions will have to be adjusted.
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12496 instruct CallStaticJavaDirect(method meth) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12497 match(CallStaticJava);
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12498 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12499 effect(USE meth);
a61af66fc99e Initial load
duke
parents:
diff changeset
12500
a61af66fc99e Initial load
duke
parents:
diff changeset
12501 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
12502 format %{ "call,static " %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12503 opcode(0xE8); /* E8 cd */
a61af66fc99e Initial load
duke
parents:
diff changeset
12504 ins_encode(Java_Static_Call(meth), call_epilog);
a61af66fc99e Initial load
duke
parents:
diff changeset
12505 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
12506 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12507 ins_alignment(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
12508 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12509
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12510 // Call Java Static Instruction (method handle version)
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12511 // Note: If this code changes, the corresponding ret_addr_offset() and
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12512 // compute_padding() functions will have to be adjusted.
1567
110501f54a99 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 1396
diff changeset
12513 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12514 match(CallStaticJava);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12515 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke());
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12516 effect(USE meth);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12517 // RBP is saved by all callees (for interpreter stack correction).
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12518 // We use it here for a similar purpose, in {preserve,restore}_SP.
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12519
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12520 ins_cost(300);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12521 format %{ "call,static/MethodHandle " %}
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12522 opcode(0xE8); /* E8 cd */
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12523 ins_encode(preserve_SP,
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12524 Java_Static_Call(meth),
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12525 restore_SP,
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12526 call_epilog);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12527 ins_pipe(pipe_slow);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12528 ins_pc_relative(1);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12529 ins_alignment(4);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12530 %}
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
12531
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12532 // Call Java Dynamic Instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
12533 // Note: If this code changes, the corresponding ret_addr_offset() and
a61af66fc99e Initial load
duke
parents:
diff changeset
12534 // compute_padding() functions will have to be adjusted.
a61af66fc99e Initial load
duke
parents:
diff changeset
12535 instruct CallDynamicJavaDirect(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
12536 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12537 match(CallDynamicJava);
a61af66fc99e Initial load
duke
parents:
diff changeset
12538 effect(USE meth);
a61af66fc99e Initial load
duke
parents:
diff changeset
12539
a61af66fc99e Initial load
duke
parents:
diff changeset
12540 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
12541 format %{ "movq rax, #Universe::non_oop_word()\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12542 "call,dynamic " %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12543 opcode(0xE8); /* E8 cd */
a61af66fc99e Initial load
duke
parents:
diff changeset
12544 ins_encode(Java_Dynamic_Call(meth), call_epilog);
a61af66fc99e Initial load
duke
parents:
diff changeset
12545 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
12546 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12547 ins_alignment(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
12548 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12549
a61af66fc99e Initial load
duke
parents:
diff changeset
12550 // Call Runtime Instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
12551 instruct CallRuntimeDirect(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
12552 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12553 match(CallRuntime);
a61af66fc99e Initial load
duke
parents:
diff changeset
12554 effect(USE meth);
a61af66fc99e Initial load
duke
parents:
diff changeset
12555
a61af66fc99e Initial load
duke
parents:
diff changeset
12556 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
12557 format %{ "call,runtime " %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12558 opcode(0xE8); /* E8 cd */
a61af66fc99e Initial load
duke
parents:
diff changeset
12559 ins_encode(Java_To_Runtime(meth));
a61af66fc99e Initial load
duke
parents:
diff changeset
12560 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
12561 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12562 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12563
a61af66fc99e Initial load
duke
parents:
diff changeset
12564 // Call runtime without safepoint
a61af66fc99e Initial load
duke
parents:
diff changeset
12565 instruct CallLeafDirect(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
12566 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12567 match(CallLeaf);
a61af66fc99e Initial load
duke
parents:
diff changeset
12568 effect(USE meth);
a61af66fc99e Initial load
duke
parents:
diff changeset
12569
a61af66fc99e Initial load
duke
parents:
diff changeset
12570 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
12571 format %{ "call_leaf,runtime " %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12572 opcode(0xE8); /* E8 cd */
a61af66fc99e Initial load
duke
parents:
diff changeset
12573 ins_encode(Java_To_Runtime(meth));
a61af66fc99e Initial load
duke
parents:
diff changeset
12574 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
12575 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12576 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12577
a61af66fc99e Initial load
duke
parents:
diff changeset
12578 // Call runtime without safepoint
a61af66fc99e Initial load
duke
parents:
diff changeset
12579 instruct CallLeafNoFPDirect(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
12580 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12581 match(CallLeafNoFP);
a61af66fc99e Initial load
duke
parents:
diff changeset
12582 effect(USE meth);
a61af66fc99e Initial load
duke
parents:
diff changeset
12583
a61af66fc99e Initial load
duke
parents:
diff changeset
12584 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
12585 format %{ "call_leaf_nofp,runtime " %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12586 opcode(0xE8); /* E8 cd */
a61af66fc99e Initial load
duke
parents:
diff changeset
12587 ins_encode(Java_To_Runtime(meth));
a61af66fc99e Initial load
duke
parents:
diff changeset
12588 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
12589 ins_pc_relative(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
12590 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12591
a61af66fc99e Initial load
duke
parents:
diff changeset
12592 // Return Instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
12593 // Remove the return address & jump to it.
a61af66fc99e Initial load
duke
parents:
diff changeset
12594 // Notice: We always emit a nop after a ret to make sure there is room
a61af66fc99e Initial load
duke
parents:
diff changeset
12595 // for safepoint patching
a61af66fc99e Initial load
duke
parents:
diff changeset
12596 instruct Ret()
a61af66fc99e Initial load
duke
parents:
diff changeset
12597 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12598 match(Return);
a61af66fc99e Initial load
duke
parents:
diff changeset
12599
a61af66fc99e Initial load
duke
parents:
diff changeset
12600 format %{ "ret" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12601 opcode(0xC3);
a61af66fc99e Initial load
duke
parents:
diff changeset
12602 ins_encode(OpcP);
a61af66fc99e Initial load
duke
parents:
diff changeset
12603 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
12604 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12605
a61af66fc99e Initial load
duke
parents:
diff changeset
12606 // Tail Call; Jump from runtime stub to Java code.
a61af66fc99e Initial load
duke
parents:
diff changeset
12607 // Also known as an 'interprocedural jump'.
a61af66fc99e Initial load
duke
parents:
diff changeset
12608 // Target of jump will eventually return to caller.
a61af66fc99e Initial load
duke
parents:
diff changeset
12609 // TailJump below removes the return address.
a61af66fc99e Initial load
duke
parents:
diff changeset
12610 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
a61af66fc99e Initial load
duke
parents:
diff changeset
12611 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12612 match(TailCall jump_target method_oop);
a61af66fc99e Initial load
duke
parents:
diff changeset
12613
a61af66fc99e Initial load
duke
parents:
diff changeset
12614 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
12615 format %{ "jmp $jump_target\t# rbx holds method oop" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12616 opcode(0xFF, 0x4); /* Opcode FF /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
12617 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
a61af66fc99e Initial load
duke
parents:
diff changeset
12618 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
12619 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12620
a61af66fc99e Initial load
duke
parents:
diff changeset
12621 // Tail Jump; remove the return address; jump to target.
a61af66fc99e Initial load
duke
parents:
diff changeset
12622 // TailCall above leaves the return address around.
a61af66fc99e Initial load
duke
parents:
diff changeset
12623 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
a61af66fc99e Initial load
duke
parents:
diff changeset
12624 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12625 match(TailJump jump_target ex_oop);
a61af66fc99e Initial load
duke
parents:
diff changeset
12626
a61af66fc99e Initial load
duke
parents:
diff changeset
12627 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
12628 format %{ "popq rdx\t# pop return address\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
12629 "jmp $jump_target" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12630 opcode(0xFF, 0x4); /* Opcode FF /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
12631 ins_encode(Opcode(0x5a), // popq rdx
a61af66fc99e Initial load
duke
parents:
diff changeset
12632 REX_reg(jump_target), OpcP, reg_opc(jump_target));
a61af66fc99e Initial load
duke
parents:
diff changeset
12633 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
12634 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12635
a61af66fc99e Initial load
duke
parents:
diff changeset
12636 // Create exception oop: created by stack-crawling runtime code.
a61af66fc99e Initial load
duke
parents:
diff changeset
12637 // Created exception is now available to this handler, and is setup
a61af66fc99e Initial load
duke
parents:
diff changeset
12638 // just prior to jumping to this handler. No code emitted.
a61af66fc99e Initial load
duke
parents:
diff changeset
12639 instruct CreateException(rax_RegP ex_oop)
a61af66fc99e Initial load
duke
parents:
diff changeset
12640 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12641 match(Set ex_oop (CreateEx));
a61af66fc99e Initial load
duke
parents:
diff changeset
12642
a61af66fc99e Initial load
duke
parents:
diff changeset
12643 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
12644 // use the following format syntax
a61af66fc99e Initial load
duke
parents:
diff changeset
12645 format %{ "# exception oop is in rax; no code emitted" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12646 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
12647 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
12648 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12649
a61af66fc99e Initial load
duke
parents:
diff changeset
12650 // Rethrow exception:
a61af66fc99e Initial load
duke
parents:
diff changeset
12651 // The exception oop will come in the first argument position.
a61af66fc99e Initial load
duke
parents:
diff changeset
12652 // Then JUMP (not call) to the rethrow stub code.
a61af66fc99e Initial load
duke
parents:
diff changeset
12653 instruct RethrowException()
a61af66fc99e Initial load
duke
parents:
diff changeset
12654 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12655 match(Rethrow);
a61af66fc99e Initial load
duke
parents:
diff changeset
12656
a61af66fc99e Initial load
duke
parents:
diff changeset
12657 // use the following format syntax
a61af66fc99e Initial load
duke
parents:
diff changeset
12658 format %{ "jmp rethrow_stub" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12659 ins_encode(enc_rethrow);
a61af66fc99e Initial load
duke
parents:
diff changeset
12660 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
12661 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12662
a61af66fc99e Initial load
duke
parents:
diff changeset
12663
a61af66fc99e Initial load
duke
parents:
diff changeset
12664 //----------PEEPHOLE RULES-----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
12665 // These must follow all instruction definitions as they use the names
a61af66fc99e Initial load
duke
parents:
diff changeset
12666 // defined in the instructions definitions.
a61af66fc99e Initial load
duke
parents:
diff changeset
12667 //
605
98cb887364d3 6810672: Comment typos
twisti
parents: 569
diff changeset
12668 // peepmatch ( root_instr_name [preceding_instruction]* );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
12669 //
a61af66fc99e Initial load
duke
parents:
diff changeset
12670 // peepconstraint %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12671 // (instruction_number.operand_name relational_op instruction_number.operand_name
a61af66fc99e Initial load
duke
parents:
diff changeset
12672 // [, ...] );
a61af66fc99e Initial load
duke
parents:
diff changeset
12673 // // instruction numbers are zero-based using left to right order in peepmatch
a61af66fc99e Initial load
duke
parents:
diff changeset
12674 //
a61af66fc99e Initial load
duke
parents:
diff changeset
12675 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
12676 // // provide an instruction_number.operand_name for each operand that appears
a61af66fc99e Initial load
duke
parents:
diff changeset
12677 // // in the replacement instruction's match rule
a61af66fc99e Initial load
duke
parents:
diff changeset
12678 //
a61af66fc99e Initial load
duke
parents:
diff changeset
12679 // ---------VM FLAGS---------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
12680 //
a61af66fc99e Initial load
duke
parents:
diff changeset
12681 // All peephole optimizations can be turned off using -XX:-OptoPeephole
a61af66fc99e Initial load
duke
parents:
diff changeset
12682 //
a61af66fc99e Initial load
duke
parents:
diff changeset
12683 // Each peephole rule is given an identifying number starting with zero and
a61af66fc99e Initial load
duke
parents:
diff changeset
12684 // increasing by one in the order seen by the parser. An individual peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
12685 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
a61af66fc99e Initial load
duke
parents:
diff changeset
12686 // on the command-line.
a61af66fc99e Initial load
duke
parents:
diff changeset
12687 //
a61af66fc99e Initial load
duke
parents:
diff changeset
12688 // ---------CURRENT LIMITATIONS----------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
12689 //
a61af66fc99e Initial load
duke
parents:
diff changeset
12690 // Only match adjacent instructions in same basic block
a61af66fc99e Initial load
duke
parents:
diff changeset
12691 // Only equality constraints
a61af66fc99e Initial load
duke
parents:
diff changeset
12692 // Only constraints between operands, not (0.dest_reg == RAX_enc)
a61af66fc99e Initial load
duke
parents:
diff changeset
12693 // Only one replacement instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
12694 //
a61af66fc99e Initial load
duke
parents:
diff changeset
12695 // ---------EXAMPLE----------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
12696 //
a61af66fc99e Initial load
duke
parents:
diff changeset
12697 // // pertinent parts of existing instructions in architecture description
a61af66fc99e Initial load
duke
parents:
diff changeset
12698 // instruct movI(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
12699 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12700 // match(Set dst (CopyI src));
a61af66fc99e Initial load
duke
parents:
diff changeset
12701 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12702 //
a61af66fc99e Initial load
duke
parents:
diff changeset
12703 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
12704 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12705 // match(Set dst (AddI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
12706 // effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
12707 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12708 //
a61af66fc99e Initial load
duke
parents:
diff changeset
12709 // // Change (inc mov) to lea
a61af66fc99e Initial load
duke
parents:
diff changeset
12710 // peephole %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12711 // // increment preceeded by register-register move
a61af66fc99e Initial load
duke
parents:
diff changeset
12712 // peepmatch ( incI_rReg movI );
a61af66fc99e Initial load
duke
parents:
diff changeset
12713 // // require that the destination register of the increment
a61af66fc99e Initial load
duke
parents:
diff changeset
12714 // // match the destination register of the move
a61af66fc99e Initial load
duke
parents:
diff changeset
12715 // peepconstraint ( 0.dst == 1.dst );
a61af66fc99e Initial load
duke
parents:
diff changeset
12716 // // construct a replacement instruction that sets
a61af66fc99e Initial load
duke
parents:
diff changeset
12717 // // the destination to ( move's source register + one )
a61af66fc99e Initial load
duke
parents:
diff changeset
12718 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
12719 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12720 //
a61af66fc99e Initial load
duke
parents:
diff changeset
12721
a61af66fc99e Initial load
duke
parents:
diff changeset
12722 // Implementation no longer uses movX instructions since
a61af66fc99e Initial load
duke
parents:
diff changeset
12723 // machine-independent system no longer uses CopyX nodes.
a61af66fc99e Initial load
duke
parents:
diff changeset
12724 //
a61af66fc99e Initial load
duke
parents:
diff changeset
12725 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
12726 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12727 // peepmatch (incI_rReg movI);
a61af66fc99e Initial load
duke
parents:
diff changeset
12728 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
12729 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
12730 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12731
a61af66fc99e Initial load
duke
parents:
diff changeset
12732 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
12733 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12734 // peepmatch (decI_rReg movI);
a61af66fc99e Initial load
duke
parents:
diff changeset
12735 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
12736 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
12737 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12738
a61af66fc99e Initial load
duke
parents:
diff changeset
12739 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
12740 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12741 // peepmatch (addI_rReg_imm movI);
a61af66fc99e Initial load
duke
parents:
diff changeset
12742 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
12743 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
12744 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12745
a61af66fc99e Initial load
duke
parents:
diff changeset
12746 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
12747 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12748 // peepmatch (incL_rReg movL);
a61af66fc99e Initial load
duke
parents:
diff changeset
12749 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
12750 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
12751 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12752
a61af66fc99e Initial load
duke
parents:
diff changeset
12753 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
12754 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12755 // peepmatch (decL_rReg movL);
a61af66fc99e Initial load
duke
parents:
diff changeset
12756 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
12757 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
12758 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12759
a61af66fc99e Initial load
duke
parents:
diff changeset
12760 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
12761 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12762 // peepmatch (addL_rReg_imm movL);
a61af66fc99e Initial load
duke
parents:
diff changeset
12763 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
12764 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
a61af66fc99e Initial load
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parents:
diff changeset
12765 // %}
a61af66fc99e Initial load
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parents:
diff changeset
12766
a61af66fc99e Initial load
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parents:
diff changeset
12767 // peephole
a61af66fc99e Initial load
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parents:
diff changeset
12768 // %{
a61af66fc99e Initial load
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parents:
diff changeset
12769 // peepmatch (addP_rReg_imm movP);
a61af66fc99e Initial load
duke
parents:
diff changeset
12770 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
12771 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
a61af66fc99e Initial load
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parents:
diff changeset
12772 // %}
a61af66fc99e Initial load
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parents:
diff changeset
12773
a61af66fc99e Initial load
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parents:
diff changeset
12774 // // Change load of spilled value to only a spill
a61af66fc99e Initial load
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parents:
diff changeset
12775 // instruct storeI(memory mem, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
12776 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12777 // match(Set mem (StoreI mem src));
a61af66fc99e Initial load
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parents:
diff changeset
12778 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12779 //
a61af66fc99e Initial load
duke
parents:
diff changeset
12780 // instruct loadI(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
12781 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12782 // match(Set dst (LoadI mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
12783 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12784 //
a61af66fc99e Initial load
duke
parents:
diff changeset
12785
a61af66fc99e Initial load
duke
parents:
diff changeset
12786 peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
12787 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12788 peepmatch (loadI storeI);
a61af66fc99e Initial load
duke
parents:
diff changeset
12789 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
12790 peepreplace (storeI(1.mem 1.mem 1.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
12791 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12792
a61af66fc99e Initial load
duke
parents:
diff changeset
12793 peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
12794 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
12795 peepmatch (loadL storeL);
a61af66fc99e Initial load
duke
parents:
diff changeset
12796 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
12797 peepreplace (storeL(1.mem 1.mem 1.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
12798 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
12799
a61af66fc99e Initial load
duke
parents:
diff changeset
12800 //----------SMARTSPILL RULES---------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
12801 // These must follow all instruction definitions as they use the names
a61af66fc99e Initial load
duke
parents:
diff changeset
12802 // defined in the instructions definitions.