Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sparc.ad @ 12660:a2b1ee69ce46
Loose unnecessary input dependencies from write barriers
author | Christos Kotselidis <christos.kotselidis@oracle.com> |
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date | Mon, 04 Nov 2013 15:42:27 +0100 |
parents | c9ccd7b85f20 |
children | 59e8ad757e19 209aa13ab8c0 |
rev | line source |
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0 | 1 // |
9154 | 2 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved. |
0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 // | |
5 // This code is free software; you can redistribute it and/or modify it | |
6 // under the terms of the GNU General Public License version 2 only, as | |
7 // published by the Free Software Foundation. | |
8 // | |
9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 // version 2 for more details (a copy is included in the LICENSE file that | |
13 // accompanied this code). | |
14 // | |
15 // You should have received a copy of the GNU General Public License version | |
16 // 2 along with this work; if not, write to the Free Software Foundation, | |
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 // | |
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
0 | 22 // |
23 // | |
24 | |
25 // SPARC Architecture Description File | |
26 | |
27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
28 // This information is used by the matcher and the register allocator to | |
29 // describe individual registers and classes of registers within the target | |
30 // archtecture. | |
31 register %{ | |
32 //----------Architecture Description Register Definitions---------------------- | |
33 // General Registers | |
34 // "reg_def" name ( register save type, C convention save type, | |
35 // ideal register type, encoding, vm name ); | |
36 // Register Save Types: | |
37 // | |
38 // NS = No-Save: The register allocator assumes that these registers | |
39 // can be used without saving upon entry to the method, & | |
40 // that they do not need to be saved at call sites. | |
41 // | |
42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
43 // can be used without saving upon entry to the method, | |
44 // but that they must be saved at call sites. | |
45 // | |
46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
47 // must be saved before using them upon entry to the | |
48 // method, but they do not need to be saved at call | |
49 // sites. | |
50 // | |
51 // AS = Always-Save: The register allocator assumes that these registers | |
52 // must be saved before using them upon entry to the | |
53 // method, & that they must be saved at call sites. | |
54 // | |
55 // Ideal Register Type is used to determine how to save & restore a | |
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
58 // | |
59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
60 | |
61 | |
62 // ---------------------------- | |
63 // Integer/Long Registers | |
64 // ---------------------------- | |
65 | |
66 // Need to expose the hi/lo aspect of 64-bit registers | |
67 // This register set is used for both the 64-bit build and | |
68 // the 32-bit build with 1-register longs. | |
69 | |
70 // Global Registers 0-7 | |
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
87 | |
88 // Output Registers 0-7 | |
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
105 | |
106 // Local Registers 0-7 | |
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
123 | |
124 // Input Registers 0-7 | |
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
141 | |
142 // ---------------------------- | |
143 // Float/Double Registers | |
144 // ---------------------------- | |
145 | |
146 // Float Registers | |
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
179 | |
180 // Double Registers | |
181 // The rules of ADL require that double registers be defined in pairs. | |
182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
183 // single float registers. In each pair, ADLC-assigned register numbers | |
184 // must be adjacent, with the lower number even. Finally, when the | |
185 // CPU stores such a register pair to memory, the word associated with | |
186 // the lower ADLC-assigned number must be stored to the lower address. | |
187 | |
188 // These definitions specify the actual bit encodings of the sparc | |
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
190 // wants 0-63, so we have to convert every time we want to use fp regs | |
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
605 | 192 // 255 is a flag meaning "don't go here". |
0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
194 // the place in the sparc stack crawler that asserts on the 255 is | |
195 // fixed up. | |
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196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
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197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
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198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
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199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
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200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
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201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
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202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
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203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
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204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
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205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
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206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
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207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
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208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
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209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
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210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
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211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
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212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
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213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
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214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
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215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
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216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
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217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
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218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
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219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
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220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
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221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
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222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
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223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
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224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
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225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
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226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
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227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
0 | 228 |
229 | |
230 // ---------------------------- | |
231 // Special Registers | |
232 // Condition Codes Flag Registers | |
233 // I tried to break out ICC and XCC but it's not very pretty. | |
234 // Every Sparc instruction which defs/kills one also kills the other. | |
235 // Hence every compare instruction which defs one kind of flags ends | |
236 // up needing a kill of the other. | |
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
238 | |
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
243 | |
244 // ---------------------------- | |
245 // Specify the enum values for the registers. These enums are only used by the | |
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
247 // for visibility to the rest of the vm. The order of this enum influences the | |
248 // register allocator so having the freedom to set this order and not be stuck | |
249 // with the order that is natural for the rest of the vm is worth it. | |
250 alloc_class chunk0( | |
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
255 | |
256 // Note that a register is not allocatable unless it is also mentioned | |
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
258 | |
259 alloc_class chunk1( | |
260 // The first registers listed here are those most likely to be used | |
261 // as temporaries. We move F0..F7 away from the front of the list, | |
262 // to reduce the likelihood of interferences with parameters and | |
263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
264 // since they are used for return values. | |
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
274 | |
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
276 | |
277 //----------Architecture Description Register Classes-------------------------- | |
278 // Several register classes are automatically defined based upon information in | |
279 // this architecture description. | |
280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
283 // | |
284 | |
285 // G0 is not included in integer class since it has special meaning. | |
286 reg_class g0_reg(R_G0); | |
287 | |
288 // ---------------------------- | |
289 // Integer Register Classes | |
290 // ---------------------------- | |
291 // Exclusions from i_reg: | |
292 // R_G0: hardwired zero | |
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
294 // R_G6: reserved by Solaris ABI to tools | |
295 // R_G7: reserved by Solaris ABI to libthread | |
296 // R_O7: Used as a temp in many encodings | |
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
298 | |
299 // Class for all integer registers, except the G registers. This is used for | |
300 // encodings which use G registers as temps. The regular inputs to such | |
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
302 // will not put an input into a temp register. | |
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
304 | |
305 reg_class g1_regI(R_G1); | |
306 reg_class g3_regI(R_G3); | |
307 reg_class g4_regI(R_G4); | |
308 reg_class o0_regI(R_O0); | |
309 reg_class o7_regI(R_O7); | |
310 | |
311 // ---------------------------- | |
312 // Pointer Register Classes | |
313 // ---------------------------- | |
314 #ifdef _LP64 | |
315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
320 // Lock encodings use G3 and G4 internally | |
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
326 // It is also used for memory addressing, allowing direct TLS addressing. | |
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
332 // We use it to save R_G2 across calls out of Java. | |
333 reg_class l7_regP(R_L7H,R_L7); | |
334 | |
335 // Other special pointer regs | |
336 reg_class g1_regP(R_G1H,R_G1); | |
337 reg_class g2_regP(R_G2H,R_G2); | |
338 reg_class g3_regP(R_G3H,R_G3); | |
339 reg_class g4_regP(R_G4H,R_G4); | |
340 reg_class g5_regP(R_G5H,R_G5); | |
341 reg_class i0_regP(R_I0H,R_I0); | |
342 reg_class o0_regP(R_O0H,R_O0); | |
343 reg_class o1_regP(R_O1H,R_O1); | |
344 reg_class o2_regP(R_O2H,R_O2); | |
345 reg_class o7_regP(R_O7H,R_O7); | |
346 | |
347 #else // _LP64 | |
348 // 32-bit build means 32-bit pointers means 1 register. | |
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
353 // Lock encodings use G3 and G4 internally | |
354 reg_class lock_ptr_reg(R_G1, R_G5, | |
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
359 // It is also used for memory addressing, allowing direct TLS addressing. | |
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
365 // We use it to save R_G2 across calls out of Java. | |
366 reg_class l7_regP(R_L7); | |
367 | |
368 // Other special pointer regs | |
369 reg_class g1_regP(R_G1); | |
370 reg_class g2_regP(R_G2); | |
371 reg_class g3_regP(R_G3); | |
372 reg_class g4_regP(R_G4); | |
373 reg_class g5_regP(R_G5); | |
374 reg_class i0_regP(R_I0); | |
375 reg_class o0_regP(R_O0); | |
376 reg_class o1_regP(R_O1); | |
377 reg_class o2_regP(R_O2); | |
378 reg_class o7_regP(R_O7); | |
379 #endif // _LP64 | |
380 | |
381 | |
382 // ---------------------------- | |
383 // Long Register Classes | |
384 // ---------------------------- | |
385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
389 #ifdef _LP64 | |
390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
394 #endif // _LP64 | |
395 ); | |
396 | |
397 reg_class g1_regL(R_G1H,R_G1); | |
420
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398 reg_class g3_regL(R_G3H,R_G3); |
0 | 399 reg_class o2_regL(R_O2H,R_O2); |
400 reg_class o7_regL(R_O7H,R_O7); | |
401 | |
402 // ---------------------------- | |
403 // Special Class for Condition Code Flags Register | |
404 reg_class int_flags(CCR); | |
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
406 reg_class float_flag0(FCC0); | |
407 | |
408 | |
409 // ---------------------------- | |
410 // Float Point Register Classes | |
411 // ---------------------------- | |
412 // Skip F30/F31, they are reserved for mem-mem copies | |
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
414 | |
415 // Paired floating point registers--they show up in the same order as the floats, | |
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
422 ); | |
423 | |
424 // Paired floating point registers--they show up in the same order as the floats, | |
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
3804 | 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); |
0 | 429 %} |
430 | |
431 //----------DEFINITION BLOCK--------------------------------------------------- | |
432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
434 // Format: | |
435 // int_def <name> ( <int_value>, <expression>); | |
436 // Generated Code in ad_<arch>.hpp | |
437 // #define <name> (<expression>) | |
438 // // value == <int_value> | |
439 // Generated code in ad_<arch>.cpp adlc_verification() | |
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
441 // | |
442 definitions %{ | |
443 // The default cost (of an ALU instruction). | |
444 int_def DEFAULT_COST ( 100, 100); | |
445 int_def HUGE_COST (1000000, 1000000); | |
446 | |
447 // Memory refs are twice as expensive as run-of-the-mill. | |
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
449 | |
450 // Branches are even more expensive. | |
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
453 %} | |
454 | |
455 | |
456 //----------SOURCE BLOCK------------------------------------------------------- | |
457 // This is a block of C++ code which provides values, functions, and | |
458 // definitions necessary in the rest of the architecture description | |
459 source_hpp %{ | |
460 // Must be visible to the DFA in dfa_sparc.cpp | |
461 extern bool can_branch_register( Node *bol, Node *cmp ); | |
462 | |
3892 | 463 extern bool use_block_zeroing(Node* count); |
464 | |
0 | 465 // Macros to extract hi & lo halves from a long pair. |
466 // G0 is not part of any long pair, so assert on that. | |
605 | 467 // Prevents accidentally using G1 instead of G0. |
0 | 468 #define LONG_HI_REG(x) (x) |
469 #define LONG_LO_REG(x) (x) | |
470 | |
471 %} | |
472 | |
473 source %{ | |
474 #define __ _masm. | |
475 | |
476 // tertiary op of a LoadP or StoreP encoding | |
477 #define REGP_OP true | |
478 | |
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
481 static Register reg_to_register_object(int register_encoding); | |
482 | |
483 // Used by the DFA in dfa_sparc.cpp. | |
484 // Check for being able to use a V9 branch-on-register. Requires a | |
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
486 // extended. Doesn't work following an integer ADD, for example, because of | |
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
489 // replace them with zero, which could become sign-extension in a different OS | |
490 // release. There's no obvious reason why an interrupt will ever fill these | |
491 // bits with non-zero junk (the registers are reloaded with standard LD | |
492 // instructions which either zero-fill or sign-fill). | |
493 bool can_branch_register( Node *bol, Node *cmp ) { | |
494 if( !BranchOnRegister ) return false; | |
495 #ifdef _LP64 | |
496 if( cmp->Opcode() == Op_CmpP ) | |
497 return true; // No problems with pointer compares | |
498 #endif | |
499 if( cmp->Opcode() == Op_CmpL ) | |
500 return true; // No problems with long compares | |
501 | |
502 if( !SparcV9RegsHiBitsZero ) return false; | |
503 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
504 bol->as_Bool()->_test._test != BoolTest::eq ) | |
505 return false; | |
506 | |
507 // Check for comparing against a 'safe' value. Any operation which | |
508 // clears out the high word is safe. Thus, loads and certain shifts | |
509 // are safe, as are non-negative constants. Any operation which | |
510 // preserves zero bits in the high word is safe as long as each of its | |
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
512 // inputs are safe. At present, the only important case to recognize | |
513 // seems to be loads. Constants should fold away, and shifts & | |
514 // logicals can use the 'cc' forms. | |
515 Node *x = cmp->in(1); | |
516 if( x->is_Load() ) return true; | |
517 if( x->is_Phi() ) { | |
518 for( uint i = 1; i < x->req(); i++ ) | |
519 if( !x->in(i)->is_Load() ) | |
520 return false; | |
521 return true; | |
522 } | |
523 return false; | |
524 } | |
525 | |
3892 | 526 bool use_block_zeroing(Node* count) { |
527 // Use BIS for zeroing if count is not constant | |
528 // or it is >= BlockZeroingLowLimit. | |
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit); | |
530 } | |
531 | |
0 | 532 // **************************************************************************** |
533 | |
534 // REQUIRED FUNCTIONALITY | |
535 | |
536 // !!!!! Special hack to get all type of calls to specify the byte offset | |
537 // from the start of the call to the point where the return address | |
538 // will point. | |
539 // The "return address" is the address of the call instruction, plus 8. | |
540 | |
541 int MachCallStaticJavaNode::ret_addr_offset() { | |
1567 | 542 int offset = NativeCall::instruction_size; // call; delay slot |
543 if (_method_handle_invoke) | |
544 offset += 4; // restore SP | |
545 return offset; | |
0 | 546 } |
547 | |
548 int MachCallDynamicJavaNode::ret_addr_offset() { | |
549 int vtable_index = this->_vtable_index; | |
550 if (vtable_index < 0) { | |
551 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
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552 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
0 | 553 return (NativeMovConstReg::instruction_size + |
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
555 } else { | |
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
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557 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
0 | 558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); |
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559 int klass_load_size; |
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560 if (UseCompressedClassPointers) { |
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561 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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562 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; |
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563 } else { |
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564 klass_load_size = 1*BytesPerInstWord; |
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565 } |
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566 if (Assembler::is_simm13(v_off)) { |
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567 return klass_load_size + |
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568 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
0 | 569 NativeCall::instruction_size); // call; delay slot |
570 } else { | |
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571 return klass_load_size + |
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572 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
0 | 573 NativeCall::instruction_size); // call; delay slot |
574 } | |
575 } | |
576 } | |
577 | |
578 int MachCallRuntimeNode::ret_addr_offset() { | |
579 #ifdef _LP64 | |
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580 if (MacroAssembler::is_far_target(entry_point())) { |
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581 return NativeFarCall::instruction_size; |
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582 } else { |
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583 return NativeCall::instruction_size; |
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584 } |
0 | 585 #else |
586 return NativeCall::instruction_size; // call; delay slot | |
587 #endif | |
588 } | |
589 | |
590 // Indicate if the safepoint node needs the polling page as an input. | |
591 // Since Sparc does not have absolute addressing, it does. | |
592 bool SafePointNode::needs_polling_address_input() { | |
593 return true; | |
594 } | |
595 | |
596 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
597 void emit_break(CodeBuffer &cbuf) { | |
598 MacroAssembler _masm(&cbuf); | |
599 __ breakpoint_trap(); | |
600 } | |
601 | |
602 #ifndef PRODUCT | |
603 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
604 st->print("TA"); | |
605 } | |
606 #endif | |
607 | |
608 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
609 emit_break(cbuf); | |
610 } | |
611 | |
612 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
613 return MachNode::size(ra_); | |
614 } | |
615 | |
616 // Traceable jump | |
617 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
618 MacroAssembler _masm(&cbuf); | |
619 Register rdest = reg_to_register_object(jump_target); | |
620 __ JMP(rdest, 0); | |
621 __ delayed()->nop(); | |
622 } | |
623 | |
624 // Traceable jump and set exception pc | |
625 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
626 MacroAssembler _masm(&cbuf); | |
627 Register rdest = reg_to_register_object(jump_target); | |
628 __ JMP(rdest, 0); | |
629 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
630 } | |
631 | |
632 void emit_nop(CodeBuffer &cbuf) { | |
633 MacroAssembler _masm(&cbuf); | |
634 __ nop(); | |
635 } | |
636 | |
637 void emit_illtrap(CodeBuffer &cbuf) { | |
638 MacroAssembler _masm(&cbuf); | |
639 __ illtrap(0); | |
640 } | |
641 | |
642 | |
643 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
644 assert(n->rule() != loadUB_rule, ""); | |
645 | |
646 intptr_t offset = 0; | |
647 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
648 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
649 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
650 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
651 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
652 atype = atype->add_offset(offset); | |
653 assert(disp32 == offset, "wrong disp32"); | |
654 return atype->_offset; | |
655 } | |
656 | |
657 | |
658 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
659 assert(n->rule() != loadUB_rule, ""); | |
660 | |
661 intptr_t offset = 0; | |
662 Node* addr = n->in(2); | |
663 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
664 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
665 Node* a = addr->in(2/*AddPNode::Address*/); | |
666 Node* o = addr->in(3/*AddPNode::Offset*/); | |
667 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
668 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
669 assert(atype->isa_oop_ptr(), "still an oop"); | |
670 } | |
671 offset = atype->is_ptr()->_offset; | |
672 if (offset != Type::OffsetBot) offset += disp32; | |
673 return offset; | |
674 } | |
675 | |
2008 | 676 static inline jdouble replicate_immI(int con, int count, int width) { |
677 // Load a constant replicated "count" times with width "width" | |
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678 assert(count*width == 8 && width <= 4, "sanity"); |
2008 | 679 int bit_width = width * 8; |
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680 jlong val = con; |
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681 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits |
2008 | 682 for (int i = 0; i < count - 1; i++) { |
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683 val |= (val << bit_width); |
2008 | 684 } |
685 jdouble dval = *((jdouble*) &val); // coerce to double type | |
686 return dval; | |
687 } | |
688 | |
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689 static inline jdouble replicate_immF(float con) { |
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690 // Replicate float con 2 times and pack into vector. |
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691 int val = *((int*)&con); |
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692 jlong lval = val; |
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693 lval = (lval << 32) | (lval & 0xFFFFFFFFl); |
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694 jdouble dval = *((jdouble*) &lval); // coerce to double type |
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695 return dval; |
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696 } |
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697 |
0 | 698 // Standard Sparc opcode form2 field breakdown |
699 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
700 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
701 int op = (f30 << 30) | | |
702 (f29 << 29) | | |
703 (f25 << 25) | | |
704 (f22 << 22) | | |
705 (f20 << 20) | | |
706 (f19 << 19) | | |
707 (f0 << 0); | |
1748 | 708 cbuf.insts()->emit_int32(op); |
0 | 709 } |
710 | |
711 // Standard Sparc opcode form2 field breakdown | |
712 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
713 f0 >>= 10; // Drop 10 bits | |
714 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
715 int op = (f30 << 30) | | |
716 (f25 << 25) | | |
717 (f22 << 22) | | |
718 (f0 << 0); | |
1748 | 719 cbuf.insts()->emit_int32(op); |
0 | 720 } |
721 | |
722 // Standard Sparc opcode form3 field breakdown | |
723 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
724 int op = (f30 << 30) | | |
725 (f25 << 25) | | |
726 (f19 << 19) | | |
727 (f14 << 14) | | |
728 (f5 << 5) | | |
729 (f0 << 0); | |
1748 | 730 cbuf.insts()->emit_int32(op); |
0 | 731 } |
732 | |
733 // Standard Sparc opcode form3 field breakdown | |
734 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
735 simm13 &= (1<<13)-1; // Mask to 13 bits | |
736 int op = (f30 << 30) | | |
737 (f25 << 25) | | |
738 (f19 << 19) | | |
739 (f14 << 14) | | |
740 (1 << 13) | // bit to indicate immediate-mode | |
741 (simm13<<0); | |
1748 | 742 cbuf.insts()->emit_int32(op); |
0 | 743 } |
744 | |
745 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
746 simm10 &= (1<<10)-1; // Mask to 10 bits | |
747 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
748 } | |
749 | |
750 #ifdef ASSERT | |
751 // Helper function for VerifyOops in emit_form3_mem_reg | |
752 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
753 warning("VerifyOops encountered unexpected instruction:"); | |
754 n->dump(2); | |
755 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
756 } | |
757 #endif | |
758 | |
759 | |
760 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
761 int src1_enc, int disp32, int src2_enc, int dst_enc) { | |
762 | |
763 #ifdef ASSERT | |
764 // The following code implements the +VerifyOops feature. | |
765 // It verifies oop values which are loaded into or stored out of | |
766 // the current method activation. +VerifyOops complements techniques | |
767 // like ScavengeALot, because it eagerly inspects oops in transit, | |
768 // as they enter or leave the stack, as opposed to ScavengeALot, | |
769 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
770 // For this reason, +VerifyOops can sometimes detect bugs very close | |
771 // to their point of creation. It can also serve as a cross-check | |
772 // on the validity of oop maps, when used toegether with ScavengeALot. | |
773 | |
774 // It would be good to verify oops at other points, especially | |
775 // when an oop is used as a base pointer for a load or store. | |
776 // This is presently difficult, because it is hard to know when | |
777 // a base address is biased or not. (If we had such information, | |
778 // it would be easy and useful to make a two-argument version of | |
779 // verify_oop which unbiases the base, and performs verification.) | |
780 | |
781 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
782 bool is_verified_oop_base = false; | |
783 bool is_verified_oop_load = false; | |
784 bool is_verified_oop_store = false; | |
785 int tmp_enc = -1; | |
786 if (VerifyOops && src1_enc != R_SP_enc) { | |
787 // classify the op, mainly for an assert check | |
788 int st_op = 0, ld_op = 0; | |
789 switch (primary) { | |
790 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
791 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
792 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
793 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
794 case Assembler::std_op3: st_op = Op_StoreL; break; | |
795 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
796 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
797 | |
798 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
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799 case Assembler::ldub_op3: ld_op = Op_LoadUB; break; |
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800 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
0 | 801 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
802 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
803 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
804 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
805 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
806 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
807 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
808 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
809 | |
810 default: ShouldNotReachHere(); | |
811 } | |
812 if (tertiary == REGP_OP) { | |
813 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
814 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
815 else ShouldNotReachHere(); | |
816 if (st_op) { | |
817 // a store | |
818 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
819 Node* n2 = n->in(3); | |
820 if (n2 != NULL) { | |
821 const Type* t = n2->bottom_type(); | |
822 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
823 } | |
824 } else { | |
825 // a load | |
826 const Type* t = n->bottom_type(); | |
827 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
828 } | |
829 } | |
830 | |
831 if (ld_op) { | |
832 // a Load | |
833 // inputs are (0:control, 1:memory, 2:address) | |
834 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
835 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
836 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
837 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
838 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
839 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
840 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
841 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
842 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
843 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
844 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
845 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
846 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
3898 | 847 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) && |
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848 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) && |
0 | 849 !(n->rule() == loadUB_rule)) { |
850 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
851 } | |
852 } else if (st_op) { | |
853 // a Store | |
854 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
855 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
856 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
857 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
858 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
859 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
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860 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) && |
0 | 861 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { |
862 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
863 } | |
864 } | |
865 | |
866 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
867 Node* addr = n->in(2); | |
868 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
869 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
870 if (atype != NULL) { | |
871 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
872 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
873 if (offset != offset_2) { | |
874 get_offset_from_base(n, atype, disp32); | |
875 get_offset_from_base_2(n, atype, disp32); | |
876 } | |
877 assert(offset == offset_2, "different offsets"); | |
878 if (offset == disp32) { | |
879 // we now know that src1 is a true oop pointer | |
880 is_verified_oop_base = true; | |
881 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
882 if( primary == Assembler::ldd_op3 ) { | |
883 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
884 } else { | |
885 tmp_enc = dst_enc; | |
886 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
887 assert(src1_enc != dst_enc, ""); | |
888 } | |
889 } | |
890 } | |
891 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
892 || offset == oopDesc::mark_offset_in_bytes())) { | |
893 // loading the mark should not be allowed either, but | |
894 // we don't check this since it conflicts with InlineObjectHash | |
895 // usage of LoadINode to get the mark. We could keep the | |
896 // check if we create a new LoadMarkNode | |
897 // but do not verify the object before its header is initialized | |
898 ShouldNotReachHere(); | |
899 } | |
900 } | |
901 } | |
902 } | |
903 } | |
904 #endif | |
905 | |
906 uint instr; | |
907 instr = (Assembler::ldst_op << 30) | |
908 | (dst_enc << 25) | |
909 | (primary << 19) | |
910 | (src1_enc << 14); | |
911 | |
912 uint index = src2_enc; | |
913 int disp = disp32; | |
914 | |
915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
916 disp += STACK_BIAS; | |
917 | |
918 // We should have a compiler bailout here rather than a guarantee. | |
919 // Better yet would be some mechanism to handle variable-size matches correctly. | |
920 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
921 | |
922 if( disp == 0 ) { | |
923 // use reg-reg form | |
924 // bit 13 is already zero | |
925 instr |= index; | |
926 } else { | |
927 // use reg-imm form | |
928 instr |= 0x00002000; // set bit 13 to one | |
929 instr |= disp & 0x1FFF; | |
930 } | |
931 | |
1748 | 932 cbuf.insts()->emit_int32(instr); |
0 | 933 |
934 #ifdef ASSERT | |
935 { | |
936 MacroAssembler _masm(&cbuf); | |
937 if (is_verified_oop_base) { | |
938 __ verify_oop(reg_to_register_object(src1_enc)); | |
939 } | |
940 if (is_verified_oop_store) { | |
941 __ verify_oop(reg_to_register_object(dst_enc)); | |
942 } | |
943 if (tmp_enc != -1) { | |
944 __ mov(O7, reg_to_register_object(tmp_enc)); | |
945 } | |
946 if (is_verified_oop_load) { | |
947 __ verify_oop(reg_to_register_object(dst_enc)); | |
948 } | |
949 } | |
950 #endif | |
951 } | |
952 | |
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953 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) { |
0 | 954 // The method which records debug information at every safepoint |
955 // expects the call to be the first instruction in the snippet as | |
956 // it creates a PcDesc structure which tracks the offset of a call | |
957 // from the start of the codeBlob. This offset is computed as | |
958 // code_end() - code_begin() of the code which has been emitted | |
959 // so far. | |
960 // In this particular case we have skirted around the problem by | |
961 // putting the "mov" instruction in the delay slot but the problem | |
962 // may bite us again at some other point and a cleaner/generic | |
963 // solution using relocations would be needed. | |
964 MacroAssembler _masm(&cbuf); | |
965 __ set_inst_mark(); | |
966 | |
967 // We flush the current window just so that there is a valid stack copy | |
968 // the fact that the current window becomes active again instantly is | |
969 // not a problem there is nothing live in it. | |
970 | |
971 #ifdef ASSERT | |
972 int startpos = __ offset(); | |
973 #endif /* ASSERT */ | |
974 | |
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975 __ call((address)entry_point, rtype); |
0 | 976 |
977 if (preserve_g2) __ delayed()->mov(G2, L7); | |
978 else __ delayed()->nop(); | |
979 | |
980 if (preserve_g2) __ mov(L7, G2); | |
981 | |
982 #ifdef ASSERT | |
983 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
984 #ifdef _LP64 | |
985 // Trash argument dump slots. | |
986 __ set(0xb0b8ac0db0b8ac0d, G1); | |
987 __ mov(G1, G5); | |
988 __ stx(G1, SP, STACK_BIAS + 0x80); | |
989 __ stx(G1, SP, STACK_BIAS + 0x88); | |
990 __ stx(G1, SP, STACK_BIAS + 0x90); | |
991 __ stx(G1, SP, STACK_BIAS + 0x98); | |
992 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
993 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
994 #else // _LP64 | |
995 // this is also a native call, so smash the first 7 stack locations, | |
996 // and the various registers | |
997 | |
998 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
999 // while [SP+0x44..0x58] are the argument dump slots. | |
1000 __ set((intptr_t)0xbaadf00d, G1); | |
1001 __ mov(G1, G5); | |
1002 __ sllx(G1, 32, G1); | |
1003 __ or3(G1, G5, G1); | |
1004 __ mov(G1, G5); | |
1005 __ stx(G1, SP, 0x40); | |
1006 __ stx(G1, SP, 0x48); | |
1007 __ stx(G1, SP, 0x50); | |
1008 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
1009 #endif // _LP64 | |
1010 } | |
1011 #endif /*ASSERT*/ | |
1012 } | |
1013 | |
1014 //============================================================================= | |
1015 // REQUIRED FUNCTIONALITY for encoding | |
1016 void emit_lo(CodeBuffer &cbuf, int val) { } | |
1017 void emit_hi(CodeBuffer &cbuf, int val) { } | |
1018 | |
1019 | |
1020 //============================================================================= | |
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1021 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask(); |
2008 | 1022 |
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1023 int Compile::ConstantTable::calculate_table_base_offset() const { |
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1024 if (UseRDPCForConstantTableBase) { |
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1025 // The table base offset might be less but then it fits into |
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1026 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit). |
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1027 return Assembler::min_simm13(); |
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1028 } else { |
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1029 int offset = -(size() / 2); |
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1030 if (!Assembler::is_simm13(offset)) { |
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1031 offset = Assembler::min_simm13(); |
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1032 } |
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1033 return offset; |
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1034 } |
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1035 } |
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1036 |
2008 | 1037 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
1038 Compile* C = ra_->C; | |
1039 Compile::ConstantTable& constant_table = C->constant_table(); | |
1040 MacroAssembler _masm(&cbuf); | |
1041 | |
1042 Register r = as_Register(ra_->get_encode(this)); | |
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1043 CodeSection* consts_section = __ code()->consts(); |
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1044 int consts_size = consts_section->align_at_start(consts_section->size()); |
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1045 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); |
2008 | 1046 |
1047 if (UseRDPCForConstantTableBase) { | |
1048 // For the following RDPC logic to work correctly the consts | |
1049 // section must be allocated right before the insts section. This | |
1050 // assert checks for that. The layout and the SECT_* constants | |
1051 // are defined in src/share/vm/asm/codeBuffer.hpp. | |
1052 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); | |
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1053 int insts_offset = __ offset(); |
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1054 |
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1055 // Layout: |
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1056 // |
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1057 // |----------- consts section ------------|----------- insts section -----------... |
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1058 // |------ constant table -----|- padding -|------------------x---- |
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1059 // \ current PC (RDPC instruction) |
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1060 // |<------------- consts_size ----------->|<- insts_offset ->| |
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1061 // \ table base |
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1062 // The table base offset is later added to the load displacement |
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1063 // so it has to be negative. |
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1064 int table_base_offset = -(consts_size + insts_offset); |
2008 | 1065 int disp; |
1066 | |
1067 // If the displacement from the current PC to the constant table | |
1068 // base fits into simm13 we set the constant table base to the | |
1069 // current PC. | |
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1070 if (Assembler::is_simm13(table_base_offset)) { |
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1071 constant_table.set_table_base_offset(table_base_offset); |
2008 | 1072 disp = 0; |
1073 } else { | |
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1074 // Otherwise we set the constant table base offset to the |
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1075 // maximum negative displacement of load instructions to keep |
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1076 // the disp as small as possible: |
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1077 // |
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1078 // |<------------- consts_size ----------->|<- insts_offset ->| |
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1079 // |<--------- min_simm13 --------->|<-------- disp --------->| |
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1080 // \ table base |
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1081 table_base_offset = Assembler::min_simm13(); |
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1082 constant_table.set_table_base_offset(table_base_offset); |
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1083 disp = (consts_size + insts_offset) + table_base_offset; |
2008 | 1084 } |
1085 | |
1086 __ rdpc(r); | |
1087 | |
1088 if (disp != 0) { | |
1089 assert(r != O7, "need temporary"); | |
1090 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); | |
1091 } | |
1092 } | |
1093 else { | |
1094 // Materialize the constant table base. | |
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1095 address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); |
2008 | 1096 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); |
1097 AddressLiteral base(baseaddr, rspec); | |
1098 __ set(base, r); | |
1099 } | |
1100 } | |
1101 | |
1102 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { | |
1103 if (UseRDPCForConstantTableBase) { | |
1104 // This is really the worst case but generally it's only 1 instruction. | |
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1105 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; |
2008 | 1106 } else { |
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1107 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; |
2008 | 1108 } |
1109 } | |
1110 | |
1111 #ifndef PRODUCT | |
1112 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
1113 char reg[128]; | |
1114 ra_->dump_register(this, reg); | |
1115 if (UseRDPCForConstantTableBase) { | |
1116 st->print("RDPC %s\t! constant table base", reg); | |
1117 } else { | |
1118 st->print("SET &constanttable,%s\t! constant table base", reg); | |
1119 } | |
1120 } | |
1121 #endif | |
1122 | |
1123 | |
1124 //============================================================================= | |
0 | 1125 |
1126 #ifndef PRODUCT | |
1127 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1128 Compile* C = ra_->C; | |
1129 | |
1130 for (int i = 0; i < OptoPrologueNops; i++) { | |
1131 st->print_cr("NOP"); st->print("\t"); | |
1132 } | |
1133 | |
1134 if( VerifyThread ) { | |
1135 st->print_cr("Verify_Thread"); st->print("\t"); | |
1136 } | |
1137 | |
1138 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
1139 | |
1140 // Calls to C2R adapters often do not accept exceptional returns. | |
1141 // We require that their callers must bang for them. But be careful, because | |
1142 // some VM calls (such as call site linkage) can use several kilobytes of | |
1143 // stack. But the stack safety zone should account for that. | |
1144 // See bugs 4446381, 4468289, 4497237. | |
1145 if (C->need_stack_bang(framesize)) { | |
1146 st->print_cr("! stack bang"); st->print("\t"); | |
1147 } | |
1148 | |
1149 if (Assembler::is_simm13(-framesize)) { | |
1150 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
1151 } else { | |
1152 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
1153 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
1154 st->print ("SAVE R_SP,R_G3,R_SP"); | |
1155 } | |
1156 | |
1157 } | |
1158 #endif | |
1159 | |
1160 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1161 Compile* C = ra_->C; | |
1162 MacroAssembler _masm(&cbuf); | |
1163 | |
1164 for (int i = 0; i < OptoPrologueNops; i++) { | |
1165 __ nop(); | |
1166 } | |
1167 | |
1168 __ verify_thread(); | |
1169 | |
1170 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
1171 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
1172 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
1173 | |
1174 // Calls to C2R adapters often do not accept exceptional returns. | |
1175 // We require that their callers must bang for them. But be careful, because | |
1176 // some VM calls (such as call site linkage) can use several kilobytes of | |
1177 // stack. But the stack safety zone should account for that. | |
1178 // See bugs 4446381, 4468289, 4497237. | |
1179 if (C->need_stack_bang(framesize)) { | |
1180 __ generate_stack_overflow_check(framesize); | |
1181 } | |
1182 | |
1183 if (Assembler::is_simm13(-framesize)) { | |
1184 __ save(SP, -framesize, SP); | |
1185 } else { | |
1186 __ sethi(-framesize & ~0x3ff, G3); | |
1187 __ add(G3, -framesize & 0x3ff, G3); | |
1188 __ save(SP, G3, SP); | |
1189 } | |
1190 C->set_frame_complete( __ offset() ); | |
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1191 |
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1192 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) { |
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1193 // NOTE: We set the table base offset here because users might be |
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1194 // emitted before MachConstantBaseNode. |
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1195 Compile::ConstantTable& constant_table = C->constant_table(); |
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1196 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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1197 } |
0 | 1198 } |
1199 | |
1200 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
1201 return MachNode::size(ra_); | |
1202 } | |
1203 | |
1204 int MachPrologNode::reloc() const { | |
1205 return 10; // a large enough number | |
1206 } | |
1207 | |
1208 //============================================================================= | |
1209 #ifndef PRODUCT | |
1210 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1211 Compile* C = ra_->C; | |
1212 | |
1213 if( do_polling() && ra_->C->is_method_compilation() ) { | |
1214 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
1215 #ifdef _LP64 | |
1216 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
1217 #else | |
1218 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
1219 #endif | |
1220 } | |
1221 | |
1222 if( do_polling() ) | |
1223 st->print("RET\n\t"); | |
1224 | |
1225 st->print("RESTORE"); | |
1226 } | |
1227 #endif | |
1228 | |
1229 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1230 MacroAssembler _masm(&cbuf); | |
1231 Compile* C = ra_->C; | |
1232 | |
1233 __ verify_thread(); | |
1234 | |
1235 // If this does safepoint polling, then do it here | |
1236 if( do_polling() && ra_->C->is_method_compilation() ) { | |
727 | 1237 AddressLiteral polling_page(os::get_polling_page()); |
1238 __ sethi(polling_page, L0); | |
0 | 1239 __ relocate(relocInfo::poll_return_type); |
1240 __ ld_ptr( L0, 0, G0 ); | |
1241 } | |
1242 | |
1243 // If this is a return, then stuff the restore in the delay slot | |
1244 if( do_polling() ) { | |
1245 __ ret(); | |
1246 __ delayed()->restore(); | |
1247 } else { | |
1248 __ restore(); | |
1249 } | |
1250 } | |
1251 | |
1252 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
1253 return MachNode::size(ra_); | |
1254 } | |
1255 | |
1256 int MachEpilogNode::reloc() const { | |
1257 return 16; // a large enough number | |
1258 } | |
1259 | |
1260 const Pipeline * MachEpilogNode::pipeline() const { | |
1261 return MachNode::pipeline_class(); | |
1262 } | |
1263 | |
1264 int MachEpilogNode::safepoint_offset() const { | |
1265 assert( do_polling(), "no return for this epilog node"); | |
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1266 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; |
0 | 1267 } |
1268 | |
1269 //============================================================================= | |
1270 | |
1271 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
1272 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
1273 static enum RC rc_class( OptoReg::Name reg ) { | |
1274 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
1275 if (OptoReg::is_stack(reg)) return rc_stack; | |
1276 VMReg r = OptoReg::as_VMReg(reg); | |
1277 if (r->is_Register()) return rc_int; | |
1278 assert(r->is_FloatRegister(), "must be"); | |
1279 return rc_float; | |
1280 } | |
1281 | |
1282 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { | |
1283 if( cbuf ) { | |
1284 // Better yet would be some mechanism to handle variable-size matches correctly | |
1285 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
1286 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
1287 } else { | |
1288 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
1289 } | |
1290 } | |
1291 #ifndef PRODUCT | |
1292 else if( !do_size ) { | |
1293 if( size != 0 ) st->print("\n\t"); | |
1294 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | |
1295 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | |
1296 } | |
1297 #endif | |
1298 return size+4; | |
1299 } | |
1300 | |
1301 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
1302 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
1303 #ifndef PRODUCT | |
1304 else if( !do_size ) { | |
1305 if( size != 0 ) st->print("\n\t"); | |
1306 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
1307 } | |
1308 #endif | |
1309 return size+4; | |
1310 } | |
1311 | |
1312 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
1313 PhaseRegAlloc *ra_, | |
1314 bool do_size, | |
1315 outputStream* st ) const { | |
1316 // Get registers to move | |
1317 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
1318 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
1319 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
1320 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
1321 | |
1322 enum RC src_second_rc = rc_class(src_second); | |
1323 enum RC src_first_rc = rc_class(src_first); | |
1324 enum RC dst_second_rc = rc_class(dst_second); | |
1325 enum RC dst_first_rc = rc_class(dst_first); | |
1326 | |
1327 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
1328 | |
1329 // Generate spill code! | |
1330 int size = 0; | |
1331 | |
1332 if( src_first == dst_first && src_second == dst_second ) | |
1333 return size; // Self copy, no move | |
1334 | |
1335 // -------------------------------------- | |
1336 // Check for mem-mem move. Load into unused float registers and fall into | |
1337 // the float-store case. | |
1338 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
1339 int offset = ra_->reg2offset(src_first); | |
1340 // Further check for aligned-adjacent pair, so we can use a double load | |
1341 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
1342 src_second = OptoReg::Name(R_F31_num); | |
1343 src_second_rc = rc_float; | |
1344 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
1345 } else { | |
1346 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
1347 } | |
1348 src_first = OptoReg::Name(R_F30_num); | |
1349 src_first_rc = rc_float; | |
1350 } | |
1351 | |
1352 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
1353 int offset = ra_->reg2offset(src_second); | |
1354 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
1355 src_second = OptoReg::Name(R_F31_num); | |
1356 src_second_rc = rc_float; | |
1357 } | |
1358 | |
1359 // -------------------------------------- | |
1360 // Check for float->int copy; requires a trip through memory | |
3804 | 1361 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { |
0 | 1362 int offset = frame::register_save_words*wordSize; |
3804 | 1363 if (cbuf) { |
0 | 1364 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); |
1365 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1366 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1367 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
1368 } | |
1369 #ifndef PRODUCT | |
3804 | 1370 else if (!do_size) { |
1371 if (size != 0) st->print("\n\t"); | |
0 | 1372 st->print( "SUB R_SP,16,R_SP\n"); |
1373 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1374 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1375 st->print("\tADD R_SP,16,R_SP\n"); | |
1376 } | |
1377 #endif | |
1378 size += 16; | |
1379 } | |
1380 | |
3804 | 1381 // Check for float->int copy on T4 |
1382 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { | |
1383 // Further check for aligned-adjacent pair, so we can use a double move | |
1384 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
1385 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st); | |
1386 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st); | |
1387 } | |
1388 // Check for int->float copy on T4 | |
1389 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { | |
1390 // Further check for aligned-adjacent pair, so we can use a double move | |
1391 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
1392 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st); | |
1393 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st); | |
1394 } | |
1395 | |
0 | 1396 // -------------------------------------- |
1397 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
1398 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
1399 // hardware does the flop for me. Doubles are always aligned, so no problem | |
1400 // there. Misaligned sources only come from native-long-returns (handled | |
1401 // special below). | |
1402 #ifndef _LP64 | |
1403 if( src_first_rc == rc_int && // source is already big-endian | |
1404 src_second_rc != rc_bad && // 64-bit move | |
1405 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
1406 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
1407 // Do the big-endian flop. | |
1408 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
1409 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
1410 } | |
1411 #endif | |
1412 | |
1413 // -------------------------------------- | |
1414 // Check for integer reg-reg copy | |
1415 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
1416 #ifndef _LP64 | |
1417 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
1418 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1419 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1420 // operand contains the least significant word of the 64-bit value and vice versa. | |
1421 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
1422 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
1423 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
1424 if( cbuf ) { | |
1425 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
1426 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
1427 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
1428 #ifndef PRODUCT | |
1429 } else if( !do_size ) { | |
1430 if( size != 0 ) st->print("\n\t"); | |
1431 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
1432 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
1433 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
1434 #endif | |
1435 } | |
1436 return size+12; | |
1437 } | |
1438 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
1439 // returning a long value in I0/I1 | |
1440 // a SpillCopy must be able to target a return instruction's reg_class | |
1441 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1442 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1443 // operand contains the least significant word of the 64-bit value and vice versa. | |
1444 OptoReg::Name tdest = dst_first; | |
1445 | |
1446 if (src_first == dst_first) { | |
1447 tdest = OptoReg::Name(R_O7_num); | |
1448 size += 4; | |
1449 } | |
1450 | |
1451 if( cbuf ) { | |
1452 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
1453 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
1454 // ShrL_reg_imm6 | |
1455 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
1456 // ShrR_reg_imm6 src, 0, dst | |
1457 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
1458 if (tdest != dst_first) { | |
1459 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
1460 } | |
1461 } | |
1462 #ifndef PRODUCT | |
1463 else if( !do_size ) { | |
1464 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
1465 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
1466 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
1467 if (tdest != dst_first) { | |
1468 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
1469 } | |
1470 } | |
1471 #endif // PRODUCT | |
1472 return size+8; | |
1473 } | |
1474 #endif // !_LP64 | |
1475 // Else normal reg-reg copy | |
1476 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
1477 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
1478 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
1479 // This moves an aligned adjacent pair. | |
1480 // See if we are done. | |
1481 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
1482 return size; | |
1483 } | |
1484 | |
1485 // Check for integer store | |
1486 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
1487 int offset = ra_->reg2offset(dst_first); | |
1488 // Further check for aligned-adjacent pair, so we can use a double store | |
1489 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1490 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
1491 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
1492 } | |
1493 | |
1494 // Check for integer load | |
1495 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
1496 int offset = ra_->reg2offset(src_first); | |
1497 // Further check for aligned-adjacent pair, so we can use a double load | |
1498 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1499 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
1500 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1501 } | |
1502 | |
1503 // Check for float reg-reg copy | |
1504 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
1505 // Further check for aligned-adjacent pair, so we can use a double move | |
1506 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1507 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
1508 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
1509 } | |
1510 | |
1511 // Check for float store | |
1512 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
1513 int offset = ra_->reg2offset(dst_first); | |
1514 // Further check for aligned-adjacent pair, so we can use a double store | |
1515 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1516 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
1517 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1518 } | |
1519 | |
1520 // Check for float load | |
1521 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
1522 int offset = ra_->reg2offset(src_first); | |
1523 // Further check for aligned-adjacent pair, so we can use a double load | |
1524 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1525 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
1526 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
1527 } | |
1528 | |
1529 // -------------------------------------------------------------------- | |
1530 // Check for hi bits still needing moving. Only happens for misaligned | |
1531 // arguments to native calls. | |
1532 if( src_second == dst_second ) | |
1533 return size; // Self copy; no move | |
1534 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
1535 | |
1536 #ifndef _LP64 | |
1537 // In the LP64 build, all registers can be moved as aligned/adjacent | |
605 | 1538 // pairs, so there's never any need to move the high bits separately. |
0 | 1539 // The 32-bit builds have to deal with the 32-bit ABI which can force |
1540 // all sorts of silly alignment problems. | |
1541 | |
1542 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
1543 // 32-bits of a 64-bit register, but are needed in low bits of another | |
1544 // register (else it's a hi-bits-to-hi-bits copy which should have | |
1545 // happened already as part of a 64-bit move) | |
1546 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
1547 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
1548 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
1549 // Shift src_second down to dst_second's low bits. | |
1550 if( cbuf ) { | |
1551 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1552 #ifndef PRODUCT | |
1553 } else if( !do_size ) { | |
1554 if( size != 0 ) st->print("\n\t"); | |
1555 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
1556 #endif | |
1557 } | |
1558 return size+4; | |
1559 } | |
1560 | |
1561 // Check for high word integer store. Must down-shift the hi bits | |
1562 // into a temp register, then fall into the case of storing int bits. | |
1563 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
1564 // Shift src_second down to dst_second's low bits. | |
1565 if( cbuf ) { | |
1566 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1567 #ifndef PRODUCT | |
1568 } else if( !do_size ) { | |
1569 if( size != 0 ) st->print("\n\t"); | |
1570 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
1571 #endif | |
1572 } | |
1573 size+=4; | |
1574 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
1575 } | |
1576 | |
1577 // Check for high word integer load | |
1578 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
1579 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
1580 | |
1581 // Check for high word integer store | |
1582 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
1583 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
1584 | |
1585 // Check for high word float store | |
1586 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
1587 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
1588 | |
1589 #endif // !_LP64 | |
1590 | |
1591 Unimplemented(); | |
1592 } | |
1593 | |
1594 #ifndef PRODUCT | |
1595 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1596 implementation( NULL, ra_, false, st ); | |
1597 } | |
1598 #endif | |
1599 | |
1600 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1601 implementation( &cbuf, ra_, false, NULL ); | |
1602 } | |
1603 | |
1604 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
1605 return implementation( NULL, ra_, true, NULL ); | |
1606 } | |
1607 | |
1608 //============================================================================= | |
1609 #ifndef PRODUCT | |
1610 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
1611 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
1612 } | |
1613 #endif | |
1614 | |
1615 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
1616 MacroAssembler _masm(&cbuf); | |
1617 for(int i = 0; i < _count; i += 1) { | |
1618 __ nop(); | |
1619 } | |
1620 } | |
1621 | |
1622 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
1623 return 4 * _count; | |
1624 } | |
1625 | |
1626 | |
1627 //============================================================================= | |
1628 #ifndef PRODUCT | |
1629 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1630 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
1631 int reg = ra_->get_reg_first(this); | |
1632 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
1633 } | |
1634 #endif | |
1635 | |
1636 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1637 MacroAssembler _masm(&cbuf); | |
1638 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
1639 int reg = ra_->get_encode(this); | |
1640 | |
1641 if (Assembler::is_simm13(offset)) { | |
1642 __ add(SP, offset, reg_to_register_object(reg)); | |
1643 } else { | |
1644 __ set(offset, O7); | |
1645 __ add(SP, O7, reg_to_register_object(reg)); | |
1646 } | |
1647 } | |
1648 | |
1649 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
1650 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
1651 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
1652 return ra_->C->scratch_emit_size(this); | |
1653 } | |
1654 | |
1655 //============================================================================= | |
1656 #ifndef PRODUCT | |
1657 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1658 st->print_cr("\nUEP:"); | |
1659 #ifdef _LP64 | |
12226
7944aba7ba41
8015107: NPG: Use consistent naming for metaspace concepts
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parents:
12056
diff
changeset
|
1660 if (UseCompressedClassPointers) { |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
1661 assert(Universe::heap() != NULL, "java heap should be initialized"); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1662 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
12056
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
10997
diff
changeset
|
1663 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base"); |
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
10997
diff
changeset
|
1664 if (Universe::narrow_klass_shift() != 0) { |
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
10997
diff
changeset
|
1665 st->print_cr("\tSLL R_G5,3,R_G5"); |
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
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diff
changeset
|
1666 } |
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1667 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
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1668 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base"); |
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1669 } else { |
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1670 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
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1671 } |
0 | 1672 st->print_cr("\tCMP R_G5,R_G3" ); |
1673 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1674 #else // _LP64 | |
1675 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
1676 st->print_cr("\tCMP R_G5,R_G3" ); | |
1677 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1678 #endif // _LP64 | |
1679 } | |
1680 #endif | |
1681 | |
1682 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1683 MacroAssembler _masm(&cbuf); | |
1684 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
1685 Register temp_reg = G3; | |
1686 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
1687 | |
605 | 1688 // Load klass from receiver |
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1689 __ load_klass(O0, temp_reg); |
0 | 1690 // Compare against expected klass |
1691 __ cmp(temp_reg, G5_ic_reg); | |
1692 // Branch to miss code, checks xcc or icc depending | |
1693 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
1694 } | |
1695 | |
1696 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
1697 return MachNode::size(ra_); | |
1698 } | |
1699 | |
1700 | |
1701 //============================================================================= | |
1702 | |
1703 uint size_exception_handler() { | |
1704 if (TraceJumps) { | |
1705 return (400); // just a guess | |
1706 } | |
1707 return ( NativeJump::instruction_size ); // sethi;jmp;nop | |
1708 } | |
1709 | |
1710 uint size_deopt_handler() { | |
1711 if (TraceJumps) { | |
1712 return (400); // just a guess | |
1713 } | |
1714 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore | |
1715 } | |
1716 | |
1717 // Emit exception handler code. | |
1718 int emit_exception_handler(CodeBuffer& cbuf) { | |
1719 Register temp_reg = G3; | |
1748 | 1720 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); |
0 | 1721 MacroAssembler _masm(&cbuf); |
1722 | |
1723 address base = | |
1724 __ start_a_stub(size_exception_handler()); | |
1725 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1726 | |
1727 int offset = __ offset(); | |
1728 | |
727 | 1729 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
0 | 1730 __ delayed()->nop(); |
1731 | |
1732 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
1733 | |
1734 __ end_a_stub(); | |
1735 | |
1736 return offset; | |
1737 } | |
1738 | |
1739 int emit_deopt_handler(CodeBuffer& cbuf) { | |
1740 // Can't use any of the current frame's registers as we may have deopted | |
1741 // at a poll and everything (including G3) can be live. | |
1742 Register temp_reg = L0; | |
727 | 1743 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
0 | 1744 MacroAssembler _masm(&cbuf); |
1745 | |
1746 address base = | |
1747 __ start_a_stub(size_deopt_handler()); | |
1748 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1749 | |
1750 int offset = __ offset(); | |
1751 __ save_frame(0); | |
727 | 1752 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
0 | 1753 __ delayed()->restore(); |
1754 | |
1755 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
1756 | |
1757 __ end_a_stub(); | |
1758 return offset; | |
1759 | |
1760 } | |
1761 | |
1762 // Given a register encoding, produce a Integer Register object | |
1763 static Register reg_to_register_object(int register_encoding) { | |
1764 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
1765 return as_Register(register_encoding); | |
1766 } | |
1767 | |
1768 // Given a register encoding, produce a single-precision Float Register object | |
1769 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
1770 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
1771 return as_SingleFloatRegister(register_encoding); | |
1772 } | |
1773 | |
1774 // Given a register encoding, produce a double-precision Float Register object | |
1775 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
1776 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
1777 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
1778 return as_DoubleFloatRegister(register_encoding); | |
1779 } | |
1780 | |
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1781 const bool Matcher::match_rule_supported(int opcode) { |
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1782 if (!has_match_rule(opcode)) |
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1783 return false; |
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1784 |
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1785 switch (opcode) { |
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1786 case Op_CountLeadingZerosI: |
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1787 case Op_CountLeadingZerosL: |
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1788 case Op_CountTrailingZerosI: |
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1789 case Op_CountTrailingZerosL: |
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1790 case Op_PopCountI: |
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1791 case Op_PopCountL: |
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1792 if (!UsePopCountInstruction) |
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1793 return false; |
6795
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1794 case Op_CompareAndSwapL: |
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1795 #ifdef _LP64 |
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1796 case Op_CompareAndSwapP: |
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1797 #endif |
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1798 if (!VM_Version::supports_cx8()) |
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1799 return false; |
775
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1800 break; |
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1801 } |
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1802 |
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1803 return true; // Per default match rules are supported. |
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1804 } |
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1805 |
0 | 1806 int Matcher::regnum_to_fpu_offset(int regnum) { |
1807 return regnum - 32; // The FP registers are in the second chunk | |
1808 } | |
1809 | |
1810 #ifdef ASSERT | |
1811 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
1812 #endif | |
1813 | |
1814 // Vector width in bytes | |
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1815 const int Matcher::vector_width_in_bytes(BasicType bt) { |
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1816 assert(MaxVectorSize == 8, ""); |
0 | 1817 return 8; |
1818 } | |
1819 | |
1820 // Vector ideal reg | |
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1821 const int Matcher::vector_ideal_reg(int size) { |
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1822 assert(MaxVectorSize == 8, ""); |
0 | 1823 return Op_RegD; |
1824 } | |
1825 | |
6823 | 1826 const int Matcher::vector_shift_count_ideal_reg(int size) { |
1827 fatal("vector shift is not supported"); | |
1828 return Node::NotAMachineReg; | |
1829 } | |
1830 | |
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1831 // Limits on vector size (number of elements) loaded into vector. |
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1832 const int Matcher::max_vector_size(const BasicType bt) { |
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1833 assert(is_java_primitive(bt), "only primitive type vectors"); |
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1834 return vector_width_in_bytes(bt)/type2aelembytes(bt); |
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1835 } |
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1836 |
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1837 const int Matcher::min_vector_size(const BasicType bt) { |
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1838 return max_vector_size(bt); // Same as max. |
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1839 } |
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1840 |
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1841 // SPARC doesn't support misaligned vectors store/load. |
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1842 const bool Matcher::misaligned_vectors_ok() { |
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1843 return false; |
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1844 } |
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1845 |
0 | 1846 // USII supports fxtof through the whole range of number, USIII doesn't |
1847 const bool Matcher::convL2FSupported(void) { | |
1848 return VM_Version::has_fast_fxtof(); | |
1849 } | |
1850 | |
1851 // Is this branch offset short enough that a short branch can be used? | |
1852 // | |
1853 // NOTE: If the platform does not provide any short branch variants, then | |
1854 // this method should return false for offset 0. | |
3851 | 1855 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
1856 // The passed offset is relative to address of the branch. | |
1857 // Don't need to adjust the offset. | |
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1858 return UseCBCond && Assembler::is_simm12(offset); |
0 | 1859 } |
1860 | |
1861 const bool Matcher::isSimpleConstant64(jlong value) { | |
1862 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
1863 // Depends on optimizations in MacroAssembler::setx. | |
1864 int hi = (int)(value >> 32); | |
1865 int lo = (int)(value & ~0); | |
1866 return (hi == 0) || (hi == -1) || (lo == 0); | |
1867 } | |
1868 | |
1869 // No scaling for the parameter the ClearArray node. | |
1870 const bool Matcher::init_array_count_is_in_bytes = true; | |
1871 | |
1872 // Threshold size for cleararray. | |
1873 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
1874 | |
4047 | 1875 // No additional cost for CMOVL. |
1876 const int Matcher::long_cmove_cost() { return 0; } | |
1877 | |
1878 // CMOVF/CMOVD are expensive on T4 and on SPARC64. | |
1879 const int Matcher::float_cmove_cost() { | |
1880 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; | |
1881 } | |
1882 | |
0 | 1883 // Should the Matcher clone shifts on addressing modes, expecting them to |
1884 // be subsumed into complex addressing expressions or compute them into | |
1885 // registers? True for Intel but false for most RISCs | |
1886 const bool Matcher::clone_shift_expressions = false; | |
1887 | |
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1888 // Do we need to mask the count passed to shift instructions or does |
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1889 // the cpu only look at the lower 5/6 bits anyway? |
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1890 const bool Matcher::need_masked_shift_count = false; |
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1891 |
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1892 bool Matcher::narrow_oop_use_complex_address() { |
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1893 NOT_LP64(ShouldNotCallThis()); |
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1894 assert(UseCompressedOops, "only for compressed oops code"); |
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1895 return false; |
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1896 } |
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1897 |
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1898 bool Matcher::narrow_klass_use_complex_address() { |
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1899 NOT_LP64(ShouldNotCallThis()); |
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1900 assert(UseCompressedClassPointers, "only for compressed klass code"); |
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1901 return false; |
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1902 } |
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1903 |
0 | 1904 // Is it better to copy float constants, or load them directly from memory? |
1905 // Intel can load a float constant from a direct address, requiring no | |
1906 // extra registers. Most RISCs will have to materialize an address into a | |
1907 // register first, so they would do better to copy the constant from stack. | |
1908 const bool Matcher::rematerialize_float_constants = false; | |
1909 | |
1910 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
1911 // needed. Else we split the double into 2 integer pieces and move it | |
1912 // piece-by-piece. Only happens when passing doubles into C code as the | |
1913 // Java calling convention forces doubles to be aligned. | |
1914 #ifdef _LP64 | |
1915 const bool Matcher::misaligned_doubles_ok = true; | |
1916 #else | |
1917 const bool Matcher::misaligned_doubles_ok = false; | |
1918 #endif | |
1919 | |
1920 // No-op on SPARC. | |
1921 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
1922 } | |
1923 | |
1924 // Advertise here if the CPU requires explicit rounding operations | |
1925 // to implement the UseStrictFP mode. | |
1926 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
1927 | |
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1928 // Are floats conerted to double when stored to stack during deoptimization? |
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1929 // Sparc does not handle callee-save floats. |
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1930 bool Matcher::float_in_double() { return false; } |
0 | 1931 |
1932 // Do ints take an entire long register or just half? | |
1933 // Note that we if-def off of _LP64. | |
1934 // The relevant question is how the int is callee-saved. In _LP64 | |
1935 // the whole long is written but de-opt'ing will have to extract | |
1936 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
1937 #ifdef _LP64 | |
1938 const bool Matcher::int_in_long = true; | |
1939 #else | |
1940 const bool Matcher::int_in_long = false; | |
1941 #endif | |
1942 | |
1943 // Return whether or not this register is ever used as an argument. This | |
1944 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
1945 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
1946 // arguments in those registers not be available to the callee. | |
1947 bool Matcher::can_be_java_arg( int reg ) { | |
1948 // Standard sparc 6 args in registers | |
1949 if( reg == R_I0_num || | |
1950 reg == R_I1_num || | |
1951 reg == R_I2_num || | |
1952 reg == R_I3_num || | |
1953 reg == R_I4_num || | |
1954 reg == R_I5_num ) return true; | |
1955 #ifdef _LP64 | |
1956 // 64-bit builds can pass 64-bit pointers and longs in | |
1957 // the high I registers | |
1958 if( reg == R_I0H_num || | |
1959 reg == R_I1H_num || | |
1960 reg == R_I2H_num || | |
1961 reg == R_I3H_num || | |
1962 reg == R_I4H_num || | |
1963 reg == R_I5H_num ) return true; | |
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1964 |
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1965 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
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1966 return true; |
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1967 } |
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1968 |
0 | 1969 #else |
1970 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
1971 // Longs cannot be passed in O regs, because O regs become I regs | |
1972 // after a 'save' and I regs get their high bits chopped off on | |
1973 // interrupt. | |
1974 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
1975 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
1976 #endif | |
1977 // A few float args in registers | |
1978 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
1979 | |
1980 return false; | |
1981 } | |
1982 | |
1983 bool Matcher::is_spillable_arg( int reg ) { | |
1984 return can_be_java_arg(reg); | |
1985 } | |
1986 | |
1914
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1987 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
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1988 // Use hardware SDIVX instruction when it is |
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1989 // faster than a code which use multiply. |
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1990 return VM_Version::has_fast_idiv(); |
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1991 } |
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1992 |
0 | 1993 // Register for DIVI projection of divmodI |
1994 RegMask Matcher::divI_proj_mask() { | |
1995 ShouldNotReachHere(); | |
1996 return RegMask(); | |
1997 } | |
1998 | |
1999 // Register for MODI projection of divmodI | |
2000 RegMask Matcher::modI_proj_mask() { | |
2001 ShouldNotReachHere(); | |
2002 return RegMask(); | |
2003 } | |
2004 | |
2005 // Register for DIVL projection of divmodL | |
2006 RegMask Matcher::divL_proj_mask() { | |
2007 ShouldNotReachHere(); | |
2008 return RegMask(); | |
2009 } | |
2010 | |
2011 // Register for MODL projection of divmodL | |
2012 RegMask Matcher::modL_proj_mask() { | |
2013 ShouldNotReachHere(); | |
2014 return RegMask(); | |
2015 } | |
2016 | |
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2017 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
4121
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2018 return L7_REGP_mask(); |
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2019 } |
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2020 |
12323 | 2021 const RegMask Matcher::mathExactI_result_proj_mask() { |
2022 return G1_REGI_mask(); | |
2023 } | |
2024 | |
2025 const RegMask Matcher::mathExactI_flags_proj_mask() { | |
2026 return INT_FLAGS_mask(); | |
2027 } | |
2028 | |
2029 | |
0 | 2030 %} |
2031 | |
2032 | |
2033 // The intptr_t operand types, defined by textual substitution. | |
2034 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
2035 #ifdef _LP64 | |
824 | 2036 #define immX immL |
2037 #define immX13 immL13 | |
2038 #define immX13m7 immL13m7 | |
2039 #define iRegX iRegL | |
2040 #define g1RegX g1RegL | |
0 | 2041 #else |
824 | 2042 #define immX immI |
2043 #define immX13 immI13 | |
2044 #define immX13m7 immI13m7 | |
2045 #define iRegX iRegI | |
2046 #define g1RegX g1RegI | |
0 | 2047 #endif |
2048 | |
2049 //----------ENCODING BLOCK----------------------------------------------------- | |
2050 // This block specifies the encoding classes used by the compiler to output | |
2051 // byte streams. Encoding classes are parameterized macros used by | |
2052 // Machine Instruction Nodes in order to generate the bit encoding of the | |
2053 // instruction. Operands specify their base encoding interface with the | |
2054 // interface keyword. There are currently supported four interfaces, | |
2055 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
2056 // operand to generate a function which returns its register number when | |
2057 // queried. CONST_INTER causes an operand to generate a function which | |
2058 // returns the value of the constant when queried. MEMORY_INTER causes an | |
2059 // operand to generate four functions which return the Base Register, the | |
2060 // Index Register, the Scale Value, and the Offset Value of the operand when | |
2061 // queried. COND_INTER causes an operand to generate six functions which | |
2062 // return the encoding code (ie - encoding bits for the instruction) | |
2063 // associated with each basic boolean condition for a conditional instruction. | |
2064 // | |
2065 // Instructions specify two basic values for encoding. Again, a function | |
2066 // is available to check if the constant displacement is an oop. They use the | |
2067 // ins_encode keyword to specify their encoding classes (which must be | |
2068 // a sequence of enc_class names, and their parameters, specified in | |
2069 // the encoding block), and they use the | |
2070 // opcode keyword to specify, in order, their primary, secondary, and | |
2071 // tertiary opcode. Only the opcode sections which a particular instruction | |
2072 // needs for encoding need to be specified. | |
2073 encode %{ | |
2074 enc_class enc_untested %{ | |
2075 #ifdef ASSERT | |
2076 MacroAssembler _masm(&cbuf); | |
2077 __ untested("encoding"); | |
2078 #endif | |
2079 %} | |
2080 | |
2081 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
2082 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
2083 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | |
2084 %} | |
2085 | |
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2086 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
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2087 emit_form3_mem_reg(cbuf, this, $primary, -1, |
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2088 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
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2089 %} |
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2090 |
0 | 2091 enc_class form3_mem_prefetch_read( memory mem ) %{ |
415
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2092 emit_form3_mem_reg(cbuf, this, $primary, -1, |
0 | 2093 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
2094 %} | |
2095 | |
2096 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
415
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2097 emit_form3_mem_reg(cbuf, this, $primary, -1, |
0 | 2098 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
2099 %} | |
2100 | |
2101 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
4114
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2102 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
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2103 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
0 | 2104 guarantee($mem$$index == R_G0_enc, "double index?"); |
415
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2105 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
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2106 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
0 | 2107 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
2108 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
2109 %} | |
2110 | |
2111 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
4114
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2112 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
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2113 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
0 | 2114 guarantee($mem$$index == R_G0_enc, "double index?"); |
2115 // Load long with 2 instructions | |
415
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2116 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
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2117 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
0 | 2118 %} |
2119 | |
2120 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
2121 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
2122 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
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2123 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
0 | 2124 %} |
2125 | |
2126 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
2127 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2128 if( $rs2$$reg != $rd$$reg ) | |
2129 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
2130 %} | |
2131 | |
2132 // Target lo half of long | |
2133 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
2134 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2135 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
2136 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
2137 %} | |
2138 | |
2139 // Source lo half of long | |
2140 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
2141 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2142 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
2143 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
2144 %} | |
2145 | |
2146 // Target hi half of long | |
2147 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
2148 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
2149 %} | |
2150 | |
2151 // Source lo half of long, and leave it sign extended. | |
2152 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
2153 // Sign extend low half | |
2154 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
2155 %} | |
2156 | |
2157 // Source hi half of long, and leave it sign extended. | |
2158 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
2159 // Shift high half to low half | |
2160 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
2161 %} | |
2162 | |
2163 // Source hi half of long | |
2164 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
2165 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2166 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
2167 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
2168 %} | |
2169 | |
2170 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
2171 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
2172 %} | |
2173 | |
2174 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
2175 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
2176 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
2177 %} | |
2178 | |
2179 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
2180 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
2181 // clear if nothing else is happening | |
2182 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
2183 // blt,a,pn done | |
2184 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
2185 // mov dst,-1 in delay slot | |
2186 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2187 %} | |
2188 | |
2189 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
2190 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
2191 %} | |
2192 | |
2193 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
2194 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
2195 %} | |
2196 | |
2197 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
2198 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
2199 %} | |
2200 | |
2201 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
2202 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
2203 %} | |
2204 | |
2205 enc_class move_return_pc_to_o1() %{ | |
2206 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
2207 %} | |
2208 | |
2209 #ifdef _LP64 | |
2210 /* %%% merge with enc_to_bool */ | |
2211 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
2212 MacroAssembler _masm(&cbuf); | |
2213 | |
2214 Register src_reg = reg_to_register_object($src$$reg); | |
2215 Register dst_reg = reg_to_register_object($dst$$reg); | |
2216 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
2217 %} | |
2218 #endif | |
2219 | |
2220 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
2221 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
2222 MacroAssembler _masm(&cbuf); | |
2223 | |
2224 Register p_reg = reg_to_register_object($p$$reg); | |
2225 Register q_reg = reg_to_register_object($q$$reg); | |
2226 Register y_reg = reg_to_register_object($y$$reg); | |
2227 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
2228 | |
2229 __ subcc( p_reg, q_reg, p_reg ); | |
2230 __ add ( p_reg, y_reg, tmp_reg ); | |
2231 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
2232 %} | |
2233 | |
2234 enc_class form_d2i_helper(regD src, regF dst) %{ | |
2235 // fcmp %fcc0,$src,$src | |
2236 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2237 // branch %fcc0 not-nan, predict taken | |
2238 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2239 // fdtoi $src,$dst | |
2240 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
2241 // fitos $dst,$dst (if nan) | |
2242 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2243 // clear $dst (if nan) | |
2244 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2245 // carry on here... | |
2246 %} | |
2247 | |
2248 enc_class form_d2l_helper(regD src, regD dst) %{ | |
2249 // fcmp %fcc0,$src,$src check for NAN | |
2250 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2251 // branch %fcc0 not-nan, predict taken | |
2252 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2253 // fdtox $src,$dst convert in delay slot | |
2254 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
2255 // fxtod $dst,$dst (if nan) | |
2256 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2257 // clear $dst (if nan) | |
2258 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2259 // carry on here... | |
2260 %} | |
2261 | |
2262 enc_class form_f2i_helper(regF src, regF dst) %{ | |
2263 // fcmps %fcc0,$src,$src | |
2264 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2265 // branch %fcc0 not-nan, predict taken | |
2266 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2267 // fstoi $src,$dst | |
2268 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
2269 // fitos $dst,$dst (if nan) | |
2270 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2271 // clear $dst (if nan) | |
2272 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2273 // carry on here... | |
2274 %} | |
2275 | |
2276 enc_class form_f2l_helper(regF src, regD dst) %{ | |
2277 // fcmps %fcc0,$src,$src | |
2278 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2279 // branch %fcc0 not-nan, predict taken | |
2280 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2281 // fstox $src,$dst | |
2282 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
2283 // fxtod $dst,$dst (if nan) | |
2284 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2285 // clear $dst (if nan) | |
2286 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2287 // carry on here... | |
2288 %} | |
2289 | |
2290 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2291 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2292 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2293 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2294 | |
2295 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2296 | |
2297 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2298 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2299 | |
2300 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
2301 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2302 %} | |
2303 | |
2304 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
2305 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2306 %} | |
2307 | |
2308 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
2309 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2310 %} | |
2311 | |
2312 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
2313 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2314 %} | |
2315 | |
2316 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
2317 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
2318 %} | |
2319 | |
2320 // Encloding class for traceable jumps | |
2321 enc_class form_jmpl(g3RegP dest) %{ | |
2322 emit_jmpl(cbuf, $dest$$reg); | |
2323 %} | |
2324 | |
2325 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
2326 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
2327 %} | |
2328 | |
2329 enc_class form2_nop() %{ | |
2330 emit_nop(cbuf); | |
2331 %} | |
2332 | |
2333 enc_class form2_illtrap() %{ | |
2334 emit_illtrap(cbuf); | |
2335 %} | |
2336 | |
2337 | |
2338 // Compare longs and convert into -1, 0, 1. | |
2339 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
2340 // CMP $src1,$src2 | |
2341 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
2342 // blt,a,pn done | |
2343 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
2344 // mov dst,-1 in delay slot | |
2345 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2346 // bgt,a,pn done | |
2347 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
2348 // mov dst,1 in delay slot | |
2349 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
2350 // CLR $dst | |
2351 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
2352 %} | |
2353 | |
2354 enc_class enc_PartialSubtypeCheck() %{ | |
2355 MacroAssembler _masm(&cbuf); | |
2356 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
2357 __ delayed()->nop(); | |
2358 %} | |
2359 | |
3839 | 2360 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ |
0 | 2361 MacroAssembler _masm(&cbuf); |
3839 | 2362 Label* L = $labl$$label; |
0 | 2363 Assembler::Predict predict_taken = |
3839 | 2364 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
2365 | |
2366 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
0 | 2367 __ delayed()->nop(); |
2368 %} | |
2369 | |
3839 | 2370 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ |
0 | 2371 MacroAssembler _masm(&cbuf); |
3839 | 2372 Label* L = $labl$$label; |
0 | 2373 Assembler::Predict predict_taken = |
3839 | 2374 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
2375 | |
2376 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); | |
0 | 2377 __ delayed()->nop(); |
2378 %} | |
2379 | |
2380 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
2381 int op = (Assembler::arith_op << 30) | | |
2382 ($dst$$reg << 25) | | |
2383 (Assembler::movcc_op3 << 19) | | |
2384 (1 << 18) | // cc2 bit for 'icc' | |
2385 ($cmp$$cmpcode << 14) | | |
2386 (0 << 13) | // select register move | |
2387 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
2388 ($src$$reg << 0); | |
1748 | 2389 cbuf.insts()->emit_int32(op); |
0 | 2390 %} |
2391 | |
2392 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
2393 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2394 int op = (Assembler::arith_op << 30) | | |
2395 ($dst$$reg << 25) | | |
2396 (Assembler::movcc_op3 << 19) | | |
2397 (1 << 18) | // cc2 bit for 'icc' | |
2398 ($cmp$$cmpcode << 14) | | |
2399 (1 << 13) | // select immediate move | |
2400 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
2401 (simm11 << 0); | |
1748 | 2402 cbuf.insts()->emit_int32(op); |
0 | 2403 %} |
2404 | |
2405 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
2406 int op = (Assembler::arith_op << 30) | | |
2407 ($dst$$reg << 25) | | |
2408 (Assembler::movcc_op3 << 19) | | |
2409 (0 << 18) | // cc2 bit for 'fccX' | |
2410 ($cmp$$cmpcode << 14) | | |
2411 (0 << 13) | // select register move | |
2412 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2413 ($src$$reg << 0); | |
1748 | 2414 cbuf.insts()->emit_int32(op); |
0 | 2415 %} |
2416 | |
2417 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
2418 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2419 int op = (Assembler::arith_op << 30) | | |
2420 ($dst$$reg << 25) | | |
2421 (Assembler::movcc_op3 << 19) | | |
2422 (0 << 18) | // cc2 bit for 'fccX' | |
2423 ($cmp$$cmpcode << 14) | | |
2424 (1 << 13) | // select immediate move | |
2425 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2426 (simm11 << 0); | |
1748 | 2427 cbuf.insts()->emit_int32(op); |
0 | 2428 %} |
2429 | |
2430 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
2431 int op = (Assembler::arith_op << 30) | | |
2432 ($dst$$reg << 25) | | |
2433 (Assembler::fpop2_op3 << 19) | | |
2434 (0 << 18) | | |
2435 ($cmp$$cmpcode << 14) | | |
2436 (1 << 13) | // select register move | |
2437 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
2438 ($primary << 5) | // select single, double or quad | |
2439 ($src$$reg << 0); | |
1748 | 2440 cbuf.insts()->emit_int32(op); |
0 | 2441 %} |
2442 | |
2443 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
2444 int op = (Assembler::arith_op << 30) | | |
2445 ($dst$$reg << 25) | | |
2446 (Assembler::fpop2_op3 << 19) | | |
2447 (0 << 18) | | |
2448 ($cmp$$cmpcode << 14) | | |
2449 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
2450 ($primary << 5) | // select single, double or quad | |
2451 ($src$$reg << 0); | |
1748 | 2452 cbuf.insts()->emit_int32(op); |
0 | 2453 %} |
2454 | |
2455 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
2456 // the condition comes from opcode-field instead of an argument. | |
2457 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
2458 int op = (Assembler::arith_op << 30) | | |
2459 ($dst$$reg << 25) | | |
2460 (Assembler::movcc_op3 << 19) | | |
2461 (1 << 18) | // cc2 bit for 'icc' | |
2462 ($primary << 14) | | |
2463 (0 << 13) | // select register move | |
2464 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2465 ($src$$reg << 0); | |
1748 | 2466 cbuf.insts()->emit_int32(op); |
0 | 2467 %} |
2468 | |
2469 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
2470 int op = (Assembler::arith_op << 30) | | |
2471 ($dst$$reg << 25) | | |
2472 (Assembler::movcc_op3 << 19) | | |
2473 (6 << 16) | // cc2 bit for 'xcc' | |
2474 ($primary << 14) | | |
2475 (0 << 13) | // select register move | |
2476 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2477 ($src$$reg << 0); | |
1748 | 2478 cbuf.insts()->emit_int32(op); |
0 | 2479 %} |
2480 | |
2481 enc_class Set13( immI13 src, iRegI rd ) %{ | |
2482 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
2483 %} | |
2484 | |
2485 enc_class SetHi22( immI src, iRegI rd ) %{ | |
2486 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
2487 %} | |
2488 | |
2489 enc_class Set32( immI src, iRegI rd ) %{ | |
2490 MacroAssembler _masm(&cbuf); | |
2491 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
2492 %} | |
2493 | |
2494 enc_class call_epilog %{ | |
2495 if( VerifyStackAtCalls ) { | |
2496 MacroAssembler _masm(&cbuf); | |
2497 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
2498 Register temp_reg = G3; | |
2499 __ add(SP, framesize, temp_reg); | |
2500 __ cmp(temp_reg, FP); | |
2501 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
2502 } | |
2503 %} | |
2504 | |
2505 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
2506 // to G1 so the register allocator will not have to deal with the misaligned register | |
2507 // pair. | |
2508 enc_class adjust_long_from_native_call %{ | |
2509 #ifndef _LP64 | |
2510 if (returns_long()) { | |
2511 // sllx O0,32,O0 | |
2512 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
2513 // srl O1,0,O1 | |
2514 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
2515 // or O0,O1,G1 | |
2516 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
2517 } | |
2518 #endif | |
2519 %} | |
2520 | |
2521 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
2522 // CALL directly to the runtime | |
2523 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
2524 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
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2525 /*preserve_g2=*/true); |
0 | 2526 %} |
2527 | |
1567 | 2528 enc_class preserve_SP %{ |
2529 MacroAssembler _masm(&cbuf); | |
2530 __ mov(SP, L7_mh_SP_save); | |
2531 %} | |
2532 | |
2533 enc_class restore_SP %{ | |
2534 MacroAssembler _masm(&cbuf); | |
2535 __ mov(L7_mh_SP_save, SP); | |
2536 %} | |
2537 | |
0 | 2538 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
2539 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
2540 // who we intended to call. | |
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2541 if (!_method) { |
0 | 2542 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); |
2543 } else if (_optimized_virtual) { | |
2544 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
2545 } else { | |
2546 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
2547 } | |
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2548 if (_method) { // Emit stub for static call. |
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2549 CompiledStaticCall::emit_to_interp_stub(cbuf); |
0 | 2550 } |
2551 %} | |
2552 | |
2553 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
2554 MacroAssembler _masm(&cbuf); | |
2555 __ set_inst_mark(); | |
2556 int vtable_index = this->_vtable_index; | |
2557 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
2558 if (vtable_index < 0) { | |
2559 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
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2560 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
0 | 2561 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); |
2562 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
2563 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
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2564 __ ic_call((address)$meth$$method); |
0 | 2565 } else { |
2566 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
2567 // Just go thru the vtable | |
2568 // get receiver klass (receiver already checked for non-null) | |
2569 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
2570 int off = __ offset(); | |
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2571 __ load_klass(O0, G3_scratch); |
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2572 int klass_load_size; |
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2573 if (UseCompressedClassPointers) { |
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2574 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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2575 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; |
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2576 } else { |
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2577 klass_load_size = 1*BytesPerInstWord; |
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2578 } |
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2579 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
0 | 2580 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); |
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2581 if (Assembler::is_simm13(v_off)) { |
0 | 2582 __ ld_ptr(G3, v_off, G5_method); |
2583 } else { | |
2584 // Generate 2 instructions | |
2585 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
2586 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
2587 // ld_ptr, set_hi, set | |
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2588 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
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2589 "Unexpected instruction size(s)"); |
0 | 2590 __ ld_ptr(G3, G5_method, G5_method); |
2591 } | |
2592 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
2593 // However it may very well end up in handle_wrong_method if the | |
2594 // method is abstract for the particular class. | |
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2595 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch); |
0 | 2596 // jump to target (either compiled code or c2iadapter) |
2597 __ jmpl(G3_scratch, G0, O7); | |
2598 __ delayed()->nop(); | |
2599 } | |
2600 %} | |
2601 | |
2602 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
2603 MacroAssembler _masm(&cbuf); | |
2604 | |
2605 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
2606 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
2607 // we might be calling a C2I adapter which needs it. | |
2608 | |
2609 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
2610 // Load nmethod | |
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2611 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg); |
0 | 2612 |
2613 // CALL to compiled java, indirect the contents of G3 | |
2614 __ set_inst_mark(); | |
2615 __ callr(temp_reg, G0); | |
2616 __ delayed()->nop(); | |
2617 %} | |
2618 | |
2619 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
2620 MacroAssembler _masm(&cbuf); | |
2621 Register Rdividend = reg_to_register_object($src1$$reg); | |
2622 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2623 Register Rresult = reg_to_register_object($dst$$reg); | |
2624 | |
2625 __ sra(Rdivisor, 0, Rdivisor); | |
2626 __ sra(Rdividend, 0, Rdividend); | |
2627 __ sdivx(Rdividend, Rdivisor, Rresult); | |
2628 %} | |
2629 | |
2630 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
2631 MacroAssembler _masm(&cbuf); | |
2632 | |
2633 Register Rdividend = reg_to_register_object($src1$$reg); | |
2634 int divisor = $imm$$constant; | |
2635 Register Rresult = reg_to_register_object($dst$$reg); | |
2636 | |
2637 __ sra(Rdividend, 0, Rdividend); | |
2638 __ sdivx(Rdividend, divisor, Rresult); | |
2639 %} | |
2640 | |
2641 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
2642 MacroAssembler _masm(&cbuf); | |
2643 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
2644 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
2645 Register Rdst = reg_to_register_object($dst$$reg); | |
2646 | |
2647 __ sra( Rsrc1, 0, Rsrc1 ); | |
2648 __ sra( Rsrc2, 0, Rsrc2 ); | |
2649 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
2650 __ srlx( Rdst, 32, Rdst ); | |
2651 %} | |
2652 | |
2653 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
2654 MacroAssembler _masm(&cbuf); | |
2655 Register Rdividend = reg_to_register_object($src1$$reg); | |
2656 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2657 Register Rresult = reg_to_register_object($dst$$reg); | |
2658 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2659 | |
2660 assert(Rdividend != Rscratch, ""); | |
2661 assert(Rdivisor != Rscratch, ""); | |
2662 | |
2663 __ sra(Rdividend, 0, Rdividend); | |
2664 __ sra(Rdivisor, 0, Rdivisor); | |
2665 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
2666 __ mulx(Rscratch, Rdivisor, Rscratch); | |
2667 __ sub(Rdividend, Rscratch, Rresult); | |
2668 %} | |
2669 | |
2670 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
2671 MacroAssembler _masm(&cbuf); | |
2672 | |
2673 Register Rdividend = reg_to_register_object($src1$$reg); | |
2674 int divisor = $imm$$constant; | |
2675 Register Rresult = reg_to_register_object($dst$$reg); | |
2676 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2677 | |
2678 assert(Rdividend != Rscratch, ""); | |
2679 | |
2680 __ sra(Rdividend, 0, Rdividend); | |
2681 __ sdivx(Rdividend, divisor, Rscratch); | |
2682 __ mulx(Rscratch, divisor, Rscratch); | |
2683 __ sub(Rdividend, Rscratch, Rresult); | |
2684 %} | |
2685 | |
2686 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
2687 MacroAssembler _masm(&cbuf); | |
2688 | |
2689 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2690 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2691 | |
2692 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
2693 %} | |
2694 | |
2695 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
2696 MacroAssembler _masm(&cbuf); | |
2697 | |
2698 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2699 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2700 | |
2701 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
2702 %} | |
2703 | |
2704 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
2705 MacroAssembler _masm(&cbuf); | |
2706 | |
2707 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2708 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2709 | |
2710 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
2711 %} | |
2712 | |
2713 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
2714 MacroAssembler _masm(&cbuf); | |
2715 | |
2716 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2717 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2718 | |
2719 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
2720 %} | |
2721 | |
2722 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
2723 MacroAssembler _masm(&cbuf); | |
2724 | |
2725 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2726 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2727 | |
2728 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
2729 %} | |
2730 | |
2731 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
2732 MacroAssembler _masm(&cbuf); | |
2733 | |
2734 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2735 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2736 | |
2737 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
2738 %} | |
2739 | |
2740 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
2741 MacroAssembler _masm(&cbuf); | |
2742 | |
2743 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2744 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2745 | |
2746 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
2747 %} | |
2748 | |
2749 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2750 MacroAssembler _masm(&cbuf); | |
2751 | |
2752 Register Roop = reg_to_register_object($oop$$reg); | |
2753 Register Rbox = reg_to_register_object($box$$reg); | |
2754 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2755 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2756 | |
2757 assert(Roop != Rscratch, ""); | |
2758 assert(Roop != Rmark, ""); | |
2759 assert(Rbox != Rscratch, ""); | |
2760 assert(Rbox != Rmark, ""); | |
2761 | |
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2762 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2763 %} |
2764 | |
2765 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2766 MacroAssembler _masm(&cbuf); | |
2767 | |
2768 Register Roop = reg_to_register_object($oop$$reg); | |
2769 Register Rbox = reg_to_register_object($box$$reg); | |
2770 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2771 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2772 | |
2773 assert(Roop != Rscratch, ""); | |
2774 assert(Roop != Rmark, ""); | |
2775 assert(Rbox != Rscratch, ""); | |
2776 assert(Rbox != Rmark, ""); | |
2777 | |
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2778 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2779 %} |
2780 | |
2781 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
2782 MacroAssembler _masm(&cbuf); | |
2783 Register Rmem = reg_to_register_object($mem$$reg); | |
2784 Register Rold = reg_to_register_object($old$$reg); | |
2785 Register Rnew = reg_to_register_object($new$$reg); | |
2786 | |
10997 | 2787 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
0 | 2788 __ cmp( Rold, Rnew ); |
2789 %} | |
2790 | |
2791 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
2792 Register Rmem = reg_to_register_object($mem$$reg); | |
2793 Register Rold = reg_to_register_object($old$$reg); | |
2794 Register Rnew = reg_to_register_object($new$$reg); | |
2795 | |
2796 MacroAssembler _masm(&cbuf); | |
2797 __ mov(Rnew, O7); | |
2798 __ casx(Rmem, Rold, O7); | |
2799 __ cmp( Rold, O7 ); | |
2800 %} | |
2801 | |
2802 // raw int cas, used for compareAndSwap | |
2803 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
2804 Register Rmem = reg_to_register_object($mem$$reg); | |
2805 Register Rold = reg_to_register_object($old$$reg); | |
2806 Register Rnew = reg_to_register_object($new$$reg); | |
2807 | |
2808 MacroAssembler _masm(&cbuf); | |
2809 __ mov(Rnew, O7); | |
2810 __ cas(Rmem, Rold, O7); | |
2811 __ cmp( Rold, O7 ); | |
2812 %} | |
2813 | |
2814 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
2815 Register Rres = reg_to_register_object($res$$reg); | |
2816 | |
2817 MacroAssembler _masm(&cbuf); | |
2818 __ mov(1, Rres); | |
2819 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
2820 %} | |
2821 | |
2822 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
2823 Register Rres = reg_to_register_object($res$$reg); | |
2824 | |
2825 MacroAssembler _masm(&cbuf); | |
2826 __ mov(1, Rres); | |
2827 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
2828 %} | |
2829 | |
2830 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
2831 MacroAssembler _masm(&cbuf); | |
2832 Register Rdst = reg_to_register_object($dst$$reg); | |
2833 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
2834 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
2835 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
2836 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
2837 | |
2838 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
2839 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
2840 %} | |
2841 | |
2842 | |
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2843 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
0 | 2844 Label Ldone, Lloop; |
2845 MacroAssembler _masm(&cbuf); | |
2846 | |
2847 Register str1_reg = reg_to_register_object($str1$$reg); | |
2848 Register str2_reg = reg_to_register_object($str2$$reg); | |
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2849 Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
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2850 Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
0 | 2851 Register result_reg = reg_to_register_object($result$$reg); |
2852 | |
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2853 assert(result_reg != str1_reg && |
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2854 result_reg != str2_reg && |
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2855 result_reg != cnt1_reg && |
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2856 result_reg != cnt2_reg , |
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2857 "need different registers"); |
0 | 2858 |
2859 // Compute the minimum of the string lengths(str1_reg) and the | |
2860 // difference of the string lengths (stack) | |
2861 | |
2862 // See if the lengths are different, and calculate min in str1_reg. | |
2863 // Stash diff in O7 in case we need it for a tie-breaker. | |
2864 Label Lskip; | |
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2865 __ subcc(cnt1_reg, cnt2_reg, O7); |
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2866 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
0 | 2867 __ br(Assembler::greater, true, Assembler::pt, Lskip); |
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2868 // cnt2 is shorter, so use its count: |
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2869 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
0 | 2870 __ bind(Lskip); |
2871 | |
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2872 // reallocate cnt1_reg, cnt2_reg, result_reg |
0 | 2873 // Note: limit_reg holds the string length pre-scaled by 2 |
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2874 Register limit_reg = cnt1_reg; |
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2875 Register chr2_reg = cnt2_reg; |
0 | 2876 Register chr1_reg = result_reg; |
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2877 // str{12} are the base pointers |
0 | 2878 |
2879 // Is the minimum length zero? | |
2880 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
2881 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2882 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2883 | |
2884 // Load first characters | |
986
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2885 __ lduh(str1_reg, 0, chr1_reg); |
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2886 __ lduh(str2_reg, 0, chr2_reg); |
0 | 2887 |
2888 // Compare first characters | |
2889 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
2890 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2891 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2892 __ delayed()->nop(); | |
2893 | |
2894 { | |
2895 // Check after comparing first character to see if strings are equivalent | |
2896 Label LSkip2; | |
2897 // Check if the strings start at same location | |
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2898 __ cmp(str1_reg, str2_reg); |
0 | 2899 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
2900 __ delayed()->nop(); | |
2901 | |
2902 // Check if the length difference is zero (in O7) | |
2903 __ cmp(G0, O7); | |
2904 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2905 __ delayed()->mov(G0, result_reg); // result is zero | |
2906 | |
2907 // Strings might not be equal | |
2908 __ bind(LSkip2); | |
2909 } | |
2910 | |
2911 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); | |
2912 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2913 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2914 | |
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2915 // Shift str1_reg and str2_reg to the end of the arrays, negate limit |
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2916 __ add(str1_reg, limit_reg, str1_reg); |
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2917 __ add(str2_reg, limit_reg, str2_reg); |
0 | 2918 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
2919 | |
2920 // Compare the rest of the characters | |
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2921 __ lduh(str1_reg, limit_reg, chr1_reg); |
0 | 2922 __ bind(Lloop); |
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2923 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
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2924 __ lduh(str2_reg, limit_reg, chr2_reg); |
0 | 2925 __ subcc(chr1_reg, chr2_reg, chr1_reg); |
2926 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2927 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2928 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
2929 // annul LDUH if branch is not taken to prevent access past end of string | |
2930 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
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2931 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
0 | 2932 |
2933 // If strings are equal up to min length, return the length difference. | |
2934 __ mov(O7, result_reg); | |
2935 | |
2936 // Otherwise, return the difference between the first mismatched chars. | |
2937 __ bind(Ldone); | |
2938 %} | |
2939 | |
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2940 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
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2941 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
681 | 2942 MacroAssembler _masm(&cbuf); |
2943 | |
2944 Register str1_reg = reg_to_register_object($str1$$reg); | |
2945 Register str2_reg = reg_to_register_object($str2$$reg); | |
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2946 Register cnt_reg = reg_to_register_object($cnt$$reg); |
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2947 Register tmp1_reg = O7; |
681 | 2948 Register result_reg = reg_to_register_object($result$$reg); |
2949 | |
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2950 assert(result_reg != str1_reg && |
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2951 result_reg != str2_reg && |
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2952 result_reg != cnt_reg && |
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2953 result_reg != tmp1_reg , |
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2954 "need different registers"); |
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2955 |
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2956 __ cmp(str1_reg, str2_reg); //same char[] ? |
681 | 2957 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
2958 __ delayed()->add(G0, 1, result_reg); | |
2959 | |
3839 | 2960 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn); |
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2961 __ delayed()->add(G0, 1, result_reg); // count == 0 |
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2962 |
681 | 2963 //rename registers |
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2964 Register limit_reg = cnt_reg; |
681 | 2965 Register chr1_reg = result_reg; |
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2966 Register chr2_reg = tmp1_reg; |
681 | 2967 |
2968 //check for alignment and position the pointers to the ends | |
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2969 __ or3(str1_reg, str2_reg, chr1_reg); |
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2970 __ andcc(chr1_reg, 0x3, chr1_reg); |
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2971 // notZero means at least one not 4-byte aligned. |
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2972 // We could optimize the case when both arrays are not aligned |
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2973 // but it is not frequent case and it requires additional checks. |
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2974 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
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2975 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
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2976 |
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2977 // Compare char[] arrays aligned to 4 bytes. |
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2978 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
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2979 chr1_reg, chr2_reg, Ldone); |
3839 | 2980 __ ba(Ldone); |
681 | 2981 __ delayed()->add(G0, 1, result_reg); |
2982 | |
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2983 // char by char compare |
681 | 2984 __ bind(Lchar); |
986
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2985 __ add(str1_reg, limit_reg, str1_reg); |
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2986 __ add(str2_reg, limit_reg, str2_reg); |
681 | 2987 __ neg(limit_reg); //negate count |
2988 | |
986
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2989 __ lduh(str1_reg, limit_reg, chr1_reg); |
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2990 // Lchar_loop |
681 | 2991 __ bind(Lchar_loop); |
986
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2992 __ lduh(str2_reg, limit_reg, chr2_reg); |
681 | 2993 __ cmp(chr1_reg, chr2_reg); |
2994 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
2995 __ delayed()->mov(G0, result_reg); //not equal | |
2996 __ inccc(limit_reg, sizeof(jchar)); | |
2997 // annul LDUH if branch is not taken to prevent access past end of string | |
986
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2998 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
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2999 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
681 | 3000 |
3001 __ add(G0, 1, result_reg); //equal | |
3002 | |
3003 __ bind(Ldone); | |
3004 %} | |
3005 | |
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3006 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
681 | 3007 Label Lvector, Ldone, Lloop; |
3008 MacroAssembler _masm(&cbuf); | |
3009 | |
3010 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
3011 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
3012 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
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3013 Register tmp2_reg = O7; |
681 | 3014 Register result_reg = reg_to_register_object($result$$reg); |
3015 | |
3016 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
3017 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
3018 | |
3019 // return true if the same array | |
3020 __ cmp(ary1_reg, ary2_reg); | |
1016 | 3021 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
681 | 3022 __ delayed()->add(G0, 1, result_reg); // equal |
3023 | |
3024 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
3025 __ delayed()->mov(G0, result_reg); // not equal | |
3026 | |
3027 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
3028 __ delayed()->mov(G0, result_reg); // not equal | |
3029 | |
3030 //load the lengths of arrays | |
727 | 3031 __ ld(Address(ary1_reg, length_offset), tmp1_reg); |
3032 __ ld(Address(ary2_reg, length_offset), tmp2_reg); | |
681 | 3033 |
3034 // return false if the two arrays are not equal length | |
3035 __ cmp(tmp1_reg, tmp2_reg); | |
3036 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
3037 __ delayed()->mov(G0, result_reg); // not equal | |
3038 | |
3839 | 3039 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn); |
681 | 3040 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
3041 | |
3042 // load array addresses | |
3043 __ add(ary1_reg, base_offset, ary1_reg); | |
3044 __ add(ary2_reg, base_offset, ary2_reg); | |
3045 | |
3046 // renaming registers | |
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3047 Register chr1_reg = result_reg; // for characters in ary1 |
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3048 Register chr2_reg = tmp2_reg; // for characters in ary2 |
681 | 3049 Register limit_reg = tmp1_reg; // length |
3050 | |
3051 // set byte count | |
3052 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
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3053 |
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3054 // Compare char[] arrays aligned to 4 bytes. |
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3055 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
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3056 chr1_reg, chr2_reg, Ldone); |
681 | 3057 __ add(G0, 1, result_reg); // equals |
3058 | |
3059 __ bind(Ldone); | |
3060 %} | |
3061 | |
0 | 3062 enc_class enc_rethrow() %{ |
1748 | 3063 cbuf.set_insts_mark(); |
0 | 3064 Register temp_reg = G3; |
727 | 3065 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
0 | 3066 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
3067 MacroAssembler _masm(&cbuf); | |
3068 #ifdef ASSERT | |
3069 __ save_frame(0); | |
727 | 3070 AddressLiteral last_rethrow_addrlit(&last_rethrow); |
3071 __ sethi(last_rethrow_addrlit, L1); | |
3072 Address addr(L1, last_rethrow_addrlit.low10()); | |
10997 | 3073 __ rdpc(L2); |
0 | 3074 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to |
727 | 3075 __ st_ptr(L2, addr); |
0 | 3076 __ restore(); |
3077 #endif | |
727 | 3078 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
0 | 3079 __ delayed()->nop(); |
3080 %} | |
3081 | |
3082 enc_class emit_mem_nop() %{ | |
3083 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
1748 | 3084 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); |
0 | 3085 %} |
3086 | |
3087 enc_class emit_fadd_nop() %{ | |
3088 // Generates the instruction FMOVS f31,f31 | |
1748 | 3089 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); |
0 | 3090 %} |
3091 | |
3092 enc_class emit_br_nop() %{ | |
3093 // Generates the instruction BPN,PN . | |
1748 | 3094 cbuf.insts()->emit_int32((unsigned int) 0x00400000); |
0 | 3095 %} |
3096 | |
3097 enc_class enc_membar_acquire %{ | |
3098 MacroAssembler _masm(&cbuf); | |
3099 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
3100 %} | |
3101 | |
3102 enc_class enc_membar_release %{ | |
3103 MacroAssembler _masm(&cbuf); | |
3104 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
3105 %} | |
3106 | |
3107 enc_class enc_membar_volatile %{ | |
3108 MacroAssembler _masm(&cbuf); | |
3109 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
3110 %} | |
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3111 |
0 | 3112 %} |
3113 | |
3114 //----------FRAME-------------------------------------------------------------- | |
3115 // Definition of frame structure and management information. | |
3116 // | |
3117 // S T A C K L A Y O U T Allocators stack-slot number | |
3118 // | (to get allocators register number | |
3119 // G Owned by | | v add VMRegImpl::stack0) | |
3120 // r CALLER | | | |
3121 // o | +--------+ pad to even-align allocators stack-slot | |
3122 // w V | pad0 | numbers; owned by CALLER | |
3123 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
3124 // h ^ | in | 5 | |
3125 // | | args | 4 Holes in incoming args owned by SELF | |
3126 // | | | | 3 | |
3127 // | | +--------+ | |
3128 // V | | old out| Empty on Intel, window on Sparc | |
3129 // | old |preserve| Must be even aligned. | |
3130 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
3131 // | | in | 3 area for Intel ret address | |
3132 // Owned by |preserve| Empty on Sparc. | |
3133 // SELF +--------+ | |
3134 // | | pad2 | 2 pad to align old SP | |
3135 // | +--------+ 1 | |
3136 // | | locks | 0 | |
3137 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
3138 // | | pad1 | 11 pad to align new SP | |
3139 // | +--------+ | |
3140 // | | | 10 | |
3141 // | | spills | 9 spills | |
3142 // V | | 8 (pad0 slot for callee) | |
3143 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
3144 // ^ | out | 7 | |
3145 // | | args | 6 Holes in outgoing args owned by CALLEE | |
3146 // Owned by +--------+ | |
3147 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
3148 // | new |preserve| Must be even-aligned. | |
3149 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
3150 // | | | | |
3151 // | |
3152 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
3153 // known from SELF's arguments and the Java calling convention. | |
3154 // Region 6-7 is determined per call site. | |
3155 // Note 2: If the calling convention leaves holes in the incoming argument | |
3156 // area, those holes are owned by SELF. Holes in the outgoing area | |
3157 // are owned by the CALLEE. Holes should not be nessecary in the | |
3158 // incoming area, as the Java calling convention is completely under | |
3159 // the control of the AD file. Doubles can be sorted and packed to | |
3160 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
3161 // varargs C calling conventions. | |
3162 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
3163 // even aligned with pad0 as needed. | |
3164 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
3165 // region 6-11 is even aligned; it may be padded out more so that | |
3166 // the region from SP to FP meets the minimum stack alignment. | |
3167 | |
3168 frame %{ | |
3169 // What direction does stack grow in (assumed to be same for native & Java) | |
3170 stack_direction(TOWARDS_LOW); | |
3171 | |
3172 // These two registers define part of the calling convention | |
3173 // between compiled code and the interpreter. | |
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3174 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C |
0 | 3175 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter |
3176 | |
3177 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
3178 cisc_spilling_operand_name(indOffset); | |
3179 | |
3180 // Number of stack slots consumed by a Monitor enter | |
3181 #ifdef _LP64 | |
3182 sync_stack_slots(2); | |
3183 #else | |
3184 sync_stack_slots(1); | |
3185 #endif | |
3186 | |
3187 // Compiled code's Frame Pointer | |
3188 frame_pointer(R_SP); | |
3189 | |
3190 // Stack alignment requirement | |
3191 stack_alignment(StackAlignmentInBytes); | |
3192 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
3193 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
3194 | |
3195 // Number of stack slots between incoming argument block and the start of | |
3196 // a new frame. The PROLOG must add this many slots to the stack. The | |
3197 // EPILOG must remove this many slots. | |
3198 in_preserve_stack_slots(0); | |
3199 | |
3200 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
3201 // for calls to C. Supports the var-args backing area for register parms. | |
3202 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
3203 #ifdef _LP64 | |
3204 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
3205 varargs_C_out_slots_killed(12); | |
3206 #else | |
3207 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
3208 varargs_C_out_slots_killed( 7); | |
3209 #endif | |
3210 | |
3211 // The after-PROLOG location of the return address. Location of | |
3212 // return address specifies a type (REG or STACK) and a number | |
3213 // representing the register number (i.e. - use a register name) or | |
3214 // stack slot. | |
3215 return_addr(REG R_I7); // Ret Addr is in register I7 | |
3216 | |
3217 // Body of function which returns an OptoRegs array locating | |
3218 // arguments either in registers or in stack slots for calling | |
3219 // java | |
3220 calling_convention %{ | |
3221 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
3222 | |
3223 %} | |
3224 | |
3225 // Body of function which returns an OptoRegs array locating | |
3226 // arguments either in registers or in stack slots for callin | |
3227 // C. | |
3228 c_calling_convention %{ | |
3229 // This is obviously always outgoing | |
3230 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
3231 %} | |
3232 | |
3233 // Location of native (C/C++) and interpreter return values. This is specified to | |
3234 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
3235 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
3236 // to and from the register pairs is done by the appropriate call and epilog | |
3237 // opcodes. This simplifies the register allocator. | |
3238 c_return_value %{ | |
3239 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3240 #ifdef _LP64 | |
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3241 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3242 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3243 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3244 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3245 #else // !_LP64 |
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3246 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3247 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
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3248 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3249 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
0 | 3250 #endif |
3251 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3252 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3253 %} | |
3254 | |
3255 // Location of compiled Java return values. Same as C | |
3256 return_value %{ | |
3257 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3258 #ifdef _LP64 | |
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3259 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3260 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3261 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3262 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3263 #else // !_LP64 |
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3264 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3265 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
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3266 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3267 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
0 | 3268 #endif |
3269 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3270 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3271 %} | |
3272 | |
3273 %} | |
3274 | |
3275 | |
3276 //----------ATTRIBUTES--------------------------------------------------------- | |
3277 //----------Operand Attributes------------------------------------------------- | |
3278 op_attrib op_cost(1); // Required cost attribute | |
3279 | |
3280 //----------Instruction Attributes--------------------------------------------- | |
3281 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
3842 | 3282 ins_attrib ins_size(32); // Required size attribute (in bits) |
3851 | 3283 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back |
3842 | 3284 ins_attrib ins_short_branch(0); // Required flag: is this instruction a |
3285 // non-matching short branch variant of some | |
0 | 3286 // long branch? |
3287 | |
3288 //----------OPERANDS----------------------------------------------------------- | |
3289 // Operand definitions must precede instruction definitions for correct parsing | |
3290 // in the ADLC because operands constitute user defined types which are used in | |
3291 // instruction definitions. | |
3292 | |
3293 //----------Simple Operands---------------------------------------------------- | |
3294 // Immediate Operands | |
3295 // Integer Immediate: 32-bit | |
3296 operand immI() %{ | |
3297 match(ConI); | |
3298 | |
3299 op_cost(0); | |
3300 // formats are generated automatically for constants and base registers | |
3301 format %{ %} | |
3302 interface(CONST_INTER); | |
3303 %} | |
3304 | |
824 | 3305 // Integer Immediate: 8-bit |
3306 operand immI8() %{ | |
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3307 predicate(Assembler::is_simm8(n->get_int())); |
824 | 3308 match(ConI); |
3309 op_cost(0); | |
3310 format %{ %} | |
3311 interface(CONST_INTER); | |
3312 %} | |
3313 | |
0 | 3314 // Integer Immediate: 13-bit |
3315 operand immI13() %{ | |
3316 predicate(Assembler::is_simm13(n->get_int())); | |
3317 match(ConI); | |
3318 op_cost(0); | |
3319 | |
3320 format %{ %} | |
3321 interface(CONST_INTER); | |
3322 %} | |
3323 | |
785 | 3324 // Integer Immediate: 13-bit minus 7 |
3325 operand immI13m7() %{ | |
3326 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); | |
3327 match(ConI); | |
3328 op_cost(0); | |
3329 | |
3330 format %{ %} | |
3331 interface(CONST_INTER); | |
3332 %} | |
3333 | |
824 | 3334 // Integer Immediate: 16-bit |
3335 operand immI16() %{ | |
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3336 predicate(Assembler::is_simm16(n->get_int())); |
824 | 3337 match(ConI); |
3338 op_cost(0); | |
3339 format %{ %} | |
3340 interface(CONST_INTER); | |
3341 %} | |
3342 | |
0 | 3343 // Unsigned (positive) Integer Immediate: 13-bit |
3344 operand immU13() %{ | |
3345 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | |
3346 match(ConI); | |
3347 op_cost(0); | |
3348 | |
3349 format %{ %} | |
3350 interface(CONST_INTER); | |
3351 %} | |
3352 | |
3353 // Integer Immediate: 6-bit | |
3354 operand immU6() %{ | |
3355 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
3356 match(ConI); | |
3357 op_cost(0); | |
3358 format %{ %} | |
3359 interface(CONST_INTER); | |
3360 %} | |
3361 | |
3362 // Integer Immediate: 11-bit | |
3363 operand immI11() %{ | |
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3364 predicate(Assembler::is_simm11(n->get_int())); |
0 | 3365 match(ConI); |
3366 op_cost(0); | |
3367 format %{ %} | |
3368 interface(CONST_INTER); | |
3369 %} | |
3370 | |
3851 | 3371 // Integer Immediate: 5-bit |
3372 operand immI5() %{ | |
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3373 predicate(Assembler::is_simm5(n->get_int())); |
3851 | 3374 match(ConI); |
3375 op_cost(0); | |
3376 format %{ %} | |
3377 interface(CONST_INTER); | |
3378 %} | |
3379 | |
0 | 3380 // Integer Immediate: 0-bit |
3381 operand immI0() %{ | |
3382 predicate(n->get_int() == 0); | |
3383 match(ConI); | |
3384 op_cost(0); | |
3385 | |
3386 format %{ %} | |
3387 interface(CONST_INTER); | |
3388 %} | |
3389 | |
3390 // Integer Immediate: the value 10 | |
3391 operand immI10() %{ | |
3392 predicate(n->get_int() == 10); | |
3393 match(ConI); | |
3394 op_cost(0); | |
3395 | |
3396 format %{ %} | |
3397 interface(CONST_INTER); | |
3398 %} | |
3399 | |
3400 // Integer Immediate: the values 0-31 | |
3401 operand immU5() %{ | |
3402 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
3403 match(ConI); | |
3404 op_cost(0); | |
3405 | |
3406 format %{ %} | |
3407 interface(CONST_INTER); | |
3408 %} | |
3409 | |
3410 // Integer Immediate: the values 1-31 | |
3411 operand immI_1_31() %{ | |
3412 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
3413 match(ConI); | |
3414 op_cost(0); | |
3415 | |
3416 format %{ %} | |
3417 interface(CONST_INTER); | |
3418 %} | |
3419 | |
3420 // Integer Immediate: the values 32-63 | |
3421 operand immI_32_63() %{ | |
3422 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
3423 match(ConI); | |
3424 op_cost(0); | |
3425 | |
3426 format %{ %} | |
3427 interface(CONST_INTER); | |
3428 %} | |
3429 | |
785 | 3430 // Immediates for special shifts (sign extend) |
3431 | |
3432 // Integer Immediate: the value 16 | |
3433 operand immI_16() %{ | |
3434 predicate(n->get_int() == 16); | |
3435 match(ConI); | |
3436 op_cost(0); | |
3437 | |
3438 format %{ %} | |
3439 interface(CONST_INTER); | |
3440 %} | |
3441 | |
3442 // Integer Immediate: the value 24 | |
3443 operand immI_24() %{ | |
3444 predicate(n->get_int() == 24); | |
3445 match(ConI); | |
3446 op_cost(0); | |
3447 | |
3448 format %{ %} | |
3449 interface(CONST_INTER); | |
3450 %} | |
3451 | |
0 | 3452 // Integer Immediate: the value 255 |
3453 operand immI_255() %{ | |
3454 predicate( n->get_int() == 255 ); | |
3455 match(ConI); | |
3456 op_cost(0); | |
3457 | |
3458 format %{ %} | |
3459 interface(CONST_INTER); | |
3460 %} | |
3461 | |
785 | 3462 // Integer Immediate: the value 65535 |
3463 operand immI_65535() %{ | |
3464 predicate(n->get_int() == 65535); | |
3465 match(ConI); | |
3466 op_cost(0); | |
3467 | |
3468 format %{ %} | |
3469 interface(CONST_INTER); | |
3470 %} | |
3471 | |
0 | 3472 // Long Immediate: the value FF |
3473 operand immL_FF() %{ | |
3474 predicate( n->get_long() == 0xFFL ); | |
3475 match(ConL); | |
3476 op_cost(0); | |
3477 | |
3478 format %{ %} | |
3479 interface(CONST_INTER); | |
3480 %} | |
3481 | |
3482 // Long Immediate: the value FFFF | |
3483 operand immL_FFFF() %{ | |
3484 predicate( n->get_long() == 0xFFFFL ); | |
3485 match(ConL); | |
3486 op_cost(0); | |
3487 | |
3488 format %{ %} | |
3489 interface(CONST_INTER); | |
3490 %} | |
3491 | |
3492 // Pointer Immediate: 32 or 64-bit | |
3493 operand immP() %{ | |
3494 match(ConP); | |
3495 | |
3496 op_cost(5); | |
3497 // formats are generated automatically for constants and base registers | |
3498 format %{ %} | |
3499 interface(CONST_INTER); | |
3500 %} | |
3501 | |
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3502 #ifdef _LP64 |
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3503 // Pointer Immediate: 64-bit |
2008 | 3504 operand immP_set() %{ |
2080 | 3505 predicate(!VM_Version::is_niagara_plus()); |
2008 | 3506 match(ConP); |
3507 | |
3508 op_cost(5); | |
3509 // formats are generated automatically for constants and base registers | |
3510 format %{ %} | |
3511 interface(CONST_INTER); | |
3512 %} | |
3513 | |
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3514 // Pointer Immediate: 64-bit |
2008 | 3515 // From Niagara2 processors on a load should be better than materializing. |
3516 operand immP_load() %{ | |
2080 | 3517 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); |
2008 | 3518 match(ConP); |
3519 | |
3520 op_cost(5); | |
3521 // formats are generated automatically for constants and base registers | |
3522 format %{ %} | |
3523 interface(CONST_INTER); | |
3524 %} | |
3525 | |
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3526 // Pointer Immediate: 64-bit |
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3527 operand immP_no_oop_cheap() %{ |
2080 | 3528 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); |
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3529 match(ConP); |
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3530 |
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3531 op_cost(5); |
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3532 // formats are generated automatically for constants and base registers |
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3533 format %{ %} |
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3534 interface(CONST_INTER); |
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3535 %} |
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3536 #endif |
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3537 |
0 | 3538 operand immP13() %{ |
3539 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
3540 match(ConP); | |
3541 op_cost(0); | |
3542 | |
3543 format %{ %} | |
3544 interface(CONST_INTER); | |
3545 %} | |
3546 | |
3547 operand immP0() %{ | |
3548 predicate(n->get_ptr() == 0); | |
3549 match(ConP); | |
3550 op_cost(0); | |
3551 | |
3552 format %{ %} | |
3553 interface(CONST_INTER); | |
3554 %} | |
3555 | |
3556 operand immP_poll() %{ | |
3557 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
3558 match(ConP); | |
3559 | |
3560 // formats are generated automatically for constants and base registers | |
3561 format %{ %} | |
3562 interface(CONST_INTER); | |
3563 %} | |
3564 | |
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3565 // Pointer Immediate |
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3566 operand immN() |
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3567 %{ |
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3568 match(ConN); |
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3569 |
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3570 op_cost(10); |
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3571 format %{ %} |
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3572 interface(CONST_INTER); |
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3573 %} |
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3574 |
6848
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3575 operand immNKlass() |
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3576 %{ |
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3577 match(ConNKlass); |
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|
3578 |
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3579 op_cost(10); |
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3580 format %{ %} |
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|
3581 interface(CONST_INTER); |
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3582 %} |
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3583 |
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3584 // NULL Pointer Immediate |
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3585 operand immN0() |
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3586 %{ |
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3587 predicate(n->get_narrowcon() == 0); |
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3588 match(ConN); |
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3589 |
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3590 op_cost(0); |
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3591 format %{ %} |
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3592 interface(CONST_INTER); |
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3593 %} |
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3594 |
0 | 3595 operand immL() %{ |
3596 match(ConL); | |
3597 op_cost(40); | |
3598 // formats are generated automatically for constants and base registers | |
3599 format %{ %} | |
3600 interface(CONST_INTER); | |
3601 %} | |
3602 | |
3603 operand immL0() %{ | |
3604 predicate(n->get_long() == 0L); | |
3605 match(ConL); | |
3606 op_cost(0); | |
3607 // formats are generated automatically for constants and base registers | |
3608 format %{ %} | |
3609 interface(CONST_INTER); | |
3610 %} | |
3611 | |
3851 | 3612 // Integer Immediate: 5-bit |
3613 operand immL5() %{ | |
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3614 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long())); |
3851 | 3615 match(ConL); |
3616 op_cost(0); | |
3617 format %{ %} | |
3618 interface(CONST_INTER); | |
3619 %} | |
3620 | |
0 | 3621 // Long Immediate: 13-bit |
3622 operand immL13() %{ | |
3623 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
3624 match(ConL); | |
3625 op_cost(0); | |
3626 | |
3627 format %{ %} | |
3628 interface(CONST_INTER); | |
3629 %} | |
3630 | |
785 | 3631 // Long Immediate: 13-bit minus 7 |
3632 operand immL13m7() %{ | |
3633 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); | |
3634 match(ConL); | |
3635 op_cost(0); | |
3636 | |
3637 format %{ %} | |
3638 interface(CONST_INTER); | |
3639 %} | |
3640 | |
0 | 3641 // Long Immediate: low 32-bit mask |
3642 operand immL_32bits() %{ | |
3643 predicate(n->get_long() == 0xFFFFFFFFL); | |
3644 match(ConL); | |
3645 op_cost(0); | |
3646 | |
3647 format %{ %} | |
3648 interface(CONST_INTER); | |
3649 %} | |
3650 | |
2008 | 3651 // Long Immediate: cheap (materialize in <= 3 instructions) |
3652 operand immL_cheap() %{ | |
2080 | 3653 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); |
2008 | 3654 match(ConL); |
3655 op_cost(0); | |
3656 | |
3657 format %{ %} | |
3658 interface(CONST_INTER); | |
3659 %} | |
3660 | |
3661 // Long Immediate: expensive (materialize in > 3 instructions) | |
3662 operand immL_expensive() %{ | |
2080 | 3663 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3); |
2008 | 3664 match(ConL); |
3665 op_cost(0); | |
3666 | |
3667 format %{ %} | |
3668 interface(CONST_INTER); | |
3669 %} | |
3670 | |
0 | 3671 // Double Immediate |
3672 operand immD() %{ | |
3673 match(ConD); | |
3674 | |
3675 op_cost(40); | |
3676 format %{ %} | |
3677 interface(CONST_INTER); | |
3678 %} | |
3679 | |
3680 operand immD0() %{ | |
3681 #ifdef _LP64 | |
3682 // on 64-bit architectures this comparision is faster | |
3683 predicate(jlong_cast(n->getd()) == 0); | |
3684 #else | |
3685 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
3686 #endif | |
3687 match(ConD); | |
3688 | |
3689 op_cost(0); | |
3690 format %{ %} | |
3691 interface(CONST_INTER); | |
3692 %} | |
3693 | |
3694 // Float Immediate | |
3695 operand immF() %{ | |
3696 match(ConF); | |
3697 | |
3698 op_cost(20); | |
3699 format %{ %} | |
3700 interface(CONST_INTER); | |
3701 %} | |
3702 | |
3703 // Float Immediate: 0 | |
3704 operand immF0() %{ | |
3705 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
3706 match(ConF); | |
3707 | |
3708 op_cost(0); | |
3709 format %{ %} | |
3710 interface(CONST_INTER); | |
3711 %} | |
3712 | |
3713 // Integer Register Operands | |
3714 // Integer Register | |
3715 operand iRegI() %{ | |
3716 constraint(ALLOC_IN_RC(int_reg)); | |
3717 match(RegI); | |
3718 | |
3719 match(notemp_iRegI); | |
3720 match(g1RegI); | |
3721 match(o0RegI); | |
3722 match(iRegIsafe); | |
3723 | |
3724 format %{ %} | |
3725 interface(REG_INTER); | |
3726 %} | |
3727 | |
3728 operand notemp_iRegI() %{ | |
3729 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
3730 match(RegI); | |
3731 | |
3732 match(o0RegI); | |
3733 | |
3734 format %{ %} | |
3735 interface(REG_INTER); | |
3736 %} | |
3737 | |
3738 operand o0RegI() %{ | |
3739 constraint(ALLOC_IN_RC(o0_regI)); | |
3740 match(iRegI); | |
3741 | |
3742 format %{ %} | |
3743 interface(REG_INTER); | |
3744 %} | |
3745 | |
3746 // Pointer Register | |
3747 operand iRegP() %{ | |
3748 constraint(ALLOC_IN_RC(ptr_reg)); | |
3749 match(RegP); | |
3750 | |
3751 match(lock_ptr_RegP); | |
3752 match(g1RegP); | |
3753 match(g2RegP); | |
3754 match(g3RegP); | |
3755 match(g4RegP); | |
3756 match(i0RegP); | |
3757 match(o0RegP); | |
3758 match(o1RegP); | |
3759 match(l7RegP); | |
3760 | |
3761 format %{ %} | |
3762 interface(REG_INTER); | |
3763 %} | |
3764 | |
3765 operand sp_ptr_RegP() %{ | |
3766 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
3767 match(RegP); | |
3768 match(iRegP); | |
3769 | |
3770 format %{ %} | |
3771 interface(REG_INTER); | |
3772 %} | |
3773 | |
3774 operand lock_ptr_RegP() %{ | |
3775 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
3776 match(RegP); | |
3777 match(i0RegP); | |
3778 match(o0RegP); | |
3779 match(o1RegP); | |
3780 match(l7RegP); | |
3781 | |
3782 format %{ %} | |
3783 interface(REG_INTER); | |
3784 %} | |
3785 | |
3786 operand g1RegP() %{ | |
3787 constraint(ALLOC_IN_RC(g1_regP)); | |
3788 match(iRegP); | |
3789 | |
3790 format %{ %} | |
3791 interface(REG_INTER); | |
3792 %} | |
3793 | |
3794 operand g2RegP() %{ | |
3795 constraint(ALLOC_IN_RC(g2_regP)); | |
3796 match(iRegP); | |
3797 | |
3798 format %{ %} | |
3799 interface(REG_INTER); | |
3800 %} | |
3801 | |
3802 operand g3RegP() %{ | |
3803 constraint(ALLOC_IN_RC(g3_regP)); | |
3804 match(iRegP); | |
3805 | |
3806 format %{ %} | |
3807 interface(REG_INTER); | |
3808 %} | |
3809 | |
3810 operand g1RegI() %{ | |
3811 constraint(ALLOC_IN_RC(g1_regI)); | |
3812 match(iRegI); | |
3813 | |
3814 format %{ %} | |
3815 interface(REG_INTER); | |
3816 %} | |
3817 | |
3818 operand g3RegI() %{ | |
3819 constraint(ALLOC_IN_RC(g3_regI)); | |
3820 match(iRegI); | |
3821 | |
3822 format %{ %} | |
3823 interface(REG_INTER); | |
3824 %} | |
3825 | |
3826 operand g4RegI() %{ | |
3827 constraint(ALLOC_IN_RC(g4_regI)); | |
3828 match(iRegI); | |
3829 | |
3830 format %{ %} | |
3831 interface(REG_INTER); | |
3832 %} | |
3833 | |
3834 operand g4RegP() %{ | |
3835 constraint(ALLOC_IN_RC(g4_regP)); | |
3836 match(iRegP); | |
3837 | |
3838 format %{ %} | |
3839 interface(REG_INTER); | |
3840 %} | |
3841 | |
3842 operand i0RegP() %{ | |
3843 constraint(ALLOC_IN_RC(i0_regP)); | |
3844 match(iRegP); | |
3845 | |
3846 format %{ %} | |
3847 interface(REG_INTER); | |
3848 %} | |
3849 | |
3850 operand o0RegP() %{ | |
3851 constraint(ALLOC_IN_RC(o0_regP)); | |
3852 match(iRegP); | |
3853 | |
3854 format %{ %} | |
3855 interface(REG_INTER); | |
3856 %} | |
3857 | |
3858 operand o1RegP() %{ | |
3859 constraint(ALLOC_IN_RC(o1_regP)); | |
3860 match(iRegP); | |
3861 | |
3862 format %{ %} | |
3863 interface(REG_INTER); | |
3864 %} | |
3865 | |
3866 operand o2RegP() %{ | |
3867 constraint(ALLOC_IN_RC(o2_regP)); | |
3868 match(iRegP); | |
3869 | |
3870 format %{ %} | |
3871 interface(REG_INTER); | |
3872 %} | |
3873 | |
3874 operand o7RegP() %{ | |
3875 constraint(ALLOC_IN_RC(o7_regP)); | |
3876 match(iRegP); | |
3877 | |
3878 format %{ %} | |
3879 interface(REG_INTER); | |
3880 %} | |
3881 | |
3882 operand l7RegP() %{ | |
3883 constraint(ALLOC_IN_RC(l7_regP)); | |
3884 match(iRegP); | |
3885 | |
3886 format %{ %} | |
3887 interface(REG_INTER); | |
3888 %} | |
3889 | |
3890 operand o7RegI() %{ | |
3891 constraint(ALLOC_IN_RC(o7_regI)); | |
3892 match(iRegI); | |
3893 | |
3894 format %{ %} | |
3895 interface(REG_INTER); | |
3896 %} | |
3897 | |
113
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3898 operand iRegN() %{ |
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3899 constraint(ALLOC_IN_RC(int_reg)); |
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3900 match(RegN); |
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3901 |
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3902 format %{ %} |
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3903 interface(REG_INTER); |
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3904 %} |
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3905 |
0 | 3906 // Long Register |
3907 operand iRegL() %{ | |
3908 constraint(ALLOC_IN_RC(long_reg)); | |
3909 match(RegL); | |
3910 | |
3911 format %{ %} | |
3912 interface(REG_INTER); | |
3913 %} | |
3914 | |
3915 operand o2RegL() %{ | |
3916 constraint(ALLOC_IN_RC(o2_regL)); | |
3917 match(iRegL); | |
3918 | |
3919 format %{ %} | |
3920 interface(REG_INTER); | |
3921 %} | |
3922 | |
3923 operand o7RegL() %{ | |
3924 constraint(ALLOC_IN_RC(o7_regL)); | |
3925 match(iRegL); | |
3926 | |
3927 format %{ %} | |
3928 interface(REG_INTER); | |
3929 %} | |
3930 | |
3931 operand g1RegL() %{ | |
3932 constraint(ALLOC_IN_RC(g1_regL)); | |
3933 match(iRegL); | |
3934 | |
3935 format %{ %} | |
3936 interface(REG_INTER); | |
3937 %} | |
3938 | |
420
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3939 operand g3RegL() %{ |
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3940 constraint(ALLOC_IN_RC(g3_regL)); |
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3941 match(iRegL); |
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3942 |
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3943 format %{ %} |
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3944 interface(REG_INTER); |
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3945 %} |
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3946 |
0 | 3947 // Int Register safe |
3948 // This is 64bit safe | |
3949 operand iRegIsafe() %{ | |
3950 constraint(ALLOC_IN_RC(long_reg)); | |
3951 | |
3952 match(iRegI); | |
3953 | |
3954 format %{ %} | |
3955 interface(REG_INTER); | |
3956 %} | |
3957 | |
3958 // Condition Code Flag Register | |
3959 operand flagsReg() %{ | |
3960 constraint(ALLOC_IN_RC(int_flags)); | |
3961 match(RegFlags); | |
3962 | |
3963 format %{ "ccr" %} // both ICC and XCC | |
3964 interface(REG_INTER); | |
3965 %} | |
3966 | |
3967 // Condition Code Register, unsigned comparisons. | |
3968 operand flagsRegU() %{ | |
3969 constraint(ALLOC_IN_RC(int_flags)); | |
3970 match(RegFlags); | |
3971 | |
3972 format %{ "icc_U" %} | |
3973 interface(REG_INTER); | |
3974 %} | |
3975 | |
3976 // Condition Code Register, pointer comparisons. | |
3977 operand flagsRegP() %{ | |
3978 constraint(ALLOC_IN_RC(int_flags)); | |
3979 match(RegFlags); | |
3980 | |
3981 #ifdef _LP64 | |
3982 format %{ "xcc_P" %} | |
3983 #else | |
3984 format %{ "icc_P" %} | |
3985 #endif | |
3986 interface(REG_INTER); | |
3987 %} | |
3988 | |
3989 // Condition Code Register, long comparisons. | |
3990 operand flagsRegL() %{ | |
3991 constraint(ALLOC_IN_RC(int_flags)); | |
3992 match(RegFlags); | |
3993 | |
3994 format %{ "xcc_L" %} | |
3995 interface(REG_INTER); | |
3996 %} | |
3997 | |
3998 // Condition Code Register, floating comparisons, unordered same as "less". | |
3999 operand flagsRegF() %{ | |
4000 constraint(ALLOC_IN_RC(float_flags)); | |
4001 match(RegFlags); | |
4002 match(flagsRegF0); | |
4003 | |
4004 format %{ %} | |
4005 interface(REG_INTER); | |
4006 %} | |
4007 | |
4008 operand flagsRegF0() %{ | |
4009 constraint(ALLOC_IN_RC(float_flag0)); | |
4010 match(RegFlags); | |
4011 | |
4012 format %{ %} | |
4013 interface(REG_INTER); | |
4014 %} | |
4015 | |
4016 | |
4017 // Condition Code Flag Register used by long compare | |
4018 operand flagsReg_long_LTGE() %{ | |
4019 constraint(ALLOC_IN_RC(int_flags)); | |
4020 match(RegFlags); | |
4021 format %{ "icc_LTGE" %} | |
4022 interface(REG_INTER); | |
4023 %} | |
4024 operand flagsReg_long_EQNE() %{ | |
4025 constraint(ALLOC_IN_RC(int_flags)); | |
4026 match(RegFlags); | |
4027 format %{ "icc_EQNE" %} | |
4028 interface(REG_INTER); | |
4029 %} | |
4030 operand flagsReg_long_LEGT() %{ | |
4031 constraint(ALLOC_IN_RC(int_flags)); | |
4032 match(RegFlags); | |
4033 format %{ "icc_LEGT" %} | |
4034 interface(REG_INTER); | |
4035 %} | |
4036 | |
4037 | |
4038 operand regD() %{ | |
4039 constraint(ALLOC_IN_RC(dflt_reg)); | |
4040 match(RegD); | |
4041 | |
551 | 4042 match(regD_low); |
4043 | |
0 | 4044 format %{ %} |
4045 interface(REG_INTER); | |
4046 %} | |
4047 | |
4048 operand regF() %{ | |
4049 constraint(ALLOC_IN_RC(sflt_reg)); | |
4050 match(RegF); | |
4051 | |
4052 format %{ %} | |
4053 interface(REG_INTER); | |
4054 %} | |
4055 | |
4056 operand regD_low() %{ | |
4057 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
551 | 4058 match(regD); |
0 | 4059 |
4060 format %{ %} | |
4061 interface(REG_INTER); | |
4062 %} | |
4063 | |
4064 // Special Registers | |
4065 | |
4066 // Method Register | |
4067 operand inline_cache_regP(iRegP reg) %{ | |
4068 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
4069 match(reg); | |
4070 format %{ %} | |
4071 interface(REG_INTER); | |
4072 %} | |
4073 | |
4074 operand interpreter_method_oop_regP(iRegP reg) %{ | |
4075 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
4076 match(reg); | |
4077 format %{ %} | |
4078 interface(REG_INTER); | |
4079 %} | |
4080 | |
4081 | |
4082 //----------Complex Operands--------------------------------------------------- | |
4083 // Indirect Memory Reference | |
4084 operand indirect(sp_ptr_RegP reg) %{ | |
4085 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4086 match(reg); | |
4087 | |
4088 op_cost(100); | |
4089 format %{ "[$reg]" %} | |
4090 interface(MEMORY_INTER) %{ | |
4091 base($reg); | |
4092 index(0x0); | |
4093 scale(0x0); | |
4094 disp(0x0); | |
4095 %} | |
4096 %} | |
4097 | |
785 | 4098 // Indirect with simm13 Offset |
0 | 4099 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
4100 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4101 match(AddP reg offset); | |
4102 | |
4103 op_cost(100); | |
4104 format %{ "[$reg + $offset]" %} | |
4105 interface(MEMORY_INTER) %{ | |
4106 base($reg); | |
4107 index(0x0); | |
4108 scale(0x0); | |
4109 disp($offset); | |
4110 %} | |
4111 %} | |
4112 | |
785 | 4113 // Indirect with simm13 Offset minus 7 |
4114 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ | |
4115 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4116 match(AddP reg offset); | |
4117 | |
4118 op_cost(100); | |
4119 format %{ "[$reg + $offset]" %} | |
4120 interface(MEMORY_INTER) %{ | |
4121 base($reg); | |
4122 index(0x0); | |
4123 scale(0x0); | |
4124 disp($offset); | |
4125 %} | |
4126 %} | |
4127 | |
0 | 4128 // Note: Intel has a swapped version also, like this: |
4129 //operand indOffsetX(iRegI reg, immP offset) %{ | |
4130 // constraint(ALLOC_IN_RC(int_reg)); | |
4131 // match(AddP offset reg); | |
4132 // | |
4133 // op_cost(100); | |
4134 // format %{ "[$reg + $offset]" %} | |
4135 // interface(MEMORY_INTER) %{ | |
4136 // base($reg); | |
4137 // index(0x0); | |
4138 // scale(0x0); | |
4139 // disp($offset); | |
4140 // %} | |
4141 //%} | |
4142 //// However, it doesn't make sense for SPARC, since | |
4143 // we have no particularly good way to embed oops in | |
4144 // single instructions. | |
4145 | |
4146 // Indirect with Register Index | |
4147 operand indIndex(iRegP addr, iRegX index) %{ | |
4148 constraint(ALLOC_IN_RC(ptr_reg)); | |
4149 match(AddP addr index); | |
4150 | |
4151 op_cost(100); | |
4152 format %{ "[$addr + $index]" %} | |
4153 interface(MEMORY_INTER) %{ | |
4154 base($addr); | |
4155 index($index); | |
4156 scale(0x0); | |
4157 disp(0x0); | |
4158 %} | |
4159 %} | |
4160 | |
4161 //----------Special Memory Operands-------------------------------------------- | |
4162 // Stack Slot Operand - This operand is used for loading and storing temporary | |
4163 // values on the stack where a match requires a value to | |
4164 // flow through memory. | |
4165 operand stackSlotI(sRegI reg) %{ | |
4166 constraint(ALLOC_IN_RC(stack_slots)); | |
4167 op_cost(100); | |
4168 //match(RegI); | |
4169 format %{ "[$reg]" %} | |
4170 interface(MEMORY_INTER) %{ | |
4171 base(0xE); // R_SP | |
4172 index(0x0); | |
4173 scale(0x0); | |
4174 disp($reg); // Stack Offset | |
4175 %} | |
4176 %} | |
4177 | |
4178 operand stackSlotP(sRegP reg) %{ | |
4179 constraint(ALLOC_IN_RC(stack_slots)); | |
4180 op_cost(100); | |
4181 //match(RegP); | |
4182 format %{ "[$reg]" %} | |
4183 interface(MEMORY_INTER) %{ | |
4184 base(0xE); // R_SP | |
4185 index(0x0); | |
4186 scale(0x0); | |
4187 disp($reg); // Stack Offset | |
4188 %} | |
4189 %} | |
4190 | |
4191 operand stackSlotF(sRegF reg) %{ | |
4192 constraint(ALLOC_IN_RC(stack_slots)); | |
4193 op_cost(100); | |
4194 //match(RegF); | |
4195 format %{ "[$reg]" %} | |
4196 interface(MEMORY_INTER) %{ | |
4197 base(0xE); // R_SP | |
4198 index(0x0); | |
4199 scale(0x0); | |
4200 disp($reg); // Stack Offset | |
4201 %} | |
4202 %} | |
4203 operand stackSlotD(sRegD reg) %{ | |
4204 constraint(ALLOC_IN_RC(stack_slots)); | |
4205 op_cost(100); | |
4206 //match(RegD); | |
4207 format %{ "[$reg]" %} | |
4208 interface(MEMORY_INTER) %{ | |
4209 base(0xE); // R_SP | |
4210 index(0x0); | |
4211 scale(0x0); | |
4212 disp($reg); // Stack Offset | |
4213 %} | |
4214 %} | |
4215 operand stackSlotL(sRegL reg) %{ | |
4216 constraint(ALLOC_IN_RC(stack_slots)); | |
4217 op_cost(100); | |
4218 //match(RegL); | |
4219 format %{ "[$reg]" %} | |
4220 interface(MEMORY_INTER) %{ | |
4221 base(0xE); // R_SP | |
4222 index(0x0); | |
4223 scale(0x0); | |
4224 disp($reg); // Stack Offset | |
4225 %} | |
4226 %} | |
4227 | |
4228 // Operands for expressing Control Flow | |
4229 // NOTE: Label is a predefined operand which should not be redefined in | |
4230 // the AD file. It is generically handled within the ADLC. | |
4231 | |
4232 //----------Conditional Branch Operands---------------------------------------- | |
4233 // Comparison Op - This is the operation of the comparison, and is limited to | |
4234 // the following set of codes: | |
4235 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
4236 // | |
4237 // Other attributes of the comparison, such as unsignedness, are specified | |
4238 // by the comparison instruction that sets a condition code flags register. | |
4239 // That result is represented by a flags operand whose subtype is appropriate | |
4240 // to the unsignedness (etc.) of the comparison. | |
4241 // | |
4242 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
4243 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
4244 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
4245 | |
4246 operand cmpOp() %{ | |
4247 match(Bool); | |
4248 | |
4249 format %{ "" %} | |
4250 interface(COND_INTER) %{ | |
4251 equal(0x1); | |
4252 not_equal(0x9); | |
4253 less(0x3); | |
4254 greater_equal(0xB); | |
4255 less_equal(0x2); | |
4256 greater(0xA); | |
12323 | 4257 overflow(0x7); |
4258 no_overflow(0xF); | |
0 | 4259 %} |
4260 %} | |
4261 | |
4262 // Comparison Op, unsigned | |
4263 operand cmpOpU() %{ | |
4264 match(Bool); | |
12323 | 4265 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4266 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
0 | 4267 |
4268 format %{ "u" %} | |
4269 interface(COND_INTER) %{ | |
4270 equal(0x1); | |
4271 not_equal(0x9); | |
4272 less(0x5); | |
4273 greater_equal(0xD); | |
4274 less_equal(0x4); | |
4275 greater(0xC); | |
12323 | 4276 overflow(0x7); |
4277 no_overflow(0xF); | |
0 | 4278 %} |
4279 %} | |
4280 | |
4281 // Comparison Op, pointer (same as unsigned) | |
4282 operand cmpOpP() %{ | |
4283 match(Bool); | |
12323 | 4284 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4285 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
0 | 4286 |
4287 format %{ "p" %} | |
4288 interface(COND_INTER) %{ | |
4289 equal(0x1); | |
4290 not_equal(0x9); | |
4291 less(0x5); | |
4292 greater_equal(0xD); | |
4293 less_equal(0x4); | |
4294 greater(0xC); | |
12323 | 4295 overflow(0x7); |
4296 no_overflow(0xF); | |
0 | 4297 %} |
4298 %} | |
4299 | |
4300 // Comparison Op, branch-register encoding | |
4301 operand cmpOp_reg() %{ | |
4302 match(Bool); | |
12323 | 4303 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4304 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
0 | 4305 |
4306 format %{ "" %} | |
4307 interface(COND_INTER) %{ | |
4308 equal (0x1); | |
4309 not_equal (0x5); | |
4310 less (0x3); | |
4311 greater_equal(0x7); | |
4312 less_equal (0x2); | |
4313 greater (0x6); | |
12323 | 4314 overflow(0x7); // not supported |
4315 no_overflow(0xF); // not supported | |
0 | 4316 %} |
4317 %} | |
4318 | |
4319 // Comparison Code, floating, unordered same as less | |
4320 operand cmpOpF() %{ | |
4321 match(Bool); | |
12323 | 4322 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4323 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
0 | 4324 |
4325 format %{ "fl" %} | |
4326 interface(COND_INTER) %{ | |
4327 equal(0x9); | |
4328 not_equal(0x1); | |
4329 less(0x3); | |
4330 greater_equal(0xB); | |
4331 less_equal(0xE); | |
4332 greater(0x6); | |
12323 | 4333 |
4334 overflow(0x7); // not supported | |
4335 no_overflow(0xF); // not supported | |
0 | 4336 %} |
4337 %} | |
4338 | |
4339 // Used by long compare | |
4340 operand cmpOp_commute() %{ | |
4341 match(Bool); | |
12323 | 4342 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4343 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
0 | 4344 |
4345 format %{ "" %} | |
4346 interface(COND_INTER) %{ | |
4347 equal(0x1); | |
4348 not_equal(0x9); | |
4349 less(0xA); | |
4350 greater_equal(0x2); | |
4351 less_equal(0xB); | |
4352 greater(0x3); | |
12323 | 4353 overflow(0x7); |
4354 no_overflow(0xF); | |
0 | 4355 %} |
4356 %} | |
4357 | |
4358 //----------OPERAND CLASSES---------------------------------------------------- | |
4359 // Operand Classes are groups of operands that are used to simplify | |
605 | 4360 // instruction definitions by not requiring the AD writer to specify separate |
0 | 4361 // instructions for every form of operand when the instruction accepts |
4362 // multiple operand types with the same basic encoding and format. The classic | |
4363 // case of this is memory operands. | |
4364 opclass memory( indirect, indOffset13, indIndex ); | |
1396
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4365 opclass indIndexMemory( indIndex ); |
0 | 4366 |
4367 //----------PIPELINE----------------------------------------------------------- | |
4368 pipeline %{ | |
4369 | |
4370 //----------ATTRIBUTES--------------------------------------------------------- | |
4371 attributes %{ | |
4372 fixed_size_instructions; // Fixed size instructions | |
4373 branch_has_delay_slot; // Branch has delay slot following | |
4374 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
4375 instruction_unit_size = 4; // An instruction is 4 bytes long | |
4376 instruction_fetch_unit_size = 16; // The processor fetches one line | |
4377 instruction_fetch_units = 1; // of 16 bytes | |
4378 | |
4379 // List of nop instructions | |
4380 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
4381 %} | |
4382 | |
4383 //----------RESOURCES---------------------------------------------------------- | |
4384 // Resources are the functional units available to the machine | |
4385 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
4386 | |
4387 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
4388 // Pipeline Description specifies the stages in the machine's pipeline | |
4389 | |
4390 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
4391 | |
4392 //----------PIPELINE CLASSES--------------------------------------------------- | |
4393 // Pipeline Classes describe the stages in which input and output are | |
4394 // referenced by the hardware pipeline. | |
4395 | |
4396 // Integer ALU reg-reg operation | |
4397 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4398 single_instruction; | |
4399 dst : E(write); | |
4400 src1 : R(read); | |
4401 src2 : R(read); | |
4402 IALU : R; | |
4403 %} | |
4404 | |
4405 // Integer ALU reg-reg long operation | |
4406 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
4407 instruction_count(2); | |
4408 dst : E(write); | |
4409 src1 : R(read); | |
4410 src2 : R(read); | |
4411 IALU : R; | |
4412 IALU : R; | |
4413 %} | |
4414 | |
4415 // Integer ALU reg-reg long dependent operation | |
4416 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
4417 instruction_count(1); multiple_bundles; | |
4418 dst : E(write); | |
4419 src1 : R(read); | |
4420 src2 : R(read); | |
4421 cr : E(write); | |
4422 IALU : R(2); | |
4423 %} | |
4424 | |
4425 // Integer ALU reg-imm operaion | |
4426 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4427 single_instruction; | |
4428 dst : E(write); | |
4429 src1 : R(read); | |
4430 IALU : R; | |
4431 %} | |
4432 | |
4433 // Integer ALU reg-reg operation with condition code | |
4434 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
4435 single_instruction; | |
4436 dst : E(write); | |
4437 cr : E(write); | |
4438 src1 : R(read); | |
4439 src2 : R(read); | |
4440 IALU : R; | |
4441 %} | |
4442 | |
4443 // Integer ALU reg-imm operation with condition code | |
4444 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
4445 single_instruction; | |
4446 dst : E(write); | |
4447 cr : E(write); | |
4448 src1 : R(read); | |
4449 IALU : R; | |
4450 %} | |
4451 | |
4452 // Integer ALU zero-reg operation | |
4453 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
4454 single_instruction; | |
4455 dst : E(write); | |
4456 src2 : R(read); | |
4457 IALU : R; | |
4458 %} | |
4459 | |
4460 // Integer ALU zero-reg operation with condition code only | |
4461 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
4462 single_instruction; | |
4463 cr : E(write); | |
4464 src : R(read); | |
4465 IALU : R; | |
4466 %} | |
4467 | |
4468 // Integer ALU reg-reg operation with condition code only | |
4469 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4470 single_instruction; | |
4471 cr : E(write); | |
4472 src1 : R(read); | |
4473 src2 : R(read); | |
4474 IALU : R; | |
4475 %} | |
4476 | |
4477 // Integer ALU reg-imm operation with condition code only | |
4478 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4479 single_instruction; | |
4480 cr : E(write); | |
4481 src1 : R(read); | |
4482 IALU : R; | |
4483 %} | |
4484 | |
4485 // Integer ALU reg-reg-zero operation with condition code only | |
4486 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
4487 single_instruction; | |
4488 cr : E(write); | |
4489 src1 : R(read); | |
4490 src2 : R(read); | |
4491 IALU : R; | |
4492 %} | |
4493 | |
4494 // Integer ALU reg-imm-zero operation with condition code only | |
4495 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
4496 single_instruction; | |
4497 cr : E(write); | |
4498 src1 : R(read); | |
4499 IALU : R; | |
4500 %} | |
4501 | |
4502 // Integer ALU reg-reg operation with condition code, src1 modified | |
4503 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4504 single_instruction; | |
4505 cr : E(write); | |
4506 src1 : E(write); | |
4507 src1 : R(read); | |
4508 src2 : R(read); | |
4509 IALU : R; | |
4510 %} | |
4511 | |
4512 // Integer ALU reg-imm operation with condition code, src1 modified | |
4513 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4514 single_instruction; | |
4515 cr : E(write); | |
4516 src1 : E(write); | |
4517 src1 : R(read); | |
4518 IALU : R; | |
4519 %} | |
4520 | |
4521 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
4522 multiple_bundles; | |
4523 dst : E(write)+4; | |
4524 cr : E(write); | |
4525 src1 : R(read); | |
4526 src2 : R(read); | |
4527 IALU : R(3); | |
4528 BR : R(2); | |
4529 %} | |
4530 | |
4531 // Integer ALU operation | |
4532 pipe_class ialu_none(iRegI dst) %{ | |
4533 single_instruction; | |
4534 dst : E(write); | |
4535 IALU : R; | |
4536 %} | |
4537 | |
4538 // Integer ALU reg operation | |
4539 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
4540 single_instruction; may_have_no_code; | |
4541 dst : E(write); | |
4542 src : R(read); | |
4543 IALU : R; | |
4544 %} | |
4545 | |
4546 // Integer ALU reg conditional operation | |
4547 // This instruction has a 1 cycle stall, and cannot execute | |
4548 // in the same cycle as the instruction setting the condition | |
4549 // code. We kludge this by pretending to read the condition code | |
4550 // 1 cycle earlier, and by marking the functional units as busy | |
4551 // for 2 cycles with the result available 1 cycle later than | |
4552 // is really the case. | |
4553 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
4554 single_instruction; | |
4555 op2_out : C(write); | |
4556 op1 : R(read); | |
4557 cr : R(read); // This is really E, with a 1 cycle stall | |
4558 BR : R(2); | |
4559 MS : R(2); | |
4560 %} | |
4561 | |
4562 #ifdef _LP64 | |
4563 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
4564 instruction_count(1); multiple_bundles; | |
4565 dst : C(write)+1; | |
4566 src : R(read)+1; | |
4567 IALU : R(1); | |
4568 BR : E(2); | |
4569 MS : E(2); | |
4570 %} | |
4571 #endif | |
4572 | |
4573 // Integer ALU reg operation | |
4574 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
4575 single_instruction; may_have_no_code; | |
4576 dst : E(write); | |
4577 src : R(read); | |
4578 IALU : R; | |
4579 %} | |
4580 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
4581 single_instruction; may_have_no_code; | |
4582 dst : E(write); | |
4583 src : R(read); | |
4584 IALU : R; | |
4585 %} | |
4586 | |
4587 // Two integer ALU reg operations | |
4588 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
4589 instruction_count(2); | |
4590 dst : E(write); | |
4591 src : R(read); | |
4592 A0 : R; | |
4593 A1 : R; | |
4594 %} | |
4595 | |
4596 // Two integer ALU reg operations | |
4597 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
4598 instruction_count(2); may_have_no_code; | |
4599 dst : E(write); | |
4600 src : R(read); | |
4601 A0 : R; | |
4602 A1 : R; | |
4603 %} | |
4604 | |
4605 // Integer ALU imm operation | |
4606 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
4607 single_instruction; | |
4608 dst : E(write); | |
4609 IALU : R; | |
4610 %} | |
4611 | |
4612 // Integer ALU reg-reg with carry operation | |
4613 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
4614 single_instruction; | |
4615 dst : E(write); | |
4616 src1 : R(read); | |
4617 src2 : R(read); | |
4618 IALU : R; | |
4619 %} | |
4620 | |
4621 // Integer ALU cc operation | |
4622 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
4623 single_instruction; | |
4624 dst : E(write); | |
4625 cc : R(read); | |
4626 IALU : R; | |
4627 %} | |
4628 | |
4629 // Integer ALU cc / second IALU operation | |
4630 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
4631 instruction_count(1); multiple_bundles; | |
4632 dst : E(write)+1; | |
4633 src : R(read); | |
4634 IALU : R; | |
4635 %} | |
4636 | |
4637 // Integer ALU cc / second IALU operation | |
4638 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
4639 instruction_count(1); multiple_bundles; | |
4640 dst : E(write)+1; | |
4641 p : R(read); | |
4642 q : R(read); | |
4643 IALU : R; | |
4644 %} | |
4645 | |
4646 // Integer ALU hi-lo-reg operation | |
4647 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
4648 instruction_count(1); multiple_bundles; | |
4649 dst : E(write)+1; | |
4650 IALU : R(2); | |
4651 %} | |
4652 | |
4653 // Float ALU hi-lo-reg operation (with temp) | |
4654 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
4655 instruction_count(1); multiple_bundles; | |
4656 dst : E(write)+1; | |
4657 IALU : R(2); | |
4658 %} | |
4659 | |
4660 // Long Constant | |
4661 pipe_class loadConL( iRegL dst, immL src ) %{ | |
4662 instruction_count(2); multiple_bundles; | |
4663 dst : E(write)+1; | |
4664 IALU : R(2); | |
4665 IALU : R(2); | |
4666 %} | |
4667 | |
4668 // Pointer Constant | |
4669 pipe_class loadConP( iRegP dst, immP src ) %{ | |
4670 instruction_count(0); multiple_bundles; | |
4671 fixed_latency(6); | |
4672 %} | |
4673 | |
4674 // Polling Address | |
4675 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
4676 #ifdef _LP64 | |
4677 instruction_count(0); multiple_bundles; | |
4678 fixed_latency(6); | |
4679 #else | |
4680 dst : E(write); | |
4681 IALU : R; | |
4682 #endif | |
4683 %} | |
4684 | |
4685 // Long Constant small | |
4686 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
4687 instruction_count(2); | |
4688 dst : E(write); | |
4689 IALU : R; | |
4690 IALU : R; | |
4691 %} | |
4692 | |
4693 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
4694 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
4695 instruction_count(1); multiple_bundles; | |
4696 src : R(read); | |
4697 dst : M(write)+1; | |
4698 IALU : R; | |
4699 MS : E; | |
4700 %} | |
4701 | |
4702 // Integer ALU nop operation | |
4703 pipe_class ialu_nop() %{ | |
4704 single_instruction; | |
4705 IALU : R; | |
4706 %} | |
4707 | |
4708 // Integer ALU nop operation | |
4709 pipe_class ialu_nop_A0() %{ | |
4710 single_instruction; | |
4711 A0 : R; | |
4712 %} | |
4713 | |
4714 // Integer ALU nop operation | |
4715 pipe_class ialu_nop_A1() %{ | |
4716 single_instruction; | |
4717 A1 : R; | |
4718 %} | |
4719 | |
4720 // Integer Multiply reg-reg operation | |
4721 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4722 single_instruction; | |
4723 dst : E(write); | |
4724 src1 : R(read); | |
4725 src2 : R(read); | |
4726 MS : R(5); | |
4727 %} | |
4728 | |
4729 // Integer Multiply reg-imm operation | |
4730 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4731 single_instruction; | |
4732 dst : E(write); | |
4733 src1 : R(read); | |
4734 MS : R(5); | |
4735 %} | |
4736 | |
4737 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4738 single_instruction; | |
4739 dst : E(write)+4; | |
4740 src1 : R(read); | |
4741 src2 : R(read); | |
4742 MS : R(6); | |
4743 %} | |
4744 | |
4745 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4746 single_instruction; | |
4747 dst : E(write)+4; | |
4748 src1 : R(read); | |
4749 MS : R(6); | |
4750 %} | |
4751 | |
4752 // Integer Divide reg-reg | |
4753 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
4754 instruction_count(1); multiple_bundles; | |
4755 dst : E(write); | |
4756 temp : E(write); | |
4757 src1 : R(read); | |
4758 src2 : R(read); | |
4759 temp : R(read); | |
4760 MS : R(38); | |
4761 %} | |
4762 | |
4763 // Integer Divide reg-imm | |
4764 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
4765 instruction_count(1); multiple_bundles; | |
4766 dst : E(write); | |
4767 temp : E(write); | |
4768 src1 : R(read); | |
4769 temp : R(read); | |
4770 MS : R(38); | |
4771 %} | |
4772 | |
4773 // Long Divide | |
4774 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4775 dst : E(write)+71; | |
4776 src1 : R(read); | |
4777 src2 : R(read)+1; | |
4778 MS : R(70); | |
4779 %} | |
4780 | |
4781 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4782 dst : E(write)+71; | |
4783 src1 : R(read); | |
4784 MS : R(70); | |
4785 %} | |
4786 | |
4787 // Floating Point Add Float | |
4788 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4789 single_instruction; | |
4790 dst : X(write); | |
4791 src1 : E(read); | |
4792 src2 : E(read); | |
4793 FA : R; | |
4794 %} | |
4795 | |
4796 // Floating Point Add Double | |
4797 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4798 single_instruction; | |
4799 dst : X(write); | |
4800 src1 : E(read); | |
4801 src2 : E(read); | |
4802 FA : R; | |
4803 %} | |
4804 | |
4805 // Floating Point Conditional Move based on integer flags | |
4806 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
4807 single_instruction; | |
4808 dst : X(write); | |
4809 src : E(read); | |
4810 cr : R(read); | |
4811 FA : R(2); | |
4812 BR : R(2); | |
4813 %} | |
4814 | |
4815 // Floating Point Conditional Move based on integer flags | |
4816 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
4817 single_instruction; | |
4818 dst : X(write); | |
4819 src : E(read); | |
4820 cr : R(read); | |
4821 FA : R(2); | |
4822 BR : R(2); | |
4823 %} | |
4824 | |
4825 // Floating Point Multiply Float | |
4826 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4827 single_instruction; | |
4828 dst : X(write); | |
4829 src1 : E(read); | |
4830 src2 : E(read); | |
4831 FM : R; | |
4832 %} | |
4833 | |
4834 // Floating Point Multiply Double | |
4835 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4836 single_instruction; | |
4837 dst : X(write); | |
4838 src1 : E(read); | |
4839 src2 : E(read); | |
4840 FM : R; | |
4841 %} | |
4842 | |
4843 // Floating Point Divide Float | |
4844 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4845 single_instruction; | |
4846 dst : X(write); | |
4847 src1 : E(read); | |
4848 src2 : E(read); | |
4849 FM : R; | |
4850 FDIV : C(14); | |
4851 %} | |
4852 | |
4853 // Floating Point Divide Double | |
4854 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4855 single_instruction; | |
4856 dst : X(write); | |
4857 src1 : E(read); | |
4858 src2 : E(read); | |
4859 FM : R; | |
4860 FDIV : C(17); | |
4861 %} | |
4862 | |
4863 // Floating Point Move/Negate/Abs Float | |
4864 pipe_class faddF_reg(regF dst, regF src) %{ | |
4865 single_instruction; | |
4866 dst : W(write); | |
4867 src : E(read); | |
4868 FA : R(1); | |
4869 %} | |
4870 | |
4871 // Floating Point Move/Negate/Abs Double | |
4872 pipe_class faddD_reg(regD dst, regD src) %{ | |
4873 single_instruction; | |
4874 dst : W(write); | |
4875 src : E(read); | |
4876 FA : R; | |
4877 %} | |
4878 | |
4879 // Floating Point Convert F->D | |
4880 pipe_class fcvtF2D(regD dst, regF src) %{ | |
4881 single_instruction; | |
4882 dst : X(write); | |
4883 src : E(read); | |
4884 FA : R; | |
4885 %} | |
4886 | |
4887 // Floating Point Convert I->D | |
4888 pipe_class fcvtI2D(regD dst, regF src) %{ | |
4889 single_instruction; | |
4890 dst : X(write); | |
4891 src : E(read); | |
4892 FA : R; | |
4893 %} | |
4894 | |
4895 // Floating Point Convert LHi->D | |
4896 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
4897 single_instruction; | |
4898 dst : X(write); | |
4899 src : E(read); | |
4900 FA : R; | |
4901 %} | |
4902 | |
4903 // Floating Point Convert L->D | |
4904 pipe_class fcvtL2D(regD dst, regF src) %{ | |
4905 single_instruction; | |
4906 dst : X(write); | |
4907 src : E(read); | |
4908 FA : R; | |
4909 %} | |
4910 | |
4911 // Floating Point Convert L->F | |
4912 pipe_class fcvtL2F(regD dst, regF src) %{ | |
4913 single_instruction; | |
4914 dst : X(write); | |
4915 src : E(read); | |
4916 FA : R; | |
4917 %} | |
4918 | |
4919 // Floating Point Convert D->F | |
4920 pipe_class fcvtD2F(regD dst, regF src) %{ | |
4921 single_instruction; | |
4922 dst : X(write); | |
4923 src : E(read); | |
4924 FA : R; | |
4925 %} | |
4926 | |
4927 // Floating Point Convert I->L | |
4928 pipe_class fcvtI2L(regD dst, regF src) %{ | |
4929 single_instruction; | |
4930 dst : X(write); | |
4931 src : E(read); | |
4932 FA : R; | |
4933 %} | |
4934 | |
4935 // Floating Point Convert D->F | |
4936 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
4937 instruction_count(1); multiple_bundles; | |
4938 dst : X(write)+6; | |
4939 src : E(read); | |
4940 FA : R; | |
4941 %} | |
4942 | |
4943 // Floating Point Convert D->L | |
4944 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
4945 instruction_count(1); multiple_bundles; | |
4946 dst : X(write)+6; | |
4947 src : E(read); | |
4948 FA : R; | |
4949 %} | |
4950 | |
4951 // Floating Point Convert F->I | |
4952 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
4953 instruction_count(1); multiple_bundles; | |
4954 dst : X(write)+6; | |
4955 src : E(read); | |
4956 FA : R; | |
4957 %} | |
4958 | |
4959 // Floating Point Convert F->L | |
4960 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
4961 instruction_count(1); multiple_bundles; | |
4962 dst : X(write)+6; | |
4963 src : E(read); | |
4964 FA : R; | |
4965 %} | |
4966 | |
4967 // Floating Point Convert I->F | |
4968 pipe_class fcvtI2F(regF dst, regF src) %{ | |
4969 single_instruction; | |
4970 dst : X(write); | |
4971 src : E(read); | |
4972 FA : R; | |
4973 %} | |
4974 | |
4975 // Floating Point Compare | |
4976 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
4977 single_instruction; | |
4978 cr : X(write); | |
4979 src1 : E(read); | |
4980 src2 : E(read); | |
4981 FA : R; | |
4982 %} | |
4983 | |
4984 // Floating Point Compare | |
4985 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
4986 single_instruction; | |
4987 cr : X(write); | |
4988 src1 : E(read); | |
4989 src2 : E(read); | |
4990 FA : R; | |
4991 %} | |
4992 | |
4993 // Floating Add Nop | |
4994 pipe_class fadd_nop() %{ | |
4995 single_instruction; | |
4996 FA : R; | |
4997 %} | |
4998 | |
4999 // Integer Store to Memory | |
5000 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
5001 single_instruction; | |
5002 mem : R(read); | |
5003 src : C(read); | |
5004 MS : R; | |
5005 %} | |
5006 | |
5007 // Integer Store to Memory | |
5008 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
5009 single_instruction; | |
5010 mem : R(read); | |
5011 src : C(read); | |
5012 MS : R; | |
5013 %} | |
5014 | |
5015 // Integer Store Zero to Memory | |
5016 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
5017 single_instruction; | |
5018 mem : R(read); | |
5019 MS : R; | |
5020 %} | |
5021 | |
5022 // Special Stack Slot Store | |
5023 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
5024 single_instruction; | |
5025 stkSlot : R(read); | |
5026 src : C(read); | |
5027 MS : R; | |
5028 %} | |
5029 | |
5030 // Special Stack Slot Store | |
5031 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
5032 instruction_count(2); multiple_bundles; | |
5033 stkSlot : R(read); | |
5034 src : C(read); | |
5035 MS : R(2); | |
5036 %} | |
5037 | |
5038 // Float Store | |
5039 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
5040 single_instruction; | |
5041 mem : R(read); | |
5042 src : C(read); | |
5043 MS : R; | |
5044 %} | |
5045 | |
5046 // Float Store | |
5047 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
5048 single_instruction; | |
5049 mem : R(read); | |
5050 MS : R; | |
5051 %} | |
5052 | |
5053 // Double Store | |
5054 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
5055 instruction_count(1); | |
5056 mem : R(read); | |
5057 src : C(read); | |
5058 MS : R; | |
5059 %} | |
5060 | |
5061 // Double Store | |
5062 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
5063 single_instruction; | |
5064 mem : R(read); | |
5065 MS : R; | |
5066 %} | |
5067 | |
5068 // Special Stack Slot Float Store | |
5069 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
5070 single_instruction; | |
5071 stkSlot : R(read); | |
5072 src : C(read); | |
5073 MS : R; | |
5074 %} | |
5075 | |
5076 // Special Stack Slot Double Store | |
5077 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
5078 single_instruction; | |
5079 stkSlot : R(read); | |
5080 src : C(read); | |
5081 MS : R; | |
5082 %} | |
5083 | |
5084 // Integer Load (when sign bit propagation not needed) | |
5085 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
5086 single_instruction; | |
5087 mem : R(read); | |
5088 dst : C(write); | |
5089 MS : R; | |
5090 %} | |
5091 | |
5092 // Integer Load from stack operand | |
5093 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
5094 single_instruction; | |
5095 mem : R(read); | |
5096 dst : C(write); | |
5097 MS : R; | |
5098 %} | |
5099 | |
5100 // Integer Load (when sign bit propagation or masking is needed) | |
5101 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
5102 single_instruction; | |
5103 mem : R(read); | |
5104 dst : M(write); | |
5105 MS : R; | |
5106 %} | |
5107 | |
5108 // Float Load | |
5109 pipe_class floadF_mem(regF dst, memory mem) %{ | |
5110 single_instruction; | |
5111 mem : R(read); | |
5112 dst : M(write); | |
5113 MS : R; | |
5114 %} | |
5115 | |
5116 // Float Load | |
5117 pipe_class floadD_mem(regD dst, memory mem) %{ | |
5118 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
5119 mem : R(read); | |
5120 dst : M(write); | |
5121 MS : R; | |
5122 %} | |
5123 | |
5124 // Float Load | |
5125 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
5126 single_instruction; | |
5127 stkSlot : R(read); | |
5128 dst : M(write); | |
5129 MS : R; | |
5130 %} | |
5131 | |
5132 // Float Load | |
5133 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
5134 single_instruction; | |
5135 stkSlot : R(read); | |
5136 dst : M(write); | |
5137 MS : R; | |
5138 %} | |
5139 | |
5140 // Memory Nop | |
5141 pipe_class mem_nop() %{ | |
5142 single_instruction; | |
5143 MS : R; | |
5144 %} | |
5145 | |
5146 pipe_class sethi(iRegP dst, immI src) %{ | |
5147 single_instruction; | |
5148 dst : E(write); | |
5149 IALU : R; | |
5150 %} | |
5151 | |
5152 pipe_class loadPollP(iRegP poll) %{ | |
5153 single_instruction; | |
5154 poll : R(read); | |
5155 MS : R; | |
5156 %} | |
5157 | |
5158 pipe_class br(Universe br, label labl) %{ | |
5159 single_instruction_with_delay_slot; | |
5160 BR : R; | |
5161 %} | |
5162 | |
5163 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
5164 single_instruction_with_delay_slot; | |
5165 cr : E(read); | |
5166 BR : R; | |
5167 %} | |
5168 | |
5169 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
5170 single_instruction_with_delay_slot; | |
5171 op1 : E(read); | |
5172 BR : R; | |
5173 MS : R; | |
5174 %} | |
5175 | |
3851 | 5176 // Compare and branch |
5177 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ | |
5178 instruction_count(2); has_delay_slot; | |
5179 cr : E(write); | |
5180 src1 : R(read); | |
5181 src2 : R(read); | |
5182 IALU : R; | |
5183 BR : R; | |
5184 %} | |
5185 | |
5186 // Compare and branch | |
5187 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ | |
5188 instruction_count(2); has_delay_slot; | |
5189 cr : E(write); | |
5190 src1 : R(read); | |
5191 IALU : R; | |
5192 BR : R; | |
5193 %} | |
5194 | |
5195 // Compare and branch using cbcond | |
5196 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ | |
5197 single_instruction; | |
5198 src1 : E(read); | |
5199 src2 : E(read); | |
5200 IALU : R; | |
5201 BR : R; | |
5202 %} | |
5203 | |
5204 // Compare and branch using cbcond | |
5205 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ | |
5206 single_instruction; | |
5207 src1 : E(read); | |
5208 IALU : R; | |
5209 BR : R; | |
5210 %} | |
5211 | |
0 | 5212 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ |
5213 single_instruction_with_delay_slot; | |
5214 cr : E(read); | |
5215 BR : R; | |
5216 %} | |
5217 | |
5218 pipe_class br_nop() %{ | |
5219 single_instruction; | |
5220 BR : R; | |
5221 %} | |
5222 | |
5223 pipe_class simple_call(method meth) %{ | |
5224 instruction_count(2); multiple_bundles; force_serialization; | |
5225 fixed_latency(100); | |
5226 BR : R(1); | |
5227 MS : R(1); | |
5228 A0 : R(1); | |
5229 %} | |
5230 | |
5231 pipe_class compiled_call(method meth) %{ | |
5232 instruction_count(1); multiple_bundles; force_serialization; | |
5233 fixed_latency(100); | |
5234 MS : R(1); | |
5235 %} | |
5236 | |
5237 pipe_class call(method meth) %{ | |
5238 instruction_count(0); multiple_bundles; force_serialization; | |
5239 fixed_latency(100); | |
5240 %} | |
5241 | |
5242 pipe_class tail_call(Universe ignore, label labl) %{ | |
5243 single_instruction; has_delay_slot; | |
5244 fixed_latency(100); | |
5245 BR : R(1); | |
5246 MS : R(1); | |
5247 %} | |
5248 | |
5249 pipe_class ret(Universe ignore) %{ | |
5250 single_instruction; has_delay_slot; | |
5251 BR : R(1); | |
5252 MS : R(1); | |
5253 %} | |
5254 | |
5255 pipe_class ret_poll(g3RegP poll) %{ | |
5256 instruction_count(3); has_delay_slot; | |
5257 poll : E(read); | |
5258 MS : R; | |
5259 %} | |
5260 | |
5261 // The real do-nothing guy | |
5262 pipe_class empty( ) %{ | |
5263 instruction_count(0); | |
5264 %} | |
5265 | |
5266 pipe_class long_memory_op() %{ | |
5267 instruction_count(0); multiple_bundles; force_serialization; | |
5268 fixed_latency(25); | |
5269 MS : R(1); | |
5270 %} | |
5271 | |
5272 // Check-cast | |
5273 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
5274 array : R(read); | |
5275 match : R(read); | |
5276 IALU : R(2); | |
5277 BR : R(2); | |
5278 MS : R; | |
5279 %} | |
5280 | |
5281 // Convert FPU flags into +1,0,-1 | |
5282 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
5283 src1 : E(read); | |
5284 src2 : E(read); | |
5285 dst : E(write); | |
5286 FA : R; | |
5287 MS : R(2); | |
5288 BR : R(2); | |
5289 %} | |
5290 | |
5291 // Compare for p < q, and conditionally add y | |
5292 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
5293 p : E(read); | |
5294 q : E(read); | |
5295 y : E(read); | |
5296 IALU : R(3) | |
5297 %} | |
5298 | |
5299 // Perform a compare, then move conditionally in a branch delay slot. | |
5300 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
5301 src2 : E(read); | |
5302 srcdst : E(read); | |
5303 IALU : R; | |
5304 BR : R; | |
5305 %} | |
5306 | |
5307 // Define the class for the Nop node | |
5308 define %{ | |
5309 MachNop = ialu_nop; | |
5310 %} | |
5311 | |
5312 %} | |
5313 | |
5314 //----------INSTRUCTIONS------------------------------------------------------- | |
5315 | |
5316 //------------Special Stack Slot instructions - no match rules----------------- | |
5317 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
5318 // No match rule to avoid chain rule match. | |
5319 effect(DEF dst, USE src); | |
5320 ins_cost(MEMORY_REF_COST); | |
5321 size(4); | |
5322 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
5323 opcode(Assembler::ldf_op3); | |
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5324 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5325 ins_pipe(floadF_stk); |
5326 %} | |
5327 | |
5328 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
5329 // No match rule to avoid chain rule match. | |
5330 effect(DEF dst, USE src); | |
5331 ins_cost(MEMORY_REF_COST); | |
5332 size(4); | |
5333 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
5334 opcode(Assembler::lddf_op3); | |
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5335 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5336 ins_pipe(floadD_stk); |
5337 %} | |
5338 | |
5339 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
5340 // No match rule to avoid chain rule match. | |
5341 effect(DEF dst, USE src); | |
5342 ins_cost(MEMORY_REF_COST); | |
5343 size(4); | |
5344 format %{ "STF $src,$dst\t! regF to stkI" %} | |
5345 opcode(Assembler::stf_op3); | |
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5346 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5347 ins_pipe(fstoreF_stk_reg); |
5348 %} | |
5349 | |
5350 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
5351 // No match rule to avoid chain rule match. | |
5352 effect(DEF dst, USE src); | |
5353 ins_cost(MEMORY_REF_COST); | |
5354 size(4); | |
5355 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
5356 opcode(Assembler::stdf_op3); | |
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5357 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5358 ins_pipe(fstoreD_stk_reg); |
5359 %} | |
5360 | |
5361 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
5362 effect(DEF dst, USE src); | |
5363 ins_cost(MEMORY_REF_COST*2); | |
5364 size(8); | |
5365 format %{ "STW $src,$dst.hi\t! long\n\t" | |
5366 "STW R_G0,$dst.lo" %} | |
5367 opcode(Assembler::stw_op3); | |
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5368 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
0 | 5369 ins_pipe(lstoreI_stk_reg); |
5370 %} | |
5371 | |
5372 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
5373 // No match rule to avoid chain rule match. | |
5374 effect(DEF dst, USE src); | |
5375 ins_cost(MEMORY_REF_COST); | |
5376 size(4); | |
5377 format %{ "STX $src,$dst\t! regL to stkD" %} | |
5378 opcode(Assembler::stx_op3); | |
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5379 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5380 ins_pipe(istore_stk_reg); |
5381 %} | |
5382 | |
5383 //---------- Chain stack slots between similar types -------- | |
5384 | |
5385 // Load integer from stack slot | |
5386 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
5387 match(Set dst src); | |
5388 ins_cost(MEMORY_REF_COST); | |
5389 | |
5390 size(4); | |
5391 format %{ "LDUW $src,$dst\t!stk" %} | |
5392 opcode(Assembler::lduw_op3); | |
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5393 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5394 ins_pipe(iload_mem); |
5395 %} | |
5396 | |
5397 // Store integer to stack slot | |
5398 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
5399 match(Set dst src); | |
5400 ins_cost(MEMORY_REF_COST); | |
5401 | |
5402 size(4); | |
5403 format %{ "STW $src,$dst\t!stk" %} | |
5404 opcode(Assembler::stw_op3); | |
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5405 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5406 ins_pipe(istore_mem_reg); |
5407 %} | |
5408 | |
5409 // Load long from stack slot | |
5410 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
5411 match(Set dst src); | |
5412 | |
5413 ins_cost(MEMORY_REF_COST); | |
5414 size(4); | |
5415 format %{ "LDX $src,$dst\t! long" %} | |
5416 opcode(Assembler::ldx_op3); | |
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5417 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5418 ins_pipe(iload_mem); |
5419 %} | |
5420 | |
5421 // Store long to stack slot | |
5422 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
5423 match(Set dst src); | |
5424 | |
5425 ins_cost(MEMORY_REF_COST); | |
5426 size(4); | |
5427 format %{ "STX $src,$dst\t! long" %} | |
5428 opcode(Assembler::stx_op3); | |
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5429 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5430 ins_pipe(istore_mem_reg); |
5431 %} | |
5432 | |
5433 #ifdef _LP64 | |
5434 // Load pointer from stack slot, 64-bit encoding | |
5435 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5436 match(Set dst src); | |
5437 ins_cost(MEMORY_REF_COST); | |
5438 size(4); | |
5439 format %{ "LDX $src,$dst\t!ptr" %} | |
5440 opcode(Assembler::ldx_op3); | |
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5441 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5442 ins_pipe(iload_mem); |
5443 %} | |
5444 | |
5445 // Store pointer to stack slot | |
5446 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5447 match(Set dst src); | |
5448 ins_cost(MEMORY_REF_COST); | |
5449 size(4); | |
5450 format %{ "STX $src,$dst\t!ptr" %} | |
5451 opcode(Assembler::stx_op3); | |
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5452 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5453 ins_pipe(istore_mem_reg); |
5454 %} | |
5455 #else // _LP64 | |
5456 // Load pointer from stack slot, 32-bit encoding | |
5457 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5458 match(Set dst src); | |
5459 ins_cost(MEMORY_REF_COST); | |
5460 format %{ "LDUW $src,$dst\t!ptr" %} | |
5461 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
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5462 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5463 ins_pipe(iload_mem); |
5464 %} | |
5465 | |
5466 // Store pointer to stack slot | |
5467 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5468 match(Set dst src); | |
5469 ins_cost(MEMORY_REF_COST); | |
5470 format %{ "STW $src,$dst\t!ptr" %} | |
5471 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
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5472 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5473 ins_pipe(istore_mem_reg); |
5474 %} | |
5475 #endif // _LP64 | |
5476 | |
5477 //------------Special Nop instructions for bundling - no match rules----------- | |
5478 // Nop using the A0 functional unit | |
5479 instruct Nop_A0() %{ | |
5480 ins_cost(0); | |
5481 | |
5482 format %{ "NOP ! Alu Pipeline" %} | |
5483 opcode(Assembler::or_op3, Assembler::arith_op); | |
5484 ins_encode( form2_nop() ); | |
5485 ins_pipe(ialu_nop_A0); | |
5486 %} | |
5487 | |
5488 // Nop using the A1 functional unit | |
5489 instruct Nop_A1( ) %{ | |
5490 ins_cost(0); | |
5491 | |
5492 format %{ "NOP ! Alu Pipeline" %} | |
5493 opcode(Assembler::or_op3, Assembler::arith_op); | |
5494 ins_encode( form2_nop() ); | |
5495 ins_pipe(ialu_nop_A1); | |
5496 %} | |
5497 | |
5498 // Nop using the memory functional unit | |
5499 instruct Nop_MS( ) %{ | |
5500 ins_cost(0); | |
5501 | |
5502 format %{ "NOP ! Memory Pipeline" %} | |
5503 ins_encode( emit_mem_nop ); | |
5504 ins_pipe(mem_nop); | |
5505 %} | |
5506 | |
5507 // Nop using the floating add functional unit | |
5508 instruct Nop_FA( ) %{ | |
5509 ins_cost(0); | |
5510 | |
5511 format %{ "NOP ! Floating Add Pipeline" %} | |
5512 ins_encode( emit_fadd_nop ); | |
5513 ins_pipe(fadd_nop); | |
5514 %} | |
5515 | |
5516 // Nop using the branch functional unit | |
5517 instruct Nop_BR( ) %{ | |
5518 ins_cost(0); | |
5519 | |
5520 format %{ "NOP ! Branch Pipeline" %} | |
5521 ins_encode( emit_br_nop ); | |
5522 ins_pipe(br_nop); | |
5523 %} | |
5524 | |
5525 //----------Load/Store/Move Instructions--------------------------------------- | |
5526 //----------Load Instructions-------------------------------------------------- | |
5527 // Load Byte (8bit signed) | |
5528 instruct loadB(iRegI dst, memory mem) %{ | |
5529 match(Set dst (LoadB mem)); | |
5530 ins_cost(MEMORY_REF_COST); | |
5531 | |
5532 size(4); | |
624 | 5533 format %{ "LDSB $mem,$dst\t! byte" %} |
727 | 5534 ins_encode %{ |
5535 __ ldsb($mem$$Address, $dst$$Register); | |
5536 %} | |
624 | 5537 ins_pipe(iload_mask_mem); |
5538 %} | |
5539 | |
5540 // Load Byte (8bit signed) into a Long Register | |
5541 instruct loadB2L(iRegL dst, memory mem) %{ | |
5542 match(Set dst (ConvI2L (LoadB mem))); | |
5543 ins_cost(MEMORY_REF_COST); | |
5544 | |
5545 size(4); | |
5546 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
727 | 5547 ins_encode %{ |
5548 __ ldsb($mem$$Address, $dst$$Register); | |
5549 %} | |
0 | 5550 ins_pipe(iload_mask_mem); |
5551 %} | |
5552 | |
624 | 5553 // Load Unsigned Byte (8bit UNsigned) into an int reg |
5554 instruct loadUB(iRegI dst, memory mem) %{ | |
5555 match(Set dst (LoadUB mem)); | |
0 | 5556 ins_cost(MEMORY_REF_COST); |
5557 | |
5558 size(4); | |
624 | 5559 format %{ "LDUB $mem,$dst\t! ubyte" %} |
727 | 5560 ins_encode %{ |
5561 __ ldub($mem$$Address, $dst$$Register); | |
5562 %} | |
824 | 5563 ins_pipe(iload_mem); |
624 | 5564 %} |
5565 | |
5566 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
5567 instruct loadUB2L(iRegL dst, memory mem) %{ | |
5568 match(Set dst (ConvI2L (LoadUB mem))); | |
5569 ins_cost(MEMORY_REF_COST); | |
5570 | |
5571 size(4); | |
5572 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
727 | 5573 ins_encode %{ |
5574 __ ldub($mem$$Address, $dst$$Register); | |
5575 %} | |
824 | 5576 ins_pipe(iload_mem); |
5577 %} | |
5578 | |
5579 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register | |
5580 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ | |
5581 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
5582 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5583 | |
5584 size(2*4); | |
5585 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" | |
5586 "AND $dst,$mask,$dst" %} | |
5587 ins_encode %{ | |
5588 __ ldub($mem$$Address, $dst$$Register); | |
5589 __ and3($dst$$Register, $mask$$constant, $dst$$Register); | |
5590 %} | |
5591 ins_pipe(iload_mem); | |
0 | 5592 %} |
5593 | |
624 | 5594 // Load Short (16bit signed) |
5595 instruct loadS(iRegI dst, memory mem) %{ | |
5596 match(Set dst (LoadS mem)); | |
5597 ins_cost(MEMORY_REF_COST); | |
5598 | |
5599 size(4); | |
5600 format %{ "LDSH $mem,$dst\t! short" %} | |
727 | 5601 ins_encode %{ |
5602 __ ldsh($mem$$Address, $dst$$Register); | |
5603 %} | |
624 | 5604 ins_pipe(iload_mask_mem); |
5605 %} | |
5606 | |
785 | 5607 // Load Short (16 bit signed) to Byte (8 bit signed) |
5608 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5609 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
5610 ins_cost(MEMORY_REF_COST); | |
5611 | |
5612 size(4); | |
5613 | |
5614 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} | |
5615 ins_encode %{ | |
5616 __ ldsb($mem$$Address, $dst$$Register, 1); | |
5617 %} | |
5618 ins_pipe(iload_mask_mem); | |
5619 %} | |
5620 | |
624 | 5621 // Load Short (16bit signed) into a Long Register |
5622 instruct loadS2L(iRegL dst, memory mem) %{ | |
5623 match(Set dst (ConvI2L (LoadS mem))); | |
0 | 5624 ins_cost(MEMORY_REF_COST); |
5625 | |
5626 size(4); | |
624 | 5627 format %{ "LDSH $mem,$dst\t! short -> long" %} |
727 | 5628 ins_encode %{ |
5629 __ ldsh($mem$$Address, $dst$$Register); | |
5630 %} | |
624 | 5631 ins_pipe(iload_mask_mem); |
5632 %} | |
5633 | |
5634 // Load Unsigned Short/Char (16bit UNsigned) | |
5635 instruct loadUS(iRegI dst, memory mem) %{ | |
5636 match(Set dst (LoadUS mem)); | |
5637 ins_cost(MEMORY_REF_COST); | |
5638 | |
5639 size(4); | |
5640 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
727 | 5641 ins_encode %{ |
5642 __ lduh($mem$$Address, $dst$$Register); | |
5643 %} | |
824 | 5644 ins_pipe(iload_mem); |
0 | 5645 %} |
5646 | |
785 | 5647 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
5648 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5649 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
5650 ins_cost(MEMORY_REF_COST); | |
5651 | |
5652 size(4); | |
5653 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} | |
5654 ins_encode %{ | |
5655 __ ldsb($mem$$Address, $dst$$Register, 1); | |
5656 %} | |
5657 ins_pipe(iload_mask_mem); | |
5658 %} | |
5659 | |
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|
5660 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
624 | 5661 instruct loadUS2L(iRegL dst, memory mem) %{ |
5662 match(Set dst (ConvI2L (LoadUS mem))); | |
0 | 5663 ins_cost(MEMORY_REF_COST); |
5664 | |
5665 size(4); | |
624 | 5666 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
727 | 5667 ins_encode %{ |
5668 __ lduh($mem$$Address, $dst$$Register); | |
5669 %} | |
824 | 5670 ins_pipe(iload_mem); |
5671 %} | |
5672 | |
5673 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register | |
5674 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
5675 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5676 ins_cost(MEMORY_REF_COST); | |
5677 | |
5678 size(4); | |
5679 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} | |
5680 ins_encode %{ | |
5681 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE | |
5682 %} | |
5683 ins_pipe(iload_mem); | |
5684 %} | |
5685 | |
5686 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register | |
5687 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
5688 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5689 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5690 | |
5691 size(2*4); | |
5692 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" | |
5693 "AND $dst,$mask,$dst" %} | |
5694 ins_encode %{ | |
5695 Register Rdst = $dst$$Register; | |
5696 __ lduh($mem$$Address, Rdst); | |
5697 __ and3(Rdst, $mask$$constant, Rdst); | |
5698 %} | |
5699 ins_pipe(iload_mem); | |
5700 %} | |
5701 | |
5702 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register | |
5703 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | |
5704 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5705 effect(TEMP dst, TEMP tmp); | |
5706 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
5707 | |
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diff
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|
5708 size((3+1)*4); // set may use two instructions. |
824 | 5709 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
5710 "SET $mask,$tmp\n\t" | |
5711 "AND $dst,$tmp,$dst" %} | |
5712 ins_encode %{ | |
5713 Register Rdst = $dst$$Register; | |
5714 Register Rtmp = $tmp$$Register; | |
5715 __ lduh($mem$$Address, Rdst); | |
5716 __ set($mask$$constant, Rtmp); | |
5717 __ and3(Rdst, Rtmp, Rdst); | |
5718 %} | |
5719 ins_pipe(iload_mem); | |
0 | 5720 %} |
5721 | |
5722 // Load Integer | |
5723 instruct loadI(iRegI dst, memory mem) %{ | |
5724 match(Set dst (LoadI mem)); | |
5725 ins_cost(MEMORY_REF_COST); | |
624 | 5726 |
5727 size(4); | |
5728 format %{ "LDUW $mem,$dst\t! int" %} | |
727 | 5729 ins_encode %{ |
5730 __ lduw($mem$$Address, $dst$$Register); | |
5731 %} | |
624 | 5732 ins_pipe(iload_mem); |
5733 %} | |
5734 | |
785 | 5735 // Load Integer to Byte (8 bit signed) |
5736 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5737 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
5738 ins_cost(MEMORY_REF_COST); | |
5739 | |
5740 size(4); | |
5741 | |
5742 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} | |
5743 ins_encode %{ | |
5744 __ ldsb($mem$$Address, $dst$$Register, 3); | |
5745 %} | |
5746 ins_pipe(iload_mask_mem); | |
5747 %} | |
5748 | |
5749 // Load Integer to Unsigned Byte (8 bit UNsigned) | |
5750 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ | |
5751 match(Set dst (AndI (LoadI mem) mask)); | |
5752 ins_cost(MEMORY_REF_COST); | |
5753 | |
5754 size(4); | |
5755 | |
5756 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} | |
5757 ins_encode %{ | |
5758 __ ldub($mem$$Address, $dst$$Register, 3); | |
5759 %} | |
5760 ins_pipe(iload_mask_mem); | |
5761 %} | |
5762 | |
5763 // Load Integer to Short (16 bit signed) | |
5764 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ | |
5765 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
5766 ins_cost(MEMORY_REF_COST); | |
5767 | |
5768 size(4); | |
5769 | |
5770 format %{ "LDSH $mem+2,$dst\t! int -> short" %} | |
5771 ins_encode %{ | |
5772 __ ldsh($mem$$Address, $dst$$Register, 2); | |
5773 %} | |
5774 ins_pipe(iload_mask_mem); | |
5775 %} | |
5776 | |
5777 // Load Integer to Unsigned Short (16 bit UNsigned) | |
5778 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ | |
5779 match(Set dst (AndI (LoadI mem) mask)); | |
5780 ins_cost(MEMORY_REF_COST); | |
5781 | |
5782 size(4); | |
5783 | |
5784 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} | |
5785 ins_encode %{ | |
5786 __ lduh($mem$$Address, $dst$$Register, 2); | |
5787 %} | |
5788 ins_pipe(iload_mask_mem); | |
5789 %} | |
5790 | |
624 | 5791 // Load Integer into a Long Register |
5792 instruct loadI2L(iRegL dst, memory mem) %{ | |
5793 match(Set dst (ConvI2L (LoadI mem))); | |
5794 ins_cost(MEMORY_REF_COST); | |
5795 | |
5796 size(4); | |
5797 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
727 | 5798 ins_encode %{ |
5799 __ ldsw($mem$$Address, $dst$$Register); | |
5800 %} | |
824 | 5801 ins_pipe(iload_mask_mem); |
5802 %} | |
5803 | |
5804 // Load Integer with mask 0xFF into a Long Register | |
5805 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
5806 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5807 ins_cost(MEMORY_REF_COST); | |
5808 | |
5809 size(4); | |
5810 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} | |
5811 ins_encode %{ | |
5812 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE | |
5813 %} | |
5814 ins_pipe(iload_mem); | |
5815 %} | |
5816 | |
5817 // Load Integer with mask 0xFFFF into a Long Register | |
5818 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ | |
5819 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5820 ins_cost(MEMORY_REF_COST); | |
5821 | |
5822 size(4); | |
5823 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} | |
5824 ins_encode %{ | |
5825 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | |
5826 %} | |
5827 ins_pipe(iload_mem); | |
5828 %} | |
5829 | |
5830 // Load Integer with a 13-bit mask into a Long Register | |
5831 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
5832 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5833 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5834 | |
5835 size(2*4); | |
5836 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" | |
5837 "AND $dst,$mask,$dst" %} | |
5838 ins_encode %{ | |
5839 Register Rdst = $dst$$Register; | |
5840 __ lduw($mem$$Address, Rdst); | |
5841 __ and3(Rdst, $mask$$constant, Rdst); | |
5842 %} | |
5843 ins_pipe(iload_mem); | |
5844 %} | |
5845 | |
5846 // Load Integer with a 32-bit mask into a Long Register | |
5847 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ | |
5848 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5849 effect(TEMP dst, TEMP tmp); | |
5850 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
5851 | |
951
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5852 size((3+1)*4); // set may use two instructions. |
824 | 5853 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" |
5854 "SET $mask,$tmp\n\t" | |
5855 "AND $dst,$tmp,$dst" %} | |
5856 ins_encode %{ | |
5857 Register Rdst = $dst$$Register; | |
5858 Register Rtmp = $tmp$$Register; | |
5859 __ lduw($mem$$Address, Rdst); | |
5860 __ set($mask$$constant, Rtmp); | |
5861 __ and3(Rdst, Rtmp, Rdst); | |
5862 %} | |
624 | 5863 ins_pipe(iload_mem); |
5864 %} | |
5865 | |
5866 // Load Unsigned Integer into a Long Register | |
6849 | 5867 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{ |
5868 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
624 | 5869 ins_cost(MEMORY_REF_COST); |
5870 | |
5871 size(4); | |
5872 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
727 | 5873 ins_encode %{ |
5874 __ lduw($mem$$Address, $dst$$Register); | |
5875 %} | |
0 | 5876 ins_pipe(iload_mem); |
5877 %} | |
5878 | |
5879 // Load Long - aligned | |
5880 instruct loadL(iRegL dst, memory mem ) %{ | |
5881 match(Set dst (LoadL mem)); | |
5882 ins_cost(MEMORY_REF_COST); | |
624 | 5883 |
0 | 5884 size(4); |
5885 format %{ "LDX $mem,$dst\t! long" %} | |
727 | 5886 ins_encode %{ |
5887 __ ldx($mem$$Address, $dst$$Register); | |
5888 %} | |
0 | 5889 ins_pipe(iload_mem); |
5890 %} | |
5891 | |
5892 // Load Long - UNaligned | |
5893 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
5894 match(Set dst (LoadL_unaligned mem)); | |
5895 effect(KILL tmp); | |
5896 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
5897 size(16); | |
5898 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
5899 "\tLDUW $mem ,$dst\n" | |
5900 "\tSLLX #32, $dst, $dst\n" | |
5901 "\tOR $dst, R_O7, $dst" %} | |
5902 opcode(Assembler::lduw_op3); | |
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235
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|
5903 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
0 | 5904 ins_pipe(iload_mem); |
5905 %} | |
5906 | |
5907 // Load Range | |
5908 instruct loadRange(iRegI dst, memory mem) %{ | |
5909 match(Set dst (LoadRange mem)); | |
5910 ins_cost(MEMORY_REF_COST); | |
5911 | |
5912 size(4); | |
5913 format %{ "LDUW $mem,$dst\t! range" %} | |
5914 opcode(Assembler::lduw_op3); | |
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5915 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5916 ins_pipe(iload_mem); |
5917 %} | |
5918 | |
5919 // Load Integer into %f register (for fitos/fitod) | |
5920 instruct loadI_freg(regF dst, memory mem) %{ | |
5921 match(Set dst (LoadI mem)); | |
5922 ins_cost(MEMORY_REF_COST); | |
5923 size(4); | |
5924 | |
5925 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
5926 opcode(Assembler::ldf_op3); | |
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5927 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5928 ins_pipe(floadF_mem); |
5929 %} | |
5930 | |
5931 // Load Pointer | |
5932 instruct loadP(iRegP dst, memory mem) %{ | |
5933 match(Set dst (LoadP mem)); | |
5934 ins_cost(MEMORY_REF_COST); | |
5935 size(4); | |
5936 | |
5937 #ifndef _LP64 | |
5938 format %{ "LDUW $mem,$dst\t! ptr" %} | |
727 | 5939 ins_encode %{ |
5940 __ lduw($mem$$Address, $dst$$Register); | |
5941 %} | |
0 | 5942 #else |
5943 format %{ "LDX $mem,$dst\t! ptr" %} | |
727 | 5944 ins_encode %{ |
5945 __ ldx($mem$$Address, $dst$$Register); | |
5946 %} | |
0 | 5947 #endif |
5948 ins_pipe(iload_mem); | |
5949 %} | |
5950 | |
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|
5951 // Load Compressed Pointer |
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5952 instruct loadN(iRegN dst, memory mem) %{ |
727 | 5953 match(Set dst (LoadN mem)); |
5954 ins_cost(MEMORY_REF_COST); | |
5955 size(4); | |
5956 | |
5957 format %{ "LDUW $mem,$dst\t! compressed ptr" %} | |
5958 ins_encode %{ | |
5959 __ lduw($mem$$Address, $dst$$Register); | |
5960 %} | |
5961 ins_pipe(iload_mem); | |
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|
5962 %} |
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|
5963 |
0 | 5964 // Load Klass Pointer |
5965 instruct loadKlass(iRegP dst, memory mem) %{ | |
5966 match(Set dst (LoadKlass mem)); | |
5967 ins_cost(MEMORY_REF_COST); | |
5968 size(4); | |
5969 | |
5970 #ifndef _LP64 | |
5971 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
727 | 5972 ins_encode %{ |
5973 __ lduw($mem$$Address, $dst$$Register); | |
5974 %} | |
0 | 5975 #else |
5976 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
727 | 5977 ins_encode %{ |
5978 __ ldx($mem$$Address, $dst$$Register); | |
5979 %} | |
0 | 5980 #endif |
5981 ins_pipe(iload_mem); | |
5982 %} | |
5983 | |
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|
5984 // Load narrow Klass Pointer |
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5985 instruct loadNKlass(iRegN dst, memory mem) %{ |
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5986 match(Set dst (LoadNKlass mem)); |
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5987 ins_cost(MEMORY_REF_COST); |
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|
5988 size(4); |
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5989 |
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5990 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
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5991 ins_encode %{ |
727 | 5992 __ lduw($mem$$Address, $dst$$Register); |
113
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5993 %} |
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5994 ins_pipe(iload_mem); |
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5995 %} |
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5996 |
0 | 5997 // Load Double |
5998 instruct loadD(regD dst, memory mem) %{ | |
5999 match(Set dst (LoadD mem)); | |
6000 ins_cost(MEMORY_REF_COST); | |
6001 | |
6002 size(4); | |
6003 format %{ "LDDF $mem,$dst" %} | |
6004 opcode(Assembler::lddf_op3); | |
415
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6005 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 6006 ins_pipe(floadD_mem); |
6007 %} | |
6008 | |
6009 // Load Double - UNaligned | |
6010 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
6011 match(Set dst (LoadD_unaligned mem)); | |
6012 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
6013 size(8); | |
6014 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
6015 "\tLDF $mem+4,$dst.lo\t!" %} | |
6016 opcode(Assembler::ldf_op3); | |
6017 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
6018 ins_pipe(iload_mem); | |
6019 %} | |
6020 | |
6021 // Load Float | |
6022 instruct loadF(regF dst, memory mem) %{ | |
6023 match(Set dst (LoadF mem)); | |
6024 ins_cost(MEMORY_REF_COST); | |
6025 | |
6026 size(4); | |
6027 format %{ "LDF $mem,$dst" %} | |
6028 opcode(Assembler::ldf_op3); | |
415
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6029 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 6030 ins_pipe(floadF_mem); |
6031 %} | |
6032 | |
6033 // Load Constant | |
6034 instruct loadConI( iRegI dst, immI src ) %{ | |
6035 match(Set dst src); | |
6036 ins_cost(DEFAULT_COST * 3/2); | |
6037 format %{ "SET $src,$dst" %} | |
6038 ins_encode( Set32(src, dst) ); | |
6039 ins_pipe(ialu_hi_lo_reg); | |
6040 %} | |
6041 | |
6042 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
6043 match(Set dst src); | |
6044 | |
6045 size(4); | |
6046 format %{ "MOV $src,$dst" %} | |
6047 ins_encode( Set13( src, dst ) ); | |
6048 ins_pipe(ialu_imm); | |
6049 %} | |
6050 | |
2008 | 6051 #ifndef _LP64 |
6052 instruct loadConP(iRegP dst, immP con) %{ | |
6053 match(Set dst con); | |
6054 ins_cost(DEFAULT_COST * 3/2); | |
6055 format %{ "SET $con,$dst\t!ptr" %} | |
6056 ins_encode %{ | |
6725
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|
6057 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); |
2008 | 6058 intptr_t val = $con$$constant; |
6725
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|
6059 if (constant_reloc == relocInfo::oop_type) { |
2008 | 6060 __ set_oop_constant((jobject) val, $dst$$Register); |
6725
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|
6061 } else if (constant_reloc == relocInfo::metadata_type) { |
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6179
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|
6062 __ set_metadata_constant((Metadata*)val, $dst$$Register); |
2008 | 6063 } else { // non-oop pointers, e.g. card mark base, heap top |
6725
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|
6064 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); |
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|
6065 __ set(val, $dst$$Register); |
2008 | 6066 } |
6067 %} | |
6068 ins_pipe(loadConP); | |
6069 %} | |
6070 #else | |
6071 instruct loadConP_set(iRegP dst, immP_set con) %{ | |
6072 match(Set dst con); | |
0 | 6073 ins_cost(DEFAULT_COST * 3/2); |
2008 | 6074 format %{ "SET $con,$dst\t! ptr" %} |
6075 ins_encode %{ | |
6725
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|
6076 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); |
2008 | 6077 intptr_t val = $con$$constant; |
6725
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|
6078 if (constant_reloc == relocInfo::oop_type) { |
2008 | 6079 __ set_oop_constant((jobject) val, $dst$$Register); |
6725
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|
6080 } else if (constant_reloc == relocInfo::metadata_type) { |
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6179
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|
6081 __ set_metadata_constant((Metadata*)val, $dst$$Register); |
2008 | 6082 } else { // non-oop pointers, e.g. card mark base, heap top |
6725
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|
6083 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); |
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|
6084 __ set(val, $dst$$Register); |
2008 | 6085 } |
6086 %} | |
0 | 6087 ins_pipe(loadConP); |
2008 | 6088 %} |
6089 | |
6090 instruct loadConP_load(iRegP dst, immP_load con) %{ | |
6091 match(Set dst con); | |
6092 ins_cost(MEMORY_REF_COST); | |
6093 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} | |
6094 ins_encode %{ | |
2076
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|
6095 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
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|
6096 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); |
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|
6097 %} |
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|
6098 ins_pipe(loadConP); |
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|
6099 %} |
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|
6100 |
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diff
changeset
|
6101 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ |
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|
6102 match(Set dst con); |
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|
6103 ins_cost(DEFAULT_COST * 3/2); |
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diff
changeset
|
6104 format %{ "SET $con,$dst\t! non-oop ptr" %} |
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twisti
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|
6105 ins_encode %{ |
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diff
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|
6106 __ set($con$$constant, $dst$$Register); |
2008 | 6107 %} |
6108 ins_pipe(loadConP); | |
6109 %} | |
6110 #endif // _LP64 | |
0 | 6111 |
6112 instruct loadConP0(iRegP dst, immP0 src) %{ | |
6113 match(Set dst src); | |
6114 | |
6115 size(4); | |
6116 format %{ "CLR $dst\t!ptr" %} | |
2008 | 6117 ins_encode %{ |
6118 __ clr($dst$$Register); | |
6119 %} | |
0 | 6120 ins_pipe(ialu_imm); |
6121 %} | |
6122 | |
6123 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
6124 match(Set dst src); | |
6125 ins_cost(DEFAULT_COST); | |
6126 format %{ "SET $src,$dst\t!ptr" %} | |
6127 ins_encode %{ | |
727 | 6128 AddressLiteral polling_page(os::get_polling_page()); |
6129 __ sethi(polling_page, reg_to_register_object($dst$$reg)); | |
0 | 6130 %} |
6131 ins_pipe(loadConP_poll); | |
6132 %} | |
6133 | |
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|
6134 instruct loadConN0(iRegN dst, immN0 src) %{ |
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6135 match(Set dst src); |
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|
6136 |
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|
6137 size(4); |
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|
6138 format %{ "CLR $dst\t! compressed NULL ptr" %} |
2008 | 6139 ins_encode %{ |
6140 __ clr($dst$$Register); | |
6141 %} | |
164
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|
6142 ins_pipe(ialu_imm); |
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|
6143 %} |
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|
6144 |
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|
6145 instruct loadConN(iRegN dst, immN src) %{ |
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|
6146 match(Set dst src); |
164
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|
6147 ins_cost(DEFAULT_COST * 3/2); |
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|
6148 format %{ "SET $src,$dst\t! compressed ptr" %} |
113
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6149 ins_encode %{ |
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|
6150 Register dst = $dst$$Register; |
164
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|
6151 __ set_narrow_oop((jobject)$src$$constant, dst); |
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|
6152 %} |
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|
6153 ins_pipe(ialu_hi_lo_reg); |
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6154 %} |
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|
6155 |
6848
8e47bac5643a
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6823
diff
changeset
|
6156 instruct loadConNKlass(iRegN dst, immNKlass src) %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6157 match(Set dst src); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
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6823
diff
changeset
|
6158 ins_cost(DEFAULT_COST * 3/2); |
8e47bac5643a
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roland
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6823
diff
changeset
|
6159 format %{ "SET $src,$dst\t! compressed klass ptr" %} |
8e47bac5643a
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roland
parents:
6823
diff
changeset
|
6160 ins_encode %{ |
8e47bac5643a
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6823
diff
changeset
|
6161 Register dst = $dst$$Register; |
8e47bac5643a
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roland
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6823
diff
changeset
|
6162 __ set_narrow_klass((Klass*)$src$$constant, dst); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
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6823
diff
changeset
|
6163 %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6164 ins_pipe(ialu_hi_lo_reg); |
8e47bac5643a
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roland
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6823
diff
changeset
|
6165 %} |
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diff
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|
6166 |
2008 | 6167 // Materialize long value (predicated by immL_cheap). |
6168 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ | |
6169 match(Set dst con); | |
0 | 6170 effect(KILL tmp); |
2008 | 6171 ins_cost(DEFAULT_COST * 3); |
6172 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} | |
6173 ins_encode %{ | |
6174 __ set64($con$$constant, $dst$$Register, $tmp$$Register); | |
6175 %} | |
6176 ins_pipe(loadConL); | |
6177 %} | |
6178 | |
6179 // Load long value from constant table (predicated by immL_expensive). | |
6180 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ | |
6181 match(Set dst con); | |
6182 ins_cost(MEMORY_REF_COST); | |
6183 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} | |
6184 ins_encode %{ | |
2012
5fe0781a8560
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2008
diff
changeset
|
6185 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
5fe0781a8560
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diff
changeset
|
6186 __ ldx($constanttablebase, con_offset, $dst$$Register); |
2008 | 6187 %} |
0 | 6188 ins_pipe(loadConL); |
6189 %} | |
6190 | |
6191 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
6192 match(Set dst src); | |
6193 ins_cost(DEFAULT_COST); | |
6194 size(4); | |
6195 format %{ "CLR $dst\t! long" %} | |
6196 ins_encode( Set13( src, dst ) ); | |
6197 ins_pipe(ialu_imm); | |
6198 %} | |
6199 | |
6200 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
6201 match(Set dst src); | |
6202 ins_cost(DEFAULT_COST * 2); | |
6203 | |
6204 size(4); | |
6205 format %{ "MOV $src,$dst\t! long" %} | |
6206 ins_encode( Set13( src, dst ) ); | |
6207 ins_pipe(ialu_imm); | |
6208 %} | |
6209 | |
2012
5fe0781a8560
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kvn
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diff
changeset
|
6210 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ |
2008 | 6211 match(Set dst con); |
2012
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7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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2008
diff
changeset
|
6212 effect(KILL tmp); |
2008 | 6213 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} |
727 | 6214 ins_encode %{ |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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2008
diff
changeset
|
6215 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
5fe0781a8560
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kvn
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2008
diff
changeset
|
6216 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); |
727 | 6217 %} |
0 | 6218 ins_pipe(loadConFD); |
6219 %} | |
6220 | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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2008
diff
changeset
|
6221 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ |
2008 | 6222 match(Set dst con); |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6223 effect(KILL tmp); |
2008 | 6224 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} |
727 | 6225 ins_encode %{ |
732
fb4c18a2ec66
6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents:
727
diff
changeset
|
6226 // XXX This is a quick fix for 6833573. |
2008 | 6227 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); |
2012
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7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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2008
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changeset
|
6228 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
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2008
diff
changeset
|
6229 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
727 | 6230 %} |
0 | 6231 ins_pipe(loadConFD); |
6232 %} | |
6233 | |
6234 // Prefetch instructions. | |
6235 // Must be safe to execute with invalid address (cannot fault). | |
6236 | |
6237 instruct prefetchr( memory mem ) %{ | |
6238 match( PrefetchRead mem ); | |
6239 ins_cost(MEMORY_REF_COST); | |
3854 | 6240 size(4); |
0 | 6241 |
6242 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
6243 opcode(Assembler::prefetch_op3); | |
6244 ins_encode( form3_mem_prefetch_read( mem ) ); | |
6245 ins_pipe(iload_mem); | |
6246 %} | |
6247 | |
6248 instruct prefetchw( memory mem ) %{ | |
6249 match( PrefetchWrite mem ); | |
6250 ins_cost(MEMORY_REF_COST); | |
3854 | 6251 size(4); |
0 | 6252 |
6253 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
6254 opcode(Assembler::prefetch_op3); | |
6255 ins_encode( form3_mem_prefetch_write( mem ) ); | |
6256 ins_pipe(iload_mem); | |
6257 %} | |
6258 | |
3854 | 6259 // Prefetch instructions for allocation. |
6260 | |
6261 instruct prefetchAlloc( memory mem ) %{ | |
6262 predicate(AllocatePrefetchInstr == 0); | |
6263 match( PrefetchAllocation mem ); | |
6264 ins_cost(MEMORY_REF_COST); | |
6265 size(4); | |
6266 | |
6267 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %} | |
6268 opcode(Assembler::prefetch_op3); | |
6269 ins_encode( form3_mem_prefetch_write( mem ) ); | |
6270 ins_pipe(iload_mem); | |
6271 %} | |
6272 | |
6273 // Use BIS instruction to prefetch for allocation. | |
6274 // Could fault, need space at the end of TLAB. | |
6275 instruct prefetchAlloc_bis( iRegP dst ) %{ | |
6276 predicate(AllocatePrefetchInstr == 1); | |
6277 match( PrefetchAllocation dst ); | |
6278 ins_cost(MEMORY_REF_COST); | |
6279 size(4); | |
6280 | |
6281 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %} | |
6282 ins_encode %{ | |
6283 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); | |
1367
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6284 %} |
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6285 ins_pipe(istore_mem_reg); |
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6286 %} |
0 | 6287 |
3854 | 6288 // Next code is used for finding next cache line address to prefetch. |
6289 #ifndef _LP64 | |
6290 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{ | |
6291 match(Set dst (CastX2P (AndI (CastP2X src) mask))); | |
6292 ins_cost(DEFAULT_COST); | |
6293 size(4); | |
6294 | |
6295 format %{ "AND $src,$mask,$dst\t! next cache line address" %} | |
6296 ins_encode %{ | |
6297 __ and3($src$$Register, $mask$$constant, $dst$$Register); | |
6298 %} | |
6299 ins_pipe(ialu_reg_imm); | |
6300 %} | |
6301 #else | |
6302 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{ | |
6303 match(Set dst (CastX2P (AndL (CastP2X src) mask))); | |
6304 ins_cost(DEFAULT_COST); | |
6305 size(4); | |
6306 | |
6307 format %{ "AND $src,$mask,$dst\t! next cache line address" %} | |
6308 ins_encode %{ | |
6309 __ and3($src$$Register, $mask$$constant, $dst$$Register); | |
6310 %} | |
6311 ins_pipe(ialu_reg_imm); | |
6312 %} | |
6313 #endif | |
6314 | |
0 | 6315 //----------Store Instructions------------------------------------------------- |
6316 // Store Byte | |
6317 instruct storeB(memory mem, iRegI src) %{ | |
6318 match(Set mem (StoreB mem src)); | |
6319 ins_cost(MEMORY_REF_COST); | |
6320 | |
6321 size(4); | |
6322 format %{ "STB $src,$mem\t! byte" %} | |
6323 opcode(Assembler::stb_op3); | |
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6324 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6325 ins_pipe(istore_mem_reg); |
6326 %} | |
6327 | |
6328 instruct storeB0(memory mem, immI0 src) %{ | |
6329 match(Set mem (StoreB mem src)); | |
6330 ins_cost(MEMORY_REF_COST); | |
6331 | |
6332 size(4); | |
6333 format %{ "STB $src,$mem\t! byte" %} | |
6334 opcode(Assembler::stb_op3); | |
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6335 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6336 ins_pipe(istore_mem_zero); |
6337 %} | |
6338 | |
6339 instruct storeCM0(memory mem, immI0 src) %{ | |
6340 match(Set mem (StoreCM mem src)); | |
6341 ins_cost(MEMORY_REF_COST); | |
6342 | |
6343 size(4); | |
6344 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
6345 opcode(Assembler::stb_op3); | |
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6346 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6347 ins_pipe(istore_mem_zero); |
6348 %} | |
6349 | |
6350 // Store Char/Short | |
6351 instruct storeC(memory mem, iRegI src) %{ | |
6352 match(Set mem (StoreC mem src)); | |
6353 ins_cost(MEMORY_REF_COST); | |
6354 | |
6355 size(4); | |
6356 format %{ "STH $src,$mem\t! short" %} | |
6357 opcode(Assembler::sth_op3); | |
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6358 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6359 ins_pipe(istore_mem_reg); |
6360 %} | |
6361 | |
6362 instruct storeC0(memory mem, immI0 src) %{ | |
6363 match(Set mem (StoreC mem src)); | |
6364 ins_cost(MEMORY_REF_COST); | |
6365 | |
6366 size(4); | |
6367 format %{ "STH $src,$mem\t! short" %} | |
6368 opcode(Assembler::sth_op3); | |
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6369 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6370 ins_pipe(istore_mem_zero); |
6371 %} | |
6372 | |
6373 // Store Integer | |
6374 instruct storeI(memory mem, iRegI src) %{ | |
6375 match(Set mem (StoreI mem src)); | |
6376 ins_cost(MEMORY_REF_COST); | |
6377 | |
6378 size(4); | |
6379 format %{ "STW $src,$mem" %} | |
6380 opcode(Assembler::stw_op3); | |
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6381 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6382 ins_pipe(istore_mem_reg); |
6383 %} | |
6384 | |
6385 // Store Long | |
6386 instruct storeL(memory mem, iRegL src) %{ | |
6387 match(Set mem (StoreL mem src)); | |
6388 ins_cost(MEMORY_REF_COST); | |
6389 size(4); | |
6390 format %{ "STX $src,$mem\t! long" %} | |
6391 opcode(Assembler::stx_op3); | |
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6392 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6393 ins_pipe(istore_mem_reg); |
6394 %} | |
6395 | |
6396 instruct storeI0(memory mem, immI0 src) %{ | |
6397 match(Set mem (StoreI mem src)); | |
6398 ins_cost(MEMORY_REF_COST); | |
6399 | |
6400 size(4); | |
6401 format %{ "STW $src,$mem" %} | |
6402 opcode(Assembler::stw_op3); | |
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6403 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6404 ins_pipe(istore_mem_zero); |
6405 %} | |
6406 | |
6407 instruct storeL0(memory mem, immL0 src) %{ | |
6408 match(Set mem (StoreL mem src)); | |
6409 ins_cost(MEMORY_REF_COST); | |
6410 | |
6411 size(4); | |
6412 format %{ "STX $src,$mem" %} | |
6413 opcode(Assembler::stx_op3); | |
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6414 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6415 ins_pipe(istore_mem_zero); |
6416 %} | |
6417 | |
6418 // Store Integer from float register (used after fstoi) | |
6419 instruct storeI_Freg(memory mem, regF src) %{ | |
6420 match(Set mem (StoreI mem src)); | |
6421 ins_cost(MEMORY_REF_COST); | |
6422 | |
6423 size(4); | |
6424 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
6425 opcode(Assembler::stf_op3); | |
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6426 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6427 ins_pipe(fstoreF_mem_reg); |
6428 %} | |
6429 | |
6430 // Store Pointer | |
6431 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
6432 match(Set dst (StoreP dst src)); | |
6433 ins_cost(MEMORY_REF_COST); | |
6434 size(4); | |
6435 | |
6436 #ifndef _LP64 | |
6437 format %{ "STW $src,$dst\t! ptr" %} | |
6438 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6439 #else | |
6440 format %{ "STX $src,$dst\t! ptr" %} | |
6441 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6442 #endif | |
6443 ins_encode( form3_mem_reg( dst, src ) ); | |
6444 ins_pipe(istore_mem_spORreg); | |
6445 %} | |
6446 | |
6447 instruct storeP0(memory dst, immP0 src) %{ | |
6448 match(Set dst (StoreP dst src)); | |
6449 ins_cost(MEMORY_REF_COST); | |
6450 size(4); | |
6451 | |
6452 #ifndef _LP64 | |
6453 format %{ "STW $src,$dst\t! ptr" %} | |
6454 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6455 #else | |
6456 format %{ "STX $src,$dst\t! ptr" %} | |
6457 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6458 #endif | |
6459 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
6460 ins_pipe(istore_mem_zero); | |
6461 %} | |
6462 | |
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6463 // Store Compressed Pointer |
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6464 instruct storeN(memory dst, iRegN src) %{ |
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6465 match(Set dst (StoreN dst src)); |
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6466 ins_cost(MEMORY_REF_COST); |
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6467 size(4); |
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6468 |
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6469 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6470 ins_encode %{ |
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6471 Register base = as_Register($dst$$base); |
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6472 Register index = as_Register($dst$$index); |
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6473 Register src = $src$$Register; |
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6474 if (index != G0) { |
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6475 __ stw(src, base, index); |
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6476 } else { |
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6477 __ stw(src, base, $dst$$disp); |
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6478 } |
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|
6479 %} |
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6480 ins_pipe(istore_mem_spORreg); |
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6481 %} |
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|
6482 |
6848
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diff
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|
6483 instruct storeNKlass(memory dst, iRegN src) %{ |
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diff
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|
6484 match(Set dst (StoreNKlass dst src)); |
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diff
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|
6485 ins_cost(MEMORY_REF_COST); |
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diff
changeset
|
6486 size(4); |
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diff
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|
6487 |
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|
6488 format %{ "STW $src,$dst\t! compressed klass ptr" %} |
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diff
changeset
|
6489 ins_encode %{ |
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|
6490 Register base = as_Register($dst$$base); |
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diff
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|
6491 Register index = as_Register($dst$$index); |
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diff
changeset
|
6492 Register src = $src$$Register; |
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diff
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|
6493 if (index != G0) { |
8e47bac5643a
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diff
changeset
|
6494 __ stw(src, base, index); |
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diff
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|
6495 } else { |
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diff
changeset
|
6496 __ stw(src, base, $dst$$disp); |
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diff
changeset
|
6497 } |
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diff
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|
6498 %} |
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diff
changeset
|
6499 ins_pipe(istore_mem_spORreg); |
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|
6500 %} |
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|
6501 |
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6502 instruct storeN0(memory dst, immN0 src) %{ |
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6503 match(Set dst (StoreN dst src)); |
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6504 ins_cost(MEMORY_REF_COST); |
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6505 size(4); |
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6506 |
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|
6507 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6508 ins_encode %{ |
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6509 Register base = as_Register($dst$$base); |
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6510 Register index = as_Register($dst$$index); |
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6511 if (index != G0) { |
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6512 __ stw(0, base, index); |
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6513 } else { |
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6514 __ stw(0, base, $dst$$disp); |
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|
6515 } |
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|
6516 %} |
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|
6517 ins_pipe(istore_mem_zero); |
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6518 %} |
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6519 |
0 | 6520 // Store Double |
6521 instruct storeD( memory mem, regD src) %{ | |
6522 match(Set mem (StoreD mem src)); | |
6523 ins_cost(MEMORY_REF_COST); | |
6524 | |
6525 size(4); | |
6526 format %{ "STDF $src,$mem" %} | |
6527 opcode(Assembler::stdf_op3); | |
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6528 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6529 ins_pipe(fstoreD_mem_reg); |
6530 %} | |
6531 | |
6532 instruct storeD0( memory mem, immD0 src) %{ | |
6533 match(Set mem (StoreD mem src)); | |
6534 ins_cost(MEMORY_REF_COST); | |
6535 | |
6536 size(4); | |
6537 format %{ "STX $src,$mem" %} | |
6538 opcode(Assembler::stx_op3); | |
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6539 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6540 ins_pipe(fstoreD_mem_zero); |
6541 %} | |
6542 | |
6543 // Store Float | |
6544 instruct storeF( memory mem, regF src) %{ | |
6545 match(Set mem (StoreF mem src)); | |
6546 ins_cost(MEMORY_REF_COST); | |
6547 | |
6548 size(4); | |
6549 format %{ "STF $src,$mem" %} | |
6550 opcode(Assembler::stf_op3); | |
415
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|
6551 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6552 ins_pipe(fstoreF_mem_reg); |
6553 %} | |
6554 | |
6555 instruct storeF0( memory mem, immF0 src) %{ | |
6556 match(Set mem (StoreF mem src)); | |
6557 ins_cost(MEMORY_REF_COST); | |
6558 | |
6559 size(4); | |
6560 format %{ "STW $src,$mem\t! storeF0" %} | |
6561 opcode(Assembler::stw_op3); | |
415
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|
6562 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6563 ins_pipe(fstoreF_mem_zero); |
6564 %} | |
6565 | |
113
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81
diff
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|
6566 // Convert oop pointer into compressed form |
ba764ed4b6f2
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diff
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|
6567 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
221
1e026f8da827
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diff
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|
6568 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
113
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|
6569 match(Set dst (EncodeP src)); |
124
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6689060: Escape Analysis does not work with Compressed Oops
kvn
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113
diff
changeset
|
6570 format %{ "encode_heap_oop $src, $dst" %} |
113
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81
diff
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|
6571 ins_encode %{ |
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changeset
|
6572 __ encode_heap_oop($src$$Register, $dst$$Register); |
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|
6573 %} |
ba764ed4b6f2
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diff
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|
6574 ins_pipe(ialu_reg); |
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diff
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|
6575 %} |
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|
6576 |
124
b130b98db9cf
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113
diff
changeset
|
6577 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
221
1e026f8da827
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parents:
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diff
changeset
|
6578 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6579 match(Set dst (EncodeP src)); |
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
6580 format %{ "encode_heap_oop_not_null $src, $dst" %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6581 ins_encode %{ |
b130b98db9cf
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kvn
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113
diff
changeset
|
6582 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6583 %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6584 ins_pipe(ialu_reg); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6585 %} |
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
6586 |
113
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diff
changeset
|
6587 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
182
44abbb0d4c18
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diff
changeset
|
6588 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
44abbb0d4c18
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parents:
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diff
changeset
|
6589 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
113
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diff
changeset
|
6590 match(Set dst (DecodeN src)); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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diff
changeset
|
6591 format %{ "decode_heap_oop $src, $dst" %} |
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diff
changeset
|
6592 ins_encode %{ |
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changeset
|
6593 __ decode_heap_oop($src$$Register, $dst$$Register); |
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|
6594 %} |
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diff
changeset
|
6595 ins_pipe(ialu_reg); |
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81
diff
changeset
|
6596 %} |
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81
diff
changeset
|
6597 |
124
b130b98db9cf
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parents:
113
diff
changeset
|
6598 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
182
44abbb0d4c18
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kvn
parents:
181
diff
changeset
|
6599 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
44abbb0d4c18
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kvn
parents:
181
diff
changeset
|
6600 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
124
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
6601 match(Set dst (DecodeN src)); |
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kvn
parents:
113
diff
changeset
|
6602 format %{ "decode_heap_oop_not_null $src, $dst" %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6603 ins_encode %{ |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6604 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6605 %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6606 ins_pipe(ialu_reg); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6607 %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6608 |
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6609 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6610 match(Set dst (EncodePKlass src)); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6611 format %{ "encode_klass_not_null $src, $dst" %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6612 ins_encode %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6613 __ encode_klass_not_null($src$$Register, $dst$$Register); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6614 %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6615 ins_pipe(ialu_reg); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6616 %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6617 |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6618 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6619 match(Set dst (DecodeNKlass src)); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6620 format %{ "decode_klass_not_null $src, $dst" %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6621 ins_encode %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6622 __ decode_klass_not_null($src$$Register, $dst$$Register); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6623 %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6624 ins_pipe(ialu_reg); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6625 %} |
113
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coleenp
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diff
changeset
|
6626 |
0 | 6627 //----------MemBar Instructions----------------------------------------------- |
6628 // Memory barrier flavors | |
6629 | |
6630 instruct membar_acquire() %{ | |
6631 match(MemBarAcquire); | |
6632 ins_cost(4*MEMORY_REF_COST); | |
6633 | |
6634 size(0); | |
6635 format %{ "MEMBAR-acquire" %} | |
6636 ins_encode( enc_membar_acquire ); | |
6637 ins_pipe(long_memory_op); | |
6638 %} | |
6639 | |
6640 instruct membar_acquire_lock() %{ | |
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6641 match(MemBarAcquireLock); |
0 | 6642 ins_cost(0); |
6643 | |
6644 size(0); | |
6645 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
6646 ins_encode( ); | |
6647 ins_pipe(empty); | |
6648 %} | |
6649 | |
6650 instruct membar_release() %{ | |
6651 match(MemBarRelease); | |
6652 ins_cost(4*MEMORY_REF_COST); | |
6653 | |
6654 size(0); | |
6655 format %{ "MEMBAR-release" %} | |
6656 ins_encode( enc_membar_release ); | |
6657 ins_pipe(long_memory_op); | |
6658 %} | |
6659 | |
6660 instruct membar_release_lock() %{ | |
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6661 match(MemBarReleaseLock); |
0 | 6662 ins_cost(0); |
6663 | |
6664 size(0); | |
6665 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
6666 ins_encode( ); | |
6667 ins_pipe(empty); | |
6668 %} | |
6669 | |
6670 instruct membar_volatile() %{ | |
6671 match(MemBarVolatile); | |
6672 ins_cost(4*MEMORY_REF_COST); | |
6673 | |
6674 size(4); | |
6675 format %{ "MEMBAR-volatile" %} | |
6676 ins_encode( enc_membar_volatile ); | |
6677 ins_pipe(long_memory_op); | |
6678 %} | |
6679 | |
6680 instruct unnecessary_membar_volatile() %{ | |
6681 match(MemBarVolatile); | |
6682 predicate(Matcher::post_store_load_barrier(n)); | |
6683 ins_cost(0); | |
6684 | |
6685 size(0); | |
6686 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
6687 ins_encode( ); | |
6688 ins_pipe(empty); | |
6689 %} | |
6690 | |
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6691 instruct membar_storestore() %{ |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6692 match(MemBarStoreStore); |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6693 ins_cost(0); |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6694 |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6695 size(0); |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6696 format %{ "!MEMBAR-storestore (empty encoding)" %} |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6697 ins_encode( ); |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6698 ins_pipe(empty); |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6699 %} |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6700 |
0 | 6701 //----------Register Move Instructions----------------------------------------- |
6702 instruct roundDouble_nop(regD dst) %{ | |
6703 match(Set dst (RoundDouble dst)); | |
6704 ins_cost(0); | |
6705 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6706 ins_encode( ); | |
6707 ins_pipe(empty); | |
6708 %} | |
6709 | |
6710 | |
6711 instruct roundFloat_nop(regF dst) %{ | |
6712 match(Set dst (RoundFloat dst)); | |
6713 ins_cost(0); | |
6714 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6715 ins_encode( ); | |
6716 ins_pipe(empty); | |
6717 %} | |
6718 | |
6719 | |
6720 // Cast Index to Pointer for unsafe natives | |
6721 instruct castX2P(iRegX src, iRegP dst) %{ | |
6722 match(Set dst (CastX2P src)); | |
6723 | |
6724 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
6725 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6726 ins_pipe(ialu_reg); | |
6727 %} | |
6728 | |
6729 // Cast Pointer to Index for unsafe natives | |
6730 instruct castP2X(iRegP src, iRegX dst) %{ | |
6731 match(Set dst (CastP2X src)); | |
6732 | |
6733 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
6734 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6735 ins_pipe(ialu_reg); | |
6736 %} | |
6737 | |
6738 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
6739 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6740 match(Set stkSlot src); // chain rule | |
6741 ins_cost(MEMORY_REF_COST); | |
6742 format %{ "STDF $src,$stkSlot\t!stk" %} | |
6743 opcode(Assembler::stdf_op3); | |
415
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parents:
235
diff
changeset
|
6744 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6745 ins_pipe(fstoreD_stk_reg); |
6746 %} | |
6747 | |
6748 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
6749 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6750 match(Set dst stkSlot); // chain rule | |
6751 ins_cost(MEMORY_REF_COST); | |
6752 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
6753 opcode(Assembler::lddf_op3); | |
415
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parents:
235
diff
changeset
|
6754 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
0 | 6755 ins_pipe(floadD_stk); |
6756 %} | |
6757 | |
6758 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
6759 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6760 match(Set stkSlot src); // chain rule | |
6761 ins_cost(MEMORY_REF_COST); | |
6762 format %{ "STF $src,$stkSlot\t!stk" %} | |
6763 opcode(Assembler::stf_op3); | |
415
4d9884b01ba6
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parents:
235
diff
changeset
|
6764 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6765 ins_pipe(fstoreF_stk_reg); |
6766 %} | |
6767 | |
6768 //----------Conditional Move--------------------------------------------------- | |
6769 // Conditional move | |
6770 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
6771 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6772 ins_cost(150); | |
6773 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6774 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6775 ins_pipe(ialu_reg); | |
6776 %} | |
6777 | |
6778 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
6779 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6780 ins_cost(140); | |
6781 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6782 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6783 ins_pipe(ialu_imm); | |
6784 %} | |
6785 | |
6786 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
6787 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6788 ins_cost(150); | |
6789 size(4); | |
6790 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6791 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6792 ins_pipe(ialu_reg); | |
6793 %} | |
6794 | |
6795 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
6796 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6797 ins_cost(140); | |
6798 size(4); | |
6799 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6800 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6801 ins_pipe(ialu_imm); | |
6802 %} | |
6803 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6804 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
0 | 6805 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6806 ins_cost(150); | |
6807 size(4); | |
6808 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6809 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6810 ins_pipe(ialu_reg); | |
6811 %} | |
6812 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6813 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
0 | 6814 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6815 ins_cost(140); | |
6816 size(4); | |
6817 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6818 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6819 ins_pipe(ialu_imm); | |
6820 %} | |
6821 | |
6822 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
6823 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6824 ins_cost(150); | |
6825 size(4); | |
6826 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6827 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6828 ins_pipe(ialu_reg); | |
6829 %} | |
6830 | |
6831 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
6832 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6833 ins_cost(140); | |
6834 size(4); | |
6835 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6836 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
6837 ins_pipe(ialu_imm); | |
6838 %} | |
6839 | |
164
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163
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changeset
|
6840 // Conditional move for RegN. Only cmov(reg,reg). |
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163
diff
changeset
|
6841 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
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163
diff
changeset
|
6842 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
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parents:
163
diff
changeset
|
6843 ins_cost(150); |
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parents:
163
diff
changeset
|
6844 format %{ "MOV$cmp $pcc,$src,$dst" %} |
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parents:
163
diff
changeset
|
6845 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
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parents:
163
diff
changeset
|
6846 ins_pipe(ialu_reg); |
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parents:
163
diff
changeset
|
6847 %} |
c436414a719e
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parents:
163
diff
changeset
|
6848 |
c436414a719e
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parents:
163
diff
changeset
|
6849 // This instruction also works with CmpN so we don't need cmovNN_reg. |
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parents:
163
diff
changeset
|
6850 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
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parents:
163
diff
changeset
|
6851 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
c436414a719e
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parents:
163
diff
changeset
|
6852 ins_cost(150); |
c436414a719e
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parents:
163
diff
changeset
|
6853 size(4); |
c436414a719e
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parents:
163
diff
changeset
|
6854 format %{ "MOV$cmp $icc,$src,$dst" %} |
c436414a719e
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parents:
163
diff
changeset
|
6855 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
c436414a719e
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parents:
163
diff
changeset
|
6856 ins_pipe(ialu_reg); |
c436414a719e
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parents:
163
diff
changeset
|
6857 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6858 |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6859 // This instruction also works with CmpN so we don't need cmovNN_reg. |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6860 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
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diff
changeset
|
6861 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6862 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6863 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6864 format %{ "MOV$cmp $icc,$src,$dst" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6865 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6866 ins_pipe(ialu_reg); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6867 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6868 |
164
c436414a719e
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kvn
parents:
163
diff
changeset
|
6869 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
c436414a719e
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parents:
163
diff
changeset
|
6870 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6871 ins_cost(150); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6872 size(4); |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6873 format %{ "MOV$cmp $fcc,$src,$dst" %} |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6874 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
c436414a719e
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parents:
163
diff
changeset
|
6875 ins_pipe(ialu_reg); |
c436414a719e
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parents:
163
diff
changeset
|
6876 %} |
c436414a719e
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parents:
163
diff
changeset
|
6877 |
0 | 6878 // Conditional move |
6879 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
6880 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6881 ins_cost(150); | |
6882 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6883 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6884 ins_pipe(ialu_reg); | |
6885 %} | |
6886 | |
6887 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
6888 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6889 ins_cost(140); | |
6890 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6891 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6892 ins_pipe(ialu_imm); | |
6893 %} | |
6894 | |
164
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parents:
163
diff
changeset
|
6895 // This instruction also works with CmpN so we don't need cmovPN_reg. |
0 | 6896 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
6897 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
6898 ins_cost(150); | |
6899 | |
6900 size(4); | |
6901 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
6902 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6903 ins_pipe(ialu_reg); | |
6904 %} | |
6905 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6906 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6907 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6908 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6909 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6910 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6911 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6912 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6913 ins_pipe(ialu_reg); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6914 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6915 |
0 | 6916 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ |
6917 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
6918 ins_cost(140); | |
6919 | |
6920 size(4); | |
6921 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
6922 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6923 ins_pipe(ialu_imm); | |
6924 %} | |
6925 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6926 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6927 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6928 ins_cost(140); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6929 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6930 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6931 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6932 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6933 ins_pipe(ialu_imm); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6934 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6935 |
0 | 6936 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ |
6937 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
6938 ins_cost(150); | |
6939 size(4); | |
6940 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6941 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6942 ins_pipe(ialu_imm); | |
6943 %} | |
6944 | |
6945 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
6946 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
6947 ins_cost(140); | |
6948 size(4); | |
6949 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6950 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
6951 ins_pipe(ialu_imm); | |
6952 %} | |
6953 | |
6954 // Conditional move | |
6955 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
6956 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
6957 ins_cost(150); | |
6958 opcode(0x101); | |
6959 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
6960 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6961 ins_pipe(int_conditional_float_move); | |
6962 %} | |
6963 | |
6964 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
6965 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
6966 ins_cost(150); | |
6967 | |
6968 size(4); | |
6969 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
6970 opcode(0x101); | |
6971 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
6972 ins_pipe(int_conditional_float_move); | |
6973 %} | |
6974 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6975 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6976 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6977 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6978 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6979 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
6980 format %{ "FMOVS$cmp $icc,$src,$dst" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6981 opcode(0x101); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6982 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6983 ins_pipe(int_conditional_float_move); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6984 %} |
f24201449cac
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1137
diff
changeset
|
6985 |
0 | 6986 // Conditional move, |
6987 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
6988 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
6989 ins_cost(150); | |
6990 size(4); | |
6991 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
6992 opcode(0x1); | |
6993 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
6994 ins_pipe(int_conditional_double_move); | |
6995 %} | |
6996 | |
6997 // Conditional move | |
6998 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
6999 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
7000 ins_cost(150); | |
7001 size(4); | |
7002 opcode(0x102); | |
7003 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
7004 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
7005 ins_pipe(int_conditional_double_move); | |
7006 %} | |
7007 | |
7008 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
7009 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
7010 ins_cost(150); | |
7011 | |
7012 size(4); | |
7013 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
7014 opcode(0x102); | |
7015 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
7016 ins_pipe(int_conditional_double_move); | |
7017 %} | |
7018 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
7019 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
7020 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7021 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7022 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7023 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
7024 format %{ "FMOVD$cmp $icc,$src,$dst" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7025 opcode(0x102); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
7026 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
7027 ins_pipe(int_conditional_double_move); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
7028 %} |
f24201449cac
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1137
diff
changeset
|
7029 |
0 | 7030 // Conditional move, |
7031 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
7032 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
7033 ins_cost(150); | |
7034 size(4); | |
7035 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
7036 opcode(0x2); | |
7037 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
7038 ins_pipe(int_conditional_double_move); | |
7039 %} | |
7040 | |
7041 // Conditional move | |
7042 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
7043 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
7044 ins_cost(150); | |
7045 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
7046 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
7047 ins_pipe(ialu_reg); | |
7048 %} | |
7049 | |
7050 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
7051 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
7052 ins_cost(140); | |
7053 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
7054 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
7055 ins_pipe(ialu_imm); | |
7056 %} | |
7057 | |
7058 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
7059 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
7060 ins_cost(150); | |
7061 | |
7062 size(4); | |
7063 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
7064 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
7065 ins_pipe(ialu_reg); | |
7066 %} | |
7067 | |
7068 | |
1160
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
7069 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
7070 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
7071 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
7072 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
7073 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
7074 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
f24201449cac
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parents:
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diff
changeset
|
7075 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
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parents:
1137
diff
changeset
|
7076 ins_pipe(ialu_reg); |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
7077 %} |
f24201449cac
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diff
changeset
|
7078 |
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diff
changeset
|
7079 |
0 | 7080 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ |
7081 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
7082 ins_cost(150); | |
7083 | |
7084 size(4); | |
7085 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
7086 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
7087 ins_pipe(ialu_reg); | |
7088 %} | |
7089 | |
7090 | |
7091 | |
7092 //----------OS and Locking Instructions---------------------------------------- | |
7093 | |
7094 // This name is KNOWN by the ADLC and cannot be changed. | |
7095 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
7096 // for this guy. | |
7097 instruct tlsLoadP(g2RegP dst) %{ | |
7098 match(Set dst (ThreadLocal)); | |
7099 | |
7100 size(0); | |
7101 ins_cost(0); | |
7102 format %{ "# TLS is in G2" %} | |
7103 ins_encode( /*empty encoding*/ ); | |
7104 ins_pipe(ialu_none); | |
7105 %} | |
7106 | |
7107 instruct checkCastPP( iRegP dst ) %{ | |
7108 match(Set dst (CheckCastPP dst)); | |
7109 | |
7110 size(0); | |
7111 format %{ "# checkcastPP of $dst" %} | |
7112 ins_encode( /*empty encoding*/ ); | |
7113 ins_pipe(empty); | |
7114 %} | |
7115 | |
7116 | |
7117 instruct castPP( iRegP dst ) %{ | |
7118 match(Set dst (CastPP dst)); | |
7119 format %{ "# castPP of $dst" %} | |
7120 ins_encode( /*empty encoding*/ ); | |
7121 ins_pipe(empty); | |
7122 %} | |
7123 | |
7124 instruct castII( iRegI dst ) %{ | |
7125 match(Set dst (CastII dst)); | |
7126 format %{ "# castII of $dst" %} | |
7127 ins_encode( /*empty encoding*/ ); | |
7128 ins_cost(0); | |
7129 ins_pipe(empty); | |
7130 %} | |
7131 | |
7132 //----------Arithmetic Instructions-------------------------------------------- | |
7133 // Addition Instructions | |
7134 // Register Addition | |
7135 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7136 match(Set dst (AddI src1 src2)); | |
7137 | |
7138 size(4); | |
7139 format %{ "ADD $src1,$src2,$dst" %} | |
7140 ins_encode %{ | |
7141 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
7142 %} | |
7143 ins_pipe(ialu_reg_reg); | |
7144 %} | |
7145 | |
7146 // Immediate Addition | |
7147 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7148 match(Set dst (AddI src1 src2)); | |
7149 | |
7150 size(4); | |
7151 format %{ "ADD $src1,$src2,$dst" %} | |
7152 opcode(Assembler::add_op3, Assembler::arith_op); | |
7153 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7154 ins_pipe(ialu_reg_imm); | |
7155 %} | |
7156 | |
7157 // Pointer Register Addition | |
7158 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
7159 match(Set dst (AddP src1 src2)); | |
7160 | |
7161 size(4); | |
7162 format %{ "ADD $src1,$src2,$dst" %} | |
7163 opcode(Assembler::add_op3, Assembler::arith_op); | |
7164 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7165 ins_pipe(ialu_reg_reg); | |
7166 %} | |
7167 | |
7168 // Pointer Immediate Addition | |
7169 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
7170 match(Set dst (AddP src1 src2)); | |
7171 | |
7172 size(4); | |
7173 format %{ "ADD $src1,$src2,$dst" %} | |
7174 opcode(Assembler::add_op3, Assembler::arith_op); | |
7175 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7176 ins_pipe(ialu_reg_imm); | |
7177 %} | |
7178 | |
7179 // Long Addition | |
7180 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7181 match(Set dst (AddL src1 src2)); | |
7182 | |
7183 size(4); | |
7184 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
7185 opcode(Assembler::add_op3, Assembler::arith_op); | |
7186 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7187 ins_pipe(ialu_reg_reg); | |
7188 %} | |
7189 | |
7190 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7191 match(Set dst (AddL src1 con)); | |
7192 | |
7193 size(4); | |
7194 format %{ "ADD $src1,$con,$dst" %} | |
7195 opcode(Assembler::add_op3, Assembler::arith_op); | |
7196 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7197 ins_pipe(ialu_reg_imm); | |
7198 %} | |
7199 | |
7200 //----------Conditional_store-------------------------------------------------- | |
7201 // Conditional-store of the updated heap-top. | |
7202 // Used during allocation of the shared heap. | |
7203 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
7204 | |
7205 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
7206 instruct loadPLocked(iRegP dst, memory mem) %{ | |
7207 match(Set dst (LoadPLocked mem)); | |
7208 ins_cost(MEMORY_REF_COST); | |
7209 | |
7210 #ifndef _LP64 | |
7211 size(4); | |
7212 format %{ "LDUW $mem,$dst\t! ptr" %} | |
7213 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
7214 #else | |
7215 format %{ "LDX $mem,$dst\t! ptr" %} | |
7216 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
7217 #endif | |
7218 ins_encode( form3_mem_reg( mem, dst ) ); | |
7219 ins_pipe(iload_mem); | |
7220 %} | |
7221 | |
7222 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
7223 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
7224 effect( KILL newval ); | |
7225 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
7226 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
7227 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
7228 ins_pipe( long_memory_op ); | |
7229 %} | |
7230 | |
420
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7231 // Conditional-store of an int value. |
a1980da045cc
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7232 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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7233 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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changeset
|
7234 effect( KILL newval ); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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changeset
|
7235 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
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|
7236 "CMP $oldval,$newval\t\t! See if we made progress" %} |
a1980da045cc
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|
7237 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 7238 ins_pipe( long_memory_op ); |
7239 %} | |
7240 | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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changeset
|
7241 // Conditional-store of a long value. |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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changeset
|
7242 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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|
7243 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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diff
changeset
|
7244 effect( KILL newval ); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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diff
changeset
|
7245 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
a1980da045cc
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diff
changeset
|
7246 "CMP $oldval,$newval\t\t! See if we made progress" %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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changeset
|
7247 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 7248 ins_pipe( long_memory_op ); |
7249 %} | |
7250 | |
7251 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
7252 | |
7253 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7254 predicate(VM_Version::supports_cx8()); |
0 | 7255 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
7256 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7257 format %{ | |
7258 "MOV $newval,O7\n\t" | |
7259 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7260 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7261 "MOV 1,$res\n\t" | |
7262 "MOVne xcc,R_G0,$res" | |
7263 %} | |
7264 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
7265 enc_lflags_ne_to_boolean(res) ); | |
7266 ins_pipe( long_memory_op ); | |
7267 %} | |
7268 | |
7269 | |
7270 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
7271 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
7272 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7273 format %{ | |
7274 "MOV $newval,O7\n\t" | |
7275 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7276 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7277 "MOV 1,$res\n\t" | |
7278 "MOVne icc,R_G0,$res" | |
7279 %} | |
7280 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
7281 enc_iflags_ne_to_boolean(res) ); | |
7282 ins_pipe( long_memory_op ); | |
7283 %} | |
7284 | |
7285 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7286 #ifdef _LP64 |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7287 predicate(VM_Version::supports_cx8()); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7288 #endif |
0 | 7289 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
7290 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7291 format %{ | |
7292 "MOV $newval,O7\n\t" | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
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diff
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|
7293 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
0 | 7294 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
7295 "MOV 1,$res\n\t" | |
7296 "MOVne xcc,R_G0,$res" | |
7297 %} | |
113
ba764ed4b6f2
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diff
changeset
|
7298 #ifdef _LP64 |
0 | 7299 ins_encode( enc_casx(mem_ptr, oldval, newval), |
7300 enc_lflags_ne_to_boolean(res) ); | |
7301 #else | |
113
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|
7302 ins_encode( enc_casi(mem_ptr, oldval, newval), |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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diff
changeset
|
7303 enc_iflags_ne_to_boolean(res) ); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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changeset
|
7304 #endif |
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changeset
|
7305 ins_pipe( long_memory_op ); |
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6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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|
7306 %} |
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|
7307 |
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
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165
diff
changeset
|
7308 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
113
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|
7309 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
181
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|
7310 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
0 | 7311 format %{ |
7312 "MOV $newval,O7\n\t" | |
7313 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7314 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7315 "MOV 1,$res\n\t" | |
7316 "MOVne icc,R_G0,$res" | |
7317 %} | |
181
823298b11afc
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|
7318 ins_encode( enc_casi(mem_ptr, oldval, newval), |
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|
7319 enc_iflags_ne_to_boolean(res) ); |
0 | 7320 ins_pipe( long_memory_op ); |
7321 %} | |
7322 | |
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
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|
7323 instruct xchgI( memory mem, iRegI newval) %{ |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
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|
7324 match(Set newval (GetAndSetI mem newval)); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7325 format %{ "SWAP [$mem],$newval" %} |
7eca5de9e0b6
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diff
changeset
|
7326 size(4); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7327 ins_encode %{ |
7eca5de9e0b6
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6725
diff
changeset
|
7328 __ swap($mem$$Address, $newval$$Register); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
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|
7329 %} |
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6725
diff
changeset
|
7330 ins_pipe( long_memory_op ); |
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diff
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|
7331 %} |
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diff
changeset
|
7332 |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7333 #ifndef _LP64 |
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7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7334 instruct xchgP( memory mem, iRegP newval) %{ |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7335 match(Set newval (GetAndSetP mem newval)); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7336 format %{ "SWAP [$mem],$newval" %} |
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6725
diff
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|
7337 size(4); |
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7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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changeset
|
7338 ins_encode %{ |
7eca5de9e0b6
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7339 __ swap($mem$$Address, $newval$$Register); |
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7340 %} |
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7341 ins_pipe( long_memory_op ); |
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7342 %} |
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7343 #endif |
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7344 |
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7345 instruct xchgN( memory mem, iRegN newval) %{ |
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7346 match(Set newval (GetAndSetN mem newval)); |
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7347 format %{ "SWAP [$mem],$newval" %} |
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7348 size(4); |
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7349 ins_encode %{ |
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7350 __ swap($mem$$Address, $newval$$Register); |
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7351 %} |
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7352 ins_pipe( long_memory_op ); |
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7353 %} |
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7354 |
0 | 7355 //--------------------- |
7356 // Subtraction Instructions | |
7357 // Register Subtraction | |
7358 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7359 match(Set dst (SubI src1 src2)); | |
7360 | |
7361 size(4); | |
7362 format %{ "SUB $src1,$src2,$dst" %} | |
7363 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7364 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7365 ins_pipe(ialu_reg_reg); | |
7366 %} | |
7367 | |
7368 // Immediate Subtraction | |
7369 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7370 match(Set dst (SubI src1 src2)); | |
7371 | |
7372 size(4); | |
7373 format %{ "SUB $src1,$src2,$dst" %} | |
7374 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7375 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7376 ins_pipe(ialu_reg_imm); | |
7377 %} | |
7378 | |
7379 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
7380 match(Set dst (SubI zero src2)); | |
7381 | |
7382 size(4); | |
7383 format %{ "NEG $src2,$dst" %} | |
7384 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7385 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
7386 ins_pipe(ialu_zero_reg); | |
7387 %} | |
7388 | |
7389 // Long subtraction | |
7390 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7391 match(Set dst (SubL src1 src2)); | |
7392 | |
7393 size(4); | |
7394 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7395 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7396 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7397 ins_pipe(ialu_reg_reg); | |
7398 %} | |
7399 | |
7400 // Immediate Subtraction | |
7401 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7402 match(Set dst (SubL src1 con)); | |
7403 | |
7404 size(4); | |
7405 format %{ "SUB $src1,$con,$dst\t! long" %} | |
7406 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7407 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7408 ins_pipe(ialu_reg_imm); | |
7409 %} | |
7410 | |
7411 // Long negation | |
7412 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
7413 match(Set dst (SubL zero src2)); | |
7414 | |
7415 size(4); | |
7416 format %{ "NEG $src2,$dst\t! long" %} | |
7417 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7418 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
7419 ins_pipe(ialu_zero_reg); | |
7420 %} | |
7421 | |
7422 // Multiplication Instructions | |
7423 // Integer Multiplication | |
7424 // Register Multiplication | |
7425 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7426 match(Set dst (MulI src1 src2)); | |
7427 | |
7428 size(4); | |
7429 format %{ "MULX $src1,$src2,$dst" %} | |
7430 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7431 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7432 ins_pipe(imul_reg_reg); | |
7433 %} | |
7434 | |
7435 // Immediate Multiplication | |
7436 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7437 match(Set dst (MulI src1 src2)); | |
7438 | |
7439 size(4); | |
7440 format %{ "MULX $src1,$src2,$dst" %} | |
7441 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7442 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7443 ins_pipe(imul_reg_imm); | |
7444 %} | |
7445 | |
7446 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7447 match(Set dst (MulL src1 src2)); | |
7448 ins_cost(DEFAULT_COST * 5); | |
7449 size(4); | |
7450 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7451 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7452 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7453 ins_pipe(mulL_reg_reg); | |
7454 %} | |
7455 | |
7456 // Immediate Multiplication | |
7457 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7458 match(Set dst (MulL src1 src2)); | |
7459 ins_cost(DEFAULT_COST * 5); | |
7460 size(4); | |
7461 format %{ "MULX $src1,$src2,$dst" %} | |
7462 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7463 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7464 ins_pipe(mulL_reg_imm); | |
7465 %} | |
7466 | |
7467 // Integer Division | |
7468 // Register Division | |
7469 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
7470 match(Set dst (DivI src1 src2)); | |
7471 ins_cost((2+71)*DEFAULT_COST); | |
7472 | |
7473 format %{ "SRA $src2,0,$src2\n\t" | |
7474 "SRA $src1,0,$src1\n\t" | |
7475 "SDIVX $src1,$src2,$dst" %} | |
7476 ins_encode( idiv_reg( src1, src2, dst ) ); | |
7477 ins_pipe(sdiv_reg_reg); | |
7478 %} | |
7479 | |
7480 // Immediate Division | |
7481 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
7482 match(Set dst (DivI src1 src2)); | |
7483 ins_cost((2+71)*DEFAULT_COST); | |
7484 | |
7485 format %{ "SRA $src1,0,$src1\n\t" | |
7486 "SDIVX $src1,$src2,$dst" %} | |
7487 ins_encode( idiv_imm( src1, src2, dst ) ); | |
7488 ins_pipe(sdiv_reg_imm); | |
7489 %} | |
7490 | |
7491 //----------Div-By-10-Expansion------------------------------------------------ | |
7492 // Extract hi bits of a 32x32->64 bit multiply. | |
7493 // Expand rule only, not matched | |
7494 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
7495 effect( DEF dst, USE src1, USE src2 ); | |
7496 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
7497 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
7498 ins_encode( enc_mul_hi(dst,src1,src2)); | |
7499 ins_pipe(sdiv_reg_reg); | |
7500 %} | |
7501 | |
605 | 7502 // Magic constant, reciprocal of 10 |
0 | 7503 instruct loadConI_x66666667(iRegIsafe dst) %{ |
7504 effect( DEF dst ); | |
7505 | |
7506 size(8); | |
7507 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
7508 ins_encode( Set32(0x66666667, dst) ); | |
7509 ins_pipe(ialu_hi_lo_reg); | |
7510 %} | |
7511 | |
605 | 7512 // Register Shift Right Arithmetic Long by 32-63 |
0 | 7513 instruct sra_31( iRegI dst, iRegI src ) %{ |
7514 effect( DEF dst, USE src ); | |
7515 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
7516 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
7517 ins_pipe(ialu_reg_reg); | |
7518 %} | |
7519 | |
7520 // Arithmetic Shift Right by 8-bit immediate | |
7521 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
7522 effect( DEF dst, USE src ); | |
7523 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
7524 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7525 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
7526 ins_pipe(ialu_reg_imm); | |
7527 %} | |
7528 | |
7529 // Integer DIV with 10 | |
7530 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
7531 match(Set dst (DivI src div)); | |
7532 ins_cost((6+6)*DEFAULT_COST); | |
7533 expand %{ | |
7534 iRegIsafe tmp1; // Killed temps; | |
7535 iRegIsafe tmp2; // Killed temps; | |
7536 iRegI tmp3; // Killed temps; | |
7537 iRegI tmp4; // Killed temps; | |
7538 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
7539 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
7540 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
7541 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
7542 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
7543 %} | |
7544 %} | |
7545 | |
7546 // Register Long Division | |
7547 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7548 match(Set dst (DivL src1 src2)); | |
7549 ins_cost(DEFAULT_COST*71); | |
7550 size(4); | |
7551 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7552 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7553 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7554 ins_pipe(divL_reg_reg); | |
7555 %} | |
7556 | |
7557 // Register Long Division | |
7558 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7559 match(Set dst (DivL src1 src2)); | |
7560 ins_cost(DEFAULT_COST*71); | |
7561 size(4); | |
7562 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7563 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7564 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7565 ins_pipe(divL_reg_imm); | |
7566 %} | |
7567 | |
7568 // Integer Remainder | |
7569 // Register Remainder | |
7570 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
7571 match(Set dst (ModI src1 src2)); | |
7572 effect( KILL ccr, KILL temp); | |
7573 | |
7574 format %{ "SREM $src1,$src2,$dst" %} | |
7575 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
7576 ins_pipe(sdiv_reg_reg); | |
7577 %} | |
7578 | |
7579 // Immediate Remainder | |
7580 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
7581 match(Set dst (ModI src1 src2)); | |
7582 effect( KILL ccr, KILL temp); | |
7583 | |
7584 format %{ "SREM $src1,$src2,$dst" %} | |
7585 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
7586 ins_pipe(sdiv_reg_imm); | |
7587 %} | |
7588 | |
7589 // Register Long Remainder | |
7590 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7591 effect(DEF dst, USE src1, USE src2); | |
7592 size(4); | |
7593 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7594 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7595 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7596 ins_pipe(divL_reg_reg); | |
7597 %} | |
7598 | |
7599 // Register Long Division | |
7600 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7601 effect(DEF dst, USE src1, USE src2); | |
7602 size(4); | |
7603 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7604 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7605 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7606 ins_pipe(divL_reg_imm); | |
7607 %} | |
7608 | |
7609 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7610 effect(DEF dst, USE src1, USE src2); | |
7611 size(4); | |
7612 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7613 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7614 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7615 ins_pipe(mulL_reg_reg); | |
7616 %} | |
7617 | |
7618 // Immediate Multiplication | |
7619 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7620 effect(DEF dst, USE src1, USE src2); | |
7621 size(4); | |
7622 format %{ "MULX $src1,$src2,$dst" %} | |
7623 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7624 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7625 ins_pipe(mulL_reg_imm); | |
7626 %} | |
7627 | |
7628 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7629 effect(DEF dst, USE src1, USE src2); | |
7630 size(4); | |
7631 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7632 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7633 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7634 ins_pipe(ialu_reg_reg); | |
7635 %} | |
7636 | |
7637 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
7638 effect(DEF dst, USE src1, USE src2); | |
7639 size(4); | |
7640 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7641 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7642 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7643 ins_pipe(ialu_reg_reg); | |
7644 %} | |
7645 | |
7646 // Register Long Remainder | |
7647 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7648 match(Set dst (ModL src1 src2)); | |
7649 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7650 expand %{ | |
7651 iRegL tmp1; | |
7652 iRegL tmp2; | |
7653 divL_reg_reg_1(tmp1, src1, src2); | |
7654 mulL_reg_reg_1(tmp2, tmp1, src2); | |
7655 subL_reg_reg_1(dst, src1, tmp2); | |
7656 %} | |
7657 %} | |
7658 | |
7659 // Register Long Remainder | |
7660 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7661 match(Set dst (ModL src1 src2)); | |
7662 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7663 expand %{ | |
7664 iRegL tmp1; | |
7665 iRegL tmp2; | |
7666 divL_reg_imm13_1(tmp1, src1, src2); | |
7667 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
7668 subL_reg_reg_2 (dst, src1, tmp2); | |
7669 %} | |
7670 %} | |
7671 | |
7672 // Integer Shift Instructions | |
7673 // Register Shift Left | |
7674 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7675 match(Set dst (LShiftI src1 src2)); | |
7676 | |
7677 size(4); | |
7678 format %{ "SLL $src1,$src2,$dst" %} | |
7679 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7680 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7681 ins_pipe(ialu_reg_reg); | |
7682 %} | |
7683 | |
7684 // Register Shift Left Immediate | |
7685 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7686 match(Set dst (LShiftI src1 src2)); | |
7687 | |
7688 size(4); | |
7689 format %{ "SLL $src1,$src2,$dst" %} | |
7690 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7691 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7692 ins_pipe(ialu_reg_imm); | |
7693 %} | |
7694 | |
7695 // Register Shift Left | |
7696 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7697 match(Set dst (LShiftL src1 src2)); | |
7698 | |
7699 size(4); | |
7700 format %{ "SLLX $src1,$src2,$dst" %} | |
7701 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7702 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7703 ins_pipe(ialu_reg_reg); | |
7704 %} | |
7705 | |
7706 // Register Shift Left Immediate | |
7707 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7708 match(Set dst (LShiftL src1 src2)); | |
7709 | |
7710 size(4); | |
7711 format %{ "SLLX $src1,$src2,$dst" %} | |
7712 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7713 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7714 ins_pipe(ialu_reg_imm); | |
7715 %} | |
7716 | |
7717 // Register Arithmetic Shift Right | |
7718 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7719 match(Set dst (RShiftI src1 src2)); | |
7720 size(4); | |
7721 format %{ "SRA $src1,$src2,$dst" %} | |
7722 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7723 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7724 ins_pipe(ialu_reg_reg); | |
7725 %} | |
7726 | |
7727 // Register Arithmetic Shift Right Immediate | |
7728 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7729 match(Set dst (RShiftI src1 src2)); | |
7730 | |
7731 size(4); | |
7732 format %{ "SRA $src1,$src2,$dst" %} | |
7733 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7734 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7735 ins_pipe(ialu_reg_imm); | |
7736 %} | |
7737 | |
7738 // Register Shift Right Arithmatic Long | |
7739 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7740 match(Set dst (RShiftL src1 src2)); | |
7741 | |
7742 size(4); | |
7743 format %{ "SRAX $src1,$src2,$dst" %} | |
7744 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7745 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7746 ins_pipe(ialu_reg_reg); | |
7747 %} | |
7748 | |
7749 // Register Shift Left Immediate | |
7750 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7751 match(Set dst (RShiftL src1 src2)); | |
7752 | |
7753 size(4); | |
7754 format %{ "SRAX $src1,$src2,$dst" %} | |
7755 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7756 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7757 ins_pipe(ialu_reg_imm); | |
7758 %} | |
7759 | |
7760 // Register Shift Right | |
7761 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7762 match(Set dst (URShiftI src1 src2)); | |
7763 | |
7764 size(4); | |
7765 format %{ "SRL $src1,$src2,$dst" %} | |
7766 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7767 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7768 ins_pipe(ialu_reg_reg); | |
7769 %} | |
7770 | |
7771 // Register Shift Right Immediate | |
7772 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7773 match(Set dst (URShiftI src1 src2)); | |
7774 | |
7775 size(4); | |
7776 format %{ "SRL $src1,$src2,$dst" %} | |
7777 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7778 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7779 ins_pipe(ialu_reg_imm); | |
7780 %} | |
7781 | |
7782 // Register Shift Right | |
7783 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7784 match(Set dst (URShiftL src1 src2)); | |
7785 | |
7786 size(4); | |
7787 format %{ "SRLX $src1,$src2,$dst" %} | |
7788 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7789 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7790 ins_pipe(ialu_reg_reg); | |
7791 %} | |
7792 | |
7793 // Register Shift Right Immediate | |
7794 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7795 match(Set dst (URShiftL src1 src2)); | |
7796 | |
7797 size(4); | |
7798 format %{ "SRLX $src1,$src2,$dst" %} | |
7799 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7800 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7801 ins_pipe(ialu_reg_imm); | |
7802 %} | |
7803 | |
7804 // Register Shift Right Immediate with a CastP2X | |
7805 #ifdef _LP64 | |
7806 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
7807 match(Set dst (URShiftL (CastP2X src1) src2)); | |
7808 size(4); | |
7809 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
7810 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7811 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7812 ins_pipe(ialu_reg_imm); | |
7813 %} | |
7814 #else | |
7815 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
7816 match(Set dst (URShiftI (CastP2X src1) src2)); | |
7817 size(4); | |
7818 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
7819 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7820 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7821 ins_pipe(ialu_reg_imm); | |
7822 %} | |
7823 #endif | |
7824 | |
7825 | |
7826 //----------Floating Point Arithmetic Instructions----------------------------- | |
7827 | |
7828 // Add float single precision | |
7829 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7830 match(Set dst (AddF src1 src2)); | |
7831 | |
7832 size(4); | |
7833 format %{ "FADDS $src1,$src2,$dst" %} | |
7834 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
7835 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7836 ins_pipe(faddF_reg_reg); | |
7837 %} | |
7838 | |
7839 // Add float double precision | |
7840 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7841 match(Set dst (AddD src1 src2)); | |
7842 | |
7843 size(4); | |
7844 format %{ "FADDD $src1,$src2,$dst" %} | |
7845 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
7846 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7847 ins_pipe(faddD_reg_reg); | |
7848 %} | |
7849 | |
7850 // Sub float single precision | |
7851 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7852 match(Set dst (SubF src1 src2)); | |
7853 | |
7854 size(4); | |
7855 format %{ "FSUBS $src1,$src2,$dst" %} | |
7856 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
7857 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7858 ins_pipe(faddF_reg_reg); | |
7859 %} | |
7860 | |
7861 // Sub float double precision | |
7862 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7863 match(Set dst (SubD src1 src2)); | |
7864 | |
7865 size(4); | |
7866 format %{ "FSUBD $src1,$src2,$dst" %} | |
7867 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
7868 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7869 ins_pipe(faddD_reg_reg); | |
7870 %} | |
7871 | |
7872 // Mul float single precision | |
7873 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7874 match(Set dst (MulF src1 src2)); | |
7875 | |
7876 size(4); | |
7877 format %{ "FMULS $src1,$src2,$dst" %} | |
7878 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
7879 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7880 ins_pipe(fmulF_reg_reg); | |
7881 %} | |
7882 | |
7883 // Mul float double precision | |
7884 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7885 match(Set dst (MulD src1 src2)); | |
7886 | |
7887 size(4); | |
7888 format %{ "FMULD $src1,$src2,$dst" %} | |
7889 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
7890 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7891 ins_pipe(fmulD_reg_reg); | |
7892 %} | |
7893 | |
7894 // Div float single precision | |
7895 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7896 match(Set dst (DivF src1 src2)); | |
7897 | |
7898 size(4); | |
7899 format %{ "FDIVS $src1,$src2,$dst" %} | |
7900 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
7901 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7902 ins_pipe(fdivF_reg_reg); | |
7903 %} | |
7904 | |
7905 // Div float double precision | |
7906 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7907 match(Set dst (DivD src1 src2)); | |
7908 | |
7909 size(4); | |
7910 format %{ "FDIVD $src1,$src2,$dst" %} | |
7911 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
7912 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7913 ins_pipe(fdivD_reg_reg); | |
7914 %} | |
7915 | |
7916 // Absolute float double precision | |
7917 instruct absD_reg(regD dst, regD src) %{ | |
7918 match(Set dst (AbsD src)); | |
7919 | |
7920 format %{ "FABSd $src,$dst" %} | |
7921 ins_encode(fabsd(dst, src)); | |
7922 ins_pipe(faddD_reg); | |
7923 %} | |
7924 | |
7925 // Absolute float single precision | |
7926 instruct absF_reg(regF dst, regF src) %{ | |
7927 match(Set dst (AbsF src)); | |
7928 | |
7929 format %{ "FABSs $src,$dst" %} | |
7930 ins_encode(fabss(dst, src)); | |
7931 ins_pipe(faddF_reg); | |
7932 %} | |
7933 | |
7934 instruct negF_reg(regF dst, regF src) %{ | |
7935 match(Set dst (NegF src)); | |
7936 | |
7937 size(4); | |
7938 format %{ "FNEGs $src,$dst" %} | |
7939 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
7940 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
7941 ins_pipe(faddF_reg); | |
7942 %} | |
7943 | |
7944 instruct negD_reg(regD dst, regD src) %{ | |
7945 match(Set dst (NegD src)); | |
7946 | |
7947 format %{ "FNEGd $src,$dst" %} | |
7948 ins_encode(fnegd(dst, src)); | |
7949 ins_pipe(faddD_reg); | |
7950 %} | |
7951 | |
7952 // Sqrt float double precision | |
7953 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
7954 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
7955 | |
7956 size(4); | |
7957 format %{ "FSQRTS $src,$dst" %} | |
7958 ins_encode(fsqrts(dst, src)); | |
7959 ins_pipe(fdivF_reg_reg); | |
7960 %} | |
7961 | |
7962 // Sqrt float double precision | |
7963 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
7964 match(Set dst (SqrtD src)); | |
7965 | |
7966 size(4); | |
7967 format %{ "FSQRTD $src,$dst" %} | |
7968 ins_encode(fsqrtd(dst, src)); | |
7969 ins_pipe(fdivD_reg_reg); | |
7970 %} | |
7971 | |
7972 //----------Logical Instructions----------------------------------------------- | |
7973 // And Instructions | |
7974 // Register And | |
7975 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7976 match(Set dst (AndI src1 src2)); | |
7977 | |
7978 size(4); | |
7979 format %{ "AND $src1,$src2,$dst" %} | |
7980 opcode(Assembler::and_op3, Assembler::arith_op); | |
7981 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7982 ins_pipe(ialu_reg_reg); | |
7983 %} | |
7984 | |
7985 // Immediate And | |
7986 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7987 match(Set dst (AndI src1 src2)); | |
7988 | |
7989 size(4); | |
7990 format %{ "AND $src1,$src2,$dst" %} | |
7991 opcode(Assembler::and_op3, Assembler::arith_op); | |
7992 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7993 ins_pipe(ialu_reg_imm); | |
7994 %} | |
7995 | |
7996 // Register And Long | |
7997 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7998 match(Set dst (AndL src1 src2)); | |
7999 | |
8000 ins_cost(DEFAULT_COST); | |
8001 size(4); | |
8002 format %{ "AND $src1,$src2,$dst\t! long" %} | |
8003 opcode(Assembler::and_op3, Assembler::arith_op); | |
8004 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8005 ins_pipe(ialu_reg_reg); | |
8006 %} | |
8007 | |
8008 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
8009 match(Set dst (AndL src1 con)); | |
8010 | |
8011 ins_cost(DEFAULT_COST); | |
8012 size(4); | |
8013 format %{ "AND $src1,$con,$dst\t! long" %} | |
8014 opcode(Assembler::and_op3, Assembler::arith_op); | |
8015 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
8016 ins_pipe(ialu_reg_imm); | |
8017 %} | |
8018 | |
8019 // Or Instructions | |
8020 // Register Or | |
8021 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
8022 match(Set dst (OrI src1 src2)); | |
8023 | |
8024 size(4); | |
8025 format %{ "OR $src1,$src2,$dst" %} | |
8026 opcode(Assembler::or_op3, Assembler::arith_op); | |
8027 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8028 ins_pipe(ialu_reg_reg); | |
8029 %} | |
8030 | |
8031 // Immediate Or | |
8032 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
8033 match(Set dst (OrI src1 src2)); | |
8034 | |
8035 size(4); | |
8036 format %{ "OR $src1,$src2,$dst" %} | |
8037 opcode(Assembler::or_op3, Assembler::arith_op); | |
8038 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
8039 ins_pipe(ialu_reg_imm); | |
8040 %} | |
8041 | |
8042 // Register Or Long | |
8043 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
8044 match(Set dst (OrL src1 src2)); | |
8045 | |
8046 ins_cost(DEFAULT_COST); | |
8047 size(4); | |
8048 format %{ "OR $src1,$src2,$dst\t! long" %} | |
8049 opcode(Assembler::or_op3, Assembler::arith_op); | |
8050 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8051 ins_pipe(ialu_reg_reg); | |
8052 %} | |
8053 | |
8054 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
8055 match(Set dst (OrL src1 con)); | |
8056 ins_cost(DEFAULT_COST*2); | |
8057 | |
8058 ins_cost(DEFAULT_COST); | |
8059 size(4); | |
8060 format %{ "OR $src1,$con,$dst\t! long" %} | |
8061 opcode(Assembler::or_op3, Assembler::arith_op); | |
8062 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
8063 ins_pipe(ialu_reg_imm); | |
8064 %} | |
8065 | |
420
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8066 #ifndef _LP64 |
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8067 |
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8068 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
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8069 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
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8070 match(Set dst (OrI src1 (CastP2X src2))); |
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8071 |
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8072 size(4); |
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8073 format %{ "OR $src1,$src2,$dst" %} |
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8074 opcode(Assembler::or_op3, Assembler::arith_op); |
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8075 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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8076 ins_pipe(ialu_reg_reg); |
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8077 %} |
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8078 |
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8079 #else |
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8080 |
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8081 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
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8082 match(Set dst (OrL src1 (CastP2X src2))); |
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8083 |
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8084 ins_cost(DEFAULT_COST); |
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8085 size(4); |
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8086 format %{ "OR $src1,$src2,$dst\t! long" %} |
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8087 opcode(Assembler::or_op3, Assembler::arith_op); |
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8088 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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8089 ins_pipe(ialu_reg_reg); |
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8090 %} |
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8091 |
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8092 #endif |
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8093 |
0 | 8094 // Xor Instructions |
8095 // Register Xor | |
8096 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
8097 match(Set dst (XorI src1 src2)); | |
8098 | |
8099 size(4); | |
8100 format %{ "XOR $src1,$src2,$dst" %} | |
8101 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8102 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8103 ins_pipe(ialu_reg_reg); | |
8104 %} | |
8105 | |
8106 // Immediate Xor | |
8107 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
8108 match(Set dst (XorI src1 src2)); | |
8109 | |
8110 size(4); | |
8111 format %{ "XOR $src1,$src2,$dst" %} | |
8112 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8113 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
8114 ins_pipe(ialu_reg_imm); | |
8115 %} | |
8116 | |
8117 // Register Xor Long | |
8118 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
8119 match(Set dst (XorL src1 src2)); | |
8120 | |
8121 ins_cost(DEFAULT_COST); | |
8122 size(4); | |
8123 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
8124 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8125 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8126 ins_pipe(ialu_reg_reg); | |
8127 %} | |
8128 | |
8129 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
8130 match(Set dst (XorL src1 con)); | |
8131 | |
8132 ins_cost(DEFAULT_COST); | |
8133 size(4); | |
8134 format %{ "XOR $src1,$con,$dst\t! long" %} | |
8135 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8136 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
8137 ins_pipe(ialu_reg_imm); | |
8138 %} | |
8139 | |
8140 //----------Convert to Boolean------------------------------------------------- | |
8141 // Nice hack for 32-bit tests but doesn't work for | |
8142 // 64-bit pointers. | |
8143 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
8144 match(Set dst (Conv2B src)); | |
8145 effect( KILL ccr ); | |
8146 ins_cost(DEFAULT_COST*2); | |
8147 format %{ "CMP R_G0,$src\n\t" | |
8148 "ADDX R_G0,0,$dst" %} | |
8149 ins_encode( enc_to_bool( src, dst ) ); | |
8150 ins_pipe(ialu_reg_ialu); | |
8151 %} | |
8152 | |
8153 #ifndef _LP64 | |
8154 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
8155 match(Set dst (Conv2B src)); | |
8156 effect( KILL ccr ); | |
8157 ins_cost(DEFAULT_COST*2); | |
8158 format %{ "CMP R_G0,$src\n\t" | |
8159 "ADDX R_G0,0,$dst" %} | |
8160 ins_encode( enc_to_bool( src, dst ) ); | |
8161 ins_pipe(ialu_reg_ialu); | |
8162 %} | |
8163 #else | |
8164 instruct convP2B( iRegI dst, iRegP src ) %{ | |
8165 match(Set dst (Conv2B src)); | |
8166 ins_cost(DEFAULT_COST*2); | |
8167 format %{ "MOV $src,$dst\n\t" | |
8168 "MOVRNZ $src,1,$dst" %} | |
8169 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
8170 ins_pipe(ialu_clr_and_mover); | |
8171 %} | |
8172 #endif | |
8173 | |
2254
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7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8174 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8175 match(Set dst (CmpLTMask src zero)); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8176 effect(KILL ccr); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8177 size(4); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8178 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8179 ins_encode %{ |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8180 __ sra($src$$Register, 31, $dst$$Register); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8181 %} |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8182 ins_pipe(ialu_reg_imm); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8183 %} |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8184 |
0 | 8185 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ |
8186 match(Set dst (CmpLTMask p q)); | |
8187 effect( KILL ccr ); | |
8188 ins_cost(DEFAULT_COST*4); | |
8189 format %{ "CMP $p,$q\n\t" | |
8190 "MOV #0,$dst\n\t" | |
8191 "BLT,a .+8\n\t" | |
8192 "MOV #-1,$dst" %} | |
8193 ins_encode( enc_ltmask(p,q,dst) ); | |
8194 ins_pipe(ialu_reg_reg_ialu); | |
8195 %} | |
8196 | |
8197 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
8198 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
8199 effect(KILL ccr, TEMP tmp); | |
8200 ins_cost(DEFAULT_COST*3); | |
8201 | |
8202 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
8203 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
2254
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8204 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} |
9154 | 8205 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp)); |
8206 ins_pipe(cadd_cmpltmask); | |
8207 %} | |
8208 | |
8209 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{ | |
8210 match(Set p (AndI (CmpLTMask p q) y)); | |
8211 effect(KILL ccr); | |
8212 ins_cost(DEFAULT_COST*3); | |
8213 | |
8214 format %{ "CMP $p,$q\n\t" | |
8215 "MOV $y,$p\n\t" | |
8216 "MOVge G0,$p" %} | |
8217 ins_encode %{ | |
8218 __ cmp($p$$Register, $q$$Register); | |
8219 __ mov($y$$Register, $p$$Register); | |
8220 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register); | |
8221 %} | |
8222 ins_pipe(ialu_reg_reg_ialu); | |
8223 %} | |
3804 | 8224 |
8225 //----------------------------------------------------------------- | |
8226 // Direct raw moves between float and general registers using VIS3. | |
8227 | |
8228 // ins_pipe(faddF_reg); | |
8229 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ | |
8230 predicate(UseVIS >= 3); | |
8231 match(Set dst (MoveF2I src)); | |
8232 | |
8233 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} | |
8234 ins_encode %{ | |
8235 __ movstouw($src$$FloatRegister, $dst$$Register); | |
8236 %} | |
8237 ins_pipe(ialu_reg_reg); | |
8238 %} | |
8239 | |
8240 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ | |
8241 predicate(UseVIS >= 3); | |
8242 match(Set dst (MoveI2F src)); | |
8243 | |
8244 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} | |
8245 ins_encode %{ | |
8246 __ movwtos($src$$Register, $dst$$FloatRegister); | |
8247 %} | |
0 | 8248 ins_pipe(ialu_reg_reg); |
8249 %} | |
8250 | |
3804 | 8251 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ |
8252 predicate(UseVIS >= 3); | |
8253 match(Set dst (MoveD2L src)); | |
8254 | |
8255 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} | |
8256 ins_encode %{ | |
8257 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); | |
8258 %} | |
0 | 8259 ins_pipe(ialu_reg_reg); |
8260 %} | |
8261 | |
3804 | 8262 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ |
8263 predicate(UseVIS >= 3); | |
8264 match(Set dst (MoveL2D src)); | |
8265 | |
8266 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} | |
8267 ins_encode %{ | |
8268 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); | |
8269 %} | |
0 | 8270 ins_pipe(ialu_reg_reg); |
8271 %} | |
8272 | |
3804 | 8273 |
8274 // Raw moves between float and general registers using stack. | |
8275 | |
0 | 8276 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ |
8277 match(Set dst (MoveF2I src)); | |
8278 effect(DEF dst, USE src); | |
8279 ins_cost(MEMORY_REF_COST); | |
8280 | |
8281 size(4); | |
8282 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
8283 opcode(Assembler::lduw_op3); | |
415
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parents:
235
diff
changeset
|
8284 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8285 ins_pipe(iload_mem); |
8286 %} | |
8287 | |
8288 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
8289 match(Set dst (MoveI2F src)); | |
8290 effect(DEF dst, USE src); | |
8291 ins_cost(MEMORY_REF_COST); | |
8292 | |
8293 size(4); | |
8294 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
8295 opcode(Assembler::ldf_op3); | |
415
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parents:
235
diff
changeset
|
8296 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8297 ins_pipe(floadF_stk); |
8298 %} | |
8299 | |
8300 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
8301 match(Set dst (MoveD2L src)); | |
8302 effect(DEF dst, USE src); | |
8303 ins_cost(MEMORY_REF_COST); | |
8304 | |
8305 size(4); | |
8306 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
8307 opcode(Assembler::ldx_op3); | |
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8308 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8309 ins_pipe(iload_mem); |
8310 %} | |
8311 | |
8312 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
8313 match(Set dst (MoveL2D src)); | |
8314 effect(DEF dst, USE src); | |
8315 ins_cost(MEMORY_REF_COST); | |
8316 | |
8317 size(4); | |
8318 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
8319 opcode(Assembler::lddf_op3); | |
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
235
diff
changeset
|
8320 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8321 ins_pipe(floadD_stk); |
8322 %} | |
8323 | |
8324 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
8325 match(Set dst (MoveF2I src)); | |
8326 effect(DEF dst, USE src); | |
8327 ins_cost(MEMORY_REF_COST); | |
8328 | |
8329 size(4); | |
3804 | 8330 format %{ "STF $src,$dst\t! MoveF2I" %} |
0 | 8331 opcode(Assembler::stf_op3); |
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8332 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8333 ins_pipe(fstoreF_stk_reg); |
8334 %} | |
8335 | |
8336 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
8337 match(Set dst (MoveI2F src)); | |
8338 effect(DEF dst, USE src); | |
8339 ins_cost(MEMORY_REF_COST); | |
8340 | |
8341 size(4); | |
3804 | 8342 format %{ "STW $src,$dst\t! MoveI2F" %} |
0 | 8343 opcode(Assembler::stw_op3); |
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
235
diff
changeset
|
8344 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8345 ins_pipe(istore_mem_reg); |
8346 %} | |
8347 | |
8348 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
8349 match(Set dst (MoveD2L src)); | |
8350 effect(DEF dst, USE src); | |
8351 ins_cost(MEMORY_REF_COST); | |
8352 | |
8353 size(4); | |
3804 | 8354 format %{ "STDF $src,$dst\t! MoveD2L" %} |
0 | 8355 opcode(Assembler::stdf_op3); |
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
235
diff
changeset
|
8356 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8357 ins_pipe(fstoreD_stk_reg); |
8358 %} | |
8359 | |
8360 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
8361 match(Set dst (MoveL2D src)); | |
8362 effect(DEF dst, USE src); | |
8363 ins_cost(MEMORY_REF_COST); | |
8364 | |
8365 size(4); | |
3804 | 8366 format %{ "STX $src,$dst\t! MoveL2D" %} |
0 | 8367 opcode(Assembler::stx_op3); |
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
235
diff
changeset
|
8368 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8369 ins_pipe(istore_mem_reg); |
8370 %} | |
8371 | |
8372 | |
3804 | 8373 //----------Arithmetic Conversion Instructions--------------------------------- |
8374 // The conversions operations are all Alpha sorted. Please keep it that way! | |
8375 | |
8376 instruct convD2F_reg(regF dst, regD src) %{ | |
8377 match(Set dst (ConvD2F src)); | |
8378 size(4); | |
8379 format %{ "FDTOS $src,$dst" %} | |
8380 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
8381 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
8382 ins_pipe(fcvtD2F); | |
8383 %} | |
8384 | |
8385 | |
8386 // Convert a double to an int in a float register. | |
8387 // If the double is a NAN, stuff a zero in instead. | |
8388 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
8389 effect(DEF dst, USE src, KILL fcc0); | |
8390 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
8391 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8392 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
8393 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
8394 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
8395 "skip:" %} | |
8396 ins_encode(form_d2i_helper(src,dst)); | |
8397 ins_pipe(fcvtD2I); | |
8398 %} | |
8399 | |
8400 instruct convD2I_stk(stackSlotI dst, regD src) %{ | |
8401 match(Set dst (ConvD2I src)); | |
8402 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8403 expand %{ | |
8404 regF tmp; | |
8405 convD2I_helper(tmp, src); | |
8406 regF_to_stkI(dst, tmp); | |
8407 %} | |
8408 %} | |
8409 | |
8410 instruct convD2I_reg(iRegI dst, regD src) %{ | |
8411 predicate(UseVIS >= 3); | |
8412 match(Set dst (ConvD2I src)); | |
8413 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
8414 expand %{ | |
8415 regF tmp; | |
8416 convD2I_helper(tmp, src); | |
8417 MoveF2I_reg_reg(dst, tmp); | |
8418 %} | |
8419 %} | |
8420 | |
8421 | |
8422 // Convert a double to a long in a double register. | |
8423 // If the double is a NAN, stuff a zero in instead. | |
8424 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
8425 effect(DEF dst, USE src, KILL fcc0); | |
8426 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
8427 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8428 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
8429 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
8430 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
8431 "skip:" %} | |
8432 ins_encode(form_d2l_helper(src,dst)); | |
8433 ins_pipe(fcvtD2L); | |
8434 %} | |
8435 | |
8436 instruct convD2L_stk(stackSlotL dst, regD src) %{ | |
8437 match(Set dst (ConvD2L src)); | |
8438 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8439 expand %{ | |
8440 regD tmp; | |
8441 convD2L_helper(tmp, src); | |
8442 regD_to_stkL(dst, tmp); | |
8443 %} | |
8444 %} | |
8445 | |
8446 instruct convD2L_reg(iRegL dst, regD src) %{ | |
8447 predicate(UseVIS >= 3); | |
8448 match(Set dst (ConvD2L src)); | |
8449 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
8450 expand %{ | |
8451 regD tmp; | |
8452 convD2L_helper(tmp, src); | |
8453 MoveD2L_reg_reg(dst, tmp); | |
8454 %} | |
8455 %} | |
8456 | |
8457 | |
8458 instruct convF2D_reg(regD dst, regF src) %{ | |
8459 match(Set dst (ConvF2D src)); | |
8460 format %{ "FSTOD $src,$dst" %} | |
8461 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
8462 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
8463 ins_pipe(fcvtF2D); | |
8464 %} | |
8465 | |
8466 | |
8467 // Convert a float to an int in a float register. | |
8468 // If the float is a NAN, stuff a zero in instead. | |
8469 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
8470 effect(DEF dst, USE src, KILL fcc0); | |
8471 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
8472 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8473 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
8474 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
8475 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
8476 "skip:" %} | |
8477 ins_encode(form_f2i_helper(src,dst)); | |
8478 ins_pipe(fcvtF2I); | |
8479 %} | |
8480 | |
8481 instruct convF2I_stk(stackSlotI dst, regF src) %{ | |
8482 match(Set dst (ConvF2I src)); | |
8483 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8484 expand %{ | |
8485 regF tmp; | |
8486 convF2I_helper(tmp, src); | |
8487 regF_to_stkI(dst, tmp); | |
8488 %} | |
8489 %} | |
8490 | |
8491 instruct convF2I_reg(iRegI dst, regF src) %{ | |
8492 predicate(UseVIS >= 3); | |
8493 match(Set dst (ConvF2I src)); | |
8494 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
8495 expand %{ | |
8496 regF tmp; | |
8497 convF2I_helper(tmp, src); | |
8498 MoveF2I_reg_reg(dst, tmp); | |
8499 %} | |
8500 %} | |
8501 | |
8502 | |
8503 // Convert a float to a long in a float register. | |
8504 // If the float is a NAN, stuff a zero in instead. | |
8505 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
8506 effect(DEF dst, USE src, KILL fcc0); | |
8507 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
8508 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8509 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
8510 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
8511 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
8512 "skip:" %} | |
8513 ins_encode(form_f2l_helper(src,dst)); | |
8514 ins_pipe(fcvtF2L); | |
8515 %} | |
8516 | |
8517 instruct convF2L_stk(stackSlotL dst, regF src) %{ | |
8518 match(Set dst (ConvF2L src)); | |
8519 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8520 expand %{ | |
8521 regD tmp; | |
8522 convF2L_helper(tmp, src); | |
8523 regD_to_stkL(dst, tmp); | |
8524 %} | |
8525 %} | |
8526 | |
8527 instruct convF2L_reg(iRegL dst, regF src) %{ | |
8528 predicate(UseVIS >= 3); | |
8529 match(Set dst (ConvF2L src)); | |
8530 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
8531 expand %{ | |
8532 regD tmp; | |
8533 convF2L_helper(tmp, src); | |
8534 MoveD2L_reg_reg(dst, tmp); | |
8535 %} | |
8536 %} | |
8537 | |
8538 | |
8539 instruct convI2D_helper(regD dst, regF tmp) %{ | |
8540 effect(USE tmp, DEF dst); | |
8541 format %{ "FITOD $tmp,$dst" %} | |
8542 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
8543 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
8544 ins_pipe(fcvtI2D); | |
8545 %} | |
8546 | |
8547 instruct convI2D_stk(stackSlotI src, regD dst) %{ | |
8548 match(Set dst (ConvI2D src)); | |
8549 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8550 expand %{ | |
8551 regF tmp; | |
8552 stkI_to_regF(tmp, src); | |
8553 convI2D_helper(dst, tmp); | |
8554 %} | |
8555 %} | |
8556 | |
8557 instruct convI2D_reg(regD_low dst, iRegI src) %{ | |
8558 predicate(UseVIS >= 3); | |
8559 match(Set dst (ConvI2D src)); | |
8560 expand %{ | |
8561 regF tmp; | |
8562 MoveI2F_reg_reg(tmp, src); | |
8563 convI2D_helper(dst, tmp); | |
8564 %} | |
8565 %} | |
8566 | |
8567 instruct convI2D_mem(regD_low dst, memory mem) %{ | |
8568 match(Set dst (ConvI2D (LoadI mem))); | |
8569 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8570 size(8); | |
8571 format %{ "LDF $mem,$dst\n\t" | |
8572 "FITOD $dst,$dst" %} | |
8573 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
8574 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
8575 ins_pipe(floadF_mem); | |
8576 %} | |
8577 | |
8578 | |
8579 instruct convI2F_helper(regF dst, regF tmp) %{ | |
8580 effect(DEF dst, USE tmp); | |
8581 format %{ "FITOS $tmp,$dst" %} | |
8582 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
8583 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
8584 ins_pipe(fcvtI2F); | |
8585 %} | |
8586 | |
8587 instruct convI2F_stk(regF dst, stackSlotI src) %{ | |
8588 match(Set dst (ConvI2F src)); | |
8589 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8590 expand %{ | |
8591 regF tmp; | |
8592 stkI_to_regF(tmp,src); | |
8593 convI2F_helper(dst, tmp); | |
8594 %} | |
8595 %} | |
8596 | |
8597 instruct convI2F_reg(regF dst, iRegI src) %{ | |
8598 predicate(UseVIS >= 3); | |
8599 match(Set dst (ConvI2F src)); | |
8600 ins_cost(DEFAULT_COST); | |
8601 expand %{ | |
8602 regF tmp; | |
8603 MoveI2F_reg_reg(tmp, src); | |
8604 convI2F_helper(dst, tmp); | |
8605 %} | |
8606 %} | |
8607 | |
8608 instruct convI2F_mem( regF dst, memory mem ) %{ | |
8609 match(Set dst (ConvI2F (LoadI mem))); | |
8610 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8611 size(8); | |
8612 format %{ "LDF $mem,$dst\n\t" | |
8613 "FITOS $dst,$dst" %} | |
8614 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
8615 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
8616 ins_pipe(floadF_mem); | |
8617 %} | |
8618 | |
8619 | |
8620 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
8621 match(Set dst (ConvI2L src)); | |
8622 size(4); | |
8623 format %{ "SRA $src,0,$dst\t! int->long" %} | |
8624 opcode(Assembler::sra_op3, Assembler::arith_op); | |
8625 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8626 ins_pipe(ialu_reg_reg); | |
8627 %} | |
8628 | |
8629 // Zero-extend convert int to long | |
8630 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
8631 match(Set dst (AndL (ConvI2L src) mask) ); | |
8632 size(4); | |
8633 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
8634 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8635 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8636 ins_pipe(ialu_reg_reg); | |
8637 %} | |
8638 | |
8639 // Zero-extend long | |
8640 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
8641 match(Set dst (AndL src mask) ); | |
8642 size(4); | |
8643 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
8644 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8645 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8646 ins_pipe(ialu_reg_reg); | |
8647 %} | |
8648 | |
8649 | |
0 | 8650 //----------- |
8651 // Long to Double conversion using V8 opcodes. | |
8652 // Still useful because cheetah traps and becomes | |
8653 // amazingly slow for some common numbers. | |
8654 | |
8655 // Magic constant, 0x43300000 | |
8656 instruct loadConI_x43300000(iRegI dst) %{ | |
8657 effect(DEF dst); | |
8658 size(4); | |
8659 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
8660 ins_encode(SetHi22(0x43300000, dst)); | |
8661 ins_pipe(ialu_none); | |
8662 %} | |
8663 | |
8664 // Magic constant, 0x41f00000 | |
8665 instruct loadConI_x41f00000(iRegI dst) %{ | |
8666 effect(DEF dst); | |
8667 size(4); | |
8668 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
8669 ins_encode(SetHi22(0x41f00000, dst)); | |
8670 ins_pipe(ialu_none); | |
8671 %} | |
8672 | |
8673 // Construct a double from two float halves | |
8674 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
8675 effect(DEF dst, USE src1, USE src2); | |
8676 size(8); | |
8677 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
8678 "FMOVS $src2.lo,$dst.lo" %} | |
8679 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
8680 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
8681 ins_pipe(faddD_reg_reg); | |
8682 %} | |
8683 | |
8684 // Convert integer in high half of a double register (in the lower half of | |
8685 // the double register file) to double | |
8686 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
8687 effect(DEF dst, USE src); | |
8688 size(4); | |
8689 format %{ "FITOD $src,$dst" %} | |
8690 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
8691 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
8692 ins_pipe(fcvtLHi2D); | |
8693 %} | |
8694 | |
8695 // Add float double precision | |
8696 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8697 effect(DEF dst, USE src1, USE src2); | |
8698 size(4); | |
8699 format %{ "FADDD $src1,$src2,$dst" %} | |
8700 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
8701 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8702 ins_pipe(faddD_reg_reg); | |
8703 %} | |
8704 | |
8705 // Sub float double precision | |
8706 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8707 effect(DEF dst, USE src1, USE src2); | |
8708 size(4); | |
8709 format %{ "FSUBD $src1,$src2,$dst" %} | |
8710 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
8711 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8712 ins_pipe(faddD_reg_reg); | |
8713 %} | |
8714 | |
8715 // Mul float double precision | |
8716 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8717 effect(DEF dst, USE src1, USE src2); | |
8718 size(4); | |
8719 format %{ "FMULD $src1,$src2,$dst" %} | |
8720 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
8721 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8722 ins_pipe(fmulD_reg_reg); | |
8723 %} | |
8724 | |
8725 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
8726 match(Set dst (ConvL2D src)); | |
8727 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
8728 | |
8729 expand %{ | |
8730 regD_low tmpsrc; | |
8731 iRegI ix43300000; | |
8732 iRegI ix41f00000; | |
8733 stackSlotL lx43300000; | |
8734 stackSlotL lx41f00000; | |
8735 regD_low dx43300000; | |
8736 regD dx41f00000; | |
8737 regD tmp1; | |
8738 regD_low tmp2; | |
8739 regD tmp3; | |
8740 regD tmp4; | |
8741 | |
8742 stkL_to_regD(tmpsrc, src); | |
8743 | |
8744 loadConI_x43300000(ix43300000); | |
8745 loadConI_x41f00000(ix41f00000); | |
8746 regI_to_stkLHi(lx43300000, ix43300000); | |
8747 regI_to_stkLHi(lx41f00000, ix41f00000); | |
8748 stkL_to_regD(dx43300000, lx43300000); | |
8749 stkL_to_regD(dx41f00000, lx41f00000); | |
8750 | |
8751 convI2D_regDHi_regD(tmp1, tmpsrc); | |
8752 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
8753 subD_regD_regD(tmp3, tmp2, dx43300000); | |
8754 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
8755 addD_regD_regD(dst, tmp3, tmp4); | |
8756 %} | |
8757 %} | |
8758 | |
8759 // Long to Double conversion using fast fxtof | |
8760 instruct convL2D_helper(regD dst, regD tmp) %{ | |
8761 effect(DEF dst, USE tmp); | |
8762 size(4); | |
8763 format %{ "FXTOD $tmp,$dst" %} | |
8764 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
8765 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
8766 ins_pipe(fcvtL2D); | |
8767 %} | |
8768 | |
3804 | 8769 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ |
0 | 8770 predicate(VM_Version::has_fast_fxtof()); |
8771 match(Set dst (ConvL2D src)); | |
8772 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
8773 expand %{ | |
8774 regD tmp; | |
8775 stkL_to_regD(tmp, src); | |
8776 convL2D_helper(dst, tmp); | |
8777 %} | |
8778 %} | |
8779 | |
3804 | 8780 instruct convL2D_reg(regD dst, iRegL src) %{ |
8781 predicate(UseVIS >= 3); | |
8782 match(Set dst (ConvL2D src)); | |
8783 expand %{ | |
8784 regD tmp; | |
8785 MoveL2D_reg_reg(tmp, src); | |
8786 convL2D_helper(dst, tmp); | |
8787 %} | |
8788 %} | |
0 | 8789 |
8790 // Long to Float conversion using fast fxtof | |
8791 instruct convL2F_helper(regF dst, regD tmp) %{ | |
8792 effect(DEF dst, USE tmp); | |
8793 size(4); | |
8794 format %{ "FXTOS $tmp,$dst" %} | |
8795 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
8796 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
8797 ins_pipe(fcvtL2F); | |
8798 %} | |
8799 | |
3804 | 8800 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ |
0 | 8801 match(Set dst (ConvL2F src)); |
8802 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8803 expand %{ | |
8804 regD tmp; | |
8805 stkL_to_regD(tmp, src); | |
8806 convL2F_helper(dst, tmp); | |
8807 %} | |
8808 %} | |
3804 | 8809 |
8810 instruct convL2F_reg(regF dst, iRegL src) %{ | |
8811 predicate(UseVIS >= 3); | |
8812 match(Set dst (ConvL2F src)); | |
8813 ins_cost(DEFAULT_COST); | |
8814 expand %{ | |
8815 regD tmp; | |
8816 MoveL2D_reg_reg(tmp, src); | |
8817 convL2F_helper(dst, tmp); | |
8818 %} | |
8819 %} | |
8820 | |
0 | 8821 //----------- |
8822 | |
8823 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
8824 match(Set dst (ConvL2I src)); | |
8825 #ifndef _LP64 | |
8826 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
8827 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
8828 ins_pipe(ialu_move_reg_I_to_L); | |
8829 #else | |
8830 size(4); | |
8831 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
8832 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
8833 ins_pipe(ialu_reg); | |
8834 #endif | |
8835 %} | |
8836 | |
8837 // Register Shift Right Immediate | |
8838 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
8839 match(Set dst (ConvL2I (RShiftL src cnt))); | |
8840 | |
8841 size(4); | |
8842 format %{ "SRAX $src,$cnt,$dst" %} | |
8843 opcode(Assembler::srax_op3, Assembler::arith_op); | |
8844 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
8845 ins_pipe(ialu_reg_imm); | |
8846 %} | |
8847 | |
8848 //----------Control Flow Instructions------------------------------------------ | |
8849 // Compare Instructions | |
8850 // Compare Integers | |
8851 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
8852 match(Set icc (CmpI op1 op2)); | |
8853 effect( DEF icc, USE op1, USE op2 ); | |
8854 | |
8855 size(4); | |
8856 format %{ "CMP $op1,$op2" %} | |
8857 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8858 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8859 ins_pipe(ialu_cconly_reg_reg); | |
8860 %} | |
8861 | |
8862 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
8863 match(Set icc (CmpU op1 op2)); | |
8864 | |
8865 size(4); | |
8866 format %{ "CMP $op1,$op2\t! unsigned" %} | |
8867 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8868 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8869 ins_pipe(ialu_cconly_reg_reg); | |
8870 %} | |
8871 | |
8872 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
8873 match(Set icc (CmpI op1 op2)); | |
8874 effect( DEF icc, USE op1 ); | |
8875 | |
8876 size(4); | |
8877 format %{ "CMP $op1,$op2" %} | |
8878 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8879 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8880 ins_pipe(ialu_cconly_reg_imm); | |
8881 %} | |
8882 | |
8883 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
8884 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8885 | |
8886 size(4); | |
8887 format %{ "BTST $op2,$op1" %} | |
8888 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8889 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8890 ins_pipe(ialu_cconly_reg_reg_zero); | |
8891 %} | |
8892 | |
8893 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
8894 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8895 | |
8896 size(4); | |
8897 format %{ "BTST $op2,$op1" %} | |
8898 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8899 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8900 ins_pipe(ialu_cconly_reg_imm_zero); | |
8901 %} | |
8902 | |
8903 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
8904 match(Set xcc (CmpL op1 op2)); | |
8905 effect( DEF xcc, USE op1, USE op2 ); | |
8906 | |
8907 size(4); | |
8908 format %{ "CMP $op1,$op2\t\t! long" %} | |
8909 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8910 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8911 ins_pipe(ialu_cconly_reg_reg); | |
8912 %} | |
8913 | |
8914 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
8915 match(Set xcc (CmpL op1 con)); | |
8916 effect( DEF xcc, USE op1, USE con ); | |
8917 | |
8918 size(4); | |
8919 format %{ "CMP $op1,$con\t\t! long" %} | |
8920 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8921 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
8922 ins_pipe(ialu_cconly_reg_reg); | |
8923 %} | |
8924 | |
8925 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
8926 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
8927 effect( DEF xcc, USE op1, USE op2 ); | |
8928 | |
8929 size(4); | |
8930 format %{ "BTST $op1,$op2\t\t! long" %} | |
8931 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8932 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8933 ins_pipe(ialu_cconly_reg_reg); | |
8934 %} | |
8935 | |
8936 // useful for checking the alignment of a pointer: | |
8937 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
8938 match(Set xcc (CmpL (AndL op1 con) zero)); | |
8939 effect( DEF xcc, USE op1, USE con ); | |
8940 | |
8941 size(4); | |
8942 format %{ "BTST $op1,$con\t\t! long" %} | |
8943 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8944 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
8945 ins_pipe(ialu_cconly_reg_reg); | |
8946 %} | |
8947 | |
8948 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ | |
8949 match(Set icc (CmpU op1 op2)); | |
8950 | |
8951 size(4); | |
8952 format %{ "CMP $op1,$op2\t! unsigned" %} | |
8953 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8954 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8955 ins_pipe(ialu_cconly_reg_imm); | |
8956 %} | |
8957 | |
8958 // Compare Pointers | |
8959 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
8960 match(Set pcc (CmpP op1 op2)); | |
8961 | |
8962 size(4); | |
8963 format %{ "CMP $op1,$op2\t! ptr" %} | |
8964 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8965 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8966 ins_pipe(ialu_cconly_reg_reg); | |
8967 %} | |
8968 | |
8969 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
8970 match(Set pcc (CmpP op1 op2)); | |
8971 | |
8972 size(4); | |
8973 format %{ "CMP $op1,$op2\t! ptr" %} | |
8974 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8975 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8976 ins_pipe(ialu_cconly_reg_imm); | |
8977 %} | |
8978 | |
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8979 // Compare Narrow oops |
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8980 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
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8981 match(Set icc (CmpN op1 op2)); |
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8982 |
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8983 size(4); |
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8984 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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8985 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8986 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
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8987 ins_pipe(ialu_cconly_reg_reg); |
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8988 %} |
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8989 |
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8990 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
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8991 match(Set icc (CmpN op1 op2)); |
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8992 |
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8993 size(4); |
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8994 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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8995 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8996 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
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8997 ins_pipe(ialu_cconly_reg_imm); |
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8998 %} |
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8999 |
0 | 9000 //----------Max and Min-------------------------------------------------------- |
9001 // Min Instructions | |
9002 // Conditional move for min | |
9003 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
9004 effect( USE_DEF op2, USE op1, USE icc ); | |
9005 | |
9006 size(4); | |
9007 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
9008 opcode(Assembler::less); | |
9009 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
9010 ins_pipe(ialu_reg_flags); | |
9011 %} | |
9012 | |
9013 // Min Register with Register. | |
9014 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
9015 match(Set op2 (MinI op1 op2)); | |
9016 ins_cost(DEFAULT_COST*2); | |
9017 expand %{ | |
9018 flagsReg icc; | |
9019 compI_iReg(icc,op1,op2); | |
9020 cmovI_reg_lt(op2,op1,icc); | |
9021 %} | |
9022 %} | |
9023 | |
9024 // Max Instructions | |
9025 // Conditional move for max | |
9026 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
9027 effect( USE_DEF op2, USE op1, USE icc ); | |
9028 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
9029 opcode(Assembler::greater); | |
9030 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
9031 ins_pipe(ialu_reg_flags); | |
9032 %} | |
9033 | |
9034 // Max Register with Register | |
9035 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
9036 match(Set op2 (MaxI op1 op2)); | |
9037 ins_cost(DEFAULT_COST*2); | |
9038 expand %{ | |
9039 flagsReg icc; | |
9040 compI_iReg(icc,op1,op2); | |
9041 cmovI_reg_gt(op2,op1,icc); | |
9042 %} | |
9043 %} | |
9044 | |
9045 | |
9046 //----------Float Compares---------------------------------------------------- | |
9047 // Compare floating, generate condition code | |
9048 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
9049 match(Set fcc (CmpF src1 src2)); | |
9050 | |
9051 size(4); | |
9052 format %{ "FCMPs $fcc,$src1,$src2" %} | |
9053 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
9054 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
9055 ins_pipe(faddF_fcc_reg_reg_zero); | |
9056 %} | |
9057 | |
9058 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
9059 match(Set fcc (CmpD src1 src2)); | |
9060 | |
9061 size(4); | |
9062 format %{ "FCMPd $fcc,$src1,$src2" %} | |
9063 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
9064 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
9065 ins_pipe(faddD_fcc_reg_reg_zero); | |
9066 %} | |
9067 | |
9068 | |
9069 // Compare floating, generate -1,0,1 | |
9070 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
9071 match(Set dst (CmpF3 src1 src2)); | |
9072 effect(KILL fcc0); | |
9073 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
9074 format %{ "fcmpl $dst,$src1,$src2" %} | |
9075 // Primary = float | |
9076 opcode( true ); | |
9077 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
9078 ins_pipe( floating_cmp ); | |
9079 %} | |
9080 | |
9081 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
9082 match(Set dst (CmpD3 src1 src2)); | |
9083 effect(KILL fcc0); | |
9084 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
9085 format %{ "dcmpl $dst,$src1,$src2" %} | |
9086 // Primary = double (not float) | |
9087 opcode( false ); | |
9088 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
9089 ins_pipe( floating_cmp ); | |
9090 %} | |
9091 | |
9092 //----------Branches--------------------------------------------------------- | |
9093 // Jump | |
9094 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
9095 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
9096 match(Jump switch_val); | |
4776
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9097 effect(TEMP table); |
0 | 9098 |
9099 ins_cost(350); | |
9100 | |
2008 | 9101 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" |
9102 "LD [O7 + $switch_val], O7\n\t" | |
4114
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9103 "JUMP O7" %} |
2008 | 9104 ins_encode %{ |
9105 // Calculate table address into a register. | |
9106 Register table_reg; | |
9107 Register label_reg = O7; | |
4114
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9108 // If we are calculating the size of this instruction don't trust |
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9109 // zero offsets because they might change when |
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9110 // MachConstantBaseNode decides to optimize the constant table |
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9111 // base. |
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9112 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) { |
2008 | 9113 table_reg = $constanttablebase; |
9114 } else { | |
9115 table_reg = O7; | |
2012
5fe0781a8560
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9116 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); |
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9117 __ add($constanttablebase, con_offset, table_reg); |
2008 | 9118 } |
9119 | |
9120 // Jump to base address + switch value | |
9121 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); | |
9122 __ jmp(label_reg, G0); | |
9123 __ delayed()->nop(); | |
9124 %} | |
0 | 9125 ins_pipe(ialu_reg_reg); |
9126 %} | |
9127 | |
9128 // Direct Branch. Use V8 version with longer range. | |
9129 instruct branch(label labl) %{ | |
9130 match(Goto); | |
9131 effect(USE labl); | |
9132 | |
9133 size(8); | |
9134 ins_cost(BRANCH_COST); | |
9135 format %{ "BA $labl" %} | |
3839 | 9136 ins_encode %{ |
9137 Label* L = $labl$$label; | |
9138 __ ba(*L); | |
9139 __ delayed()->nop(); | |
9140 %} | |
0 | 9141 ins_pipe(br); |
9142 %} | |
9143 | |
3851 | 9144 // Direct Branch, short with no delay slot |
9145 instruct branch_short(label labl) %{ | |
9146 match(Goto); | |
9147 predicate(UseCBCond); | |
9148 effect(USE labl); | |
9149 | |
9150 size(4); | |
9151 ins_cost(BRANCH_COST); | |
9152 format %{ "BA $labl\t! short branch" %} | |
9153 ins_encode %{ | |
9154 Label* L = $labl$$label; | |
9155 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9156 __ ba_short(*L); | |
9157 %} | |
9158 ins_short_branch(1); | |
9159 ins_avoid_back_to_back(1); | |
9160 ins_pipe(cbcond_reg_imm); | |
9161 %} | |
9162 | |
0 | 9163 // Conditional Direct Branch |
9164 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
9165 match(If cmp icc); | |
9166 effect(USE labl); | |
9167 | |
9168 size(8); | |
9169 ins_cost(BRANCH_COST); | |
9170 format %{ "BP$cmp $icc,$labl" %} | |
9171 // Prim = bits 24-22, Secnd = bits 31-30 | |
9172 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9173 ins_pipe(br_cc); | |
9174 %} | |
9175 | |
9176 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9177 match(If cmp icc); | |
9178 effect(USE labl); | |
9179 | |
3851 | 9180 ins_cost(BRANCH_COST); |
0 | 9181 format %{ "BP$cmp $icc,$labl" %} |
9182 // Prim = bits 24-22, Secnd = bits 31-30 | |
9183 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9184 ins_pipe(br_cc); | |
9185 %} | |
9186 | |
9187 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
9188 match(If cmp pcc); | |
9189 effect(USE labl); | |
9190 | |
9191 size(8); | |
9192 ins_cost(BRANCH_COST); | |
9193 format %{ "BP$cmp $pcc,$labl" %} | |
3839 | 9194 ins_encode %{ |
9195 Label* L = $labl$$label; | |
9196 Assembler::Predict predict_taken = | |
9197 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9198 | |
9199 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
9200 __ delayed()->nop(); | |
9201 %} | |
0 | 9202 ins_pipe(br_cc); |
9203 %} | |
9204 | |
9205 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
9206 match(If cmp fcc); | |
9207 effect(USE labl); | |
9208 | |
9209 size(8); | |
9210 ins_cost(BRANCH_COST); | |
9211 format %{ "FBP$cmp $fcc,$labl" %} | |
3839 | 9212 ins_encode %{ |
9213 Label* L = $labl$$label; | |
9214 Assembler::Predict predict_taken = | |
9215 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9216 | |
9217 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); | |
9218 __ delayed()->nop(); | |
9219 %} | |
0 | 9220 ins_pipe(br_fcc); |
9221 %} | |
9222 | |
9223 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
9224 match(CountedLoopEnd cmp icc); | |
9225 effect(USE labl); | |
9226 | |
9227 size(8); | |
9228 ins_cost(BRANCH_COST); | |
9229 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9230 // Prim = bits 24-22, Secnd = bits 31-30 | |
9231 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9232 ins_pipe(br_cc); | |
9233 %} | |
9234 | |
9235 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9236 match(CountedLoopEnd cmp icc); | |
9237 effect(USE labl); | |
9238 | |
9239 size(8); | |
9240 ins_cost(BRANCH_COST); | |
9241 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9242 // Prim = bits 24-22, Secnd = bits 31-30 | |
9243 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9244 ins_pipe(br_cc); | |
9245 %} | |
9246 | |
3851 | 9247 // Compare and branch instructions |
9248 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9249 match(If cmp (CmpI op1 op2)); | |
9250 effect(USE labl, KILL icc); | |
9251 | |
9252 size(12); | |
9253 ins_cost(BRANCH_COST); | |
9254 format %{ "CMP $op1,$op2\t! int\n\t" | |
9255 "BP$cmp $labl" %} | |
9256 ins_encode %{ | |
9257 Label* L = $labl$$label; | |
9258 Assembler::Predict predict_taken = | |
9259 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9260 __ cmp($op1$$Register, $op2$$Register); | |
9261 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9262 __ delayed()->nop(); | |
9263 %} | |
9264 ins_pipe(cmp_br_reg_reg); | |
9265 %} | |
9266 | |
9267 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9268 match(If cmp (CmpI op1 op2)); | |
9269 effect(USE labl, KILL icc); | |
9270 | |
9271 size(12); | |
9272 ins_cost(BRANCH_COST); | |
9273 format %{ "CMP $op1,$op2\t! int\n\t" | |
9274 "BP$cmp $labl" %} | |
9275 ins_encode %{ | |
9276 Label* L = $labl$$label; | |
9277 Assembler::Predict predict_taken = | |
9278 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9279 __ cmp($op1$$Register, $op2$$constant); | |
9280 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9281 __ delayed()->nop(); | |
9282 %} | |
9283 ins_pipe(cmp_br_reg_imm); | |
9284 %} | |
9285 | |
9286 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
9287 match(If cmp (CmpU op1 op2)); | |
9288 effect(USE labl, KILL icc); | |
9289 | |
9290 size(12); | |
9291 ins_cost(BRANCH_COST); | |
9292 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
9293 "BP$cmp $labl" %} | |
9294 ins_encode %{ | |
9295 Label* L = $labl$$label; | |
9296 Assembler::Predict predict_taken = | |
9297 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9298 __ cmp($op1$$Register, $op2$$Register); | |
9299 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9300 __ delayed()->nop(); | |
9301 %} | |
9302 ins_pipe(cmp_br_reg_reg); | |
9303 %} | |
9304 | |
9305 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
9306 match(If cmp (CmpU op1 op2)); | |
9307 effect(USE labl, KILL icc); | |
9308 | |
9309 size(12); | |
9310 ins_cost(BRANCH_COST); | |
9311 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
9312 "BP$cmp $labl" %} | |
9313 ins_encode %{ | |
9314 Label* L = $labl$$label; | |
9315 Assembler::Predict predict_taken = | |
9316 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9317 __ cmp($op1$$Register, $op2$$constant); | |
9318 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9319 __ delayed()->nop(); | |
9320 %} | |
9321 ins_pipe(cmp_br_reg_imm); | |
9322 %} | |
9323 | |
9324 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
9325 match(If cmp (CmpL op1 op2)); | |
9326 effect(USE labl, KILL xcc); | |
9327 | |
9328 size(12); | |
9329 ins_cost(BRANCH_COST); | |
9330 format %{ "CMP $op1,$op2\t! long\n\t" | |
9331 "BP$cmp $labl" %} | |
9332 ins_encode %{ | |
9333 Label* L = $labl$$label; | |
9334 Assembler::Predict predict_taken = | |
9335 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9336 __ cmp($op1$$Register, $op2$$Register); | |
9337 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
9338 __ delayed()->nop(); | |
9339 %} | |
9340 ins_pipe(cmp_br_reg_reg); | |
9341 %} | |
9342 | |
9343 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
9344 match(If cmp (CmpL op1 op2)); | |
9345 effect(USE labl, KILL xcc); | |
9346 | |
9347 size(12); | |
9348 ins_cost(BRANCH_COST); | |
9349 format %{ "CMP $op1,$op2\t! long\n\t" | |
9350 "BP$cmp $labl" %} | |
9351 ins_encode %{ | |
9352 Label* L = $labl$$label; | |
9353 Assembler::Predict predict_taken = | |
9354 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9355 __ cmp($op1$$Register, $op2$$constant); | |
9356 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
9357 __ delayed()->nop(); | |
9358 %} | |
9359 ins_pipe(cmp_br_reg_imm); | |
9360 %} | |
9361 | |
9362 // Compare Pointers and branch | |
9363 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
9364 match(If cmp (CmpP op1 op2)); | |
9365 effect(USE labl, KILL pcc); | |
9366 | |
9367 size(12); | |
9368 ins_cost(BRANCH_COST); | |
9369 format %{ "CMP $op1,$op2\t! ptr\n\t" | |
9370 "B$cmp $labl" %} | |
9371 ins_encode %{ | |
9372 Label* L = $labl$$label; | |
9373 Assembler::Predict predict_taken = | |
9374 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9375 __ cmp($op1$$Register, $op2$$Register); | |
9376 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
9377 __ delayed()->nop(); | |
9378 %} | |
9379 ins_pipe(cmp_br_reg_reg); | |
9380 %} | |
9381 | |
9382 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
9383 match(If cmp (CmpP op1 null)); | |
9384 effect(USE labl, KILL pcc); | |
9385 | |
9386 size(12); | |
9387 ins_cost(BRANCH_COST); | |
9388 format %{ "CMP $op1,0\t! ptr\n\t" | |
9389 "B$cmp $labl" %} | |
9390 ins_encode %{ | |
9391 Label* L = $labl$$label; | |
9392 Assembler::Predict predict_taken = | |
9393 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9394 __ cmp($op1$$Register, G0); | |
9395 // bpr() is not used here since it has shorter distance. | |
9396 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
9397 __ delayed()->nop(); | |
9398 %} | |
9399 ins_pipe(cmp_br_reg_reg); | |
9400 %} | |
9401 | |
9402 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
9403 match(If cmp (CmpN op1 op2)); | |
9404 effect(USE labl, KILL icc); | |
9405 | |
9406 size(12); | |
9407 ins_cost(BRANCH_COST); | |
9408 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" | |
9409 "BP$cmp $labl" %} | |
9410 ins_encode %{ | |
9411 Label* L = $labl$$label; | |
9412 Assembler::Predict predict_taken = | |
9413 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9414 __ cmp($op1$$Register, $op2$$Register); | |
9415 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9416 __ delayed()->nop(); | |
9417 %} | |
9418 ins_pipe(cmp_br_reg_reg); | |
9419 %} | |
9420 | |
9421 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
9422 match(If cmp (CmpN op1 null)); | |
9423 effect(USE labl, KILL icc); | |
9424 | |
9425 size(12); | |
9426 ins_cost(BRANCH_COST); | |
9427 format %{ "CMP $op1,0\t! compressed ptr\n\t" | |
9428 "BP$cmp $labl" %} | |
9429 ins_encode %{ | |
9430 Label* L = $labl$$label; | |
9431 Assembler::Predict predict_taken = | |
9432 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9433 __ cmp($op1$$Register, G0); | |
9434 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9435 __ delayed()->nop(); | |
9436 %} | |
9437 ins_pipe(cmp_br_reg_reg); | |
9438 %} | |
9439 | |
9440 // Loop back branch | |
9441 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9442 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9443 effect(USE labl, KILL icc); | |
9444 | |
9445 size(12); | |
9446 ins_cost(BRANCH_COST); | |
9447 format %{ "CMP $op1,$op2\t! int\n\t" | |
9448 "BP$cmp $labl\t! Loop end" %} | |
9449 ins_encode %{ | |
9450 Label* L = $labl$$label; | |
9451 Assembler::Predict predict_taken = | |
9452 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9453 __ cmp($op1$$Register, $op2$$Register); | |
9454 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9455 __ delayed()->nop(); | |
9456 %} | |
9457 ins_pipe(cmp_br_reg_reg); | |
9458 %} | |
9459 | |
9460 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9461 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9462 effect(USE labl, KILL icc); | |
9463 | |
9464 size(12); | |
9465 ins_cost(BRANCH_COST); | |
9466 format %{ "CMP $op1,$op2\t! int\n\t" | |
9467 "BP$cmp $labl\t! Loop end" %} | |
9468 ins_encode %{ | |
9469 Label* L = $labl$$label; | |
9470 Assembler::Predict predict_taken = | |
9471 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9472 __ cmp($op1$$Register, $op2$$constant); | |
9473 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9474 __ delayed()->nop(); | |
9475 %} | |
9476 ins_pipe(cmp_br_reg_imm); | |
9477 %} | |
9478 | |
9479 // Short compare and branch instructions | |
9480 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9481 match(If cmp (CmpI op1 op2)); | |
9482 predicate(UseCBCond); | |
9483 effect(USE labl, KILL icc); | |
9484 | |
9485 size(4); | |
9486 ins_cost(BRANCH_COST); | |
9487 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
9488 ins_encode %{ | |
9489 Label* L = $labl$$label; | |
9490 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9491 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9492 %} | |
9493 ins_short_branch(1); | |
9494 ins_avoid_back_to_back(1); | |
9495 ins_pipe(cbcond_reg_reg); | |
9496 %} | |
9497 | |
9498 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9499 match(If cmp (CmpI op1 op2)); | |
9500 predicate(UseCBCond); | |
9501 effect(USE labl, KILL icc); | |
9502 | |
9503 size(4); | |
9504 ins_cost(BRANCH_COST); | |
9505 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
9506 ins_encode %{ | |
9507 Label* L = $labl$$label; | |
9508 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9509 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
9510 %} | |
9511 ins_short_branch(1); | |
9512 ins_avoid_back_to_back(1); | |
9513 ins_pipe(cbcond_reg_imm); | |
9514 %} | |
9515 | |
9516 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
9517 match(If cmp (CmpU op1 op2)); | |
9518 predicate(UseCBCond); | |
9519 effect(USE labl, KILL icc); | |
9520 | |
9521 size(4); | |
9522 ins_cost(BRANCH_COST); | |
9523 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
9524 ins_encode %{ | |
9525 Label* L = $labl$$label; | |
9526 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9527 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9528 %} | |
9529 ins_short_branch(1); | |
9530 ins_avoid_back_to_back(1); | |
9531 ins_pipe(cbcond_reg_reg); | |
9532 %} | |
9533 | |
9534 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
9535 match(If cmp (CmpU op1 op2)); | |
9536 predicate(UseCBCond); | |
9537 effect(USE labl, KILL icc); | |
9538 | |
9539 size(4); | |
9540 ins_cost(BRANCH_COST); | |
9541 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
9542 ins_encode %{ | |
9543 Label* L = $labl$$label; | |
9544 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9545 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
9546 %} | |
9547 ins_short_branch(1); | |
9548 ins_avoid_back_to_back(1); | |
9549 ins_pipe(cbcond_reg_imm); | |
9550 %} | |
9551 | |
9552 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
9553 match(If cmp (CmpL op1 op2)); | |
9554 predicate(UseCBCond); | |
9555 effect(USE labl, KILL xcc); | |
9556 | |
9557 size(4); | |
9558 ins_cost(BRANCH_COST); | |
9559 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
9560 ins_encode %{ | |
9561 Label* L = $labl$$label; | |
9562 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9563 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); | |
9564 %} | |
9565 ins_short_branch(1); | |
9566 ins_avoid_back_to_back(1); | |
9567 ins_pipe(cbcond_reg_reg); | |
9568 %} | |
9569 | |
9570 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
9571 match(If cmp (CmpL op1 op2)); | |
9572 predicate(UseCBCond); | |
9573 effect(USE labl, KILL xcc); | |
9574 | |
9575 size(4); | |
9576 ins_cost(BRANCH_COST); | |
9577 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
9578 ins_encode %{ | |
9579 Label* L = $labl$$label; | |
9580 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9581 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); | |
9582 %} | |
9583 ins_short_branch(1); | |
9584 ins_avoid_back_to_back(1); | |
9585 ins_pipe(cbcond_reg_imm); | |
9586 %} | |
9587 | |
9588 // Compare Pointers and branch | |
9589 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
9590 match(If cmp (CmpP op1 op2)); | |
9591 predicate(UseCBCond); | |
9592 effect(USE labl, KILL pcc); | |
9593 | |
9594 size(4); | |
9595 ins_cost(BRANCH_COST); | |
9596 #ifdef _LP64 | |
9597 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} | |
9598 #else | |
9599 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %} | |
9600 #endif | |
9601 ins_encode %{ | |
9602 Label* L = $labl$$label; | |
9603 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9604 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); | |
9605 %} | |
9606 ins_short_branch(1); | |
9607 ins_avoid_back_to_back(1); | |
9608 ins_pipe(cbcond_reg_reg); | |
9609 %} | |
9610 | |
9611 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
9612 match(If cmp (CmpP op1 null)); | |
9613 predicate(UseCBCond); | |
9614 effect(USE labl, KILL pcc); | |
9615 | |
9616 size(4); | |
9617 ins_cost(BRANCH_COST); | |
9618 #ifdef _LP64 | |
9619 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} | |
9620 #else | |
9621 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %} | |
9622 #endif | |
9623 ins_encode %{ | |
9624 Label* L = $labl$$label; | |
9625 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9626 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); | |
9627 %} | |
9628 ins_short_branch(1); | |
9629 ins_avoid_back_to_back(1); | |
9630 ins_pipe(cbcond_reg_reg); | |
9631 %} | |
9632 | |
9633 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
9634 match(If cmp (CmpN op1 op2)); | |
9635 predicate(UseCBCond); | |
9636 effect(USE labl, KILL icc); | |
9637 | |
9638 size(4); | |
9639 ins_cost(BRANCH_COST); | |
9640 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %} | |
9641 ins_encode %{ | |
9642 Label* L = $labl$$label; | |
9643 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9644 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9645 %} | |
9646 ins_short_branch(1); | |
9647 ins_avoid_back_to_back(1); | |
9648 ins_pipe(cbcond_reg_reg); | |
9649 %} | |
9650 | |
9651 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
9652 match(If cmp (CmpN op1 null)); | |
9653 predicate(UseCBCond); | |
9654 effect(USE labl, KILL icc); | |
9655 | |
9656 size(4); | |
9657 ins_cost(BRANCH_COST); | |
9658 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} | |
9659 ins_encode %{ | |
9660 Label* L = $labl$$label; | |
9661 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9662 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); | |
9663 %} | |
9664 ins_short_branch(1); | |
9665 ins_avoid_back_to_back(1); | |
9666 ins_pipe(cbcond_reg_reg); | |
9667 %} | |
9668 | |
9669 // Loop back branch | |
9670 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9671 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9672 predicate(UseCBCond); | |
9673 effect(USE labl, KILL icc); | |
9674 | |
9675 size(4); | |
9676 ins_cost(BRANCH_COST); | |
9677 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
9678 ins_encode %{ | |
9679 Label* L = $labl$$label; | |
9680 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9681 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9682 %} | |
9683 ins_short_branch(1); | |
9684 ins_avoid_back_to_back(1); | |
9685 ins_pipe(cbcond_reg_reg); | |
9686 %} | |
9687 | |
9688 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9689 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9690 predicate(UseCBCond); | |
9691 effect(USE labl, KILL icc); | |
9692 | |
9693 size(4); | |
9694 ins_cost(BRANCH_COST); | |
9695 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
9696 ins_encode %{ | |
9697 Label* L = $labl$$label; | |
9698 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9699 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
9700 %} | |
9701 ins_short_branch(1); | |
9702 ins_avoid_back_to_back(1); | |
9703 ins_pipe(cbcond_reg_imm); | |
9704 %} | |
9705 | |
9706 // Branch-on-register tests all 64 bits. We assume that values | |
9707 // in 64-bit registers always remains zero or sign extended | |
9708 // unless our code munges the high bits. Interrupts can chop | |
9709 // the high order bits to zero or sign at any time. | |
9710 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
9711 match(If cmp (CmpI op1 zero)); | |
9712 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
9713 effect(USE labl); | |
9714 | |
9715 size(8); | |
9716 ins_cost(BRANCH_COST); | |
9717 format %{ "BR$cmp $op1,$labl" %} | |
9718 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
9719 ins_pipe(br_reg); | |
9720 %} | |
9721 | |
9722 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
9723 match(If cmp (CmpP op1 null)); | |
9724 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
9725 effect(USE labl); | |
9726 | |
9727 size(8); | |
9728 ins_cost(BRANCH_COST); | |
9729 format %{ "BR$cmp $op1,$labl" %} | |
9730 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
9731 ins_pipe(br_reg); | |
9732 %} | |
9733 | |
9734 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
9735 match(If cmp (CmpL op1 zero)); | |
9736 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
9737 effect(USE labl); | |
9738 | |
9739 size(8); | |
9740 ins_cost(BRANCH_COST); | |
9741 format %{ "BR$cmp $op1,$labl" %} | |
9742 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
9743 ins_pipe(br_reg); | |
9744 %} | |
9745 | |
9746 | |
0 | 9747 // ============================================================================ |
9748 // Long Compare | |
9749 // | |
9750 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
9751 // is tricky. The flavor of compare used depends on whether we are testing | |
9752 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
9753 // The GE test is the negated LT test. The LE test can be had by commuting | |
9754 // the operands (yielding a GE test) and then negating; negate again for the | |
9755 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
9756 // NE test is negated from that. | |
9757 | |
9758 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
9759 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
9760 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
9761 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
9762 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
9763 // foo match ends up with the wrong leaf. One fix is to not match both | |
9764 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
9765 // both forms beat the trinary form of long-compare and both are very useful | |
9766 // on Intel which has so few registers. | |
9767 | |
9768 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
9769 match(If cmp xcc); | |
9770 effect(USE labl); | |
9771 | |
9772 size(8); | |
9773 ins_cost(BRANCH_COST); | |
9774 format %{ "BP$cmp $xcc,$labl" %} | |
3839 | 9775 ins_encode %{ |
9776 Label* L = $labl$$label; | |
9777 Assembler::Predict predict_taken = | |
9778 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9779 | |
9780 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
9781 __ delayed()->nop(); | |
9782 %} | |
0 | 9783 ins_pipe(br_cc); |
9784 %} | |
9785 | |
9786 // Manifest a CmpL3 result in an integer register. Very painful. | |
9787 // This is the test to avoid. | |
9788 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
9789 match(Set dst (CmpL3 src1 src2) ); | |
9790 effect( KILL ccr ); | |
9791 ins_cost(6*DEFAULT_COST); | |
9792 size(24); | |
9793 format %{ "CMP $src1,$src2\t\t! long\n" | |
9794 "\tBLT,a,pn done\n" | |
9795 "\tMOV -1,$dst\t! delay slot\n" | |
9796 "\tBGT,a,pn done\n" | |
9797 "\tMOV 1,$dst\t! delay slot\n" | |
9798 "\tCLR $dst\n" | |
9799 "done:" %} | |
9800 ins_encode( cmpl_flag(src1,src2,dst) ); | |
9801 ins_pipe(cmpL_reg); | |
9802 %} | |
9803 | |
9804 // Conditional move | |
9805 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
9806 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
9807 ins_cost(150); | |
9808 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
9809 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9810 ins_pipe(ialu_reg); | |
9811 %} | |
9812 | |
9813 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
9814 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
9815 ins_cost(140); | |
9816 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
9817 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9818 ins_pipe(ialu_imm); | |
9819 %} | |
9820 | |
9821 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
9822 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
9823 ins_cost(150); | |
9824 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9825 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9826 ins_pipe(ialu_reg); | |
9827 %} | |
9828 | |
9829 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
9830 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
9831 ins_cost(140); | |
9832 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9833 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9834 ins_pipe(ialu_imm); | |
9835 %} | |
9836 | |
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9837 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
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9838 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
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9839 ins_cost(150); |
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9840 format %{ "MOV$cmp $xcc,$src,$dst" %} |
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9841 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
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9842 ins_pipe(ialu_reg); |
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9843 %} |
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9844 |
0 | 9845 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
9846 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
9847 ins_cost(150); | |
9848 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9849 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9850 ins_pipe(ialu_reg); | |
9851 %} | |
9852 | |
9853 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
9854 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
9855 ins_cost(140); | |
9856 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9857 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9858 ins_pipe(ialu_imm); | |
9859 %} | |
9860 | |
9861 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
9862 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
9863 ins_cost(150); | |
9864 opcode(0x101); | |
9865 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
9866 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9867 ins_pipe(int_conditional_float_move); | |
9868 %} | |
9869 | |
9870 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
9871 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
9872 ins_cost(150); | |
9873 opcode(0x102); | |
9874 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
9875 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9876 ins_pipe(int_conditional_float_move); | |
9877 %} | |
9878 | |
9879 // ============================================================================ | |
9880 // Safepoint Instruction | |
9881 instruct safePoint_poll(iRegP poll) %{ | |
9882 match(SafePoint poll); | |
9883 effect(USE poll); | |
9884 | |
9885 size(4); | |
9886 #ifdef _LP64 | |
9887 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
9888 #else | |
9889 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
9890 #endif | |
9891 ins_encode %{ | |
9892 __ relocate(relocInfo::poll_type); | |
9893 __ ld_ptr($poll$$Register, 0, G0); | |
9894 %} | |
9895 ins_pipe(loadPollP); | |
9896 %} | |
9897 | |
9898 // ============================================================================ | |
9899 // Call Instructions | |
9900 // Call Java Static Instruction | |
9901 instruct CallStaticJavaDirect( method meth ) %{ | |
9902 match(CallStaticJava); | |
1567 | 9903 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
0 | 9904 effect(USE meth); |
9905 | |
9906 size(8); | |
9907 ins_cost(CALL_COST); | |
9908 format %{ "CALL,static ; NOP ==> " %} | |
9909 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
9910 ins_pipe(simple_call); | |
9911 %} | |
9912 | |
1567 | 9913 // Call Java Static Instruction (method handle version) |
9914 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ | |
9915 match(CallStaticJava); | |
9916 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); | |
9917 effect(USE meth, KILL l7_mh_SP_save); | |
9918 | |
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9919 size(16); |
1567 | 9920 ins_cost(CALL_COST); |
9921 format %{ "CALL,static/MethodHandle" %} | |
9922 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); | |
9923 ins_pipe(simple_call); | |
9924 %} | |
9925 | |
0 | 9926 // Call Java Dynamic Instruction |
9927 instruct CallDynamicJavaDirect( method meth ) %{ | |
9928 match(CallDynamicJava); | |
9929 effect(USE meth); | |
9930 | |
9931 ins_cost(CALL_COST); | |
9932 format %{ "SET (empty),R_G5\n\t" | |
9933 "CALL,dynamic ; NOP ==> " %} | |
9934 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
9935 ins_pipe(call); | |
9936 %} | |
9937 | |
9938 // Call Runtime Instruction | |
9939 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
9940 match(CallRuntime); | |
9941 effect(USE meth, KILL l7); | |
9942 ins_cost(CALL_COST); | |
9943 format %{ "CALL,runtime" %} | |
9944 ins_encode( Java_To_Runtime( meth ), | |
9945 call_epilog, adjust_long_from_native_call ); | |
9946 ins_pipe(simple_call); | |
9947 %} | |
9948 | |
9949 // Call runtime without safepoint - same as CallRuntime | |
9950 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
9951 match(CallLeaf); | |
9952 effect(USE meth, KILL l7); | |
9953 ins_cost(CALL_COST); | |
9954 format %{ "CALL,runtime leaf" %} | |
9955 ins_encode( Java_To_Runtime( meth ), | |
9956 call_epilog, | |
9957 adjust_long_from_native_call ); | |
9958 ins_pipe(simple_call); | |
9959 %} | |
9960 | |
9961 // Call runtime without safepoint - same as CallLeaf | |
9962 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
9963 match(CallLeafNoFP); | |
9964 effect(USE meth, KILL l7); | |
9965 ins_cost(CALL_COST); | |
9966 format %{ "CALL,runtime leaf nofp" %} | |
9967 ins_encode( Java_To_Runtime( meth ), | |
9968 call_epilog, | |
9969 adjust_long_from_native_call ); | |
9970 ins_pipe(simple_call); | |
9971 %} | |
9972 | |
9973 // Tail Call; Jump from runtime stub to Java code. | |
9974 // Also known as an 'interprocedural jump'. | |
9975 // Target of jump will eventually return to caller. | |
9976 // TailJump below removes the return address. | |
9977 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
9978 match(TailCall jump_target method_oop ); | |
9979 | |
9980 ins_cost(CALL_COST); | |
9981 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
9982 ins_encode(form_jmpl(jump_target)); | |
9983 ins_pipe(tail_call); | |
9984 %} | |
9985 | |
9986 | |
9987 // Return Instruction | |
9988 instruct Ret() %{ | |
9989 match(Return); | |
9990 | |
9991 // The epilogue node did the ret already. | |
9992 size(0); | |
9993 format %{ "! return" %} | |
9994 ins_encode(); | |
9995 ins_pipe(empty); | |
9996 %} | |
9997 | |
9998 | |
9999 // Tail Jump; remove the return address; jump to target. | |
10000 // TailCall above leaves the return address around. | |
10001 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
10002 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
10003 // "restore" before this instruction (in Epilogue), we need to materialize it | |
10004 // in %i0. | |
10005 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
10006 match( TailJump jump_target ex_oop ); | |
10007 ins_cost(CALL_COST); | |
10008 format %{ "! discard R_O7\n\t" | |
10009 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
10010 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
10011 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
10012 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
10013 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
10014 ins_pipe(tail_call); | |
10015 %} | |
10016 | |
10017 // Create exception oop: created by stack-crawling runtime code. | |
10018 // Created exception is now available to this handler, and is setup | |
10019 // just prior to jumping to this handler. No code emitted. | |
10020 instruct CreateException( o0RegP ex_oop ) | |
10021 %{ | |
10022 match(Set ex_oop (CreateEx)); | |
10023 ins_cost(0); | |
10024 | |
10025 size(0); | |
10026 // use the following format syntax | |
10027 format %{ "! exception oop is in R_O0; no code emitted" %} | |
10028 ins_encode(); | |
10029 ins_pipe(empty); | |
10030 %} | |
10031 | |
10032 | |
10033 // Rethrow exception: | |
10034 // The exception oop will come in the first argument position. | |
10035 // Then JUMP (not call) to the rethrow stub code. | |
10036 instruct RethrowException() | |
10037 %{ | |
10038 match(Rethrow); | |
10039 ins_cost(CALL_COST); | |
10040 | |
10041 // use the following format syntax | |
10042 format %{ "Jmp rethrow_stub" %} | |
10043 ins_encode(enc_rethrow); | |
10044 ins_pipe(tail_call); | |
10045 %} | |
10046 | |
10047 | |
10048 // Die now | |
10049 instruct ShouldNotReachHere( ) | |
10050 %{ | |
10051 match(Halt); | |
10052 ins_cost(CALL_COST); | |
10053 | |
10054 size(4); | |
10055 // Use the following format syntax | |
10056 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
10057 ins_encode( form2_illtrap() ); | |
10058 ins_pipe(tail_call); | |
10059 %} | |
10060 | |
10061 // ============================================================================ | |
10062 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
10063 // array for an instance of the superklass. Set a hidden internal cache on a | |
10064 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
10065 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
10066 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
10067 match(Set index (PartialSubtypeCheck sub super)); | |
10068 effect( KILL pcc, KILL o7 ); | |
10069 ins_cost(DEFAULT_COST*10); | |
10070 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
10071 ins_encode( enc_PartialSubtypeCheck() ); | |
10072 ins_pipe(partial_subtype_check_pipe); | |
10073 %} | |
10074 | |
10075 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
10076 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
10077 effect( KILL idx, KILL o7 ); | |
10078 ins_cost(DEFAULT_COST*10); | |
10079 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
10080 ins_encode( enc_PartialSubtypeCheck() ); | |
10081 ins_pipe(partial_subtype_check_pipe); | |
10082 %} | |
10083 | |
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10084 |
0 | 10085 // ============================================================================ |
10086 // inlined locking and unlocking | |
10087 | |
4777 | 10088 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ |
0 | 10089 match(Set pcc (FastLock object box)); |
10090 | |
4777 | 10091 effect(TEMP scratch2, USE_KILL box, KILL scratch); |
0 | 10092 ins_cost(100); |
10093 | |
4777 | 10094 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} |
0 | 10095 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); |
10096 ins_pipe(long_memory_op); | |
10097 %} | |
10098 | |
10099 | |
4777 | 10100 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ |
0 | 10101 match(Set pcc (FastUnlock object box)); |
4777 | 10102 effect(TEMP scratch2, USE_KILL box, KILL scratch); |
0 | 10103 ins_cost(100); |
10104 | |
4777 | 10105 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} |
0 | 10106 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); |
10107 ins_pipe(long_memory_op); | |
10108 %} | |
10109 | |
3892 | 10110 // The encodings are generic. |
0 | 10111 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ |
3892 | 10112 predicate(!use_block_zeroing(n->in(2)) ); |
0 | 10113 match(Set dummy (ClearArray cnt base)); |
10114 effect(TEMP temp, KILL ccr); | |
10115 ins_cost(300); | |
10116 format %{ "MOV $cnt,$temp\n" | |
10117 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
10118 " BRge loop\t\t! Clearing loop\n" | |
10119 " STX G0,[$base+$temp]\t! delay slot" %} | |
3892 | 10120 |
10121 ins_encode %{ | |
10122 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
10123 Register nof_bytes_arg = $cnt$$Register; | |
10124 Register nof_bytes_tmp = $temp$$Register; | |
10125 Register base_pointer_arg = $base$$Register; | |
10126 | |
10127 Label loop; | |
10128 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
10129 | |
10130 // Loop and clear, walking backwards through the array. | |
10131 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
10132 __ bind(loop); | |
10133 __ deccc(nof_bytes_tmp, 8); | |
10134 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
10135 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
10136 // %%%% this mini-loop must not cross a cache boundary! | |
10137 %} | |
10138 ins_pipe(long_memory_op); | |
10139 %} | |
10140 | |
10141 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{ | |
10142 predicate(use_block_zeroing(n->in(2))); | |
10143 match(Set dummy (ClearArray cnt base)); | |
10144 effect(USE_KILL cnt, USE_KILL base, KILL ccr); | |
10145 ins_cost(300); | |
10146 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} | |
10147 | |
10148 ins_encode %{ | |
10149 | |
10150 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); | |
10151 Register to = $base$$Register; | |
10152 Register count = $cnt$$Register; | |
10153 | |
10154 Label Ldone; | |
10155 __ nop(); // Separate short branches | |
10156 // Use BIS for zeroing (temp is not used). | |
10157 __ bis_zeroing(to, count, G0, Ldone); | |
10158 __ bind(Ldone); | |
10159 | |
10160 %} | |
10161 ins_pipe(long_memory_op); | |
10162 %} | |
10163 | |
10164 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{ | |
10165 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit)); | |
10166 match(Set dummy (ClearArray cnt base)); | |
10167 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr); | |
10168 ins_cost(300); | |
10169 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} | |
10170 | |
10171 ins_encode %{ | |
10172 | |
10173 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); | |
10174 Register to = $base$$Register; | |
10175 Register count = $cnt$$Register; | |
10176 Register temp = $tmp$$Register; | |
10177 | |
10178 Label Ldone; | |
10179 __ nop(); // Separate short branches | |
10180 // Use BIS for zeroing | |
10181 __ bis_zeroing(to, count, temp, Ldone); | |
10182 __ bind(Ldone); | |
10183 | |
10184 %} | |
0 | 10185 ins_pipe(long_memory_op); |
10186 %} | |
10187 | |
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10188 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
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10189 o7RegI tmp, flagsReg ccr) %{ |
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10190 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
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10191 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
0 | 10192 ins_cost(300); |
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10193 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
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10194 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
0 | 10195 ins_pipe(long_memory_op); |
10196 %} | |
10197 | |
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10198 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
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10199 o7RegI tmp, flagsReg ccr) %{ |
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10200 match(Set result (StrEquals (Binary str1 str2) cnt)); |
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10201 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
681 | 10202 ins_cost(300); |
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10203 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
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10204 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
681 | 10205 ins_pipe(long_memory_op); |
10206 %} | |
10207 | |
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10208 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
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10209 o7RegI tmp2, flagsReg ccr) %{ |
681 | 10210 match(Set result (AryEq ary1 ary2)); |
10211 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
10212 ins_cost(300); | |
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10213 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
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10214 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
681 | 10215 ins_pipe(long_memory_op); |
10216 %} | |
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10217 |
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10218 |
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10219 //---------- Zeros Count Instructions ------------------------------------------ |
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10220 |
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10221 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
775
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10222 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
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10223 match(Set dst (CountLeadingZerosI src)); |
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10224 effect(TEMP dst, TEMP tmp, KILL cr); |
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10225 |
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10226 // x |= (x >> 1); |
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10227 // x |= (x >> 2); |
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10228 // x |= (x >> 4); |
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10229 // x |= (x >> 8); |
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10230 // x |= (x >> 16); |
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10231 // return (WORDBITS - popc(x)); |
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10232 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
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10233 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
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10234 "OR $dst,$tmp,$dst\n\t" |
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10235 "SRL $dst,2,$tmp\n\t" |
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10236 "OR $dst,$tmp,$dst\n\t" |
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10237 "SRL $dst,4,$tmp\n\t" |
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10238 "OR $dst,$tmp,$dst\n\t" |
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10239 "SRL $dst,8,$tmp\n\t" |
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10240 "OR $dst,$tmp,$dst\n\t" |
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10241 "SRL $dst,16,$tmp\n\t" |
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10242 "OR $dst,$tmp,$dst\n\t" |
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10243 "POPC $dst,$dst\n\t" |
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10244 "MOV 32,$tmp\n\t" |
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10245 "SUB $tmp,$dst,$dst" %} |
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changeset
|
10246 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10247 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10248 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10249 Register Rtmp = $tmp$$Register; |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10250 __ srl(Rsrc, 1, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10251 __ srl(Rsrc, 0, Rdst); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10252 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10253 __ srl(Rdst, 2, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10254 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10255 __ srl(Rdst, 4, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10256 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10257 __ srl(Rdst, 8, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10258 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10259 __ srl(Rdst, 16, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10260 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10261 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10262 __ mov(BitsPerInt, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10263 __ sub(Rtmp, Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10264 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10265 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10266 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10267 |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10268 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10269 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10270 match(Set dst (CountLeadingZerosL src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10271 effect(TEMP dst, TEMP tmp, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10272 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10273 // x |= (x >> 1); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10274 // x |= (x >> 2); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10275 // x |= (x >> 4); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10276 // x |= (x >> 8); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10277 // x |= (x >> 16); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10278 // x |= (x >> 32); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10279 // return (WORDBITS - popc(x)); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10280 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10281 "OR $src,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10282 "SRLX $dst,2,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10283 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10284 "SRLX $dst,4,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10285 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10286 "SRLX $dst,8,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10287 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10288 "SRLX $dst,16,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10289 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10290 "SRLX $dst,32,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10291 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10292 "POPC $dst,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10293 "MOV 64,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10294 "SUB $tmp,$dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10295 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10296 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10297 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10298 Register Rtmp = $tmp$$Register; |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10299 __ srlx(Rsrc, 1, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10300 __ or3( Rsrc, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10301 __ srlx(Rdst, 2, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10302 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10303 __ srlx(Rdst, 4, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10304 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10305 __ srlx(Rdst, 8, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10306 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10307 __ srlx(Rdst, 16, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10308 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10309 __ srlx(Rdst, 32, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10310 __ or3( Rdst, Rtmp, Rdst); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10311 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10312 __ mov(BitsPerLong, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10313 __ sub(Rtmp, Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10314 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10315 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10316 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10317 |
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10318 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{ |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10319 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10320 match(Set dst (CountTrailingZerosI src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10321 effect(TEMP dst, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10322 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10323 // return popc(~x & (x - 1)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10324 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10325 "ANDN $dst,$src,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10326 "SRL $dst,R_G0,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10327 "POPC $dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10328 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10329 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10330 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10331 __ sub(Rsrc, 1, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10332 __ andn(Rdst, Rsrc, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10333 __ srl(Rdst, G0, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10334 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10335 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10336 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10337 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10338 |
4003
4bac06a82bc3
7100757: The BitSet.nextSetBit() produces incorrect result in 32bit VM on Sparc
kvn
parents:
3898
diff
changeset
|
10339 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{ |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10340 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10341 match(Set dst (CountTrailingZerosL src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10342 effect(TEMP dst, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10343 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10344 // return popc(~x & (x - 1)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10345 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10346 "ANDN $dst,$src,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10347 "POPC $dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10348 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10349 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10350 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10351 __ sub(Rsrc, 1, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10352 __ andn(Rdst, Rsrc, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10353 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10354 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10355 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10356 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10357 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10358 |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10359 //---------- Population Count Instructions ------------------------------------- |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10360 |
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10361 instruct popCountI(iRegIsafe dst, iRegI src) %{ |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10362 predicate(UsePopCountInstruction); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10363 match(Set dst (PopCountI src)); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10364 |
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10365 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t" |
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10366 "POPC $dst, $dst" %} |
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10367 ins_encode %{ |
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10368 __ srl($src$$Register, G0, $dst$$Register); |
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10369 __ popc($dst$$Register, $dst$$Register); |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10370 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10371 ins_pipe(ialu_reg); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10372 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10373 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10374 // Note: Long.bitCount(long) returns an int. |
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10375 instruct popCountL(iRegIsafe dst, iRegL src) %{ |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10376 predicate(UsePopCountInstruction); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10377 match(Set dst (PopCountL src)); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10378 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10379 format %{ "POPC $src, $dst" %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10380 ins_encode %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10381 __ popc($src$$Register, $dst$$Register); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10382 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10383 ins_pipe(ialu_reg); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10384 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10385 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10386 |
0 | 10387 // ============================================================================ |
10388 //------------Bytes reverse-------------------------------------------------- | |
10389 | |
10390 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
10391 match(Set dst (ReverseBytesI src)); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10392 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10393 // Op cost is artificially doubled to make sure that load or store |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10394 // instructions are preferred over this one which requires a spill |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10395 // onto a stack slot. |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10396 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10397 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10398 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10399 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10400 __ set($src$$disp + STACK_BIAS, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10401 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10402 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10403 ins_pipe( iload_mem ); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10404 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10405 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10406 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10407 match(Set dst (ReverseBytesL src)); |
0 | 10408 |
10409 // Op cost is artificially doubled to make sure that load or store | |
10410 // instructions are preferred over this one which requires a spill | |
10411 // onto a stack slot. | |
10412 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10413 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10414 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10415 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10416 __ set($src$$disp + STACK_BIAS, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10417 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10418 %} |
0 | 10419 ins_pipe( iload_mem ); |
10420 %} | |
10421 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10422 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10423 match(Set dst (ReverseBytesUS src)); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10424 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10425 // Op cost is artificially doubled to make sure that load or store |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10426 // instructions are preferred over this one which requires a spill |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10427 // onto a stack slot. |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10428 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10429 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10430 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10431 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10432 // the value was spilled as an int so bias the load |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10433 __ set($src$$disp + STACK_BIAS + 2, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10434 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10435 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10436 ins_pipe( iload_mem ); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10437 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10438 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10439 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10440 match(Set dst (ReverseBytesS src)); |
0 | 10441 |
10442 // Op cost is artificially doubled to make sure that load or store | |
10443 // instructions are preferred over this one which requires a spill | |
10444 // onto a stack slot. | |
10445 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10446 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10447 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10448 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10449 // the value was spilled as an int so bias the load |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10450 __ set($src$$disp + STACK_BIAS + 2, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10451 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10452 %} |
0 | 10453 ins_pipe( iload_mem ); |
10454 %} | |
10455 | |
10456 // Load Integer reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10457 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ |
0 | 10458 match(Set dst (ReverseBytesI (LoadI src))); |
10459 | |
10460 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10461 size(4); |
0 | 10462 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
10463 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10464 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10465 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10466 %} |
0 | 10467 ins_pipe(iload_mem); |
10468 %} | |
10469 | |
10470 // Load Long - aligned and reversed | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10471 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ |
0 | 10472 match(Set dst (ReverseBytesL (LoadL src))); |
10473 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10474 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10475 size(4); |
0 | 10476 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
10477 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10478 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10479 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10480 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10481 ins_pipe(iload_mem); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10482 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10483 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10484 // Load unsigned short / char reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10485 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10486 match(Set dst (ReverseBytesUS (LoadUS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10487 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10488 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10489 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10490 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10491 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10492 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10493 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10494 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10495 ins_pipe(iload_mem); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10496 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10497 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10498 // Load short reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10499 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10500 match(Set dst (ReverseBytesS (LoadS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10501 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10502 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10503 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10504 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10505 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10506 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10507 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10508 %} |
0 | 10509 ins_pipe(iload_mem); |
10510 %} | |
10511 | |
10512 // Store Integer reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10513 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ |
0 | 10514 match(Set dst (StoreI dst (ReverseBytesI src))); |
10515 | |
10516 ins_cost(MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10517 size(4); |
0 | 10518 format %{ "STWA $src, $dst\t!asi=primary_little" %} |
10519 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10520 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10521 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10522 %} |
0 | 10523 ins_pipe(istore_mem_reg); |
10524 %} | |
10525 | |
10526 // Store Long reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10527 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ |
0 | 10528 match(Set dst (StoreL dst (ReverseBytesL src))); |
10529 | |
10530 ins_cost(MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10531 size(4); |
0 | 10532 format %{ "STXA $src, $dst\t!asi=primary_little" %} |
10533 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10534 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10535 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10536 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10537 ins_pipe(istore_mem_reg); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10538 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10539 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10540 // Store unsighed short/char reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10541 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10542 match(Set dst (StoreC dst (ReverseBytesUS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10543 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10544 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10545 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10546 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10547 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10548 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10549 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10550 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10551 ins_pipe(istore_mem_reg); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10552 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10553 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10554 // Store short reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10555 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10556 match(Set dst (StoreC dst (ReverseBytesS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10557 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10558 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10559 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10560 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10561 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10562 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10563 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10564 %} |
0 | 10565 ins_pipe(istore_mem_reg); |
10566 %} | |
10567 | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10568 // ====================VECTOR INSTRUCTIONS===================================== |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10569 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10570 // Load Aligned Packed values into a Double Register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10571 instruct loadV8(regD dst, memory mem) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10572 predicate(n->as_LoadVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10573 match(Set dst (LoadVector mem)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10574 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10575 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10576 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10577 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10578 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10579 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10580 ins_pipe(floadD_mem); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10581 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10582 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10583 // Store Vector in Double register to memory |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10584 instruct storeV8(memory mem, regD src) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10585 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10586 match(Set mem (StoreVector mem src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10587 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10588 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10589 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10590 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10591 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10592 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10593 ins_pipe(fstoreD_mem_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10594 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10595 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10596 // Store Zero into vector in memory |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10597 instruct storeV8B_zero(memory mem, immI0 zero) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10598 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10599 match(Set mem (StoreVector mem (ReplicateB zero))); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10600 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10601 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10602 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10603 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10604 __ stx(G0, $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10605 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10606 ins_pipe(fstoreD_mem_zero); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10607 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10608 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10609 instruct storeV4S_zero(memory mem, immI0 zero) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10610 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10611 match(Set mem (StoreVector mem (ReplicateS zero))); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10612 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10613 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10614 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10615 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10616 __ stx(G0, $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10617 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10618 ins_pipe(fstoreD_mem_zero); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10619 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10620 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10621 instruct storeV2I_zero(memory mem, immI0 zero) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10622 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10623 match(Set mem (StoreVector mem (ReplicateI zero))); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10624 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10625 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10626 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10627 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10628 __ stx(G0, $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10629 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10630 ins_pipe(fstoreD_mem_zero); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10631 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10632 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10633 instruct storeV2F_zero(memory mem, immF0 zero) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10634 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10635 match(Set mem (StoreVector mem (ReplicateF zero))); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10636 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10637 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10638 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10639 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10640 __ stx(G0, $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10641 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10642 ins_pipe(fstoreD_mem_zero); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10643 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10644 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10645 // Replicate scalar to packed byte values into Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10646 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10647 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10648 match(Set dst (ReplicateB src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10649 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10650 format %{ "SLLX $src,56,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10651 "SRLX $tmp, 8,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10652 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10653 "SRLX $tmp,16,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10654 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10655 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10656 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10657 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10658 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10659 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10660 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10661 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10662 __ sllx(Rsrc, 56, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10663 __ srlx(Rtmp, 8, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10664 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10665 __ srlx(Rtmp, 16, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10666 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10667 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10668 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10669 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10670 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10671 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10672 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10673 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10674 // Replicate scalar to packed byte values into Double stack |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10675 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10676 predicate(n->as_Vector()->length() == 8 && UseVIS < 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10677 match(Set dst (ReplicateB src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10678 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10679 format %{ "SLLX $src,56,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10680 "SRLX $tmp, 8,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10681 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10682 "SRLX $tmp,16,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10683 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10684 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10685 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10686 "STX $tmp,$dst\t! regL to stkD" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10687 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10688 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10689 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10690 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10691 __ sllx(Rsrc, 56, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10692 __ srlx(Rtmp, 8, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10693 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10694 __ srlx(Rtmp, 16, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10695 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10696 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10697 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10698 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10699 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10700 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10701 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10702 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10703 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10704 // Replicate scalar constant to packed byte values in Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10705 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10706 predicate(n->as_Vector()->length() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10707 match(Set dst (ReplicateB con)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10708 effect(KILL tmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10709 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10710 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10711 // XXX This is a quick fix for 6833573. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10712 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10713 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10714 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10715 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10716 ins_pipe(loadConFD); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10717 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10718 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10719 // Replicate scalar to packed char/short values into Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10720 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10721 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10722 match(Set dst (ReplicateS src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10723 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10724 format %{ "SLLX $src,48,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10725 "SRLX $tmp,16,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10726 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10727 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10728 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10729 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10730 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10731 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10732 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10733 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10734 __ sllx(Rsrc, 48, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10735 __ srlx(Rtmp, 16, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10736 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10737 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10738 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10739 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10740 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10741 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10742 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10743 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10744 // Replicate scalar to packed char/short values into Double stack |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10745 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10746 predicate(n->as_Vector()->length() == 4 && UseVIS < 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10747 match(Set dst (ReplicateS src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10748 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10749 format %{ "SLLX $src,48,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10750 "SRLX $tmp,16,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10751 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10752 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10753 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10754 "STX $tmp,$dst\t! regL to stkD" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10755 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10756 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10757 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10758 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10759 __ sllx(Rsrc, 48, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10760 __ srlx(Rtmp, 16, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10761 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10762 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10763 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10764 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10765 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10766 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10767 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10768 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10769 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10770 // Replicate scalar constant to packed char/short values in Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10771 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10772 predicate(n->as_Vector()->length() == 4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10773 match(Set dst (ReplicateS con)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10774 effect(KILL tmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10775 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10776 ins_encode %{ |
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10777 // XXX This is a quick fix for 6833573. |
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10778 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); |
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10779 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); |
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10780 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
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10781 %} |
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10782 ins_pipe(loadConFD); |
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|
10783 %} |
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|
10784 |
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10785 // Replicate scalar to packed int values into Double register |
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10786 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
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10787 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3); |
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10788 match(Set dst (ReplicateI src)); |
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10789 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
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10790 format %{ "SLLX $src,32,$tmp\n\t" |
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10791 "SRLX $tmp,32,$tmp2\n\t" |
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10792 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" |
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10793 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
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10794 ins_encode %{ |
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10795 Register Rsrc = $src$$Register; |
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10796 Register Rtmp = $tmp$$Register; |
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10797 Register Rtmp2 = $tmp2$$Register; |
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10798 __ sllx(Rsrc, 32, Rtmp); |
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10799 __ srlx(Rtmp, 32, Rtmp2); |
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10800 __ or3 (Rtmp, Rtmp2, Rtmp); |
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10801 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
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10802 %} |
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10803 ins_pipe(ialu_reg); |
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|
10804 %} |
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|
10805 |
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10806 // Replicate scalar to packed int values into Double stack |
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10807 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
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10808 predicate(n->as_Vector()->length() == 2 && UseVIS < 3); |
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10809 match(Set dst (ReplicateI src)); |
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10810 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
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10811 format %{ "SLLX $src,32,$tmp\n\t" |
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10812 "SRLX $tmp,32,$tmp2\n\t" |
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10813 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" |
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10814 "STX $tmp,$dst\t! regL to stkD" %} |
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10815 ins_encode %{ |
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10816 Register Rsrc = $src$$Register; |
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10817 Register Rtmp = $tmp$$Register; |
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10818 Register Rtmp2 = $tmp2$$Register; |
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10819 __ sllx(Rsrc, 32, Rtmp); |
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10820 __ srlx(Rtmp, 32, Rtmp2); |
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10821 __ or3 (Rtmp, Rtmp2, Rtmp); |
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10822 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
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10823 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
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|
10824 %} |
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|
10825 ins_pipe(ialu_reg); |
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|
10826 %} |
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|
10827 |
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|
10828 // Replicate scalar zero constant to packed int values in Double register |
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10829 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ |
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10830 predicate(n->as_Vector()->length() == 2); |
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10831 match(Set dst (ReplicateI con)); |
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|
10832 effect(KILL tmp); |
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|
10833 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} |
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|
10834 ins_encode %{ |
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|
10835 // XXX This is a quick fix for 6833573. |
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10836 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); |
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10837 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); |
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10838 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
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|
10839 %} |
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|
10840 ins_pipe(loadConFD); |
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|
10841 %} |
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|
10842 |
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|
10843 // Replicate scalar to packed float values into Double stack |
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|
10844 instruct Repl2F_stk(stackSlotD dst, regF src) %{ |
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|
10845 predicate(n->as_Vector()->length() == 2); |
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|
10846 match(Set dst (ReplicateF src)); |
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|
10847 ins_cost(MEMORY_REF_COST*2); |
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|
10848 format %{ "STF $src,$dst.hi\t! packed2F\n\t" |
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|
10849 "STF $src,$dst.lo" %} |
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|
10850 opcode(Assembler::stf_op3); |
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|
10851 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src)); |
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|
10852 ins_pipe(fstoreF_stk_reg); |
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|
10853 %} |
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|
10854 |
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|
10855 // Replicate scalar zero constant to packed float values in Double register |
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|
10856 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{ |
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|
10857 predicate(n->as_Vector()->length() == 2); |
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|
10858 match(Set dst (ReplicateF con)); |
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|
10859 effect(KILL tmp); |
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|
10860 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %} |
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|
10861 ins_encode %{ |
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|
10862 // XXX This is a quick fix for 6833573. |
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|
10863 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister); |
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|
10864 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register); |
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|
10865 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
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|
10866 %} |
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|
10867 ins_pipe(loadConFD); |
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|
10868 %} |
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|
10869 |
0 | 10870 //----------PEEPHOLE RULES----------------------------------------------------- |
10871 // These must follow all instruction definitions as they use the names | |
10872 // defined in the instructions definitions. | |
10873 // | |
605 | 10874 // peepmatch ( root_instr_name [preceding_instruction]* ); |
0 | 10875 // |
10876 // peepconstraint %{ | |
10877 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
10878 // [, ...] ); | |
10879 // // instruction numbers are zero-based using left to right order in peepmatch | |
10880 // | |
10881 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
10882 // // provide an instruction_number.operand_name for each operand that appears | |
10883 // // in the replacement instruction's match rule | |
10884 // | |
10885 // ---------VM FLAGS--------------------------------------------------------- | |
10886 // | |
10887 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
10888 // | |
10889 // Each peephole rule is given an identifying number starting with zero and | |
10890 // increasing by one in the order seen by the parser. An individual peephole | |
10891 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
10892 // on the command-line. | |
10893 // | |
10894 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
10895 // | |
10896 // Only match adjacent instructions in same basic block | |
10897 // Only equality constraints | |
10898 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
10899 // Only one replacement instruction | |
10900 // | |
10901 // ---------EXAMPLE---------------------------------------------------------- | |
10902 // | |
10903 // // pertinent parts of existing instructions in architecture description | |
10904 // instruct movI(eRegI dst, eRegI src) %{ | |
10905 // match(Set dst (CopyI src)); | |
10906 // %} | |
10907 // | |
10908 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
10909 // match(Set dst (AddI dst src)); | |
10910 // effect(KILL cr); | |
10911 // %} | |
10912 // | |
10913 // // Change (inc mov) to lea | |
10914 // peephole %{ | |
10915 // // increment preceeded by register-register move | |
10916 // peepmatch ( incI_eReg movI ); | |
10917 // // require that the destination register of the increment | |
10918 // // match the destination register of the move | |
10919 // peepconstraint ( 0.dst == 1.dst ); | |
10920 // // construct a replacement instruction that sets | |
10921 // // the destination to ( move's source register + one ) | |
10922 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
10923 // %} | |
10924 // | |
10925 | |
10926 // // Change load of spilled value to only a spill | |
10927 // instruct storeI(memory mem, eRegI src) %{ | |
10928 // match(Set mem (StoreI mem src)); | |
10929 // %} | |
10930 // | |
10931 // instruct loadI(eRegI dst, memory mem) %{ | |
10932 // match(Set dst (LoadI mem)); | |
10933 // %} | |
10934 // | |
10935 // peephole %{ | |
10936 // peepmatch ( loadI storeI ); | |
10937 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
10938 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
10939 // %} | |
10940 | |
10941 //----------SMARTSPILL RULES--------------------------------------------------- | |
10942 // These must follow all instruction definitions as they use the names | |
10943 // defined in the instructions definitions. | |
10944 // | |
10945 // SPARC will probably not have any of these rules due to RISC instruction set. | |
10946 | |
10947 //----------PIPELINE----------------------------------------------------------- | |
10948 // Rules which define the behavior of the target architectures pipeline. |