Mercurial > hg > truffle
annotate src/cpu/x86/vm/assembler_x86.cpp @ 8001:db9981fd3124
8005915: Unify SERIALGC and INCLUDE_ALTERNATE_GCS
Summary: Rename INCLUDE_ALTERNATE_GCS to INCLUDE_ALL_GCS and replace SERIALGC with INCLUDE_ALL_GCS.
Reviewed-by: coleenp, stefank
author | jprovino |
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date | Wed, 23 Jan 2013 13:02:39 -0500 |
parents | 038dd2875b94 |
children | 8391fdd36e1f |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/assembler.hpp" |
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27 #include "asm/assembler.inline.hpp" |
1972 | 28 #include "gc_interface/collectedHeap.inline.hpp" |
29 #include "interpreter/interpreter.hpp" | |
30 #include "memory/cardTableModRefBS.hpp" | |
31 #include "memory/resourceArea.hpp" | |
32 #include "prims/methodHandles.hpp" | |
33 #include "runtime/biasedLocking.hpp" | |
34 #include "runtime/interfaceSupport.hpp" | |
35 #include "runtime/objectMonitor.hpp" | |
36 #include "runtime/os.hpp" | |
37 #include "runtime/sharedRuntime.hpp" | |
38 #include "runtime/stubRoutines.hpp" | |
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39 #include "utilities/macros.hpp" |
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40 #if INCLUDE_ALL_GCS |
1972 | 41 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" |
42 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" | |
43 #include "gc_implementation/g1/heapRegion.hpp" | |
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44 #endif // INCLUDE_ALL_GCS |
0 | 45 |
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46 #ifdef PRODUCT |
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47 #define BLOCK_COMMENT(str) /* nothing */ |
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48 #define STOP(error) stop(error) |
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49 #else |
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50 #define BLOCK_COMMENT(str) block_comment(str) |
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51 #define STOP(error) block_comment(error); stop(error) |
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52 #endif |
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53 |
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54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") |
0 | 55 // Implementation of AddressLiteral |
56 | |
57 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { | |
58 _is_lval = false; | |
59 _target = target; | |
60 switch (rtype) { | |
61 case relocInfo::oop_type: | |
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62 case relocInfo::metadata_type: |
0 | 63 // Oops are a special case. Normally they would be their own section |
64 // but in cases like icBuffer they are literals in the code stream that | |
65 // we don't have a section for. We use none so that we get a literal address | |
66 // which is always patchable. | |
67 break; | |
68 case relocInfo::external_word_type: | |
69 _rspec = external_word_Relocation::spec(target); | |
70 break; | |
71 case relocInfo::internal_word_type: | |
72 _rspec = internal_word_Relocation::spec(target); | |
73 break; | |
74 case relocInfo::opt_virtual_call_type: | |
75 _rspec = opt_virtual_call_Relocation::spec(); | |
76 break; | |
77 case relocInfo::static_call_type: | |
78 _rspec = static_call_Relocation::spec(); | |
79 break; | |
80 case relocInfo::runtime_call_type: | |
81 _rspec = runtime_call_Relocation::spec(); | |
82 break; | |
83 case relocInfo::poll_type: | |
84 case relocInfo::poll_return_type: | |
85 _rspec = Relocation::spec_simple(rtype); | |
86 break; | |
87 case relocInfo::none: | |
88 break; | |
89 default: | |
90 ShouldNotReachHere(); | |
91 break; | |
92 } | |
93 } | |
94 | |
95 // Implementation of Address | |
96 | |
304 | 97 #ifdef _LP64 |
98 | |
0 | 99 Address Address::make_array(ArrayAddress adr) { |
100 // Not implementable on 64bit machines | |
101 // Should have been handled higher up the call chain. | |
102 ShouldNotReachHere(); | |
304 | 103 return Address(); |
104 } | |
105 | |
106 // exceedingly dangerous constructor | |
107 Address::Address(int disp, address loc, relocInfo::relocType rtype) { | |
108 _base = noreg; | |
109 _index = noreg; | |
110 _scale = no_scale; | |
111 _disp = disp; | |
112 switch (rtype) { | |
113 case relocInfo::external_word_type: | |
114 _rspec = external_word_Relocation::spec(loc); | |
115 break; | |
116 case relocInfo::internal_word_type: | |
117 _rspec = internal_word_Relocation::spec(loc); | |
118 break; | |
119 case relocInfo::runtime_call_type: | |
120 // HMM | |
121 _rspec = runtime_call_Relocation::spec(); | |
122 break; | |
123 case relocInfo::poll_type: | |
124 case relocInfo::poll_return_type: | |
125 _rspec = Relocation::spec_simple(rtype); | |
126 break; | |
127 case relocInfo::none: | |
128 break; | |
129 default: | |
130 ShouldNotReachHere(); | |
131 } | |
132 } | |
133 #else // LP64 | |
134 | |
135 Address Address::make_array(ArrayAddress adr) { | |
0 | 136 AddressLiteral base = adr.base(); |
137 Address index = adr.index(); | |
138 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
139 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); | |
140 array._rspec = base._rspec; | |
141 return array; | |
304 | 142 } |
0 | 143 |
144 // exceedingly dangerous constructor | |
145 Address::Address(address loc, RelocationHolder spec) { | |
146 _base = noreg; | |
147 _index = noreg; | |
148 _scale = no_scale; | |
149 _disp = (intptr_t) loc; | |
150 _rspec = spec; | |
151 } | |
304 | 152 |
0 | 153 #endif // _LP64 |
154 | |
304 | 155 |
156 | |
0 | 157 // Convert the raw encoding form into the form expected by the constructor for |
158 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
159 // that to noreg for the Address constructor. | |
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160 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) { |
624 | 161 RelocationHolder rspec; |
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162 if (disp_reloc != relocInfo::none) { |
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163 rspec = Relocation::spec_simple(disp_reloc); |
624 | 164 } |
0 | 165 bool valid_index = index != rsp->encoding(); |
166 if (valid_index) { | |
167 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); | |
624 | 168 madr._rspec = rspec; |
0 | 169 return madr; |
170 } else { | |
171 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); | |
624 | 172 madr._rspec = rspec; |
0 | 173 return madr; |
174 } | |
175 } | |
176 | |
177 // Implementation of Assembler | |
178 | |
179 int AbstractAssembler::code_fill_byte() { | |
180 return (u_char)'\xF4'; // hlt | |
181 } | |
182 | |
183 // make this go away someday | |
184 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { | |
185 if (rtype == relocInfo::none) | |
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186 emit_int32(data); |
0 | 187 else emit_data(data, Relocation::spec_simple(rtype), format); |
188 } | |
189 | |
190 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { | |
304 | 191 assert(imm_operand == 0, "default format must be immediate in this file"); |
0 | 192 assert(inst_mark() != NULL, "must be inside InstructionMark"); |
193 if (rspec.type() != relocInfo::none) { | |
194 #ifdef ASSERT | |
195 check_relocation(rspec, format); | |
196 #endif | |
197 // Do not use AbstractAssembler::relocate, which is not intended for | |
198 // embedded words. Instead, relocate to the enclosing instruction. | |
199 | |
200 // hack. call32 is too wide for mask so use disp32 | |
201 if (format == call32_operand) | |
202 code_section()->relocate(inst_mark(), rspec, disp32_operand); | |
203 else | |
204 code_section()->relocate(inst_mark(), rspec, format); | |
205 } | |
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206 emit_int32(data); |
0 | 207 } |
208 | |
304 | 209 static int encode(Register r) { |
210 int enc = r->encoding(); | |
211 if (enc >= 8) { | |
212 enc -= 8; | |
213 } | |
214 return enc; | |
215 } | |
216 | |
217 static int encode(XMMRegister r) { | |
218 int enc = r->encoding(); | |
219 if (enc >= 8) { | |
220 enc -= 8; | |
221 } | |
222 return enc; | |
223 } | |
0 | 224 |
225 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { | |
226 assert(dst->has_byte_register(), "must have byte register"); | |
227 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
228 assert(isByte(imm8), "not a byte"); | |
229 assert((op1 & 0x01) == 0, "should be 8bit operation"); | |
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230 emit_int8(op1); |
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231 emit_int8(op2 | encode(dst)); |
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232 emit_int8(imm8); |
0 | 233 } |
234 | |
235 | |
304 | 236 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { |
0 | 237 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
238 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
239 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
240 if (is8bit(imm32)) { | |
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241 emit_int8(op1 | 0x02); // set sign bit |
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242 emit_int8(op2 | encode(dst)); |
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243 emit_int8(imm32 & 0xFF); |
0 | 244 } else { |
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245 emit_int8(op1); |
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246 emit_int8(op2 | encode(dst)); |
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247 emit_int32(imm32); |
0 | 248 } |
249 } | |
250 | |
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251 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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252 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { |
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253 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
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254 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
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255 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); |
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256 emit_int8(op1); |
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257 emit_int8(op2 | encode(dst)); |
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258 emit_int32(imm32); |
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259 } |
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260 |
0 | 261 // immediate-to-memory forms |
304 | 262 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { |
0 | 263 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
264 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
265 if (is8bit(imm32)) { | |
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266 emit_int8(op1 | 0x02); // set sign bit |
304 | 267 emit_operand(rm, adr, 1); |
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268 emit_int8(imm32 & 0xFF); |
0 | 269 } else { |
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270 emit_int8(op1); |
304 | 271 emit_operand(rm, adr, 4); |
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272 emit_int32(imm32); |
0 | 273 } |
274 } | |
275 | |
276 | |
277 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { | |
278 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
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279 emit_int8(op1); |
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280 emit_int8(op2 | encode(dst) << 3 | encode(src)); |
304 | 281 } |
282 | |
283 | |
284 void Assembler::emit_operand(Register reg, Register base, Register index, | |
285 Address::ScaleFactor scale, int disp, | |
286 RelocationHolder const& rspec, | |
287 int rip_relative_correction) { | |
0 | 288 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); |
304 | 289 |
290 // Encode the registers as needed in the fields they are used in | |
291 | |
292 int regenc = encode(reg) << 3; | |
293 int indexenc = index->is_valid() ? encode(index) << 3 : 0; | |
294 int baseenc = base->is_valid() ? encode(base) : 0; | |
295 | |
0 | 296 if (base->is_valid()) { |
297 if (index->is_valid()) { | |
298 assert(scale != Address::no_scale, "inconsistent address"); | |
299 // [base + index*scale + disp] | |
304 | 300 if (disp == 0 && rtype == relocInfo::none && |
301 base != rbp LP64_ONLY(&& base != r13)) { | |
0 | 302 // [base + index*scale] |
303 // [00 reg 100][ss index base] | |
304 assert(index != rsp, "illegal addressing mode"); | |
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305 emit_int8(0x04 | regenc); |
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306 emit_int8(scale << 6 | indexenc | baseenc); |
0 | 307 } else if (is8bit(disp) && rtype == relocInfo::none) { |
308 // [base + index*scale + imm8] | |
309 // [01 reg 100][ss index base] imm8 | |
310 assert(index != rsp, "illegal addressing mode"); | |
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311 emit_int8(0x44 | regenc); |
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312 emit_int8(scale << 6 | indexenc | baseenc); |
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313 emit_int8(disp & 0xFF); |
0 | 314 } else { |
304 | 315 // [base + index*scale + disp32] |
316 // [10 reg 100][ss index base] disp32 | |
0 | 317 assert(index != rsp, "illegal addressing mode"); |
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318 emit_int8(0x84 | regenc); |
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319 emit_int8(scale << 6 | indexenc | baseenc); |
0 | 320 emit_data(disp, rspec, disp32_operand); |
321 } | |
304 | 322 } else if (base == rsp LP64_ONLY(|| base == r12)) { |
323 // [rsp + disp] | |
0 | 324 if (disp == 0 && rtype == relocInfo::none) { |
304 | 325 // [rsp] |
0 | 326 // [00 reg 100][00 100 100] |
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327 emit_int8(0x04 | regenc); |
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328 emit_int8(0x24); |
0 | 329 } else if (is8bit(disp) && rtype == relocInfo::none) { |
304 | 330 // [rsp + imm8] |
331 // [01 reg 100][00 100 100] disp8 | |
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332 emit_int8(0x44 | regenc); |
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333 emit_int8(0x24); |
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334 emit_int8(disp & 0xFF); |
0 | 335 } else { |
304 | 336 // [rsp + imm32] |
337 // [10 reg 100][00 100 100] disp32 | |
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338 emit_int8(0x84 | regenc); |
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339 emit_int8(0x24); |
0 | 340 emit_data(disp, rspec, disp32_operand); |
341 } | |
342 } else { | |
343 // [base + disp] | |
304 | 344 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); |
345 if (disp == 0 && rtype == relocInfo::none && | |
346 base != rbp LP64_ONLY(&& base != r13)) { | |
0 | 347 // [base] |
348 // [00 reg base] | |
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349 emit_int8(0x00 | regenc | baseenc); |
0 | 350 } else if (is8bit(disp) && rtype == relocInfo::none) { |
304 | 351 // [base + disp8] |
352 // [01 reg base] disp8 | |
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353 emit_int8(0x40 | regenc | baseenc); |
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354 emit_int8(disp & 0xFF); |
0 | 355 } else { |
304 | 356 // [base + disp32] |
357 // [10 reg base] disp32 | |
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358 emit_int8(0x80 | regenc | baseenc); |
0 | 359 emit_data(disp, rspec, disp32_operand); |
360 } | |
361 } | |
362 } else { | |
363 if (index->is_valid()) { | |
364 assert(scale != Address::no_scale, "inconsistent address"); | |
365 // [index*scale + disp] | |
304 | 366 // [00 reg 100][ss index 101] disp32 |
0 | 367 assert(index != rsp, "illegal addressing mode"); |
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368 emit_int8(0x04 | regenc); |
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369 emit_int8(scale << 6 | indexenc | 0x05); |
0 | 370 emit_data(disp, rspec, disp32_operand); |
304 | 371 } else if (rtype != relocInfo::none ) { |
372 // [disp] (64bit) RIP-RELATIVE (32bit) abs | |
373 // [00 000 101] disp32 | |
374 | |
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375 emit_int8(0x05 | regenc); |
304 | 376 // Note that the RIP-rel. correction applies to the generated |
377 // disp field, but _not_ to the target address in the rspec. | |
378 | |
379 // disp was created by converting the target address minus the pc | |
380 // at the start of the instruction. That needs more correction here. | |
381 // intptr_t disp = target - next_ip; | |
382 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
383 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; | |
384 int64_t adjusted = disp; | |
385 // Do rip-rel adjustment for 64bit | |
386 LP64_ONLY(adjusted -= (next_ip - inst_mark())); | |
387 assert(is_simm32(adjusted), | |
388 "must be 32bit offset (RIP relative address)"); | |
389 emit_data((int32_t) adjusted, rspec, disp32_operand); | |
390 | |
0 | 391 } else { |
304 | 392 // 32bit never did this, did everything as the rip-rel/disp code above |
393 // [disp] ABSOLUTE | |
394 // [00 reg 100][00 100 101] disp32 | |
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395 emit_int8(0x04 | regenc); |
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396 emit_int8(0x25); |
0 | 397 emit_data(disp, rspec, disp32_operand); |
398 } | |
399 } | |
400 } | |
401 | |
304 | 402 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, |
403 Address::ScaleFactor scale, int disp, | |
404 RelocationHolder const& rspec) { | |
405 emit_operand((Register)reg, base, index, scale, disp, rspec); | |
406 } | |
407 | |
0 | 408 // Secret local extension to Assembler::WhichOperand: |
409 #define end_pc_operand (_WhichOperand_limit) | |
410 | |
411 address Assembler::locate_operand(address inst, WhichOperand which) { | |
412 // Decode the given instruction, and return the address of | |
413 // an embedded 32-bit operand word. | |
414 | |
415 // If "which" is disp32_operand, selects the displacement portion | |
416 // of an effective address specifier. | |
304 | 417 // If "which" is imm64_operand, selects the trailing immediate constant. |
0 | 418 // If "which" is call32_operand, selects the displacement of a call or jump. |
419 // Caller is responsible for ensuring that there is such an operand, | |
304 | 420 // and that it is 32/64 bits wide. |
0 | 421 |
422 // If "which" is end_pc_operand, find the end of the instruction. | |
423 | |
424 address ip = inst; | |
304 | 425 bool is_64bit = false; |
426 | |
427 debug_only(bool has_disp32 = false); | |
428 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn | |
429 | |
430 again_after_prefix: | |
0 | 431 switch (0xFF & *ip++) { |
432 | |
433 // These convenience macros generate groups of "case" labels for the switch. | |
304 | 434 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 |
435 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ | |
0 | 436 case (x)+4: case (x)+5: case (x)+6: case (x)+7 |
304 | 437 #define REP16(x) REP8((x)+0): \ |
0 | 438 case REP8((x)+8) |
439 | |
440 case CS_segment: | |
441 case SS_segment: | |
442 case DS_segment: | |
443 case ES_segment: | |
444 case FS_segment: | |
445 case GS_segment: | |
304 | 446 // Seems dubious |
447 LP64_ONLY(assert(false, "shouldn't have that prefix")); | |
0 | 448 assert(ip == inst+1, "only one prefix allowed"); |
449 goto again_after_prefix; | |
450 | |
304 | 451 case 0x67: |
452 case REX: | |
453 case REX_B: | |
454 case REX_X: | |
455 case REX_XB: | |
456 case REX_R: | |
457 case REX_RB: | |
458 case REX_RX: | |
459 case REX_RXB: | |
460 NOT_LP64(assert(false, "64bit prefixes")); | |
461 goto again_after_prefix; | |
462 | |
463 case REX_W: | |
464 case REX_WB: | |
465 case REX_WX: | |
466 case REX_WXB: | |
467 case REX_WR: | |
468 case REX_WRB: | |
469 case REX_WRX: | |
470 case REX_WRXB: | |
471 NOT_LP64(assert(false, "64bit prefixes")); | |
472 is_64bit = true; | |
473 goto again_after_prefix; | |
474 | |
475 case 0xFF: // pushq a; decl a; incl a; call a; jmp a | |
0 | 476 case 0x88: // movb a, r |
477 case 0x89: // movl a, r | |
478 case 0x8A: // movb r, a | |
479 case 0x8B: // movl r, a | |
480 case 0x8F: // popl a | |
304 | 481 debug_only(has_disp32 = true); |
0 | 482 break; |
483 | |
304 | 484 case 0x68: // pushq #32 |
485 if (which == end_pc_operand) { | |
486 return ip + 4; | |
487 } | |
488 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); | |
0 | 489 return ip; // not produced by emit_operand |
490 | |
491 case 0x66: // movw ... (size prefix) | |
304 | 492 again_after_size_prefix2: |
0 | 493 switch (0xFF & *ip++) { |
304 | 494 case REX: |
495 case REX_B: | |
496 case REX_X: | |
497 case REX_XB: | |
498 case REX_R: | |
499 case REX_RB: | |
500 case REX_RX: | |
501 case REX_RXB: | |
502 case REX_W: | |
503 case REX_WB: | |
504 case REX_WX: | |
505 case REX_WXB: | |
506 case REX_WR: | |
507 case REX_WRB: | |
508 case REX_WRX: | |
509 case REX_WRXB: | |
510 NOT_LP64(assert(false, "64bit prefix found")); | |
511 goto again_after_size_prefix2; | |
0 | 512 case 0x8B: // movw r, a |
513 case 0x89: // movw a, r | |
304 | 514 debug_only(has_disp32 = true); |
0 | 515 break; |
516 case 0xC7: // movw a, #16 | |
304 | 517 debug_only(has_disp32 = true); |
0 | 518 tail_size = 2; // the imm16 |
519 break; | |
520 case 0x0F: // several SSE/SSE2 variants | |
521 ip--; // reparse the 0x0F | |
522 goto again_after_prefix; | |
523 default: | |
524 ShouldNotReachHere(); | |
525 } | |
526 break; | |
527 | |
304 | 528 case REP8(0xB8): // movl/q r, #32/#64(oop?) |
529 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); | |
530 // these asserts are somewhat nonsensical | |
531 #ifndef _LP64 | |
5984 | 532 assert(which == imm_operand || which == disp32_operand, |
533 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip)); | |
304 | 534 #else |
535 assert((which == call32_operand || which == imm_operand) && is_64bit || | |
5984 | 536 which == narrow_oop_operand && !is_64bit, |
537 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip)); | |
304 | 538 #endif // _LP64 |
0 | 539 return ip; |
540 | |
541 case 0x69: // imul r, a, #32 | |
542 case 0xC7: // movl a, #32(oop?) | |
543 tail_size = 4; | |
304 | 544 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 545 break; |
546 | |
547 case 0x0F: // movx..., etc. | |
548 switch (0xFF & *ip++) { | |
4759 | 549 case 0x3A: // pcmpestri |
550 tail_size = 1; | |
551 case 0x38: // ptest, pmovzxbw | |
552 ip++; // skip opcode | |
553 debug_only(has_disp32 = true); // has both kinds of operands! | |
554 break; | |
555 | |
556 case 0x70: // pshufd r, r/a, #8 | |
557 debug_only(has_disp32 = true); // has both kinds of operands! | |
558 case 0x73: // psrldq r, #8 | |
559 tail_size = 1; | |
560 break; | |
561 | |
0 | 562 case 0x12: // movlps |
563 case 0x28: // movaps | |
564 case 0x2E: // ucomiss | |
565 case 0x2F: // comiss | |
566 case 0x54: // andps | |
567 case 0x55: // andnps | |
568 case 0x56: // orps | |
569 case 0x57: // xorps | |
570 case 0x6E: // movd | |
571 case 0x7E: // movd | |
4759 | 572 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush |
304 | 573 debug_only(has_disp32 = true); |
0 | 574 break; |
575 | |
576 case 0xAD: // shrd r, a, %cl | |
577 case 0xAF: // imul r, a | |
304 | 578 case 0xBE: // movsbl r, a (movsxb) |
579 case 0xBF: // movswl r, a (movsxw) | |
580 case 0xB6: // movzbl r, a (movzxb) | |
581 case 0xB7: // movzwl r, a (movzxw) | |
0 | 582 case REP16(0x40): // cmovl cc, r, a |
583 case 0xB0: // cmpxchgb | |
584 case 0xB1: // cmpxchg | |
585 case 0xC1: // xaddl | |
586 case 0xC7: // cmpxchg8 | |
587 case REP16(0x90): // setcc a | |
304 | 588 debug_only(has_disp32 = true); |
0 | 589 // fall out of the switch to decode the address |
590 break; | |
304 | 591 |
4759 | 592 case 0xC4: // pinsrw r, a, #8 |
593 debug_only(has_disp32 = true); | |
594 case 0xC5: // pextrw r, r, #8 | |
595 tail_size = 1; // the imm8 | |
596 break; | |
597 | |
0 | 598 case 0xAC: // shrd r, a, #8 |
304 | 599 debug_only(has_disp32 = true); |
0 | 600 tail_size = 1; // the imm8 |
601 break; | |
304 | 602 |
0 | 603 case REP16(0x80): // jcc rdisp32 |
604 if (which == end_pc_operand) return ip + 4; | |
304 | 605 assert(which == call32_operand, "jcc has no disp32 or imm"); |
0 | 606 return ip; |
607 default: | |
608 ShouldNotReachHere(); | |
609 } | |
610 break; | |
611 | |
612 case 0x81: // addl a, #32; addl r, #32 | |
613 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
304 | 614 // on 32bit in the case of cmpl, the imm might be an oop |
0 | 615 tail_size = 4; |
304 | 616 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 617 break; |
618 | |
619 case 0x83: // addl a, #8; addl r, #8 | |
620 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
304 | 621 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 622 tail_size = 1; |
623 break; | |
624 | |
625 case 0x9B: | |
626 switch (0xFF & *ip++) { | |
627 case 0xD9: // fnstcw a | |
304 | 628 debug_only(has_disp32 = true); |
0 | 629 break; |
630 default: | |
631 ShouldNotReachHere(); | |
632 } | |
633 break; | |
634 | |
635 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a | |
636 case REP4(0x10): // adc... | |
637 case REP4(0x20): // and... | |
638 case REP4(0x30): // xor... | |
639 case REP4(0x08): // or... | |
640 case REP4(0x18): // sbb... | |
641 case REP4(0x28): // sub... | |
304 | 642 case 0xF7: // mull a |
643 case 0x8D: // lea r, a | |
644 case 0x87: // xchg r, a | |
0 | 645 case REP4(0x38): // cmp... |
304 | 646 case 0x85: // test r, a |
647 debug_only(has_disp32 = true); // has both kinds of operands! | |
0 | 648 break; |
649 | |
650 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 | |
651 case 0xC6: // movb a, #8 | |
652 case 0x80: // cmpb a, #8 | |
653 case 0x6B: // imul r, a, #8 | |
304 | 654 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 655 tail_size = 1; // the imm8 |
656 break; | |
657 | |
4759 | 658 case 0xC4: // VEX_3bytes |
659 case 0xC5: // VEX_2bytes | |
660 assert((UseAVX > 0), "shouldn't have VEX prefix"); | |
661 assert(ip == inst+1, "no prefixes allowed"); | |
662 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions | |
663 // but they have prefix 0x0F and processed when 0x0F processed above. | |
664 // | |
665 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES | |
666 // instructions (these instructions are not supported in 64-bit mode). | |
667 // To distinguish them bits [7:6] are set in the VEX second byte since | |
668 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set | |
669 // those VEX bits REX and vvvv bits are inverted. | |
670 // | |
671 // Fortunately C2 doesn't generate these instructions so we don't need | |
672 // to check for them in product version. | |
673 | |
674 // Check second byte | |
675 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); | |
676 | |
677 // First byte | |
678 if ((0xFF & *inst) == VEX_3bytes) { | |
679 ip++; // third byte | |
680 is_64bit = ((VEX_W & *ip) == VEX_W); | |
681 } | |
682 ip++; // opcode | |
683 // To find the end of instruction (which == end_pc_operand). | |
684 switch (0xFF & *ip) { | |
685 case 0x61: // pcmpestri r, r/a, #8 | |
686 case 0x70: // pshufd r, r/a, #8 | |
687 case 0x73: // psrldq r, #8 | |
688 tail_size = 1; // the imm8 | |
689 break; | |
690 default: | |
691 break; | |
692 } | |
693 ip++; // skip opcode | |
694 debug_only(has_disp32 = true); // has both kinds of operands! | |
695 break; | |
0 | 696 |
697 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | |
698 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | |
699 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | |
700 case 0xDD: // fld_d a; fst_d a; fstp_d a | |
701 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a | |
702 case 0xDF: // fild_d a; fistp_d a | |
703 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | |
704 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | |
705 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | |
304 | 706 debug_only(has_disp32 = true); |
0 | 707 break; |
708 | |
4759 | 709 case 0xE8: // call rdisp32 |
710 case 0xE9: // jmp rdisp32 | |
711 if (which == end_pc_operand) return ip + 4; | |
712 assert(which == call32_operand, "call has no disp32 or imm"); | |
713 return ip; | |
714 | |
420
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715 case 0xF0: // Lock |
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716 assert(os::is_MP(), "only on MP"); |
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717 goto again_after_prefix; |
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718 |
0 | 719 case 0xF3: // For SSE |
720 case 0xF2: // For SSE2 | |
304 | 721 switch (0xFF & *ip++) { |
722 case REX: | |
723 case REX_B: | |
724 case REX_X: | |
725 case REX_XB: | |
726 case REX_R: | |
727 case REX_RB: | |
728 case REX_RX: | |
729 case REX_RXB: | |
730 case REX_W: | |
731 case REX_WB: | |
732 case REX_WX: | |
733 case REX_WXB: | |
734 case REX_WR: | |
735 case REX_WRB: | |
736 case REX_WRX: | |
737 case REX_WRXB: | |
738 NOT_LP64(assert(false, "found 64bit prefix")); | |
739 ip++; | |
740 default: | |
741 ip++; | |
742 } | |
743 debug_only(has_disp32 = true); // has both kinds of operands! | |
0 | 744 break; |
745 | |
746 default: | |
747 ShouldNotReachHere(); | |
748 | |
304 | 749 #undef REP8 |
750 #undef REP16 | |
0 | 751 } |
752 | |
753 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); | |
304 | 754 #ifdef _LP64 |
755 assert(which != imm_operand, "instruction is not a movq reg, imm64"); | |
756 #else | |
757 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); | |
758 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); | |
759 #endif // LP64 | |
760 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); | |
0 | 761 |
762 // parse the output of emit_operand | |
763 int op2 = 0xFF & *ip++; | |
764 int base = op2 & 0x07; | |
765 int op3 = -1; | |
766 const int b100 = 4; | |
767 const int b101 = 5; | |
768 if (base == b100 && (op2 >> 6) != 3) { | |
769 op3 = 0xFF & *ip++; | |
770 base = op3 & 0x07; // refetch the base | |
771 } | |
772 // now ip points at the disp (if any) | |
773 | |
774 switch (op2 >> 6) { | |
775 case 0: | |
776 // [00 reg 100][ss index base] | |
304 | 777 // [00 reg 100][00 100 esp] |
0 | 778 // [00 reg base] |
779 // [00 reg 100][ss index 101][disp32] | |
780 // [00 reg 101] [disp32] | |
781 | |
782 if (base == b101) { | |
783 if (which == disp32_operand) | |
784 return ip; // caller wants the disp32 | |
785 ip += 4; // skip the disp32 | |
786 } | |
787 break; | |
788 | |
789 case 1: | |
790 // [01 reg 100][ss index base][disp8] | |
304 | 791 // [01 reg 100][00 100 esp][disp8] |
0 | 792 // [01 reg base] [disp8] |
793 ip += 1; // skip the disp8 | |
794 break; | |
795 | |
796 case 2: | |
797 // [10 reg 100][ss index base][disp32] | |
304 | 798 // [10 reg 100][00 100 esp][disp32] |
0 | 799 // [10 reg base] [disp32] |
800 if (which == disp32_operand) | |
801 return ip; // caller wants the disp32 | |
802 ip += 4; // skip the disp32 | |
803 break; | |
804 | |
805 case 3: | |
806 // [11 reg base] (not a memory addressing mode) | |
807 break; | |
808 } | |
809 | |
810 if (which == end_pc_operand) { | |
811 return ip + tail_size; | |
812 } | |
813 | |
304 | 814 #ifdef _LP64 |
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815 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); |
304 | 816 #else |
817 assert(which == imm_operand, "instruction has only an imm field"); | |
818 #endif // LP64 | |
0 | 819 return ip; |
820 } | |
821 | |
822 address Assembler::locate_next_instruction(address inst) { | |
823 // Secretly share code with locate_operand: | |
824 return locate_operand(inst, end_pc_operand); | |
825 } | |
826 | |
827 | |
828 #ifdef ASSERT | |
829 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { | |
830 address inst = inst_mark(); | |
831 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); | |
832 address opnd; | |
833 | |
834 Relocation* r = rspec.reloc(); | |
835 if (r->type() == relocInfo::none) { | |
836 return; | |
837 } else if (r->is_call() || format == call32_operand) { | |
838 // assert(format == imm32_operand, "cannot specify a nonzero format"); | |
839 opnd = locate_operand(inst, call32_operand); | |
840 } else if (r->is_data()) { | |
304 | 841 assert(format == imm_operand || format == disp32_operand |
842 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); | |
0 | 843 opnd = locate_operand(inst, (WhichOperand)format); |
844 } else { | |
304 | 845 assert(format == imm_operand, "cannot specify a format"); |
0 | 846 return; |
847 } | |
848 assert(opnd == pc(), "must put operand where relocs can find it"); | |
849 } | |
304 | 850 #endif // ASSERT |
851 | |
852 void Assembler::emit_operand32(Register reg, Address adr) { | |
853 assert(reg->encoding() < 8, "no extended registers"); | |
854 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
855 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
856 adr._rspec); | |
857 } | |
858 | |
859 void Assembler::emit_operand(Register reg, Address adr, | |
860 int rip_relative_correction) { | |
861 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
862 adr._rspec, | |
863 rip_relative_correction); | |
864 } | |
865 | |
866 void Assembler::emit_operand(XMMRegister reg, Address adr) { | |
867 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
868 adr._rspec); | |
869 } | |
870 | |
871 // MMX operations | |
872 void Assembler::emit_operand(MMXRegister reg, Address adr) { | |
873 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
874 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
875 } | |
876 | |
877 // work around gcc (3.2.1-7a) bug | |
878 void Assembler::emit_operand(Address adr, MMXRegister reg) { | |
879 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
880 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
0 | 881 } |
882 | |
883 | |
884 void Assembler::emit_farith(int b1, int b2, int i) { | |
885 assert(isByte(b1) && isByte(b2), "wrong opcode"); | |
886 assert(0 <= i && i < 8, "illegal stack offset"); | |
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887 emit_int8(b1); |
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888 emit_int8(b2 + i); |
0 | 889 } |
890 | |
891 | |
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892 // Now the Assembler instructions (identical for 32/64 bits) |
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893 |
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894 void Assembler::adcl(Address dst, int32_t imm32) { |
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895 InstructionMark im(this); |
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896 prefix(dst); |
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897 emit_arith_operand(0x81, rdx, dst, imm32); |
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898 } |
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899 |
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900 void Assembler::adcl(Address dst, Register src) { |
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901 InstructionMark im(this); |
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902 prefix(dst, src); |
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903 emit_int8(0x11); |
2100
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904 emit_operand(src, dst); |
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905 } |
304 | 906 |
907 void Assembler::adcl(Register dst, int32_t imm32) { | |
908 prefix(dst); | |
0 | 909 emit_arith(0x81, 0xD0, dst, imm32); |
910 } | |
911 | |
912 void Assembler::adcl(Register dst, Address src) { | |
913 InstructionMark im(this); | |
304 | 914 prefix(src, dst); |
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915 emit_int8(0x13); |
0 | 916 emit_operand(dst, src); |
917 } | |
918 | |
919 void Assembler::adcl(Register dst, Register src) { | |
304 | 920 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
0 | 921 emit_arith(0x13, 0xC0, dst, src); |
922 } | |
923 | |
304 | 924 void Assembler::addl(Address dst, int32_t imm32) { |
925 InstructionMark im(this); | |
926 prefix(dst); | |
927 emit_arith_operand(0x81, rax, dst, imm32); | |
928 } | |
0 | 929 |
930 void Assembler::addl(Address dst, Register src) { | |
931 InstructionMark im(this); | |
304 | 932 prefix(dst, src); |
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933 emit_int8(0x01); |
0 | 934 emit_operand(src, dst); |
935 } | |
936 | |
304 | 937 void Assembler::addl(Register dst, int32_t imm32) { |
938 prefix(dst); | |
0 | 939 emit_arith(0x81, 0xC0, dst, imm32); |
940 } | |
941 | |
942 void Assembler::addl(Register dst, Address src) { | |
943 InstructionMark im(this); | |
304 | 944 prefix(src, dst); |
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945 emit_int8(0x03); |
0 | 946 emit_operand(dst, src); |
947 } | |
948 | |
949 void Assembler::addl(Register dst, Register src) { | |
304 | 950 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
0 | 951 emit_arith(0x03, 0xC0, dst, src); |
952 } | |
953 | |
954 void Assembler::addr_nop_4() { | |
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955 assert(UseAddressNop, "no CPU support"); |
0 | 956 // 4 bytes: NOP DWORD PTR [EAX+0] |
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957 emit_int8(0x0F); |
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958 emit_int8(0x1F); |
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959 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); |
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960 emit_int8(0); // 8-bits offset (1 byte) |
0 | 961 } |
962 | |
963 void Assembler::addr_nop_5() { | |
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964 assert(UseAddressNop, "no CPU support"); |
0 | 965 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset |
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966 emit_int8(0x0F); |
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967 emit_int8(0x1F); |
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968 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); |
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969 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); |
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970 emit_int8(0); // 8-bits offset (1 byte) |
0 | 971 } |
972 | |
973 void Assembler::addr_nop_7() { | |
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974 assert(UseAddressNop, "no CPU support"); |
0 | 975 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset |
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976 emit_int8(0x0F); |
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977 emit_int8(0x1F); |
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978 emit_int8((unsigned char)0x80); |
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979 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); |
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980 emit_int32(0); // 32-bits offset (4 bytes) |
0 | 981 } |
982 | |
983 void Assembler::addr_nop_8() { | |
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984 assert(UseAddressNop, "no CPU support"); |
0 | 985 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset |
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986 emit_int8(0x0F); |
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987 emit_int8(0x1F); |
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988 emit_int8((unsigned char)0x84); |
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989 // emit_rm(cbuf, 0x2, EAX_enc, 0x4); |
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990 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); |
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991 emit_int32(0); // 32-bits offset (4 bytes) |
0 | 992 } |
993 | |
304 | 994 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
995 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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996 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2); |
304 | 997 } |
998 | |
999 void Assembler::addsd(XMMRegister dst, Address src) { | |
1000 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1001 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2); |
304 | 1002 } |
1003 | |
1004 void Assembler::addss(XMMRegister dst, XMMRegister src) { | |
1005 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1006 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3); |
304 | 1007 } |
1008 | |
1009 void Assembler::addss(XMMRegister dst, Address src) { | |
1010 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1011 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3); |
304 | 1012 } |
1013 | |
6894 | 1014 void Assembler::aesdec(XMMRegister dst, Address src) { |
1015 assert(VM_Version::supports_aes(), ""); | |
1016 InstructionMark im(this); | |
1017 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1018 emit_int8((unsigned char)0xDE); |
6894 | 1019 emit_operand(dst, src); |
1020 } | |
1021 | |
1022 void Assembler::aesdec(XMMRegister dst, XMMRegister src) { | |
1023 assert(VM_Version::supports_aes(), ""); | |
1024 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1025 emit_int8((unsigned char)0xDE); |
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1026 emit_int8(0xC0 | encode); |
6894 | 1027 } |
1028 | |
1029 void Assembler::aesdeclast(XMMRegister dst, Address src) { | |
1030 assert(VM_Version::supports_aes(), ""); | |
1031 InstructionMark im(this); | |
1032 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1033 emit_int8((unsigned char)0xDF); |
6894 | 1034 emit_operand(dst, src); |
1035 } | |
1036 | |
1037 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) { | |
1038 assert(VM_Version::supports_aes(), ""); | |
1039 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1040 emit_int8((unsigned char)0xDF); |
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1041 emit_int8((unsigned char)(0xC0 | encode)); |
6894 | 1042 } |
1043 | |
1044 void Assembler::aesenc(XMMRegister dst, Address src) { | |
1045 assert(VM_Version::supports_aes(), ""); | |
1046 InstructionMark im(this); | |
1047 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1048 emit_int8((unsigned char)0xDC); |
6894 | 1049 emit_operand(dst, src); |
1050 } | |
1051 | |
1052 void Assembler::aesenc(XMMRegister dst, XMMRegister src) { | |
1053 assert(VM_Version::supports_aes(), ""); | |
1054 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1055 emit_int8((unsigned char)0xDC); |
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1056 emit_int8(0xC0 | encode); |
6894 | 1057 } |
1058 | |
1059 void Assembler::aesenclast(XMMRegister dst, Address src) { | |
1060 assert(VM_Version::supports_aes(), ""); | |
1061 InstructionMark im(this); | |
1062 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1063 emit_int8((unsigned char)0xDD); |
6894 | 1064 emit_operand(dst, src); |
1065 } | |
1066 | |
1067 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { | |
1068 assert(VM_Version::supports_aes(), ""); | |
1069 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1070 emit_int8((unsigned char)0xDD); |
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1071 emit_int8((unsigned char)(0xC0 | encode)); |
6894 | 1072 } |
1073 | |
1074 | |
4759 | 1075 void Assembler::andl(Address dst, int32_t imm32) { |
1076 InstructionMark im(this); | |
1077 prefix(dst); | |
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1078 emit_int8((unsigned char)0x81); |
4759 | 1079 emit_operand(rsp, dst, 4); |
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1080 emit_int32(imm32); |
4759 | 1081 } |
1082 | |
304 | 1083 void Assembler::andl(Register dst, int32_t imm32) { |
1084 prefix(dst); | |
1085 emit_arith(0x81, 0xE0, dst, imm32); | |
1086 } | |
1087 | |
1088 void Assembler::andl(Register dst, Address src) { | |
1089 InstructionMark im(this); | |
1090 prefix(src, dst); | |
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1091 emit_int8(0x23); |
304 | 1092 emit_operand(dst, src); |
1093 } | |
1094 | |
1095 void Assembler::andl(Register dst, Register src) { | |
1096 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
1097 emit_arith(0x23, 0xC0, dst, src); | |
1098 } | |
1099 | |
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1100 void Assembler::bsfl(Register dst, Register src) { |
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1101 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1102 emit_int8(0x0F); |
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1103 emit_int8((unsigned char)0xBC); |
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1104 emit_int8((unsigned char)(0xC0 | encode)); |
775
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1105 } |
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1106 |
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1107 void Assembler::bsrl(Register dst, Register src) { |
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1108 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
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1109 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1110 emit_int8(0x0F); |
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1111 emit_int8((unsigned char)0xBD); |
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1112 emit_int8((unsigned char)(0xC0 | encode)); |
775
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1113 } |
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1114 |
304 | 1115 void Assembler::bswapl(Register reg) { // bswap |
1116 int encode = prefix_and_encode(reg->encoding()); | |
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1117 emit_int8(0x0F); |
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1118 emit_int8((unsigned char)(0xC8 | encode)); |
304 | 1119 } |
1120 | |
1121 void Assembler::call(Label& L, relocInfo::relocType rtype) { | |
1122 // suspect disp32 is always good | |
1123 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); | |
1124 | |
1125 if (L.is_bound()) { | |
1126 const int long_size = 5; | |
1127 int offs = (int)( target(L) - pc() ); | |
1128 assert(offs <= 0, "assembler error"); | |
1129 InstructionMark im(this); | |
1130 // 1110 1000 #32-bit disp | |
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1131 emit_int8((unsigned char)0xE8); |
304 | 1132 emit_data(offs - long_size, rtype, operand); |
1133 } else { | |
1134 InstructionMark im(this); | |
1135 // 1110 1000 #32-bit disp | |
1136 L.add_patch_at(code(), locator()); | |
1137 | |
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1138 emit_int8((unsigned char)0xE8); |
304 | 1139 emit_data(int(0), rtype, operand); |
1140 } | |
1141 } | |
1142 | |
1143 void Assembler::call(Register dst) { | |
4759 | 1144 int encode = prefix_and_encode(dst->encoding()); |
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1145 emit_int8((unsigned char)0xFF); |
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1146 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 1147 } |
1148 | |
1149 | |
1150 void Assembler::call(Address adr) { | |
1151 InstructionMark im(this); | |
1152 prefix(adr); | |
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1153 emit_int8((unsigned char)0xFF); |
304 | 1154 emit_operand(rdx, adr); |
1155 } | |
1156 | |
1157 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { | |
1158 assert(entry != NULL, "call most probably wrong"); | |
1159 InstructionMark im(this); | |
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1160 emit_int8((unsigned char)0xE8); |
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1161 intptr_t disp = entry - (pc() + sizeof(int32_t)); |
304 | 1162 assert(is_simm32(disp), "must be 32bit offset (call2)"); |
1163 // Technically, should use call32_operand, but this format is | |
1164 // implied by the fact that we're emitting a call instruction. | |
1165 | |
1166 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); | |
1167 emit_data((int) disp, rspec, operand); | |
1168 } | |
1169 | |
1170 void Assembler::cdql() { | |
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1171 emit_int8((unsigned char)0x99); |
304 | 1172 } |
1173 | |
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1174 void Assembler::cld() { |
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1175 emit_int8((unsigned char)0xFC); |
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1176 } |
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1177 |
304 | 1178 void Assembler::cmovl(Condition cc, Register dst, Register src) { |
1179 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
1180 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1181 emit_int8(0x0F); |
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1182 emit_int8(0x40 | cc); |
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1183 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1184 } |
1185 | |
1186 | |
1187 void Assembler::cmovl(Condition cc, Register dst, Address src) { | |
1188 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
1189 prefix(src, dst); | |
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1190 emit_int8(0x0F); |
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1191 emit_int8(0x40 | cc); |
304 | 1192 emit_operand(dst, src); |
1193 } | |
1194 | |
1195 void Assembler::cmpb(Address dst, int imm8) { | |
1196 InstructionMark im(this); | |
1197 prefix(dst); | |
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1198 emit_int8((unsigned char)0x80); |
304 | 1199 emit_operand(rdi, dst, 1); |
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1200 emit_int8(imm8); |
304 | 1201 } |
1202 | |
1203 void Assembler::cmpl(Address dst, int32_t imm32) { | |
1204 InstructionMark im(this); | |
1205 prefix(dst); | |
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1206 emit_int8((unsigned char)0x81); |
304 | 1207 emit_operand(rdi, dst, 4); |
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1208 emit_int32(imm32); |
304 | 1209 } |
1210 | |
1211 void Assembler::cmpl(Register dst, int32_t imm32) { | |
1212 prefix(dst); | |
1213 emit_arith(0x81, 0xF8, dst, imm32); | |
1214 } | |
1215 | |
1216 void Assembler::cmpl(Register dst, Register src) { | |
1217 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
1218 emit_arith(0x3B, 0xC0, dst, src); | |
1219 } | |
1220 | |
1221 | |
1222 void Assembler::cmpl(Register dst, Address src) { | |
1223 InstructionMark im(this); | |
1224 prefix(src, dst); | |
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1225 emit_int8((unsigned char)0x3B); |
304 | 1226 emit_operand(dst, src); |
1227 } | |
1228 | |
1229 void Assembler::cmpw(Address dst, int imm16) { | |
1230 InstructionMark im(this); | |
1231 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); | |
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1232 emit_int8(0x66); |
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1233 emit_int8((unsigned char)0x81); |
304 | 1234 emit_operand(rdi, dst, 2); |
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1235 emit_int16(imm16); |
304 | 1236 } |
1237 | |
1238 // The 32-bit cmpxchg compares the value at adr with the contents of rax, | |
1239 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | |
1240 // The ZF is set if the compared values were equal, and cleared otherwise. | |
1241 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg | |
6834 | 1242 InstructionMark im(this); |
1243 prefix(adr, reg); | |
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1244 emit_int8(0x0F); |
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1245 emit_int8((unsigned char)0xB1); |
6834 | 1246 emit_operand(reg, adr); |
304 | 1247 } |
1248 | |
1249 void Assembler::comisd(XMMRegister dst, Address src) { | |
1250 // NOTE: dbx seems to decode this as comiss even though the | |
1251 // 0x66 is there. Strangly ucomisd comes out correct | |
1252 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1253 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66); |
4759 | 1254 } |
1255 | |
1256 void Assembler::comisd(XMMRegister dst, XMMRegister src) { | |
1257 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1258 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66); |
304 | 1259 } |
1260 | |
1261 void Assembler::comiss(XMMRegister dst, Address src) { | |
1262 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1263 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE); |
304 | 1264 } |
1265 | |
4759 | 1266 void Assembler::comiss(XMMRegister dst, XMMRegister src) { |
1267 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1268 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE); |
4759 | 1269 } |
1270 | |
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1271 void Assembler::cpuid() { |
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1272 emit_int8(0x0F); |
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1273 emit_int8((unsigned char)0xA2); |
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1274 } |
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1275 |
304 | 1276 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { |
1277 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1278 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3); |
304 | 1279 } |
1280 | |
1281 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | |
1282 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1283 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE); |
304 | 1284 } |
1285 | |
1286 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | |
1287 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1288 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2); |
304 | 1289 } |
1290 | |
4759 | 1291 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { |
1292 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1293 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2); |
4759 | 1294 } |
1295 | |
304 | 1296 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { |
1297 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 1298 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
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1299 emit_int8(0x2A); |
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1300 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1301 } |
1302 | |
4759 | 1303 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { |
1304 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1305 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2); |
4759 | 1306 } |
1307 | |
304 | 1308 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { |
1309 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4759 | 1310 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
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1311 emit_int8(0x2A); |
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1312 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1313 } |
1314 | |
4759 | 1315 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { |
1316 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1317 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3); |
4759 | 1318 } |
1319 | |
304 | 1320 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { |
1321 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1322 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3); |
304 | 1323 } |
1324 | |
4759 | 1325 void Assembler::cvtss2sd(XMMRegister dst, Address src) { |
1326 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1327 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3); |
4759 | 1328 } |
1329 | |
1330 | |
304 | 1331 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { |
1332 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 1333 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); |
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1334 emit_int8(0x2C); |
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1335 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1336 } |
1337 | |
1338 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | |
1339 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4759 | 1340 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
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1341 emit_int8(0x2C); |
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1342 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1343 } |
1344 | |
1345 void Assembler::decl(Address dst) { | |
1346 // Don't use it directly. Use MacroAssembler::decrement() instead. | |
1347 InstructionMark im(this); | |
1348 prefix(dst); | |
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1349 emit_int8((unsigned char)0xFF); |
304 | 1350 emit_operand(rcx, dst); |
1351 } | |
1352 | |
1353 void Assembler::divsd(XMMRegister dst, Address src) { | |
1354 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1355 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2); |
304 | 1356 } |
1357 | |
1358 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | |
1359 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1360 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2); |
304 | 1361 } |
1362 | |
1363 void Assembler::divss(XMMRegister dst, Address src) { | |
1364 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1365 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); |
304 | 1366 } |
1367 | |
1368 void Assembler::divss(XMMRegister dst, XMMRegister src) { | |
1369 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1370 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); |
304 | 1371 } |
1372 | |
1373 void Assembler::emms() { | |
1374 NOT_LP64(assert(VM_Version::supports_mmx(), "")); | |
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1375 emit_int8(0x0F); |
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1376 emit_int8(0x77); |
304 | 1377 } |
1378 | |
1379 void Assembler::hlt() { | |
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1380 emit_int8((unsigned char)0xF4); |
304 | 1381 } |
1382 | |
1383 void Assembler::idivl(Register src) { | |
1384 int encode = prefix_and_encode(src->encoding()); | |
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1385 emit_int8((unsigned char)0xF7); |
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1386 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 1387 } |
1388 | |
1920 | 1389 void Assembler::divl(Register src) { // Unsigned |
1390 int encode = prefix_and_encode(src->encoding()); | |
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1391 emit_int8((unsigned char)0xF7); |
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1392 emit_int8((unsigned char)(0xF0 | encode)); |
1920 | 1393 } |
1394 | |
304 | 1395 void Assembler::imull(Register dst, Register src) { |
1396 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1397 emit_int8(0x0F); |
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1398 emit_int8((unsigned char)0xAF); |
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1399 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1400 } |
1401 | |
1402 | |
1403 void Assembler::imull(Register dst, Register src, int value) { | |
1404 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1405 if (is8bit(value)) { | |
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1406 emit_int8(0x6B); |
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1407 emit_int8((unsigned char)(0xC0 | encode)); |
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1408 emit_int8(value & 0xFF); |
304 | 1409 } else { |
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1410 emit_int8(0x69); |
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1411 emit_int8((unsigned char)(0xC0 | encode)); |
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1412 emit_int32(value); |
304 | 1413 } |
1414 } | |
1415 | |
1416 void Assembler::incl(Address dst) { | |
1417 // Don't use it directly. Use MacroAssembler::increment() instead. | |
1418 InstructionMark im(this); | |
1419 prefix(dst); | |
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1420 emit_int8((unsigned char)0xFF); |
304 | 1421 emit_operand(rax, dst); |
1422 } | |
1423 | |
3851 | 1424 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { |
1425 InstructionMark im(this); | |
304 | 1426 assert((0 <= cc) && (cc < 16), "illegal cc"); |
1427 if (L.is_bound()) { | |
1428 address dst = target(L); | |
1429 assert(dst != NULL, "jcc most probably wrong"); | |
1430 | |
1431 const int short_size = 2; | |
1432 const int long_size = 6; | |
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1433 intptr_t offs = (intptr_t)dst - (intptr_t)pc(); |
3851 | 1434 if (maybe_short && is8bit(offs - short_size)) { |
304 | 1435 // 0111 tttn #8-bit disp |
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1436 emit_int8(0x70 | cc); |
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1437 emit_int8((offs - short_size) & 0xFF); |
304 | 1438 } else { |
1439 // 0000 1111 1000 tttn #32-bit disp | |
1440 assert(is_simm32(offs - long_size), | |
1441 "must be 32bit offset (call4)"); | |
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1442 emit_int8(0x0F); |
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1443 emit_int8((unsigned char)(0x80 | cc)); |
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1444 emit_int32(offs - long_size); |
304 | 1445 } |
1446 } else { | |
1447 // Note: could eliminate cond. jumps to this jump if condition | |
1448 // is the same however, seems to be rather unlikely case. | |
1449 // Note: use jccb() if label to be bound is very close to get | |
1450 // an 8-bit displacement | |
1451 L.add_patch_at(code(), locator()); | |
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1452 emit_int8(0x0F); |
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1453 emit_int8((unsigned char)(0x80 | cc)); |
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1454 emit_int32(0); |
304 | 1455 } |
1456 } | |
1457 | |
1458 void Assembler::jccb(Condition cc, Label& L) { | |
1459 if (L.is_bound()) { | |
1460 const int short_size = 2; | |
1461 address entry = target(L); | |
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1462 #ifdef ASSERT |
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1463 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); |
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1464 intptr_t delta = short_branch_delta(); |
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1465 if (delta != 0) { |
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1466 dist += (dist < 0 ? (-delta) :delta); |
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1467 } |
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1468 assert(is8bit(dist), "Dispacement too large for a short jmp"); |
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1469 #endif |
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1470 intptr_t offs = (intptr_t)entry - (intptr_t)pc(); |
304 | 1471 // 0111 tttn #8-bit disp |
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1472 emit_int8(0x70 | cc); |
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1473 emit_int8((offs - short_size) & 0xFF); |
304 | 1474 } else { |
1475 InstructionMark im(this); | |
1476 L.add_patch_at(code(), locator()); | |
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1477 emit_int8(0x70 | cc); |
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1478 emit_int8(0); |
304 | 1479 } |
1480 } | |
1481 | |
1482 void Assembler::jmp(Address adr) { | |
1483 InstructionMark im(this); | |
1484 prefix(adr); | |
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1485 emit_int8((unsigned char)0xFF); |
304 | 1486 emit_operand(rsp, adr); |
1487 } | |
1488 | |
3851 | 1489 void Assembler::jmp(Label& L, bool maybe_short) { |
304 | 1490 if (L.is_bound()) { |
1491 address entry = target(L); | |
1492 assert(entry != NULL, "jmp most probably wrong"); | |
1493 InstructionMark im(this); | |
1494 const int short_size = 2; | |
1495 const int long_size = 5; | |
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1496 intptr_t offs = entry - pc(); |
3851 | 1497 if (maybe_short && is8bit(offs - short_size)) { |
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1498 emit_int8((unsigned char)0xEB); |
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1499 emit_int8((offs - short_size) & 0xFF); |
304 | 1500 } else { |
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1501 emit_int8((unsigned char)0xE9); |
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1502 emit_int32(offs - long_size); |
304 | 1503 } |
1504 } else { | |
1505 // By default, forward jumps are always 32-bit displacements, since | |
1506 // we can't yet know where the label will be bound. If you're sure that | |
1507 // the forward jump will not run beyond 256 bytes, use jmpb to | |
1508 // force an 8-bit displacement. | |
1509 InstructionMark im(this); | |
1510 L.add_patch_at(code(), locator()); | |
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1511 emit_int8((unsigned char)0xE9); |
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1512 emit_int32(0); |
304 | 1513 } |
1514 } | |
1515 | |
1516 void Assembler::jmp(Register entry) { | |
1517 int encode = prefix_and_encode(entry->encoding()); | |
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1518 emit_int8((unsigned char)0xFF); |
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1519 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 1520 } |
1521 | |
1522 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { | |
1523 InstructionMark im(this); | |
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1524 emit_int8((unsigned char)0xE9); |
304 | 1525 assert(dest != NULL, "must have a target"); |
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1526 intptr_t disp = dest - (pc() + sizeof(int32_t)); |
304 | 1527 assert(is_simm32(disp), "must be 32bit offset (jmp)"); |
1528 emit_data(disp, rspec.reloc(), call32_operand); | |
1529 } | |
1530 | |
1531 void Assembler::jmpb(Label& L) { | |
1532 if (L.is_bound()) { | |
1533 const int short_size = 2; | |
1534 address entry = target(L); | |
1535 assert(entry != NULL, "jmp most probably wrong"); | |
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1536 #ifdef ASSERT |
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1537 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); |
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1538 intptr_t delta = short_branch_delta(); |
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1539 if (delta != 0) { |
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1540 dist += (dist < 0 ? (-delta) :delta); |
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1541 } |
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1542 assert(is8bit(dist), "Dispacement too large for a short jmp"); |
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1543 #endif |
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1544 intptr_t offs = entry - pc(); |
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1545 emit_int8((unsigned char)0xEB); |
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1546 emit_int8((offs - short_size) & 0xFF); |
304 | 1547 } else { |
1548 InstructionMark im(this); | |
1549 L.add_patch_at(code(), locator()); | |
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1550 emit_int8((unsigned char)0xEB); |
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1551 emit_int8(0); |
304 | 1552 } |
1553 } | |
1554 | |
1555 void Assembler::ldmxcsr( Address src) { | |
1556 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1557 InstructionMark im(this); | |
1558 prefix(src); | |
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1559 emit_int8(0x0F); |
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1560 emit_int8((unsigned char)0xAE); |
304 | 1561 emit_operand(as_Register(2), src); |
1562 } | |
1563 | |
1564 void Assembler::leal(Register dst, Address src) { | |
1565 InstructionMark im(this); | |
1566 #ifdef _LP64 | |
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1567 emit_int8(0x67); // addr32 |
304 | 1568 prefix(src, dst); |
1569 #endif // LP64 | |
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1570 emit_int8((unsigned char)0x8D); |
304 | 1571 emit_operand(dst, src); |
1572 } | |
1573 | |
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1574 void Assembler::lfence() { |
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1575 emit_int8(0x0F); |
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1576 emit_int8((unsigned char)0xAE); |
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1577 emit_int8((unsigned char)0xE8); |
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1578 } |
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1579 |
304 | 1580 void Assembler::lock() { |
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1581 emit_int8((unsigned char)0xF0); |
304 | 1582 } |
1583 | |
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1584 void Assembler::lzcntl(Register dst, Register src) { |
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1585 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
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1586 emit_int8((unsigned char)0xF3); |
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1587 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1588 emit_int8(0x0F); |
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1589 emit_int8((unsigned char)0xBD); |
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1590 emit_int8((unsigned char)(0xC0 | encode)); |
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1591 } |
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1592 |
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1593 // Emit mfence instruction |
304 | 1594 void Assembler::mfence() { |
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1595 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
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1596 emit_int8(0x0F); |
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1597 emit_int8((unsigned char)0xAE); |
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1598 emit_int8((unsigned char)0xF0); |
304 | 1599 } |
1600 | |
1601 void Assembler::mov(Register dst, Register src) { | |
1602 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
1603 } | |
1604 | |
1605 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | |
1606 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1607 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66); |
304 | 1608 } |
1609 | |
1610 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | |
1611 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1612 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE); |
304 | 1613 } |
1614 | |
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1615 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { |
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1616 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
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1617 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE); |
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1618 emit_int8(0x16); |
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1619 emit_int8((unsigned char)(0xC0 | encode)); |
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1620 } |
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1621 |
304 | 1622 void Assembler::movb(Register dst, Address src) { |
1623 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
1624 InstructionMark im(this); | |
1625 prefix(src, dst, true); | |
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1626 emit_int8((unsigned char)0x8A); |
304 | 1627 emit_operand(dst, src); |
1628 } | |
1629 | |
1630 | |
1631 void Assembler::movb(Address dst, int imm8) { | |
1632 InstructionMark im(this); | |
1633 prefix(dst); | |
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1634 emit_int8((unsigned char)0xC6); |
304 | 1635 emit_operand(rax, dst, 1); |
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1636 emit_int8(imm8); |
304 | 1637 } |
1638 | |
1639 | |
1640 void Assembler::movb(Address dst, Register src) { | |
1641 assert(src->has_byte_register(), "must have byte register"); | |
1642 InstructionMark im(this); | |
1643 prefix(dst, src, true); | |
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1644 emit_int8((unsigned char)0x88); |
304 | 1645 emit_operand(src, dst); |
1646 } | |
1647 | |
1648 void Assembler::movdl(XMMRegister dst, Register src) { | |
1649 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 1650 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
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1651 emit_int8(0x6E); |
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1652 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1653 } |
1654 | |
1655 void Assembler::movdl(Register dst, XMMRegister src) { | |
1656 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1657 // swap src/dst to get correct prefix | |
4759 | 1658 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66); |
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1659 emit_int8(0x7E); |
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1660 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1661 } |
1662 | |
2320
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1663 void Assembler::movdl(XMMRegister dst, Address src) { |
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1664 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
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1665 InstructionMark im(this); |
4759 | 1666 simd_prefix(dst, src, VEX_SIMD_66); |
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1667 emit_int8(0x6E); |
2320
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1668 emit_operand(dst, src); |
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1669 } |
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1670 |
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1671 void Assembler::movdl(Address dst, XMMRegister src) { |
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1672 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
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1673 InstructionMark im(this); |
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1674 simd_prefix(dst, src, VEX_SIMD_66); |
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1675 emit_int8(0x7E); |
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|
1676 emit_operand(src, dst); |
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1677 } |
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1678 |
304 | 1679 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { |
1680 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1681 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66); |
304 | 1682 } |
1683 | |
405 | 1684 void Assembler::movdqu(XMMRegister dst, Address src) { |
1685 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1686 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3); |
405 | 1687 } |
1688 | |
1689 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |
1690 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1691 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3); |
405 | 1692 } |
1693 | |
1694 void Assembler::movdqu(Address dst, XMMRegister src) { | |
1695 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1696 InstructionMark im(this); | |
4759 | 1697 simd_prefix(dst, src, VEX_SIMD_F3); |
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1698 emit_int8(0x7F); |
405 | 1699 emit_operand(src, dst); |
1700 } | |
1701 | |
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1702 // Move Unaligned 256bit Vector |
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1703 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) { |
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1704 assert(UseAVX, ""); |
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|
1705 bool vector256 = true; |
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1706 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256); |
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1707 emit_int8(0x6F); |
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1708 emit_int8((unsigned char)(0xC0 | encode)); |
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1709 } |
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|
1710 |
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1711 void Assembler::vmovdqu(XMMRegister dst, Address src) { |
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1712 assert(UseAVX, ""); |
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|
1713 InstructionMark im(this); |
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1714 bool vector256 = true; |
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1715 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256); |
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1716 emit_int8(0x6F); |
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1717 emit_operand(dst, src); |
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1718 } |
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1719 |
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1720 void Assembler::vmovdqu(Address dst, XMMRegister src) { |
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1721 assert(UseAVX, ""); |
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1722 InstructionMark im(this); |
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1723 bool vector256 = true; |
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1724 // swap src<->dst for encoding |
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1725 assert(src != xnoreg, "sanity"); |
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1726 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256); |
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1727 emit_int8(0x7F); |
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1728 emit_operand(src, dst); |
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1729 } |
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1730 |
304 | 1731 // Uses zero extension on 64bit |
1732 | |
1733 void Assembler::movl(Register dst, int32_t imm32) { | |
1734 int encode = prefix_and_encode(dst->encoding()); | |
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1735 emit_int8((unsigned char)(0xB8 | encode)); |
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1736 emit_int32(imm32); |
304 | 1737 } |
1738 | |
1739 void Assembler::movl(Register dst, Register src) { | |
1740 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1741 emit_int8((unsigned char)0x8B); |
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1742 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1743 } |
1744 | |
1745 void Assembler::movl(Register dst, Address src) { | |
1746 InstructionMark im(this); | |
1747 prefix(src, dst); | |
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1748 emit_int8((unsigned char)0x8B); |
304 | 1749 emit_operand(dst, src); |
1750 } | |
1751 | |
1752 void Assembler::movl(Address dst, int32_t imm32) { | |
1753 InstructionMark im(this); | |
1754 prefix(dst); | |
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1755 emit_int8((unsigned char)0xC7); |
304 | 1756 emit_operand(rax, dst, 4); |
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1757 emit_int32(imm32); |
304 | 1758 } |
1759 | |
1760 void Assembler::movl(Address dst, Register src) { | |
1761 InstructionMark im(this); | |
1762 prefix(dst, src); | |
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1763 emit_int8((unsigned char)0x89); |
304 | 1764 emit_operand(src, dst); |
1765 } | |
1766 | |
1767 // New cpus require to use movsd and movss to avoid partial register stall | |
1768 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
1769 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
1770 void Assembler::movlpd(XMMRegister dst, Address src) { | |
1771 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1772 emit_simd_arith(0x12, dst, src, VEX_SIMD_66); |
304 | 1773 } |
1774 | |
1775 void Assembler::movq( MMXRegister dst, Address src ) { | |
1776 assert( VM_Version::supports_mmx(), "" ); | |
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1777 emit_int8(0x0F); |
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1778 emit_int8(0x6F); |
304 | 1779 emit_operand(dst, src); |
1780 } | |
1781 | |
1782 void Assembler::movq( Address dst, MMXRegister src ) { | |
1783 assert( VM_Version::supports_mmx(), "" ); | |
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1784 emit_int8(0x0F); |
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1785 emit_int8(0x7F); |
304 | 1786 // workaround gcc (3.2.1-7a) bug |
1787 // In that version of gcc with only an emit_operand(MMX, Address) | |
1788 // gcc will tail jump and try and reverse the parameters completely | |
1789 // obliterating dst in the process. By having a version available | |
1790 // that doesn't need to swap the args at the tail jump the bug is | |
1791 // avoided. | |
1792 emit_operand(dst, src); | |
1793 } | |
1794 | |
1795 void Assembler::movq(XMMRegister dst, Address src) { | |
1796 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1797 InstructionMark im(this); | |
4759 | 1798 simd_prefix(dst, src, VEX_SIMD_F3); |
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1799 emit_int8(0x7E); |
304 | 1800 emit_operand(dst, src); |
1801 } | |
1802 | |
1803 void Assembler::movq(Address dst, XMMRegister src) { | |
1804 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1805 InstructionMark im(this); | |
4759 | 1806 simd_prefix(dst, src, VEX_SIMD_66); |
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1807 emit_int8((unsigned char)0xD6); |
304 | 1808 emit_operand(src, dst); |
1809 } | |
1810 | |
1811 void Assembler::movsbl(Register dst, Address src) { // movsxb | |
1812 InstructionMark im(this); | |
1813 prefix(src, dst); | |
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1814 emit_int8(0x0F); |
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1815 emit_int8((unsigned char)0xBE); |
304 | 1816 emit_operand(dst, src); |
1817 } | |
1818 | |
1819 void Assembler::movsbl(Register dst, Register src) { // movsxb | |
1820 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
1821 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
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1822 emit_int8(0x0F); |
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1823 emit_int8((unsigned char)0xBE); |
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1824 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1825 } |
1826 | |
1827 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | |
1828 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1829 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2); |
304 | 1830 } |
1831 | |
1832 void Assembler::movsd(XMMRegister dst, Address src) { | |
1833 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1834 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2); |
304 | 1835 } |
1836 | |
1837 void Assembler::movsd(Address dst, XMMRegister src) { | |
1838 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1839 InstructionMark im(this); | |
4759 | 1840 simd_prefix(dst, src, VEX_SIMD_F2); |
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1841 emit_int8(0x11); |
304 | 1842 emit_operand(src, dst); |
1843 } | |
1844 | |
1845 void Assembler::movss(XMMRegister dst, XMMRegister src) { | |
1846 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1847 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3); |
304 | 1848 } |
1849 | |
1850 void Assembler::movss(XMMRegister dst, Address src) { | |
1851 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1852 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3); |
304 | 1853 } |
1854 | |
1855 void Assembler::movss(Address dst, XMMRegister src) { | |
1856 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1857 InstructionMark im(this); | |
4759 | 1858 simd_prefix(dst, src, VEX_SIMD_F3); |
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1859 emit_int8(0x11); |
304 | 1860 emit_operand(src, dst); |
1861 } | |
1862 | |
1863 void Assembler::movswl(Register dst, Address src) { // movsxw | |
1864 InstructionMark im(this); | |
1865 prefix(src, dst); | |
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1866 emit_int8(0x0F); |
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1867 emit_int8((unsigned char)0xBF); |
304 | 1868 emit_operand(dst, src); |
1869 } | |
1870 | |
1871 void Assembler::movswl(Register dst, Register src) { // movsxw | |
1872 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1873 emit_int8(0x0F); |
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1874 emit_int8((unsigned char)0xBF); |
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1875 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1876 } |
1877 | |
1878 void Assembler::movw(Address dst, int imm16) { | |
1879 InstructionMark im(this); | |
1880 | |
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1881 emit_int8(0x66); // switch to 16-bit mode |
304 | 1882 prefix(dst); |
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1883 emit_int8((unsigned char)0xC7); |
304 | 1884 emit_operand(rax, dst, 2); |
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1885 emit_int16(imm16); |
304 | 1886 } |
1887 | |
1888 void Assembler::movw(Register dst, Address src) { | |
1889 InstructionMark im(this); | |
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1890 emit_int8(0x66); |
304 | 1891 prefix(src, dst); |
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1892 emit_int8((unsigned char)0x8B); |
304 | 1893 emit_operand(dst, src); |
1894 } | |
1895 | |
1896 void Assembler::movw(Address dst, Register src) { | |
1897 InstructionMark im(this); | |
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1898 emit_int8(0x66); |
304 | 1899 prefix(dst, src); |
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1900 emit_int8((unsigned char)0x89); |
304 | 1901 emit_operand(src, dst); |
1902 } | |
1903 | |
1904 void Assembler::movzbl(Register dst, Address src) { // movzxb | |
1905 InstructionMark im(this); | |
1906 prefix(src, dst); | |
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1907 emit_int8(0x0F); |
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1908 emit_int8((unsigned char)0xB6); |
304 | 1909 emit_operand(dst, src); |
1910 } | |
1911 | |
1912 void Assembler::movzbl(Register dst, Register src) { // movzxb | |
1913 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
1914 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
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1915 emit_int8(0x0F); |
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1916 emit_int8((unsigned char)0xB6); |
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1917 emit_int8(0xC0 | encode); |
304 | 1918 } |
1919 | |
1920 void Assembler::movzwl(Register dst, Address src) { // movzxw | |
1921 InstructionMark im(this); | |
1922 prefix(src, dst); | |
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1923 emit_int8(0x0F); |
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1924 emit_int8((unsigned char)0xB7); |
304 | 1925 emit_operand(dst, src); |
1926 } | |
1927 | |
1928 void Assembler::movzwl(Register dst, Register src) { // movzxw | |
1929 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1930 emit_int8(0x0F); |
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1931 emit_int8((unsigned char)0xB7); |
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1932 emit_int8(0xC0 | encode); |
304 | 1933 } |
1934 | |
1935 void Assembler::mull(Address src) { | |
1936 InstructionMark im(this); | |
1937 prefix(src); | |
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1938 emit_int8((unsigned char)0xF7); |
304 | 1939 emit_operand(rsp, src); |
1940 } | |
1941 | |
1942 void Assembler::mull(Register src) { | |
1943 int encode = prefix_and_encode(src->encoding()); | |
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1944 emit_int8((unsigned char)0xF7); |
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1945 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 1946 } |
1947 | |
1948 void Assembler::mulsd(XMMRegister dst, Address src) { | |
1949 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1950 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); |
304 | 1951 } |
1952 | |
1953 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | |
1954 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1955 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); |
304 | 1956 } |
1957 | |
1958 void Assembler::mulss(XMMRegister dst, Address src) { | |
1959 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1960 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); |
304 | 1961 } |
1962 | |
1963 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | |
1964 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1965 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); |
304 | 1966 } |
1967 | |
1968 void Assembler::negl(Register dst) { | |
1969 int encode = prefix_and_encode(dst->encoding()); | |
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1970 emit_int8((unsigned char)0xF7); |
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1971 emit_int8((unsigned char)(0xD8 | encode)); |
304 | 1972 } |
1973 | |
0 | 1974 void Assembler::nop(int i) { |
304 | 1975 #ifdef ASSERT |
0 | 1976 assert(i > 0, " "); |
304 | 1977 // The fancy nops aren't currently recognized by debuggers making it a |
1978 // pain to disassemble code while debugging. If asserts are on clearly | |
1979 // speed is not an issue so simply use the single byte traditional nop | |
1980 // to do alignment. | |
1981 | |
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1982 for (; i > 0 ; i--) emit_int8((unsigned char)0x90); |
304 | 1983 return; |
1984 | |
1985 #endif // ASSERT | |
1986 | |
0 | 1987 if (UseAddressNop && VM_Version::is_intel()) { |
1988 // | |
1989 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel | |
1990 // 1: 0x90 | |
1991 // 2: 0x66 0x90 | |
1992 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
1993 // 4: 0x0F 0x1F 0x40 0x00 | |
1994 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
1995 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
1996 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
1997 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1998 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1999 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2000 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2001 | |
2002 // The rest coding is Intel specific - don't use consecutive address nops | |
2003 | |
2004 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
2005 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
2006 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
2007 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
2008 | |
2009 while(i >= 15) { | |
2010 // For Intel don't generate consecutive addess nops (mix with regular nops) | |
2011 i -= 15; | |
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2012 emit_int8(0x66); // size prefix |
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2013 emit_int8(0x66); // size prefix |
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2014 emit_int8(0x66); // size prefix |
0 | 2015 addr_nop_8(); |
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2016 emit_int8(0x66); // size prefix |
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2017 emit_int8(0x66); // size prefix |
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2018 emit_int8(0x66); // size prefix |
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2019 emit_int8((unsigned char)0x90); |
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2020 // nop |
0 | 2021 } |
2022 switch (i) { | |
2023 case 14: | |
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2024 emit_int8(0x66); // size prefix |
0 | 2025 case 13: |
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2026 emit_int8(0x66); // size prefix |
0 | 2027 case 12: |
2028 addr_nop_8(); | |
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2029 emit_int8(0x66); // size prefix |
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2030 emit_int8(0x66); // size prefix |
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2031 emit_int8(0x66); // size prefix |
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2032 emit_int8((unsigned char)0x90); |
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2033 // nop |
0 | 2034 break; |
2035 case 11: | |
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2036 emit_int8(0x66); // size prefix |
0 | 2037 case 10: |
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2038 emit_int8(0x66); // size prefix |
0 | 2039 case 9: |
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2040 emit_int8(0x66); // size prefix |
0 | 2041 case 8: |
2042 addr_nop_8(); | |
2043 break; | |
2044 case 7: | |
2045 addr_nop_7(); | |
2046 break; | |
2047 case 6: | |
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2048 emit_int8(0x66); // size prefix |
0 | 2049 case 5: |
2050 addr_nop_5(); | |
2051 break; | |
2052 case 4: | |
2053 addr_nop_4(); | |
2054 break; | |
2055 case 3: | |
2056 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
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2057 emit_int8(0x66); // size prefix |
0 | 2058 case 2: |
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2059 emit_int8(0x66); // size prefix |
0 | 2060 case 1: |
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2061 emit_int8((unsigned char)0x90); |
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2062 // nop |
0 | 2063 break; |
2064 default: | |
2065 assert(i == 0, " "); | |
2066 } | |
2067 return; | |
2068 } | |
2069 if (UseAddressNop && VM_Version::is_amd()) { | |
2070 // | |
2071 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. | |
2072 // 1: 0x90 | |
2073 // 2: 0x66 0x90 | |
2074 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
2075 // 4: 0x0F 0x1F 0x40 0x00 | |
2076 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
2077 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2078 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2079 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2080 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2081 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2082 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2083 | |
2084 // The rest coding is AMD specific - use consecutive address nops | |
2085 | |
2086 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2087 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2088 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2089 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2090 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2091 // Size prefixes (0x66) are added for larger sizes | |
2092 | |
2093 while(i >= 22) { | |
2094 i -= 11; | |
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2095 emit_int8(0x66); // size prefix |
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2096 emit_int8(0x66); // size prefix |
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2097 emit_int8(0x66); // size prefix |
0 | 2098 addr_nop_8(); |
2099 } | |
2100 // Generate first nop for size between 21-12 | |
2101 switch (i) { | |
2102 case 21: | |
2103 i -= 1; | |
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2104 emit_int8(0x66); // size prefix |
0 | 2105 case 20: |
2106 case 19: | |
2107 i -= 1; | |
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2108 emit_int8(0x66); // size prefix |
0 | 2109 case 18: |
2110 case 17: | |
2111 i -= 1; | |
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2112 emit_int8(0x66); // size prefix |
0 | 2113 case 16: |
2114 case 15: | |
2115 i -= 8; | |
2116 addr_nop_8(); | |
2117 break; | |
2118 case 14: | |
2119 case 13: | |
2120 i -= 7; | |
2121 addr_nop_7(); | |
2122 break; | |
2123 case 12: | |
2124 i -= 6; | |
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2125 emit_int8(0x66); // size prefix |
0 | 2126 addr_nop_5(); |
2127 break; | |
2128 default: | |
2129 assert(i < 12, " "); | |
2130 } | |
2131 | |
2132 // Generate second nop for size between 11-1 | |
2133 switch (i) { | |
2134 case 11: | |
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2135 emit_int8(0x66); // size prefix |
0 | 2136 case 10: |
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2137 emit_int8(0x66); // size prefix |
0 | 2138 case 9: |
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2139 emit_int8(0x66); // size prefix |
0 | 2140 case 8: |
2141 addr_nop_8(); | |
2142 break; | |
2143 case 7: | |
2144 addr_nop_7(); | |
2145 break; | |
2146 case 6: | |
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2147 emit_int8(0x66); // size prefix |
0 | 2148 case 5: |
2149 addr_nop_5(); | |
2150 break; | |
2151 case 4: | |
2152 addr_nop_4(); | |
2153 break; | |
2154 case 3: | |
2155 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
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2156 emit_int8(0x66); // size prefix |
0 | 2157 case 2: |
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2158 emit_int8(0x66); // size prefix |
0 | 2159 case 1: |
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2160 emit_int8((unsigned char)0x90); |
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2161 // nop |
0 | 2162 break; |
2163 default: | |
2164 assert(i == 0, " "); | |
2165 } | |
2166 return; | |
2167 } | |
2168 | |
2169 // Using nops with size prefixes "0x66 0x90". | |
2170 // From AMD Optimization Guide: | |
2171 // 1: 0x90 | |
2172 // 2: 0x66 0x90 | |
2173 // 3: 0x66 0x66 0x90 | |
2174 // 4: 0x66 0x66 0x66 0x90 | |
2175 // 5: 0x66 0x66 0x90 0x66 0x90 | |
2176 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 | |
2177 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 | |
2178 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 | |
2179 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
2180 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
2181 // | |
2182 while(i > 12) { | |
2183 i -= 4; | |
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2184 emit_int8(0x66); // size prefix |
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2185 emit_int8(0x66); |
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2186 emit_int8(0x66); |
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2187 emit_int8((unsigned char)0x90); |
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|
2188 // nop |
0 | 2189 } |
2190 // 1 - 12 nops | |
2191 if(i > 8) { | |
2192 if(i > 9) { | |
2193 i -= 1; | |
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2194 emit_int8(0x66); |
0 | 2195 } |
2196 i -= 3; | |
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2197 emit_int8(0x66); |
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2198 emit_int8(0x66); |
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2199 emit_int8((unsigned char)0x90); |
0 | 2200 } |
2201 // 1 - 8 nops | |
2202 if(i > 4) { | |
2203 if(i > 6) { | |
2204 i -= 1; | |
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2205 emit_int8(0x66); |
0 | 2206 } |
2207 i -= 3; | |
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2208 emit_int8(0x66); |
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|
2209 emit_int8(0x66); |
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2210 emit_int8((unsigned char)0x90); |
0 | 2211 } |
2212 switch (i) { | |
2213 case 4: | |
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2214 emit_int8(0x66); |
0 | 2215 case 3: |
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2216 emit_int8(0x66); |
0 | 2217 case 2: |
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2218 emit_int8(0x66); |
0 | 2219 case 1: |
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2220 emit_int8((unsigned char)0x90); |
0 | 2221 break; |
2222 default: | |
2223 assert(i == 0, " "); | |
2224 } | |
2225 } | |
2226 | |
304 | 2227 void Assembler::notl(Register dst) { |
2228 int encode = prefix_and_encode(dst->encoding()); | |
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2229 emit_int8((unsigned char)0xF7); |
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2230 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 2231 } |
2232 | |
2233 void Assembler::orl(Address dst, int32_t imm32) { | |
2234 InstructionMark im(this); | |
2235 prefix(dst); | |
2100
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2236 emit_arith_operand(0x81, rcx, dst, imm32); |
304 | 2237 } |
2238 | |
2239 void Assembler::orl(Register dst, int32_t imm32) { | |
2240 prefix(dst); | |
2241 emit_arith(0x81, 0xC8, dst, imm32); | |
2242 } | |
2243 | |
2244 void Assembler::orl(Register dst, Address src) { | |
2245 InstructionMark im(this); | |
2246 prefix(src, dst); | |
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2247 emit_int8(0x0B); |
304 | 2248 emit_operand(dst, src); |
2249 } | |
2250 | |
2251 void Assembler::orl(Register dst, Register src) { | |
2252 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2253 emit_arith(0x0B, 0xC0, dst, src); | |
2254 } | |
2255 | |
4759 | 2256 void Assembler::packuswb(XMMRegister dst, Address src) { |
2257 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2258 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
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2259 emit_simd_arith(0x67, dst, src, VEX_SIMD_66); |
4759 | 2260 } |
2261 | |
2262 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { | |
2263 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2264 emit_simd_arith(0x67, dst, src, VEX_SIMD_66); |
4759 | 2265 } |
2266 | |
681 | 2267 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
2268 assert(VM_Version::supports_sse4_2(), ""); | |
4759 | 2269 InstructionMark im(this); |
2270 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); | |
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2271 emit_int8(0x61); |
681 | 2272 emit_operand(dst, src); |
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2273 emit_int8(imm8); |
681 | 2274 } |
2275 | |
2276 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | |
2277 assert(VM_Version::supports_sse4_2(), ""); | |
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2278 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); |
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2279 emit_int8(0x61); |
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2280 emit_int8((unsigned char)(0xC0 | encode)); |
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2281 emit_int8(imm8); |
681 | 2282 } |
2283 | |
4759 | 2284 void Assembler::pmovzxbw(XMMRegister dst, Address src) { |
2285 assert(VM_Version::supports_sse4_1(), ""); | |
2286 InstructionMark im(this); | |
2287 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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2288 emit_int8(0x30); |
4759 | 2289 emit_operand(dst, src); |
2290 } | |
2291 | |
2292 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { | |
2293 assert(VM_Version::supports_sse4_1(), ""); | |
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2294 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
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2295 emit_int8(0x30); |
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2296 emit_int8((unsigned char)(0xC0 | encode)); |
4759 | 2297 } |
2298 | |
304 | 2299 // generic |
2300 void Assembler::pop(Register dst) { | |
2301 int encode = prefix_and_encode(dst->encoding()); | |
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2302 emit_int8(0x58 | encode); |
304 | 2303 } |
2304 | |
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2305 void Assembler::popcntl(Register dst, Address src) { |
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|
2306 assert(VM_Version::supports_popcnt(), "must support"); |
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|
2307 InstructionMark im(this); |
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2308 emit_int8((unsigned char)0xF3); |
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2309 prefix(src, dst); |
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2310 emit_int8(0x0F); |
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2311 emit_int8((unsigned char)0xB8); |
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2312 emit_operand(dst, src); |
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2313 } |
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2314 |
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2315 void Assembler::popcntl(Register dst, Register src) { |
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2316 assert(VM_Version::supports_popcnt(), "must support"); |
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2317 emit_int8((unsigned char)0xF3); |
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2318 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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2319 emit_int8(0x0F); |
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2320 emit_int8((unsigned char)0xB8); |
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2321 emit_int8((unsigned char)(0xC0 | encode)); |
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2322 } |
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2323 |
304 | 2324 void Assembler::popf() { |
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2325 emit_int8((unsigned char)0x9D); |
304 | 2326 } |
2327 | |
1060 | 2328 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 2329 void Assembler::popl(Address dst) { |
2330 // NOTE: this will adjust stack by 8byte on 64bits | |
2331 InstructionMark im(this); | |
2332 prefix(dst); | |
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2333 emit_int8((unsigned char)0x8F); |
304 | 2334 emit_operand(rax, dst); |
2335 } | |
1060 | 2336 #endif |
304 | 2337 |
2338 void Assembler::prefetch_prefix(Address src) { | |
2339 prefix(src); | |
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2340 emit_int8(0x0F); |
304 | 2341 } |
2342 | |
2343 void Assembler::prefetchnta(Address src) { | |
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2344 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); |
304 | 2345 InstructionMark im(this); |
2346 prefetch_prefix(src); | |
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2347 emit_int8(0x18); |
304 | 2348 emit_operand(rax, src); // 0, src |
2349 } | |
2350 | |
2351 void Assembler::prefetchr(Address src) { | |
3854 | 2352 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
304 | 2353 InstructionMark im(this); |
2354 prefetch_prefix(src); | |
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2355 emit_int8(0x0D); |
304 | 2356 emit_operand(rax, src); // 0, src |
2357 } | |
2358 | |
2359 void Assembler::prefetcht0(Address src) { | |
2360 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2361 InstructionMark im(this); | |
2362 prefetch_prefix(src); | |
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2363 emit_int8(0x18); |
304 | 2364 emit_operand(rcx, src); // 1, src |
2365 } | |
2366 | |
2367 void Assembler::prefetcht1(Address src) { | |
2368 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2369 InstructionMark im(this); | |
2370 prefetch_prefix(src); | |
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2371 emit_int8(0x18); |
304 | 2372 emit_operand(rdx, src); // 2, src |
2373 } | |
2374 | |
2375 void Assembler::prefetcht2(Address src) { | |
2376 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2377 InstructionMark im(this); | |
2378 prefetch_prefix(src); | |
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2379 emit_int8(0x18); |
304 | 2380 emit_operand(rbx, src); // 3, src |
2381 } | |
2382 | |
2383 void Assembler::prefetchw(Address src) { | |
3854 | 2384 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
304 | 2385 InstructionMark im(this); |
2386 prefetch_prefix(src); | |
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2387 emit_int8(0x0D); |
304 | 2388 emit_operand(rcx, src); // 1, src |
2389 } | |
2390 | |
2391 void Assembler::prefix(Prefix p) { | |
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2392 emit_int8(p); |
304 | 2393 } |
2394 | |
6894 | 2395 void Assembler::pshufb(XMMRegister dst, XMMRegister src) { |
2396 assert(VM_Version::supports_ssse3(), ""); | |
2397 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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2398 emit_int8(0x00); |
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2399 emit_int8((unsigned char)(0xC0 | encode)); |
6894 | 2400 } |
2401 | |
2402 void Assembler::pshufb(XMMRegister dst, Address src) { | |
2403 assert(VM_Version::supports_ssse3(), ""); | |
2404 InstructionMark im(this); | |
2405 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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2406 emit_int8(0x00); |
6894 | 2407 emit_operand(dst, src); |
2408 } | |
2409 | |
304 | 2410 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { |
2411 assert(isByte(mode), "invalid value"); | |
2412 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2413 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66); |
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2414 emit_int8(mode & 0xFF); |
304 | 2415 |
2416 } | |
2417 | |
2418 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | |
2419 assert(isByte(mode), "invalid value"); | |
2420 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 2421 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2422 InstructionMark im(this); | |
2423 simd_prefix(dst, src, VEX_SIMD_66); | |
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2424 emit_int8(0x70); |
304 | 2425 emit_operand(dst, src); |
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2426 emit_int8(mode & 0xFF); |
304 | 2427 } |
2428 | |
2429 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | |
2430 assert(isByte(mode), "invalid value"); | |
2431 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2432 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2); |
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2433 emit_int8(mode & 0xFF); |
304 | 2434 } |
2435 | |
2436 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | |
2437 assert(isByte(mode), "invalid value"); | |
2438 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 2439 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2440 InstructionMark im(this); | |
2441 simd_prefix(dst, src, VEX_SIMD_F2); | |
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2442 emit_int8(0x70); |
304 | 2443 emit_operand(dst, src); |
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2444 emit_int8(mode & 0xFF); |
304 | 2445 } |
2446 | |
2320
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2447 void Assembler::psrldq(XMMRegister dst, int shift) { |
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2448 // Shift 128 bit value in xmm register by number of bytes. |
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2449 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4759 | 2450 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66); |
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2451 emit_int8(0x73); |
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2452 emit_int8((unsigned char)(0xC0 | encode)); |
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2453 emit_int8(shift); |
2320
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2454 } |
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2455 |
681 | 2456 void Assembler::ptest(XMMRegister dst, Address src) { |
2457 assert(VM_Version::supports_sse4_1(), ""); | |
4759 | 2458 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2459 InstructionMark im(this); | |
2460 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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2461 emit_int8(0x17); |
681 | 2462 emit_operand(dst, src); |
2463 } | |
2464 | |
2465 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | |
2466 assert(VM_Version::supports_sse4_1(), ""); | |
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2467 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
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2468 emit_int8(0x17); |
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2469 emit_int8((unsigned char)(0xC0 | encode)); |
681 | 2470 } |
2471 | |
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2472 void Assembler::vptest(XMMRegister dst, Address src) { |
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2473 assert(VM_Version::supports_avx(), ""); |
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2474 InstructionMark im(this); |
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2475 bool vector256 = true; |
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2476 assert(dst != xnoreg, "sanity"); |
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2477 int dst_enc = dst->encoding(); |
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2478 // swap src<->dst for encoding |
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2479 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256); |
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2480 emit_int8(0x17); |
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2481 emit_operand(dst, src); |
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2482 } |
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2483 |
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2484 void Assembler::vptest(XMMRegister dst, XMMRegister src) { |
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2485 assert(VM_Version::supports_avx(), ""); |
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2486 bool vector256 = true; |
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2487 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
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2488 emit_int8(0x17); |
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2489 emit_int8((unsigned char)(0xC0 | encode)); |
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2490 } |
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2491 |
4759 | 2492 void Assembler::punpcklbw(XMMRegister dst, Address src) { |
2493 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2494 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
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2495 emit_simd_arith(0x60, dst, src, VEX_SIMD_66); |
4759 | 2496 } |
2497 | |
304 | 2498 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
2499 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2500 emit_simd_arith(0x60, dst, src, VEX_SIMD_66); |
304 | 2501 } |
2502 | |
4759 | 2503 void Assembler::punpckldq(XMMRegister dst, Address src) { |
2504 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2505 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
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2506 emit_simd_arith(0x62, dst, src, VEX_SIMD_66); |
4759 | 2507 } |
2508 | |
2509 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { | |
2510 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2511 emit_simd_arith(0x62, dst, src, VEX_SIMD_66); |
4759 | 2512 } |
2513 | |
6225 | 2514 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) { |
2515 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2516 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66); |
6225 | 2517 } |
2518 | |
304 | 2519 void Assembler::push(int32_t imm32) { |
2520 // in 64bits we push 64bits onto the stack but only | |
2521 // take a 32bit immediate | |
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2522 emit_int8(0x68); |
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2523 emit_int32(imm32); |
304 | 2524 } |
2525 | |
2526 void Assembler::push(Register src) { | |
2527 int encode = prefix_and_encode(src->encoding()); | |
2528 | |
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2529 emit_int8(0x50 | encode); |
304 | 2530 } |
2531 | |
2532 void Assembler::pushf() { | |
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|
2533 emit_int8((unsigned char)0x9C); |
304 | 2534 } |
2535 | |
1060 | 2536 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 2537 void Assembler::pushl(Address src) { |
2538 // Note this will push 64bit on 64bit | |
2539 InstructionMark im(this); | |
2540 prefix(src); | |
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2541 emit_int8((unsigned char)0xFF); |
304 | 2542 emit_operand(rsi, src); |
2543 } | |
1060 | 2544 #endif |
304 | 2545 |
2546 void Assembler::rcll(Register dst, int imm8) { | |
2547 assert(isShiftCount(imm8), "illegal shift count"); | |
2548 int encode = prefix_and_encode(dst->encoding()); | |
2549 if (imm8 == 1) { | |
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2550 emit_int8((unsigned char)0xD1); |
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2551 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 2552 } else { |
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|
2553 emit_int8((unsigned char)0xC1); |
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|
2554 emit_int8((unsigned char)0xD0 | encode); |
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|
2555 emit_int8(imm8); |
304 | 2556 } |
2557 } | |
2558 | |
2559 // copies data from [esi] to [edi] using rcx pointer sized words | |
2560 // generic | |
2561 void Assembler::rep_mov() { | |
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2562 emit_int8((unsigned char)0xF3); |
304 | 2563 // MOVSQ |
2564 LP64_ONLY(prefix(REX_W)); | |
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2565 emit_int8((unsigned char)0xA5); |
304 | 2566 } |
2567 | |
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2568 // sets rcx bytes with rax, value at [edi] |
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2569 void Assembler::rep_stosb() { |
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2570 emit_int8((unsigned char)0xF3); // REP |
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2571 LP64_ONLY(prefix(REX_W)); |
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2572 emit_int8((unsigned char)0xAA); // STOSB |
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2573 } |
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2574 |
304 | 2575 // sets rcx pointer sized words with rax, value at [edi] |
2576 // generic | |
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2577 void Assembler::rep_stos() { |
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2578 emit_int8((unsigned char)0xF3); // REP |
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2579 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD |
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2580 emit_int8((unsigned char)0xAB); |
304 | 2581 } |
2582 | |
2583 // scans rcx pointer sized words at [edi] for occurance of rax, | |
2584 // generic | |
2585 void Assembler::repne_scan() { // repne_scan | |
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|
2586 emit_int8((unsigned char)0xF2); |
304 | 2587 // SCASQ |
2588 LP64_ONLY(prefix(REX_W)); | |
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|
2589 emit_int8((unsigned char)0xAF); |
304 | 2590 } |
2591 | |
2592 #ifdef _LP64 | |
2593 // scans rcx 4 byte words at [edi] for occurance of rax, | |
2594 // generic | |
2595 void Assembler::repne_scanl() { // repne_scan | |
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|
2596 emit_int8((unsigned char)0xF2); |
304 | 2597 // SCASL |
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|
2598 emit_int8((unsigned char)0xAF); |
304 | 2599 } |
2600 #endif | |
2601 | |
0 | 2602 void Assembler::ret(int imm16) { |
2603 if (imm16 == 0) { | |
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|
2604 emit_int8((unsigned char)0xC3); |
0 | 2605 } else { |
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|
2606 emit_int8((unsigned char)0xC2); |
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|
2607 emit_int16(imm16); |
0 | 2608 } |
2609 } | |
2610 | |
304 | 2611 void Assembler::sahf() { |
2612 #ifdef _LP64 | |
2613 // Not supported in 64bit mode | |
2614 ShouldNotReachHere(); | |
2615 #endif | |
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|
2616 emit_int8((unsigned char)0x9E); |
304 | 2617 } |
2618 | |
2619 void Assembler::sarl(Register dst, int imm8) { | |
2620 int encode = prefix_and_encode(dst->encoding()); | |
2621 assert(isShiftCount(imm8), "illegal shift count"); | |
2622 if (imm8 == 1) { | |
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|
2623 emit_int8((unsigned char)0xD1); |
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|
2624 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 2625 } else { |
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changeset
|
2626 emit_int8((unsigned char)0xC1); |
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|
2627 emit_int8((unsigned char)(0xF8 | encode)); |
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changeset
|
2628 emit_int8(imm8); |
304 | 2629 } |
2630 } | |
2631 | |
2632 void Assembler::sarl(Register dst) { | |
2633 int encode = prefix_and_encode(dst->encoding()); | |
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|
2634 emit_int8((unsigned char)0xD3); |
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changeset
|
2635 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 2636 } |
2637 | |
2638 void Assembler::sbbl(Address dst, int32_t imm32) { | |
2639 InstructionMark im(this); | |
2640 prefix(dst); | |
2641 emit_arith_operand(0x81, rbx, dst, imm32); | |
2642 } | |
2643 | |
2644 void Assembler::sbbl(Register dst, int32_t imm32) { | |
2645 prefix(dst); | |
2646 emit_arith(0x81, 0xD8, dst, imm32); | |
2647 } | |
2648 | |
2649 | |
2650 void Assembler::sbbl(Register dst, Address src) { | |
2651 InstructionMark im(this); | |
2652 prefix(src, dst); | |
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changeset
|
2653 emit_int8(0x1B); |
304 | 2654 emit_operand(dst, src); |
2655 } | |
2656 | |
2657 void Assembler::sbbl(Register dst, Register src) { | |
2658 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2659 emit_arith(0x1B, 0xC0, dst, src); | |
2660 } | |
2661 | |
2662 void Assembler::setb(Condition cc, Register dst) { | |
2663 assert(0 <= cc && cc < 16, "illegal cc"); | |
2664 int encode = prefix_and_encode(dst->encoding(), true); | |
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|
2665 emit_int8(0x0F); |
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changeset
|
2666 emit_int8((unsigned char)0x90 | cc); |
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changeset
|
2667 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 2668 } |
2669 | |
2670 void Assembler::shll(Register dst, int imm8) { | |
2671 assert(isShiftCount(imm8), "illegal shift count"); | |
2672 int encode = prefix_and_encode(dst->encoding()); | |
2673 if (imm8 == 1 ) { | |
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|
2674 emit_int8((unsigned char)0xD1); |
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changeset
|
2675 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 2676 } else { |
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|
2677 emit_int8((unsigned char)0xC1); |
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changeset
|
2678 emit_int8((unsigned char)(0xE0 | encode)); |
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changeset
|
2679 emit_int8(imm8); |
304 | 2680 } |
2681 } | |
2682 | |
2683 void Assembler::shll(Register dst) { | |
2684 int encode = prefix_and_encode(dst->encoding()); | |
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changeset
|
2685 emit_int8((unsigned char)0xD3); |
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changeset
|
2686 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 2687 } |
2688 | |
2689 void Assembler::shrl(Register dst, int imm8) { | |
2690 assert(isShiftCount(imm8), "illegal shift count"); | |
2691 int encode = prefix_and_encode(dst->encoding()); | |
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changeset
|
2692 emit_int8((unsigned char)0xC1); |
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changeset
|
2693 emit_int8((unsigned char)(0xE8 | encode)); |
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changeset
|
2694 emit_int8(imm8); |
304 | 2695 } |
2696 | |
2697 void Assembler::shrl(Register dst) { | |
2698 int encode = prefix_and_encode(dst->encoding()); | |
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changeset
|
2699 emit_int8((unsigned char)0xD3); |
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|
2700 emit_int8((unsigned char)(0xE8 | encode)); |
304 | 2701 } |
0 | 2702 |
2703 // copies a single word from [esi] to [edi] | |
2704 void Assembler::smovl() { | |
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|
2705 emit_int8((unsigned char)0xA5); |
0 | 2706 } |
2707 | |
304 | 2708 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
2709 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2710 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); |
304 | 2711 } |
2712 | |
2008 | 2713 void Assembler::sqrtsd(XMMRegister dst, Address src) { |
2714 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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|
2715 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); |
2008 | 2716 } |
2717 | |
2718 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { | |
4759 | 2719 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
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2720 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); |
2008 | 2721 } |
2722 | |
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|
2723 void Assembler::std() { |
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|
2724 emit_int8((unsigned char)0xFD); |
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|
2725 } |
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|
2726 |
2008 | 2727 void Assembler::sqrtss(XMMRegister dst, Address src) { |
4759 | 2728 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
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|
2729 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); |
2008 | 2730 } |
2731 | |
304 | 2732 void Assembler::stmxcsr( Address dst) { |
2733 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2734 InstructionMark im(this); | |
2735 prefix(dst); | |
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|
2736 emit_int8(0x0F); |
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|
2737 emit_int8((unsigned char)0xAE); |
304 | 2738 emit_operand(as_Register(3), dst); |
2739 } | |
2740 | |
2741 void Assembler::subl(Address dst, int32_t imm32) { | |
2742 InstructionMark im(this); | |
2743 prefix(dst); | |
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changeset
|
2744 emit_arith_operand(0x81, rbp, dst, imm32); |
304 | 2745 } |
2746 | |
2747 void Assembler::subl(Address dst, Register src) { | |
2748 InstructionMark im(this); | |
2749 prefix(dst, src); | |
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|
2750 emit_int8(0x29); |
304 | 2751 emit_operand(src, dst); |
2752 } | |
2753 | |
2100
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|
2754 void Assembler::subl(Register dst, int32_t imm32) { |
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|
2755 prefix(dst); |
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|
2756 emit_arith(0x81, 0xE8, dst, imm32); |
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|
2757 } |
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|
2758 |
4947
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changeset
|
2759 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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|
2760 void Assembler::subl_imm32(Register dst, int32_t imm32) { |
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|
2761 prefix(dst); |
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changeset
|
2762 emit_arith_imm32(0x81, 0xE8, dst, imm32); |
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|
2763 } |
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|
2764 |
304 | 2765 void Assembler::subl(Register dst, Address src) { |
2766 InstructionMark im(this); | |
2767 prefix(src, dst); | |
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changeset
|
2768 emit_int8(0x2B); |
304 | 2769 emit_operand(dst, src); |
2770 } | |
2771 | |
2772 void Assembler::subl(Register dst, Register src) { | |
2773 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2774 emit_arith(0x2B, 0xC0, dst, src); | |
2775 } | |
2776 | |
2777 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | |
2778 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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changeset
|
2779 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2); |
304 | 2780 } |
2781 | |
2782 void Assembler::subsd(XMMRegister dst, Address src) { | |
2783 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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changeset
|
2784 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2); |
304 | 2785 } |
2786 | |
2787 void Assembler::subss(XMMRegister dst, XMMRegister src) { | |
2788 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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|
2789 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3); |
304 | 2790 } |
2791 | |
2792 void Assembler::subss(XMMRegister dst, Address src) { | |
2793 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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|
2794 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3); |
304 | 2795 } |
2796 | |
2797 void Assembler::testb(Register dst, int imm8) { | |
2798 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
2799 (void) prefix_and_encode(dst->encoding(), true); | |
2800 emit_arith_b(0xF6, 0xC0, dst, imm8); | |
2801 } | |
2802 | |
2803 void Assembler::testl(Register dst, int32_t imm32) { | |
2804 // not using emit_arith because test | |
2805 // doesn't support sign-extension of | |
2806 // 8bit operands | |
2807 int encode = dst->encoding(); | |
2808 if (encode == 0) { | |
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changeset
|
2809 emit_int8((unsigned char)0xA9); |
304 | 2810 } else { |
2811 encode = prefix_and_encode(encode); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
2812 emit_int8((unsigned char)0xF7); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
2813 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 2814 } |
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
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7475
diff
changeset
|
2815 emit_int32(imm32); |
304 | 2816 } |
2817 | |
2818 void Assembler::testl(Register dst, Register src) { | |
2819 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2820 emit_arith(0x85, 0xC0, dst, src); | |
2821 } | |
2822 | |
2823 void Assembler::testl(Register dst, Address src) { | |
2824 InstructionMark im(this); | |
2825 prefix(src, dst); | |
7430
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changeset
|
2826 emit_int8((unsigned char)0x85); |
304 | 2827 emit_operand(dst, src); |
2828 } | |
2829 | |
2830 void Assembler::ucomisd(XMMRegister dst, Address src) { | |
2831 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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|
2832 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66); |
304 | 2833 } |
2834 | |
2835 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | |
2836 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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|
2837 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66); |
304 | 2838 } |
2839 | |
2840 void Assembler::ucomiss(XMMRegister dst, Address src) { | |
2841 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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|
2842 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE); |
304 | 2843 } |
2844 | |
2845 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | |
2846 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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|
2847 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE); |
304 | 2848 } |
2849 | |
2850 | |
2851 void Assembler::xaddl(Address dst, Register src) { | |
2852 InstructionMark im(this); | |
2853 prefix(dst, src); | |
7430
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changeset
|
2854 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
2855 emit_int8((unsigned char)0xC1); |
304 | 2856 emit_operand(src, dst); |
2857 } | |
2858 | |
2859 void Assembler::xchgl(Register dst, Address src) { // xchg | |
2860 InstructionMark im(this); | |
2861 prefix(src, dst); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
2862 emit_int8((unsigned char)0x87); |
304 | 2863 emit_operand(dst, src); |
2864 } | |
2865 | |
2866 void Assembler::xchgl(Register dst, Register src) { | |
2867 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
7430
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|
2868 emit_int8((unsigned char)0x87); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
2869 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 2870 } |
2871 | |
7199
cd3d6a6b95d9
8003240: x86: move MacroAssembler into separate file
twisti
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7198
diff
changeset
|
2872 void Assembler::xgetbv() { |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
2873 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
2874 emit_int8(0x01); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
2875 emit_int8((unsigned char)0xD0); |
7199
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changeset
|
2876 } |
cd3d6a6b95d9
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changeset
|
2877 |
304 | 2878 void Assembler::xorl(Register dst, int32_t imm32) { |
2879 prefix(dst); | |
2880 emit_arith(0x81, 0xF0, dst, imm32); | |
2881 } | |
2882 | |
2883 void Assembler::xorl(Register dst, Address src) { | |
2884 InstructionMark im(this); | |
2885 prefix(src, dst); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
2886 emit_int8(0x33); |
304 | 2887 emit_operand(dst, src); |
2888 } | |
2889 | |
2890 void Assembler::xorl(Register dst, Register src) { | |
2891 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2892 emit_arith(0x33, 0xC0, dst, src); | |
2893 } | |
2894 | |
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|
2895 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2896 // AVX 3-operands scalar float-point arithmetic instructions |
4761
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|
2897 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2898 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2899 assert(VM_Version::supports_avx(), ""); |
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|
2900 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
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changeset
|
2901 } |
65149e74c706
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changeset
|
2902 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2903 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2904 assert(VM_Version::supports_avx(), ""); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2905 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2906 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2907 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2908 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2909 assert(VM_Version::supports_avx(), ""); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2910 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2911 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2912 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2913 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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parents:
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diff
changeset
|
2914 assert(VM_Version::supports_avx(), ""); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2915 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2916 } |
65149e74c706
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changeset
|
2917 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2918 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
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diff
changeset
|
2919 assert(VM_Version::supports_avx(), ""); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2920 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2921 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2922 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2923 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2924 assert(VM_Version::supports_avx(), ""); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
2925 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2926 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2927 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2928 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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diff
changeset
|
2929 assert(VM_Version::supports_avx(), ""); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2930 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
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|
2931 } |
65149e74c706
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changeset
|
2932 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2933 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2934 assert(VM_Version::supports_avx(), ""); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2935 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
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|
2936 } |
65149e74c706
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|
2937 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2938 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2939 assert(VM_Version::supports_avx(), ""); |
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2940 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
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|
2941 } |
65149e74c706
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changeset
|
2942 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2943 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2944 assert(VM_Version::supports_avx(), ""); |
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2945 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
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|
2946 } |
65149e74c706
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|
2947 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2948 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { |
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|
2949 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2950 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
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|
2951 } |
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|
2952 |
65149e74c706
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|
2953 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
2954 assert(VM_Version::supports_avx(), ""); |
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changeset
|
2955 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
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|
2956 } |
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|
2957 |
65149e74c706
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|
2958 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
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|
2959 assert(VM_Version::supports_avx(), ""); |
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changeset
|
2960 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
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|
2961 } |
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changeset
|
2962 |
65149e74c706
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changeset
|
2963 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2964 assert(VM_Version::supports_avx(), ""); |
6614
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changeset
|
2965 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
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diff
changeset
|
2966 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2967 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2968 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2969 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2970 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2971 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2972 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2973 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2974 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2975 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2976 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2977 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2978 //====================VECTOR ARITHMETIC===================================== |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2979 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2980 // Float-point vector arithmetic |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2981 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2982 void Assembler::addpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2983 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2984 emit_simd_arith(0x58, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2985 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2986 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2987 void Assembler::addps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2988 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2989 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2990 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2991 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2992 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2993 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2994 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2995 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2996 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2997 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2998 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2999 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3000 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3001 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3002 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3003 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3004 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3005 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3006 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3007 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3008 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3009 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3010 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3011 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3012 void Assembler::subpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3013 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3014 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3015 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3016 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3017 void Assembler::subps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3018 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3019 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3020 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3021 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3022 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3023 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3024 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3025 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3026 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3027 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3028 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3029 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3030 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3031 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3032 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3033 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3034 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3035 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3036 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3037 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3038 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3039 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3040 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3041 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3042 void Assembler::mulpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3043 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3044 emit_simd_arith(0x59, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3045 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3046 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3047 void Assembler::mulps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3048 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3049 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3050 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3051 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3052 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3053 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3054 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3055 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3056 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3057 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3058 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3059 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3060 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3061 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3062 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3063 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3064 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3065 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3066 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3067 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3068 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3069 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3070 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3071 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3072 void Assembler::divpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3073 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3074 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3075 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3076 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3077 void Assembler::divps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3078 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3079 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3080 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3081 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3082 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3083 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3084 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3085 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3086 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3087 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3088 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3089 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3090 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3091 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3092 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3093 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3094 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3095 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3096 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3097 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3098 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3099 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3100 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3101 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3102 void Assembler::andpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3103 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3104 emit_simd_arith(0x54, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3105 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3106 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3107 void Assembler::andps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3108 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3109 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3110 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3111 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3112 void Assembler::andps(XMMRegister dst, Address src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3113 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3114 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3115 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3116 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3117 void Assembler::andpd(XMMRegister dst, Address src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3118 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3119 emit_simd_arith(0x54, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3120 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3121 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3122 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3123 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3124 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3125 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3126 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3127 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3128 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3129 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3130 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3131 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3132 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3133 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3134 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3135 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3136 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3137 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3138 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3139 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3140 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3141 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3142 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3143 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3144 emit_simd_arith(0x57, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3145 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3146 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3147 void Assembler::xorps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3148 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3149 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3150 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3151 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3152 void Assembler::xorpd(XMMRegister dst, Address src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3153 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3154 emit_simd_arith(0x57, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3155 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3156 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3157 void Assembler::xorps(XMMRegister dst, Address src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3158 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3159 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3160 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3161 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3162 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3163 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3164 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3165 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3166 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3167 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3168 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3169 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3170 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3171 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3172 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3173 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3174 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3175 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3176 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3177 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3178 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3179 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3180 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3181 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3182 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3183 // Integer vector arithmetic |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3184 void Assembler::paddb(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3185 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3186 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3187 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3188 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3189 void Assembler::paddw(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3190 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3191 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3192 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3193 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3194 void Assembler::paddd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3195 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3196 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3197 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3198 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3199 void Assembler::paddq(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3200 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3201 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3202 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3203 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3204 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3205 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3206 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3207 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3208 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3209 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3210 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3211 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3212 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3213 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3214 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3215 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3216 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3217 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3218 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3219 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3220 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3221 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3222 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3223 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3224 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3225 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3226 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3227 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3228 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3229 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3230 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3231 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3232 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3233 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3234 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3235 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3236 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3237 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3238 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3239 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3240 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3241 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3242 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3243 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3244 void Assembler::psubb(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3245 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3246 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3247 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3248 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3249 void Assembler::psubw(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3250 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3251 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3252 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3253 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3254 void Assembler::psubd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3255 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3256 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3257 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3258 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3259 void Assembler::psubq(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3260 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3261 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3262 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3263 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3264 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3265 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3266 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3267 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3268 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3269 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3270 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3271 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3272 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3273 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3274 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3275 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3276 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3277 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3278 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3279 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3280 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3281 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3282 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3283 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3284 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3285 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3286 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3287 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3288 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3289 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3290 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3291 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3292 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3293 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3294 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3295 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3296 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3297 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3298 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3299 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3300 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3301 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3302 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3303 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3304 void Assembler::pmullw(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3305 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3306 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3307 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3308 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3309 void Assembler::pmulld(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3310 assert(VM_Version::supports_sse4_1(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3311 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3312 emit_int8(0x40); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3313 emit_int8((unsigned char)(0xC0 | encode)); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3314 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3315 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3316 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3317 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3318 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3319 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3320 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3321 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3322 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3323 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3324 emit_int8(0x40); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3325 emit_int8((unsigned char)(0xC0 | encode)); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3326 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3327 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3328 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3329 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3330 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3331 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3332 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3333 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3334 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3335 InstructionMark im(this); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3336 int dst_enc = dst->encoding(); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3337 int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3338 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3339 emit_int8(0x40); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3340 emit_operand(dst, src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3341 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3342 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3343 // Shift packed integers left by specified number of bits. |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3344 void Assembler::psllw(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3345 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3346 // XMM6 is for /6 encoding: 66 0F 71 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3347 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3348 emit_int8(0x71); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3349 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3350 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3351 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3352 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3353 void Assembler::pslld(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3354 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3355 // XMM6 is for /6 encoding: 66 0F 72 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3356 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3357 emit_int8(0x72); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3358 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3359 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3360 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3361 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3362 void Assembler::psllq(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3363 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3364 // XMM6 is for /6 encoding: 66 0F 73 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3365 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3366 emit_int8(0x73); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3367 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3368 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3369 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3370 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3371 void Assembler::psllw(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3372 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3373 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3374 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3375 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3376 void Assembler::pslld(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3377 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3378 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3379 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3380 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3381 void Assembler::psllq(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3382 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3383 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3384 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3385 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3386 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3387 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3388 // XMM6 is for /6 encoding: 66 0F 71 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3389 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3390 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3391 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3392 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3393 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3394 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3395 // XMM6 is for /6 encoding: 66 0F 72 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3396 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3397 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3398 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3399 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3400 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3401 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3402 // XMM6 is for /6 encoding: 66 0F 73 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3403 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3404 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3405 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3406 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3407 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3408 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3409 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3410 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3411 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3412 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3413 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3414 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3415 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3416 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3417 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3418 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3419 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3420 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3421 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3422 // Shift packed integers logically right by specified number of bits. |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3423 void Assembler::psrlw(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3424 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3425 // XMM2 is for /2 encoding: 66 0F 71 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3426 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3427 emit_int8(0x71); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3428 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3429 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3430 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3431 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3432 void Assembler::psrld(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3433 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3434 // XMM2 is for /2 encoding: 66 0F 72 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3435 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3436 emit_int8(0x72); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3437 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3438 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3439 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3440 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3441 void Assembler::psrlq(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3442 // Do not confuse it with psrldq SSE2 instruction which |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3443 // shifts 128 bit value in xmm register by number of bytes. |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3444 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3445 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3446 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3447 emit_int8(0x73); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3448 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3449 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3450 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3451 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3452 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3453 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3454 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3455 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3456 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3457 void Assembler::psrld(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3458 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3459 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3460 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3461 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3462 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3463 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3464 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3465 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3466 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3467 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3468 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3469 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3470 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3471 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3472 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3473 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3474 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3475 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3476 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3477 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3478 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3479 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3480 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3481 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3482 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3483 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3484 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3485 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3486 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3487 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3488 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3489 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3490 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3491 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3492 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3493 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3494 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3495 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3496 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3497 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3498 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3499 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3500 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3501 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3502 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3503 // Shift packed integers arithmetically right by specified number of bits. |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3504 void Assembler::psraw(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3505 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3506 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3507 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3508 emit_int8(0x71); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3509 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3510 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3511 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3512 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3513 void Assembler::psrad(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3514 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3515 // XMM4 is for /4 encoding: 66 0F 72 /4 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3516 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3517 emit_int8(0x72); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3518 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3519 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3520 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3521 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3522 void Assembler::psraw(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3523 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3524 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3525 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3526 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3527 void Assembler::psrad(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3528 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3529 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3530 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3531 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3532 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3533 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3534 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3535 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3536 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3537 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3538 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3539 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3540 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3541 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3542 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3543 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3544 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3545 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3546 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3547 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3548 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3549 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3550 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3551 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3552 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3553 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3554 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3555 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3556 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3557 // AND packed integers |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3558 void Assembler::pand(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3559 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3560 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3561 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3562 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3563 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3564 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3565 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3566 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3567 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3568 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3569 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3570 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3571 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3572 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3573 void Assembler::por(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3574 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3575 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3576 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3577 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3578 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3579 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3580 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3581 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3582 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3583 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3584 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3585 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3586 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3587 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3588 void Assembler::pxor(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3589 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3590 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66); |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3591 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3592 |
6225 | 3593 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3594 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3595 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3596 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3597 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3598 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3599 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3600 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3601 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3602 |
6225 | 3603 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3604 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3605 assert(VM_Version::supports_avx(), ""); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3606 bool vector256 = true; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3607 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3608 emit_int8(0x18); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3609 emit_int8((unsigned char)(0xC0 | encode)); |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3610 // 0x00 - insert into lower 128 bits |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3611 // 0x01 - insert into upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3612 emit_int8(0x01); |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3613 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3614 |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3615 void Assembler::vinsertf128h(XMMRegister dst, Address src) { |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3616 assert(VM_Version::supports_avx(), ""); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3617 InstructionMark im(this); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3618 bool vector256 = true; |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3619 assert(dst != xnoreg, "sanity"); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3620 int dst_enc = dst->encoding(); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3621 // swap src<->dst for encoding |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3622 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3623 emit_int8(0x18); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3624 emit_operand(dst, src); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3625 // 0x01 - insert into upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3626 emit_int8(0x01); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3627 } |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3628 |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3629 void Assembler::vextractf128h(Address dst, XMMRegister src) { |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3630 assert(VM_Version::supports_avx(), ""); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3631 InstructionMark im(this); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3632 bool vector256 = true; |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3633 assert(src != xnoreg, "sanity"); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3634 int src_enc = src->encoding(); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3635 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3636 emit_int8(0x19); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3637 emit_operand(src, dst); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3638 // 0x01 - extract from upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3639 emit_int8(0x01); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3640 } |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3641 |
6225 | 3642 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
3643 assert(VM_Version::supports_avx2(), ""); | |
3644 bool vector256 = true; | |
3645 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3646 emit_int8(0x38); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3647 emit_int8((unsigned char)(0xC0 | encode)); |
6225 | 3648 // 0x00 - insert into lower 128 bits |
3649 // 0x01 - insert into upper 128 bits | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3650 emit_int8(0x01); |
6225 | 3651 } |
3652 | |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3653 void Assembler::vinserti128h(XMMRegister dst, Address src) { |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3654 assert(VM_Version::supports_avx2(), ""); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3655 InstructionMark im(this); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3656 bool vector256 = true; |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3657 assert(dst != xnoreg, "sanity"); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3658 int dst_enc = dst->encoding(); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3659 // swap src<->dst for encoding |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3660 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3661 emit_int8(0x38); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3662 emit_operand(dst, src); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3663 // 0x01 - insert into upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3664 emit_int8(0x01); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3665 } |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3666 |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3667 void Assembler::vextracti128h(Address dst, XMMRegister src) { |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3668 assert(VM_Version::supports_avx2(), ""); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3669 InstructionMark im(this); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3670 bool vector256 = true; |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3671 assert(src != xnoreg, "sanity"); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3672 int src_enc = src->encoding(); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3673 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3674 emit_int8(0x39); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
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6725
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changeset
|
3675 emit_operand(src, dst); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
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6725
diff
changeset
|
3676 // 0x01 - extract from upper 128 bits |
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d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
3677 emit_int8(0x01); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
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6725
diff
changeset
|
3678 } |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
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diff
changeset
|
3679 |
7475
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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7474
diff
changeset
|
3680 // duplicate 4-bytes integer data from src into 8 locations in dest |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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diff
changeset
|
3681 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) { |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
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diff
changeset
|
3682 assert(VM_Version::supports_avx2(), ""); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3683 bool vector256 = true; |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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diff
changeset
|
3684 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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diff
changeset
|
3685 emit_int8(0x58); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
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7474
diff
changeset
|
3686 emit_int8((unsigned char)(0xC0 | encode)); |
e2e6bf86682c
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7474
diff
changeset
|
3687 } |
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7474
diff
changeset
|
3688 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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6141
diff
changeset
|
3689 void Assembler::vzeroupper() { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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6141
diff
changeset
|
3690 assert(VM_Version::supports_avx(), ""); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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6141
diff
changeset
|
3691 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
3692 emit_int8(0x77); |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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6141
diff
changeset
|
3693 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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diff
changeset
|
3694 |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3695 |
304 | 3696 #ifndef _LP64 |
3697 // 32bit only pieces of the assembler | |
3698 | |
3699 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | |
3700 // NO PREFIX AS NEVER 64BIT | |
3701 InstructionMark im(this); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
3702 emit_int8((unsigned char)0x81); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
3703 emit_int8((unsigned char)(0xF8 | src1->encoding())); |
304 | 3704 emit_data(imm32, rspec, 0); |
3705 } | |
3706 | |
3707 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { | |
3708 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs | |
3709 InstructionMark im(this); | |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
3710 emit_int8((unsigned char)0x81); |
304 | 3711 emit_operand(rdi, src1); |
3712 emit_data(imm32, rspec, 0); | |
3713 } | |
3714 | |
3715 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, | |
3716 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded | |
3717 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. | |
3718 void Assembler::cmpxchg8(Address adr) { | |
3719 InstructionMark im(this); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
3720 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
3721 emit_int8((unsigned char)0xC7); |
304 | 3722 emit_operand(rcx, adr); |
3723 } | |
3724 | |
3725 void Assembler::decl(Register dst) { | |
3726 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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diff
changeset
|
3727 emit_int8(0x48 | dst->encoding()); |
304 | 3728 } |
3729 | |
3730 #endif // _LP64 | |
3731 | |
3732 // 64bit typically doesn't use the x87 but needs to for the trig funcs | |
3733 | |
3734 void Assembler::fabs() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
3735 emit_int8((unsigned char)0xD9); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
3736 emit_int8((unsigned char)0xE1); |
304 | 3737 } |
3738 | |
3739 void Assembler::fadd(int i) { | |
3740 emit_farith(0xD8, 0xC0, i); | |
3741 } | |
3742 | |
3743 void Assembler::fadd_d(Address src) { | |
3744 InstructionMark im(this); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
3745 emit_int8((unsigned char)0xDC); |
304 | 3746 emit_operand32(rax, src); |
3747 } | |
3748 | |
3749 void Assembler::fadd_s(Address src) { | |
3750 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
3751 emit_int8((unsigned char)0xD8); |
304 | 3752 emit_operand32(rax, src); |
3753 } | |
3754 | |
3755 void Assembler::fadda(int i) { | |
3756 emit_farith(0xDC, 0xC0, i); | |
3757 } | |
3758 | |
3759 void Assembler::faddp(int i) { | |
3760 emit_farith(0xDE, 0xC0, i); | |
3761 } | |
3762 | |
3763 void Assembler::fchs() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
3764 emit_int8((unsigned char)0xD9); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
3765 emit_int8((unsigned char)0xE0); |
304 | 3766 } |
3767 | |
3768 void Assembler::fcom(int i) { | |
3769 emit_farith(0xD8, 0xD0, i); | |
3770 } | |
3771 | |
3772 void Assembler::fcomp(int i) { | |
3773 emit_farith(0xD8, 0xD8, i); | |
3774 } | |
3775 | |
3776 void Assembler::fcomp_d(Address src) { | |
3777 InstructionMark im(this); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3778 emit_int8((unsigned char)0xDC); |
304 | 3779 emit_operand32(rbx, src); |
3780 } | |
3781 | |
3782 void Assembler::fcomp_s(Address src) { | |
3783 InstructionMark im(this); | |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
3784 emit_int8((unsigned char)0xD8); |
304 | 3785 emit_operand32(rbx, src); |
3786 } | |
3787 | |
3788 void Assembler::fcompp() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3789 emit_int8((unsigned char)0xDE); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
3790 emit_int8((unsigned char)0xD9); |
304 | 3791 } |
3792 | |
3793 void Assembler::fcos() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3794 emit_int8((unsigned char)0xD9); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3795 emit_int8((unsigned char)0xFF); |
304 | 3796 } |
3797 | |
3798 void Assembler::fdecstp() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3799 emit_int8((unsigned char)0xD9); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
3800 emit_int8((unsigned char)0xF6); |
304 | 3801 } |
3802 | |
3803 void Assembler::fdiv(int i) { | |
3804 emit_farith(0xD8, 0xF0, i); | |
3805 } | |
3806 | |
3807 void Assembler::fdiv_d(Address src) { | |
3808 InstructionMark im(this); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
3809 emit_int8((unsigned char)0xDC); |
304 | 3810 emit_operand32(rsi, src); |
3811 } | |
3812 | |
3813 void Assembler::fdiv_s(Address src) { | |
3814 InstructionMark im(this); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
3815 emit_int8((unsigned char)0xD8); |
304 | 3816 emit_operand32(rsi, src); |
3817 } | |
3818 | |
3819 void Assembler::fdiva(int i) { | |
3820 emit_farith(0xDC, 0xF8, i); | |
3821 } | |
3822 | |
3823 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) | |
3824 // is erroneous for some of the floating-point instructions below. | |
3825 | |
3826 void Assembler::fdivp(int i) { | |
3827 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) | |
3828 } | |
3829 | |
3830 void Assembler::fdivr(int i) { | |
3831 emit_farith(0xD8, 0xF8, i); | |
3832 } | |
3833 | |
3834 void Assembler::fdivr_d(Address src) { | |
3835 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3836 emit_int8((unsigned char)0xDC); |
304 | 3837 emit_operand32(rdi, src); |
3838 } | |
3839 | |
3840 void Assembler::fdivr_s(Address src) { | |
3841 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3842 emit_int8((unsigned char)0xD8); |
304 | 3843 emit_operand32(rdi, src); |
3844 } | |
3845 | |
3846 void Assembler::fdivra(int i) { | |
3847 emit_farith(0xDC, 0xF0, i); | |
3848 } | |
3849 | |
3850 void Assembler::fdivrp(int i) { | |
3851 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) | |
3852 } | |
3853 | |
3854 void Assembler::ffree(int i) { | |
3855 emit_farith(0xDD, 0xC0, i); | |
3856 } | |
3857 | |
3858 void Assembler::fild_d(Address adr) { | |
3859 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
3860 emit_int8((unsigned char)0xDF); |
304 | 3861 emit_operand32(rbp, adr); |
3862 } | |
3863 | |
3864 void Assembler::fild_s(Address adr) { | |
3865 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3866 emit_int8((unsigned char)0xDB); |
304 | 3867 emit_operand32(rax, adr); |
3868 } | |
3869 | |
3870 void Assembler::fincstp() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3871 emit_int8((unsigned char)0xD9); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
3872 emit_int8((unsigned char)0xF7); |
304 | 3873 } |
3874 | |
3875 void Assembler::finit() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
3876 emit_int8((unsigned char)0x9B); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
3877 emit_int8((unsigned char)0xDB); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
3878 emit_int8((unsigned char)0xE3); |
304 | 3879 } |
3880 | |
3881 void Assembler::fist_s(Address adr) { | |
3882 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
3883 emit_int8((unsigned char)0xDB); |
304 | 3884 emit_operand32(rdx, adr); |
3885 } | |
3886 | |
3887 void Assembler::fistp_d(Address adr) { | |
3888 InstructionMark im(this); | |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
3889 emit_int8((unsigned char)0xDF); |
304 | 3890 emit_operand32(rdi, adr); |
3891 } | |
3892 | |
3893 void Assembler::fistp_s(Address adr) { | |
3894 InstructionMark im(this); | |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
3895 emit_int8((unsigned char)0xDB); |
304 | 3896 emit_operand32(rbx, adr); |
3897 } | |
0 | 3898 |
3899 void Assembler::fld1() { | |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
3900 emit_int8((unsigned char)0xD9); |
d02120b7a34f
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changeset
|
3901 emit_int8((unsigned char)0xE8); |
0 | 3902 } |
3903 | |
304 | 3904 void Assembler::fld_d(Address adr) { |
3905 InstructionMark im(this); | |
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changeset
|
3906 emit_int8((unsigned char)0xDD); |
304 | 3907 emit_operand32(rax, adr); |
3908 } | |
0 | 3909 |
3910 void Assembler::fld_s(Address adr) { | |
3911 InstructionMark im(this); | |
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changeset
|
3912 emit_int8((unsigned char)0xD9); |
304 | 3913 emit_operand32(rax, adr); |
3914 } | |
3915 | |
3916 | |
3917 void Assembler::fld_s(int index) { | |
0 | 3918 emit_farith(0xD9, 0xC0, index); |
3919 } | |
3920 | |
3921 void Assembler::fld_x(Address adr) { | |
3922 InstructionMark im(this); | |
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diff
changeset
|
3923 emit_int8((unsigned char)0xDB); |
304 | 3924 emit_operand32(rbp, adr); |
3925 } | |
3926 | |
3927 void Assembler::fldcw(Address src) { | |
3928 InstructionMark im(this); | |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
3929 emit_int8((unsigned char)0xD9); |
304 | 3930 emit_operand32(rbp, src); |
3931 } | |
3932 | |
3933 void Assembler::fldenv(Address src) { | |
0 | 3934 InstructionMark im(this); |
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changeset
|
3935 emit_int8((unsigned char)0xD9); |
304 | 3936 emit_operand32(rsp, src); |
3937 } | |
3938 | |
3939 void Assembler::fldlg2() { | |
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|
3940 emit_int8((unsigned char)0xD9); |
d02120b7a34f
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changeset
|
3941 emit_int8((unsigned char)0xEC); |
304 | 3942 } |
0 | 3943 |
3944 void Assembler::fldln2() { | |
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|
3945 emit_int8((unsigned char)0xD9); |
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changeset
|
3946 emit_int8((unsigned char)0xED); |
0 | 3947 } |
3948 | |
304 | 3949 void Assembler::fldz() { |
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|
3950 emit_int8((unsigned char)0xD9); |
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changeset
|
3951 emit_int8((unsigned char)0xEE); |
304 | 3952 } |
0 | 3953 |
3954 void Assembler::flog() { | |
3955 fldln2(); | |
3956 fxch(); | |
3957 fyl2x(); | |
3958 } | |
3959 | |
3960 void Assembler::flog10() { | |
3961 fldlg2(); | |
3962 fxch(); | |
3963 fyl2x(); | |
3964 } | |
3965 | |
304 | 3966 void Assembler::fmul(int i) { |
3967 emit_farith(0xD8, 0xC8, i); | |
3968 } | |
3969 | |
3970 void Assembler::fmul_d(Address src) { | |
3971 InstructionMark im(this); | |
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3972 emit_int8((unsigned char)0xDC); |
304 | 3973 emit_operand32(rcx, src); |
3974 } | |
3975 | |
3976 void Assembler::fmul_s(Address src) { | |
3977 InstructionMark im(this); | |
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3978 emit_int8((unsigned char)0xD8); |
304 | 3979 emit_operand32(rcx, src); |
3980 } | |
3981 | |
3982 void Assembler::fmula(int i) { | |
3983 emit_farith(0xDC, 0xC8, i); | |
3984 } | |
3985 | |
3986 void Assembler::fmulp(int i) { | |
3987 emit_farith(0xDE, 0xC8, i); | |
3988 } | |
3989 | |
3990 void Assembler::fnsave(Address dst) { | |
3991 InstructionMark im(this); | |
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3992 emit_int8((unsigned char)0xDD); |
304 | 3993 emit_operand32(rsi, dst); |
3994 } | |
3995 | |
3996 void Assembler::fnstcw(Address src) { | |
3997 InstructionMark im(this); | |
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3998 emit_int8((unsigned char)0x9B); |
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3999 emit_int8((unsigned char)0xD9); |
304 | 4000 emit_operand32(rdi, src); |
4001 } | |
4002 | |
4003 void Assembler::fnstsw_ax() { | |
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4004 emit_int8((unsigned char)0xDF); |
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4005 emit_int8((unsigned char)0xE0); |
304 | 4006 } |
4007 | |
4008 void Assembler::fprem() { | |
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4009 emit_int8((unsigned char)0xD9); |
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4010 emit_int8((unsigned char)0xF8); |
304 | 4011 } |
4012 | |
4013 void Assembler::fprem1() { | |
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4014 emit_int8((unsigned char)0xD9); |
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4015 emit_int8((unsigned char)0xF5); |
304 | 4016 } |
4017 | |
4018 void Assembler::frstor(Address src) { | |
4019 InstructionMark im(this); | |
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4020 emit_int8((unsigned char)0xDD); |
304 | 4021 emit_operand32(rsp, src); |
4022 } | |
0 | 4023 |
4024 void Assembler::fsin() { | |
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4025 emit_int8((unsigned char)0xD9); |
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4026 emit_int8((unsigned char)0xFE); |
0 | 4027 } |
4028 | |
304 | 4029 void Assembler::fsqrt() { |
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4030 emit_int8((unsigned char)0xD9); |
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4031 emit_int8((unsigned char)0xFA); |
304 | 4032 } |
4033 | |
4034 void Assembler::fst_d(Address adr) { | |
4035 InstructionMark im(this); | |
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4036 emit_int8((unsigned char)0xDD); |
304 | 4037 emit_operand32(rdx, adr); |
4038 } | |
4039 | |
4040 void Assembler::fst_s(Address adr) { | |
4041 InstructionMark im(this); | |
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4042 emit_int8((unsigned char)0xD9); |
304 | 4043 emit_operand32(rdx, adr); |
4044 } | |
4045 | |
4046 void Assembler::fstp_d(Address adr) { | |
4047 InstructionMark im(this); | |
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4048 emit_int8((unsigned char)0xDD); |
304 | 4049 emit_operand32(rbx, adr); |
4050 } | |
4051 | |
4052 void Assembler::fstp_d(int index) { | |
4053 emit_farith(0xDD, 0xD8, index); | |
4054 } | |
4055 | |
4056 void Assembler::fstp_s(Address adr) { | |
4057 InstructionMark im(this); | |
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4058 emit_int8((unsigned char)0xD9); |
304 | 4059 emit_operand32(rbx, adr); |
4060 } | |
4061 | |
4062 void Assembler::fstp_x(Address adr) { | |
4063 InstructionMark im(this); | |
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4064 emit_int8((unsigned char)0xDB); |
304 | 4065 emit_operand32(rdi, adr); |
4066 } | |
4067 | |
4068 void Assembler::fsub(int i) { | |
4069 emit_farith(0xD8, 0xE0, i); | |
4070 } | |
4071 | |
4072 void Assembler::fsub_d(Address src) { | |
4073 InstructionMark im(this); | |
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4074 emit_int8((unsigned char)0xDC); |
304 | 4075 emit_operand32(rsp, src); |
4076 } | |
4077 | |
4078 void Assembler::fsub_s(Address src) { | |
4079 InstructionMark im(this); | |
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4080 emit_int8((unsigned char)0xD8); |
304 | 4081 emit_operand32(rsp, src); |
4082 } | |
4083 | |
4084 void Assembler::fsuba(int i) { | |
4085 emit_farith(0xDC, 0xE8, i); | |
4086 } | |
4087 | |
4088 void Assembler::fsubp(int i) { | |
4089 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) | |
4090 } | |
4091 | |
4092 void Assembler::fsubr(int i) { | |
4093 emit_farith(0xD8, 0xE8, i); | |
4094 } | |
4095 | |
4096 void Assembler::fsubr_d(Address src) { | |
4097 InstructionMark im(this); | |
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4098 emit_int8((unsigned char)0xDC); |
304 | 4099 emit_operand32(rbp, src); |
4100 } | |
4101 | |
4102 void Assembler::fsubr_s(Address src) { | |
4103 InstructionMark im(this); | |
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4104 emit_int8((unsigned char)0xD8); |
304 | 4105 emit_operand32(rbp, src); |
4106 } | |
4107 | |
4108 void Assembler::fsubra(int i) { | |
4109 emit_farith(0xDC, 0xE0, i); | |
4110 } | |
4111 | |
4112 void Assembler::fsubrp(int i) { | |
4113 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) | |
0 | 4114 } |
4115 | |
4116 void Assembler::ftan() { | |
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4117 emit_int8((unsigned char)0xD9); |
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4118 emit_int8((unsigned char)0xF2); |
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4119 emit_int8((unsigned char)0xDD); |
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4120 emit_int8((unsigned char)0xD8); |
0 | 4121 } |
4122 | |
304 | 4123 void Assembler::ftst() { |
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4124 emit_int8((unsigned char)0xD9); |
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4125 emit_int8((unsigned char)0xE4); |
304 | 4126 } |
0 | 4127 |
4128 void Assembler::fucomi(int i) { | |
4129 // make sure the instruction is supported (introduced for P6, together with cmov) | |
4130 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
4131 emit_farith(0xDB, 0xE8, i); | |
4132 } | |
4133 | |
4134 void Assembler::fucomip(int i) { | |
4135 // make sure the instruction is supported (introduced for P6, together with cmov) | |
4136 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
4137 emit_farith(0xDF, 0xE8, i); | |
4138 } | |
4139 | |
4140 void Assembler::fwait() { | |
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4141 emit_int8((unsigned char)0x9B); |
0 | 4142 } |
4143 | |
304 | 4144 void Assembler::fxch(int i) { |
4145 emit_farith(0xD9, 0xC8, i); | |
4146 } | |
4147 | |
4148 void Assembler::fyl2x() { | |
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|
4149 emit_int8((unsigned char)0xD9); |
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4150 emit_int8((unsigned char)0xF1); |
304 | 4151 } |
4152 | |
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4153 void Assembler::frndint() { |
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|
4154 emit_int8((unsigned char)0xD9); |
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4155 emit_int8((unsigned char)0xFC); |
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|
4156 } |
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|
4157 |
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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|
4158 void Assembler::f2xm1() { |
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|
4159 emit_int8((unsigned char)0xD9); |
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|
4160 emit_int8((unsigned char)0xF0); |
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|
4161 } |
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|
4162 |
6759698e3140
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|
4163 void Assembler::fldl2e() { |
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|
4164 emit_int8((unsigned char)0xD9); |
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|
4165 emit_int8((unsigned char)0xEA); |
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|
4166 } |
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|
4167 |
4759 | 4168 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. |
4169 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; | |
4170 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. | |
4171 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; | |
4172 | |
4173 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. | |
4174 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
4175 if (pre > 0) { | |
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4176 emit_int8(simd_pre[pre]); |
4759 | 4177 } |
4178 if (rex_w) { | |
4179 prefixq(adr, xreg); | |
4180 } else { | |
4181 prefix(adr, xreg); | |
4182 } | |
4183 if (opc > 0) { | |
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|
4184 emit_int8(0x0F); |
4759 | 4185 int opc2 = simd_opc[opc]; |
4186 if (opc2 > 0) { | |
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|
4187 emit_int8(opc2); |
4759 | 4188 } |
4189 } | |
4190 } | |
4191 | |
4192 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
4193 if (pre > 0) { | |
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4194 emit_int8(simd_pre[pre]); |
4759 | 4195 } |
4196 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : | |
4197 prefix_and_encode(dst_enc, src_enc); | |
4198 if (opc > 0) { | |
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4199 emit_int8(0x0F); |
4759 | 4200 int opc2 = simd_opc[opc]; |
4201 if (opc2 > 0) { | |
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|
4202 emit_int8(opc2); |
4759 | 4203 } |
4204 } | |
4205 return encode; | |
4206 } | |
4207 | |
4208 | |
4209 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) { | |
4210 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { | |
4211 prefix(VEX_3bytes); | |
4212 | |
4213 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); | |
4214 byte1 = (~byte1) & 0xE0; | |
4215 byte1 |= opc; | |
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|
4216 emit_int8(byte1); |
4759 | 4217 |
4218 int byte2 = ((~nds_enc) & 0xf) << 3; | |
4219 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre; | |
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4220 emit_int8(byte2); |
4759 | 4221 } else { |
4222 prefix(VEX_2bytes); | |
4223 | |
4224 int byte1 = vex_r ? VEX_R : 0; | |
4225 byte1 = (~byte1) & 0x80; | |
4226 byte1 |= ((~nds_enc) & 0xf) << 3; | |
4227 byte1 |= (vector256 ? 4 : 0) | pre; | |
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|
4228 emit_int8(byte1); |
4759 | 4229 } |
4230 } | |
4231 | |
4232 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){ | |
4233 bool vex_r = (xreg_enc >= 8); | |
4234 bool vex_b = adr.base_needs_rex(); | |
4235 bool vex_x = adr.index_needs_rex(); | |
4236 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
4237 } | |
4238 | |
4239 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) { | |
4240 bool vex_r = (dst_enc >= 8); | |
4241 bool vex_b = (src_enc >= 8); | |
4242 bool vex_x = false; | |
4243 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
4244 return (((dst_enc & 7) << 3) | (src_enc & 7)); | |
4245 } | |
4246 | |
4247 | |
4248 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
4249 if (UseAVX > 0) { | |
4250 int xreg_enc = xreg->encoding(); | |
4251 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
4252 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256); | |
4253 } else { | |
4254 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); | |
4255 rex_prefix(adr, xreg, pre, opc, rex_w); | |
4256 } | |
4257 } | |
4258 | |
4259 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
4260 int dst_enc = dst->encoding(); | |
4261 int src_enc = src->encoding(); | |
4262 if (UseAVX > 0) { | |
4263 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
4264 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256); | |
4265 } else { | |
4266 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); | |
4267 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w); | |
4268 } | |
4269 } | |
304 | 4270 |
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4271 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { |
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4272 InstructionMark im(this); |
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4273 simd_prefix(dst, dst, src, pre); |
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4274 emit_int8(opcode); |
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4275 emit_operand(dst, src); |
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|
4276 } |
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|
4277 |
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4278 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { |
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4279 int encode = simd_prefix_and_encode(dst, dst, src, pre); |
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4280 emit_int8(opcode); |
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4281 emit_int8((unsigned char)(0xC0 | encode)); |
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4282 } |
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4283 |
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4284 // Versions with no second source register (non-destructive source). |
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4285 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { |
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4286 InstructionMark im(this); |
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4287 simd_prefix(dst, xnoreg, src, pre); |
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4288 emit_int8(opcode); |
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4289 emit_operand(dst, src); |
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4290 } |
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4291 |
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4292 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { |
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4293 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre); |
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4294 emit_int8(opcode); |
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4295 emit_int8((unsigned char)(0xC0 | encode)); |
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4296 } |
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|
4297 |
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4298 // 3-operands AVX instructions |
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4299 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
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4300 Address src, VexSimdPrefix pre, bool vector256) { |
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4301 InstructionMark im(this); |
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4302 vex_prefix(dst, nds, src, pre, vector256); |
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4303 emit_int8(opcode); |
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4304 emit_operand(dst, src); |
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|
4305 } |
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|
4306 |
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4307 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
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4308 XMMRegister src, VexSimdPrefix pre, bool vector256) { |
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4309 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256); |
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4310 emit_int8(opcode); |
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4311 emit_int8((unsigned char)(0xC0 | encode)); |
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4312 } |
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4313 |
304 | 4314 #ifndef _LP64 |
4315 | |
4316 void Assembler::incl(Register dst) { | |
4317 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
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4318 emit_int8(0x40 | dst->encoding()); |
304 | 4319 } |
4320 | |
4321 void Assembler::lea(Register dst, Address src) { | |
4322 leal(dst, src); | |
4323 } | |
4324 | |
4325 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { | |
4326 InstructionMark im(this); | |
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4327 emit_int8((unsigned char)0xC7); |
304 | 4328 emit_operand(rax, dst); |
4329 emit_data((int)imm32, rspec, 0); | |
4330 } | |
4331 | |
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4332 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
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4333 InstructionMark im(this); |
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4334 int encode = prefix_and_encode(dst->encoding()); |
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4335 emit_int8((unsigned char)(0xB8 | encode)); |
642
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4336 emit_data((int)imm32, rspec, 0); |
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4337 } |
304 | 4338 |
4339 void Assembler::popa() { // 32bit | |
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4340 emit_int8(0x61); |
304 | 4341 } |
4342 | |
4343 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { | |
4344 InstructionMark im(this); | |
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|
4345 emit_int8(0x68); |
304 | 4346 emit_data(imm32, rspec, 0); |
4347 } | |
4348 | |
4349 void Assembler::pusha() { // 32bit | |
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4350 emit_int8(0x60); |
304 | 4351 } |
4352 | |
4353 void Assembler::set_byte_if_not_zero(Register dst) { | |
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4354 emit_int8(0x0F); |
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|
4355 emit_int8((unsigned char)0x95); |
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4356 emit_int8((unsigned char)(0xE0 | dst->encoding())); |
304 | 4357 } |
4358 | |
4359 void Assembler::shldl(Register dst, Register src) { | |
7430
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|
4360 emit_int8(0x0F); |
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|
4361 emit_int8((unsigned char)0xA5); |
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4362 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); |
304 | 4363 } |
4364 | |
4365 void Assembler::shrdl(Register dst, Register src) { | |
7430
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|
4366 emit_int8(0x0F); |
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|
4367 emit_int8((unsigned char)0xAD); |
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4368 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); |
304 | 4369 } |
4370 | |
4371 #else // LP64 | |
4372 | |
1369 | 4373 void Assembler::set_byte_if_not_zero(Register dst) { |
4374 int enc = prefix_and_encode(dst->encoding(), true); | |
7430
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|
4375 emit_int8(0x0F); |
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|
4376 emit_int8((unsigned char)0x95); |
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|
4377 emit_int8((unsigned char)(0xE0 | enc)); |
1369 | 4378 } |
4379 | |
304 | 4380 // 64bit only pieces of the assembler |
4381 // This should only be used by 64bit instructions that can use rip-relative | |
4382 // it cannot be used by instructions that want an immediate value. | |
4383 | |
4384 bool Assembler::reachable(AddressLiteral adr) { | |
4385 int64_t disp; | |
4386 // None will force a 64bit literal to the code stream. Likely a placeholder | |
4387 // for something that will be patched later and we need to certain it will | |
4388 // always be reachable. | |
4389 if (adr.reloc() == relocInfo::none) { | |
4390 return false; | |
4391 } | |
4392 if (adr.reloc() == relocInfo::internal_word_type) { | |
4393 // This should be rip relative and easily reachable. | |
4394 return true; | |
4395 } | |
4396 if (adr.reloc() == relocInfo::virtual_call_type || | |
4397 adr.reloc() == relocInfo::opt_virtual_call_type || | |
4398 adr.reloc() == relocInfo::static_call_type || | |
4399 adr.reloc() == relocInfo::static_stub_type ) { | |
4400 // This should be rip relative within the code cache and easily | |
4401 // reachable until we get huge code caches. (At which point | |
4402 // ic code is going to have issues). | |
4403 return true; | |
4404 } | |
4405 if (adr.reloc() != relocInfo::external_word_type && | |
4406 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special | |
4407 adr.reloc() != relocInfo::poll_type && // relocs to identify them | |
4408 adr.reloc() != relocInfo::runtime_call_type ) { | |
4409 return false; | |
4410 } | |
4411 | |
4412 // Stress the correction code | |
4413 if (ForceUnreachable) { | |
4414 // Must be runtimecall reloc, see if it is in the codecache | |
4415 // Flipping stuff in the codecache to be unreachable causes issues | |
4416 // with things like inline caches where the additional instructions | |
4417 // are not handled. | |
4418 if (CodeCache::find_blob(adr._target) == NULL) { | |
4419 return false; | |
4420 } | |
4421 } | |
4422 // For external_word_type/runtime_call_type if it is reachable from where we | |
4423 // are now (possibly a temp buffer) and where we might end up | |
4424 // anywhere in the codeCache then we are always reachable. | |
4425 // This would have to change if we ever save/restore shared code | |
4426 // to be more pessimistic. | |
4427 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); | |
4428 if (!is_simm32(disp)) return false; | |
4429 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); | |
4430 if (!is_simm32(disp)) return false; | |
4431 | |
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4432 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int)); |
304 | 4433 |
4434 // Because rip relative is a disp + address_of_next_instruction and we | |
4435 // don't know the value of address_of_next_instruction we apply a fudge factor | |
4436 // to make sure we will be ok no matter the size of the instruction we get placed into. | |
4437 // We don't have to fudge the checks above here because they are already worst case. | |
4438 | |
4439 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal | |
4440 // + 4 because better safe than sorry. | |
4441 const int fudge = 12 + 4; | |
4442 if (disp < 0) { | |
4443 disp -= fudge; | |
4444 } else { | |
4445 disp += fudge; | |
4446 } | |
4447 return is_simm32(disp); | |
4448 } | |
4449 | |
2404
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4450 // Check if the polling page is not reachable from the code cache using rip-relative |
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4451 // addressing. |
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|
4452 bool Assembler::is_polling_page_far() { |
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4453 intptr_t addr = (intptr_t)os::get_polling_page(); |
4118
59bc0d4d9ea3
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3938
diff
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|
4454 return ForceUnreachable || |
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|
4455 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) || |
2404
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4456 !is_simm32(addr - (intptr_t)CodeCache::high_bound()); |
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|
4457 } |
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|
4458 |
304 | 4459 void Assembler::emit_data64(jlong data, |
4460 relocInfo::relocType rtype, | |
4461 int format) { | |
4462 if (rtype == relocInfo::none) { | |
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4463 emit_int64(data); |
304 | 4464 } else { |
4465 emit_data64(data, Relocation::spec_simple(rtype), format); | |
4466 } | |
4467 } | |
4468 | |
4469 void Assembler::emit_data64(jlong data, | |
4470 RelocationHolder const& rspec, | |
4471 int format) { | |
4472 assert(imm_operand == 0, "default format must be immediate in this file"); | |
4473 assert(imm_operand == format, "must be immediate"); | |
4474 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
4475 // Do not use AbstractAssembler::relocate, which is not intended for | |
4476 // embedded words. Instead, relocate to the enclosing instruction. | |
4477 code_section()->relocate(inst_mark(), rspec, format); | |
4478 #ifdef ASSERT | |
4479 check_relocation(rspec, format); | |
4480 #endif | |
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4481 emit_int64(data); |
304 | 4482 } |
4483 | |
4484 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { | |
4485 if (reg_enc >= 8) { | |
4486 prefix(REX_B); | |
4487 reg_enc -= 8; | |
4488 } else if (byteinst && reg_enc >= 4) { | |
4489 prefix(REX); | |
4490 } | |
4491 return reg_enc; | |
4492 } | |
4493 | |
4494 int Assembler::prefixq_and_encode(int reg_enc) { | |
4495 if (reg_enc < 8) { | |
4496 prefix(REX_W); | |
4497 } else { | |
4498 prefix(REX_WB); | |
4499 reg_enc -= 8; | |
4500 } | |
4501 return reg_enc; | |
4502 } | |
4503 | |
4504 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { | |
4505 if (dst_enc < 8) { | |
4506 if (src_enc >= 8) { | |
4507 prefix(REX_B); | |
4508 src_enc -= 8; | |
4509 } else if (byteinst && src_enc >= 4) { | |
4510 prefix(REX); | |
4511 } | |
4512 } else { | |
4513 if (src_enc < 8) { | |
4514 prefix(REX_R); | |
4515 } else { | |
4516 prefix(REX_RB); | |
4517 src_enc -= 8; | |
4518 } | |
4519 dst_enc -= 8; | |
4520 } | |
4521 return dst_enc << 3 | src_enc; | |
4522 } | |
4523 | |
4524 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { | |
4525 if (dst_enc < 8) { | |
4526 if (src_enc < 8) { | |
4527 prefix(REX_W); | |
4528 } else { | |
4529 prefix(REX_WB); | |
4530 src_enc -= 8; | |
4531 } | |
4532 } else { | |
4533 if (src_enc < 8) { | |
4534 prefix(REX_WR); | |
4535 } else { | |
4536 prefix(REX_WRB); | |
4537 src_enc -= 8; | |
4538 } | |
4539 dst_enc -= 8; | |
4540 } | |
4541 return dst_enc << 3 | src_enc; | |
4542 } | |
4543 | |
4544 void Assembler::prefix(Register reg) { | |
4545 if (reg->encoding() >= 8) { | |
4546 prefix(REX_B); | |
4547 } | |
4548 } | |
4549 | |
4550 void Assembler::prefix(Address adr) { | |
4551 if (adr.base_needs_rex()) { | |
4552 if (adr.index_needs_rex()) { | |
4553 prefix(REX_XB); | |
4554 } else { | |
4555 prefix(REX_B); | |
4556 } | |
4557 } else { | |
4558 if (adr.index_needs_rex()) { | |
4559 prefix(REX_X); | |
4560 } | |
4561 } | |
4562 } | |
4563 | |
4564 void Assembler::prefixq(Address adr) { | |
4565 if (adr.base_needs_rex()) { | |
4566 if (adr.index_needs_rex()) { | |
4567 prefix(REX_WXB); | |
4568 } else { | |
4569 prefix(REX_WB); | |
4570 } | |
4571 } else { | |
4572 if (adr.index_needs_rex()) { | |
4573 prefix(REX_WX); | |
4574 } else { | |
4575 prefix(REX_W); | |
4576 } | |
4577 } | |
4578 } | |
4579 | |
4580 | |
4581 void Assembler::prefix(Address adr, Register reg, bool byteinst) { | |
4582 if (reg->encoding() < 8) { | |
4583 if (adr.base_needs_rex()) { | |
4584 if (adr.index_needs_rex()) { | |
4585 prefix(REX_XB); | |
4586 } else { | |
4587 prefix(REX_B); | |
4588 } | |
4589 } else { | |
4590 if (adr.index_needs_rex()) { | |
4591 prefix(REX_X); | |
3855 | 4592 } else if (byteinst && reg->encoding() >= 4 ) { |
304 | 4593 prefix(REX); |
4594 } | |
4595 } | |
4596 } else { | |
4597 if (adr.base_needs_rex()) { | |
4598 if (adr.index_needs_rex()) { | |
4599 prefix(REX_RXB); | |
4600 } else { | |
4601 prefix(REX_RB); | |
4602 } | |
4603 } else { | |
4604 if (adr.index_needs_rex()) { | |
4605 prefix(REX_RX); | |
4606 } else { | |
4607 prefix(REX_R); | |
4608 } | |
4609 } | |
4610 } | |
4611 } | |
4612 | |
4613 void Assembler::prefixq(Address adr, Register src) { | |
4614 if (src->encoding() < 8) { | |
4615 if (adr.base_needs_rex()) { | |
4616 if (adr.index_needs_rex()) { | |
4617 prefix(REX_WXB); | |
4618 } else { | |
4619 prefix(REX_WB); | |
4620 } | |
4621 } else { | |
4622 if (adr.index_needs_rex()) { | |
4623 prefix(REX_WX); | |
4624 } else { | |
4625 prefix(REX_W); | |
4626 } | |
4627 } | |
4628 } else { | |
4629 if (adr.base_needs_rex()) { | |
4630 if (adr.index_needs_rex()) { | |
4631 prefix(REX_WRXB); | |
4632 } else { | |
4633 prefix(REX_WRB); | |
4634 } | |
4635 } else { | |
4636 if (adr.index_needs_rex()) { | |
4637 prefix(REX_WRX); | |
4638 } else { | |
4639 prefix(REX_WR); | |
4640 } | |
4641 } | |
4642 } | |
4643 } | |
4644 | |
4645 void Assembler::prefix(Address adr, XMMRegister reg) { | |
4646 if (reg->encoding() < 8) { | |
4647 if (adr.base_needs_rex()) { | |
4648 if (adr.index_needs_rex()) { | |
4649 prefix(REX_XB); | |
4650 } else { | |
4651 prefix(REX_B); | |
4652 } | |
4653 } else { | |
4654 if (adr.index_needs_rex()) { | |
4655 prefix(REX_X); | |
4656 } | |
4657 } | |
4658 } else { | |
4659 if (adr.base_needs_rex()) { | |
4660 if (adr.index_needs_rex()) { | |
4661 prefix(REX_RXB); | |
4662 } else { | |
4663 prefix(REX_RB); | |
4664 } | |
4665 } else { | |
4666 if (adr.index_needs_rex()) { | |
4667 prefix(REX_RX); | |
4668 } else { | |
4669 prefix(REX_R); | |
4670 } | |
4671 } | |
4672 } | |
4673 } | |
4674 | |
4759 | 4675 void Assembler::prefixq(Address adr, XMMRegister src) { |
4676 if (src->encoding() < 8) { | |
4677 if (adr.base_needs_rex()) { | |
4678 if (adr.index_needs_rex()) { | |
4679 prefix(REX_WXB); | |
4680 } else { | |
4681 prefix(REX_WB); | |
4682 } | |
4683 } else { | |
4684 if (adr.index_needs_rex()) { | |
4685 prefix(REX_WX); | |
4686 } else { | |
4687 prefix(REX_W); | |
4688 } | |
4689 } | |
4690 } else { | |
4691 if (adr.base_needs_rex()) { | |
4692 if (adr.index_needs_rex()) { | |
4693 prefix(REX_WRXB); | |
4694 } else { | |
4695 prefix(REX_WRB); | |
4696 } | |
4697 } else { | |
4698 if (adr.index_needs_rex()) { | |
4699 prefix(REX_WRX); | |
4700 } else { | |
4701 prefix(REX_WR); | |
4702 } | |
4703 } | |
4704 } | |
4705 } | |
4706 | |
304 | 4707 void Assembler::adcq(Register dst, int32_t imm32) { |
4708 (void) prefixq_and_encode(dst->encoding()); | |
4709 emit_arith(0x81, 0xD0, dst, imm32); | |
4710 } | |
4711 | |
4712 void Assembler::adcq(Register dst, Address src) { | |
4713 InstructionMark im(this); | |
4714 prefixq(src, dst); | |
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changeset
|
4715 emit_int8(0x13); |
304 | 4716 emit_operand(dst, src); |
4717 } | |
4718 | |
4719 void Assembler::adcq(Register dst, Register src) { | |
4720 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4721 emit_arith(0x13, 0xC0, dst, src); | |
4722 } | |
4723 | |
4724 void Assembler::addq(Address dst, int32_t imm32) { | |
4725 InstructionMark im(this); | |
4726 prefixq(dst); | |
4727 emit_arith_operand(0x81, rax, dst,imm32); | |
4728 } | |
4729 | |
4730 void Assembler::addq(Address dst, Register src) { | |
4731 InstructionMark im(this); | |
4732 prefixq(dst, src); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4733 emit_int8(0x01); |
304 | 4734 emit_operand(src, dst); |
4735 } | |
4736 | |
4737 void Assembler::addq(Register dst, int32_t imm32) { | |
4738 (void) prefixq_and_encode(dst->encoding()); | |
4739 emit_arith(0x81, 0xC0, dst, imm32); | |
4740 } | |
4741 | |
4742 void Assembler::addq(Register dst, Address src) { | |
4743 InstructionMark im(this); | |
4744 prefixq(src, dst); | |
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diff
changeset
|
4745 emit_int8(0x03); |
304 | 4746 emit_operand(dst, src); |
4747 } | |
4748 | |
4749 void Assembler::addq(Register dst, Register src) { | |
4750 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4751 emit_arith(0x03, 0xC0, dst, src); | |
4752 } | |
4753 | |
3783 | 4754 void Assembler::andq(Address dst, int32_t imm32) { |
4755 InstructionMark im(this); | |
4756 prefixq(dst); | |
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diff
changeset
|
4757 emit_int8((unsigned char)0x81); |
3783 | 4758 emit_operand(rsp, dst, 4); |
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
twisti
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7475
diff
changeset
|
4759 emit_int32(imm32); |
3783 | 4760 } |
4761 | |
304 | 4762 void Assembler::andq(Register dst, int32_t imm32) { |
4763 (void) prefixq_and_encode(dst->encoding()); | |
4764 emit_arith(0x81, 0xE0, dst, imm32); | |
4765 } | |
4766 | |
4767 void Assembler::andq(Register dst, Address src) { | |
4768 InstructionMark im(this); | |
4769 prefixq(src, dst); | |
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7427
diff
changeset
|
4770 emit_int8(0x23); |
304 | 4771 emit_operand(dst, src); |
4772 } | |
4773 | |
4774 void Assembler::andq(Register dst, Register src) { | |
4775 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4776 emit_arith(0x23, 0xC0, dst, src); | |
4777 } | |
4778 | |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4779 void Assembler::bsfq(Register dst, Register src) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
|
4780 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
7430
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diff
changeset
|
4781 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4782 emit_int8((unsigned char)0xBC); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4783 emit_int8((unsigned char)(0xC0 | encode)); |
775
93c14e5562c4
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diff
changeset
|
4784 } |
93c14e5562c4
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diff
changeset
|
4785 |
93c14e5562c4
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diff
changeset
|
4786 void Assembler::bsrq(Register dst, Register src) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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710
diff
changeset
|
4787 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
93c14e5562c4
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710
diff
changeset
|
4788 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
7430
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diff
changeset
|
4789 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4790 emit_int8((unsigned char)0xBD); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4791 emit_int8((unsigned char)(0xC0 | encode)); |
775
93c14e5562c4
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twisti
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710
diff
changeset
|
4792 } |
93c14e5562c4
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diff
changeset
|
4793 |
304 | 4794 void Assembler::bswapq(Register reg) { |
4795 int encode = prefixq_and_encode(reg->encoding()); | |
7430
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|
4796 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4797 emit_int8((unsigned char)(0xC8 | encode)); |
304 | 4798 } |
4799 | |
4800 void Assembler::cdqq() { | |
4801 prefix(REX_W); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4802 emit_int8((unsigned char)0x99); |
304 | 4803 } |
4804 | |
4805 void Assembler::clflush(Address adr) { | |
4806 prefix(adr); | |
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|
4807 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4808 emit_int8((unsigned char)0xAE); |
304 | 4809 emit_operand(rdi, adr); |
4810 } | |
4811 | |
4812 void Assembler::cmovq(Condition cc, Register dst, Register src) { | |
4813 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
7430
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7427
diff
changeset
|
4814 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4815 emit_int8(0x40 | cc); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4816 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4817 } |
4818 | |
4819 void Assembler::cmovq(Condition cc, Register dst, Address src) { | |
4820 InstructionMark im(this); | |
4821 prefixq(src, dst); | |
7430
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diff
changeset
|
4822 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4823 emit_int8(0x40 | cc); |
304 | 4824 emit_operand(dst, src); |
4825 } | |
4826 | |
4827 void Assembler::cmpq(Address dst, int32_t imm32) { | |
4828 InstructionMark im(this); | |
4829 prefixq(dst); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4830 emit_int8((unsigned char)0x81); |
304 | 4831 emit_operand(rdi, dst, 4); |
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
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7475
diff
changeset
|
4832 emit_int32(imm32); |
304 | 4833 } |
4834 | |
4835 void Assembler::cmpq(Register dst, int32_t imm32) { | |
4836 (void) prefixq_and_encode(dst->encoding()); | |
4837 emit_arith(0x81, 0xF8, dst, imm32); | |
4838 } | |
4839 | |
4840 void Assembler::cmpq(Address dst, Register src) { | |
4841 InstructionMark im(this); | |
4842 prefixq(dst, src); | |
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7427
diff
changeset
|
4843 emit_int8(0x3B); |
304 | 4844 emit_operand(src, dst); |
4845 } | |
4846 | |
4847 void Assembler::cmpq(Register dst, Register src) { | |
4848 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4849 emit_arith(0x3B, 0xC0, dst, src); | |
4850 } | |
4851 | |
4852 void Assembler::cmpq(Register dst, Address src) { | |
4853 InstructionMark im(this); | |
4854 prefixq(src, dst); | |
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diff
changeset
|
4855 emit_int8(0x3B); |
304 | 4856 emit_operand(dst, src); |
4857 } | |
4858 | |
4859 void Assembler::cmpxchgq(Register reg, Address adr) { | |
4860 InstructionMark im(this); | |
4861 prefixq(adr, reg); | |
7430
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7427
diff
changeset
|
4862 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4863 emit_int8((unsigned char)0xB1); |
304 | 4864 emit_operand(reg, adr); |
4865 } | |
4866 | |
4867 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | |
4868 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 4869 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2); |
7430
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diff
changeset
|
4870 emit_int8(0x2A); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4871 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4872 } |
4873 | |
4759 | 4874 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { |
4875 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4876 InstructionMark im(this); | |
4877 simd_prefix_q(dst, dst, src, VEX_SIMD_F2); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4878 emit_int8(0x2A); |
4759 | 4879 emit_operand(dst, src); |
4880 } | |
4881 | |
304 | 4882 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { |
4883 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4759 | 4884 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3); |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4885 emit_int8(0x2A); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4886 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4887 } |
4888 | |
4759 | 4889 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { |
4890 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4891 InstructionMark im(this); | |
4892 simd_prefix_q(dst, dst, src, VEX_SIMD_F3); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4893 emit_int8(0x2A); |
4759 | 4894 emit_operand(dst, src); |
4895 } | |
4896 | |
304 | 4897 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { |
4898 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 4899 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2); |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4900 emit_int8(0x2C); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4901 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4902 } |
4903 | |
4904 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | |
4905 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4759 | 4906 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3); |
7430
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|
4907 emit_int8(0x2C); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4908 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4909 } |
4910 | |
4911 void Assembler::decl(Register dst) { | |
4912 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
4913 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) | |
4914 int encode = prefix_and_encode(dst->encoding()); | |
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changeset
|
4915 emit_int8((unsigned char)0xFF); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4916 emit_int8((unsigned char)(0xC8 | encode)); |
304 | 4917 } |
4918 | |
4919 void Assembler::decq(Register dst) { | |
4920 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
4921 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
4922 int encode = prefixq_and_encode(dst->encoding()); | |
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changeset
|
4923 emit_int8((unsigned char)0xFF); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4924 emit_int8(0xC8 | encode); |
304 | 4925 } |
4926 | |
4927 void Assembler::decq(Address dst) { | |
4928 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
4929 InstructionMark im(this); | |
4930 prefixq(dst); | |
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changeset
|
4931 emit_int8((unsigned char)0xFF); |
304 | 4932 emit_operand(rcx, dst); |
4933 } | |
4934 | |
4935 void Assembler::fxrstor(Address src) { | |
4936 prefixq(src); | |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4937 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4938 emit_int8((unsigned char)0xAE); |
304 | 4939 emit_operand(as_Register(1), src); |
4940 } | |
4941 | |
4942 void Assembler::fxsave(Address dst) { | |
4943 prefixq(dst); | |
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changeset
|
4944 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4945 emit_int8((unsigned char)0xAE); |
304 | 4946 emit_operand(as_Register(0), dst); |
4947 } | |
4948 | |
4949 void Assembler::idivq(Register src) { | |
4950 int encode = prefixq_and_encode(src->encoding()); | |
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|
4951 emit_int8((unsigned char)0xF7); |
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changeset
|
4952 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 4953 } |
4954 | |
4955 void Assembler::imulq(Register dst, Register src) { | |
4956 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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|
4957 emit_int8(0x0F); |
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|
4958 emit_int8((unsigned char)0xAF); |
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changeset
|
4959 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4960 } |
4961 | |
4962 void Assembler::imulq(Register dst, Register src, int value) { | |
4963 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4964 if (is8bit(value)) { | |
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changeset
|
4965 emit_int8(0x6B); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4966 emit_int8((unsigned char)(0xC0 | encode)); |
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changeset
|
4967 emit_int8(value & 0xFF); |
304 | 4968 } else { |
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changeset
|
4969 emit_int8(0x69); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4970 emit_int8((unsigned char)(0xC0 | encode)); |
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
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7475
diff
changeset
|
4971 emit_int32(value); |
304 | 4972 } |
4973 } | |
4974 | |
4975 void Assembler::incl(Register dst) { | |
4976 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
4977 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
4978 int encode = prefix_and_encode(dst->encoding()); | |
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changeset
|
4979 emit_int8((unsigned char)0xFF); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4980 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4981 } |
4982 | |
4983 void Assembler::incq(Register dst) { | |
4984 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
4985 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
4986 int encode = prefixq_and_encode(dst->encoding()); | |
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changeset
|
4987 emit_int8((unsigned char)0xFF); |
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changeset
|
4988 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4989 } |
4990 | |
4991 void Assembler::incq(Address dst) { | |
4992 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
4993 InstructionMark im(this); | |
4994 prefixq(dst); | |
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|
4995 emit_int8((unsigned char)0xFF); |
304 | 4996 emit_operand(rax, dst); |
4997 } | |
4998 | |
4999 void Assembler::lea(Register dst, Address src) { | |
5000 leaq(dst, src); | |
5001 } | |
5002 | |
5003 void Assembler::leaq(Register dst, Address src) { | |
5004 InstructionMark im(this); | |
5005 prefixq(src, dst); | |
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changeset
|
5006 emit_int8((unsigned char)0x8D); |
304 | 5007 emit_operand(dst, src); |
5008 } | |
5009 | |
5010 void Assembler::mov64(Register dst, int64_t imm64) { | |
5011 InstructionMark im(this); | |
5012 int encode = prefixq_and_encode(dst->encoding()); | |
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changeset
|
5013 emit_int8((unsigned char)(0xB8 | encode)); |
7198
6ab62ad83507
8003195: AbstractAssembler should not store code pointers but use the CodeSection directly
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6894
diff
changeset
|
5014 emit_int64(imm64); |
304 | 5015 } |
5016 | |
5017 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { | |
5018 InstructionMark im(this); | |
5019 int encode = prefixq_and_encode(dst->encoding()); | |
7430
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changeset
|
5020 emit_int8(0xB8 | encode); |
304 | 5021 emit_data64(imm64, rspec); |
5022 } | |
5023 | |
642
660978a2a31a
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|
5024 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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changeset
|
5025 InstructionMark im(this); |
660978a2a31a
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changeset
|
5026 int encode = prefix_and_encode(dst->encoding()); |
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changeset
|
5027 emit_int8((unsigned char)(0xB8 | encode)); |
642
660978a2a31a
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624
diff
changeset
|
5028 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
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624
diff
changeset
|
5029 } |
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diff
changeset
|
5030 |
660978a2a31a
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diff
changeset
|
5031 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
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diff
changeset
|
5032 InstructionMark im(this); |
660978a2a31a
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diff
changeset
|
5033 prefix(dst); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
5034 emit_int8((unsigned char)0xC7); |
642
660978a2a31a
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624
diff
changeset
|
5035 emit_operand(rax, dst, 4); |
660978a2a31a
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kvn
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diff
changeset
|
5036 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
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624
diff
changeset
|
5037 } |
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624
diff
changeset
|
5038 |
660978a2a31a
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diff
changeset
|
5039 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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diff
changeset
|
5040 InstructionMark im(this); |
660978a2a31a
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624
diff
changeset
|
5041 int encode = prefix_and_encode(src1->encoding()); |
7430
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7427
diff
changeset
|
5042 emit_int8((unsigned char)0x81); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5043 emit_int8((unsigned char)(0xF8 | encode)); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
5044 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
5045 } |
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624
diff
changeset
|
5046 |
660978a2a31a
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diff
changeset
|
5047 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
5048 InstructionMark im(this); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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parents:
624
diff
changeset
|
5049 prefix(src1); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5050 emit_int8((unsigned char)0x81); |
642
660978a2a31a
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624
diff
changeset
|
5051 emit_operand(rax, src1, 4); |
660978a2a31a
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diff
changeset
|
5052 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
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624
diff
changeset
|
5053 } |
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diff
changeset
|
5054 |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
5055 void Assembler::lzcntq(Register dst, Register src) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
5056 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5057 emit_int8((unsigned char)0xF3); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
5058 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
7430
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changeset
|
5059 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5060 emit_int8((unsigned char)0xBD); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5061 emit_int8((unsigned char)(0xC0 | encode)); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
5062 } |
93c14e5562c4
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twisti
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710
diff
changeset
|
5063 |
304 | 5064 void Assembler::movdq(XMMRegister dst, Register src) { |
5065 // table D-1 says MMX/SSE2 | |
4759 | 5066 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
5067 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66); | |
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7427
diff
changeset
|
5068 emit_int8(0x6E); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5069 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5070 } |
5071 | |
5072 void Assembler::movdq(Register dst, XMMRegister src) { | |
5073 // table D-1 says MMX/SSE2 | |
4759 | 5074 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
304 | 5075 // swap src/dst to get correct prefix |
4759 | 5076 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66); |
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7427
diff
changeset
|
5077 emit_int8(0x7E); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5078 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5079 } |
5080 | |
5081 void Assembler::movq(Register dst, Register src) { | |
5082 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
7430
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changeset
|
5083 emit_int8((unsigned char)0x8B); |
d02120b7a34f
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diff
changeset
|
5084 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5085 } |
5086 | |
5087 void Assembler::movq(Register dst, Address src) { | |
5088 InstructionMark im(this); | |
5089 prefixq(src, dst); | |
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diff
changeset
|
5090 emit_int8((unsigned char)0x8B); |
304 | 5091 emit_operand(dst, src); |
5092 } | |
5093 | |
5094 void Assembler::movq(Address dst, Register src) { | |
5095 InstructionMark im(this); | |
5096 prefixq(dst, src); | |
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diff
changeset
|
5097 emit_int8((unsigned char)0x89); |
304 | 5098 emit_operand(src, dst); |
5099 } | |
5100 | |
624 | 5101 void Assembler::movsbq(Register dst, Address src) { |
5102 InstructionMark im(this); | |
5103 prefixq(src, dst); | |
7430
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diff
changeset
|
5104 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5105 emit_int8((unsigned char)0xBE); |
624 | 5106 emit_operand(dst, src); |
5107 } | |
5108 | |
5109 void Assembler::movsbq(Register dst, Register src) { | |
5110 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
7430
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7427
diff
changeset
|
5111 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5112 emit_int8((unsigned char)0xBE); |
d02120b7a34f
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changeset
|
5113 emit_int8((unsigned char)(0xC0 | encode)); |
624 | 5114 } |
5115 | |
304 | 5116 void Assembler::movslq(Register dst, int32_t imm32) { |
5117 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) | |
5118 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) | |
5119 // as a result we shouldn't use until tested at runtime... | |
5120 ShouldNotReachHere(); | |
5121 InstructionMark im(this); | |
5122 int encode = prefixq_and_encode(dst->encoding()); | |
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5123 emit_int8((unsigned char)(0xC7 | encode)); |
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5124 emit_int32(imm32); |
304 | 5125 } |
5126 | |
5127 void Assembler::movslq(Address dst, int32_t imm32) { | |
5128 assert(is_simm32(imm32), "lost bits"); | |
5129 InstructionMark im(this); | |
5130 prefixq(dst); | |
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5131 emit_int8((unsigned char)0xC7); |
304 | 5132 emit_operand(rax, dst, 4); |
7476
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5133 emit_int32(imm32); |
304 | 5134 } |
5135 | |
5136 void Assembler::movslq(Register dst, Address src) { | |
5137 InstructionMark im(this); | |
5138 prefixq(src, dst); | |
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5139 emit_int8(0x63); |
304 | 5140 emit_operand(dst, src); |
5141 } | |
5142 | |
5143 void Assembler::movslq(Register dst, Register src) { | |
5144 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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5145 emit_int8(0x63); |
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5146 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5147 } |
5148 | |
624 | 5149 void Assembler::movswq(Register dst, Address src) { |
5150 InstructionMark im(this); | |
5151 prefixq(src, dst); | |
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5152 emit_int8(0x0F); |
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5153 emit_int8((unsigned char)0xBF); |
624 | 5154 emit_operand(dst, src); |
5155 } | |
5156 | |
5157 void Assembler::movswq(Register dst, Register src) { | |
5158 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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5159 emit_int8((unsigned char)0x0F); |
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5160 emit_int8((unsigned char)0xBF); |
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5161 emit_int8((unsigned char)(0xC0 | encode)); |
624 | 5162 } |
5163 | |
5164 void Assembler::movzbq(Register dst, Address src) { | |
5165 InstructionMark im(this); | |
5166 prefixq(src, dst); | |
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5167 emit_int8((unsigned char)0x0F); |
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5168 emit_int8((unsigned char)0xB6); |
624 | 5169 emit_operand(dst, src); |
5170 } | |
5171 | |
5172 void Assembler::movzbq(Register dst, Register src) { | |
5173 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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5174 emit_int8(0x0F); |
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5175 emit_int8((unsigned char)0xB6); |
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5176 emit_int8(0xC0 | encode); |
624 | 5177 } |
5178 | |
5179 void Assembler::movzwq(Register dst, Address src) { | |
5180 InstructionMark im(this); | |
5181 prefixq(src, dst); | |
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5182 emit_int8((unsigned char)0x0F); |
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5183 emit_int8((unsigned char)0xB7); |
624 | 5184 emit_operand(dst, src); |
5185 } | |
5186 | |
5187 void Assembler::movzwq(Register dst, Register src) { | |
5188 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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5189 emit_int8((unsigned char)0x0F); |
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5190 emit_int8((unsigned char)0xB7); |
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5191 emit_int8((unsigned char)(0xC0 | encode)); |
624 | 5192 } |
5193 | |
304 | 5194 void Assembler::negq(Register dst) { |
5195 int encode = prefixq_and_encode(dst->encoding()); | |
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5196 emit_int8((unsigned char)0xF7); |
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5197 emit_int8((unsigned char)(0xD8 | encode)); |
304 | 5198 } |
5199 | |
5200 void Assembler::notq(Register dst) { | |
5201 int encode = prefixq_and_encode(dst->encoding()); | |
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5202 emit_int8((unsigned char)0xF7); |
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5203 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 5204 } |
5205 | |
5206 void Assembler::orq(Address dst, int32_t imm32) { | |
5207 InstructionMark im(this); | |
5208 prefixq(dst); | |
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5209 emit_int8((unsigned char)0x81); |
304 | 5210 emit_operand(rcx, dst, 4); |
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5211 emit_int32(imm32); |
304 | 5212 } |
5213 | |
5214 void Assembler::orq(Register dst, int32_t imm32) { | |
5215 (void) prefixq_and_encode(dst->encoding()); | |
5216 emit_arith(0x81, 0xC8, dst, imm32); | |
5217 } | |
5218 | |
5219 void Assembler::orq(Register dst, Address src) { | |
5220 InstructionMark im(this); | |
5221 prefixq(src, dst); | |
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5222 emit_int8(0x0B); |
304 | 5223 emit_operand(dst, src); |
5224 } | |
5225 | |
5226 void Assembler::orq(Register dst, Register src) { | |
5227 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5228 emit_arith(0x0B, 0xC0, dst, src); | |
5229 } | |
5230 | |
5231 void Assembler::popa() { // 64bit | |
5232 movq(r15, Address(rsp, 0)); | |
5233 movq(r14, Address(rsp, wordSize)); | |
5234 movq(r13, Address(rsp, 2 * wordSize)); | |
5235 movq(r12, Address(rsp, 3 * wordSize)); | |
5236 movq(r11, Address(rsp, 4 * wordSize)); | |
5237 movq(r10, Address(rsp, 5 * wordSize)); | |
5238 movq(r9, Address(rsp, 6 * wordSize)); | |
5239 movq(r8, Address(rsp, 7 * wordSize)); | |
5240 movq(rdi, Address(rsp, 8 * wordSize)); | |
5241 movq(rsi, Address(rsp, 9 * wordSize)); | |
5242 movq(rbp, Address(rsp, 10 * wordSize)); | |
5243 // skip rsp | |
5244 movq(rbx, Address(rsp, 12 * wordSize)); | |
5245 movq(rdx, Address(rsp, 13 * wordSize)); | |
5246 movq(rcx, Address(rsp, 14 * wordSize)); | |
5247 movq(rax, Address(rsp, 15 * wordSize)); | |
5248 | |
5249 addq(rsp, 16 * wordSize); | |
5250 } | |
5251 | |
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5252 void Assembler::popcntq(Register dst, Address src) { |
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5253 assert(VM_Version::supports_popcnt(), "must support"); |
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5254 InstructionMark im(this); |
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5255 emit_int8((unsigned char)0xF3); |
643
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5256 prefixq(src, dst); |
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5257 emit_int8((unsigned char)0x0F); |
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5258 emit_int8((unsigned char)0xB8); |
643
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|
5259 emit_operand(dst, src); |
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|
5260 } |
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|
5261 |
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5262 void Assembler::popcntq(Register dst, Register src) { |
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|
5263 assert(VM_Version::supports_popcnt(), "must support"); |
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|
5264 emit_int8((unsigned char)0xF3); |
643
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|
5265 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
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|
5266 emit_int8((unsigned char)0x0F); |
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|
5267 emit_int8((unsigned char)0xB8); |
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|
5268 emit_int8((unsigned char)(0xC0 | encode)); |
643
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|
5269 } |
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5270 |
304 | 5271 void Assembler::popq(Address dst) { |
5272 InstructionMark im(this); | |
5273 prefixq(dst); | |
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|
5274 emit_int8((unsigned char)0x8F); |
304 | 5275 emit_operand(rax, dst); |
5276 } | |
5277 | |
5278 void Assembler::pusha() { // 64bit | |
5279 // we have to store original rsp. ABI says that 128 bytes | |
5280 // below rsp are local scratch. | |
5281 movq(Address(rsp, -5 * wordSize), rsp); | |
5282 | |
5283 subq(rsp, 16 * wordSize); | |
5284 | |
5285 movq(Address(rsp, 15 * wordSize), rax); | |
5286 movq(Address(rsp, 14 * wordSize), rcx); | |
5287 movq(Address(rsp, 13 * wordSize), rdx); | |
5288 movq(Address(rsp, 12 * wordSize), rbx); | |
5289 // skip rsp | |
5290 movq(Address(rsp, 10 * wordSize), rbp); | |
5291 movq(Address(rsp, 9 * wordSize), rsi); | |
5292 movq(Address(rsp, 8 * wordSize), rdi); | |
5293 movq(Address(rsp, 7 * wordSize), r8); | |
5294 movq(Address(rsp, 6 * wordSize), r9); | |
5295 movq(Address(rsp, 5 * wordSize), r10); | |
5296 movq(Address(rsp, 4 * wordSize), r11); | |
5297 movq(Address(rsp, 3 * wordSize), r12); | |
5298 movq(Address(rsp, 2 * wordSize), r13); | |
5299 movq(Address(rsp, wordSize), r14); | |
5300 movq(Address(rsp, 0), r15); | |
5301 } | |
5302 | |
5303 void Assembler::pushq(Address src) { | |
5304 InstructionMark im(this); | |
5305 prefixq(src); | |
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|
5306 emit_int8((unsigned char)0xFF); |
304 | 5307 emit_operand(rsi, src); |
5308 } | |
5309 | |
5310 void Assembler::rclq(Register dst, int imm8) { | |
5311 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5312 int encode = prefixq_and_encode(dst->encoding()); | |
5313 if (imm8 == 1) { | |
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5314 emit_int8((unsigned char)0xD1); |
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5315 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 5316 } else { |
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5317 emit_int8((unsigned char)0xC1); |
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5318 emit_int8((unsigned char)(0xD0 | encode)); |
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|
5319 emit_int8(imm8); |
304 | 5320 } |
5321 } | |
5322 void Assembler::sarq(Register dst, int imm8) { | |
5323 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5324 int encode = prefixq_and_encode(dst->encoding()); | |
5325 if (imm8 == 1) { | |
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|
5326 emit_int8((unsigned char)0xD1); |
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5327 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 5328 } else { |
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|
5329 emit_int8((unsigned char)0xC1); |
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|
5330 emit_int8((unsigned char)(0xF8 | encode)); |
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|
5331 emit_int8(imm8); |
304 | 5332 } |
5333 } | |
5334 | |
5335 void Assembler::sarq(Register dst) { | |
5336 int encode = prefixq_and_encode(dst->encoding()); | |
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|
5337 emit_int8((unsigned char)0xD3); |
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|
5338 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 5339 } |
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|
5340 |
304 | 5341 void Assembler::sbbq(Address dst, int32_t imm32) { |
5342 InstructionMark im(this); | |
5343 prefixq(dst); | |
5344 emit_arith_operand(0x81, rbx, dst, imm32); | |
5345 } | |
5346 | |
5347 void Assembler::sbbq(Register dst, int32_t imm32) { | |
5348 (void) prefixq_and_encode(dst->encoding()); | |
5349 emit_arith(0x81, 0xD8, dst, imm32); | |
5350 } | |
5351 | |
5352 void Assembler::sbbq(Register dst, Address src) { | |
5353 InstructionMark im(this); | |
5354 prefixq(src, dst); | |
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|
5355 emit_int8(0x1B); |
304 | 5356 emit_operand(dst, src); |
5357 } | |
5358 | |
5359 void Assembler::sbbq(Register dst, Register src) { | |
5360 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5361 emit_arith(0x1B, 0xC0, dst, src); | |
5362 } | |
5363 | |
5364 void Assembler::shlq(Register dst, int imm8) { | |
5365 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5366 int encode = prefixq_and_encode(dst->encoding()); | |
5367 if (imm8 == 1) { | |
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|
5368 emit_int8((unsigned char)0xD1); |
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|
5369 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 5370 } else { |
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|
5371 emit_int8((unsigned char)0xC1); |
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|
5372 emit_int8((unsigned char)(0xE0 | encode)); |
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changeset
|
5373 emit_int8(imm8); |
304 | 5374 } |
5375 } | |
5376 | |
5377 void Assembler::shlq(Register dst) { | |
5378 int encode = prefixq_and_encode(dst->encoding()); | |
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5379 emit_int8((unsigned char)0xD3); |
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5380 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 5381 } |
5382 | |
5383 void Assembler::shrq(Register dst, int imm8) { | |
5384 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5385 int encode = prefixq_and_encode(dst->encoding()); | |
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5386 emit_int8((unsigned char)0xC1); |
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5387 emit_int8((unsigned char)(0xE8 | encode)); |
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5388 emit_int8(imm8); |
304 | 5389 } |
5390 | |
5391 void Assembler::shrq(Register dst) { | |
5392 int encode = prefixq_and_encode(dst->encoding()); | |
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5393 emit_int8((unsigned char)0xD3); |
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5394 emit_int8(0xE8 | encode); |
304 | 5395 } |
5396 | |
5397 void Assembler::subq(Address dst, int32_t imm32) { | |
5398 InstructionMark im(this); | |
5399 prefixq(dst); | |
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5400 emit_arith_operand(0x81, rbp, dst, imm32); |
304 | 5401 } |
5402 | |
5403 void Assembler::subq(Address dst, Register src) { | |
5404 InstructionMark im(this); | |
5405 prefixq(dst, src); | |
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5406 emit_int8(0x29); |
304 | 5407 emit_operand(src, dst); |
5408 } | |
5409 | |
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5410 void Assembler::subq(Register dst, int32_t imm32) { |
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5411 (void) prefixq_and_encode(dst->encoding()); |
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5412 emit_arith(0x81, 0xE8, dst, imm32); |
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|
5413 } |
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5414 |
4947
fd8114661503
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|
5415 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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5416 void Assembler::subq_imm32(Register dst, int32_t imm32) { |
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5417 (void) prefixq_and_encode(dst->encoding()); |
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|
5418 emit_arith_imm32(0x81, 0xE8, dst, imm32); |
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|
5419 } |
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5420 |
304 | 5421 void Assembler::subq(Register dst, Address src) { |
5422 InstructionMark im(this); | |
5423 prefixq(src, dst); | |
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5424 emit_int8(0x2B); |
304 | 5425 emit_operand(dst, src); |
5426 } | |
5427 | |
5428 void Assembler::subq(Register dst, Register src) { | |
5429 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5430 emit_arith(0x2B, 0xC0, dst, src); | |
5431 } | |
5432 | |
5433 void Assembler::testq(Register dst, int32_t imm32) { | |
5434 // not using emit_arith because test | |
5435 // doesn't support sign-extension of | |
5436 // 8bit operands | |
5437 int encode = dst->encoding(); | |
5438 if (encode == 0) { | |
5439 prefix(REX_W); | |
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|
5440 emit_int8((unsigned char)0xA9); |
304 | 5441 } else { |
5442 encode = prefixq_and_encode(encode); | |
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|
5443 emit_int8((unsigned char)0xF7); |
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5444 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5445 } |
7476
ffa87474d7a4
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7475
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|
5446 emit_int32(imm32); |
304 | 5447 } |
5448 | |
5449 void Assembler::testq(Register dst, Register src) { | |
5450 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5451 emit_arith(0x85, 0xC0, dst, src); | |
5452 } | |
5453 | |
5454 void Assembler::xaddq(Address dst, Register src) { | |
5455 InstructionMark im(this); | |
5456 prefixq(dst, src); | |
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|
5457 emit_int8(0x0F); |
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|
5458 emit_int8((unsigned char)0xC1); |
304 | 5459 emit_operand(src, dst); |
5460 } | |
5461 | |
5462 void Assembler::xchgq(Register dst, Address src) { | |
5463 InstructionMark im(this); | |
5464 prefixq(src, dst); | |
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|
5465 emit_int8((unsigned char)0x87); |
304 | 5466 emit_operand(dst, src); |
5467 } | |
5468 | |
5469 void Assembler::xchgq(Register dst, Register src) { | |
5470 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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|
5471 emit_int8((unsigned char)0x87); |
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|
5472 emit_int8((unsigned char)(0xc0 | encode)); |
304 | 5473 } |
5474 | |
5475 void Assembler::xorq(Register dst, Register src) { | |
5476 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5477 emit_arith(0x33, 0xC0, dst, src); | |
5478 } | |
5479 | |
5480 void Assembler::xorq(Register dst, Address src) { | |
5481 InstructionMark im(this); | |
5482 prefixq(src, dst); | |
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|
5483 emit_int8(0x33); |
304 | 5484 emit_operand(dst, src); |
5485 } | |
5486 | |
5487 #endif // !LP64 |