truffle: src/cpu/x86/vm/x86

annotate src/cpu/x86/vm/x86_32.ad @ 17524:89152779163c

Merge with jdk8-b132

author	Gilles Duboscq <duboscq@ssw.jku.at>
date	Wed, 15 Oct 2014 11:59:32 +0200
parents	4ca6dc0799b6
children	52b4284cb496

rev	line source
0 a61af66fc99e Initial load duke parents: diff changeset	1 //
9154 886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
0 a61af66fc99e Initial load duke parents: diff changeset	3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
a61af66fc99e Initial load duke parents: diff changeset	4 //
a61af66fc99e Initial load duke parents: diff changeset	5 // This code is free software; you can redistribute it and/or modify it
a61af66fc99e Initial load duke parents: diff changeset	6 // under the terms of the GNU General Public License version 2 only, as
a61af66fc99e Initial load duke parents: diff changeset	7 // published by the Free Software Foundation.
a61af66fc99e Initial load duke parents: diff changeset	8 //
a61af66fc99e Initial load duke parents: diff changeset	9 // This code is distributed in the hope that it will be useful, but WITHOUT
a61af66fc99e Initial load duke parents: diff changeset	10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
a61af66fc99e Initial load duke parents: diff changeset	11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
a61af66fc99e Initial load duke parents: diff changeset	12 // version 2 for more details (a copy is included in the LICENSE file that
a61af66fc99e Initial load duke parents: diff changeset	13 // accompanied this code).
a61af66fc99e Initial load duke parents: diff changeset	14 //
a61af66fc99e Initial load duke parents: diff changeset	15 // You should have received a copy of the GNU General Public License version
a61af66fc99e Initial load duke parents: diff changeset	16 // 2 along with this work; if not, write to the Free Software Foundation,
a61af66fc99e Initial load duke parents: diff changeset	17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
a61af66fc99e Initial load duke parents: diff changeset	18 //
1552 c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories trims parents: 1396 diff changeset	19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories trims parents: 1396 diff changeset	20 // or visit www.oracle.com if you need additional information or have any
c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories trims parents: 1396 diff changeset	21 // questions.
0 a61af66fc99e Initial load duke parents: diff changeset	22 //
a61af66fc99e Initial load duke parents: diff changeset	23 //
a61af66fc99e Initial load duke parents: diff changeset	24
a61af66fc99e Initial load duke parents: diff changeset	25 // X86 Architecture Description File
a61af66fc99e Initial load duke parents: diff changeset	26
a61af66fc99e Initial load duke parents: diff changeset	27 //----------REGISTER DEFINITION BLOCK------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	28 // This information is used by the matcher and the register allocator to
a61af66fc99e Initial load duke parents: diff changeset	29 // describe individual registers and classes of registers within the target
a61af66fc99e Initial load duke parents: diff changeset	30 // archtecture.
a61af66fc99e Initial load duke parents: diff changeset	31
a61af66fc99e Initial load duke parents: diff changeset	32 register %{
a61af66fc99e Initial load duke parents: diff changeset	33 //----------Architecture Description Register Definitions----------------------
a61af66fc99e Initial load duke parents: diff changeset	34 // General Registers
a61af66fc99e Initial load duke parents: diff changeset	35 // "reg_def" name ( register save type, C convention save type,
a61af66fc99e Initial load duke parents: diff changeset	36 // ideal register type, encoding );
a61af66fc99e Initial load duke parents: diff changeset	37 // Register Save Types:
a61af66fc99e Initial load duke parents: diff changeset	38 //
a61af66fc99e Initial load duke parents: diff changeset	39 // NS = No-Save: The register allocator assumes that these registers
a61af66fc99e Initial load duke parents: diff changeset	40 // can be used without saving upon entry to the method, &
a61af66fc99e Initial load duke parents: diff changeset	41 // that they do not need to be saved at call sites.
a61af66fc99e Initial load duke parents: diff changeset	42 //
a61af66fc99e Initial load duke parents: diff changeset	43 // SOC = Save-On-Call: The register allocator assumes that these registers
a61af66fc99e Initial load duke parents: diff changeset	44 // can be used without saving upon entry to the method,
a61af66fc99e Initial load duke parents: diff changeset	45 // but that they must be saved at call sites.
a61af66fc99e Initial load duke parents: diff changeset	46 //
a61af66fc99e Initial load duke parents: diff changeset	47 // SOE = Save-On-Entry: The register allocator assumes that these registers
a61af66fc99e Initial load duke parents: diff changeset	48 // must be saved before using them upon entry to the
a61af66fc99e Initial load duke parents: diff changeset	49 // method, but they do not need to be saved at call
a61af66fc99e Initial load duke parents: diff changeset	50 // sites.
a61af66fc99e Initial load duke parents: diff changeset	51 //
a61af66fc99e Initial load duke parents: diff changeset	52 // AS = Always-Save: The register allocator assumes that these registers
a61af66fc99e Initial load duke parents: diff changeset	53 // must be saved before using them upon entry to the
a61af66fc99e Initial load duke parents: diff changeset	54 // method, & that they must be saved at call sites.
a61af66fc99e Initial load duke parents: diff changeset	55 //
a61af66fc99e Initial load duke parents: diff changeset	56 // Ideal Register Type is used to determine how to save & restore a
a61af66fc99e Initial load duke parents: diff changeset	57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
a61af66fc99e Initial load duke parents: diff changeset	58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
a61af66fc99e Initial load duke parents: diff changeset	59 //
a61af66fc99e Initial load duke parents: diff changeset	60 // The encoding number is the actual bit-pattern placed into the opcodes.
a61af66fc99e Initial load duke parents: diff changeset	61
a61af66fc99e Initial load duke parents: diff changeset	62 // General Registers
a61af66fc99e Initial load duke parents: diff changeset	63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
a61af66fc99e Initial load duke parents: diff changeset	64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
a61af66fc99e Initial load duke parents: diff changeset	65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
a61af66fc99e Initial load duke parents: diff changeset	66
a61af66fc99e Initial load duke parents: diff changeset	67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
a61af66fc99e Initial load duke parents: diff changeset	68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
a61af66fc99e Initial load duke parents: diff changeset	69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
a61af66fc99e Initial load duke parents: diff changeset	70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
a61af66fc99e Initial load duke parents: diff changeset	71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
a61af66fc99e Initial load duke parents: diff changeset	72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
a61af66fc99e Initial load duke parents: diff changeset	73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
a61af66fc99e Initial load duke parents: diff changeset	74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
a61af66fc99e Initial load duke parents: diff changeset	75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
a61af66fc99e Initial load duke parents: diff changeset	76
a61af66fc99e Initial load duke parents: diff changeset	77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
a61af66fc99e Initial load duke parents: diff changeset	78 // allocator, and only shows up in the encodings.
a61af66fc99e Initial load duke parents: diff changeset	79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
a61af66fc99e Initial load duke parents: diff changeset	80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
a61af66fc99e Initial load duke parents: diff changeset	81 // Ok so here's the trick FPR1 is really st(0) except in the midst
a61af66fc99e Initial load duke parents: diff changeset	82 // of emission of assembly for a machnode. During the emission the fpu stack
a61af66fc99e Initial load duke parents: diff changeset	83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
a61af66fc99e Initial load duke parents: diff changeset	84 // the stack will not have this element so FPR1 == st(0) from the
a61af66fc99e Initial load duke parents: diff changeset	85 // oopMap viewpoint. This same weirdness with numbering causes
a61af66fc99e Initial load duke parents: diff changeset	86 // instruction encoding to have to play games with the register
a61af66fc99e Initial load duke parents: diff changeset	87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
a61af66fc99e Initial load duke parents: diff changeset	88 // where it does flt->flt moves to see an example
a61af66fc99e Initial load duke parents: diff changeset	89 //
a61af66fc99e Initial load duke parents: diff changeset	90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
a61af66fc99e Initial load duke parents: diff changeset	91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
a61af66fc99e Initial load duke parents: diff changeset	92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
a61af66fc99e Initial load duke parents: diff changeset	93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
a61af66fc99e Initial load duke parents: diff changeset	94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
a61af66fc99e Initial load duke parents: diff changeset	95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
a61af66fc99e Initial load duke parents: diff changeset	96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
a61af66fc99e Initial load duke parents: diff changeset	97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
a61af66fc99e Initial load duke parents: diff changeset	98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
a61af66fc99e Initial load duke parents: diff changeset	99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
a61af66fc99e Initial load duke parents: diff changeset	100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
a61af66fc99e Initial load duke parents: diff changeset	101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
a61af66fc99e Initial load duke parents: diff changeset	102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
a61af66fc99e Initial load duke parents: diff changeset	103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
a61af66fc99e Initial load duke parents: diff changeset	104
a61af66fc99e Initial load duke parents: diff changeset	105 // Specify priority of register selection within phases of register
a61af66fc99e Initial load duke parents: diff changeset	106 // allocation. Highest priority is first. A useful heuristic is to
a61af66fc99e Initial load duke parents: diff changeset	107 // give registers a low priority when they are required by machine
a61af66fc99e Initial load duke parents: diff changeset	108 // instructions, like EAX and EDX. Registers which are used as
605 98cb887364d3 6810672: Comment typos twisti parents: 570 diff changeset	109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
0 a61af66fc99e Initial load duke parents: diff changeset	110 // For the Intel integer registers, the equivalent Long pairs are
a61af66fc99e Initial load duke parents: diff changeset	111 // EDX:EAX, EBX:ECX, and EDI:EBP.
a61af66fc99e Initial load duke parents: diff changeset	112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
a61af66fc99e Initial load duke parents: diff changeset	113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
a61af66fc99e Initial load duke parents: diff changeset	114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
a61af66fc99e Initial load duke parents: diff changeset	115 FPR6L, FPR6H, FPR7L, FPR7H );
a61af66fc99e Initial load duke parents: diff changeset	116
a61af66fc99e Initial load duke parents: diff changeset	117
a61af66fc99e Initial load duke parents: diff changeset	118 //----------Architecture Description Register Classes--------------------------
a61af66fc99e Initial load duke parents: diff changeset	119 // Several register classes are automatically defined based upon information in
a61af66fc99e Initial load duke parents: diff changeset	120 // this architecture description.
a61af66fc99e Initial load duke parents: diff changeset	121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
a61af66fc99e Initial load duke parents: diff changeset	122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
a61af66fc99e Initial load duke parents: diff changeset	123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
a61af66fc99e Initial load duke parents: diff changeset	124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
a61af66fc99e Initial load duke parents: diff changeset	125 //
a61af66fc99e Initial load duke parents: diff changeset	126 // Class for all registers
a61af66fc99e Initial load duke parents: diff changeset	127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
a61af66fc99e Initial load duke parents: diff changeset	128 // Class for general registers
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
0 a61af66fc99e Initial load duke parents: diff changeset	130 // Class for general registers which may be used for implicit null checks on win95
a61af66fc99e Initial load duke parents: diff changeset	131 // Also safe for use by tailjump. We don't want to allocate in rbp,
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
0 a61af66fc99e Initial load duke parents: diff changeset	133 // Class of "X" registers
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
0 a61af66fc99e Initial load duke parents: diff changeset	135 // Class of registers that can appear in an address with no offset.
a61af66fc99e Initial load duke parents: diff changeset	136 // EBP and ESP require an extra instruction byte for zero offset.
a61af66fc99e Initial load duke parents: diff changeset	137 // Used in fast-unlock
a61af66fc99e Initial load duke parents: diff changeset	138 reg_class p_reg(EDX, EDI, ESI, EBX);
a61af66fc99e Initial load duke parents: diff changeset	139 // Class for general registers not including ECX
a61af66fc99e Initial load duke parents: diff changeset	140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
a61af66fc99e Initial load duke parents: diff changeset	141 // Class for general registers not including EAX
a61af66fc99e Initial load duke parents: diff changeset	142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
a61af66fc99e Initial load duke parents: diff changeset	143 // Class for general registers not including EAX or EBX.
a61af66fc99e Initial load duke parents: diff changeset	144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
a61af66fc99e Initial load duke parents: diff changeset	145 // Class of EAX (for multiply and divide operations)
a61af66fc99e Initial load duke parents: diff changeset	146 reg_class eax_reg(EAX);
a61af66fc99e Initial load duke parents: diff changeset	147 // Class of EBX (for atomic add)
a61af66fc99e Initial load duke parents: diff changeset	148 reg_class ebx_reg(EBX);
a61af66fc99e Initial load duke parents: diff changeset	149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
a61af66fc99e Initial load duke parents: diff changeset	150 reg_class ecx_reg(ECX);
a61af66fc99e Initial load duke parents: diff changeset	151 // Class of EDX (for multiply and divide operations)
a61af66fc99e Initial load duke parents: diff changeset	152 reg_class edx_reg(EDX);
a61af66fc99e Initial load duke parents: diff changeset	153 // Class of EDI (for synchronization)
a61af66fc99e Initial load duke parents: diff changeset	154 reg_class edi_reg(EDI);
a61af66fc99e Initial load duke parents: diff changeset	155 // Class of ESI (for synchronization)
a61af66fc99e Initial load duke parents: diff changeset	156 reg_class esi_reg(ESI);
a61af66fc99e Initial load duke parents: diff changeset	157 // Singleton class for interpreter's stack pointer
a61af66fc99e Initial load duke parents: diff changeset	158 reg_class ebp_reg(EBP);
a61af66fc99e Initial load duke parents: diff changeset	159 // Singleton class for stack pointer
a61af66fc99e Initial load duke parents: diff changeset	160 reg_class sp_reg(ESP);
a61af66fc99e Initial load duke parents: diff changeset	161 // Singleton class for instruction pointer
a61af66fc99e Initial load duke parents: diff changeset	162 // reg_class ip_reg(EIP);
a61af66fc99e Initial load duke parents: diff changeset	163 // Class of integer register pairs
a61af66fc99e Initial load duke parents: diff changeset	164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
a61af66fc99e Initial load duke parents: diff changeset	165 // Class of integer register pairs that aligns with calling convention
a61af66fc99e Initial load duke parents: diff changeset	166 reg_class eadx_reg( EAX,EDX );
a61af66fc99e Initial load duke parents: diff changeset	167 reg_class ebcx_reg( ECX,EBX );
a61af66fc99e Initial load duke parents: diff changeset	168 // Not AX or DX, used in divides
a61af66fc99e Initial load duke parents: diff changeset	169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
a61af66fc99e Initial load duke parents: diff changeset	170
a61af66fc99e Initial load duke parents: diff changeset	171 // Floating point registers. Notice FPR0 is not a choice.
a61af66fc99e Initial load duke parents: diff changeset	172 // FPR0 is not ever allocated; we use clever encodings to fake
a61af66fc99e Initial load duke parents: diff changeset	173 // a 2-address instructions out of Intels FP stack.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	175
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	178 FPR7L,FPR7H );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	180 reg_class fp_flt_reg0( FPR1L );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	185
0 a61af66fc99e Initial load duke parents: diff changeset	186 %}
a61af66fc99e Initial load duke parents: diff changeset	187
a61af66fc99e Initial load duke parents: diff changeset	188
a61af66fc99e Initial load duke parents: diff changeset	189 //----------SOURCE BLOCK-------------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	190 // This is a block of C++ code which provides values, functions, and
a61af66fc99e Initial load duke parents: diff changeset	191 // definitions necessary in the rest of the architecture description
1209 e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	192 source_hpp %{
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	193 // Must be visible to the DFA in dfa_x86_32.cpp
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	194 extern bool is_operand_hi32_zero(Node* n);
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	195 %}
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	196
0 a61af66fc99e Initial load duke parents: diff changeset	197 source %{
304 dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories never parents: 235 diff changeset	198 #define RELOC_IMM32 Assembler::imm_operand
0 a61af66fc99e Initial load duke parents: diff changeset	199 #define RELOC_DISP32 Assembler::disp32_operand
a61af66fc99e Initial load duke parents: diff changeset	200
a61af66fc99e Initial load duke parents: diff changeset	201 #define __ _masm.
a61af66fc99e Initial load duke parents: diff changeset	202
a61af66fc99e Initial load duke parents: diff changeset	203 // How to find the high register of a Long pair, given the low register
a61af66fc99e Initial load duke parents: diff changeset	204 #define HIGH_FROM_LOW(x) ((x)+2)
a61af66fc99e Initial load duke parents: diff changeset	205
a61af66fc99e Initial load duke parents: diff changeset	206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
a61af66fc99e Initial load duke parents: diff changeset	207 // instructions, to allow sign-masking or sign-bit flipping. They allow
a61af66fc99e Initial load duke parents: diff changeset	208 // fast versions of NegF/NegD and AbsF/AbsD.
a61af66fc99e Initial load duke parents: diff changeset	209
a61af66fc99e Initial load duke parents: diff changeset	210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
a61af66fc99e Initial load duke parents: diff changeset	211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
a61af66fc99e Initial load duke parents: diff changeset	212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
a61af66fc99e Initial load duke parents: diff changeset	213 // of 128-bits operands for SSE instructions.
a61af66fc99e Initial load duke parents: diff changeset	214 jlong operand = (jlong)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
a61af66fc99e Initial load duke parents: diff changeset	215 // Store the value to a 128-bits operand.
a61af66fc99e Initial load duke parents: diff changeset	216 operand[0] = lo;
a61af66fc99e Initial load duke parents: diff changeset	217 operand[1] = hi;
a61af66fc99e Initial load duke parents: diff changeset	218 return operand;
a61af66fc99e Initial load duke parents: diff changeset	219 }
a61af66fc99e Initial load duke parents: diff changeset	220
a61af66fc99e Initial load duke parents: diff changeset	221 // Buffer for 128-bits masks used by SSE instructions.
a61af66fc99e Initial load duke parents: diff changeset	222 static jlong fp_signmask_pool[(4+1)2]; // 4128bits(data) + 128bits(alignment)
a61af66fc99e Initial load duke parents: diff changeset	223
a61af66fc99e Initial load duke parents: diff changeset	224 // Static initialization during VM startup.
a61af66fc99e Initial load duke parents: diff changeset	225 static jlong float_signmask_pool = double_quadword(&fp_signmask_pool[12], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
a61af66fc99e Initial load duke parents: diff changeset	226 static jlong double_signmask_pool = double_quadword(&fp_signmask_pool[22], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
a61af66fc99e Initial load duke parents: diff changeset	227 static jlong float_signflip_pool = double_quadword(&fp_signmask_pool[32], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
a61af66fc99e Initial load duke parents: diff changeset	228 static jlong double_signflip_pool = double_quadword(&fp_signmask_pool[42], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
a61af66fc99e Initial load duke parents: diff changeset	229
1137 97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	230 // Offset hacking within calls.
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	231 static int pre_call_resets_size() {
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	232 int size = 0;
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	233 Compile* C = Compile::current();
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	234 if (C->in_24_bit_fp_mode()) {
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	235 size += 6; // fldcw
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	236 }
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	237 if (C->max_vector_size() > 16) {
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	238 size += 3; // vzeroupper
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	239 }
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	240 return size;
1137 97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	241 }
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	242
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	243 static int preserve_SP_size() {
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	244 return 2; // op, rm(reg/reg)
1137 97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	245 }
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	246
0 a61af66fc99e Initial load duke parents: diff changeset	247 // !!!!! Special hack to get all type of calls to specify the byte offset
a61af66fc99e Initial load duke parents: diff changeset	248 // from the start of the call to the point where the return address
a61af66fc99e Initial load duke parents: diff changeset	249 // will point.
a61af66fc99e Initial load duke parents: diff changeset	250 int MachCallStaticJavaNode::ret_addr_offset() {
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
1137 97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	252 if (_method_handle_invoke)
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	253 offset += preserve_SP_size();
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	254 return offset;
0 a61af66fc99e Initial load duke parents: diff changeset	255 }
a61af66fc99e Initial load duke parents: diff changeset	256
a61af66fc99e Initial load duke parents: diff changeset	257 int MachCallDynamicJavaNode::ret_addr_offset() {
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
0 a61af66fc99e Initial load duke parents: diff changeset	259 }
a61af66fc99e Initial load duke parents: diff changeset	260
a61af66fc99e Initial load duke parents: diff changeset	261 static int sizeof_FFree_Float_Stack_All = -1;
a61af66fc99e Initial load duke parents: diff changeset	262
a61af66fc99e Initial load duke parents: diff changeset	263 int MachCallRuntimeNode::ret_addr_offset() {
a61af66fc99e Initial load duke parents: diff changeset	264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
0 a61af66fc99e Initial load duke parents: diff changeset	266 }
a61af66fc99e Initial load duke parents: diff changeset	267
a61af66fc99e Initial load duke parents: diff changeset	268 // Indicate if the safepoint node needs the polling page as an input.
a61af66fc99e Initial load duke parents: diff changeset	269 // Since x86 does have absolute addressing, it doesn't.
a61af66fc99e Initial load duke parents: diff changeset	270 bool SafePointNode::needs_polling_address_input() {
a61af66fc99e Initial load duke parents: diff changeset	271 return false;
a61af66fc99e Initial load duke parents: diff changeset	272 }
a61af66fc99e Initial load duke parents: diff changeset	273
a61af66fc99e Initial load duke parents: diff changeset	274 //
a61af66fc99e Initial load duke parents: diff changeset	275 // Compute padding required for nodes which need alignment
a61af66fc99e Initial load duke parents: diff changeset	276 //
a61af66fc99e Initial load duke parents: diff changeset	277
a61af66fc99e Initial load duke parents: diff changeset	278 // The address of the call instruction needs to be 4-byte aligned to
a61af66fc99e Initial load duke parents: diff changeset	279 // ensure that it does not span a cache line so that it can be patched.
a61af66fc99e Initial load duke parents: diff changeset	280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	281 current_offset += pre_call_resets_size(); // skip fldcw, if any
1137 97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	282 current_offset += 1; // skip call opcode byte
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	283 return round_to(current_offset, alignment_required()) - current_offset;
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	284 }
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	285
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	286 // The address of the call instruction needs to be 4-byte aligned to
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	287 // ensure that it does not span a cache line so that it can be patched.
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	289 current_offset += pre_call_resets_size(); // skip fldcw, if any
1137 97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	290 current_offset += preserve_SP_size(); // skip mov rbp, rsp
0 a61af66fc99e Initial load duke parents: diff changeset	291 current_offset += 1; // skip call opcode byte
a61af66fc99e Initial load duke parents: diff changeset	292 return round_to(current_offset, alignment_required()) - current_offset;
a61af66fc99e Initial load duke parents: diff changeset	293 }
a61af66fc99e Initial load duke parents: diff changeset	294
a61af66fc99e Initial load duke parents: diff changeset	295 // The address of the call instruction needs to be 4-byte aligned to
a61af66fc99e Initial load duke parents: diff changeset	296 // ensure that it does not span a cache line so that it can be patched.
a61af66fc99e Initial load duke parents: diff changeset	297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	298 current_offset += pre_call_resets_size(); // skip fldcw, if any
0 a61af66fc99e Initial load duke parents: diff changeset	299 current_offset += 5; // skip MOV instruction
a61af66fc99e Initial load duke parents: diff changeset	300 current_offset += 1; // skip call opcode byte
a61af66fc99e Initial load duke parents: diff changeset	301 return round_to(current_offset, alignment_required()) - current_offset;
a61af66fc99e Initial load duke parents: diff changeset	302 }
a61af66fc99e Initial load duke parents: diff changeset	303
a61af66fc99e Initial load duke parents: diff changeset	304 // EMIT_RM()
a61af66fc99e Initial load duke parents: diff changeset	305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
a61af66fc99e Initial load duke parents: diff changeset	306 unsigned char c = (unsigned char)((f1 << 6) \| (f2 << 3) \| f3);
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	307 cbuf.insts()->emit_int8(c);
0 a61af66fc99e Initial load duke parents: diff changeset	308 }
a61af66fc99e Initial load duke parents: diff changeset	309
a61af66fc99e Initial load duke parents: diff changeset	310 // EMIT_CC()
a61af66fc99e Initial load duke parents: diff changeset	311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
a61af66fc99e Initial load duke parents: diff changeset	312 unsigned char c = (unsigned char)( f1 \| f2 );
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	313 cbuf.insts()->emit_int8(c);
0 a61af66fc99e Initial load duke parents: diff changeset	314 }
a61af66fc99e Initial load duke parents: diff changeset	315
a61af66fc99e Initial load duke parents: diff changeset	316 // EMIT_OPCODE()
a61af66fc99e Initial load duke parents: diff changeset	317 void emit_opcode(CodeBuffer &cbuf, int code) {
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	318 cbuf.insts()->emit_int8((unsigned char) code);
0 a61af66fc99e Initial load duke parents: diff changeset	319 }
a61af66fc99e Initial load duke parents: diff changeset	320
a61af66fc99e Initial load duke parents: diff changeset	321 // EMIT_OPCODE() w/ relocation information
a61af66fc99e Initial load duke parents: diff changeset	322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	323 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
0 a61af66fc99e Initial load duke parents: diff changeset	324 emit_opcode(cbuf, code);
a61af66fc99e Initial load duke parents: diff changeset	325 }
a61af66fc99e Initial load duke parents: diff changeset	326
a61af66fc99e Initial load duke parents: diff changeset	327 // EMIT_D8()
a61af66fc99e Initial load duke parents: diff changeset	328 void emit_d8(CodeBuffer &cbuf, int d8) {
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	329 cbuf.insts()->emit_int8((unsigned char) d8);
0 a61af66fc99e Initial load duke parents: diff changeset	330 }
a61af66fc99e Initial load duke parents: diff changeset	331
a61af66fc99e Initial load duke parents: diff changeset	332 // EMIT_D16()
a61af66fc99e Initial load duke parents: diff changeset	333 void emit_d16(CodeBuffer &cbuf, int d16) {
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	334 cbuf.insts()->emit_int16(d16);
0 a61af66fc99e Initial load duke parents: diff changeset	335 }
a61af66fc99e Initial load duke parents: diff changeset	336
a61af66fc99e Initial load duke parents: diff changeset	337 // EMIT_D32()
a61af66fc99e Initial load duke parents: diff changeset	338 void emit_d32(CodeBuffer &cbuf, int d32) {
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	339 cbuf.insts()->emit_int32(d32);
0 a61af66fc99e Initial load duke parents: diff changeset	340 }
a61af66fc99e Initial load duke parents: diff changeset	341
a61af66fc99e Initial load duke parents: diff changeset	342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
a61af66fc99e Initial load duke parents: diff changeset	343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
a61af66fc99e Initial load duke parents: diff changeset	344 int format) {
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	345 cbuf.relocate(cbuf.insts_mark(), reloc, format);
3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	346 cbuf.insts()->emit_int32(d32);
0 a61af66fc99e Initial load duke parents: diff changeset	347 }
a61af66fc99e Initial load duke parents: diff changeset	348
a61af66fc99e Initial load duke parents: diff changeset	349 // emit 32 bit value and construct relocation entry from RelocationHolder
a61af66fc99e Initial load duke parents: diff changeset	350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
a61af66fc99e Initial load duke parents: diff changeset	351 int format) {
a61af66fc99e Initial load duke parents: diff changeset	352 #ifdef ASSERT
a61af66fc99e Initial load duke parents: diff changeset	353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
12316 190899198332 7195622: CheckUnhandledOops has limited usefulness now hseigel parents: 10169 diff changeset	354 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode \|\| !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
0 a61af66fc99e Initial load duke parents: diff changeset	355 }
a61af66fc99e Initial load duke parents: diff changeset	356 #endif
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	357 cbuf.relocate(cbuf.insts_mark(), rspec, format);
3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	358 cbuf.insts()->emit_int32(d32);
0 a61af66fc99e Initial load duke parents: diff changeset	359 }
a61af66fc99e Initial load duke parents: diff changeset	360
a61af66fc99e Initial load duke parents: diff changeset	361 // Access stack slot for load or store
a61af66fc99e Initial load duke parents: diff changeset	362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
a61af66fc99e Initial load duke parents: diff changeset	363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
a61af66fc99e Initial load duke parents: diff changeset	364 if( -128 <= disp && disp <= 127 ) {
a61af66fc99e Initial load duke parents: diff changeset	365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
a61af66fc99e Initial load duke parents: diff changeset	366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
a61af66fc99e Initial load duke parents: diff changeset	367 emit_d8 (cbuf, disp); // Displacement // R/M byte
a61af66fc99e Initial load duke parents: diff changeset	368 } else {
a61af66fc99e Initial load duke parents: diff changeset	369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
a61af66fc99e Initial load duke parents: diff changeset	370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
a61af66fc99e Initial load duke parents: diff changeset	371 emit_d32(cbuf, disp); // Displacement // R/M byte
a61af66fc99e Initial load duke parents: diff changeset	372 }
a61af66fc99e Initial load duke parents: diff changeset	373 }
a61af66fc99e Initial load duke parents: diff changeset	374
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	375 // rRegI ereg, memory mem) %{ // emit_reg_mem
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
0 a61af66fc99e Initial load duke parents: diff changeset	377 // There is no index & no scale, use form without SIB byte
a61af66fc99e Initial load duke parents: diff changeset	378 if ((index == 0x4) &&
a61af66fc99e Initial load duke parents: diff changeset	379 (scale == 0) && (base != ESP_enc)) {
a61af66fc99e Initial load duke parents: diff changeset	380 // If no displacement, mode is 0x0; unless base is [EBP]
a61af66fc99e Initial load duke parents: diff changeset	381 if ( (displace == 0) && (base != EBP_enc) ) {
a61af66fc99e Initial load duke parents: diff changeset	382 emit_rm(cbuf, 0x0, reg_encoding, base);
a61af66fc99e Initial load duke parents: diff changeset	383 }
a61af66fc99e Initial load duke parents: diff changeset	384 else { // If 8-bit displacement, mode 0x1
a61af66fc99e Initial load duke parents: diff changeset	385 if ((displace >= -128) && (displace <= 127)
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	386 && (disp_reloc == relocInfo::none) ) {
0 a61af66fc99e Initial load duke parents: diff changeset	387 emit_rm(cbuf, 0x1, reg_encoding, base);
a61af66fc99e Initial load duke parents: diff changeset	388 emit_d8(cbuf, displace);
a61af66fc99e Initial load duke parents: diff changeset	389 }
a61af66fc99e Initial load duke parents: diff changeset	390 else { // If 32-bit displacement
a61af66fc99e Initial load duke parents: diff changeset	391 if (base == -1) { // Special flag for absolute address
a61af66fc99e Initial load duke parents: diff changeset	392 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
a61af66fc99e Initial load duke parents: diff changeset	393 // (manual lies; no SIB needed here)
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	394 if ( disp_reloc != relocInfo::none ) {
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	395 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
0 a61af66fc99e Initial load duke parents: diff changeset	396 } else {
a61af66fc99e Initial load duke parents: diff changeset	397 emit_d32 (cbuf, displace);
a61af66fc99e Initial load duke parents: diff changeset	398 }
a61af66fc99e Initial load duke parents: diff changeset	399 }
a61af66fc99e Initial load duke parents: diff changeset	400 else { // Normal base + offset
a61af66fc99e Initial load duke parents: diff changeset	401 emit_rm(cbuf, 0x2, reg_encoding, base);
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	402 if ( disp_reloc != relocInfo::none ) {
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	403 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
0 a61af66fc99e Initial load duke parents: diff changeset	404 } else {
a61af66fc99e Initial load duke parents: diff changeset	405 emit_d32 (cbuf, displace);
a61af66fc99e Initial load duke parents: diff changeset	406 }
a61af66fc99e Initial load duke parents: diff changeset	407 }
a61af66fc99e Initial load duke parents: diff changeset	408 }
a61af66fc99e Initial load duke parents: diff changeset	409 }
a61af66fc99e Initial load duke parents: diff changeset	410 }
a61af66fc99e Initial load duke parents: diff changeset	411 else { // Else, encode with the SIB byte
a61af66fc99e Initial load duke parents: diff changeset	412 // If no displacement, mode is 0x0; unless base is [EBP]
a61af66fc99e Initial load duke parents: diff changeset	413 if (displace == 0 && (base != EBP_enc)) { // If no displacement
a61af66fc99e Initial load duke parents: diff changeset	414 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
a61af66fc99e Initial load duke parents: diff changeset	415 emit_rm(cbuf, scale, index, base);
a61af66fc99e Initial load duke parents: diff changeset	416 }
a61af66fc99e Initial load duke parents: diff changeset	417 else { // If 8-bit displacement, mode 0x1
a61af66fc99e Initial load duke parents: diff changeset	418 if ((displace >= -128) && (displace <= 127)
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	419 && (disp_reloc == relocInfo::none) ) {
0 a61af66fc99e Initial load duke parents: diff changeset	420 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
a61af66fc99e Initial load duke parents: diff changeset	421 emit_rm(cbuf, scale, index, base);
a61af66fc99e Initial load duke parents: diff changeset	422 emit_d8(cbuf, displace);
a61af66fc99e Initial load duke parents: diff changeset	423 }
a61af66fc99e Initial load duke parents: diff changeset	424 else { // If 32-bit displacement
a61af66fc99e Initial load duke parents: diff changeset	425 if (base == 0x04 ) {
a61af66fc99e Initial load duke parents: diff changeset	426 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
a61af66fc99e Initial load duke parents: diff changeset	427 emit_rm(cbuf, scale, index, 0x04);
a61af66fc99e Initial load duke parents: diff changeset	428 } else {
a61af66fc99e Initial load duke parents: diff changeset	429 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
a61af66fc99e Initial load duke parents: diff changeset	430 emit_rm(cbuf, scale, index, base);
a61af66fc99e Initial load duke parents: diff changeset	431 }
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	432 if ( disp_reloc != relocInfo::none ) {
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	433 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
0 a61af66fc99e Initial load duke parents: diff changeset	434 } else {
a61af66fc99e Initial load duke parents: diff changeset	435 emit_d32 (cbuf, displace);
a61af66fc99e Initial load duke parents: diff changeset	436 }
a61af66fc99e Initial load duke parents: diff changeset	437 }
a61af66fc99e Initial load duke parents: diff changeset	438 }
a61af66fc99e Initial load duke parents: diff changeset	439 }
a61af66fc99e Initial load duke parents: diff changeset	440 }
a61af66fc99e Initial load duke parents: diff changeset	441
a61af66fc99e Initial load duke parents: diff changeset	442
a61af66fc99e Initial load duke parents: diff changeset	443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
a61af66fc99e Initial load duke parents: diff changeset	444 if( dst_encoding == src_encoding ) {
a61af66fc99e Initial load duke parents: diff changeset	445 // reg-reg copy, use an empty encoding
a61af66fc99e Initial load duke parents: diff changeset	446 } else {
a61af66fc99e Initial load duke parents: diff changeset	447 emit_opcode( cbuf, 0x8B );
a61af66fc99e Initial load duke parents: diff changeset	448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
a61af66fc99e Initial load duke parents: diff changeset	449 }
a61af66fc99e Initial load duke parents: diff changeset	450 }
a61af66fc99e Initial load duke parents: diff changeset	451
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	453 Label exit;
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	454 __ jccb(Assembler::noParity, exit);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	455 __ pushf();
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	456 //
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	457 // comiss/ucomiss instructions set ZF,PF,CF flags and
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	458 // zero OF,AF,SF for NaN values.
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	459 // Fixup flags by zeroing ZF,PF so that compare of NaN
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	460 // values returns 'less than' result (CF is set).
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	461 // Leave the rest of flags unchanged.
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	462 //
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	463 // 7 6 5 4 3 2 1 0
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	464 // \|S\|Z\|r\|A\|r\|P\|r\|C\| (r - reserved bit)
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	465 // 0 0 1 0 1 0 1 1 (0x2B)
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	466 //
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	467 __ andl(Address(rsp, 0), 0xffffff2b);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	468 __ popf();
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	469 __ bind(exit);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	470 }
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	471
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	473 Label done;
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	474 __ movl(dst, -1);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	475 __ jcc(Assembler::parity, done);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	476 __ jcc(Assembler::below, done);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	477 __ setb(Assembler::notEqual, dst);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	478 __ movzbl(dst, dst);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	479 __ bind(done);
0 a61af66fc99e Initial load duke parents: diff changeset	480 }
a61af66fc99e Initial load duke parents: diff changeset	481
a61af66fc99e Initial load duke parents: diff changeset	482
a61af66fc99e Initial load duke parents: diff changeset	483 //=============================================================================
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	485
4114 6729bbc1fcd6 7003454: order constants in constant table by number of references in code twisti parents: 4047 diff changeset	486 int Compile::ConstantTable::calculate_table_base_offset() const {
6729bbc1fcd6 7003454: order constants in constant table by number of references in code twisti parents: 4047 diff changeset	487 return 0; // absolute addressing, no offset
6729bbc1fcd6 7003454: order constants in constant table by number of references in code twisti parents: 4047 diff changeset	488 }
6729bbc1fcd6 7003454: order constants in constant table by number of references in code twisti parents: 4047 diff changeset	489
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	490 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	491 // Empty encoding
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	492 }
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	493
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	494 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	495 return 0;
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	496 }
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	497
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	498 #ifndef PRODUCT
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	499 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	500 st->print("# MachConstantBaseNode (empty encoding)");
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	501 }
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	502 #endif
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	503
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	504
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	505 //=============================================================================
0 a61af66fc99e Initial load duke parents: diff changeset	506 #ifndef PRODUCT
4947 fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	507 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
0 a61af66fc99e Initial load duke parents: diff changeset	508 Compile* C = ra_->C;
a61af66fc99e Initial load duke parents: diff changeset	509
a61af66fc99e Initial load duke parents: diff changeset	510 int framesize = C->frame_slots() << LogBytesPerInt;
a61af66fc99e Initial load duke parents: diff changeset	511 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
4947 fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	512 // Remove wordSize for return addr which is already pushed.
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	513 framesize -= wordSize;
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	514
0 a61af66fc99e Initial load duke parents: diff changeset	515 if (C->need_stack_bang(framesize)) {
a61af66fc99e Initial load duke parents: diff changeset	516 framesize -= wordSize;
4947 fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	517 st->print("# stack bang");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	518 st->print("\n\t");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	519 st->print("PUSH EBP\t# Save EBP");
0 a61af66fc99e Initial load duke parents: diff changeset	520 if (framesize) {
4947 fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	521 st->print("\n\t");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	522 st->print("SUB ESP, #%d\t# Create frame",framesize);
0 a61af66fc99e Initial load duke parents: diff changeset	523 }
a61af66fc99e Initial load duke parents: diff changeset	524 } else {
4947 fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	525 st->print("SUB ESP, #%d\t# Create frame",framesize);
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	526 st->print("\n\t");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	527 framesize -= wordSize;
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	528 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	529 }
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	530
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	531 if (VerifyStackAtCalls) {
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	532 st->print("\n\t");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	533 framesize -= wordSize;
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	534 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
0 a61af66fc99e Initial load duke parents: diff changeset	535 }
4947 fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	536
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	537 if( C->in_24_bit_fp_mode() ) {
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	538 st->print("\n\t");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	539 st->print("FLDCW \t# load 24 bit fpu control word");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	540 }
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	541 if (UseSSE >= 2 && VerifyFPU) {
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	542 st->print("\n\t");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	543 st->print("# verify FPU stack (must be clean on entry)");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	544 }
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	545
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	546 #ifdef ASSERT
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	547 if (VerifyStackAtCalls) {
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	548 st->print("\n\t");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	549 st->print("# stack alignment check");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	550 }
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	551 #endif
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	552 st->cr();
0 a61af66fc99e Initial load duke parents: diff changeset	553 }
a61af66fc99e Initial load duke parents: diff changeset	554 #endif
a61af66fc99e Initial load duke parents: diff changeset	555
a61af66fc99e Initial load duke parents: diff changeset	556
a61af66fc99e Initial load duke parents: diff changeset	557 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load duke parents: diff changeset	558 Compile* C = ra_->C;
4947 fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	559 MacroAssembler _masm(&cbuf);
0 a61af66fc99e Initial load duke parents: diff changeset	560
a61af66fc99e Initial load duke parents: diff changeset	561 int framesize = C->frame_slots() << LogBytesPerInt;
4947 fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	562
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	563 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29 kvn parents: 4777 diff changeset	564
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	565 C->set_frame_complete(cbuf.insts_size());
0 a61af66fc99e Initial load duke parents: diff changeset	566
4114 6729bbc1fcd6 7003454: order constants in constant table by number of references in code twisti parents: 4047 diff changeset	567 if (C->has_mach_constant_base_node()) {
6729bbc1fcd6 7003454: order constants in constant table by number of references in code twisti parents: 4047 diff changeset	568 // NOTE: We set the table base offset here because users might be
6729bbc1fcd6 7003454: order constants in constant table by number of references in code twisti parents: 4047 diff changeset	569 // emitted before MachConstantBaseNode.
6729bbc1fcd6 7003454: order constants in constant table by number of references in code twisti parents: 4047 diff changeset	570 Compile::ConstantTable& constant_table = C->constant_table();
6729bbc1fcd6 7003454: order constants in constant table by number of references in code twisti parents: 4047 diff changeset	571 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
6729bbc1fcd6 7003454: order constants in constant table by number of references in code twisti parents: 4047 diff changeset	572 }
0 a61af66fc99e Initial load duke parents: diff changeset	573 }
a61af66fc99e Initial load duke parents: diff changeset	574
a61af66fc99e Initial load duke parents: diff changeset	575 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load duke parents: diff changeset	576 return MachNode::size(ra_); // too many variables; just compute it the hard way
a61af66fc99e Initial load duke parents: diff changeset	577 }
a61af66fc99e Initial load duke parents: diff changeset	578
a61af66fc99e Initial load duke parents: diff changeset	579 int MachPrologNode::reloc() const {
a61af66fc99e Initial load duke parents: diff changeset	580 return 0; // a large enough number
a61af66fc99e Initial load duke parents: diff changeset	581 }
a61af66fc99e Initial load duke parents: diff changeset	582
a61af66fc99e Initial load duke parents: diff changeset	583 //=============================================================================
a61af66fc99e Initial load duke parents: diff changeset	584 #ifndef PRODUCT
a61af66fc99e Initial load duke parents: diff changeset	585 void MachEpilogNode::format( PhaseRegAlloc ra_, outputStream st ) const {
a61af66fc99e Initial load duke parents: diff changeset	586 Compile *C = ra_->C;
a61af66fc99e Initial load duke parents: diff changeset	587 int framesize = C->frame_slots() << LogBytesPerInt;
a61af66fc99e Initial load duke parents: diff changeset	588 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
a61af66fc99e Initial load duke parents: diff changeset	589 // Remove two words for return addr and rbp,
a61af66fc99e Initial load duke parents: diff changeset	590 framesize -= 2*wordSize;
a61af66fc99e Initial load duke parents: diff changeset	591
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	592 if (C->max_vector_size() > 16) {
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	593 st->print("VZEROUPPER");
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	594 st->cr(); st->print("\t");
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	595 }
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	596 if (C->in_24_bit_fp_mode()) {
0 a61af66fc99e Initial load duke parents: diff changeset	597 st->print("FLDCW standard control word");
a61af66fc99e Initial load duke parents: diff changeset	598 st->cr(); st->print("\t");
a61af66fc99e Initial load duke parents: diff changeset	599 }
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	600 if (framesize) {
0 a61af66fc99e Initial load duke parents: diff changeset	601 st->print("ADD ESP,%d\t# Destroy frame",framesize);
a61af66fc99e Initial load duke parents: diff changeset	602 st->cr(); st->print("\t");
a61af66fc99e Initial load duke parents: diff changeset	603 }
a61af66fc99e Initial load duke parents: diff changeset	604 st->print_cr("POPL EBP"); st->print("\t");
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	605 if (do_polling() && C->is_method_compilation()) {
0 a61af66fc99e Initial load duke parents: diff changeset	606 st->print("TEST PollPage,EAX\t! Poll Safepoint");
a61af66fc99e Initial load duke parents: diff changeset	607 st->cr(); st->print("\t");
a61af66fc99e Initial load duke parents: diff changeset	608 }
a61af66fc99e Initial load duke parents: diff changeset	609 }
a61af66fc99e Initial load duke parents: diff changeset	610 #endif
a61af66fc99e Initial load duke parents: diff changeset	611
a61af66fc99e Initial load duke parents: diff changeset	612 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load duke parents: diff changeset	613 Compile *C = ra_->C;
a61af66fc99e Initial load duke parents: diff changeset	614
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	615 if (C->max_vector_size() > 16) {
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	616 // Clear upper bits of YMM registers when current compiled code uses
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	617 // wide vectors to avoid AVX <-> SSE transition penalty during call.
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	618 MacroAssembler masm(&cbuf);
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	619 masm.vzeroupper();
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	620 }
0 a61af66fc99e Initial load duke parents: diff changeset	621 // If method set FPU control word, restore to standard control word
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	622 if (C->in_24_bit_fp_mode()) {
0 a61af66fc99e Initial load duke parents: diff changeset	623 MacroAssembler masm(&cbuf);
a61af66fc99e Initial load duke parents: diff changeset	624 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
a61af66fc99e Initial load duke parents: diff changeset	625 }
a61af66fc99e Initial load duke parents: diff changeset	626
a61af66fc99e Initial load duke parents: diff changeset	627 int framesize = C->frame_slots() << LogBytesPerInt;
a61af66fc99e Initial load duke parents: diff changeset	628 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
a61af66fc99e Initial load duke parents: diff changeset	629 // Remove two words for return addr and rbp,
a61af66fc99e Initial load duke parents: diff changeset	630 framesize -= 2*wordSize;
a61af66fc99e Initial load duke parents: diff changeset	631
a61af66fc99e Initial load duke parents: diff changeset	632 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
a61af66fc99e Initial load duke parents: diff changeset	633
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	634 if (framesize >= 128) {
0 a61af66fc99e Initial load duke parents: diff changeset	635 emit_opcode(cbuf, 0x81); // add SP, #framesize
a61af66fc99e Initial load duke parents: diff changeset	636 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
a61af66fc99e Initial load duke parents: diff changeset	637 emit_d32(cbuf, framesize);
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	638 } else if (framesize) {
0 a61af66fc99e Initial load duke parents: diff changeset	639 emit_opcode(cbuf, 0x83); // add SP, #framesize
a61af66fc99e Initial load duke parents: diff changeset	640 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
a61af66fc99e Initial load duke parents: diff changeset	641 emit_d8(cbuf, framesize);
a61af66fc99e Initial load duke parents: diff changeset	642 }
a61af66fc99e Initial load duke parents: diff changeset	643
a61af66fc99e Initial load duke parents: diff changeset	644 emit_opcode(cbuf, 0x58 \| EBP_enc);
a61af66fc99e Initial load duke parents: diff changeset	645
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	646 if (do_polling() && C->is_method_compilation()) {
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	647 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
0 a61af66fc99e Initial load duke parents: diff changeset	648 emit_opcode(cbuf,0x85);
a61af66fc99e Initial load duke parents: diff changeset	649 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
a61af66fc99e Initial load duke parents: diff changeset	650 emit_d32(cbuf, (intptr_t)os::get_polling_page());
a61af66fc99e Initial load duke parents: diff changeset	651 }
a61af66fc99e Initial load duke parents: diff changeset	652 }
a61af66fc99e Initial load duke parents: diff changeset	653
a61af66fc99e Initial load duke parents: diff changeset	654 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load duke parents: diff changeset	655 Compile *C = ra_->C;
a61af66fc99e Initial load duke parents: diff changeset	656 // If method set FPU control word, restore to standard control word
a61af66fc99e Initial load duke parents: diff changeset	657 int size = C->in_24_bit_fp_mode() ? 6 : 0;
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	658 if (C->max_vector_size() > 16) size += 3; // vzeroupper
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	659 if (do_polling() && C->is_method_compilation()) size += 6;
0 a61af66fc99e Initial load duke parents: diff changeset	660
a61af66fc99e Initial load duke parents: diff changeset	661 int framesize = C->frame_slots() << LogBytesPerInt;
a61af66fc99e Initial load duke parents: diff changeset	662 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
a61af66fc99e Initial load duke parents: diff changeset	663 // Remove two words for return addr and rbp,
a61af66fc99e Initial load duke parents: diff changeset	664 framesize -= 2*wordSize;
a61af66fc99e Initial load duke parents: diff changeset	665
a61af66fc99e Initial load duke parents: diff changeset	666 size++; // popl rbp,
a61af66fc99e Initial load duke parents: diff changeset	667
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	668 if (framesize >= 128) {
0 a61af66fc99e Initial load duke parents: diff changeset	669 size += 6;
a61af66fc99e Initial load duke parents: diff changeset	670 } else {
a61af66fc99e Initial load duke parents: diff changeset	671 size += framesize ? 3 : 0;
a61af66fc99e Initial load duke parents: diff changeset	672 }
a61af66fc99e Initial load duke parents: diff changeset	673 return size;
a61af66fc99e Initial load duke parents: diff changeset	674 }
a61af66fc99e Initial load duke parents: diff changeset	675
a61af66fc99e Initial load duke parents: diff changeset	676 int MachEpilogNode::reloc() const {
a61af66fc99e Initial load duke parents: diff changeset	677 return 0; // a large enough number
a61af66fc99e Initial load duke parents: diff changeset	678 }
a61af66fc99e Initial load duke parents: diff changeset	679
a61af66fc99e Initial load duke parents: diff changeset	680 const Pipeline * MachEpilogNode::pipeline() const {
a61af66fc99e Initial load duke parents: diff changeset	681 return MachNode::pipeline_class();
a61af66fc99e Initial load duke parents: diff changeset	682 }
a61af66fc99e Initial load duke parents: diff changeset	683
a61af66fc99e Initial load duke parents: diff changeset	684 int MachEpilogNode::safepoint_offset() const { return 0; }
a61af66fc99e Initial load duke parents: diff changeset	685
a61af66fc99e Initial load duke parents: diff changeset	686 //=============================================================================
a61af66fc99e Initial load duke parents: diff changeset	687
a61af66fc99e Initial load duke parents: diff changeset	688 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
a61af66fc99e Initial load duke parents: diff changeset	689 static enum RC rc_class( OptoReg::Name reg ) {
a61af66fc99e Initial load duke parents: diff changeset	690
a61af66fc99e Initial load duke parents: diff changeset	691 if( !OptoReg::is_valid(reg) ) return rc_bad;
a61af66fc99e Initial load duke parents: diff changeset	692 if (OptoReg::is_stack(reg)) return rc_stack;
a61af66fc99e Initial load duke parents: diff changeset	693
a61af66fc99e Initial load duke parents: diff changeset	694 VMReg r = OptoReg::as_VMReg(reg);
a61af66fc99e Initial load duke parents: diff changeset	695 if (r->is_Register()) return rc_int;
a61af66fc99e Initial load duke parents: diff changeset	696 if (r->is_FloatRegister()) {
a61af66fc99e Initial load duke parents: diff changeset	697 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
a61af66fc99e Initial load duke parents: diff changeset	698 return rc_float;
a61af66fc99e Initial load duke parents: diff changeset	699 }
a61af66fc99e Initial load duke parents: diff changeset	700 assert(r->is_XMMRegister(), "must be");
a61af66fc99e Initial load duke parents: diff changeset	701 return rc_xmm;
a61af66fc99e Initial load duke parents: diff changeset	702 }
a61af66fc99e Initial load duke parents: diff changeset	703
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	704 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	705 int opcode, const char op_str, int size, outputStream st ) {
0 a61af66fc99e Initial load duke parents: diff changeset	706 if( cbuf ) {
a61af66fc99e Initial load duke parents: diff changeset	707 emit_opcode (*cbuf, opcode );
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	708 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
0 a61af66fc99e Initial load duke parents: diff changeset	709 #ifndef PRODUCT
a61af66fc99e Initial load duke parents: diff changeset	710 } else if( !do_size ) {
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	711 if( size != 0 ) st->print("\n\t");
0 a61af66fc99e Initial load duke parents: diff changeset	712 if( opcode == 0x8B \|\| opcode == 0x89 ) { // MOV
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	713 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	714 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
0 a61af66fc99e Initial load duke parents: diff changeset	715 } else { // FLD, FST, PUSH, POP
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	716 st->print("%s [ESP + #%d]",op_str,offset);
0 a61af66fc99e Initial load duke parents: diff changeset	717 }
a61af66fc99e Initial load duke parents: diff changeset	718 #endif
a61af66fc99e Initial load duke parents: diff changeset	719 }
a61af66fc99e Initial load duke parents: diff changeset	720 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
a61af66fc99e Initial load duke parents: diff changeset	721 return size+3+offset_size;
a61af66fc99e Initial load duke parents: diff changeset	722 }
a61af66fc99e Initial load duke parents: diff changeset	723
a61af66fc99e Initial load duke parents: diff changeset	724 // Helper for XMM registers. Extra opcode bits, limited syntax.
a61af66fc99e Initial load duke parents: diff changeset	725 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	726 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	727 if (cbuf) {
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	728 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	729 if (reg_lo+1 == reg_hi) { // double move?
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	730 if (is_load) {
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	731 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	732 } else {
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	733 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	734 }
0 a61af66fc99e Initial load duke parents: diff changeset	735 } else {
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	736 if (is_load) {
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	737 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	738 } else {
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	739 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	740 }
0 a61af66fc99e Initial load duke parents: diff changeset	741 }
a61af66fc99e Initial load duke parents: diff changeset	742 #ifndef PRODUCT
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	743 } else if (!do_size) {
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	744 if (size != 0) st->print("\n\t");
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	745 if (reg_lo+1 == reg_hi) { // double move?
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	746 if (is_load) st->print("%s %s,[ESP + #%d]",
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	747 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	748 Matcher::regName[reg_lo], offset);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	749 else st->print("MOVSD [ESP + #%d],%s",
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	750 offset, Matcher::regName[reg_lo]);
0 a61af66fc99e Initial load duke parents: diff changeset	751 } else {
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	752 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	753 Matcher::regName[reg_lo], offset);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	754 else st->print("MOVSS [ESP + #%d],%s",
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	755 offset, Matcher::regName[reg_lo]);
0 a61af66fc99e Initial load duke parents: diff changeset	756 }
a61af66fc99e Initial load duke parents: diff changeset	757 #endif
a61af66fc99e Initial load duke parents: diff changeset	758 }
a61af66fc99e Initial load duke parents: diff changeset	759 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	760 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
0 a61af66fc99e Initial load duke parents: diff changeset	761 return size+5+offset_size;
a61af66fc99e Initial load duke parents: diff changeset	762 }
a61af66fc99e Initial load duke parents: diff changeset	763
a61af66fc99e Initial load duke parents: diff changeset	764
a61af66fc99e Initial load duke parents: diff changeset	765 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	766 int src_hi, int dst_hi, int size, outputStream* st ) {
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	767 if (cbuf) {
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	768 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	769 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	770 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	771 as_XMMRegister(Matcher::_regEncode[src_lo]));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	772 } else {
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	773 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	774 as_XMMRegister(Matcher::_regEncode[src_lo]));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	775 }
0 a61af66fc99e Initial load duke parents: diff changeset	776 #ifndef PRODUCT
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	777 } else if (!do_size) {
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	778 if (size != 0) st->print("\n\t");
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	779 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	780 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	781 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
0 a61af66fc99e Initial load duke parents: diff changeset	782 } else {
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	783 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
0 a61af66fc99e Initial load duke parents: diff changeset	784 }
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	785 } else {
0 a61af66fc99e Initial load duke parents: diff changeset	786 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	787 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
0 a61af66fc99e Initial load duke parents: diff changeset	788 } else {
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	789 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
0 a61af66fc99e Initial load duke parents: diff changeset	790 }
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	791 }
0 a61af66fc99e Initial load duke parents: diff changeset	792 #endif
a61af66fc99e Initial load duke parents: diff changeset	793 }
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	794 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	795 // Only MOVAPS SSE prefix uses 1 byte.
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	796 int sz = 4;
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	797 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	798 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	799 return size + sz;
0 a61af66fc99e Initial load duke parents: diff changeset	800 }
a61af66fc99e Initial load duke parents: diff changeset	801
1730 f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	802 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	803 int src_hi, int dst_hi, int size, outputStream* st ) {
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	804 // 32-bit
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	805 if (cbuf) {
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	806 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	807 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	808 as_Register(Matcher::_regEncode[src_lo]));
1730 f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	809 #ifndef PRODUCT
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	810 } else if (!do_size) {
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	811 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	812 #endif
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	813 }
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	814 return 4;
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	815 }
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	816
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	817
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	818 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	819 int src_hi, int dst_hi, int size, outputStream* st ) {
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	820 // 32-bit
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	821 if (cbuf) {
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	822 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	823 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	824 as_XMMRegister(Matcher::_regEncode[src_lo]));
1730 f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	825 #ifndef PRODUCT
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	826 } else if (!do_size) {
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	827 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	828 #endif
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	829 }
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	830 return 4;
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	831 }
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	832
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	833 static int impl_mov_helper( CodeBuffer cbuf, bool do_size, int src, int dst, int size, outputStream st ) {
0 a61af66fc99e Initial load duke parents: diff changeset	834 if( cbuf ) {
a61af66fc99e Initial load duke parents: diff changeset	835 emit_opcode(*cbuf, 0x8B );
a61af66fc99e Initial load duke parents: diff changeset	836 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
a61af66fc99e Initial load duke parents: diff changeset	837 #ifndef PRODUCT
a61af66fc99e Initial load duke parents: diff changeset	838 } else if( !do_size ) {
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	839 if( size != 0 ) st->print("\n\t");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	840 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
0 a61af66fc99e Initial load duke parents: diff changeset	841 #endif
a61af66fc99e Initial load duke parents: diff changeset	842 }
a61af66fc99e Initial load duke parents: diff changeset	843 return size+2;
a61af66fc99e Initial load duke parents: diff changeset	844 }
a61af66fc99e Initial load duke parents: diff changeset	845
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	846 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	847 int offset, int size, outputStream* st ) {
0 a61af66fc99e Initial load duke parents: diff changeset	848 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
a61af66fc99e Initial load duke parents: diff changeset	849 if( cbuf ) {
a61af66fc99e Initial load duke parents: diff changeset	850 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
a61af66fc99e Initial load duke parents: diff changeset	851 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
a61af66fc99e Initial load duke parents: diff changeset	852 #ifndef PRODUCT
a61af66fc99e Initial load duke parents: diff changeset	853 } else if( !do_size ) {
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	854 if( size != 0 ) st->print("\n\t");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	855 st->print("FLD %s",Matcher::regName[src_lo]);
0 a61af66fc99e Initial load duke parents: diff changeset	856 #endif
a61af66fc99e Initial load duke parents: diff changeset	857 }
a61af66fc99e Initial load duke parents: diff changeset	858 size += 2;
a61af66fc99e Initial load duke parents: diff changeset	859 }
a61af66fc99e Initial load duke parents: diff changeset	860
a61af66fc99e Initial load duke parents: diff changeset	861 int st_op = (src_lo != FPR1L_num) ? EBX_num /store & pop/ : EDX_num /store no pop/;
a61af66fc99e Initial load duke parents: diff changeset	862 const char *op_str;
a61af66fc99e Initial load duke parents: diff changeset	863 int op;
a61af66fc99e Initial load duke parents: diff changeset	864 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
a61af66fc99e Initial load duke parents: diff changeset	865 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
a61af66fc99e Initial load duke parents: diff changeset	866 op = 0xDD;
a61af66fc99e Initial load duke parents: diff changeset	867 } else { // 32-bit store
a61af66fc99e Initial load duke parents: diff changeset	868 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
a61af66fc99e Initial load duke parents: diff changeset	869 op = 0xD9;
a61af66fc99e Initial load duke parents: diff changeset	870 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
a61af66fc99e Initial load duke parents: diff changeset	871 }
a61af66fc99e Initial load duke parents: diff changeset	872
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	873 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
0 a61af66fc99e Initial load duke parents: diff changeset	874 }
a61af66fc99e Initial load duke parents: diff changeset	875
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	876 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	877 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	878 int src_hi, int dst_hi, uint ireg, outputStream* st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	879
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	880 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	881 int stack_offset, int reg, uint ireg, outputStream* st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	882
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	883 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	884 int dst_offset, uint ireg, outputStream* st) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	885 int calc_size = 0;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	886 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	887 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	888 switch (ireg) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	889 case Op_VecS:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	890 calc_size = 3+src_offset_size + 3+dst_offset_size;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	891 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	892 case Op_VecD:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	893 calc_size = 3+src_offset_size + 3+dst_offset_size;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	894 src_offset += 4;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	895 dst_offset += 4;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	896 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	897 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	898 calc_size += 3+src_offset_size + 3+dst_offset_size;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	899 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	900 case Op_VecX:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	901 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	902 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	903 case Op_VecY:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	904 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	905 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	906 default:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	907 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	908 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	909 if (cbuf) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	910 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	911 int offset = __ offset();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	912 switch (ireg) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	913 case Op_VecS:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	914 __ pushl(Address(rsp, src_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	915 __ popl (Address(rsp, dst_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	916 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	917 case Op_VecD:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	918 __ pushl(Address(rsp, src_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	919 __ popl (Address(rsp, dst_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	920 __ pushl(Address(rsp, src_offset+4));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	921 __ popl (Address(rsp, dst_offset+4));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	922 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	923 case Op_VecX:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	924 __ movdqu(Address(rsp, -16), xmm0);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	925 __ movdqu(xmm0, Address(rsp, src_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	926 __ movdqu(Address(rsp, dst_offset), xmm0);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	927 __ movdqu(xmm0, Address(rsp, -16));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	928 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	929 case Op_VecY:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	930 __ vmovdqu(Address(rsp, -32), xmm0);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	931 __ vmovdqu(xmm0, Address(rsp, src_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	932 __ vmovdqu(Address(rsp, dst_offset), xmm0);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	933 __ vmovdqu(xmm0, Address(rsp, -32));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	934 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	935 default:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	936 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	937 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	938 int size = __ offset() - offset;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	939 assert(size == calc_size, "incorrect size calculattion");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	940 return size;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	941 #ifndef PRODUCT
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	942 } else if (!do_size) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	943 switch (ireg) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	944 case Op_VecS:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	945 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	946 "popl [rsp + #%d]",
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	947 src_offset, dst_offset);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	948 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	949 case Op_VecD:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	950 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	951 "popq [rsp + #%d]\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	952 "pushl [rsp + #%d]\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	953 "popq [rsp + #%d]",
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	954 src_offset, dst_offset, src_offset+4, dst_offset+4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	955 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	956 case Op_VecX:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	957 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	958 "movdqu xmm0, [rsp + #%d]\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	959 "movdqu [rsp + #%d], xmm0\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	960 "movdqu xmm0, [rsp - #16]",
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	961 src_offset, dst_offset);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	962 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	963 case Op_VecY:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	964 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	965 "vmovdqu xmm0, [rsp + #%d]\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	966 "vmovdqu [rsp + #%d], xmm0\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	967 "vmovdqu xmm0, [rsp - #32]",
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	968 src_offset, dst_offset);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	969 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	970 default:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	971 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	972 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	973 #endif
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	974 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	975 return calc_size;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	976 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	977
0 a61af66fc99e Initial load duke parents: diff changeset	978 uint MachSpillCopyNode::implementation( CodeBuffer cbuf, PhaseRegAlloc ra_, bool do_size, outputStream* st ) const {
a61af66fc99e Initial load duke parents: diff changeset	979 // Get registers to move
a61af66fc99e Initial load duke parents: diff changeset	980 OptoReg::Name src_second = ra_->get_reg_second(in(1));
a61af66fc99e Initial load duke parents: diff changeset	981 OptoReg::Name src_first = ra_->get_reg_first(in(1));
a61af66fc99e Initial load duke parents: diff changeset	982 OptoReg::Name dst_second = ra_->get_reg_second(this );
a61af66fc99e Initial load duke parents: diff changeset	983 OptoReg::Name dst_first = ra_->get_reg_first(this );
a61af66fc99e Initial load duke parents: diff changeset	984
a61af66fc99e Initial load duke parents: diff changeset	985 enum RC src_second_rc = rc_class(src_second);
a61af66fc99e Initial load duke parents: diff changeset	986 enum RC src_first_rc = rc_class(src_first);
a61af66fc99e Initial load duke parents: diff changeset	987 enum RC dst_second_rc = rc_class(dst_second);
a61af66fc99e Initial load duke parents: diff changeset	988 enum RC dst_first_rc = rc_class(dst_first);
a61af66fc99e Initial load duke parents: diff changeset	989
a61af66fc99e Initial load duke parents: diff changeset	990 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
a61af66fc99e Initial load duke parents: diff changeset	991
a61af66fc99e Initial load duke parents: diff changeset	992 // Generate spill code!
a61af66fc99e Initial load duke parents: diff changeset	993 int size = 0;
a61af66fc99e Initial load duke parents: diff changeset	994
a61af66fc99e Initial load duke parents: diff changeset	995 if( src_first == dst_first && src_second == dst_second )
a61af66fc99e Initial load duke parents: diff changeset	996 return size; // Self copy, no move
a61af66fc99e Initial load duke parents: diff changeset	997
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	998 if (bottom_type()->isa_vect() != NULL) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	999 uint ireg = ideal_reg();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1000 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1001 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1002 assert((ireg == Op_VecS \|\| ireg == Op_VecD \|\| ireg == Op_VecX \|\| ireg == Op_VecY), "sanity");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1003 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1004 // mem -> mem
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1005 int src_offset = ra_->reg2offset(src_first);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1006 int dst_offset = ra_->reg2offset(dst_first);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1007 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1008 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1009 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1010 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1011 int stack_offset = ra_->reg2offset(dst_first);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1012 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1013 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1014 int stack_offset = ra_->reg2offset(src_first);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1015 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1016 } else {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1017 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1018 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1019 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1020
0 a61af66fc99e Initial load duke parents: diff changeset	1021 // --------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	1022 // Check for mem-mem move. push/pop to move.
a61af66fc99e Initial load duke parents: diff changeset	1023 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
a61af66fc99e Initial load duke parents: diff changeset	1024 if( src_second == dst_first ) { // overlapping stack copy ranges
a61af66fc99e Initial load duke parents: diff changeset	1025 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1026 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1027 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
0 a61af66fc99e Initial load duke parents: diff changeset	1028 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
a61af66fc99e Initial load duke parents: diff changeset	1029 }
a61af66fc99e Initial load duke parents: diff changeset	1030 // move low bits
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1031 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1032 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
0 a61af66fc99e Initial load duke parents: diff changeset	1033 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1034 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1035 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
0 a61af66fc99e Initial load duke parents: diff changeset	1036 }
a61af66fc99e Initial load duke parents: diff changeset	1037 return size;
a61af66fc99e Initial load duke parents: diff changeset	1038 }
a61af66fc99e Initial load duke parents: diff changeset	1039
a61af66fc99e Initial load duke parents: diff changeset	1040 // --------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	1041 // Check for integer reg-reg copy
a61af66fc99e Initial load duke parents: diff changeset	1042 if( src_first_rc == rc_int && dst_first_rc == rc_int )
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1043 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
0 a61af66fc99e Initial load duke parents: diff changeset	1044
a61af66fc99e Initial load duke parents: diff changeset	1045 // Check for integer store
a61af66fc99e Initial load duke parents: diff changeset	1046 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1047 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
0 a61af66fc99e Initial load duke parents: diff changeset	1048
a61af66fc99e Initial load duke parents: diff changeset	1049 // Check for integer load
a61af66fc99e Initial load duke parents: diff changeset	1050 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1051 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
0 a61af66fc99e Initial load duke parents: diff changeset	1052
1730 f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	1053 // Check for integer reg-xmm reg copy
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	1054 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	1055 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	1056 "no 64 bit integer-float reg moves" );
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	1057 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	1058 }
0 a61af66fc99e Initial load duke parents: diff changeset	1059 // --------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	1060 // Check for float reg-reg copy
a61af66fc99e Initial load duke parents: diff changeset	1061 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
a61af66fc99e Initial load duke parents: diff changeset	1062 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) \|\|
a61af66fc99e Initial load duke parents: diff changeset	1063 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
a61af66fc99e Initial load duke parents: diff changeset	1064 if( cbuf ) {
a61af66fc99e Initial load duke parents: diff changeset	1065
a61af66fc99e Initial load duke parents: diff changeset	1066 // Note the mucking with the register encode to compensate for the 0/1
a61af66fc99e Initial load duke parents: diff changeset	1067 // indexing issue mentioned in a comment in the reg_def sections
a61af66fc99e Initial load duke parents: diff changeset	1068 // for FPR registers many lines above here.
a61af66fc99e Initial load duke parents: diff changeset	1069
a61af66fc99e Initial load duke parents: diff changeset	1070 if( src_first != FPR1L_num ) {
a61af66fc99e Initial load duke parents: diff changeset	1071 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
a61af66fc99e Initial load duke parents: diff changeset	1072 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
a61af66fc99e Initial load duke parents: diff changeset	1073 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
a61af66fc99e Initial load duke parents: diff changeset	1074 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
a61af66fc99e Initial load duke parents: diff changeset	1075 } else {
a61af66fc99e Initial load duke parents: diff changeset	1076 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
a61af66fc99e Initial load duke parents: diff changeset	1077 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
a61af66fc99e Initial load duke parents: diff changeset	1078 }
a61af66fc99e Initial load duke parents: diff changeset	1079 #ifndef PRODUCT
a61af66fc99e Initial load duke parents: diff changeset	1080 } else if( !do_size ) {
a61af66fc99e Initial load duke parents: diff changeset	1081 if( size != 0 ) st->print("\n\t");
a61af66fc99e Initial load duke parents: diff changeset	1082 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
a61af66fc99e Initial load duke parents: diff changeset	1083 else st->print( "FST %s", Matcher::regName[dst_first]);
a61af66fc99e Initial load duke parents: diff changeset	1084 #endif
a61af66fc99e Initial load duke parents: diff changeset	1085 }
a61af66fc99e Initial load duke parents: diff changeset	1086 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
a61af66fc99e Initial load duke parents: diff changeset	1087 }
a61af66fc99e Initial load duke parents: diff changeset	1088
a61af66fc99e Initial load duke parents: diff changeset	1089 // Check for float store
a61af66fc99e Initial load duke parents: diff changeset	1090 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1091 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
0 a61af66fc99e Initial load duke parents: diff changeset	1092 }
a61af66fc99e Initial load duke parents: diff changeset	1093
a61af66fc99e Initial load duke parents: diff changeset	1094 // Check for float load
a61af66fc99e Initial load duke parents: diff changeset	1095 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
a61af66fc99e Initial load duke parents: diff changeset	1096 int offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load duke parents: diff changeset	1097 const char *op_str;
a61af66fc99e Initial load duke parents: diff changeset	1098 int op;
a61af66fc99e Initial load duke parents: diff changeset	1099 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
a61af66fc99e Initial load duke parents: diff changeset	1100 op_str = "FLD_D";
a61af66fc99e Initial load duke parents: diff changeset	1101 op = 0xDD;
a61af66fc99e Initial load duke parents: diff changeset	1102 } else { // 32-bit load
a61af66fc99e Initial load duke parents: diff changeset	1103 op_str = "FLD_S";
a61af66fc99e Initial load duke parents: diff changeset	1104 op = 0xD9;
a61af66fc99e Initial load duke parents: diff changeset	1105 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
a61af66fc99e Initial load duke parents: diff changeset	1106 }
a61af66fc99e Initial load duke parents: diff changeset	1107 if( cbuf ) {
a61af66fc99e Initial load duke parents: diff changeset	1108 emit_opcode (*cbuf, op );
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	1109 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
0 a61af66fc99e Initial load duke parents: diff changeset	1110 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
a61af66fc99e Initial load duke parents: diff changeset	1111 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
a61af66fc99e Initial load duke parents: diff changeset	1112 #ifndef PRODUCT
a61af66fc99e Initial load duke parents: diff changeset	1113 } else if( !do_size ) {
a61af66fc99e Initial load duke parents: diff changeset	1114 if( size != 0 ) st->print("\n\t");
a61af66fc99e Initial load duke parents: diff changeset	1115 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
a61af66fc99e Initial load duke parents: diff changeset	1116 #endif
a61af66fc99e Initial load duke parents: diff changeset	1117 }
a61af66fc99e Initial load duke parents: diff changeset	1118 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
a61af66fc99e Initial load duke parents: diff changeset	1119 return size + 3+offset_size+2;
a61af66fc99e Initial load duke parents: diff changeset	1120 }
a61af66fc99e Initial load duke parents: diff changeset	1121
a61af66fc99e Initial load duke parents: diff changeset	1122 // Check for xmm reg-reg copy
a61af66fc99e Initial load duke parents: diff changeset	1123 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
a61af66fc99e Initial load duke parents: diff changeset	1124 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) \|\|
a61af66fc99e Initial load duke parents: diff changeset	1125 (src_first+1 == src_second && dst_first+1 == dst_second),
a61af66fc99e Initial load duke parents: diff changeset	1126 "no non-adjacent float-moves" );
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1127 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
0 a61af66fc99e Initial load duke parents: diff changeset	1128 }
a61af66fc99e Initial load duke parents: diff changeset	1129
1730 f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	1130 // Check for xmm reg-integer reg copy
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	1131 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	1132 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	1133 "no 64 bit float-integer reg moves" );
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	1134 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	1135 }
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast never parents: 1579 diff changeset	1136
0 a61af66fc99e Initial load duke parents: diff changeset	1137 // Check for xmm store
a61af66fc99e Initial load duke parents: diff changeset	1138 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1139 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
0 a61af66fc99e Initial load duke parents: diff changeset	1140 }
a61af66fc99e Initial load duke parents: diff changeset	1141
a61af66fc99e Initial load duke parents: diff changeset	1142 // Check for float xmm load
a61af66fc99e Initial load duke parents: diff changeset	1143 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1144 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
0 a61af66fc99e Initial load duke parents: diff changeset	1145 }
a61af66fc99e Initial load duke parents: diff changeset	1146
a61af66fc99e Initial load duke parents: diff changeset	1147 // Copy from float reg to xmm reg
a61af66fc99e Initial load duke parents: diff changeset	1148 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
a61af66fc99e Initial load duke parents: diff changeset	1149 // copy to the top of stack from floating point reg
a61af66fc99e Initial load duke parents: diff changeset	1150 // and use LEA to preserve flags
a61af66fc99e Initial load duke parents: diff changeset	1151 if( cbuf ) {
a61af66fc99e Initial load duke parents: diff changeset	1152 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
a61af66fc99e Initial load duke parents: diff changeset	1153 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
a61af66fc99e Initial load duke parents: diff changeset	1154 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
a61af66fc99e Initial load duke parents: diff changeset	1155 emit_d8(*cbuf,0xF8);
a61af66fc99e Initial load duke parents: diff changeset	1156 #ifndef PRODUCT
a61af66fc99e Initial load duke parents: diff changeset	1157 } else if( !do_size ) {
a61af66fc99e Initial load duke parents: diff changeset	1158 if( size != 0 ) st->print("\n\t");
a61af66fc99e Initial load duke parents: diff changeset	1159 st->print("LEA ESP,[ESP-8]");
a61af66fc99e Initial load duke parents: diff changeset	1160 #endif
a61af66fc99e Initial load duke parents: diff changeset	1161 }
a61af66fc99e Initial load duke parents: diff changeset	1162 size += 4;
a61af66fc99e Initial load duke parents: diff changeset	1163
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1164 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
0 a61af66fc99e Initial load duke parents: diff changeset	1165
a61af66fc99e Initial load duke parents: diff changeset	1166 // Copy from the temp memory to the xmm reg.
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1167 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
0 a61af66fc99e Initial load duke parents: diff changeset	1168
a61af66fc99e Initial load duke parents: diff changeset	1169 if( cbuf ) {
a61af66fc99e Initial load duke parents: diff changeset	1170 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
a61af66fc99e Initial load duke parents: diff changeset	1171 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
a61af66fc99e Initial load duke parents: diff changeset	1172 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
a61af66fc99e Initial load duke parents: diff changeset	1173 emit_d8(*cbuf,0x08);
a61af66fc99e Initial load duke parents: diff changeset	1174 #ifndef PRODUCT
a61af66fc99e Initial load duke parents: diff changeset	1175 } else if( !do_size ) {
a61af66fc99e Initial load duke parents: diff changeset	1176 if( size != 0 ) st->print("\n\t");
a61af66fc99e Initial load duke parents: diff changeset	1177 st->print("LEA ESP,[ESP+8]");
a61af66fc99e Initial load duke parents: diff changeset	1178 #endif
a61af66fc99e Initial load duke parents: diff changeset	1179 }
a61af66fc99e Initial load duke parents: diff changeset	1180 size += 4;
a61af66fc99e Initial load duke parents: diff changeset	1181 return size;
a61af66fc99e Initial load duke parents: diff changeset	1182 }
a61af66fc99e Initial load duke parents: diff changeset	1183
a61af66fc99e Initial load duke parents: diff changeset	1184 assert( size > 0, "missed a case" );
a61af66fc99e Initial load duke parents: diff changeset	1185
a61af66fc99e Initial load duke parents: diff changeset	1186 // --------------------------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	1187 // Check for second bits still needing moving.
a61af66fc99e Initial load duke parents: diff changeset	1188 if( src_second == dst_second )
a61af66fc99e Initial load duke parents: diff changeset	1189 return size; // Self copy; no move
a61af66fc99e Initial load duke parents: diff changeset	1190 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
a61af66fc99e Initial load duke parents: diff changeset	1191
a61af66fc99e Initial load duke parents: diff changeset	1192 // Check for second word int-int move
a61af66fc99e Initial load duke parents: diff changeset	1193 if( src_second_rc == rc_int && dst_second_rc == rc_int )
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1194 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
0 a61af66fc99e Initial load duke parents: diff changeset	1195
a61af66fc99e Initial load duke parents: diff changeset	1196 // Check for second word integer store
a61af66fc99e Initial load duke parents: diff changeset	1197 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1198 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
0 a61af66fc99e Initial load duke parents: diff changeset	1199
a61af66fc99e Initial load duke parents: diff changeset	1200 // Check for second word integer load
a61af66fc99e Initial load duke parents: diff changeset	1201 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1202 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
0 a61af66fc99e Initial load duke parents: diff changeset	1203
a61af66fc99e Initial load duke parents: diff changeset	1204
a61af66fc99e Initial load duke parents: diff changeset	1205 Unimplemented();
a61af66fc99e Initial load duke parents: diff changeset	1206 }
a61af66fc99e Initial load duke parents: diff changeset	1207
a61af66fc99e Initial load duke parents: diff changeset	1208 #ifndef PRODUCT
4950 9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	1209 void MachSpillCopyNode::format(PhaseRegAlloc ra_, outputStream st) const {
0 a61af66fc99e Initial load duke parents: diff changeset	1210 implementation( NULL, ra_, false, st );
a61af66fc99e Initial load duke parents: diff changeset	1211 }
a61af66fc99e Initial load duke parents: diff changeset	1212 #endif
a61af66fc99e Initial load duke parents: diff changeset	1213
a61af66fc99e Initial load duke parents: diff changeset	1214 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load duke parents: diff changeset	1215 implementation( &cbuf, ra_, false, NULL );
a61af66fc99e Initial load duke parents: diff changeset	1216 }
a61af66fc99e Initial load duke parents: diff changeset	1217
a61af66fc99e Initial load duke parents: diff changeset	1218 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load duke parents: diff changeset	1219 return implementation( NULL, ra_, true, NULL );
a61af66fc99e Initial load duke parents: diff changeset	1220 }
a61af66fc99e Initial load duke parents: diff changeset	1221
a61af66fc99e Initial load duke parents: diff changeset	1222
a61af66fc99e Initial load duke parents: diff changeset	1223 //=============================================================================
a61af66fc99e Initial load duke parents: diff changeset	1224 #ifndef PRODUCT
a61af66fc99e Initial load duke parents: diff changeset	1225 void BoxLockNode::format( PhaseRegAlloc ra_, outputStream st ) const {
a61af66fc99e Initial load duke parents: diff changeset	1226 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
a61af66fc99e Initial load duke parents: diff changeset	1227 int reg = ra_->get_reg_first(this);
a61af66fc99e Initial load duke parents: diff changeset	1228 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
a61af66fc99e Initial load duke parents: diff changeset	1229 }
a61af66fc99e Initial load duke parents: diff changeset	1230 #endif
a61af66fc99e Initial load duke parents: diff changeset	1231
a61af66fc99e Initial load duke parents: diff changeset	1232 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load duke parents: diff changeset	1233 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
a61af66fc99e Initial load duke parents: diff changeset	1234 int reg = ra_->get_encode(this);
a61af66fc99e Initial load duke parents: diff changeset	1235 if( offset >= 128 ) {
a61af66fc99e Initial load duke parents: diff changeset	1236 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
a61af66fc99e Initial load duke parents: diff changeset	1237 emit_rm(cbuf, 0x2, reg, 0x04);
a61af66fc99e Initial load duke parents: diff changeset	1238 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
a61af66fc99e Initial load duke parents: diff changeset	1239 emit_d32(cbuf, offset);
a61af66fc99e Initial load duke parents: diff changeset	1240 }
a61af66fc99e Initial load duke parents: diff changeset	1241 else {
a61af66fc99e Initial load duke parents: diff changeset	1242 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
a61af66fc99e Initial load duke parents: diff changeset	1243 emit_rm(cbuf, 0x1, reg, 0x04);
a61af66fc99e Initial load duke parents: diff changeset	1244 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
a61af66fc99e Initial load duke parents: diff changeset	1245 emit_d8(cbuf, offset);
a61af66fc99e Initial load duke parents: diff changeset	1246 }
a61af66fc99e Initial load duke parents: diff changeset	1247 }
a61af66fc99e Initial load duke parents: diff changeset	1248
a61af66fc99e Initial load duke parents: diff changeset	1249 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load duke parents: diff changeset	1250 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
a61af66fc99e Initial load duke parents: diff changeset	1251 if( offset >= 128 ) {
a61af66fc99e Initial load duke parents: diff changeset	1252 return 7;
a61af66fc99e Initial load duke parents: diff changeset	1253 }
a61af66fc99e Initial load duke parents: diff changeset	1254 else {
a61af66fc99e Initial load duke parents: diff changeset	1255 return 4;
a61af66fc99e Initial load duke parents: diff changeset	1256 }
a61af66fc99e Initial load duke parents: diff changeset	1257 }
a61af66fc99e Initial load duke parents: diff changeset	1258
a61af66fc99e Initial load duke parents: diff changeset	1259 //=============================================================================
a61af66fc99e Initial load duke parents: diff changeset	1260 #ifndef PRODUCT
a61af66fc99e Initial load duke parents: diff changeset	1261 void MachUEPNode::format( PhaseRegAlloc ra_, outputStream st ) const {
a61af66fc99e Initial load duke parents: diff changeset	1262 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
a61af66fc99e Initial load duke parents: diff changeset	1263 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
a61af66fc99e Initial load duke parents: diff changeset	1264 st->print_cr("\tNOP");
a61af66fc99e Initial load duke parents: diff changeset	1265 st->print_cr("\tNOP");
a61af66fc99e Initial load duke parents: diff changeset	1266 if( !OptoBreakpoint )
a61af66fc99e Initial load duke parents: diff changeset	1267 st->print_cr("\tNOP");
a61af66fc99e Initial load duke parents: diff changeset	1268 }
a61af66fc99e Initial load duke parents: diff changeset	1269 #endif
a61af66fc99e Initial load duke parents: diff changeset	1270
a61af66fc99e Initial load duke parents: diff changeset	1271 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load duke parents: diff changeset	1272 MacroAssembler masm(&cbuf);
a61af66fc99e Initial load duke parents: diff changeset	1273 #ifdef ASSERT
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	1274 uint insts_size = cbuf.insts_size();
0 a61af66fc99e Initial load duke parents: diff changeset	1275 #endif
304 dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories never parents: 235 diff changeset	1276 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
0 a61af66fc99e Initial load duke parents: diff changeset	1277 masm.jump_cc(Assembler::notEqual,
a61af66fc99e Initial load duke parents: diff changeset	1278 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
a61af66fc99e Initial load duke parents: diff changeset	1279 /* WARNING these NOPs are critical so that verified entry point is properly
a61af66fc99e Initial load duke parents: diff changeset	1280 aligned for patching by NativeJump::patch_verified_entry() */
a61af66fc99e Initial load duke parents: diff changeset	1281 int nops_cnt = 2;
a61af66fc99e Initial load duke parents: diff changeset	1282 if( !OptoBreakpoint ) // Leave space for int3
a61af66fc99e Initial load duke parents: diff changeset	1283 nops_cnt += 1;
a61af66fc99e Initial load duke parents: diff changeset	1284 masm.nop(nops_cnt);
a61af66fc99e Initial load duke parents: diff changeset	1285
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	1286 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
0 a61af66fc99e Initial load duke parents: diff changeset	1287 }
a61af66fc99e Initial load duke parents: diff changeset	1288
a61af66fc99e Initial load duke parents: diff changeset	1289 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
a61af66fc99e Initial load duke parents: diff changeset	1290 return OptoBreakpoint ? 11 : 12;
a61af66fc99e Initial load duke parents: diff changeset	1291 }
a61af66fc99e Initial load duke parents: diff changeset	1292
a61af66fc99e Initial load duke parents: diff changeset	1293
a61af66fc99e Initial load duke parents: diff changeset	1294 //=============================================================================
a61af66fc99e Initial load duke parents: diff changeset	1295 uint size_exception_handler() {
a61af66fc99e Initial load duke parents: diff changeset	1296 // NativeCall instruction size is the same as NativeJump.
a61af66fc99e Initial load duke parents: diff changeset	1297 // exception handler starts out as jump and can be patched to
a61af66fc99e Initial load duke parents: diff changeset	1298 // a call be deoptimization. (4932387)
a61af66fc99e Initial load duke parents: diff changeset	1299 // Note that this value is also credited (in output.cpp) to
a61af66fc99e Initial load duke parents: diff changeset	1300 // the size of the code section.
a61af66fc99e Initial load duke parents: diff changeset	1301 return NativeJump::instruction_size;
a61af66fc99e Initial load duke parents: diff changeset	1302 }
a61af66fc99e Initial load duke parents: diff changeset	1303
a61af66fc99e Initial load duke parents: diff changeset	1304 // Emit exception handler code. Stuff framesize into a register
a61af66fc99e Initial load duke parents: diff changeset	1305 // and call a VM stub routine.
a61af66fc99e Initial load duke parents: diff changeset	1306 int emit_exception_handler(CodeBuffer& cbuf) {
a61af66fc99e Initial load duke parents: diff changeset	1307
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	1308 // Note that the code buffer's insts_mark is always relative to insts.
0 a61af66fc99e Initial load duke parents: diff changeset	1309 // That's why we must use the macroassembler to generate a handler.
a61af66fc99e Initial load duke parents: diff changeset	1310 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load duke parents: diff changeset	1311 address base =
a61af66fc99e Initial load duke parents: diff changeset	1312 __ start_a_stub(size_exception_handler());
a61af66fc99e Initial load duke parents: diff changeset	1313 if (base == NULL) return 0; // CodeBuffer::expand failed
a61af66fc99e Initial load duke parents: diff changeset	1314 int offset = __ offset();
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	1315 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
0 a61af66fc99e Initial load duke parents: diff changeset	1316 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
a61af66fc99e Initial load duke parents: diff changeset	1317 __ end_a_stub();
a61af66fc99e Initial load duke parents: diff changeset	1318 return offset;
a61af66fc99e Initial load duke parents: diff changeset	1319 }
a61af66fc99e Initial load duke parents: diff changeset	1320
a61af66fc99e Initial load duke parents: diff changeset	1321 uint size_deopt_handler() {
a61af66fc99e Initial load duke parents: diff changeset	1322 // NativeCall instruction size is the same as NativeJump.
a61af66fc99e Initial load duke parents: diff changeset	1323 // exception handler starts out as jump and can be patched to
a61af66fc99e Initial load duke parents: diff changeset	1324 // a call be deoptimization. (4932387)
a61af66fc99e Initial load duke parents: diff changeset	1325 // Note that this value is also credited (in output.cpp) to
a61af66fc99e Initial load duke parents: diff changeset	1326 // the size of the code section.
a61af66fc99e Initial load duke parents: diff changeset	1327 return 5 + NativeJump::instruction_size; // pushl(); jmp;
a61af66fc99e Initial load duke parents: diff changeset	1328 }
a61af66fc99e Initial load duke parents: diff changeset	1329
a61af66fc99e Initial load duke parents: diff changeset	1330 // Emit deopt handler code.
a61af66fc99e Initial load duke parents: diff changeset	1331 int emit_deopt_handler(CodeBuffer& cbuf) {
a61af66fc99e Initial load duke parents: diff changeset	1332
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	1333 // Note that the code buffer's insts_mark is always relative to insts.
0 a61af66fc99e Initial load duke parents: diff changeset	1334 // That's why we must use the macroassembler to generate a handler.
a61af66fc99e Initial load duke parents: diff changeset	1335 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load duke parents: diff changeset	1336 address base =
a61af66fc99e Initial load duke parents: diff changeset	1337 __ start_a_stub(size_exception_handler());
a61af66fc99e Initial load duke parents: diff changeset	1338 if (base == NULL) return 0; // CodeBuffer::expand failed
a61af66fc99e Initial load duke parents: diff changeset	1339 int offset = __ offset();
a61af66fc99e Initial load duke parents: diff changeset	1340 InternalAddress here(__ pc());
a61af66fc99e Initial load duke parents: diff changeset	1341 __ pushptr(here.addr());
a61af66fc99e Initial load duke parents: diff changeset	1342
a61af66fc99e Initial load duke parents: diff changeset	1343 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
a61af66fc99e Initial load duke parents: diff changeset	1344 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
a61af66fc99e Initial load duke parents: diff changeset	1345 __ end_a_stub();
a61af66fc99e Initial load duke parents: diff changeset	1346 return offset;
a61af66fc99e Initial load duke parents: diff changeset	1347 }
a61af66fc99e Initial load duke parents: diff changeset	1348
a61af66fc99e Initial load duke parents: diff changeset	1349 int Matcher::regnum_to_fpu_offset(int regnum) {
a61af66fc99e Initial load duke parents: diff changeset	1350 return regnum - 32; // The FP registers are in the second chunk
a61af66fc99e Initial load duke parents: diff changeset	1351 }
a61af66fc99e Initial load duke parents: diff changeset	1352
a61af66fc99e Initial load duke parents: diff changeset	1353 // This is UltraSparc specific, true just means we have fast l2f conversion
a61af66fc99e Initial load duke parents: diff changeset	1354 const bool Matcher::convL2FSupported(void) {
a61af66fc99e Initial load duke parents: diff changeset	1355 return true;
a61af66fc99e Initial load duke parents: diff changeset	1356 }
a61af66fc99e Initial load duke parents: diff changeset	1357
a61af66fc99e Initial load duke parents: diff changeset	1358 // Is this branch offset short enough that a short branch can be used?
a61af66fc99e Initial load duke parents: diff changeset	1359 //
a61af66fc99e Initial load duke parents: diff changeset	1360 // NOTE: If the platform does not provide any short branch variants, then
a61af66fc99e Initial load duke parents: diff changeset	1361 // this method should return false for offset 0.
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	1362 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	1363 // The passed offset is relative to address of the branch.
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	1364 // On 86 a branch displacement is calculated relative to address
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	1365 // of a next instruction.
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	1366 offset -= br_size;
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	1367
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1368 // the short version of jmpConUCF2 contains multiple branches,
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1369 // making the reach slightly less
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1370 if (rule == jmpConUCF2_rule)
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	1371 return (-126 <= offset && offset <= 125);
0 a61af66fc99e Initial load duke parents: diff changeset	1372 return (-128 <= offset && offset <= 127);
a61af66fc99e Initial load duke parents: diff changeset	1373 }
a61af66fc99e Initial load duke parents: diff changeset	1374
a61af66fc99e Initial load duke parents: diff changeset	1375 const bool Matcher::isSimpleConstant64(jlong value) {
a61af66fc99e Initial load duke parents: diff changeset	1376 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
a61af66fc99e Initial load duke parents: diff changeset	1377 return false;
a61af66fc99e Initial load duke parents: diff changeset	1378 }
a61af66fc99e Initial load duke parents: diff changeset	1379
a61af66fc99e Initial load duke parents: diff changeset	1380 // The ecx parameter to rep stos for the ClearArray node is in dwords.
a61af66fc99e Initial load duke parents: diff changeset	1381 const bool Matcher::init_array_count_is_in_bytes = false;
a61af66fc99e Initial load duke parents: diff changeset	1382
a61af66fc99e Initial load duke parents: diff changeset	1383 // Threshold size for cleararray.
a61af66fc99e Initial load duke parents: diff changeset	1384 const int Matcher::init_array_short_size = 8 * BytesPerLong;
a61af66fc99e Initial load duke parents: diff changeset	1385
4047 d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	1386 // Needs 2 CMOV's for longs.
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	1387 const int Matcher::long_cmove_cost() { return 1; }
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	1388
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	1389 // No CMOVF/CMOVD with SSE/SSE2
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	1390 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	1391
0 a61af66fc99e Initial load duke parents: diff changeset	1392 // Should the Matcher clone shifts on addressing modes, expecting them to
a61af66fc99e Initial load duke parents: diff changeset	1393 // be subsumed into complex addressing expressions or compute them into
a61af66fc99e Initial load duke parents: diff changeset	1394 // registers? True for Intel but false for most RISCs
a61af66fc99e Initial load duke parents: diff changeset	1395 const bool Matcher::clone_shift_expressions = true;
a61af66fc99e Initial load duke parents: diff changeset	1396
2401 7e88bdae86ec 7029017: Additional architecture support for c2 compiler roland parents: 2320 diff changeset	1397 // Do we need to mask the count passed to shift instructions or does
7e88bdae86ec 7029017: Additional architecture support for c2 compiler roland parents: 2320 diff changeset	1398 // the cpu only look at the lower 5/6 bits anyway?
7e88bdae86ec 7029017: Additional architecture support for c2 compiler roland parents: 2320 diff changeset	1399 const bool Matcher::need_masked_shift_count = false;
7e88bdae86ec 7029017: Additional architecture support for c2 compiler roland parents: 2320 diff changeset	1400
1575 3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops kvn parents: 1567 diff changeset	1401 bool Matcher::narrow_oop_use_complex_address() {
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops kvn parents: 1567 diff changeset	1402 ShouldNotCallThis();
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops kvn parents: 1567 diff changeset	1403 return true;
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops kvn parents: 1567 diff changeset	1404 }
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops kvn parents: 1567 diff changeset	1405
6848 8e47bac5643a 7054512: Compress class pointers after perm gen removal roland parents: 6795 diff changeset	1406 bool Matcher::narrow_klass_use_complex_address() {
8e47bac5643a 7054512: Compress class pointers after perm gen removal roland parents: 6795 diff changeset	1407 ShouldNotCallThis();
8e47bac5643a 7054512: Compress class pointers after perm gen removal roland parents: 6795 diff changeset	1408 return true;
8e47bac5643a 7054512: Compress class pointers after perm gen removal roland parents: 6795 diff changeset	1409 }
8e47bac5643a 7054512: Compress class pointers after perm gen removal roland parents: 6795 diff changeset	1410
1575 3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops kvn parents: 1567 diff changeset	1411
0 a61af66fc99e Initial load duke parents: diff changeset	1412 // Is it better to copy float constants, or load them directly from memory?
a61af66fc99e Initial load duke parents: diff changeset	1413 // Intel can load a float constant from a direct address, requiring no
a61af66fc99e Initial load duke parents: diff changeset	1414 // extra registers. Most RISCs will have to materialize an address into a
a61af66fc99e Initial load duke parents: diff changeset	1415 // register first, so they would do better to copy the constant from stack.
a61af66fc99e Initial load duke parents: diff changeset	1416 const bool Matcher::rematerialize_float_constants = true;
a61af66fc99e Initial load duke parents: diff changeset	1417
a61af66fc99e Initial load duke parents: diff changeset	1418 // If CPU can load and store mis-aligned doubles directly then no fixup is
a61af66fc99e Initial load duke parents: diff changeset	1419 // needed. Else we split the double into 2 integer pieces and move it
a61af66fc99e Initial load duke parents: diff changeset	1420 // piece-by-piece. Only happens when passing doubles into C code as the
a61af66fc99e Initial load duke parents: diff changeset	1421 // Java calling convention forces doubles to be aligned.
a61af66fc99e Initial load duke parents: diff changeset	1422 const bool Matcher::misaligned_doubles_ok = true;
a61af66fc99e Initial load duke parents: diff changeset	1423
a61af66fc99e Initial load duke parents: diff changeset	1424
a61af66fc99e Initial load duke parents: diff changeset	1425 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
a61af66fc99e Initial load duke parents: diff changeset	1426 // Get the memory operand from the node
a61af66fc99e Initial load duke parents: diff changeset	1427 uint numopnds = node->num_opnds(); // Virtual call for number of operands
a61af66fc99e Initial load duke parents: diff changeset	1428 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
a61af66fc99e Initial load duke parents: diff changeset	1429 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
a61af66fc99e Initial load duke parents: diff changeset	1430 uint opcnt = 1; // First operand
a61af66fc99e Initial load duke parents: diff changeset	1431 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
a61af66fc99e Initial load duke parents: diff changeset	1432 while( idx >= skipped+num_edges ) {
a61af66fc99e Initial load duke parents: diff changeset	1433 skipped += num_edges;
a61af66fc99e Initial load duke parents: diff changeset	1434 opcnt++; // Bump operand count
a61af66fc99e Initial load duke parents: diff changeset	1435 assert( opcnt < numopnds, "Accessing non-existent operand" );
a61af66fc99e Initial load duke parents: diff changeset	1436 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
a61af66fc99e Initial load duke parents: diff changeset	1437 }
a61af66fc99e Initial load duke parents: diff changeset	1438
a61af66fc99e Initial load duke parents: diff changeset	1439 MachOper *memory = node->_opnds[opcnt];
a61af66fc99e Initial load duke parents: diff changeset	1440 MachOper *new_memory = NULL;
a61af66fc99e Initial load duke parents: diff changeset	1441 switch (memory->opcode()) {
a61af66fc99e Initial load duke parents: diff changeset	1442 case DIRECT:
a61af66fc99e Initial load duke parents: diff changeset	1443 case INDOFFSET32X:
a61af66fc99e Initial load duke parents: diff changeset	1444 // No transformation necessary.
a61af66fc99e Initial load duke parents: diff changeset	1445 return;
a61af66fc99e Initial load duke parents: diff changeset	1446 case INDIRECT:
a61af66fc99e Initial load duke parents: diff changeset	1447 new_memory = new (C) indirect_win95_safeOper( );
a61af66fc99e Initial load duke parents: diff changeset	1448 break;
a61af66fc99e Initial load duke parents: diff changeset	1449 case INDOFFSET8:
a61af66fc99e Initial load duke parents: diff changeset	1450 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
a61af66fc99e Initial load duke parents: diff changeset	1451 break;
a61af66fc99e Initial load duke parents: diff changeset	1452 case INDOFFSET32:
a61af66fc99e Initial load duke parents: diff changeset	1453 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
a61af66fc99e Initial load duke parents: diff changeset	1454 break;
a61af66fc99e Initial load duke parents: diff changeset	1455 case INDINDEXOFFSET:
a61af66fc99e Initial load duke parents: diff changeset	1456 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
a61af66fc99e Initial load duke parents: diff changeset	1457 break;
a61af66fc99e Initial load duke parents: diff changeset	1458 case INDINDEXSCALE:
a61af66fc99e Initial load duke parents: diff changeset	1459 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
a61af66fc99e Initial load duke parents: diff changeset	1460 break;
a61af66fc99e Initial load duke parents: diff changeset	1461 case INDINDEXSCALEOFFSET:
a61af66fc99e Initial load duke parents: diff changeset	1462 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
a61af66fc99e Initial load duke parents: diff changeset	1463 break;
a61af66fc99e Initial load duke parents: diff changeset	1464 case LOAD_LONG_INDIRECT:
a61af66fc99e Initial load duke parents: diff changeset	1465 case LOAD_LONG_INDOFFSET32:
a61af66fc99e Initial load duke parents: diff changeset	1466 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
a61af66fc99e Initial load duke parents: diff changeset	1467 return;
a61af66fc99e Initial load duke parents: diff changeset	1468 default:
a61af66fc99e Initial load duke parents: diff changeset	1469 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
a61af66fc99e Initial load duke parents: diff changeset	1470 return;
a61af66fc99e Initial load duke parents: diff changeset	1471 }
a61af66fc99e Initial load duke parents: diff changeset	1472 node->_opnds[opcnt] = new_memory;
a61af66fc99e Initial load duke parents: diff changeset	1473 }
a61af66fc99e Initial load duke parents: diff changeset	1474
a61af66fc99e Initial load duke parents: diff changeset	1475 // Advertise here if the CPU requires explicit rounding operations
a61af66fc99e Initial load duke parents: diff changeset	1476 // to implement the UseStrictFP mode.
a61af66fc99e Initial load duke parents: diff changeset	1477 const bool Matcher::strict_fp_requires_explicit_rounding = true;
a61af66fc99e Initial load duke parents: diff changeset	1478
1274 2883969d09e7 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag kvn parents: 1209 diff changeset	1479 // Are floats conerted to double when stored to stack during deoptimization?
2883969d09e7 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag kvn parents: 1209 diff changeset	1480 // On x32 it is stored with convertion only when FPU is used for floats.
2883969d09e7 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag kvn parents: 1209 diff changeset	1481 bool Matcher::float_in_double() { return (UseSSE == 0); }
2883969d09e7 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag kvn parents: 1209 diff changeset	1482
0 a61af66fc99e Initial load duke parents: diff changeset	1483 // Do ints take an entire long register or just half?
a61af66fc99e Initial load duke parents: diff changeset	1484 const bool Matcher::int_in_long = false;
a61af66fc99e Initial load duke parents: diff changeset	1485
a61af66fc99e Initial load duke parents: diff changeset	1486 // Return whether or not this register is ever used as an argument. This
a61af66fc99e Initial load duke parents: diff changeset	1487 // function is used on startup to build the trampoline stubs in generateOptoStub.
a61af66fc99e Initial load duke parents: diff changeset	1488 // Registers not mentioned will be killed by the VM call in the trampoline, and
a61af66fc99e Initial load duke parents: diff changeset	1489 // arguments in those registers not be available to the callee.
a61af66fc99e Initial load duke parents: diff changeset	1490 bool Matcher::can_be_java_arg( int reg ) {
a61af66fc99e Initial load duke parents: diff changeset	1491 if( reg == ECX_num \|\| reg == EDX_num ) return true;
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1492 if( (reg == XMM0_num \|\| reg == XMM1_num ) && UseSSE>=1 ) return true;
0 a61af66fc99e Initial load duke parents: diff changeset	1493 if( (reg == XMM0b_num \|\| reg == XMM1b_num) && UseSSE>=2 ) return true;
a61af66fc99e Initial load duke parents: diff changeset	1494 return false;
a61af66fc99e Initial load duke parents: diff changeset	1495 }
a61af66fc99e Initial load duke parents: diff changeset	1496
a61af66fc99e Initial load duke parents: diff changeset	1497 bool Matcher::is_spillable_arg( int reg ) {
a61af66fc99e Initial load duke parents: diff changeset	1498 return can_be_java_arg(reg);
a61af66fc99e Initial load duke parents: diff changeset	1499 }
a61af66fc99e Initial load duke parents: diff changeset	1500
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	1501 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	1502 // Use hardware integer DIV instruction when
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	1503 // it is faster than a code which use multiply.
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	1504 // Only when constant divisor fits into 32 bit
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	1505 // (min_jint is excluded to get only correct
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	1506 // positive 32 bit values from negative).
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	1507 return VM_Version::has_fast_idiv() &&
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	1508 (divisor == (int)divisor && divisor != min_jint);
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	1509 }
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	1510
0 a61af66fc99e Initial load duke parents: diff changeset	1511 // Register for DIVI projection of divmodI
a61af66fc99e Initial load duke parents: diff changeset	1512 RegMask Matcher::divI_proj_mask() {
4121 db2e64ca2d5a 7090968: Allow adlc register class to depend on runtime conditions roland parents: 4114 diff changeset	1513 return EAX_REG_mask();
0 a61af66fc99e Initial load duke parents: diff changeset	1514 }
a61af66fc99e Initial load duke parents: diff changeset	1515
a61af66fc99e Initial load duke parents: diff changeset	1516 // Register for MODI projection of divmodI
a61af66fc99e Initial load duke parents: diff changeset	1517 RegMask Matcher::modI_proj_mask() {
4121 db2e64ca2d5a 7090968: Allow adlc register class to depend on runtime conditions roland parents: 4114 diff changeset	1518 return EDX_REG_mask();
0 a61af66fc99e Initial load duke parents: diff changeset	1519 }
a61af66fc99e Initial load duke parents: diff changeset	1520
a61af66fc99e Initial load duke parents: diff changeset	1521 // Register for DIVL projection of divmodL
a61af66fc99e Initial load duke parents: diff changeset	1522 RegMask Matcher::divL_proj_mask() {
a61af66fc99e Initial load duke parents: diff changeset	1523 ShouldNotReachHere();
a61af66fc99e Initial load duke parents: diff changeset	1524 return RegMask();
a61af66fc99e Initial load duke parents: diff changeset	1525 }
a61af66fc99e Initial load duke parents: diff changeset	1526
a61af66fc99e Initial load duke parents: diff changeset	1527 // Register for MODL projection of divmodL
a61af66fc99e Initial load duke parents: diff changeset	1528 RegMask Matcher::modL_proj_mask() {
a61af66fc99e Initial load duke parents: diff changeset	1529 ShouldNotReachHere();
a61af66fc99e Initial load duke parents: diff changeset	1530 return RegMask();
a61af66fc99e Initial load duke parents: diff changeset	1531 }
a61af66fc99e Initial load duke parents: diff changeset	1532
1137 97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	1533 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
4121 db2e64ca2d5a 7090968: Allow adlc register class to depend on runtime conditions roland parents: 4114 diff changeset	1534 return EBP_REG_mask();
1137 97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	1535 }
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	1536
14909 4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	1537 const RegMask Matcher::mathExactI_result_proj_mask() {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	1538 return EAX_REG_mask();
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	1539 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	1540
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	1541 const RegMask Matcher::mathExactL_result_proj_mask() {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	1542 ShouldNotReachHere();
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	1543 return RegMask();
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	1544 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	1545
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	1546 const RegMask Matcher::mathExactI_flags_proj_mask() {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	1547 return INT_FLAGS_mask();
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	1548 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	1549
1209 e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	1550 // Returns true if the high 32 bits of the value is known to be zero.
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	1551 bool is_operand_hi32_zero(Node* n) {
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	1552 int opc = n->Opcode();
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	1553 if (opc == Op_AndL) {
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	1554 Node* o2 = n->in(2);
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	1555 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	1556 return true;
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	1557 }
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	1558 }
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	1559 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	1560 return true;
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	1561 }
1209 e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	1562 return false;
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	1563 }
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	1564
0 a61af66fc99e Initial load duke parents: diff changeset	1565 %}
a61af66fc99e Initial load duke parents: diff changeset	1566
a61af66fc99e Initial load duke parents: diff changeset	1567 //----------ENCODING BLOCK-----------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	1568 // This block specifies the encoding classes used by the compiler to output
a61af66fc99e Initial load duke parents: diff changeset	1569 // byte streams. Encoding classes generate functions which are called by
a61af66fc99e Initial load duke parents: diff changeset	1570 // Machine Instruction Nodes in order to generate the bit encoding of the
a61af66fc99e Initial load duke parents: diff changeset	1571 // instruction. Operands specify their base encoding interface with the
a61af66fc99e Initial load duke parents: diff changeset	1572 // interface keyword. There are currently supported four interfaces,
a61af66fc99e Initial load duke parents: diff changeset	1573 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
a61af66fc99e Initial load duke parents: diff changeset	1574 // operand to generate a function which returns its register number when
a61af66fc99e Initial load duke parents: diff changeset	1575 // queried. CONST_INTER causes an operand to generate a function which
a61af66fc99e Initial load duke parents: diff changeset	1576 // returns the value of the constant when queried. MEMORY_INTER causes an
a61af66fc99e Initial load duke parents: diff changeset	1577 // operand to generate four functions which return the Base Register, the
a61af66fc99e Initial load duke parents: diff changeset	1578 // Index Register, the Scale Value, and the Offset Value of the operand when
a61af66fc99e Initial load duke parents: diff changeset	1579 // queried. COND_INTER causes an operand to generate six functions which
a61af66fc99e Initial load duke parents: diff changeset	1580 // return the encoding code (ie - encoding bits for the instruction)
a61af66fc99e Initial load duke parents: diff changeset	1581 // associated with each basic boolean condition for a conditional instruction.
a61af66fc99e Initial load duke parents: diff changeset	1582 // Instructions specify two basic values for encoding. They use the
a61af66fc99e Initial load duke parents: diff changeset	1583 // ins_encode keyword to specify their encoding class (which must be one of
a61af66fc99e Initial load duke parents: diff changeset	1584 // the class names specified in the encoding block), and they use the
a61af66fc99e Initial load duke parents: diff changeset	1585 // opcode keyword to specify, in order, their primary, secondary, and
a61af66fc99e Initial load duke parents: diff changeset	1586 // tertiary opcode. Only the opcode sections which a particular instruction
a61af66fc99e Initial load duke parents: diff changeset	1587 // needs for encoding need to be specified.
a61af66fc99e Initial load duke parents: diff changeset	1588 encode %{
a61af66fc99e Initial load duke parents: diff changeset	1589 // Build emit functions for each basic byte or larger field in the intel
a61af66fc99e Initial load duke parents: diff changeset	1590 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
a61af66fc99e Initial load duke parents: diff changeset	1591 // code in the enc_class source block. Emit functions will live in the
a61af66fc99e Initial load duke parents: diff changeset	1592 // main source block for now. In future, we can generalize this by
a61af66fc99e Initial load duke parents: diff changeset	1593 // adding a syntax that specifies the sizes of fields in an order,
a61af66fc99e Initial load duke parents: diff changeset	1594 // so that the adlc can build the emit functions automagically
643 c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	1595
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	1596 // Emit primary opcode
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	1597 enc_class OpcP %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	1598 emit_opcode(cbuf, $primary);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	1599 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	1600
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	1601 // Emit secondary opcode
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	1602 enc_class OpcS %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	1603 emit_opcode(cbuf, $secondary);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	1604 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	1605
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	1606 // Emit opcode directly
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	1607 enc_class Opcode(immI d8) %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	1608 emit_opcode(cbuf, $d8$$constant);
0 a61af66fc99e Initial load duke parents: diff changeset	1609 %}
a61af66fc99e Initial load duke parents: diff changeset	1610
a61af66fc99e Initial load duke parents: diff changeset	1611 enc_class SizePrefix %{
a61af66fc99e Initial load duke parents: diff changeset	1612 emit_opcode(cbuf,0x66);
a61af66fc99e Initial load duke parents: diff changeset	1613 %}
a61af66fc99e Initial load duke parents: diff changeset	1614
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1615 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
0 a61af66fc99e Initial load duke parents: diff changeset	1616 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
a61af66fc99e Initial load duke parents: diff changeset	1617 %}
a61af66fc99e Initial load duke parents: diff changeset	1618
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1619 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
0 a61af66fc99e Initial load duke parents: diff changeset	1620 emit_opcode(cbuf,$opcode$$constant);
a61af66fc99e Initial load duke parents: diff changeset	1621 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
a61af66fc99e Initial load duke parents: diff changeset	1622 %}
a61af66fc99e Initial load duke parents: diff changeset	1623
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1624 enc_class mov_r32_imm0( rRegI dst ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	1625 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
a61af66fc99e Initial load duke parents: diff changeset	1626 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
a61af66fc99e Initial load duke parents: diff changeset	1627 %}
a61af66fc99e Initial load duke parents: diff changeset	1628
a61af66fc99e Initial load duke parents: diff changeset	1629 enc_class cdq_enc %{
a61af66fc99e Initial load duke parents: diff changeset	1630 // Full implementation of Java idiv and irem; checks for
a61af66fc99e Initial load duke parents: diff changeset	1631 // special case as described in JVM spec., p.243 & p.271.
a61af66fc99e Initial load duke parents: diff changeset	1632 //
a61af66fc99e Initial load duke parents: diff changeset	1633 // normal case special case
a61af66fc99e Initial load duke parents: diff changeset	1634 //
a61af66fc99e Initial load duke parents: diff changeset	1635 // input : rax,: dividend min_int
a61af66fc99e Initial load duke parents: diff changeset	1636 // reg: divisor -1
a61af66fc99e Initial load duke parents: diff changeset	1637 //
a61af66fc99e Initial load duke parents: diff changeset	1638 // output: rax,: quotient (= rax, idiv reg) min_int
a61af66fc99e Initial load duke parents: diff changeset	1639 // rdx: remainder (= rax, irem reg) 0
a61af66fc99e Initial load duke parents: diff changeset	1640 //
a61af66fc99e Initial load duke parents: diff changeset	1641 // Code sequnce:
a61af66fc99e Initial load duke parents: diff changeset	1642 //
a61af66fc99e Initial load duke parents: diff changeset	1643 // 81 F8 00 00 00 80 cmp rax,80000000h
a61af66fc99e Initial load duke parents: diff changeset	1644 // 0F 85 0B 00 00 00 jne normal_case
a61af66fc99e Initial load duke parents: diff changeset	1645 // 33 D2 xor rdx,edx
a61af66fc99e Initial load duke parents: diff changeset	1646 // 83 F9 FF cmp rcx,0FFh
a61af66fc99e Initial load duke parents: diff changeset	1647 // 0F 84 03 00 00 00 je done
a61af66fc99e Initial load duke parents: diff changeset	1648 // normal_case:
a61af66fc99e Initial load duke parents: diff changeset	1649 // 99 cdq
a61af66fc99e Initial load duke parents: diff changeset	1650 // F7 F9 idiv rax,ecx
a61af66fc99e Initial load duke parents: diff changeset	1651 // done:
a61af66fc99e Initial load duke parents: diff changeset	1652 //
a61af66fc99e Initial load duke parents: diff changeset	1653 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
a61af66fc99e Initial load duke parents: diff changeset	1654 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
a61af66fc99e Initial load duke parents: diff changeset	1655 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
a61af66fc99e Initial load duke parents: diff changeset	1656 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
a61af66fc99e Initial load duke parents: diff changeset	1657 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
a61af66fc99e Initial load duke parents: diff changeset	1658 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
a61af66fc99e Initial load duke parents: diff changeset	1659 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
a61af66fc99e Initial load duke parents: diff changeset	1660 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
a61af66fc99e Initial load duke parents: diff changeset	1661 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
a61af66fc99e Initial load duke parents: diff changeset	1662 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
a61af66fc99e Initial load duke parents: diff changeset	1663 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
a61af66fc99e Initial load duke parents: diff changeset	1664 // normal_case:
a61af66fc99e Initial load duke parents: diff changeset	1665 emit_opcode(cbuf,0x99); // cdq
a61af66fc99e Initial load duke parents: diff changeset	1666 // idiv (note: must be emitted by the user of this rule)
a61af66fc99e Initial load duke parents: diff changeset	1667 // normal:
a61af66fc99e Initial load duke parents: diff changeset	1668 %}
a61af66fc99e Initial load duke parents: diff changeset	1669
a61af66fc99e Initial load duke parents: diff changeset	1670 // Dense encoding for older common ops
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1671 enc_class Opc_plus(immI opcode, rRegI reg) %{
0 a61af66fc99e Initial load duke parents: diff changeset	1672 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
a61af66fc99e Initial load duke parents: diff changeset	1673 %}
a61af66fc99e Initial load duke parents: diff changeset	1674
a61af66fc99e Initial load duke parents: diff changeset	1675
a61af66fc99e Initial load duke parents: diff changeset	1676 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
a61af66fc99e Initial load duke parents: diff changeset	1677 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
a61af66fc99e Initial load duke parents: diff changeset	1678 // Check for 8-bit immediate, and set sign extend bit in opcode
a61af66fc99e Initial load duke parents: diff changeset	1679 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
a61af66fc99e Initial load duke parents: diff changeset	1680 emit_opcode(cbuf, $primary \| 0x02);
a61af66fc99e Initial load duke parents: diff changeset	1681 }
a61af66fc99e Initial load duke parents: diff changeset	1682 else { // If 32-bit immediate
a61af66fc99e Initial load duke parents: diff changeset	1683 emit_opcode(cbuf, $primary);
a61af66fc99e Initial load duke parents: diff changeset	1684 }
a61af66fc99e Initial load duke parents: diff changeset	1685 %}
a61af66fc99e Initial load duke parents: diff changeset	1686
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1687 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
0 a61af66fc99e Initial load duke parents: diff changeset	1688 // Emit primary opcode and set sign-extend bit
a61af66fc99e Initial load duke parents: diff changeset	1689 // Check for 8-bit immediate, and set sign extend bit in opcode
a61af66fc99e Initial load duke parents: diff changeset	1690 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
a61af66fc99e Initial load duke parents: diff changeset	1691 emit_opcode(cbuf, $primary \| 0x02); }
a61af66fc99e Initial load duke parents: diff changeset	1692 else { // If 32-bit immediate
a61af66fc99e Initial load duke parents: diff changeset	1693 emit_opcode(cbuf, $primary);
a61af66fc99e Initial load duke parents: diff changeset	1694 }
a61af66fc99e Initial load duke parents: diff changeset	1695 // Emit r/m byte with secondary opcode, after primary opcode.
a61af66fc99e Initial load duke parents: diff changeset	1696 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
a61af66fc99e Initial load duke parents: diff changeset	1697 %}
a61af66fc99e Initial load duke parents: diff changeset	1698
a61af66fc99e Initial load duke parents: diff changeset	1699 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
a61af66fc99e Initial load duke parents: diff changeset	1700 // Check for 8-bit immediate, and set sign extend bit in opcode
a61af66fc99e Initial load duke parents: diff changeset	1701 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
a61af66fc99e Initial load duke parents: diff changeset	1702 $$$emit8$imm$$constant;
a61af66fc99e Initial load duke parents: diff changeset	1703 }
a61af66fc99e Initial load duke parents: diff changeset	1704 else { // If 32-bit immediate
a61af66fc99e Initial load duke parents: diff changeset	1705 // Output immediate
a61af66fc99e Initial load duke parents: diff changeset	1706 $$$emit32$imm$$constant;
a61af66fc99e Initial load duke parents: diff changeset	1707 }
a61af66fc99e Initial load duke parents: diff changeset	1708 %}
a61af66fc99e Initial load duke parents: diff changeset	1709
a61af66fc99e Initial load duke parents: diff changeset	1710 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
a61af66fc99e Initial load duke parents: diff changeset	1711 // Emit primary opcode and set sign-extend bit
a61af66fc99e Initial load duke parents: diff changeset	1712 // Check for 8-bit immediate, and set sign extend bit in opcode
a61af66fc99e Initial load duke parents: diff changeset	1713 int con = (int)$imm$$constant; // Throw away top bits
a61af66fc99e Initial load duke parents: diff changeset	1714 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary \| 0x02) : $primary);
a61af66fc99e Initial load duke parents: diff changeset	1715 // Emit r/m byte with secondary opcode, after primary opcode.
a61af66fc99e Initial load duke parents: diff changeset	1716 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
a61af66fc99e Initial load duke parents: diff changeset	1717 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
a61af66fc99e Initial load duke parents: diff changeset	1718 else emit_d32(cbuf,con);
a61af66fc99e Initial load duke parents: diff changeset	1719 %}
a61af66fc99e Initial load duke parents: diff changeset	1720
a61af66fc99e Initial load duke parents: diff changeset	1721 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
a61af66fc99e Initial load duke parents: diff changeset	1722 // Emit primary opcode and set sign-extend bit
a61af66fc99e Initial load duke parents: diff changeset	1723 // Check for 8-bit immediate, and set sign extend bit in opcode
a61af66fc99e Initial load duke parents: diff changeset	1724 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
a61af66fc99e Initial load duke parents: diff changeset	1725 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary \| 0x02) : $primary);
a61af66fc99e Initial load duke parents: diff changeset	1726 // Emit r/m byte with tertiary opcode, after primary opcode.
a61af66fc99e Initial load duke parents: diff changeset	1727 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
a61af66fc99e Initial load duke parents: diff changeset	1728 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
a61af66fc99e Initial load duke parents: diff changeset	1729 else emit_d32(cbuf,con);
a61af66fc99e Initial load duke parents: diff changeset	1730 %}
a61af66fc99e Initial load duke parents: diff changeset	1731
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1732 enc_class OpcSReg (rRegI dst) %{ // BSWAP
0 a61af66fc99e Initial load duke parents: diff changeset	1733 emit_cc(cbuf, $secondary, $dst$$reg );
a61af66fc99e Initial load duke parents: diff changeset	1734 %}
a61af66fc99e Initial load duke parents: diff changeset	1735
a61af66fc99e Initial load duke parents: diff changeset	1736 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
a61af66fc99e Initial load duke parents: diff changeset	1737 int destlo = $dst$$reg;
a61af66fc99e Initial load duke parents: diff changeset	1738 int desthi = HIGH_FROM_LOW(destlo);
a61af66fc99e Initial load duke parents: diff changeset	1739 // bswap lo
a61af66fc99e Initial load duke parents: diff changeset	1740 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load duke parents: diff changeset	1741 emit_cc(cbuf, 0xC8, destlo);
a61af66fc99e Initial load duke parents: diff changeset	1742 // bswap hi
a61af66fc99e Initial load duke parents: diff changeset	1743 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load duke parents: diff changeset	1744 emit_cc(cbuf, 0xC8, desthi);
a61af66fc99e Initial load duke parents: diff changeset	1745 // xchg lo and hi
a61af66fc99e Initial load duke parents: diff changeset	1746 emit_opcode(cbuf, 0x87);
a61af66fc99e Initial load duke parents: diff changeset	1747 emit_rm(cbuf, 0x3, destlo, desthi);
a61af66fc99e Initial load duke parents: diff changeset	1748 %}
a61af66fc99e Initial load duke parents: diff changeset	1749
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1750 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
0 a61af66fc99e Initial load duke parents: diff changeset	1751 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
a61af66fc99e Initial load duke parents: diff changeset	1752 %}
a61af66fc99e Initial load duke parents: diff changeset	1753
a61af66fc99e Initial load duke parents: diff changeset	1754 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
a61af66fc99e Initial load duke parents: diff changeset	1755 $$$emit8$primary;
a61af66fc99e Initial load duke parents: diff changeset	1756 emit_cc(cbuf, $secondary, $cop$$cmpcode);
a61af66fc99e Initial load duke parents: diff changeset	1757 %}
a61af66fc99e Initial load duke parents: diff changeset	1758
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	1759 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
0 a61af66fc99e Initial load duke parents: diff changeset	1760 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
a61af66fc99e Initial load duke parents: diff changeset	1761 emit_d8(cbuf, op >> 8 );
a61af66fc99e Initial load duke parents: diff changeset	1762 emit_d8(cbuf, op & 255);
a61af66fc99e Initial load duke parents: diff changeset	1763 %}
a61af66fc99e Initial load duke parents: diff changeset	1764
a61af66fc99e Initial load duke parents: diff changeset	1765 // emulate a CMOV with a conditional branch around a MOV
a61af66fc99e Initial load duke parents: diff changeset	1766 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
a61af66fc99e Initial load duke parents: diff changeset	1767 // Invert sense of branch from sense of CMOV
a61af66fc99e Initial load duke parents: diff changeset	1768 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
a61af66fc99e Initial load duke parents: diff changeset	1769 emit_d8( cbuf, $brOffs$$constant );
a61af66fc99e Initial load duke parents: diff changeset	1770 %}
a61af66fc99e Initial load duke parents: diff changeset	1771
a61af66fc99e Initial load duke parents: diff changeset	1772 enc_class enc_PartialSubtypeCheck( ) %{
a61af66fc99e Initial load duke parents: diff changeset	1773 Register Redi = as_Register(EDI_enc); // result register
a61af66fc99e Initial load duke parents: diff changeset	1774 Register Reax = as_Register(EAX_enc); // super class
a61af66fc99e Initial load duke parents: diff changeset	1775 Register Recx = as_Register(ECX_enc); // killed
a61af66fc99e Initial load duke parents: diff changeset	1776 Register Resi = as_Register(ESI_enc); // sub class
644 c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638) jrose parents: 643 diff changeset	1777 Label miss;
0 a61af66fc99e Initial load duke parents: diff changeset	1778
a61af66fc99e Initial load duke parents: diff changeset	1779 MacroAssembler _masm(&cbuf);
644 c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638) jrose parents: 643 diff changeset	1780 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638) jrose parents: 643 diff changeset	1781 NULL, &miss,
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638) jrose parents: 643 diff changeset	1782 /set_cond_codes:/ true);
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638) jrose parents: 643 diff changeset	1783 if ($primary) {
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638) jrose parents: 643 diff changeset	1784 __ xorptr(Redi, Redi);
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638) jrose parents: 643 diff changeset	1785 }
0 a61af66fc99e Initial load duke parents: diff changeset	1786 __ bind(miss);
a61af66fc99e Initial load duke parents: diff changeset	1787 %}
a61af66fc99e Initial load duke parents: diff changeset	1788
a61af66fc99e Initial load duke parents: diff changeset	1789 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
a61af66fc99e Initial load duke parents: diff changeset	1790 MacroAssembler masm(&cbuf);
a61af66fc99e Initial load duke parents: diff changeset	1791 int start = masm.offset();
a61af66fc99e Initial load duke parents: diff changeset	1792 if (UseSSE >= 2) {
a61af66fc99e Initial load duke parents: diff changeset	1793 if (VerifyFPU) {
a61af66fc99e Initial load duke parents: diff changeset	1794 masm.verify_FPU(0, "must be empty in SSE2+ mode");
a61af66fc99e Initial load duke parents: diff changeset	1795 }
a61af66fc99e Initial load duke parents: diff changeset	1796 } else {
a61af66fc99e Initial load duke parents: diff changeset	1797 // External c_calling_convention expects the FPU stack to be 'clean'.
a61af66fc99e Initial load duke parents: diff changeset	1798 // Compiled code leaves it dirty. Do cleanup now.
a61af66fc99e Initial load duke parents: diff changeset	1799 masm.empty_FPU_stack();
a61af66fc99e Initial load duke parents: diff changeset	1800 }
a61af66fc99e Initial load duke parents: diff changeset	1801 if (sizeof_FFree_Float_Stack_All == -1) {
a61af66fc99e Initial load duke parents: diff changeset	1802 sizeof_FFree_Float_Stack_All = masm.offset() - start;
a61af66fc99e Initial load duke parents: diff changeset	1803 } else {
a61af66fc99e Initial load duke parents: diff changeset	1804 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
a61af66fc99e Initial load duke parents: diff changeset	1805 }
a61af66fc99e Initial load duke parents: diff changeset	1806 %}
a61af66fc99e Initial load duke parents: diff changeset	1807
a61af66fc99e Initial load duke parents: diff changeset	1808 enc_class Verify_FPU_For_Leaf %{
a61af66fc99e Initial load duke parents: diff changeset	1809 if( VerifyFPU ) {
a61af66fc99e Initial load duke parents: diff changeset	1810 MacroAssembler masm(&cbuf);
a61af66fc99e Initial load duke parents: diff changeset	1811 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
a61af66fc99e Initial load duke parents: diff changeset	1812 }
a61af66fc99e Initial load duke parents: diff changeset	1813 %}
a61af66fc99e Initial load duke parents: diff changeset	1814
a61af66fc99e Initial load duke parents: diff changeset	1815 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
a61af66fc99e Initial load duke parents: diff changeset	1816 // This is the instruction starting address for relocation info.
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	1817 cbuf.set_insts_mark();
0 a61af66fc99e Initial load duke parents: diff changeset	1818 $$$emit8$primary;
a61af66fc99e Initial load duke parents: diff changeset	1819 // CALL directly to the runtime
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	1820 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
0 a61af66fc99e Initial load duke parents: diff changeset	1821 runtime_call_Relocation::spec(), RELOC_IMM32 );
a61af66fc99e Initial load duke parents: diff changeset	1822
a61af66fc99e Initial load duke parents: diff changeset	1823 if (UseSSE >= 2) {
a61af66fc99e Initial load duke parents: diff changeset	1824 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load duke parents: diff changeset	1825 BasicType rt = tf()->return_type();
a61af66fc99e Initial load duke parents: diff changeset	1826
a61af66fc99e Initial load duke parents: diff changeset	1827 if ((rt == T_FLOAT \|\| rt == T_DOUBLE) && !return_value_is_used()) {
a61af66fc99e Initial load duke parents: diff changeset	1828 // A C runtime call where the return value is unused. In SSE2+
a61af66fc99e Initial load duke parents: diff changeset	1829 // mode the result needs to be removed from the FPU stack. It's
a61af66fc99e Initial load duke parents: diff changeset	1830 // likely that this function call could be removed by the
a61af66fc99e Initial load duke parents: diff changeset	1831 // optimizer if the C function is a pure function.
a61af66fc99e Initial load duke parents: diff changeset	1832 __ ffree(0);
a61af66fc99e Initial load duke parents: diff changeset	1833 } else if (rt == T_FLOAT) {
304 dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories never parents: 235 diff changeset	1834 __ lea(rsp, Address(rsp, -4));
0 a61af66fc99e Initial load duke parents: diff changeset	1835 __ fstp_s(Address(rsp, 0));
a61af66fc99e Initial load duke parents: diff changeset	1836 __ movflt(xmm0, Address(rsp, 0));
304 dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories never parents: 235 diff changeset	1837 __ lea(rsp, Address(rsp, 4));
0 a61af66fc99e Initial load duke parents: diff changeset	1838 } else if (rt == T_DOUBLE) {
304 dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories never parents: 235 diff changeset	1839 __ lea(rsp, Address(rsp, -8));
0 a61af66fc99e Initial load duke parents: diff changeset	1840 __ fstp_d(Address(rsp, 0));
a61af66fc99e Initial load duke parents: diff changeset	1841 __ movdbl(xmm0, Address(rsp, 0));
304 dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories never parents: 235 diff changeset	1842 __ lea(rsp, Address(rsp, 8));
0 a61af66fc99e Initial load duke parents: diff changeset	1843 }
a61af66fc99e Initial load duke parents: diff changeset	1844 }
a61af66fc99e Initial load duke parents: diff changeset	1845 %}
a61af66fc99e Initial load duke parents: diff changeset	1846
a61af66fc99e Initial load duke parents: diff changeset	1847
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	1848 enc_class pre_call_resets %{
0 a61af66fc99e Initial load duke parents: diff changeset	1849 // If method sets FPU control word restore it here
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	1850 debug_only(int off0 = cbuf.insts_size());
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	1851 if (ra_->C->in_24_bit_fp_mode()) {
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	1852 MacroAssembler _masm(&cbuf);
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	1853 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	1854 }
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	1855 if (ra_->C->max_vector_size() > 16) {
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	1856 // Clear upper bits of YMM registers when current compiled code uses
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	1857 // wide vectors to avoid AVX <-> SSE transition penalty during call.
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	1858 MacroAssembler _masm(&cbuf);
e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	1859 __ vzeroupper();
0 a61af66fc99e Initial load duke parents: diff changeset	1860 }
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	1861 debug_only(int off1 = cbuf.insts_size());
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	1862 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
0 a61af66fc99e Initial load duke parents: diff changeset	1863 %}
a61af66fc99e Initial load duke parents: diff changeset	1864
a61af66fc99e Initial load duke parents: diff changeset	1865 enc_class post_call_FPU %{
a61af66fc99e Initial load duke parents: diff changeset	1866 // If method sets FPU control word do it here also
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	1867 if (Compile::current()->in_24_bit_fp_mode()) {
0 a61af66fc99e Initial load duke parents: diff changeset	1868 MacroAssembler masm(&cbuf);
a61af66fc99e Initial load duke parents: diff changeset	1869 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
a61af66fc99e Initial load duke parents: diff changeset	1870 }
a61af66fc99e Initial load duke parents: diff changeset	1871 %}
a61af66fc99e Initial load duke parents: diff changeset	1872
a61af66fc99e Initial load duke parents: diff changeset	1873 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
a61af66fc99e Initial load duke parents: diff changeset	1874 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
a61af66fc99e Initial load duke parents: diff changeset	1875 // who we intended to call.
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	1876 cbuf.set_insts_mark();
0 a61af66fc99e Initial load duke parents: diff changeset	1877 $$$emit8$primary;
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	1878 if (!_method) {
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	1879 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
0 a61af66fc99e Initial load duke parents: diff changeset	1880 runtime_call_Relocation::spec(), RELOC_IMM32 );
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	1881 } else if (_optimized_virtual) {
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	1882 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
0 a61af66fc99e Initial load duke parents: diff changeset	1883 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
a61af66fc99e Initial load duke parents: diff changeset	1884 } else {
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	1885 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
0 a61af66fc99e Initial load duke parents: diff changeset	1886 static_call_Relocation::spec(), RELOC_IMM32 );
a61af66fc99e Initial load duke parents: diff changeset	1887 }
10168 a6e09d6dd8e5 8003853: specify offset of IC load in java_to_interp stub dlong parents: 8873 diff changeset	1888 if (_method) { // Emit stub for static call.
a6e09d6dd8e5 8003853: specify offset of IC load in java_to_interp stub dlong parents: 8873 diff changeset	1889 CompiledStaticCall::emit_to_interp_stub(cbuf);
0 a61af66fc99e Initial load duke parents: diff changeset	1890 }
a61af66fc99e Initial load duke parents: diff changeset	1891 %}
a61af66fc99e Initial load duke parents: diff changeset	1892
a61af66fc99e Initial load duke parents: diff changeset	1893 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	1894 MacroAssembler _masm(&cbuf);
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	1895 __ ic_call((address)$meth$$method);
0 a61af66fc99e Initial load duke parents: diff changeset	1896 %}
a61af66fc99e Initial load duke parents: diff changeset	1897
a61af66fc99e Initial load duke parents: diff changeset	1898 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	1899 int disp = in_bytes(Method::from_compiled_offset());
0 a61af66fc99e Initial load duke parents: diff changeset	1900 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
a61af66fc99e Initial load duke parents: diff changeset	1901
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	1902 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	1903 cbuf.set_insts_mark();
0 a61af66fc99e Initial load duke parents: diff changeset	1904 $$$emit8$primary;
a61af66fc99e Initial load duke parents: diff changeset	1905 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
a61af66fc99e Initial load duke parents: diff changeset	1906 emit_d8(cbuf, disp); // Displacement
a61af66fc99e Initial load duke parents: diff changeset	1907
a61af66fc99e Initial load duke parents: diff changeset	1908 %}
a61af66fc99e Initial load duke parents: diff changeset	1909
a61af66fc99e Initial load duke parents: diff changeset	1910 // Following encoding is no longer used, but may be restored if calling
a61af66fc99e Initial load duke parents: diff changeset	1911 // convention changes significantly.
a61af66fc99e Initial load duke parents: diff changeset	1912 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
a61af66fc99e Initial load duke parents: diff changeset	1913 //
a61af66fc99e Initial load duke parents: diff changeset	1914 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
a61af66fc99e Initial load duke parents: diff changeset	1915 // // int ic_reg = Matcher::inline_cache_reg();
a61af66fc99e Initial load duke parents: diff changeset	1916 // // int ic_encode = Matcher::_regEncode[ic_reg];
a61af66fc99e Initial load duke parents: diff changeset	1917 // // int imo_reg = Matcher::interpreter_method_oop_reg();
a61af66fc99e Initial load duke parents: diff changeset	1918 // // int imo_encode = Matcher::_regEncode[imo_reg];
a61af66fc99e Initial load duke parents: diff changeset	1919 //
a61af66fc99e Initial load duke parents: diff changeset	1920 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
a61af66fc99e Initial load duke parents: diff changeset	1921 // // // so we load it immediately before the call
a61af66fc99e Initial load duke parents: diff changeset	1922 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
a61af66fc99e Initial load duke parents: diff changeset	1923 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
a61af66fc99e Initial load duke parents: diff changeset	1924 //
a61af66fc99e Initial load duke parents: diff changeset	1925 // // xor rbp,ebp
a61af66fc99e Initial load duke parents: diff changeset	1926 // emit_opcode(cbuf, 0x33);
a61af66fc99e Initial load duke parents: diff changeset	1927 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
a61af66fc99e Initial load duke parents: diff changeset	1928 //
a61af66fc99e Initial load duke parents: diff changeset	1929 // // CALL to interpreter.
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	1930 // cbuf.set_insts_mark();
0 a61af66fc99e Initial load duke parents: diff changeset	1931 // $$$emit8$primary;
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	1932 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
0 a61af66fc99e Initial load duke parents: diff changeset	1933 // runtime_call_Relocation::spec(), RELOC_IMM32 );
a61af66fc99e Initial load duke parents: diff changeset	1934 // %}
a61af66fc99e Initial load duke parents: diff changeset	1935
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1936 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
0 a61af66fc99e Initial load duke parents: diff changeset	1937 $$$emit8$primary;
a61af66fc99e Initial load duke parents: diff changeset	1938 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
a61af66fc99e Initial load duke parents: diff changeset	1939 $$$emit8$shift$$constant;
a61af66fc99e Initial load duke parents: diff changeset	1940 %}
a61af66fc99e Initial load duke parents: diff changeset	1941
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1942 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
0 a61af66fc99e Initial load duke parents: diff changeset	1943 // Load immediate does not have a zero or sign extended version
a61af66fc99e Initial load duke parents: diff changeset	1944 // for 8-bit immediates
a61af66fc99e Initial load duke parents: diff changeset	1945 emit_opcode(cbuf, 0xB8 + $dst$$reg);
a61af66fc99e Initial load duke parents: diff changeset	1946 $$$emit32$src$$constant;
a61af66fc99e Initial load duke parents: diff changeset	1947 %}
a61af66fc99e Initial load duke parents: diff changeset	1948
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1949 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
0 a61af66fc99e Initial load duke parents: diff changeset	1950 // Load immediate does not have a zero or sign extended version
a61af66fc99e Initial load duke parents: diff changeset	1951 // for 8-bit immediates
a61af66fc99e Initial load duke parents: diff changeset	1952 emit_opcode(cbuf, $primary + $dst$$reg);
a61af66fc99e Initial load duke parents: diff changeset	1953 $$$emit32$src$$constant;
a61af66fc99e Initial load duke parents: diff changeset	1954 %}
a61af66fc99e Initial load duke parents: diff changeset	1955
a61af66fc99e Initial load duke parents: diff changeset	1956 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
a61af66fc99e Initial load duke parents: diff changeset	1957 // Load immediate does not have a zero or sign extended version
a61af66fc99e Initial load duke parents: diff changeset	1958 // for 8-bit immediates
a61af66fc99e Initial load duke parents: diff changeset	1959 int dst_enc = $dst$$reg;
a61af66fc99e Initial load duke parents: diff changeset	1960 int src_con = $src$$constant & 0x0FFFFFFFFL;
a61af66fc99e Initial load duke parents: diff changeset	1961 if (src_con == 0) {
a61af66fc99e Initial load duke parents: diff changeset	1962 // xor dst, dst
a61af66fc99e Initial load duke parents: diff changeset	1963 emit_opcode(cbuf, 0x33);
a61af66fc99e Initial load duke parents: diff changeset	1964 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
a61af66fc99e Initial load duke parents: diff changeset	1965 } else {
a61af66fc99e Initial load duke parents: diff changeset	1966 emit_opcode(cbuf, $primary + dst_enc);
a61af66fc99e Initial load duke parents: diff changeset	1967 emit_d32(cbuf, src_con);
a61af66fc99e Initial load duke parents: diff changeset	1968 }
a61af66fc99e Initial load duke parents: diff changeset	1969 %}
a61af66fc99e Initial load duke parents: diff changeset	1970
a61af66fc99e Initial load duke parents: diff changeset	1971 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
a61af66fc99e Initial load duke parents: diff changeset	1972 // Load immediate does not have a zero or sign extended version
a61af66fc99e Initial load duke parents: diff changeset	1973 // for 8-bit immediates
a61af66fc99e Initial load duke parents: diff changeset	1974 int dst_enc = $dst$$reg + 2;
a61af66fc99e Initial load duke parents: diff changeset	1975 int src_con = ((julong)($src$$constant)) >> 32;
a61af66fc99e Initial load duke parents: diff changeset	1976 if (src_con == 0) {
a61af66fc99e Initial load duke parents: diff changeset	1977 // xor dst, dst
a61af66fc99e Initial load duke parents: diff changeset	1978 emit_opcode(cbuf, 0x33);
a61af66fc99e Initial load duke parents: diff changeset	1979 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
a61af66fc99e Initial load duke parents: diff changeset	1980 } else {
a61af66fc99e Initial load duke parents: diff changeset	1981 emit_opcode(cbuf, $primary + dst_enc);
a61af66fc99e Initial load duke parents: diff changeset	1982 emit_d32(cbuf, src_con);
a61af66fc99e Initial load duke parents: diff changeset	1983 }
a61af66fc99e Initial load duke parents: diff changeset	1984 %}
a61af66fc99e Initial load duke parents: diff changeset	1985
a61af66fc99e Initial load duke parents: diff changeset	1986
a61af66fc99e Initial load duke parents: diff changeset	1987 // Encode a reg-reg copy. If it is useless, then empty encoding.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1988 enc_class enc_Copy( rRegI dst, rRegI src ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	1989 encode_Copy( cbuf, $dst$$reg, $src$$reg );
a61af66fc99e Initial load duke parents: diff changeset	1990 %}
a61af66fc99e Initial load duke parents: diff changeset	1991
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1992 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	1993 encode_Copy( cbuf, $dst$$reg, $src$$reg );
a61af66fc99e Initial load duke parents: diff changeset	1994 %}
a61af66fc99e Initial load duke parents: diff changeset	1995
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	1996 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
0 a61af66fc99e Initial load duke parents: diff changeset	1997 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
a61af66fc99e Initial load duke parents: diff changeset	1998 %}
a61af66fc99e Initial load duke parents: diff changeset	1999
a61af66fc99e Initial load duke parents: diff changeset	2000 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
a61af66fc99e Initial load duke parents: diff changeset	2001 $$$emit8$primary;
a61af66fc99e Initial load duke parents: diff changeset	2002 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2003 %}
a61af66fc99e Initial load duke parents: diff changeset	2004
a61af66fc99e Initial load duke parents: diff changeset	2005 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
a61af66fc99e Initial load duke parents: diff changeset	2006 $$$emit8$secondary;
a61af66fc99e Initial load duke parents: diff changeset	2007 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
a61af66fc99e Initial load duke parents: diff changeset	2008 %}
a61af66fc99e Initial load duke parents: diff changeset	2009
a61af66fc99e Initial load duke parents: diff changeset	2010 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
a61af66fc99e Initial load duke parents: diff changeset	2011 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2012 %}
a61af66fc99e Initial load duke parents: diff changeset	2013
a61af66fc99e Initial load duke parents: diff changeset	2014 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
a61af66fc99e Initial load duke parents: diff changeset	2015 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
a61af66fc99e Initial load duke parents: diff changeset	2016 %}
a61af66fc99e Initial load duke parents: diff changeset	2017
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	2018 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2019 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
a61af66fc99e Initial load duke parents: diff changeset	2020 %}
a61af66fc99e Initial load duke parents: diff changeset	2021
a61af66fc99e Initial load duke parents: diff changeset	2022 enc_class Con32 (immI src) %{ // Con32(storeImmI)
a61af66fc99e Initial load duke parents: diff changeset	2023 // Output immediate
a61af66fc99e Initial load duke parents: diff changeset	2024 $$$emit32$src$$constant;
a61af66fc99e Initial load duke parents: diff changeset	2025 %}
a61af66fc99e Initial load duke parents: diff changeset	2026
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2027 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
0 a61af66fc99e Initial load duke parents: diff changeset	2028 // Output Float immediate bits
a61af66fc99e Initial load duke parents: diff changeset	2029 jfloat jf = $src$$constant;
a61af66fc99e Initial load duke parents: diff changeset	2030 int jf_as_bits = jint_cast( jf );
a61af66fc99e Initial load duke parents: diff changeset	2031 emit_d32(cbuf, jf_as_bits);
a61af66fc99e Initial load duke parents: diff changeset	2032 %}
a61af66fc99e Initial load duke parents: diff changeset	2033
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2034 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
0 a61af66fc99e Initial load duke parents: diff changeset	2035 // Output Float immediate bits
a61af66fc99e Initial load duke parents: diff changeset	2036 jfloat jf = $src$$constant;
a61af66fc99e Initial load duke parents: diff changeset	2037 int jf_as_bits = jint_cast( jf );
a61af66fc99e Initial load duke parents: diff changeset	2038 emit_d32(cbuf, jf_as_bits);
a61af66fc99e Initial load duke parents: diff changeset	2039 %}
a61af66fc99e Initial load duke parents: diff changeset	2040
a61af66fc99e Initial load duke parents: diff changeset	2041 enc_class Con16 (immI src) %{ // Con16(storeImmI)
a61af66fc99e Initial load duke parents: diff changeset	2042 // Output immediate
a61af66fc99e Initial load duke parents: diff changeset	2043 $$$emit16$src$$constant;
a61af66fc99e Initial load duke parents: diff changeset	2044 %}
a61af66fc99e Initial load duke parents: diff changeset	2045
a61af66fc99e Initial load duke parents: diff changeset	2046 enc_class Con_d32(immI src) %{
a61af66fc99e Initial load duke parents: diff changeset	2047 emit_d32(cbuf,$src$$constant);
a61af66fc99e Initial load duke parents: diff changeset	2048 %}
a61af66fc99e Initial load duke parents: diff changeset	2049
a61af66fc99e Initial load duke parents: diff changeset	2050 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
a61af66fc99e Initial load duke parents: diff changeset	2051 // Output immediate memory reference
a61af66fc99e Initial load duke parents: diff changeset	2052 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
a61af66fc99e Initial load duke parents: diff changeset	2053 emit_d32(cbuf, 0x00);
a61af66fc99e Initial load duke parents: diff changeset	2054 %}
a61af66fc99e Initial load duke parents: diff changeset	2055
a61af66fc99e Initial load duke parents: diff changeset	2056 enc_class lock_prefix( ) %{
a61af66fc99e Initial load duke parents: diff changeset	2057 if( os::is_MP() )
a61af66fc99e Initial load duke parents: diff changeset	2058 emit_opcode(cbuf,0xF0); // [Lock]
a61af66fc99e Initial load duke parents: diff changeset	2059 %}
a61af66fc99e Initial load duke parents: diff changeset	2060
a61af66fc99e Initial load duke parents: diff changeset	2061 // Cmp-xchg long value.
a61af66fc99e Initial load duke parents: diff changeset	2062 // Note: we need to swap rbx, and rcx before and after the
a61af66fc99e Initial load duke parents: diff changeset	2063 // cmpxchg8 instruction because the instruction uses
a61af66fc99e Initial load duke parents: diff changeset	2064 // rcx as the high order word of the new value to store but
a61af66fc99e Initial load duke parents: diff changeset	2065 // our register encoding uses rbx,.
a61af66fc99e Initial load duke parents: diff changeset	2066 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
a61af66fc99e Initial load duke parents: diff changeset	2067
a61af66fc99e Initial load duke parents: diff changeset	2068 // XCHG rbx,ecx
a61af66fc99e Initial load duke parents: diff changeset	2069 emit_opcode(cbuf,0x87);
a61af66fc99e Initial load duke parents: diff changeset	2070 emit_opcode(cbuf,0xD9);
a61af66fc99e Initial load duke parents: diff changeset	2071 // [Lock]
a61af66fc99e Initial load duke parents: diff changeset	2072 if( os::is_MP() )
a61af66fc99e Initial load duke parents: diff changeset	2073 emit_opcode(cbuf,0xF0);
a61af66fc99e Initial load duke parents: diff changeset	2074 // CMPXCHG8 [Eptr]
a61af66fc99e Initial load duke parents: diff changeset	2075 emit_opcode(cbuf,0x0F);
a61af66fc99e Initial load duke parents: diff changeset	2076 emit_opcode(cbuf,0xC7);
a61af66fc99e Initial load duke parents: diff changeset	2077 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2078 // XCHG rbx,ecx
a61af66fc99e Initial load duke parents: diff changeset	2079 emit_opcode(cbuf,0x87);
a61af66fc99e Initial load duke parents: diff changeset	2080 emit_opcode(cbuf,0xD9);
a61af66fc99e Initial load duke parents: diff changeset	2081 %}
a61af66fc99e Initial load duke parents: diff changeset	2082
a61af66fc99e Initial load duke parents: diff changeset	2083 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
a61af66fc99e Initial load duke parents: diff changeset	2084 // [Lock]
a61af66fc99e Initial load duke parents: diff changeset	2085 if( os::is_MP() )
a61af66fc99e Initial load duke parents: diff changeset	2086 emit_opcode(cbuf,0xF0);
a61af66fc99e Initial load duke parents: diff changeset	2087
a61af66fc99e Initial load duke parents: diff changeset	2088 // CMPXCHG [Eptr]
a61af66fc99e Initial load duke parents: diff changeset	2089 emit_opcode(cbuf,0x0F);
a61af66fc99e Initial load duke parents: diff changeset	2090 emit_opcode(cbuf,0xB1);
a61af66fc99e Initial load duke parents: diff changeset	2091 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2092 %}
a61af66fc99e Initial load duke parents: diff changeset	2093
a61af66fc99e Initial load duke parents: diff changeset	2094 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
a61af66fc99e Initial load duke parents: diff changeset	2095 int res_encoding = $res$$reg;
a61af66fc99e Initial load duke parents: diff changeset	2096
a61af66fc99e Initial load duke parents: diff changeset	2097 // MOV res,0
a61af66fc99e Initial load duke parents: diff changeset	2098 emit_opcode( cbuf, 0xB8 + res_encoding);
a61af66fc99e Initial load duke parents: diff changeset	2099 emit_d32( cbuf, 0 );
a61af66fc99e Initial load duke parents: diff changeset	2100 // JNE,s fail
a61af66fc99e Initial load duke parents: diff changeset	2101 emit_opcode(cbuf,0x75);
a61af66fc99e Initial load duke parents: diff changeset	2102 emit_d8(cbuf, 5 );
a61af66fc99e Initial load duke parents: diff changeset	2103 // MOV res,1
a61af66fc99e Initial load duke parents: diff changeset	2104 emit_opcode( cbuf, 0xB8 + res_encoding);
a61af66fc99e Initial load duke parents: diff changeset	2105 emit_d32( cbuf, 1 );
a61af66fc99e Initial load duke parents: diff changeset	2106 // fail:
a61af66fc99e Initial load duke parents: diff changeset	2107 %}
a61af66fc99e Initial load duke parents: diff changeset	2108
a61af66fc99e Initial load duke parents: diff changeset	2109 enc_class set_instruction_start( ) %{
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	2110 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
0 a61af66fc99e Initial load duke parents: diff changeset	2111 %}
a61af66fc99e Initial load duke parents: diff changeset	2112
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	2113 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
0 a61af66fc99e Initial load duke parents: diff changeset	2114 int reg_encoding = $ereg$$reg;
a61af66fc99e Initial load duke parents: diff changeset	2115 int base = $mem$$base;
a61af66fc99e Initial load duke parents: diff changeset	2116 int index = $mem$$index;
a61af66fc99e Initial load duke parents: diff changeset	2117 int scale = $mem$$scale;
a61af66fc99e Initial load duke parents: diff changeset	2118 int displace = $mem$$disp;
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	2119 relocInfo::relocType disp_reloc = $mem->disp_reloc();
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	2120 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
0 a61af66fc99e Initial load duke parents: diff changeset	2121 %}
a61af66fc99e Initial load duke parents: diff changeset	2122
a61af66fc99e Initial load duke parents: diff changeset	2123 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
a61af66fc99e Initial load duke parents: diff changeset	2124 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
a61af66fc99e Initial load duke parents: diff changeset	2125 int base = $mem$$base;
a61af66fc99e Initial load duke parents: diff changeset	2126 int index = $mem$$index;
a61af66fc99e Initial load duke parents: diff changeset	2127 int scale = $mem$$scale;
a61af66fc99e Initial load duke parents: diff changeset	2128 int displace = $mem$$disp + 4; // Offset is 4 further in memory
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	2129 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	2130 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
0 a61af66fc99e Initial load duke parents: diff changeset	2131 %}
a61af66fc99e Initial load duke parents: diff changeset	2132
a61af66fc99e Initial load duke parents: diff changeset	2133 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
a61af66fc99e Initial load duke parents: diff changeset	2134 int r1, r2;
a61af66fc99e Initial load duke parents: diff changeset	2135 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
a61af66fc99e Initial load duke parents: diff changeset	2136 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
a61af66fc99e Initial load duke parents: diff changeset	2137 emit_opcode(cbuf,0x0F);
a61af66fc99e Initial load duke parents: diff changeset	2138 emit_opcode(cbuf,$tertiary);
a61af66fc99e Initial load duke parents: diff changeset	2139 emit_rm(cbuf, 0x3, r1, r2);
a61af66fc99e Initial load duke parents: diff changeset	2140 emit_d8(cbuf,$cnt$$constant);
a61af66fc99e Initial load duke parents: diff changeset	2141 emit_d8(cbuf,$primary);
a61af66fc99e Initial load duke parents: diff changeset	2142 emit_rm(cbuf, 0x3, $secondary, r1);
a61af66fc99e Initial load duke parents: diff changeset	2143 emit_d8(cbuf,$cnt$$constant);
a61af66fc99e Initial load duke parents: diff changeset	2144 %}
a61af66fc99e Initial load duke parents: diff changeset	2145
a61af66fc99e Initial load duke parents: diff changeset	2146 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
a61af66fc99e Initial load duke parents: diff changeset	2147 emit_opcode( cbuf, 0x8B ); // Move
a61af66fc99e Initial load duke parents: diff changeset	2148 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	2149 if( $cnt$$constant > 32 ) { // Shift, if not by zero
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	2150 emit_d8(cbuf,$primary);
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	2151 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	2152 emit_d8(cbuf,$cnt$$constant-32);
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	2153 }
0 a61af66fc99e Initial load duke parents: diff changeset	2154 emit_d8(cbuf,$primary);
a61af66fc99e Initial load duke parents: diff changeset	2155 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
a61af66fc99e Initial load duke parents: diff changeset	2156 emit_d8(cbuf,31);
a61af66fc99e Initial load duke parents: diff changeset	2157 %}
a61af66fc99e Initial load duke parents: diff changeset	2158
a61af66fc99e Initial load duke parents: diff changeset	2159 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
a61af66fc99e Initial load duke parents: diff changeset	2160 int r1, r2;
a61af66fc99e Initial load duke parents: diff changeset	2161 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
a61af66fc99e Initial load duke parents: diff changeset	2162 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
a61af66fc99e Initial load duke parents: diff changeset	2163
a61af66fc99e Initial load duke parents: diff changeset	2164 emit_opcode( cbuf, 0x8B ); // Move r1,r2
a61af66fc99e Initial load duke parents: diff changeset	2165 emit_rm(cbuf, 0x3, r1, r2);
a61af66fc99e Initial load duke parents: diff changeset	2166 if( $cnt$$constant > 32 ) { // Shift, if not by zero
a61af66fc99e Initial load duke parents: diff changeset	2167 emit_opcode(cbuf,$primary);
a61af66fc99e Initial load duke parents: diff changeset	2168 emit_rm(cbuf, 0x3, $secondary, r1);
a61af66fc99e Initial load duke parents: diff changeset	2169 emit_d8(cbuf,$cnt$$constant-32);
a61af66fc99e Initial load duke parents: diff changeset	2170 }
a61af66fc99e Initial load duke parents: diff changeset	2171 emit_opcode(cbuf,0x33); // XOR r2,r2
a61af66fc99e Initial load duke parents: diff changeset	2172 emit_rm(cbuf, 0x3, r2, r2);
a61af66fc99e Initial load duke parents: diff changeset	2173 %}
a61af66fc99e Initial load duke parents: diff changeset	2174
a61af66fc99e Initial load duke parents: diff changeset	2175 // Clone of RegMem but accepts an extra parameter to access each
a61af66fc99e Initial load duke parents: diff changeset	2176 // half of a double in memory; it never needs relocation info.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	2177 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2178 emit_opcode(cbuf,$opcode$$constant);
a61af66fc99e Initial load duke parents: diff changeset	2179 int reg_encoding = $rm_reg$$reg;
a61af66fc99e Initial load duke parents: diff changeset	2180 int base = $mem$$base;
a61af66fc99e Initial load duke parents: diff changeset	2181 int index = $mem$$index;
a61af66fc99e Initial load duke parents: diff changeset	2182 int scale = $mem$$scale;
a61af66fc99e Initial load duke parents: diff changeset	2183 int displace = $mem$$disp + $disp_for_half$$constant;
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	2184 relocInfo::relocType disp_reloc = relocInfo::none;
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	2185 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
0 a61af66fc99e Initial load duke parents: diff changeset	2186 %}
a61af66fc99e Initial load duke parents: diff changeset	2187
a61af66fc99e Initial load duke parents: diff changeset	2188 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
a61af66fc99e Initial load duke parents: diff changeset	2189 //
a61af66fc99e Initial load duke parents: diff changeset	2190 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
a61af66fc99e Initial load duke parents: diff changeset	2191 // and it never needs relocation information.
a61af66fc99e Initial load duke parents: diff changeset	2192 // Frequently used to move data between FPU's Stack Top and memory.
a61af66fc99e Initial load duke parents: diff changeset	2193 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
a61af66fc99e Initial load duke parents: diff changeset	2194 int rm_byte_opcode = $rm_opcode$$constant;
a61af66fc99e Initial load duke parents: diff changeset	2195 int base = $mem$$base;
a61af66fc99e Initial load duke parents: diff changeset	2196 int index = $mem$$index;
a61af66fc99e Initial load duke parents: diff changeset	2197 int scale = $mem$$scale;
a61af66fc99e Initial load duke parents: diff changeset	2198 int displace = $mem$$disp;
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	2199 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	2200 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
0 a61af66fc99e Initial load duke parents: diff changeset	2201 %}
a61af66fc99e Initial load duke parents: diff changeset	2202
a61af66fc99e Initial load duke parents: diff changeset	2203 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
a61af66fc99e Initial load duke parents: diff changeset	2204 int rm_byte_opcode = $rm_opcode$$constant;
a61af66fc99e Initial load duke parents: diff changeset	2205 int base = $mem$$base;
a61af66fc99e Initial load duke parents: diff changeset	2206 int index = $mem$$index;
a61af66fc99e Initial load duke parents: diff changeset	2207 int scale = $mem$$scale;
a61af66fc99e Initial load duke parents: diff changeset	2208 int displace = $mem$$disp;
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	2209 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	2210 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
0 a61af66fc99e Initial load duke parents: diff changeset	2211 %}
a61af66fc99e Initial load duke parents: diff changeset	2212
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	2213 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
0 a61af66fc99e Initial load duke parents: diff changeset	2214 int reg_encoding = $dst$$reg;
a61af66fc99e Initial load duke parents: diff changeset	2215 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
a61af66fc99e Initial load duke parents: diff changeset	2216 int index = 0x04; // 0x04 indicates no index
a61af66fc99e Initial load duke parents: diff changeset	2217 int scale = 0x00; // 0x00 indicates no scale
a61af66fc99e Initial load duke parents: diff changeset	2218 int displace = $src1$$constant; // 0x00 indicates no displacement
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	2219 relocInfo::relocType disp_reloc = relocInfo::none;
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	2220 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
0 a61af66fc99e Initial load duke parents: diff changeset	2221 %}
a61af66fc99e Initial load duke parents: diff changeset	2222
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	2223 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
0 a61af66fc99e Initial load duke parents: diff changeset	2224 // Compare dst,src
a61af66fc99e Initial load duke parents: diff changeset	2225 emit_opcode(cbuf,0x3B);
a61af66fc99e Initial load duke parents: diff changeset	2226 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2227 // jmp dst < src around move
a61af66fc99e Initial load duke parents: diff changeset	2228 emit_opcode(cbuf,0x7C);
a61af66fc99e Initial load duke parents: diff changeset	2229 emit_d8(cbuf,2);
a61af66fc99e Initial load duke parents: diff changeset	2230 // move dst,src
a61af66fc99e Initial load duke parents: diff changeset	2231 emit_opcode(cbuf,0x8B);
a61af66fc99e Initial load duke parents: diff changeset	2232 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2233 %}
a61af66fc99e Initial load duke parents: diff changeset	2234
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	2235 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
0 a61af66fc99e Initial load duke parents: diff changeset	2236 // Compare dst,src
a61af66fc99e Initial load duke parents: diff changeset	2237 emit_opcode(cbuf,0x3B);
a61af66fc99e Initial load duke parents: diff changeset	2238 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2239 // jmp dst > src around move
a61af66fc99e Initial load duke parents: diff changeset	2240 emit_opcode(cbuf,0x7F);
a61af66fc99e Initial load duke parents: diff changeset	2241 emit_d8(cbuf,2);
a61af66fc99e Initial load duke parents: diff changeset	2242 // move dst,src
a61af66fc99e Initial load duke parents: diff changeset	2243 emit_opcode(cbuf,0x8B);
a61af66fc99e Initial load duke parents: diff changeset	2244 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2245 %}
a61af66fc99e Initial load duke parents: diff changeset	2246
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2247 enc_class enc_FPR_store(memory mem, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2248 // If src is FPR1, we can just FST to store it.
a61af66fc99e Initial load duke parents: diff changeset	2249 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
a61af66fc99e Initial load duke parents: diff changeset	2250 int reg_encoding = 0x2; // Just store
a61af66fc99e Initial load duke parents: diff changeset	2251 int base = $mem$$base;
a61af66fc99e Initial load duke parents: diff changeset	2252 int index = $mem$$index;
a61af66fc99e Initial load duke parents: diff changeset	2253 int scale = $mem$$scale;
a61af66fc99e Initial load duke parents: diff changeset	2254 int displace = $mem$$disp;
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	2255 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
0 a61af66fc99e Initial load duke parents: diff changeset	2256 if( $src$$reg != FPR1L_enc ) {
a61af66fc99e Initial load duke parents: diff changeset	2257 reg_encoding = 0x3; // Store & pop
a61af66fc99e Initial load duke parents: diff changeset	2258 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
a61af66fc99e Initial load duke parents: diff changeset	2259 emit_d8( cbuf, 0xC0-1+$src$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2260 }
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	2261 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
0 a61af66fc99e Initial load duke parents: diff changeset	2262 emit_opcode(cbuf,$primary);
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	2263 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
0 a61af66fc99e Initial load duke parents: diff changeset	2264 %}
a61af66fc99e Initial load duke parents: diff changeset	2265
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	2266 enc_class neg_reg(rRegI dst) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2267 // NEG $dst
a61af66fc99e Initial load duke parents: diff changeset	2268 emit_opcode(cbuf,0xF7);
a61af66fc99e Initial load duke parents: diff changeset	2269 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2270 %}
a61af66fc99e Initial load duke parents: diff changeset	2271
a61af66fc99e Initial load duke parents: diff changeset	2272 enc_class setLT_reg(eCXRegI dst) %{
a61af66fc99e Initial load duke parents: diff changeset	2273 // SETLT $dst
a61af66fc99e Initial load duke parents: diff changeset	2274 emit_opcode(cbuf,0x0F);
a61af66fc99e Initial load duke parents: diff changeset	2275 emit_opcode(cbuf,0x9C);
a61af66fc99e Initial load duke parents: diff changeset	2276 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2277 %}
a61af66fc99e Initial load duke parents: diff changeset	2278
a61af66fc99e Initial load duke parents: diff changeset	2279 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
a61af66fc99e Initial load duke parents: diff changeset	2280 int tmpReg = $tmp$$reg;
a61af66fc99e Initial load duke parents: diff changeset	2281
a61af66fc99e Initial load duke parents: diff changeset	2282 // SUB $p,$q
a61af66fc99e Initial load duke parents: diff changeset	2283 emit_opcode(cbuf,0x2B);
a61af66fc99e Initial load duke parents: diff changeset	2284 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2285 // SBB $tmp,$tmp
a61af66fc99e Initial load duke parents: diff changeset	2286 emit_opcode(cbuf,0x1B);
a61af66fc99e Initial load duke parents: diff changeset	2287 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
a61af66fc99e Initial load duke parents: diff changeset	2288 // AND $tmp,$y
a61af66fc99e Initial load duke parents: diff changeset	2289 emit_opcode(cbuf,0x23);
a61af66fc99e Initial load duke parents: diff changeset	2290 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2291 // ADD $p,$tmp
a61af66fc99e Initial load duke parents: diff changeset	2292 emit_opcode(cbuf,0x03);
a61af66fc99e Initial load duke parents: diff changeset	2293 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
a61af66fc99e Initial load duke parents: diff changeset	2294 %}
a61af66fc99e Initial load duke parents: diff changeset	2295
a61af66fc99e Initial load duke parents: diff changeset	2296 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
a61af66fc99e Initial load duke parents: diff changeset	2297 // TEST shift,32
a61af66fc99e Initial load duke parents: diff changeset	2298 emit_opcode(cbuf,0xF7);
a61af66fc99e Initial load duke parents: diff changeset	2299 emit_rm(cbuf, 0x3, 0, ECX_enc);
a61af66fc99e Initial load duke parents: diff changeset	2300 emit_d32(cbuf,0x20);
a61af66fc99e Initial load duke parents: diff changeset	2301 // JEQ,s small
a61af66fc99e Initial load duke parents: diff changeset	2302 emit_opcode(cbuf, 0x74);
a61af66fc99e Initial load duke parents: diff changeset	2303 emit_d8(cbuf, 0x04);
a61af66fc99e Initial load duke parents: diff changeset	2304 // MOV $dst.hi,$dst.lo
a61af66fc99e Initial load duke parents: diff changeset	2305 emit_opcode( cbuf, 0x8B );
a61af66fc99e Initial load duke parents: diff changeset	2306 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2307 // CLR $dst.lo
a61af66fc99e Initial load duke parents: diff changeset	2308 emit_opcode(cbuf, 0x33);
a61af66fc99e Initial load duke parents: diff changeset	2309 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2310 // small:
a61af66fc99e Initial load duke parents: diff changeset	2311 // SHLD $dst.hi,$dst.lo,$shift
a61af66fc99e Initial load duke parents: diff changeset	2312 emit_opcode(cbuf,0x0F);
a61af66fc99e Initial load duke parents: diff changeset	2313 emit_opcode(cbuf,0xA5);
a61af66fc99e Initial load duke parents: diff changeset	2314 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
a61af66fc99e Initial load duke parents: diff changeset	2315 // SHL $dst.lo,$shift"
a61af66fc99e Initial load duke parents: diff changeset	2316 emit_opcode(cbuf,0xD3);
a61af66fc99e Initial load duke parents: diff changeset	2317 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2318 %}
a61af66fc99e Initial load duke parents: diff changeset	2319
a61af66fc99e Initial load duke parents: diff changeset	2320 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
a61af66fc99e Initial load duke parents: diff changeset	2321 // TEST shift,32
a61af66fc99e Initial load duke parents: diff changeset	2322 emit_opcode(cbuf,0xF7);
a61af66fc99e Initial load duke parents: diff changeset	2323 emit_rm(cbuf, 0x3, 0, ECX_enc);
a61af66fc99e Initial load duke parents: diff changeset	2324 emit_d32(cbuf,0x20);
a61af66fc99e Initial load duke parents: diff changeset	2325 // JEQ,s small
a61af66fc99e Initial load duke parents: diff changeset	2326 emit_opcode(cbuf, 0x74);
a61af66fc99e Initial load duke parents: diff changeset	2327 emit_d8(cbuf, 0x04);
a61af66fc99e Initial load duke parents: diff changeset	2328 // MOV $dst.lo,$dst.hi
a61af66fc99e Initial load duke parents: diff changeset	2329 emit_opcode( cbuf, 0x8B );
a61af66fc99e Initial load duke parents: diff changeset	2330 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2331 // CLR $dst.hi
a61af66fc99e Initial load duke parents: diff changeset	2332 emit_opcode(cbuf, 0x33);
a61af66fc99e Initial load duke parents: diff changeset	2333 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
a61af66fc99e Initial load duke parents: diff changeset	2334 // small:
a61af66fc99e Initial load duke parents: diff changeset	2335 // SHRD $dst.lo,$dst.hi,$shift
a61af66fc99e Initial load duke parents: diff changeset	2336 emit_opcode(cbuf,0x0F);
a61af66fc99e Initial load duke parents: diff changeset	2337 emit_opcode(cbuf,0xAD);
a61af66fc99e Initial load duke parents: diff changeset	2338 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2339 // SHR $dst.hi,$shift"
a61af66fc99e Initial load duke parents: diff changeset	2340 emit_opcode(cbuf,0xD3);
a61af66fc99e Initial load duke parents: diff changeset	2341 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2342 %}
a61af66fc99e Initial load duke parents: diff changeset	2343
a61af66fc99e Initial load duke parents: diff changeset	2344 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
a61af66fc99e Initial load duke parents: diff changeset	2345 // TEST shift,32
a61af66fc99e Initial load duke parents: diff changeset	2346 emit_opcode(cbuf,0xF7);
a61af66fc99e Initial load duke parents: diff changeset	2347 emit_rm(cbuf, 0x3, 0, ECX_enc);
a61af66fc99e Initial load duke parents: diff changeset	2348 emit_d32(cbuf,0x20);
a61af66fc99e Initial load duke parents: diff changeset	2349 // JEQ,s small
a61af66fc99e Initial load duke parents: diff changeset	2350 emit_opcode(cbuf, 0x74);
a61af66fc99e Initial load duke parents: diff changeset	2351 emit_d8(cbuf, 0x05);
a61af66fc99e Initial load duke parents: diff changeset	2352 // MOV $dst.lo,$dst.hi
a61af66fc99e Initial load duke parents: diff changeset	2353 emit_opcode( cbuf, 0x8B );
a61af66fc99e Initial load duke parents: diff changeset	2354 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2355 // SAR $dst.hi,31
a61af66fc99e Initial load duke parents: diff changeset	2356 emit_opcode(cbuf, 0xC1);
a61af66fc99e Initial load duke parents: diff changeset	2357 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2358 emit_d8(cbuf, 0x1F );
a61af66fc99e Initial load duke parents: diff changeset	2359 // small:
a61af66fc99e Initial load duke parents: diff changeset	2360 // SHRD $dst.lo,$dst.hi,$shift
a61af66fc99e Initial load duke parents: diff changeset	2361 emit_opcode(cbuf,0x0F);
a61af66fc99e Initial load duke parents: diff changeset	2362 emit_opcode(cbuf,0xAD);
a61af66fc99e Initial load duke parents: diff changeset	2363 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2364 // SAR $dst.hi,$shift"
a61af66fc99e Initial load duke parents: diff changeset	2365 emit_opcode(cbuf,0xD3);
a61af66fc99e Initial load duke parents: diff changeset	2366 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2367 %}
a61af66fc99e Initial load duke parents: diff changeset	2368
a61af66fc99e Initial load duke parents: diff changeset	2369
a61af66fc99e Initial load duke parents: diff changeset	2370 // ----------------- Encodings for floating point unit -----------------
a61af66fc99e Initial load duke parents: diff changeset	2371 // May leave result in FPU-TOS or FPU reg depending on opcodes
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2372 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
0 a61af66fc99e Initial load duke parents: diff changeset	2373 $$$emit8$primary;
a61af66fc99e Initial load duke parents: diff changeset	2374 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2375 %}
a61af66fc99e Initial load duke parents: diff changeset	2376
a61af66fc99e Initial load duke parents: diff changeset	2377 // Pop argument in FPR0 with FSTP ST(0)
a61af66fc99e Initial load duke parents: diff changeset	2378 enc_class PopFPU() %{
a61af66fc99e Initial load duke parents: diff changeset	2379 emit_opcode( cbuf, 0xDD );
a61af66fc99e Initial load duke parents: diff changeset	2380 emit_d8( cbuf, 0xD8 );
a61af66fc99e Initial load duke parents: diff changeset	2381 %}
a61af66fc99e Initial load duke parents: diff changeset	2382
a61af66fc99e Initial load duke parents: diff changeset	2383 // !!!!! equivalent to Pop_Reg_F
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2384 enc_class Pop_Reg_DPR( regDPR dst ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2385 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
a61af66fc99e Initial load duke parents: diff changeset	2386 emit_d8( cbuf, 0xD8+$dst$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2387 %}
a61af66fc99e Initial load duke parents: diff changeset	2388
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2389 enc_class Push_Reg_DPR( regDPR dst ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2390 emit_opcode( cbuf, 0xD9 );
a61af66fc99e Initial load duke parents: diff changeset	2391 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
a61af66fc99e Initial load duke parents: diff changeset	2392 %}
a61af66fc99e Initial load duke parents: diff changeset	2393
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2394 enc_class strictfp_bias1( regDPR dst ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2395 emit_opcode( cbuf, 0xDB ); // FLD m80real
a61af66fc99e Initial load duke parents: diff changeset	2396 emit_opcode( cbuf, 0x2D );
a61af66fc99e Initial load duke parents: diff changeset	2397 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
a61af66fc99e Initial load duke parents: diff changeset	2398 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
a61af66fc99e Initial load duke parents: diff changeset	2399 emit_opcode( cbuf, 0xC8+$dst$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2400 %}
a61af66fc99e Initial load duke parents: diff changeset	2401
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2402 enc_class strictfp_bias2( regDPR dst ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2403 emit_opcode( cbuf, 0xDB ); // FLD m80real
a61af66fc99e Initial load duke parents: diff changeset	2404 emit_opcode( cbuf, 0x2D );
a61af66fc99e Initial load duke parents: diff changeset	2405 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
a61af66fc99e Initial load duke parents: diff changeset	2406 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
a61af66fc99e Initial load duke parents: diff changeset	2407 emit_opcode( cbuf, 0xC8+$dst$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2408 %}
a61af66fc99e Initial load duke parents: diff changeset	2409
a61af66fc99e Initial load duke parents: diff changeset	2410 // Special case for moving an integer register to a stack slot.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	2411 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
0 a61af66fc99e Initial load duke parents: diff changeset	2412 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
a61af66fc99e Initial load duke parents: diff changeset	2413 %}
a61af66fc99e Initial load duke parents: diff changeset	2414
a61af66fc99e Initial load duke parents: diff changeset	2415 // Special case for moving a register to a stack slot.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	2416 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
0 a61af66fc99e Initial load duke parents: diff changeset	2417 // Opcode already emitted
a61af66fc99e Initial load duke parents: diff changeset	2418 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
a61af66fc99e Initial load duke parents: diff changeset	2419 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
a61af66fc99e Initial load duke parents: diff changeset	2420 emit_d32(cbuf, $dst$$disp); // Displacement
a61af66fc99e Initial load duke parents: diff changeset	2421 %}
a61af66fc99e Initial load duke parents: diff changeset	2422
a61af66fc99e Initial load duke parents: diff changeset	2423 // Push the integer in stackSlot 'src' onto FP-stack
a61af66fc99e Initial load duke parents: diff changeset	2424 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
a61af66fc99e Initial load duke parents: diff changeset	2425 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
a61af66fc99e Initial load duke parents: diff changeset	2426 %}
a61af66fc99e Initial load duke parents: diff changeset	2427
a61af66fc99e Initial load duke parents: diff changeset	2428 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2429 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
0 a61af66fc99e Initial load duke parents: diff changeset	2430 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
a61af66fc99e Initial load duke parents: diff changeset	2431 %}
a61af66fc99e Initial load duke parents: diff changeset	2432
a61af66fc99e Initial load duke parents: diff changeset	2433 // Same as Pop_Mem_F except for opcode
a61af66fc99e Initial load duke parents: diff changeset	2434 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2435 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
0 a61af66fc99e Initial load duke parents: diff changeset	2436 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
a61af66fc99e Initial load duke parents: diff changeset	2437 %}
a61af66fc99e Initial load duke parents: diff changeset	2438
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2439 enc_class Pop_Reg_FPR( regFPR dst ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2440 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
a61af66fc99e Initial load duke parents: diff changeset	2441 emit_d8( cbuf, 0xD8+$dst$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2442 %}
a61af66fc99e Initial load duke parents: diff changeset	2443
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2444 enc_class Push_Reg_FPR( regFPR dst ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2445 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
a61af66fc99e Initial load duke parents: diff changeset	2446 emit_d8( cbuf, 0xC0-1+$dst$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2447 %}
a61af66fc99e Initial load duke parents: diff changeset	2448
a61af66fc99e Initial load duke parents: diff changeset	2449 // Push FPU's float to a stack-slot, and pop FPU-stack
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2450 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2451 int pop = 0x02;
a61af66fc99e Initial load duke parents: diff changeset	2452 if ($src$$reg != FPR1L_enc) {
a61af66fc99e Initial load duke parents: diff changeset	2453 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
a61af66fc99e Initial load duke parents: diff changeset	2454 emit_d8( cbuf, 0xC0-1+$src$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2455 pop = 0x03;
a61af66fc99e Initial load duke parents: diff changeset	2456 }
a61af66fc99e Initial load duke parents: diff changeset	2457 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
a61af66fc99e Initial load duke parents: diff changeset	2458 %}
a61af66fc99e Initial load duke parents: diff changeset	2459
a61af66fc99e Initial load duke parents: diff changeset	2460 // Push FPU's double to a stack-slot, and pop FPU-stack
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2461 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2462 int pop = 0x02;
a61af66fc99e Initial load duke parents: diff changeset	2463 if ($src$$reg != FPR1L_enc) {
a61af66fc99e Initial load duke parents: diff changeset	2464 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
a61af66fc99e Initial load duke parents: diff changeset	2465 emit_d8( cbuf, 0xC0-1+$src$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2466 pop = 0x03;
a61af66fc99e Initial load duke parents: diff changeset	2467 }
a61af66fc99e Initial load duke parents: diff changeset	2468 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
a61af66fc99e Initial load duke parents: diff changeset	2469 %}
a61af66fc99e Initial load duke parents: diff changeset	2470
a61af66fc99e Initial load duke parents: diff changeset	2471 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2472 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2473 int pop = 0xD0 - 1; // -1 since we skip FLD
a61af66fc99e Initial load duke parents: diff changeset	2474 if ($src$$reg != FPR1L_enc) {
a61af66fc99e Initial load duke parents: diff changeset	2475 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
a61af66fc99e Initial load duke parents: diff changeset	2476 emit_d8( cbuf, 0xC0-1+$src$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2477 pop = 0xD8;
a61af66fc99e Initial load duke parents: diff changeset	2478 }
a61af66fc99e Initial load duke parents: diff changeset	2479 emit_opcode( cbuf, 0xDD );
a61af66fc99e Initial load duke parents: diff changeset	2480 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
a61af66fc99e Initial load duke parents: diff changeset	2481 %}
a61af66fc99e Initial load duke parents: diff changeset	2482
a61af66fc99e Initial load duke parents: diff changeset	2483
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2484 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2485 // load dst in FPR0
a61af66fc99e Initial load duke parents: diff changeset	2486 emit_opcode( cbuf, 0xD9 );
a61af66fc99e Initial load duke parents: diff changeset	2487 emit_d8( cbuf, 0xC0-1+$dst$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2488 if ($src$$reg != FPR1L_enc) {
a61af66fc99e Initial load duke parents: diff changeset	2489 // fincstp
a61af66fc99e Initial load duke parents: diff changeset	2490 emit_opcode (cbuf, 0xD9);
a61af66fc99e Initial load duke parents: diff changeset	2491 emit_opcode (cbuf, 0xF7);
a61af66fc99e Initial load duke parents: diff changeset	2492 // swap src with FPR1:
a61af66fc99e Initial load duke parents: diff changeset	2493 // FXCH FPR1 with src
a61af66fc99e Initial load duke parents: diff changeset	2494 emit_opcode(cbuf, 0xD9);
a61af66fc99e Initial load duke parents: diff changeset	2495 emit_d8(cbuf, 0xC8-1+$src$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2496 // fdecstp
a61af66fc99e Initial load duke parents: diff changeset	2497 emit_opcode (cbuf, 0xD9);
a61af66fc99e Initial load duke parents: diff changeset	2498 emit_opcode (cbuf, 0xF6);
a61af66fc99e Initial load duke parents: diff changeset	2499 }
a61af66fc99e Initial load duke parents: diff changeset	2500 %}
a61af66fc99e Initial load duke parents: diff changeset	2501
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2502 enc_class Push_ModD_encoding(regD src0, regD src1) %{
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2503 MacroAssembler _masm(&cbuf);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2504 __ subptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2505 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2506 __ fld_d(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2507 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2508 __ fld_d(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2509 %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2510
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2511 enc_class Push_ModF_encoding(regF src0, regF src1) %{
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2512 MacroAssembler _masm(&cbuf);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2513 __ subptr(rsp, 4);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2514 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2515 __ fld_s(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2516 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2517 __ fld_s(Address(rsp, 0));
0 a61af66fc99e Initial load duke parents: diff changeset	2518 %}
a61af66fc99e Initial load duke parents: diff changeset	2519
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2520 enc_class Push_ResultD(regD dst) %{
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2521 MacroAssembler _masm(&cbuf);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2522 __ fstp_d(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2523 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2524 __ addptr(rsp, 8);
0 a61af66fc99e Initial load duke parents: diff changeset	2525 %}
a61af66fc99e Initial load duke parents: diff changeset	2526
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2527 enc_class Push_ResultF(regF dst, immI d8) %{
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2528 MacroAssembler _masm(&cbuf);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2529 __ fstp_s(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2530 __ movflt($dst$$XMMRegister, Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2531 __ addptr(rsp, $d8$$constant);
0 a61af66fc99e Initial load duke parents: diff changeset	2532 %}
a61af66fc99e Initial load duke parents: diff changeset	2533
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2534 enc_class Push_SrcD(regD src) %{
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2535 MacroAssembler _masm(&cbuf);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2536 __ subptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2537 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2538 __ fld_d(Address(rsp, 0));
0 a61af66fc99e Initial load duke parents: diff changeset	2539 %}
a61af66fc99e Initial load duke parents: diff changeset	2540
a61af66fc99e Initial load duke parents: diff changeset	2541 enc_class push_stack_temp_qword() %{
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2542 MacroAssembler _masm(&cbuf);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2543 __ subptr(rsp, 8);
0 a61af66fc99e Initial load duke parents: diff changeset	2544 %}
a61af66fc99e Initial load duke parents: diff changeset	2545
a61af66fc99e Initial load duke parents: diff changeset	2546 enc_class pop_stack_temp_qword() %{
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2547 MacroAssembler _masm(&cbuf);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2548 __ addptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2549 %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2550
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2551 enc_class push_xmm_to_fpr1(regD src) %{
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2552 MacroAssembler _masm(&cbuf);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2553 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	2554 __ fld_d(Address(rsp, 0));
0 a61af66fc99e Initial load duke parents: diff changeset	2555 %}
a61af66fc99e Initial load duke parents: diff changeset	2556
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2557 enc_class Push_Result_Mod_DPR( regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2558 if ($src$$reg != FPR1L_enc) {
a61af66fc99e Initial load duke parents: diff changeset	2559 // fincstp
a61af66fc99e Initial load duke parents: diff changeset	2560 emit_opcode (cbuf, 0xD9);
a61af66fc99e Initial load duke parents: diff changeset	2561 emit_opcode (cbuf, 0xF7);
a61af66fc99e Initial load duke parents: diff changeset	2562 // FXCH FPR1 with src
a61af66fc99e Initial load duke parents: diff changeset	2563 emit_opcode(cbuf, 0xD9);
a61af66fc99e Initial load duke parents: diff changeset	2564 emit_d8(cbuf, 0xC8-1+$src$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2565 // fdecstp
a61af66fc99e Initial load duke parents: diff changeset	2566 emit_opcode (cbuf, 0xD9);
a61af66fc99e Initial load duke parents: diff changeset	2567 emit_opcode (cbuf, 0xF6);
a61af66fc99e Initial load duke parents: diff changeset	2568 }
a61af66fc99e Initial load duke parents: diff changeset	2569 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
a61af66fc99e Initial load duke parents: diff changeset	2570 // // FSTP FPR$dst$$reg
a61af66fc99e Initial load duke parents: diff changeset	2571 // emit_opcode( cbuf, 0xDD );
a61af66fc99e Initial load duke parents: diff changeset	2572 // emit_d8( cbuf, 0xD8+$dst$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2573 %}
a61af66fc99e Initial load duke parents: diff changeset	2574
a61af66fc99e Initial load duke parents: diff changeset	2575 enc_class fnstsw_sahf_skip_parity() %{
a61af66fc99e Initial load duke parents: diff changeset	2576 // fnstsw ax
a61af66fc99e Initial load duke parents: diff changeset	2577 emit_opcode( cbuf, 0xDF );
a61af66fc99e Initial load duke parents: diff changeset	2578 emit_opcode( cbuf, 0xE0 );
a61af66fc99e Initial load duke parents: diff changeset	2579 // sahf
a61af66fc99e Initial load duke parents: diff changeset	2580 emit_opcode( cbuf, 0x9E );
a61af66fc99e Initial load duke parents: diff changeset	2581 // jnp ::skip
a61af66fc99e Initial load duke parents: diff changeset	2582 emit_opcode( cbuf, 0x7B );
a61af66fc99e Initial load duke parents: diff changeset	2583 emit_opcode( cbuf, 0x05 );
a61af66fc99e Initial load duke parents: diff changeset	2584 %}
a61af66fc99e Initial load duke parents: diff changeset	2585
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	2586 enc_class emitModDPR() %{
0 a61af66fc99e Initial load duke parents: diff changeset	2587 // fprem must be iterative
a61af66fc99e Initial load duke parents: diff changeset	2588 // :: loop
a61af66fc99e Initial load duke parents: diff changeset	2589 // fprem
a61af66fc99e Initial load duke parents: diff changeset	2590 emit_opcode( cbuf, 0xD9 );
a61af66fc99e Initial load duke parents: diff changeset	2591 emit_opcode( cbuf, 0xF8 );
a61af66fc99e Initial load duke parents: diff changeset	2592 // wait
a61af66fc99e Initial load duke parents: diff changeset	2593 emit_opcode( cbuf, 0x9b );
a61af66fc99e Initial load duke parents: diff changeset	2594 // fnstsw ax
a61af66fc99e Initial load duke parents: diff changeset	2595 emit_opcode( cbuf, 0xDF );
a61af66fc99e Initial load duke parents: diff changeset	2596 emit_opcode( cbuf, 0xE0 );
a61af66fc99e Initial load duke parents: diff changeset	2597 // sahf
a61af66fc99e Initial load duke parents: diff changeset	2598 emit_opcode( cbuf, 0x9E );
a61af66fc99e Initial load duke parents: diff changeset	2599 // jp ::loop
a61af66fc99e Initial load duke parents: diff changeset	2600 emit_opcode( cbuf, 0x0F );
a61af66fc99e Initial load duke parents: diff changeset	2601 emit_opcode( cbuf, 0x8A );
a61af66fc99e Initial load duke parents: diff changeset	2602 emit_opcode( cbuf, 0xF4 );
a61af66fc99e Initial load duke parents: diff changeset	2603 emit_opcode( cbuf, 0xFF );
a61af66fc99e Initial load duke parents: diff changeset	2604 emit_opcode( cbuf, 0xFF );
a61af66fc99e Initial load duke parents: diff changeset	2605 emit_opcode( cbuf, 0xFF );
a61af66fc99e Initial load duke parents: diff changeset	2606 %}
a61af66fc99e Initial load duke parents: diff changeset	2607
a61af66fc99e Initial load duke parents: diff changeset	2608 enc_class fpu_flags() %{
a61af66fc99e Initial load duke parents: diff changeset	2609 // fnstsw_ax
a61af66fc99e Initial load duke parents: diff changeset	2610 emit_opcode( cbuf, 0xDF);
a61af66fc99e Initial load duke parents: diff changeset	2611 emit_opcode( cbuf, 0xE0);
a61af66fc99e Initial load duke parents: diff changeset	2612 // test ax,0x0400
a61af66fc99e Initial load duke parents: diff changeset	2613 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
a61af66fc99e Initial load duke parents: diff changeset	2614 emit_opcode( cbuf, 0xA9 );
a61af66fc99e Initial load duke parents: diff changeset	2615 emit_d16 ( cbuf, 0x0400 );
a61af66fc99e Initial load duke parents: diff changeset	2616 // // // This sequence works, but stalls for 12-16 cycles on PPro
a61af66fc99e Initial load duke parents: diff changeset	2617 // // test rax,0x0400
a61af66fc99e Initial load duke parents: diff changeset	2618 // emit_opcode( cbuf, 0xA9 );
a61af66fc99e Initial load duke parents: diff changeset	2619 // emit_d32 ( cbuf, 0x00000400 );
a61af66fc99e Initial load duke parents: diff changeset	2620 //
a61af66fc99e Initial load duke parents: diff changeset	2621 // jz exit (no unordered comparison)
a61af66fc99e Initial load duke parents: diff changeset	2622 emit_opcode( cbuf, 0x74 );
a61af66fc99e Initial load duke parents: diff changeset	2623 emit_d8 ( cbuf, 0x02 );
a61af66fc99e Initial load duke parents: diff changeset	2624 // mov ah,1 - treat as LT case (set carry flag)
a61af66fc99e Initial load duke parents: diff changeset	2625 emit_opcode( cbuf, 0xB4 );
a61af66fc99e Initial load duke parents: diff changeset	2626 emit_d8 ( cbuf, 0x01 );
a61af66fc99e Initial load duke parents: diff changeset	2627 // sahf
a61af66fc99e Initial load duke parents: diff changeset	2628 emit_opcode( cbuf, 0x9E);
a61af66fc99e Initial load duke parents: diff changeset	2629 %}
a61af66fc99e Initial load duke parents: diff changeset	2630
a61af66fc99e Initial load duke parents: diff changeset	2631 enc_class cmpF_P6_fixup() %{
a61af66fc99e Initial load duke parents: diff changeset	2632 // Fixup the integer flags in case comparison involved a NaN
a61af66fc99e Initial load duke parents: diff changeset	2633 //
a61af66fc99e Initial load duke parents: diff changeset	2634 // JNP exit (no unordered comparison, P-flag is set by NaN)
a61af66fc99e Initial load duke parents: diff changeset	2635 emit_opcode( cbuf, 0x7B );
a61af66fc99e Initial load duke parents: diff changeset	2636 emit_d8 ( cbuf, 0x03 );
a61af66fc99e Initial load duke parents: diff changeset	2637 // MOV AH,1 - treat as LT case (set carry flag)
a61af66fc99e Initial load duke parents: diff changeset	2638 emit_opcode( cbuf, 0xB4 );
a61af66fc99e Initial load duke parents: diff changeset	2639 emit_d8 ( cbuf, 0x01 );
a61af66fc99e Initial load duke parents: diff changeset	2640 // SAHF
a61af66fc99e Initial load duke parents: diff changeset	2641 emit_opcode( cbuf, 0x9E);
a61af66fc99e Initial load duke parents: diff changeset	2642 // NOP // target for branch to avoid branch to branch
a61af66fc99e Initial load duke parents: diff changeset	2643 emit_opcode( cbuf, 0x90);
a61af66fc99e Initial load duke parents: diff changeset	2644 %}
a61af66fc99e Initial load duke parents: diff changeset	2645
a61af66fc99e Initial load duke parents: diff changeset	2646 // fnstsw_ax();
a61af66fc99e Initial load duke parents: diff changeset	2647 // sahf();
a61af66fc99e Initial load duke parents: diff changeset	2648 // movl(dst, nan_result);
a61af66fc99e Initial load duke parents: diff changeset	2649 // jcc(Assembler::parity, exit);
a61af66fc99e Initial load duke parents: diff changeset	2650 // movl(dst, less_result);
a61af66fc99e Initial load duke parents: diff changeset	2651 // jcc(Assembler::below, exit);
a61af66fc99e Initial load duke parents: diff changeset	2652 // movl(dst, equal_result);
a61af66fc99e Initial load duke parents: diff changeset	2653 // jcc(Assembler::equal, exit);
a61af66fc99e Initial load duke parents: diff changeset	2654 // movl(dst, greater_result);
a61af66fc99e Initial load duke parents: diff changeset	2655
a61af66fc99e Initial load duke parents: diff changeset	2656 // less_result = 1;
a61af66fc99e Initial load duke parents: diff changeset	2657 // greater_result = -1;
a61af66fc99e Initial load duke parents: diff changeset	2658 // equal_result = 0;
a61af66fc99e Initial load duke parents: diff changeset	2659 // nan_result = -1;
a61af66fc99e Initial load duke parents: diff changeset	2660
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	2661 enc_class CmpF_Result(rRegI dst) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2662 // fnstsw_ax();
a61af66fc99e Initial load duke parents: diff changeset	2663 emit_opcode( cbuf, 0xDF);
a61af66fc99e Initial load duke parents: diff changeset	2664 emit_opcode( cbuf, 0xE0);
a61af66fc99e Initial load duke parents: diff changeset	2665 // sahf
a61af66fc99e Initial load duke parents: diff changeset	2666 emit_opcode( cbuf, 0x9E);
a61af66fc99e Initial load duke parents: diff changeset	2667 // movl(dst, nan_result);
a61af66fc99e Initial load duke parents: diff changeset	2668 emit_opcode( cbuf, 0xB8 + $dst$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2669 emit_d32( cbuf, -1 );
a61af66fc99e Initial load duke parents: diff changeset	2670 // jcc(Assembler::parity, exit);
a61af66fc99e Initial load duke parents: diff changeset	2671 emit_opcode( cbuf, 0x7A );
a61af66fc99e Initial load duke parents: diff changeset	2672 emit_d8 ( cbuf, 0x13 );
a61af66fc99e Initial load duke parents: diff changeset	2673 // movl(dst, less_result);
a61af66fc99e Initial load duke parents: diff changeset	2674 emit_opcode( cbuf, 0xB8 + $dst$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2675 emit_d32( cbuf, -1 );
a61af66fc99e Initial load duke parents: diff changeset	2676 // jcc(Assembler::below, exit);
a61af66fc99e Initial load duke parents: diff changeset	2677 emit_opcode( cbuf, 0x72 );
a61af66fc99e Initial load duke parents: diff changeset	2678 emit_d8 ( cbuf, 0x0C );
a61af66fc99e Initial load duke parents: diff changeset	2679 // movl(dst, equal_result);
a61af66fc99e Initial load duke parents: diff changeset	2680 emit_opcode( cbuf, 0xB8 + $dst$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2681 emit_d32( cbuf, 0 );
a61af66fc99e Initial load duke parents: diff changeset	2682 // jcc(Assembler::equal, exit);
a61af66fc99e Initial load duke parents: diff changeset	2683 emit_opcode( cbuf, 0x74 );
a61af66fc99e Initial load duke parents: diff changeset	2684 emit_d8 ( cbuf, 0x05 );
a61af66fc99e Initial load duke parents: diff changeset	2685 // movl(dst, greater_result);
a61af66fc99e Initial load duke parents: diff changeset	2686 emit_opcode( cbuf, 0xB8 + $dst$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2687 emit_d32( cbuf, 1 );
a61af66fc99e Initial load duke parents: diff changeset	2688 %}
a61af66fc99e Initial load duke parents: diff changeset	2689
a61af66fc99e Initial load duke parents: diff changeset	2690
a61af66fc99e Initial load duke parents: diff changeset	2691 // Compare the longs and set flags
a61af66fc99e Initial load duke parents: diff changeset	2692 // BROKEN! Do Not use as-is
a61af66fc99e Initial load duke parents: diff changeset	2693 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
a61af66fc99e Initial load duke parents: diff changeset	2694 // CMP $src1.hi,$src2.hi
a61af66fc99e Initial load duke parents: diff changeset	2695 emit_opcode( cbuf, 0x3B );
a61af66fc99e Initial load duke parents: diff changeset	2696 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2697 // JNE,s done
a61af66fc99e Initial load duke parents: diff changeset	2698 emit_opcode(cbuf,0x75);
a61af66fc99e Initial load duke parents: diff changeset	2699 emit_d8(cbuf, 2 );
a61af66fc99e Initial load duke parents: diff changeset	2700 // CMP $src1.lo,$src2.lo
a61af66fc99e Initial load duke parents: diff changeset	2701 emit_opcode( cbuf, 0x3B );
a61af66fc99e Initial load duke parents: diff changeset	2702 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2703 // done:
a61af66fc99e Initial load duke parents: diff changeset	2704 %}
a61af66fc99e Initial load duke parents: diff changeset	2705
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	2706 enc_class convert_int_long( regL dst, rRegI src ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2707 // mov $dst.lo,$src
a61af66fc99e Initial load duke parents: diff changeset	2708 int dst_encoding = $dst$$reg;
a61af66fc99e Initial load duke parents: diff changeset	2709 int src_encoding = $src$$reg;
a61af66fc99e Initial load duke parents: diff changeset	2710 encode_Copy( cbuf, dst_encoding , src_encoding );
a61af66fc99e Initial load duke parents: diff changeset	2711 // mov $dst.hi,$src
a61af66fc99e Initial load duke parents: diff changeset	2712 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
a61af66fc99e Initial load duke parents: diff changeset	2713 // sar $dst.hi,31
a61af66fc99e Initial load duke parents: diff changeset	2714 emit_opcode( cbuf, 0xC1 );
a61af66fc99e Initial load duke parents: diff changeset	2715 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
a61af66fc99e Initial load duke parents: diff changeset	2716 emit_d8(cbuf, 0x1F );
a61af66fc99e Initial load duke parents: diff changeset	2717 %}
a61af66fc99e Initial load duke parents: diff changeset	2718
a61af66fc99e Initial load duke parents: diff changeset	2719 enc_class convert_long_double( eRegL src ) %{
a61af66fc99e Initial load duke parents: diff changeset	2720 // push $src.hi
a61af66fc99e Initial load duke parents: diff changeset	2721 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
a61af66fc99e Initial load duke parents: diff changeset	2722 // push $src.lo
a61af66fc99e Initial load duke parents: diff changeset	2723 emit_opcode(cbuf, 0x50+$src$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2724 // fild 64-bits at [SP]
a61af66fc99e Initial load duke parents: diff changeset	2725 emit_opcode(cbuf,0xdf);
a61af66fc99e Initial load duke parents: diff changeset	2726 emit_d8(cbuf, 0x6C);
a61af66fc99e Initial load duke parents: diff changeset	2727 emit_d8(cbuf, 0x24);
a61af66fc99e Initial load duke parents: diff changeset	2728 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load duke parents: diff changeset	2729 // pop stack
a61af66fc99e Initial load duke parents: diff changeset	2730 emit_opcode(cbuf, 0x83); // add SP, #8
a61af66fc99e Initial load duke parents: diff changeset	2731 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
a61af66fc99e Initial load duke parents: diff changeset	2732 emit_d8(cbuf, 0x8);
a61af66fc99e Initial load duke parents: diff changeset	2733 %}
a61af66fc99e Initial load duke parents: diff changeset	2734
a61af66fc99e Initial load duke parents: diff changeset	2735 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
a61af66fc99e Initial load duke parents: diff changeset	2736 // IMUL EDX:EAX,$src1
a61af66fc99e Initial load duke parents: diff changeset	2737 emit_opcode( cbuf, 0xF7 );
a61af66fc99e Initial load duke parents: diff changeset	2738 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2739 // SAR EDX,$cnt-32
a61af66fc99e Initial load duke parents: diff changeset	2740 int shift_count = ((int)$cnt$$constant) - 32;
a61af66fc99e Initial load duke parents: diff changeset	2741 if (shift_count > 0) {
a61af66fc99e Initial load duke parents: diff changeset	2742 emit_opcode(cbuf, 0xC1);
a61af66fc99e Initial load duke parents: diff changeset	2743 emit_rm(cbuf, 0x3, 7, $dst$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2744 emit_d8(cbuf, shift_count);
a61af66fc99e Initial load duke parents: diff changeset	2745 }
a61af66fc99e Initial load duke parents: diff changeset	2746 %}
a61af66fc99e Initial load duke parents: diff changeset	2747
a61af66fc99e Initial load duke parents: diff changeset	2748 // this version doesn't have add sp, 8
a61af66fc99e Initial load duke parents: diff changeset	2749 enc_class convert_long_double2( eRegL src ) %{
a61af66fc99e Initial load duke parents: diff changeset	2750 // push $src.hi
a61af66fc99e Initial load duke parents: diff changeset	2751 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
a61af66fc99e Initial load duke parents: diff changeset	2752 // push $src.lo
a61af66fc99e Initial load duke parents: diff changeset	2753 emit_opcode(cbuf, 0x50+$src$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2754 // fild 64-bits at [SP]
a61af66fc99e Initial load duke parents: diff changeset	2755 emit_opcode(cbuf,0xdf);
a61af66fc99e Initial load duke parents: diff changeset	2756 emit_d8(cbuf, 0x6C);
a61af66fc99e Initial load duke parents: diff changeset	2757 emit_d8(cbuf, 0x24);
a61af66fc99e Initial load duke parents: diff changeset	2758 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load duke parents: diff changeset	2759 %}
a61af66fc99e Initial load duke parents: diff changeset	2760
a61af66fc99e Initial load duke parents: diff changeset	2761 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
a61af66fc99e Initial load duke parents: diff changeset	2762 // Basic idea: long = (long)int * (long)int
a61af66fc99e Initial load duke parents: diff changeset	2763 // IMUL EDX:EAX, src
a61af66fc99e Initial load duke parents: diff changeset	2764 emit_opcode( cbuf, 0xF7 );
a61af66fc99e Initial load duke parents: diff changeset	2765 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2766 %}
a61af66fc99e Initial load duke parents: diff changeset	2767
a61af66fc99e Initial load duke parents: diff changeset	2768 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
a61af66fc99e Initial load duke parents: diff changeset	2769 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
a61af66fc99e Initial load duke parents: diff changeset	2770 // MUL EDX:EAX, src
a61af66fc99e Initial load duke parents: diff changeset	2771 emit_opcode( cbuf, 0xF7 );
a61af66fc99e Initial load duke parents: diff changeset	2772 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2773 %}
a61af66fc99e Initial load duke parents: diff changeset	2774
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	2775 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2776 // Basic idea: lo(result) = lo(x_lo * y_lo)
a61af66fc99e Initial load duke parents: diff changeset	2777 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
a61af66fc99e Initial load duke parents: diff changeset	2778 // MOV $tmp,$src.lo
a61af66fc99e Initial load duke parents: diff changeset	2779 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2780 // IMUL $tmp,EDX
a61af66fc99e Initial load duke parents: diff changeset	2781 emit_opcode( cbuf, 0x0F );
a61af66fc99e Initial load duke parents: diff changeset	2782 emit_opcode( cbuf, 0xAF );
a61af66fc99e Initial load duke parents: diff changeset	2783 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2784 // MOV EDX,$src.hi
a61af66fc99e Initial load duke parents: diff changeset	2785 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2786 // IMUL EDX,EAX
a61af66fc99e Initial load duke parents: diff changeset	2787 emit_opcode( cbuf, 0x0F );
a61af66fc99e Initial load duke parents: diff changeset	2788 emit_opcode( cbuf, 0xAF );
a61af66fc99e Initial load duke parents: diff changeset	2789 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2790 // ADD $tmp,EDX
a61af66fc99e Initial load duke parents: diff changeset	2791 emit_opcode( cbuf, 0x03 );
a61af66fc99e Initial load duke parents: diff changeset	2792 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2793 // MUL EDX:EAX,$src.lo
a61af66fc99e Initial load duke parents: diff changeset	2794 emit_opcode( cbuf, 0xF7 );
a61af66fc99e Initial load duke parents: diff changeset	2795 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2796 // ADD EDX,ESI
a61af66fc99e Initial load duke parents: diff changeset	2797 emit_opcode( cbuf, 0x03 );
a61af66fc99e Initial load duke parents: diff changeset	2798 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2799 %}
a61af66fc99e Initial load duke parents: diff changeset	2800
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	2801 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2802 // Basic idea: lo(result) = lo(src * y_lo)
a61af66fc99e Initial load duke parents: diff changeset	2803 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
a61af66fc99e Initial load duke parents: diff changeset	2804 // IMUL $tmp,EDX,$src
a61af66fc99e Initial load duke parents: diff changeset	2805 emit_opcode( cbuf, 0x6B );
a61af66fc99e Initial load duke parents: diff changeset	2806 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2807 emit_d8( cbuf, (int)$src$$constant );
a61af66fc99e Initial load duke parents: diff changeset	2808 // MOV EDX,$src
a61af66fc99e Initial load duke parents: diff changeset	2809 emit_opcode(cbuf, 0xB8 + EDX_enc);
a61af66fc99e Initial load duke parents: diff changeset	2810 emit_d32( cbuf, (int)$src$$constant );
a61af66fc99e Initial load duke parents: diff changeset	2811 // MUL EDX:EAX,EDX
a61af66fc99e Initial load duke parents: diff changeset	2812 emit_opcode( cbuf, 0xF7 );
a61af66fc99e Initial load duke parents: diff changeset	2813 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
a61af66fc99e Initial load duke parents: diff changeset	2814 // ADD EDX,ESI
a61af66fc99e Initial load duke parents: diff changeset	2815 emit_opcode( cbuf, 0x03 );
a61af66fc99e Initial load duke parents: diff changeset	2816 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2817 %}
a61af66fc99e Initial load duke parents: diff changeset	2818
a61af66fc99e Initial load duke parents: diff changeset	2819 enc_class long_div( eRegL src1, eRegL src2 ) %{
a61af66fc99e Initial load duke parents: diff changeset	2820 // PUSH src1.hi
a61af66fc99e Initial load duke parents: diff changeset	2821 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2822 // PUSH src1.lo
a61af66fc99e Initial load duke parents: diff changeset	2823 emit_opcode(cbuf, 0x50+$src1$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2824 // PUSH src2.hi
a61af66fc99e Initial load duke parents: diff changeset	2825 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2826 // PUSH src2.lo
a61af66fc99e Initial load duke parents: diff changeset	2827 emit_opcode(cbuf, 0x50+$src2$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2828 // CALL directly to the runtime
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	2829 cbuf.set_insts_mark();
0 a61af66fc99e Initial load duke parents: diff changeset	2830 emit_opcode(cbuf,0xE8); // Call into runtime
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	2831 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
0 a61af66fc99e Initial load duke parents: diff changeset	2832 // Restore stack
a61af66fc99e Initial load duke parents: diff changeset	2833 emit_opcode(cbuf, 0x83); // add SP, #framesize
a61af66fc99e Initial load duke parents: diff changeset	2834 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
a61af66fc99e Initial load duke parents: diff changeset	2835 emit_d8(cbuf, 4*4);
a61af66fc99e Initial load duke parents: diff changeset	2836 %}
a61af66fc99e Initial load duke parents: diff changeset	2837
a61af66fc99e Initial load duke parents: diff changeset	2838 enc_class long_mod( eRegL src1, eRegL src2 ) %{
a61af66fc99e Initial load duke parents: diff changeset	2839 // PUSH src1.hi
a61af66fc99e Initial load duke parents: diff changeset	2840 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2841 // PUSH src1.lo
a61af66fc99e Initial load duke parents: diff changeset	2842 emit_opcode(cbuf, 0x50+$src1$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2843 // PUSH src2.hi
a61af66fc99e Initial load duke parents: diff changeset	2844 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2845 // PUSH src2.lo
a61af66fc99e Initial load duke parents: diff changeset	2846 emit_opcode(cbuf, 0x50+$src2$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2847 // CALL directly to the runtime
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	2848 cbuf.set_insts_mark();
0 a61af66fc99e Initial load duke parents: diff changeset	2849 emit_opcode(cbuf,0xE8); // Call into runtime
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	2850 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
0 a61af66fc99e Initial load duke parents: diff changeset	2851 // Restore stack
a61af66fc99e Initial load duke parents: diff changeset	2852 emit_opcode(cbuf, 0x83); // add SP, #framesize
a61af66fc99e Initial load duke parents: diff changeset	2853 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
a61af66fc99e Initial load duke parents: diff changeset	2854 emit_d8(cbuf, 4*4);
a61af66fc99e Initial load duke parents: diff changeset	2855 %}
a61af66fc99e Initial load duke parents: diff changeset	2856
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	2857 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2858 // MOV $tmp,$src.lo
a61af66fc99e Initial load duke parents: diff changeset	2859 emit_opcode(cbuf, 0x8B);
a61af66fc99e Initial load duke parents: diff changeset	2860 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2861 // OR $tmp,$src.hi
a61af66fc99e Initial load duke parents: diff changeset	2862 emit_opcode(cbuf, 0x0B);
a61af66fc99e Initial load duke parents: diff changeset	2863 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
a61af66fc99e Initial load duke parents: diff changeset	2864 %}
a61af66fc99e Initial load duke parents: diff changeset	2865
a61af66fc99e Initial load duke parents: diff changeset	2866 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
a61af66fc99e Initial load duke parents: diff changeset	2867 // CMP $src1.lo,$src2.lo
a61af66fc99e Initial load duke parents: diff changeset	2868 emit_opcode( cbuf, 0x3B );
a61af66fc99e Initial load duke parents: diff changeset	2869 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2870 // JNE,s skip
a61af66fc99e Initial load duke parents: diff changeset	2871 emit_cc(cbuf, 0x70, 0x5);
a61af66fc99e Initial load duke parents: diff changeset	2872 emit_d8(cbuf,2);
a61af66fc99e Initial load duke parents: diff changeset	2873 // CMP $src1.hi,$src2.hi
a61af66fc99e Initial load duke parents: diff changeset	2874 emit_opcode( cbuf, 0x3B );
a61af66fc99e Initial load duke parents: diff changeset	2875 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2876 %}
a61af66fc99e Initial load duke parents: diff changeset	2877
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	2878 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2879 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
a61af66fc99e Initial load duke parents: diff changeset	2880 emit_opcode( cbuf, 0x3B );
a61af66fc99e Initial load duke parents: diff changeset	2881 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2882 // MOV $tmp,$src1.hi
a61af66fc99e Initial load duke parents: diff changeset	2883 emit_opcode( cbuf, 0x8B );
a61af66fc99e Initial load duke parents: diff changeset	2884 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2885 // SBB $tmp,$src2.hi\t! Compute flags for long compare
a61af66fc99e Initial load duke parents: diff changeset	2886 emit_opcode( cbuf, 0x1B );
a61af66fc99e Initial load duke parents: diff changeset	2887 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2888 %}
a61af66fc99e Initial load duke parents: diff changeset	2889
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	2890 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	2891 // XOR $tmp,$tmp
a61af66fc99e Initial load duke parents: diff changeset	2892 emit_opcode(cbuf,0x33); // XOR
a61af66fc99e Initial load duke parents: diff changeset	2893 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
a61af66fc99e Initial load duke parents: diff changeset	2894 // CMP $tmp,$src.lo
a61af66fc99e Initial load duke parents: diff changeset	2895 emit_opcode( cbuf, 0x3B );
a61af66fc99e Initial load duke parents: diff changeset	2896 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2897 // SBB $tmp,$src.hi
a61af66fc99e Initial load duke parents: diff changeset	2898 emit_opcode( cbuf, 0x1B );
a61af66fc99e Initial load duke parents: diff changeset	2899 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
a61af66fc99e Initial load duke parents: diff changeset	2900 %}
a61af66fc99e Initial load duke parents: diff changeset	2901
a61af66fc99e Initial load duke parents: diff changeset	2902 // Sniff, sniff... smells like Gnu Superoptimizer
a61af66fc99e Initial load duke parents: diff changeset	2903 enc_class neg_long( eRegL dst ) %{
a61af66fc99e Initial load duke parents: diff changeset	2904 emit_opcode(cbuf,0xF7); // NEG hi
a61af66fc99e Initial load duke parents: diff changeset	2905 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
a61af66fc99e Initial load duke parents: diff changeset	2906 emit_opcode(cbuf,0xF7); // NEG lo
a61af66fc99e Initial load duke parents: diff changeset	2907 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
a61af66fc99e Initial load duke parents: diff changeset	2908 emit_opcode(cbuf,0x83); // SBB hi,0
a61af66fc99e Initial load duke parents: diff changeset	2909 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
a61af66fc99e Initial load duke parents: diff changeset	2910 emit_d8 (cbuf,0 );
a61af66fc99e Initial load duke parents: diff changeset	2911 %}
a61af66fc99e Initial load duke parents: diff changeset	2912
14909 4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2913
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2914 // Because the transitions from emitted code to the runtime
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2915 // monitorenter/exit helper stubs are so slow it's critical that
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2916 // we inline both the stack-locking fast-path and the inflated fast path.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2917 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2918 // See also: cmpFastLock and cmpFastUnlock.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2919 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2920 // What follows is a specialized inline transliteration of the code
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2921 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2922 // another option would be to emit TrySlowEnter and TrySlowExit methods
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2923 // at startup-time. These methods would accept arguments as
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2924 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2925 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2926 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2927 // In practice, however, the # of lock sites is bounded and is usually small.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2928 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2929 // if the processor uses simple bimodal branch predictors keyed by EIP
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2930 // Since the helper routines would be called from multiple synchronization
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2931 // sites.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2932 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2933 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2934 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2935 // to those specialized methods. That'd give us a mostly platform-independent
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2936 // implementation that the JITs could optimize and inline at their pleasure.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2937 // Done correctly, the only time we'd need to cross to native could would be
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2938 // to park() or unpark() threads. We'd also need a few more unsafe operators
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2939 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2940 // (b) explicit barriers or fence operations.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2941 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2942 // TODO:
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2943 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2944 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2945 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2946 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2947 // the lock operators would typically be faster than reifying Self.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2948 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2949 // * Ideally I'd define the primitives as:
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2950 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2951 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2952 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2953 // Instead, we're stuck with a rather awkward and brittle register assignments below.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2954 // Furthermore the register assignments are overconstrained, possibly resulting in
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2955 // sub-optimal code near the synchronization site.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2956 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2957 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2958 // Alternately, use a better sp-proximity test.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2959 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2960 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2961 // Either one is sufficient to uniquely identify a thread.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2962 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2963 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2964 // * Intrinsify notify() and notifyAll() for the common cases where the
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2965 // object is locked by the calling thread but the waitlist is empty.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2966 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2967 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2968 // * use jccb and jmpb instead of jcc and jmp to improve code density.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2969 // But beware of excessive branch density on AMD Opterons.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2970 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2971 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2972 // or failure of the fast-path. If the fast-path fails then we pass
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2973 // control to the slow-path, typically in C. In Fast_Lock and
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2974 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2975 // will emit a conditional branch immediately after the node.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2976 // So we have branches to branches and lots of ICC.ZF games.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2977 // Instead, it might be better to have C2 pass a "FailureLabel"
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2978 // into Fast_Lock and Fast_Unlock. In the case of success, control
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2979 // will drop through the node. ICC.ZF is undefined at exit.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2980 // In the case of failure, the node will branch directly to the
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2981 // FailureLabel
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2982
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2983
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2984 // obj: object to lock
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2985 // box: on-stack box address (displaced header location) - KILLED
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2986 // rax,: tmp -- KILLED
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2987 // scr: tmp -- KILLED
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2988 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2989
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2990 Register objReg = as_Register($obj$$reg);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2991 Register boxReg = as_Register($box$$reg);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2992 Register tmpReg = as_Register($tmp$$reg);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2993 Register scrReg = as_Register($scr$$reg);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2994
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2995 // Ensure the register assignents are disjoint
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2996 guarantee (objReg != boxReg, "") ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2997 guarantee (objReg != tmpReg, "") ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2998 guarantee (objReg != scrReg, "") ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	2999 guarantee (boxReg != tmpReg, "") ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3000 guarantee (boxReg != scrReg, "") ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3001 guarantee (tmpReg == as_Register(EAX_enc), "") ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3002
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3003 MacroAssembler masm(&cbuf);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3004
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3005 if (_counters != NULL) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3006 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3007 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3008 if (EmitSync & 1) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3009 // set box->dhw = unused_mark (3)
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3010 // Force all sync thru slow-path: slow_enter() and slow_exit()
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3011 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3012 masm.cmpptr (rsp, (int32_t)0) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3013 } else
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3014 if (EmitSync & 2) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3015 Label DONE_LABEL ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3016 if (UseBiasedLocking) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3017 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3018 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3019 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3020
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3021 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3022 masm.orptr (tmpReg, 0x1);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3023 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3024 if (os::is_MP()) { masm.lock(); }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3025 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3026 masm.jcc(Assembler::equal, DONE_LABEL);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3027 // Recursive locking
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3028 masm.subptr(tmpReg, rsp);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3029 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3030 masm.movptr(Address(boxReg, 0), tmpReg);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3031 masm.bind(DONE_LABEL) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3032 } else {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3033 // Possible cases that we'll encounter in fast_lock
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3034 // ------------------------------------------------
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3035 // * Inflated
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3036 // -- unlocked
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3037 // -- Locked
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3038 // = by self
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3039 // = by other
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3040 // * biased
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3041 // -- by Self
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3042 // -- by other
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3043 // * neutral
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3044 // * stack-locked
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3045 // -- by self
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3046 // = sp-proximity test hits
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3047 // = sp-proximity test generates false-negative
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3048 // -- by other
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3049 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3050
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3051 Label IsInflated, DONE_LABEL, PopDone ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3052
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3053 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3054 // order to reduce the number of conditional branches in the most common cases.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3055 // Beware -- there's a subtle invariant that fetch of the markword
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3056 // at [FETCH], below, will never observe a biased encoding (*101b).
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3057 // If this invariant is not held we risk exclusion (safety) failure.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3058 if (UseBiasedLocking && !UseOptoBiasInlining) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3059 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3060 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3061
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3062 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3063 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3064 masm.jccb (Assembler::notZero, IsInflated) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3065
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3066 // Attempt stack-locking ...
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3067 masm.orptr (tmpReg, 0x1);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3068 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3069 if (os::is_MP()) { masm.lock(); }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3070 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3071 if (_counters != NULL) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3072 masm.cond_inc32(Assembler::equal,
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3073 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3074 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3075 masm.jccb (Assembler::equal, DONE_LABEL);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3076
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3077 // Recursive locking
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3078 masm.subptr(tmpReg, rsp);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3079 masm.andptr(tmpReg, 0xFFFFF003 );
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3080 masm.movptr(Address(boxReg, 0), tmpReg);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3081 if (_counters != NULL) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3082 masm.cond_inc32(Assembler::equal,
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3083 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3084 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3085 masm.jmp (DONE_LABEL) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3086
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3087 masm.bind (IsInflated) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3088
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3089 // The object is inflated.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3090 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3091 // TODO-FIXME: eliminate the ugly use of manifest constants:
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3092 // Use markOopDesc::monitor_value instead of "2".
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3093 // use markOop::unused_mark() instead of "3".
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3094 // The tmpReg value is an objectMonitor reference ORed with
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3095 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3096 // objectmonitor pointer by masking off the "2" bit or we can just
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3097 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3098 // field offsets with "-2" to compensate for and annul the low-order tag bit.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3099 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3100 // I use the latter as it avoids AGI stalls.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3101 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3102 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3103 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3104 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3105
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3106 // boxReg refers to the on-stack BasicLock in the current frame.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3107 // We'd like to write:
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3108 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3109 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3110 // additional latency as we have another ST in the store buffer that must drain.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3111
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3112 if (EmitSync & 8192) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3113 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3114 masm.get_thread (scrReg) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3115 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3116 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3117 if (os::is_MP()) { masm.lock(); }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3118 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3119 } else
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3120 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3121 masm.movptr(scrReg, boxReg) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3122 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3123
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3124 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3125 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3126 // prefetchw [eax + Offset(_owner)-2]
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3127 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3128 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3129
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3130 if ((EmitSync & 64) == 0) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3131 // Optimistic form: consider XORL tmpReg,tmpReg
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3132 masm.movptr(tmpReg, NULL_WORD) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3133 } else {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3134 // Can suffer RTS->RTO upgrades on shared or cold $ lines
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3135 // Test-And-CAS instead of CAS
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3136 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3137 masm.testptr(tmpReg, tmpReg) ; // Locked ?
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3138 masm.jccb (Assembler::notZero, DONE_LABEL) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3139 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3140
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3141 // Appears unlocked - try to swing _owner from null to non-null.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3142 // Ideally, I'd manifest "Self" with get_thread and then attempt
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3143 // to CAS the register containing Self into m->Owner.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3144 // But we don't have enough registers, so instead we can either try to CAS
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3145 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3146 // we later store "Self" into m->Owner. Transiently storing a stack address
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3147 // (rsp or the address of the box) into m->owner is harmless.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3148 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3149 if (os::is_MP()) { masm.lock(); }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3150 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3151 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3152 masm.jccb (Assembler::notZero, DONE_LABEL) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3153 masm.get_thread (scrReg) ; // beware: clobbers ICCs
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3154 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3155 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3156
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3157 // If the CAS fails we can either retry or pass control to the slow-path.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3158 // We use the latter tactic.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3159 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3160 // If the CAS was successful ...
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3161 // Self has acquired the lock
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3162 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3163 // Intentional fall-through into DONE_LABEL ...
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3164 } else {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3165 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3166 masm.movptr(boxReg, tmpReg) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3167
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3168 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3169 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3170 // prefetchw [eax + Offset(_owner)-2]
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3171 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3172 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3173
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3174 if ((EmitSync & 64) == 0) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3175 // Optimistic form
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3176 masm.xorptr (tmpReg, tmpReg) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3177 } else {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3178 // Can suffer RTS->RTO upgrades on shared or cold $ lines
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3179 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3180 masm.testptr(tmpReg, tmpReg) ; // Locked ?
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3181 masm.jccb (Assembler::notZero, DONE_LABEL) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3182 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3183
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3184 // Appears unlocked - try to swing _owner from null to non-null.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3185 // Use either "Self" (in scr) or rsp as thread identity in _owner.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3186 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3187 masm.get_thread (scrReg) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3188 if (os::is_MP()) { masm.lock(); }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3189 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3190
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3191 // If the CAS fails we can either retry or pass control to the slow-path.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3192 // We use the latter tactic.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3193 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3194 // If the CAS was successful ...
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3195 // Self has acquired the lock
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3196 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3197 // Intentional fall-through into DONE_LABEL ...
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3198 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3199
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3200 // DONE_LABEL is a hot target - we'd really like to place it at the
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3201 // start of cache line by padding with NOPs.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3202 // See the AMD and Intel software optimization manuals for the
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3203 // most efficient "long" NOP encodings.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3204 // Unfortunately none of our alignment mechanisms suffice.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3205 masm.bind(DONE_LABEL);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3206
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3207 // Avoid branch-to-branch on AMD processors
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3208 // This appears to be superstition.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3209 if (EmitSync & 32) masm.nop() ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3210
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3211
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3212 // At DONE_LABEL the icc ZFlag is set as follows ...
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3213 // Fast_Unlock uses the same protocol.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3214 // ZFlag == 1 -> Success
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3215 // ZFlag == 0 -> Failure - force control through the slow-path
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3216 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3217 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3218
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3219 // obj: object to unlock
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3220 // box: box address (displaced header location), killed. Must be EAX.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3221 // rbx,: killed tmp; cannot be obj nor box.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3222 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3223 // Some commentary on balanced locking:
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3224 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3225 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3226 // Methods that don't have provably balanced locking are forced to run in the
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3227 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3228 // The interpreter provides two properties:
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3229 // I1: At return-time the interpreter automatically and quietly unlocks any
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3230 // objects acquired the current activation (frame). Recall that the
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3231 // interpreter maintains an on-stack list of locks currently held by
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3232 // a frame.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3233 // I2: If a method attempts to unlock an object that is not held by the
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3234 // the frame the interpreter throws IMSX.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3235 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3236 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3237 // B() doesn't have provably balanced locking so it runs in the interpreter.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3238 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3239 // is still locked by A().
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3240 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3241 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3242 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3243 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3244 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3245
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3246 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3247
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3248 Register objReg = as_Register($obj$$reg);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3249 Register boxReg = as_Register($box$$reg);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3250 Register tmpReg = as_Register($tmp$$reg);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3251
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3252 guarantee (objReg != boxReg, "") ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3253 guarantee (objReg != tmpReg, "") ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3254 guarantee (boxReg != tmpReg, "") ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3255 guarantee (boxReg == as_Register(EAX_enc), "") ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3256 MacroAssembler masm(&cbuf);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3257
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3258 if (EmitSync & 4) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3259 // Disable - inhibit all inlining. Force control through the slow-path
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3260 masm.cmpptr (rsp, 0) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3261 } else
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3262 if (EmitSync & 8) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3263 Label DONE_LABEL ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3264 if (UseBiasedLocking) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3265 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3266 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3267 // classic stack-locking code ...
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3268 masm.movptr(tmpReg, Address(boxReg, 0)) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3269 masm.testptr(tmpReg, tmpReg) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3270 masm.jcc (Assembler::zero, DONE_LABEL) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3271 if (os::is_MP()) { masm.lock(); }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3272 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3273 masm.bind(DONE_LABEL);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3274 } else {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3275 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3276
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3277 // Critically, the biased locking test must have precedence over
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3278 // and appear before the (box->dhw == 0) recursive stack-lock test.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3279 if (UseBiasedLocking && !UseOptoBiasInlining) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3280 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3281 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3282
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3283 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3284 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3285 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3286
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3287 masm.testptr(tmpReg, 0x02) ; // Inflated?
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3288 masm.jccb (Assembler::zero, Stacked) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3289
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3290 masm.bind (Inflated) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3291 // It's inflated.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3292 // Despite our balanced locking property we still check that m->_owner == Self
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3293 // as java routines or native JNI code called by this thread might
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3294 // have released the lock.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3295 // Refer to the comments in synchronizer.cpp for how we might encode extra
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3296 // state in _succ so we can avoid fetching EntryList\|cxq.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3297 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3298 // I'd like to add more cases in fast_lock() and fast_unlock() --
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3299 // such as recursive enter and exit -- but we have to be wary of
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3300 // I$ bloat, T$ effects and BP$ effects.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3301 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3302 // If there's no contention try a 1-0 exit. That is, exit without
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3303 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3304 // we detect and recover from the race that the 1-0 exit admits.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3305 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3306 // Conceptually Fast_Unlock() must execute a STST\|LDST "release" barrier
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3307 // before it STs null into _owner, releasing the lock. Updates
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3308 // to data protected by the critical section must be visible before
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3309 // we drop the lock (and thus before any other thread could acquire
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3310 // the lock and observe the fields protected by the lock).
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3311 // IA32's memory-model is SPO, so STs are ordered with respect to
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3312 // each other and there's no need for an explicit barrier (fence).
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3313 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3314
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3315 masm.get_thread (boxReg) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3316 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3317 // prefetchw [ebx + Offset(_owner)-2]
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3318 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3319 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3320
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3321 // Note that we could employ various encoding schemes to reduce
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3322 // the number of loads below (currently 4) to just 2 or 3.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3323 // Refer to the comments in synchronizer.cpp.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3324 // In practice the chain of fetches doesn't seem to impact performance, however.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3325 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3326 // Attempt to reduce branch density - AMD's branch predictor.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3327 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3328 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3329 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3330 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3331 masm.jccb (Assembler::notZero, DONE_LABEL) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3332 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3333 masm.jmpb (DONE_LABEL) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3334 } else {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3335 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3336 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3337 masm.jccb (Assembler::notZero, DONE_LABEL) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3338 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3339 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3340 masm.jccb (Assembler::notZero, CheckSucc) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3341 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3342 masm.jmpb (DONE_LABEL) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3343 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3344
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3345 // The Following code fragment (EmitSync & 65536) improves the performance of
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3346 // contended applications and contended synchronization microbenchmarks.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3347 // Unfortunately the emission of the code - even though not executed - causes regressions
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3348 // in scimark and jetstream, evidently because of $ effects. Replacing the code
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3349 // with an equal number of never-executed NOPs results in the same regression.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3350 // We leave it off by default.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3351
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3352 if ((EmitSync & 65536) != 0) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3353 Label LSuccess, LGoSlowPath ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3354
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3355 masm.bind (CheckSucc) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3356
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3357 // Optional pre-test ... it's safe to elide this
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3358 if ((EmitSync & 16) == 0) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3359 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3360 masm.jccb (Assembler::zero, LGoSlowPath) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3361 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3362
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3363 // We have a classic Dekker-style idiom:
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3364 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3365 // There are a number of ways to implement the barrier:
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3366 // (1) lock:andl &m->_owner, 0
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3367 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3368 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3369 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3370 // (2) If supported, an explicit MFENCE is appealing.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3371 // In older IA32 processors MFENCE is slower than lock:add or xchg
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3372 // particularly if the write-buffer is full as might be the case if
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3373 // if stores closely precede the fence or fence-equivalent instruction.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3374 // In more modern implementations MFENCE appears faster, however.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3375 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3376 // The $lines underlying the top-of-stack should be in M-state.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3377 // The locked add instruction is serializing, of course.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3378 // (4) Use xchg, which is serializing
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3379 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3380 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3381 // The integer condition codes will tell us if succ was 0.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3382 // Since _succ and _owner should reside in the same $line and
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3383 // we just stored into _owner, it's likely that the $line
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3384 // remains in M-state for the lock:orl.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3385 //
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3386 // We currently use (3), although it's likely that switching to (2)
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3387 // is correct for the future.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3388
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3389 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3390 if (os::is_MP()) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3391 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3392 masm.mfence();
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3393 } else {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3394 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3395 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3396 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3397 // Ratify _succ remains non-null
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3398 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3399 masm.jccb (Assembler::notZero, LSuccess) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3400
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3401 masm.xorptr(boxReg, boxReg) ; // box is really EAX
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3402 if (os::is_MP()) { masm.lock(); }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3403 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3404 masm.jccb (Assembler::notEqual, LSuccess) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3405 // Since we're low on registers we installed rsp as a placeholding in _owner.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3406 // Now install Self over rsp. This is safe as we're transitioning from
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3407 // non-null to non=null
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3408 masm.get_thread (boxReg) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3409 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3410 // Intentional fall-through into LGoSlowPath ...
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3411
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3412 masm.bind (LGoSlowPath) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3413 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3414 masm.jmpb (DONE_LABEL) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3415
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3416 masm.bind (LSuccess) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3417 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3418 masm.jmpb (DONE_LABEL) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3419 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3420
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3421 masm.bind (Stacked) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3422 // It's not inflated and it's not recursively stack-locked and it's not biased.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3423 // It must be stack-locked.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3424 // Try to reset the header to displaced header.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3425 // The "box" value on the stack is stable, so we can reload
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3426 // and be assured we observe the same value as above.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3427 masm.movptr(tmpReg, Address(boxReg, 0)) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3428 if (os::is_MP()) { masm.lock(); }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3429 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3430 // Intention fall-thru into DONE_LABEL
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3431
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3432
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3433 // DONE_LABEL is a hot target - we'd really like to place it at the
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3434 // start of cache line by padding with NOPs.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3435 // See the AMD and Intel software optimization manuals for the
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3436 // most efficient "long" NOP encodings.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3437 // Unfortunately none of our alignment mechanisms suffice.
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3438 if ((EmitSync & 65536) == 0) {
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3439 masm.bind (CheckSucc) ;
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3440 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3441 masm.bind(DONE_LABEL);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3442
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3443 // Avoid branch to branch on AMD processors
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3444 if (EmitSync & 32768) { masm.nop() ; }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3445 }
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3446 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3447
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3448
0 a61af66fc99e Initial load duke parents: diff changeset	3449 enc_class enc_pop_rdx() %{
a61af66fc99e Initial load duke parents: diff changeset	3450 emit_opcode(cbuf,0x5A);
a61af66fc99e Initial load duke parents: diff changeset	3451 %}
a61af66fc99e Initial load duke parents: diff changeset	3452
a61af66fc99e Initial load duke parents: diff changeset	3453 enc_class enc_rethrow() %{
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	3454 cbuf.set_insts_mark();
0 a61af66fc99e Initial load duke parents: diff changeset	3455 emit_opcode(cbuf, 0xE9); // jmp entry
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	3456 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
0 a61af66fc99e Initial load duke parents: diff changeset	3457 runtime_call_Relocation::spec(), RELOC_IMM32 );
a61af66fc99e Initial load duke parents: diff changeset	3458 %}
a61af66fc99e Initial load duke parents: diff changeset	3459
a61af66fc99e Initial load duke parents: diff changeset	3460
a61af66fc99e Initial load duke parents: diff changeset	3461 // Convert a double to an int. Java semantics require we do complex
a61af66fc99e Initial load duke parents: diff changeset	3462 // manglelations in the corner cases. So we set the rounding mode to
a61af66fc99e Initial load duke parents: diff changeset	3463 // 'zero', store the darned double down as an int, and reset the
a61af66fc99e Initial load duke parents: diff changeset	3464 // rounding mode to 'nearest'. The hardware throws an exception which
a61af66fc99e Initial load duke parents: diff changeset	3465 // patches up the correct value directly to the stack.
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	3466 enc_class DPR2I_encoding( regDPR src ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	3467 // Flip to round-to-zero mode. We attempted to allow invalid-op
a61af66fc99e Initial load duke parents: diff changeset	3468 // exceptions here, so that a NAN or other corner-case value will
a61af66fc99e Initial load duke parents: diff changeset	3469 // thrown an exception (but normal values get converted at full speed).
a61af66fc99e Initial load duke parents: diff changeset	3470 // However, I2C adapters and other float-stack manglers leave pending
a61af66fc99e Initial load duke parents: diff changeset	3471 // invalid-op exceptions hanging. We would have to clear them before
a61af66fc99e Initial load duke parents: diff changeset	3472 // enabling them and that is more expensive than just testing for the
a61af66fc99e Initial load duke parents: diff changeset	3473 // invalid value Intel stores down in the corner cases.
a61af66fc99e Initial load duke parents: diff changeset	3474 emit_opcode(cbuf,0xD9); // FLDCW trunc
a61af66fc99e Initial load duke parents: diff changeset	3475 emit_opcode(cbuf,0x2D);
a61af66fc99e Initial load duke parents: diff changeset	3476 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
a61af66fc99e Initial load duke parents: diff changeset	3477 // Allocate a word
a61af66fc99e Initial load duke parents: diff changeset	3478 emit_opcode(cbuf,0x83); // SUB ESP,4
a61af66fc99e Initial load duke parents: diff changeset	3479 emit_opcode(cbuf,0xEC);
a61af66fc99e Initial load duke parents: diff changeset	3480 emit_d8(cbuf,0x04);
a61af66fc99e Initial load duke parents: diff changeset	3481 // Encoding assumes a double has been pushed into FPR0.
a61af66fc99e Initial load duke parents: diff changeset	3482 // Store down the double as an int, popping the FPU stack
a61af66fc99e Initial load duke parents: diff changeset	3483 emit_opcode(cbuf,0xDB); // FISTP [ESP]
a61af66fc99e Initial load duke parents: diff changeset	3484 emit_opcode(cbuf,0x1C);
a61af66fc99e Initial load duke parents: diff changeset	3485 emit_d8(cbuf,0x24);
a61af66fc99e Initial load duke parents: diff changeset	3486 // Restore the rounding mode; mask the exception
a61af66fc99e Initial load duke parents: diff changeset	3487 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
a61af66fc99e Initial load duke parents: diff changeset	3488 emit_opcode(cbuf,0x2D);
a61af66fc99e Initial load duke parents: diff changeset	3489 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
a61af66fc99e Initial load duke parents: diff changeset	3490 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
a61af66fc99e Initial load duke parents: diff changeset	3491 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
a61af66fc99e Initial load duke parents: diff changeset	3492
a61af66fc99e Initial load duke parents: diff changeset	3493 // Load the converted int; adjust CPU stack
a61af66fc99e Initial load duke parents: diff changeset	3494 emit_opcode(cbuf,0x58); // POP EAX
a61af66fc99e Initial load duke parents: diff changeset	3495 emit_opcode(cbuf,0x3D); // CMP EAX,imm
a61af66fc99e Initial load duke parents: diff changeset	3496 emit_d32 (cbuf,0x80000000); // 0x80000000
a61af66fc99e Initial load duke parents: diff changeset	3497 emit_opcode(cbuf,0x75); // JNE around_slow_call
a61af66fc99e Initial load duke parents: diff changeset	3498 emit_d8 (cbuf,0x07); // Size of slow_call
a61af66fc99e Initial load duke parents: diff changeset	3499 // Push src onto stack slow-path
a61af66fc99e Initial load duke parents: diff changeset	3500 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
a61af66fc99e Initial load duke parents: diff changeset	3501 emit_d8 (cbuf,0xC0-1+$src$$reg );
a61af66fc99e Initial load duke parents: diff changeset	3502 // CALL directly to the runtime
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	3503 cbuf.set_insts_mark();
0 a61af66fc99e Initial load duke parents: diff changeset	3504 emit_opcode(cbuf,0xE8); // Call into runtime
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	3505 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
0 a61af66fc99e Initial load duke parents: diff changeset	3506 // Carry on here...
a61af66fc99e Initial load duke parents: diff changeset	3507 %}
a61af66fc99e Initial load duke parents: diff changeset	3508
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	3509 enc_class DPR2L_encoding( regDPR src ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	3510 emit_opcode(cbuf,0xD9); // FLDCW trunc
a61af66fc99e Initial load duke parents: diff changeset	3511 emit_opcode(cbuf,0x2D);
a61af66fc99e Initial load duke parents: diff changeset	3512 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
a61af66fc99e Initial load duke parents: diff changeset	3513 // Allocate a word
a61af66fc99e Initial load duke parents: diff changeset	3514 emit_opcode(cbuf,0x83); // SUB ESP,8
a61af66fc99e Initial load duke parents: diff changeset	3515 emit_opcode(cbuf,0xEC);
a61af66fc99e Initial load duke parents: diff changeset	3516 emit_d8(cbuf,0x08);
a61af66fc99e Initial load duke parents: diff changeset	3517 // Encoding assumes a double has been pushed into FPR0.
a61af66fc99e Initial load duke parents: diff changeset	3518 // Store down the double as a long, popping the FPU stack
a61af66fc99e Initial load duke parents: diff changeset	3519 emit_opcode(cbuf,0xDF); // FISTP [ESP]
a61af66fc99e Initial load duke parents: diff changeset	3520 emit_opcode(cbuf,0x3C);
a61af66fc99e Initial load duke parents: diff changeset	3521 emit_d8(cbuf,0x24);
a61af66fc99e Initial load duke parents: diff changeset	3522 // Restore the rounding mode; mask the exception
a61af66fc99e Initial load duke parents: diff changeset	3523 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
a61af66fc99e Initial load duke parents: diff changeset	3524 emit_opcode(cbuf,0x2D);
a61af66fc99e Initial load duke parents: diff changeset	3525 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
a61af66fc99e Initial load duke parents: diff changeset	3526 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
a61af66fc99e Initial load duke parents: diff changeset	3527 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
a61af66fc99e Initial load duke parents: diff changeset	3528
a61af66fc99e Initial load duke parents: diff changeset	3529 // Load the converted int; adjust CPU stack
a61af66fc99e Initial load duke parents: diff changeset	3530 emit_opcode(cbuf,0x58); // POP EAX
a61af66fc99e Initial load duke parents: diff changeset	3531 emit_opcode(cbuf,0x5A); // POP EDX
a61af66fc99e Initial load duke parents: diff changeset	3532 emit_opcode(cbuf,0x81); // CMP EDX,imm
a61af66fc99e Initial load duke parents: diff changeset	3533 emit_d8 (cbuf,0xFA); // rdx
a61af66fc99e Initial load duke parents: diff changeset	3534 emit_d32 (cbuf,0x80000000); // 0x80000000
a61af66fc99e Initial load duke parents: diff changeset	3535 emit_opcode(cbuf,0x75); // JNE around_slow_call
a61af66fc99e Initial load duke parents: diff changeset	3536 emit_d8 (cbuf,0x07+4); // Size of slow_call
a61af66fc99e Initial load duke parents: diff changeset	3537 emit_opcode(cbuf,0x85); // TEST EAX,EAX
a61af66fc99e Initial load duke parents: diff changeset	3538 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
a61af66fc99e Initial load duke parents: diff changeset	3539 emit_opcode(cbuf,0x75); // JNE around_slow_call
a61af66fc99e Initial load duke parents: diff changeset	3540 emit_d8 (cbuf,0x07); // Size of slow_call
a61af66fc99e Initial load duke parents: diff changeset	3541 // Push src onto stack slow-path
a61af66fc99e Initial load duke parents: diff changeset	3542 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
a61af66fc99e Initial load duke parents: diff changeset	3543 emit_d8 (cbuf,0xC0-1+$src$$reg );
a61af66fc99e Initial load duke parents: diff changeset	3544 // CALL directly to the runtime
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	3545 cbuf.set_insts_mark();
0 a61af66fc99e Initial load duke parents: diff changeset	3546 emit_opcode(cbuf,0xE8); // Call into runtime
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	3547 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
0 a61af66fc99e Initial load duke parents: diff changeset	3548 // Carry on here...
a61af66fc99e Initial load duke parents: diff changeset	3549 %}
a61af66fc99e Initial load duke parents: diff changeset	3550
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	3551 enc_class FMul_ST_reg( eRegFPR src1 ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	3552 // Operand was loaded from memory into fp ST (stack top)
a61af66fc99e Initial load duke parents: diff changeset	3553 // FMUL ST,$src /* D8 C8+i */
a61af66fc99e Initial load duke parents: diff changeset	3554 emit_opcode(cbuf, 0xD8);
a61af66fc99e Initial load duke parents: diff changeset	3555 emit_opcode(cbuf, 0xC8 + $src1$$reg);
a61af66fc99e Initial load duke parents: diff changeset	3556 %}
a61af66fc99e Initial load duke parents: diff changeset	3557
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	3558 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	3559 // FADDP ST,src2 /* D8 C0+i */
a61af66fc99e Initial load duke parents: diff changeset	3560 emit_opcode(cbuf, 0xD8);
a61af66fc99e Initial load duke parents: diff changeset	3561 emit_opcode(cbuf, 0xC0 + $src2$$reg);
a61af66fc99e Initial load duke parents: diff changeset	3562 //could use FADDP src2,fpST /* DE C0+i */
a61af66fc99e Initial load duke parents: diff changeset	3563 %}
a61af66fc99e Initial load duke parents: diff changeset	3564
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	3565 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	3566 // FADDP src2,ST /* DE C0+i */
a61af66fc99e Initial load duke parents: diff changeset	3567 emit_opcode(cbuf, 0xDE);
a61af66fc99e Initial load duke parents: diff changeset	3568 emit_opcode(cbuf, 0xC0 + $src2$$reg);
a61af66fc99e Initial load duke parents: diff changeset	3569 %}
a61af66fc99e Initial load duke parents: diff changeset	3570
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	3571 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	3572 // Operand has been loaded into fp ST (stack top)
a61af66fc99e Initial load duke parents: diff changeset	3573 // FSUB ST,$src1
a61af66fc99e Initial load duke parents: diff changeset	3574 emit_opcode(cbuf, 0xD8);
a61af66fc99e Initial load duke parents: diff changeset	3575 emit_opcode(cbuf, 0xE0 + $src1$$reg);
a61af66fc99e Initial load duke parents: diff changeset	3576
a61af66fc99e Initial load duke parents: diff changeset	3577 // FDIV
a61af66fc99e Initial load duke parents: diff changeset	3578 emit_opcode(cbuf, 0xD8);
a61af66fc99e Initial load duke parents: diff changeset	3579 emit_opcode(cbuf, 0xF0 + $src2$$reg);
a61af66fc99e Initial load duke parents: diff changeset	3580 %}
a61af66fc99e Initial load duke parents: diff changeset	3581
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	3582 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	3583 // Operand was loaded from memory into fp ST (stack top)
a61af66fc99e Initial load duke parents: diff changeset	3584 // FADD ST,$src /* D8 C0+i */
a61af66fc99e Initial load duke parents: diff changeset	3585 emit_opcode(cbuf, 0xD8);
a61af66fc99e Initial load duke parents: diff changeset	3586 emit_opcode(cbuf, 0xC0 + $src1$$reg);
a61af66fc99e Initial load duke parents: diff changeset	3587
a61af66fc99e Initial load duke parents: diff changeset	3588 // FMUL ST,src2 /* D8 C+i /
a61af66fc99e Initial load duke parents: diff changeset	3589 emit_opcode(cbuf, 0xD8);
a61af66fc99e Initial load duke parents: diff changeset	3590 emit_opcode(cbuf, 0xC8 + $src2$$reg);
a61af66fc99e Initial load duke parents: diff changeset	3591 %}
a61af66fc99e Initial load duke parents: diff changeset	3592
a61af66fc99e Initial load duke parents: diff changeset	3593
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	3594 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	3595 // Operand was loaded from memory into fp ST (stack top)
a61af66fc99e Initial load duke parents: diff changeset	3596 // FADD ST,$src /* D8 C0+i */
a61af66fc99e Initial load duke parents: diff changeset	3597 emit_opcode(cbuf, 0xD8);
a61af66fc99e Initial load duke parents: diff changeset	3598 emit_opcode(cbuf, 0xC0 + $src1$$reg);
a61af66fc99e Initial load duke parents: diff changeset	3599
a61af66fc99e Initial load duke parents: diff changeset	3600 // FMULP src2,ST /* DE C8+i */
a61af66fc99e Initial load duke parents: diff changeset	3601 emit_opcode(cbuf, 0xDE);
a61af66fc99e Initial load duke parents: diff changeset	3602 emit_opcode(cbuf, 0xC8 + $src2$$reg);
a61af66fc99e Initial load duke parents: diff changeset	3603 %}
a61af66fc99e Initial load duke parents: diff changeset	3604
a61af66fc99e Initial load duke parents: diff changeset	3605 // Atomically load the volatile long
a61af66fc99e Initial load duke parents: diff changeset	3606 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
a61af66fc99e Initial load duke parents: diff changeset	3607 emit_opcode(cbuf,0xDF);
a61af66fc99e Initial load duke parents: diff changeset	3608 int rm_byte_opcode = 0x05;
a61af66fc99e Initial load duke parents: diff changeset	3609 int base = $mem$$base;
a61af66fc99e Initial load duke parents: diff changeset	3610 int index = $mem$$index;
a61af66fc99e Initial load duke parents: diff changeset	3611 int scale = $mem$$scale;
a61af66fc99e Initial load duke parents: diff changeset	3612 int displace = $mem$$disp;
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	3613 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	3614 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
0 a61af66fc99e Initial load duke parents: diff changeset	3615 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
a61af66fc99e Initial load duke parents: diff changeset	3616 %}
a61af66fc99e Initial load duke parents: diff changeset	3617
a61af66fc99e Initial load duke parents: diff changeset	3618 // Volatile Store Long. Must be atomic, so move it into
a61af66fc99e Initial load duke parents: diff changeset	3619 // the FP TOS and then do a 64-bit FIST. Has to probe the
a61af66fc99e Initial load duke parents: diff changeset	3620 // target address before the store (for null-ptr checks)
a61af66fc99e Initial load duke parents: diff changeset	3621 // so the memory operand is used twice in the encoding.
a61af66fc99e Initial load duke parents: diff changeset	3622 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
a61af66fc99e Initial load duke parents: diff changeset	3623 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	3624 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
0 a61af66fc99e Initial load duke parents: diff changeset	3625 emit_opcode(cbuf,0xDF);
a61af66fc99e Initial load duke parents: diff changeset	3626 int rm_byte_opcode = 0x07;
a61af66fc99e Initial load duke parents: diff changeset	3627 int base = $mem$$base;
a61af66fc99e Initial load duke parents: diff changeset	3628 int index = $mem$$index;
a61af66fc99e Initial load duke parents: diff changeset	3629 int scale = $mem$$scale;
a61af66fc99e Initial load duke parents: diff changeset	3630 int displace = $mem$$disp;
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	3631 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	3632 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
0 a61af66fc99e Initial load duke parents: diff changeset	3633 %}
a61af66fc99e Initial load duke parents: diff changeset	3634
a61af66fc99e Initial load duke parents: diff changeset	3635 // Safepoint Poll. This polls the safepoint page, and causes an
a61af66fc99e Initial load duke parents: diff changeset	3636 // exception if it is not readable. Unfortunately, it kills the condition code
a61af66fc99e Initial load duke parents: diff changeset	3637 // in the process
a61af66fc99e Initial load duke parents: diff changeset	3638 // We current use TESTL [spp],EDI
a61af66fc99e Initial load duke parents: diff changeset	3639 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
a61af66fc99e Initial load duke parents: diff changeset	3640
a61af66fc99e Initial load duke parents: diff changeset	3641 enc_class Safepoint_Poll() %{
1748 3e8fbc61cee8 6978355: renaming for 6961697 twisti parents: 1730 diff changeset	3642 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
0 a61af66fc99e Initial load duke parents: diff changeset	3643 emit_opcode(cbuf,0x85);
a61af66fc99e Initial load duke parents: diff changeset	3644 emit_rm (cbuf, 0x0, 0x7, 0x5);
a61af66fc99e Initial load duke parents: diff changeset	3645 emit_d32(cbuf, (intptr_t)os::get_polling_page());
a61af66fc99e Initial load duke parents: diff changeset	3646 %}
a61af66fc99e Initial load duke parents: diff changeset	3647 %}
a61af66fc99e Initial load duke parents: diff changeset	3648
a61af66fc99e Initial load duke parents: diff changeset	3649
a61af66fc99e Initial load duke parents: diff changeset	3650 //----------FRAME--------------------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	3651 // Definition of frame structure and management information.
a61af66fc99e Initial load duke parents: diff changeset	3652 //
a61af66fc99e Initial load duke parents: diff changeset	3653 // S T A C K L A Y O U T Allocators stack-slot number
a61af66fc99e Initial load duke parents: diff changeset	3654 // \| (to get allocators register number
a61af66fc99e Initial load duke parents: diff changeset	3655 // G Owned by \| \| v add OptoReg::stack0())
a61af66fc99e Initial load duke parents: diff changeset	3656 // r CALLER \| \|
a61af66fc99e Initial load duke parents: diff changeset	3657 // o \| +--------+ pad to even-align allocators stack-slot
a61af66fc99e Initial load duke parents: diff changeset	3658 // w V \| pad0 \| numbers; owned by CALLER
a61af66fc99e Initial load duke parents: diff changeset	3659 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
a61af66fc99e Initial load duke parents: diff changeset	3660 // h ^ \| in \| 5
a61af66fc99e Initial load duke parents: diff changeset	3661 // \| \| args \| 4 Holes in incoming args owned by SELF
a61af66fc99e Initial load duke parents: diff changeset	3662 // \| \| \| \| 3
a61af66fc99e Initial load duke parents: diff changeset	3663 // \| \| +--------+
a61af66fc99e Initial load duke parents: diff changeset	3664 // V \| \| old out\| Empty on Intel, window on Sparc
a61af66fc99e Initial load duke parents: diff changeset	3665 // \| old \|preserve\| Must be even aligned.
a61af66fc99e Initial load duke parents: diff changeset	3666 // \| SP-+--------+----> Matcher::_old_SP, even aligned
a61af66fc99e Initial load duke parents: diff changeset	3667 // \| \| in \| 3 area for Intel ret address
a61af66fc99e Initial load duke parents: diff changeset	3668 // Owned by \|preserve\| Empty on Sparc.
a61af66fc99e Initial load duke parents: diff changeset	3669 // SELF +--------+
a61af66fc99e Initial load duke parents: diff changeset	3670 // \| \| pad2 \| 2 pad to align old SP
a61af66fc99e Initial load duke parents: diff changeset	3671 // \| +--------+ 1
a61af66fc99e Initial load duke parents: diff changeset	3672 // \| \| locks \| 0
a61af66fc99e Initial load duke parents: diff changeset	3673 // \| +--------+----> OptoReg::stack0(), even aligned
a61af66fc99e Initial load duke parents: diff changeset	3674 // \| \| pad1 \| 11 pad to align new SP
a61af66fc99e Initial load duke parents: diff changeset	3675 // \| +--------+
a61af66fc99e Initial load duke parents: diff changeset	3676 // \| \| \| 10
a61af66fc99e Initial load duke parents: diff changeset	3677 // \| \| spills \| 9 spills
a61af66fc99e Initial load duke parents: diff changeset	3678 // V \| \| 8 (pad0 slot for callee)
a61af66fc99e Initial load duke parents: diff changeset	3679 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
a61af66fc99e Initial load duke parents: diff changeset	3680 // ^ \| out \| 7
a61af66fc99e Initial load duke parents: diff changeset	3681 // \| \| args \| 6 Holes in outgoing args owned by CALLEE
a61af66fc99e Initial load duke parents: diff changeset	3682 // Owned by +--------+
a61af66fc99e Initial load duke parents: diff changeset	3683 // CALLEE \| new out\| 6 Empty on Intel, window on Sparc
a61af66fc99e Initial load duke parents: diff changeset	3684 // \| new \|preserve\| Must be even-aligned.
a61af66fc99e Initial load duke parents: diff changeset	3685 // \| SP-+--------+----> Matcher::_new_SP, even aligned
a61af66fc99e Initial load duke parents: diff changeset	3686 // \| \| \|
a61af66fc99e Initial load duke parents: diff changeset	3687 //
a61af66fc99e Initial load duke parents: diff changeset	3688 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
a61af66fc99e Initial load duke parents: diff changeset	3689 // known from SELF's arguments and the Java calling convention.
a61af66fc99e Initial load duke parents: diff changeset	3690 // Region 6-7 is determined per call site.
a61af66fc99e Initial load duke parents: diff changeset	3691 // Note 2: If the calling convention leaves holes in the incoming argument
a61af66fc99e Initial load duke parents: diff changeset	3692 // area, those holes are owned by SELF. Holes in the outgoing area
a61af66fc99e Initial load duke parents: diff changeset	3693 // are owned by the CALLEE. Holes should not be nessecary in the
a61af66fc99e Initial load duke parents: diff changeset	3694 // incoming area, as the Java calling convention is completely under
a61af66fc99e Initial load duke parents: diff changeset	3695 // the control of the AD file. Doubles can be sorted and packed to
a61af66fc99e Initial load duke parents: diff changeset	3696 // avoid holes. Holes in the outgoing arguments may be nessecary for
a61af66fc99e Initial load duke parents: diff changeset	3697 // varargs C calling conventions.
a61af66fc99e Initial load duke parents: diff changeset	3698 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
a61af66fc99e Initial load duke parents: diff changeset	3699 // even aligned with pad0 as needed.
a61af66fc99e Initial load duke parents: diff changeset	3700 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
a61af66fc99e Initial load duke parents: diff changeset	3701 // region 6-11 is even aligned; it may be padded out more so that
a61af66fc99e Initial load duke parents: diff changeset	3702 // the region from SP to FP meets the minimum stack alignment.
a61af66fc99e Initial load duke parents: diff changeset	3703
a61af66fc99e Initial load duke parents: diff changeset	3704 frame %{
a61af66fc99e Initial load duke parents: diff changeset	3705 // What direction does stack grow in (assumed to be same for C & Java)
a61af66fc99e Initial load duke parents: diff changeset	3706 stack_direction(TOWARDS_LOW);
a61af66fc99e Initial load duke parents: diff changeset	3707
a61af66fc99e Initial load duke parents: diff changeset	3708 // These three registers define part of the calling convention
a61af66fc99e Initial load duke parents: diff changeset	3709 // between compiled code and the interpreter.
a61af66fc99e Initial load duke parents: diff changeset	3710 inline_cache_reg(EAX); // Inline Cache Register
a61af66fc99e Initial load duke parents: diff changeset	3711 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
a61af66fc99e Initial load duke parents: diff changeset	3712
a61af66fc99e Initial load duke parents: diff changeset	3713 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
a61af66fc99e Initial load duke parents: diff changeset	3714 cisc_spilling_operand_name(indOffset32);
a61af66fc99e Initial load duke parents: diff changeset	3715
a61af66fc99e Initial load duke parents: diff changeset	3716 // Number of stack slots consumed by locking an object
a61af66fc99e Initial load duke parents: diff changeset	3717 sync_stack_slots(1);
a61af66fc99e Initial load duke parents: diff changeset	3718
a61af66fc99e Initial load duke parents: diff changeset	3719 // Compiled code's Frame Pointer
a61af66fc99e Initial load duke parents: diff changeset	3720 frame_pointer(ESP);
a61af66fc99e Initial load duke parents: diff changeset	3721 // Interpreter stores its frame pointer in a register which is
a61af66fc99e Initial load duke parents: diff changeset	3722 // stored to the stack by I2CAdaptors.
a61af66fc99e Initial load duke parents: diff changeset	3723 // I2CAdaptors convert from interpreted java to compiled java.
a61af66fc99e Initial load duke parents: diff changeset	3724 interpreter_frame_pointer(EBP);
a61af66fc99e Initial load duke parents: diff changeset	3725
a61af66fc99e Initial load duke parents: diff changeset	3726 // Stack alignment requirement
a61af66fc99e Initial load duke parents: diff changeset	3727 // Alignment size in bytes (128-bit -> 16 bytes)
a61af66fc99e Initial load duke parents: diff changeset	3728 stack_alignment(StackAlignmentInBytes);
a61af66fc99e Initial load duke parents: diff changeset	3729
a61af66fc99e Initial load duke parents: diff changeset	3730 // Number of stack slots between incoming argument block and the start of
a61af66fc99e Initial load duke parents: diff changeset	3731 // a new frame. The PROLOG must add this many slots to the stack. The
a61af66fc99e Initial load duke parents: diff changeset	3732 // EPILOG must remove this many slots. Intel needs one slot for
a61af66fc99e Initial load duke parents: diff changeset	3733 // return address and one for rbp, (must save rbp)
a61af66fc99e Initial load duke parents: diff changeset	3734 in_preserve_stack_slots(2+VerifyStackAtCalls);
a61af66fc99e Initial load duke parents: diff changeset	3735
a61af66fc99e Initial load duke parents: diff changeset	3736 // Number of outgoing stack slots killed above the out_preserve_stack_slots
a61af66fc99e Initial load duke parents: diff changeset	3737 // for calls to C. Supports the var-args backing area for register parms.
a61af66fc99e Initial load duke parents: diff changeset	3738 varargs_C_out_slots_killed(0);
a61af66fc99e Initial load duke parents: diff changeset	3739
a61af66fc99e Initial load duke parents: diff changeset	3740 // The after-PROLOG location of the return address. Location of
a61af66fc99e Initial load duke parents: diff changeset	3741 // return address specifies a type (REG or STACK) and a number
a61af66fc99e Initial load duke parents: diff changeset	3742 // representing the register number (i.e. - use a register name) or
a61af66fc99e Initial load duke parents: diff changeset	3743 // stack slot.
a61af66fc99e Initial load duke parents: diff changeset	3744 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
a61af66fc99e Initial load duke parents: diff changeset	3745 // Otherwise, it is above the locks and verification slot and alignment word
a61af66fc99e Initial load duke parents: diff changeset	3746 return_addr(STACK - 1 +
4950 9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	3747 round_to((Compile::current()->in_preserve_stack_slots() +
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	3748 Compile::current()->fixed_slots()),
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	3749 stack_alignment_in_slots()));
0 a61af66fc99e Initial load duke parents: diff changeset	3750
a61af66fc99e Initial load duke parents: diff changeset	3751 // Body of function which returns an integer array locating
a61af66fc99e Initial load duke parents: diff changeset	3752 // arguments either in registers or in stack slots. Passed an array
a61af66fc99e Initial load duke parents: diff changeset	3753 // of ideal registers called "sig" and a "length" count. Stack-slot
a61af66fc99e Initial load duke parents: diff changeset	3754 // offsets are based on outgoing arguments, i.e. a CALLER setting up
a61af66fc99e Initial load duke parents: diff changeset	3755 // arguments for a CALLEE. Incoming stack arguments are
a61af66fc99e Initial load duke parents: diff changeset	3756 // automatically biased by the preserve_stack_slots field above.
a61af66fc99e Initial load duke parents: diff changeset	3757 calling_convention %{
a61af66fc99e Initial load duke parents: diff changeset	3758 // No difference between ingoing/outgoing just pass false
a61af66fc99e Initial load duke parents: diff changeset	3759 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
a61af66fc99e Initial load duke parents: diff changeset	3760 %}
a61af66fc99e Initial load duke parents: diff changeset	3761
a61af66fc99e Initial load duke parents: diff changeset	3762
a61af66fc99e Initial load duke parents: diff changeset	3763 // Body of function which returns an integer array locating
a61af66fc99e Initial load duke parents: diff changeset	3764 // arguments either in registers or in stack slots. Passed an array
a61af66fc99e Initial load duke parents: diff changeset	3765 // of ideal registers called "sig" and a "length" count. Stack-slot
a61af66fc99e Initial load duke parents: diff changeset	3766 // offsets are based on outgoing arguments, i.e. a CALLER setting up
a61af66fc99e Initial load duke parents: diff changeset	3767 // arguments for a CALLEE. Incoming stack arguments are
a61af66fc99e Initial load duke parents: diff changeset	3768 // automatically biased by the preserve_stack_slots field above.
a61af66fc99e Initial load duke parents: diff changeset	3769 c_calling_convention %{
a61af66fc99e Initial load duke parents: diff changeset	3770 // This is obviously always outgoing
14909 4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	3771 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
0 a61af66fc99e Initial load duke parents: diff changeset	3772 %}
a61af66fc99e Initial load duke parents: diff changeset	3773
a61af66fc99e Initial load duke parents: diff changeset	3774 // Location of C & interpreter return values
a61af66fc99e Initial load duke parents: diff changeset	3775 c_return_value %{
a61af66fc99e Initial load duke parents: diff changeset	3776 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
113 ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes coleenp parents: 71 diff changeset	3777 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes coleenp parents: 71 diff changeset	3778 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
0 a61af66fc99e Initial load duke parents: diff changeset	3779
a61af66fc99e Initial load duke parents: diff changeset	3780 // in SSE2+ mode we want to keep the FPU stack clean so pretend
a61af66fc99e Initial load duke parents: diff changeset	3781 // that C functions return float and double results in XMM0.
a61af66fc99e Initial load duke parents: diff changeset	3782 if( ideal_reg == Op_RegD && UseSSE>=2 )
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	3783 return OptoRegPair(XMM0b_num,XMM0_num);
0 a61af66fc99e Initial load duke parents: diff changeset	3784 if( ideal_reg == Op_RegF && UseSSE>=2 )
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	3785 return OptoRegPair(OptoReg::Bad,XMM0_num);
0 a61af66fc99e Initial load duke parents: diff changeset	3786
a61af66fc99e Initial load duke parents: diff changeset	3787 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
a61af66fc99e Initial load duke parents: diff changeset	3788 %}
a61af66fc99e Initial load duke parents: diff changeset	3789
a61af66fc99e Initial load duke parents: diff changeset	3790 // Location of return values
a61af66fc99e Initial load duke parents: diff changeset	3791 return_value %{
a61af66fc99e Initial load duke parents: diff changeset	3792 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
113 ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes coleenp parents: 71 diff changeset	3793 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes coleenp parents: 71 diff changeset	3794 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
0 a61af66fc99e Initial load duke parents: diff changeset	3795 if( ideal_reg == Op_RegD && UseSSE>=2 )
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	3796 return OptoRegPair(XMM0b_num,XMM0_num);
0 a61af66fc99e Initial load duke parents: diff changeset	3797 if( ideal_reg == Op_RegF && UseSSE>=1 )
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	3798 return OptoRegPair(OptoReg::Bad,XMM0_num);
0 a61af66fc99e Initial load duke parents: diff changeset	3799 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
a61af66fc99e Initial load duke parents: diff changeset	3800 %}
a61af66fc99e Initial load duke parents: diff changeset	3801
a61af66fc99e Initial load duke parents: diff changeset	3802 %}
a61af66fc99e Initial load duke parents: diff changeset	3803
a61af66fc99e Initial load duke parents: diff changeset	3804 //----------ATTRIBUTES---------------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	3805 //----------Operand Attributes-------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	3806 op_attrib op_cost(0); // Required cost attribute
a61af66fc99e Initial load duke parents: diff changeset	3807
a61af66fc99e Initial load duke parents: diff changeset	3808 //----------Instruction Attributes---------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	3809 ins_attrib ins_cost(100); // Required cost attribute
a61af66fc99e Initial load duke parents: diff changeset	3810 ins_attrib ins_size(8); // Required size attribute (in bits)
a61af66fc99e Initial load duke parents: diff changeset	3811 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
a61af66fc99e Initial load duke parents: diff changeset	3812 // non-matching short branch variant of some
a61af66fc99e Initial load duke parents: diff changeset	3813 // long branch?
a61af66fc99e Initial load duke parents: diff changeset	3814 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
a61af66fc99e Initial load duke parents: diff changeset	3815 // specifies the alignment that some part of the instruction (not
a61af66fc99e Initial load duke parents: diff changeset	3816 // necessarily the start) requires. If > 1, a compute_padding()
a61af66fc99e Initial load duke parents: diff changeset	3817 // function must be provided for the instruction
a61af66fc99e Initial load duke parents: diff changeset	3818
a61af66fc99e Initial load duke parents: diff changeset	3819 //----------OPERANDS-----------------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	3820 // Operand definitions must precede instruction definitions for correct parsing
a61af66fc99e Initial load duke parents: diff changeset	3821 // in the ADLC because operands constitute user defined types which are used in
a61af66fc99e Initial load duke parents: diff changeset	3822 // instruction definitions.
a61af66fc99e Initial load duke parents: diff changeset	3823
a61af66fc99e Initial load duke parents: diff changeset	3824 //----------Simple Operands----------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	3825 // Immediate Operands
a61af66fc99e Initial load duke parents: diff changeset	3826 // Integer Immediate
a61af66fc99e Initial load duke parents: diff changeset	3827 operand immI() %{
a61af66fc99e Initial load duke parents: diff changeset	3828 match(ConI);
a61af66fc99e Initial load duke parents: diff changeset	3829
a61af66fc99e Initial load duke parents: diff changeset	3830 op_cost(10);
a61af66fc99e Initial load duke parents: diff changeset	3831 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	3832 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	3833 %}
a61af66fc99e Initial load duke parents: diff changeset	3834
a61af66fc99e Initial load duke parents: diff changeset	3835 // Constant for test vs zero
a61af66fc99e Initial load duke parents: diff changeset	3836 operand immI0() %{
a61af66fc99e Initial load duke parents: diff changeset	3837 predicate(n->get_int() == 0);
a61af66fc99e Initial load duke parents: diff changeset	3838 match(ConI);
a61af66fc99e Initial load duke parents: diff changeset	3839
a61af66fc99e Initial load duke parents: diff changeset	3840 op_cost(0);
a61af66fc99e Initial load duke parents: diff changeset	3841 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	3842 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	3843 %}
a61af66fc99e Initial load duke parents: diff changeset	3844
a61af66fc99e Initial load duke parents: diff changeset	3845 // Constant for increment
a61af66fc99e Initial load duke parents: diff changeset	3846 operand immI1() %{
a61af66fc99e Initial load duke parents: diff changeset	3847 predicate(n->get_int() == 1);
a61af66fc99e Initial load duke parents: diff changeset	3848 match(ConI);
a61af66fc99e Initial load duke parents: diff changeset	3849
a61af66fc99e Initial load duke parents: diff changeset	3850 op_cost(0);
a61af66fc99e Initial load duke parents: diff changeset	3851 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	3852 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	3853 %}
a61af66fc99e Initial load duke parents: diff changeset	3854
a61af66fc99e Initial load duke parents: diff changeset	3855 // Constant for decrement
a61af66fc99e Initial load duke parents: diff changeset	3856 operand immI_M1() %{
a61af66fc99e Initial load duke parents: diff changeset	3857 predicate(n->get_int() == -1);
a61af66fc99e Initial load duke parents: diff changeset	3858 match(ConI);
a61af66fc99e Initial load duke parents: diff changeset	3859
a61af66fc99e Initial load duke parents: diff changeset	3860 op_cost(0);
a61af66fc99e Initial load duke parents: diff changeset	3861 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	3862 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	3863 %}
a61af66fc99e Initial load duke parents: diff changeset	3864
a61af66fc99e Initial load duke parents: diff changeset	3865 // Valid scale values for addressing modes
a61af66fc99e Initial load duke parents: diff changeset	3866 operand immI2() %{
a61af66fc99e Initial load duke parents: diff changeset	3867 predicate(0 <= n->get_int() && (n->get_int() <= 3));
a61af66fc99e Initial load duke parents: diff changeset	3868 match(ConI);
a61af66fc99e Initial load duke parents: diff changeset	3869
a61af66fc99e Initial load duke parents: diff changeset	3870 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	3871 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	3872 %}
a61af66fc99e Initial load duke parents: diff changeset	3873
a61af66fc99e Initial load duke parents: diff changeset	3874 operand immI8() %{
a61af66fc99e Initial load duke parents: diff changeset	3875 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
a61af66fc99e Initial load duke parents: diff changeset	3876 match(ConI);
a61af66fc99e Initial load duke parents: diff changeset	3877
a61af66fc99e Initial load duke parents: diff changeset	3878 op_cost(5);
a61af66fc99e Initial load duke parents: diff changeset	3879 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	3880 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	3881 %}
a61af66fc99e Initial load duke parents: diff changeset	3882
a61af66fc99e Initial load duke parents: diff changeset	3883 operand immI16() %{
a61af66fc99e Initial load duke parents: diff changeset	3884 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
a61af66fc99e Initial load duke parents: diff changeset	3885 match(ConI);
a61af66fc99e Initial load duke parents: diff changeset	3886
a61af66fc99e Initial load duke parents: diff changeset	3887 op_cost(10);
a61af66fc99e Initial load duke parents: diff changeset	3888 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	3889 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	3890 %}
a61af66fc99e Initial load duke parents: diff changeset	3891
17524 89152779163c Merge with jdk8-b132 Gilles Duboscq <duboscq@ssw.jku.at> parents: 14909 diff changeset	3892 // Int Immediate non-negative
89152779163c Merge with jdk8-b132 Gilles Duboscq <duboscq@ssw.jku.at> parents: 14909 diff changeset	3893 operand immU31()
89152779163c Merge with jdk8-b132 Gilles Duboscq <duboscq@ssw.jku.at> parents: 14909 diff changeset	3894 %{
89152779163c Merge with jdk8-b132 Gilles Duboscq <duboscq@ssw.jku.at> parents: 14909 diff changeset	3895 predicate(n->get_int() >= 0);
89152779163c Merge with jdk8-b132 Gilles Duboscq <duboscq@ssw.jku.at> parents: 14909 diff changeset	3896 match(ConI);
89152779163c Merge with jdk8-b132 Gilles Duboscq <duboscq@ssw.jku.at> parents: 14909 diff changeset	3897
89152779163c Merge with jdk8-b132 Gilles Duboscq <duboscq@ssw.jku.at> parents: 14909 diff changeset	3898 op_cost(0);
89152779163c Merge with jdk8-b132 Gilles Duboscq <duboscq@ssw.jku.at> parents: 14909 diff changeset	3899 format %{ %}
89152779163c Merge with jdk8-b132 Gilles Duboscq <duboscq@ssw.jku.at> parents: 14909 diff changeset	3900 interface(CONST_INTER);
89152779163c Merge with jdk8-b132 Gilles Duboscq <duboscq@ssw.jku.at> parents: 14909 diff changeset	3901 %}
89152779163c Merge with jdk8-b132 Gilles Duboscq <duboscq@ssw.jku.at> parents: 14909 diff changeset	3902
0 a61af66fc99e Initial load duke parents: diff changeset	3903 // Constant for long shifts
a61af66fc99e Initial load duke parents: diff changeset	3904 operand immI_32() %{
a61af66fc99e Initial load duke parents: diff changeset	3905 predicate( n->get_int() == 32 );
a61af66fc99e Initial load duke parents: diff changeset	3906 match(ConI);
a61af66fc99e Initial load duke parents: diff changeset	3907
a61af66fc99e Initial load duke parents: diff changeset	3908 op_cost(0);
a61af66fc99e Initial load duke parents: diff changeset	3909 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	3910 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	3911 %}
a61af66fc99e Initial load duke parents: diff changeset	3912
a61af66fc99e Initial load duke parents: diff changeset	3913 operand immI_1_31() %{
a61af66fc99e Initial load duke parents: diff changeset	3914 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
a61af66fc99e Initial load duke parents: diff changeset	3915 match(ConI);
a61af66fc99e Initial load duke parents: diff changeset	3916
a61af66fc99e Initial load duke parents: diff changeset	3917 op_cost(0);
a61af66fc99e Initial load duke parents: diff changeset	3918 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	3919 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	3920 %}
a61af66fc99e Initial load duke parents: diff changeset	3921
a61af66fc99e Initial load duke parents: diff changeset	3922 operand immI_32_63() %{
a61af66fc99e Initial load duke parents: diff changeset	3923 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
a61af66fc99e Initial load duke parents: diff changeset	3924 match(ConI);
a61af66fc99e Initial load duke parents: diff changeset	3925 op_cost(0);
a61af66fc99e Initial load duke parents: diff changeset	3926
a61af66fc99e Initial load duke parents: diff changeset	3927 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	3928 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	3929 %}
a61af66fc99e Initial load duke parents: diff changeset	3930
219 ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3931 operand immI_1() %{
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3932 predicate( n->get_int() == 1 );
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3933 match(ConI);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3934
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3935 op_cost(0);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3936 format %{ %}
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3937 interface(CONST_INTER);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3938 %}
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3939
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3940 operand immI_2() %{
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3941 predicate( n->get_int() == 2 );
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3942 match(ConI);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3943
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3944 op_cost(0);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3945 format %{ %}
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3946 interface(CONST_INTER);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3947 %}
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3948
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3949 operand immI_3() %{
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3950 predicate( n->get_int() == 3 );
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3951 match(ConI);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3952
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3953 op_cost(0);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3954 format %{ %}
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3955 interface(CONST_INTER);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3956 %}
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	3957
0 a61af66fc99e Initial load duke parents: diff changeset	3958 // Pointer Immediate
a61af66fc99e Initial load duke parents: diff changeset	3959 operand immP() %{
a61af66fc99e Initial load duke parents: diff changeset	3960 match(ConP);
a61af66fc99e Initial load duke parents: diff changeset	3961
a61af66fc99e Initial load duke parents: diff changeset	3962 op_cost(10);
a61af66fc99e Initial load duke parents: diff changeset	3963 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	3964 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	3965 %}
a61af66fc99e Initial load duke parents: diff changeset	3966
a61af66fc99e Initial load duke parents: diff changeset	3967 // NULL Pointer Immediate
a61af66fc99e Initial load duke parents: diff changeset	3968 operand immP0() %{
a61af66fc99e Initial load duke parents: diff changeset	3969 predicate( n->get_ptr() == 0 );
a61af66fc99e Initial load duke parents: diff changeset	3970 match(ConP);
a61af66fc99e Initial load duke parents: diff changeset	3971 op_cost(0);
a61af66fc99e Initial load duke parents: diff changeset	3972
a61af66fc99e Initial load duke parents: diff changeset	3973 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	3974 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	3975 %}
a61af66fc99e Initial load duke parents: diff changeset	3976
a61af66fc99e Initial load duke parents: diff changeset	3977 // Long Immediate
a61af66fc99e Initial load duke parents: diff changeset	3978 operand immL() %{
a61af66fc99e Initial load duke parents: diff changeset	3979 match(ConL);
a61af66fc99e Initial load duke parents: diff changeset	3980
a61af66fc99e Initial load duke parents: diff changeset	3981 op_cost(20);
a61af66fc99e Initial load duke parents: diff changeset	3982 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	3983 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	3984 %}
a61af66fc99e Initial load duke parents: diff changeset	3985
a61af66fc99e Initial load duke parents: diff changeset	3986 // Long Immediate zero
a61af66fc99e Initial load duke parents: diff changeset	3987 operand immL0() %{
a61af66fc99e Initial load duke parents: diff changeset	3988 predicate( n->get_long() == 0L );
a61af66fc99e Initial load duke parents: diff changeset	3989 match(ConL);
a61af66fc99e Initial load duke parents: diff changeset	3990 op_cost(0);
a61af66fc99e Initial load duke parents: diff changeset	3991
a61af66fc99e Initial load duke parents: diff changeset	3992 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	3993 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	3994 %}
a61af66fc99e Initial load duke parents: diff changeset	3995
403 b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	3996 // Long Immediate zero
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	3997 operand immL_M1() %{
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	3998 predicate( n->get_long() == -1L );
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	3999 match(ConL);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	4000 op_cost(0);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	4001
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	4002 format %{ %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	4003 interface(CONST_INTER);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	4004 %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	4005
0 a61af66fc99e Initial load duke parents: diff changeset	4006 // Long immediate from 0 to 127.
a61af66fc99e Initial load duke parents: diff changeset	4007 // Used for a shorter form of long mul by 10.
a61af66fc99e Initial load duke parents: diff changeset	4008 operand immL_127() %{
a61af66fc99e Initial load duke parents: diff changeset	4009 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
a61af66fc99e Initial load duke parents: diff changeset	4010 match(ConL);
a61af66fc99e Initial load duke parents: diff changeset	4011 op_cost(0);
a61af66fc99e Initial load duke parents: diff changeset	4012
a61af66fc99e Initial load duke parents: diff changeset	4013 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4014 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4015 %}
a61af66fc99e Initial load duke parents: diff changeset	4016
a61af66fc99e Initial load duke parents: diff changeset	4017 // Long Immediate: low 32-bit mask
a61af66fc99e Initial load duke parents: diff changeset	4018 operand immL_32bits() %{
a61af66fc99e Initial load duke parents: diff changeset	4019 predicate(n->get_long() == 0xFFFFFFFFL);
a61af66fc99e Initial load duke parents: diff changeset	4020 match(ConL);
a61af66fc99e Initial load duke parents: diff changeset	4021 op_cost(0);
a61af66fc99e Initial load duke parents: diff changeset	4022
a61af66fc99e Initial load duke parents: diff changeset	4023 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4024 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4025 %}
a61af66fc99e Initial load duke parents: diff changeset	4026
a61af66fc99e Initial load duke parents: diff changeset	4027 // Long Immediate: low 32-bit mask
a61af66fc99e Initial load duke parents: diff changeset	4028 operand immL32() %{
a61af66fc99e Initial load duke parents: diff changeset	4029 predicate(n->get_long() == (int)(n->get_long()));
a61af66fc99e Initial load duke parents: diff changeset	4030 match(ConL);
a61af66fc99e Initial load duke parents: diff changeset	4031 op_cost(20);
a61af66fc99e Initial load duke parents: diff changeset	4032
a61af66fc99e Initial load duke parents: diff changeset	4033 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4034 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4035 %}
a61af66fc99e Initial load duke parents: diff changeset	4036
a61af66fc99e Initial load duke parents: diff changeset	4037 //Double Immediate zero
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4038 operand immDPR0() %{
0 a61af66fc99e Initial load duke parents: diff changeset	4039 // Do additional (and counter-intuitive) test against NaN to work around VC++
a61af66fc99e Initial load duke parents: diff changeset	4040 // bug that generates code such that NaNs compare equal to 0.0
a61af66fc99e Initial load duke parents: diff changeset	4041 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
a61af66fc99e Initial load duke parents: diff changeset	4042 match(ConD);
a61af66fc99e Initial load duke parents: diff changeset	4043
a61af66fc99e Initial load duke parents: diff changeset	4044 op_cost(5);
a61af66fc99e Initial load duke parents: diff changeset	4045 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4046 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4047 %}
a61af66fc99e Initial load duke parents: diff changeset	4048
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	4049 // Double Immediate one
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4050 operand immDPR1() %{
0 a61af66fc99e Initial load duke parents: diff changeset	4051 predicate( UseSSE<=1 && n->getd() == 1.0 );
a61af66fc99e Initial load duke parents: diff changeset	4052 match(ConD);
a61af66fc99e Initial load duke parents: diff changeset	4053
a61af66fc99e Initial load duke parents: diff changeset	4054 op_cost(5);
a61af66fc99e Initial load duke parents: diff changeset	4055 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4056 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4057 %}
a61af66fc99e Initial load duke parents: diff changeset	4058
a61af66fc99e Initial load duke parents: diff changeset	4059 // Double Immediate
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4060 operand immDPR() %{
0 a61af66fc99e Initial load duke parents: diff changeset	4061 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	4062 match(ConD);
a61af66fc99e Initial load duke parents: diff changeset	4063
a61af66fc99e Initial load duke parents: diff changeset	4064 op_cost(5);
a61af66fc99e Initial load duke parents: diff changeset	4065 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4066 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4067 %}
a61af66fc99e Initial load duke parents: diff changeset	4068
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4069 operand immD() %{
0 a61af66fc99e Initial load duke parents: diff changeset	4070 predicate(UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	4071 match(ConD);
a61af66fc99e Initial load duke parents: diff changeset	4072
a61af66fc99e Initial load duke parents: diff changeset	4073 op_cost(5);
a61af66fc99e Initial load duke parents: diff changeset	4074 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4075 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4076 %}
a61af66fc99e Initial load duke parents: diff changeset	4077
a61af66fc99e Initial load duke parents: diff changeset	4078 // Double Immediate zero
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4079 operand immD0() %{
0 a61af66fc99e Initial load duke parents: diff changeset	4080 // Do additional (and counter-intuitive) test against NaN to work around VC++
a61af66fc99e Initial load duke parents: diff changeset	4081 // bug that generates code such that NaNs compare equal to 0.0 AND do not
a61af66fc99e Initial load duke parents: diff changeset	4082 // compare equal to -0.0.
a61af66fc99e Initial load duke parents: diff changeset	4083 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
a61af66fc99e Initial load duke parents: diff changeset	4084 match(ConD);
a61af66fc99e Initial load duke parents: diff changeset	4085
a61af66fc99e Initial load duke parents: diff changeset	4086 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4087 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4088 %}
a61af66fc99e Initial load duke parents: diff changeset	4089
a61af66fc99e Initial load duke parents: diff changeset	4090 // Float Immediate zero
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4091 operand immFPR0() %{
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	4092 predicate(UseSSE == 0 && n->getf() == 0.0F);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	4093 match(ConF);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	4094
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	4095 op_cost(5);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	4096 format %{ %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	4097 interface(CONST_INTER);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	4098 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	4099
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	4100 // Float Immediate one
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4101 operand immFPR1() %{
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	4102 predicate(UseSSE == 0 && n->getf() == 1.0F);
0 a61af66fc99e Initial load duke parents: diff changeset	4103 match(ConF);
a61af66fc99e Initial load duke parents: diff changeset	4104
a61af66fc99e Initial load duke parents: diff changeset	4105 op_cost(5);
a61af66fc99e Initial load duke parents: diff changeset	4106 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4107 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4108 %}
a61af66fc99e Initial load duke parents: diff changeset	4109
a61af66fc99e Initial load duke parents: diff changeset	4110 // Float Immediate
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4111 operand immFPR() %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4112 predicate( UseSSE == 0 );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4113 match(ConF);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4114
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4115 op_cost(5);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4116 format %{ %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4117 interface(CONST_INTER);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4118 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4119
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4120 // Float Immediate
0 a61af66fc99e Initial load duke parents: diff changeset	4121 operand immF() %{
a61af66fc99e Initial load duke parents: diff changeset	4122 predicate(UseSSE >= 1);
a61af66fc99e Initial load duke parents: diff changeset	4123 match(ConF);
a61af66fc99e Initial load duke parents: diff changeset	4124
a61af66fc99e Initial load duke parents: diff changeset	4125 op_cost(5);
a61af66fc99e Initial load duke parents: diff changeset	4126 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4127 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4128 %}
a61af66fc99e Initial load duke parents: diff changeset	4129
a61af66fc99e Initial load duke parents: diff changeset	4130 // Float Immediate zero. Zero and not -0.0
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4131 operand immF0() %{
0 a61af66fc99e Initial load duke parents: diff changeset	4132 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
a61af66fc99e Initial load duke parents: diff changeset	4133 match(ConF);
a61af66fc99e Initial load duke parents: diff changeset	4134
a61af66fc99e Initial load duke parents: diff changeset	4135 op_cost(5);
a61af66fc99e Initial load duke parents: diff changeset	4136 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4137 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4138 %}
a61af66fc99e Initial load duke parents: diff changeset	4139
a61af66fc99e Initial load duke parents: diff changeset	4140 // Immediates for special shifts (sign extend)
a61af66fc99e Initial load duke parents: diff changeset	4141
a61af66fc99e Initial load duke parents: diff changeset	4142 // Constants for increment
a61af66fc99e Initial load duke parents: diff changeset	4143 operand immI_16() %{
a61af66fc99e Initial load duke parents: diff changeset	4144 predicate( n->get_int() == 16 );
a61af66fc99e Initial load duke parents: diff changeset	4145 match(ConI);
a61af66fc99e Initial load duke parents: diff changeset	4146
a61af66fc99e Initial load duke parents: diff changeset	4147 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4148 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4149 %}
a61af66fc99e Initial load duke parents: diff changeset	4150
a61af66fc99e Initial load duke parents: diff changeset	4151 operand immI_24() %{
a61af66fc99e Initial load duke parents: diff changeset	4152 predicate( n->get_int() == 24 );
a61af66fc99e Initial load duke parents: diff changeset	4153 match(ConI);
a61af66fc99e Initial load duke parents: diff changeset	4154
a61af66fc99e Initial load duke parents: diff changeset	4155 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4156 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4157 %}
a61af66fc99e Initial load duke parents: diff changeset	4158
a61af66fc99e Initial load duke parents: diff changeset	4159 // Constant for byte-wide masking
a61af66fc99e Initial load duke parents: diff changeset	4160 operand immI_255() %{
a61af66fc99e Initial load duke parents: diff changeset	4161 predicate( n->get_int() == 255 );
a61af66fc99e Initial load duke parents: diff changeset	4162 match(ConI);
a61af66fc99e Initial load duke parents: diff changeset	4163
a61af66fc99e Initial load duke parents: diff changeset	4164 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4165 interface(CONST_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4166 %}
a61af66fc99e Initial load duke parents: diff changeset	4167
785 2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	4168 // Constant for short-wide masking
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	4169 operand immI_65535() %{
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	4170 predicate(n->get_int() == 65535);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	4171 match(ConI);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	4172
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	4173 format %{ %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	4174 interface(CONST_INTER);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	4175 %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	4176
0 a61af66fc99e Initial load duke parents: diff changeset	4177 // Register Operands
a61af66fc99e Initial load duke parents: diff changeset	4178 // Integer Register
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4179 operand rRegI() %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4180 constraint(ALLOC_IN_RC(int_reg));
0 a61af66fc99e Initial load duke parents: diff changeset	4181 match(RegI);
a61af66fc99e Initial load duke parents: diff changeset	4182 match(xRegI);
a61af66fc99e Initial load duke parents: diff changeset	4183 match(eAXRegI);
a61af66fc99e Initial load duke parents: diff changeset	4184 match(eBXRegI);
a61af66fc99e Initial load duke parents: diff changeset	4185 match(eCXRegI);
a61af66fc99e Initial load duke parents: diff changeset	4186 match(eDXRegI);
a61af66fc99e Initial load duke parents: diff changeset	4187 match(eDIRegI);
a61af66fc99e Initial load duke parents: diff changeset	4188 match(eSIRegI);
a61af66fc99e Initial load duke parents: diff changeset	4189
a61af66fc99e Initial load duke parents: diff changeset	4190 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4191 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4192 %}
a61af66fc99e Initial load duke parents: diff changeset	4193
a61af66fc99e Initial load duke parents: diff changeset	4194 // Subset of Integer Register
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4195 operand xRegI(rRegI reg) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4196 constraint(ALLOC_IN_RC(int_x_reg));
0 a61af66fc99e Initial load duke parents: diff changeset	4197 match(reg);
a61af66fc99e Initial load duke parents: diff changeset	4198 match(eAXRegI);
a61af66fc99e Initial load duke parents: diff changeset	4199 match(eBXRegI);
a61af66fc99e Initial load duke parents: diff changeset	4200 match(eCXRegI);
a61af66fc99e Initial load duke parents: diff changeset	4201 match(eDXRegI);
a61af66fc99e Initial load duke parents: diff changeset	4202
a61af66fc99e Initial load duke parents: diff changeset	4203 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4204 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4205 %}
a61af66fc99e Initial load duke parents: diff changeset	4206
a61af66fc99e Initial load duke parents: diff changeset	4207 // Special Registers
a61af66fc99e Initial load duke parents: diff changeset	4208 operand eAXRegI(xRegI reg) %{
a61af66fc99e Initial load duke parents: diff changeset	4209 constraint(ALLOC_IN_RC(eax_reg));
a61af66fc99e Initial load duke parents: diff changeset	4210 match(reg);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4211 match(rRegI);
0 a61af66fc99e Initial load duke parents: diff changeset	4212
a61af66fc99e Initial load duke parents: diff changeset	4213 format %{ "EAX" %}
a61af66fc99e Initial load duke parents: diff changeset	4214 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4215 %}
a61af66fc99e Initial load duke parents: diff changeset	4216
a61af66fc99e Initial load duke parents: diff changeset	4217 // Special Registers
a61af66fc99e Initial load duke parents: diff changeset	4218 operand eBXRegI(xRegI reg) %{
a61af66fc99e Initial load duke parents: diff changeset	4219 constraint(ALLOC_IN_RC(ebx_reg));
a61af66fc99e Initial load duke parents: diff changeset	4220 match(reg);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4221 match(rRegI);
0 a61af66fc99e Initial load duke parents: diff changeset	4222
a61af66fc99e Initial load duke parents: diff changeset	4223 format %{ "EBX" %}
a61af66fc99e Initial load duke parents: diff changeset	4224 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4225 %}
a61af66fc99e Initial load duke parents: diff changeset	4226
a61af66fc99e Initial load duke parents: diff changeset	4227 operand eCXRegI(xRegI reg) %{
a61af66fc99e Initial load duke parents: diff changeset	4228 constraint(ALLOC_IN_RC(ecx_reg));
a61af66fc99e Initial load duke parents: diff changeset	4229 match(reg);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4230 match(rRegI);
0 a61af66fc99e Initial load duke parents: diff changeset	4231
a61af66fc99e Initial load duke parents: diff changeset	4232 format %{ "ECX" %}
a61af66fc99e Initial load duke parents: diff changeset	4233 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4234 %}
a61af66fc99e Initial load duke parents: diff changeset	4235
a61af66fc99e Initial load duke parents: diff changeset	4236 operand eDXRegI(xRegI reg) %{
a61af66fc99e Initial load duke parents: diff changeset	4237 constraint(ALLOC_IN_RC(edx_reg));
a61af66fc99e Initial load duke parents: diff changeset	4238 match(reg);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4239 match(rRegI);
0 a61af66fc99e Initial load duke parents: diff changeset	4240
a61af66fc99e Initial load duke parents: diff changeset	4241 format %{ "EDX" %}
a61af66fc99e Initial load duke parents: diff changeset	4242 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4243 %}
a61af66fc99e Initial load duke parents: diff changeset	4244
a61af66fc99e Initial load duke parents: diff changeset	4245 operand eDIRegI(xRegI reg) %{
a61af66fc99e Initial load duke parents: diff changeset	4246 constraint(ALLOC_IN_RC(edi_reg));
a61af66fc99e Initial load duke parents: diff changeset	4247 match(reg);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4248 match(rRegI);
0 a61af66fc99e Initial load duke parents: diff changeset	4249
a61af66fc99e Initial load duke parents: diff changeset	4250 format %{ "EDI" %}
a61af66fc99e Initial load duke parents: diff changeset	4251 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4252 %}
a61af66fc99e Initial load duke parents: diff changeset	4253
a61af66fc99e Initial load duke parents: diff changeset	4254 operand naxRegI() %{
a61af66fc99e Initial load duke parents: diff changeset	4255 constraint(ALLOC_IN_RC(nax_reg));
a61af66fc99e Initial load duke parents: diff changeset	4256 match(RegI);
a61af66fc99e Initial load duke parents: diff changeset	4257 match(eCXRegI);
a61af66fc99e Initial load duke parents: diff changeset	4258 match(eDXRegI);
a61af66fc99e Initial load duke parents: diff changeset	4259 match(eSIRegI);
a61af66fc99e Initial load duke parents: diff changeset	4260 match(eDIRegI);
a61af66fc99e Initial load duke parents: diff changeset	4261
a61af66fc99e Initial load duke parents: diff changeset	4262 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4263 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4264 %}
a61af66fc99e Initial load duke parents: diff changeset	4265
a61af66fc99e Initial load duke parents: diff changeset	4266 operand nadxRegI() %{
a61af66fc99e Initial load duke parents: diff changeset	4267 constraint(ALLOC_IN_RC(nadx_reg));
a61af66fc99e Initial load duke parents: diff changeset	4268 match(RegI);
a61af66fc99e Initial load duke parents: diff changeset	4269 match(eBXRegI);
a61af66fc99e Initial load duke parents: diff changeset	4270 match(eCXRegI);
a61af66fc99e Initial load duke parents: diff changeset	4271 match(eSIRegI);
a61af66fc99e Initial load duke parents: diff changeset	4272 match(eDIRegI);
a61af66fc99e Initial load duke parents: diff changeset	4273
a61af66fc99e Initial load duke parents: diff changeset	4274 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4275 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4276 %}
a61af66fc99e Initial load duke parents: diff changeset	4277
a61af66fc99e Initial load duke parents: diff changeset	4278 operand ncxRegI() %{
a61af66fc99e Initial load duke parents: diff changeset	4279 constraint(ALLOC_IN_RC(ncx_reg));
a61af66fc99e Initial load duke parents: diff changeset	4280 match(RegI);
a61af66fc99e Initial load duke parents: diff changeset	4281 match(eAXRegI);
a61af66fc99e Initial load duke parents: diff changeset	4282 match(eDXRegI);
a61af66fc99e Initial load duke parents: diff changeset	4283 match(eSIRegI);
a61af66fc99e Initial load duke parents: diff changeset	4284 match(eDIRegI);
a61af66fc99e Initial load duke parents: diff changeset	4285
a61af66fc99e Initial load duke parents: diff changeset	4286 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4287 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4288 %}
a61af66fc99e Initial load duke parents: diff changeset	4289
a61af66fc99e Initial load duke parents: diff changeset	4290 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
a61af66fc99e Initial load duke parents: diff changeset	4291 // //
a61af66fc99e Initial load duke parents: diff changeset	4292 operand eSIRegI(xRegI reg) %{
a61af66fc99e Initial load duke parents: diff changeset	4293 constraint(ALLOC_IN_RC(esi_reg));
a61af66fc99e Initial load duke parents: diff changeset	4294 match(reg);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4295 match(rRegI);
0 a61af66fc99e Initial load duke parents: diff changeset	4296
a61af66fc99e Initial load duke parents: diff changeset	4297 format %{ "ESI" %}
a61af66fc99e Initial load duke parents: diff changeset	4298 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4299 %}
a61af66fc99e Initial load duke parents: diff changeset	4300
a61af66fc99e Initial load duke parents: diff changeset	4301 // Pointer Register
a61af66fc99e Initial load duke parents: diff changeset	4302 operand anyRegP() %{
a61af66fc99e Initial load duke parents: diff changeset	4303 constraint(ALLOC_IN_RC(any_reg));
a61af66fc99e Initial load duke parents: diff changeset	4304 match(RegP);
a61af66fc99e Initial load duke parents: diff changeset	4305 match(eAXRegP);
a61af66fc99e Initial load duke parents: diff changeset	4306 match(eBXRegP);
a61af66fc99e Initial load duke parents: diff changeset	4307 match(eCXRegP);
a61af66fc99e Initial load duke parents: diff changeset	4308 match(eDIRegP);
a61af66fc99e Initial load duke parents: diff changeset	4309 match(eRegP);
a61af66fc99e Initial load duke parents: diff changeset	4310
a61af66fc99e Initial load duke parents: diff changeset	4311 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4312 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4313 %}
a61af66fc99e Initial load duke parents: diff changeset	4314
a61af66fc99e Initial load duke parents: diff changeset	4315 operand eRegP() %{
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4316 constraint(ALLOC_IN_RC(int_reg));
0 a61af66fc99e Initial load duke parents: diff changeset	4317 match(RegP);
a61af66fc99e Initial load duke parents: diff changeset	4318 match(eAXRegP);
a61af66fc99e Initial load duke parents: diff changeset	4319 match(eBXRegP);
a61af66fc99e Initial load duke parents: diff changeset	4320 match(eCXRegP);
a61af66fc99e Initial load duke parents: diff changeset	4321 match(eDIRegP);
a61af66fc99e Initial load duke parents: diff changeset	4322
a61af66fc99e Initial load duke parents: diff changeset	4323 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4324 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4325 %}
a61af66fc99e Initial load duke parents: diff changeset	4326
a61af66fc99e Initial load duke parents: diff changeset	4327 // On windows95, EBP is not safe to use for implicit null tests.
a61af66fc99e Initial load duke parents: diff changeset	4328 operand eRegP_no_EBP() %{
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4329 constraint(ALLOC_IN_RC(int_reg_no_rbp));
0 a61af66fc99e Initial load duke parents: diff changeset	4330 match(RegP);
a61af66fc99e Initial load duke parents: diff changeset	4331 match(eAXRegP);
a61af66fc99e Initial load duke parents: diff changeset	4332 match(eBXRegP);
a61af66fc99e Initial load duke parents: diff changeset	4333 match(eCXRegP);
a61af66fc99e Initial load duke parents: diff changeset	4334 match(eDIRegP);
a61af66fc99e Initial load duke parents: diff changeset	4335
a61af66fc99e Initial load duke parents: diff changeset	4336 op_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	4337 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4338 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4339 %}
a61af66fc99e Initial load duke parents: diff changeset	4340
a61af66fc99e Initial load duke parents: diff changeset	4341 operand naxRegP() %{
a61af66fc99e Initial load duke parents: diff changeset	4342 constraint(ALLOC_IN_RC(nax_reg));
a61af66fc99e Initial load duke parents: diff changeset	4343 match(RegP);
a61af66fc99e Initial load duke parents: diff changeset	4344 match(eBXRegP);
a61af66fc99e Initial load duke parents: diff changeset	4345 match(eDXRegP);
a61af66fc99e Initial load duke parents: diff changeset	4346 match(eCXRegP);
a61af66fc99e Initial load duke parents: diff changeset	4347 match(eSIRegP);
a61af66fc99e Initial load duke parents: diff changeset	4348 match(eDIRegP);
a61af66fc99e Initial load duke parents: diff changeset	4349
a61af66fc99e Initial load duke parents: diff changeset	4350 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4351 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4352 %}
a61af66fc99e Initial load duke parents: diff changeset	4353
a61af66fc99e Initial load duke parents: diff changeset	4354 operand nabxRegP() %{
a61af66fc99e Initial load duke parents: diff changeset	4355 constraint(ALLOC_IN_RC(nabx_reg));
a61af66fc99e Initial load duke parents: diff changeset	4356 match(RegP);
a61af66fc99e Initial load duke parents: diff changeset	4357 match(eCXRegP);
a61af66fc99e Initial load duke parents: diff changeset	4358 match(eDXRegP);
a61af66fc99e Initial load duke parents: diff changeset	4359 match(eSIRegP);
a61af66fc99e Initial load duke parents: diff changeset	4360 match(eDIRegP);
a61af66fc99e Initial load duke parents: diff changeset	4361
a61af66fc99e Initial load duke parents: diff changeset	4362 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4363 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4364 %}
a61af66fc99e Initial load duke parents: diff changeset	4365
a61af66fc99e Initial load duke parents: diff changeset	4366 operand pRegP() %{
a61af66fc99e Initial load duke parents: diff changeset	4367 constraint(ALLOC_IN_RC(p_reg));
a61af66fc99e Initial load duke parents: diff changeset	4368 match(RegP);
a61af66fc99e Initial load duke parents: diff changeset	4369 match(eBXRegP);
a61af66fc99e Initial load duke parents: diff changeset	4370 match(eDXRegP);
a61af66fc99e Initial load duke parents: diff changeset	4371 match(eSIRegP);
a61af66fc99e Initial load duke parents: diff changeset	4372 match(eDIRegP);
a61af66fc99e Initial load duke parents: diff changeset	4373
a61af66fc99e Initial load duke parents: diff changeset	4374 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4375 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4376 %}
a61af66fc99e Initial load duke parents: diff changeset	4377
a61af66fc99e Initial load duke parents: diff changeset	4378 // Special Registers
a61af66fc99e Initial load duke parents: diff changeset	4379 // Return a pointer value
a61af66fc99e Initial load duke parents: diff changeset	4380 operand eAXRegP(eRegP reg) %{
a61af66fc99e Initial load duke parents: diff changeset	4381 constraint(ALLOC_IN_RC(eax_reg));
a61af66fc99e Initial load duke parents: diff changeset	4382 match(reg);
a61af66fc99e Initial load duke parents: diff changeset	4383 format %{ "EAX" %}
a61af66fc99e Initial load duke parents: diff changeset	4384 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4385 %}
a61af66fc99e Initial load duke parents: diff changeset	4386
a61af66fc99e Initial load duke parents: diff changeset	4387 // Used in AtomicAdd
a61af66fc99e Initial load duke parents: diff changeset	4388 operand eBXRegP(eRegP reg) %{
a61af66fc99e Initial load duke parents: diff changeset	4389 constraint(ALLOC_IN_RC(ebx_reg));
a61af66fc99e Initial load duke parents: diff changeset	4390 match(reg);
a61af66fc99e Initial load duke parents: diff changeset	4391 format %{ "EBX" %}
a61af66fc99e Initial load duke parents: diff changeset	4392 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4393 %}
a61af66fc99e Initial load duke parents: diff changeset	4394
a61af66fc99e Initial load duke parents: diff changeset	4395 // Tail-call (interprocedural jump) to interpreter
a61af66fc99e Initial load duke parents: diff changeset	4396 operand eCXRegP(eRegP reg) %{
a61af66fc99e Initial load duke parents: diff changeset	4397 constraint(ALLOC_IN_RC(ecx_reg));
a61af66fc99e Initial load duke parents: diff changeset	4398 match(reg);
a61af66fc99e Initial load duke parents: diff changeset	4399 format %{ "ECX" %}
a61af66fc99e Initial load duke parents: diff changeset	4400 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4401 %}
a61af66fc99e Initial load duke parents: diff changeset	4402
a61af66fc99e Initial load duke parents: diff changeset	4403 operand eSIRegP(eRegP reg) %{
a61af66fc99e Initial load duke parents: diff changeset	4404 constraint(ALLOC_IN_RC(esi_reg));
a61af66fc99e Initial load duke parents: diff changeset	4405 match(reg);
a61af66fc99e Initial load duke parents: diff changeset	4406 format %{ "ESI" %}
a61af66fc99e Initial load duke parents: diff changeset	4407 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4408 %}
a61af66fc99e Initial load duke parents: diff changeset	4409
a61af66fc99e Initial load duke parents: diff changeset	4410 // Used in rep stosw
a61af66fc99e Initial load duke parents: diff changeset	4411 operand eDIRegP(eRegP reg) %{
a61af66fc99e Initial load duke parents: diff changeset	4412 constraint(ALLOC_IN_RC(edi_reg));
a61af66fc99e Initial load duke parents: diff changeset	4413 match(reg);
a61af66fc99e Initial load duke parents: diff changeset	4414 format %{ "EDI" %}
a61af66fc99e Initial load duke parents: diff changeset	4415 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4416 %}
a61af66fc99e Initial load duke parents: diff changeset	4417
a61af66fc99e Initial load duke parents: diff changeset	4418 operand eBPRegP() %{
a61af66fc99e Initial load duke parents: diff changeset	4419 constraint(ALLOC_IN_RC(ebp_reg));
a61af66fc99e Initial load duke parents: diff changeset	4420 match(RegP);
a61af66fc99e Initial load duke parents: diff changeset	4421 format %{ "EBP" %}
a61af66fc99e Initial load duke parents: diff changeset	4422 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4423 %}
a61af66fc99e Initial load duke parents: diff changeset	4424
a61af66fc99e Initial load duke parents: diff changeset	4425 operand eRegL() %{
a61af66fc99e Initial load duke parents: diff changeset	4426 constraint(ALLOC_IN_RC(long_reg));
a61af66fc99e Initial load duke parents: diff changeset	4427 match(RegL);
a61af66fc99e Initial load duke parents: diff changeset	4428 match(eADXRegL);
a61af66fc99e Initial load duke parents: diff changeset	4429
a61af66fc99e Initial load duke parents: diff changeset	4430 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4431 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4432 %}
a61af66fc99e Initial load duke parents: diff changeset	4433
a61af66fc99e Initial load duke parents: diff changeset	4434 operand eADXRegL( eRegL reg ) %{
a61af66fc99e Initial load duke parents: diff changeset	4435 constraint(ALLOC_IN_RC(eadx_reg));
a61af66fc99e Initial load duke parents: diff changeset	4436 match(reg);
a61af66fc99e Initial load duke parents: diff changeset	4437
a61af66fc99e Initial load duke parents: diff changeset	4438 format %{ "EDX:EAX" %}
a61af66fc99e Initial load duke parents: diff changeset	4439 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4440 %}
a61af66fc99e Initial load duke parents: diff changeset	4441
a61af66fc99e Initial load duke parents: diff changeset	4442 operand eBCXRegL( eRegL reg ) %{
a61af66fc99e Initial load duke parents: diff changeset	4443 constraint(ALLOC_IN_RC(ebcx_reg));
a61af66fc99e Initial load duke parents: diff changeset	4444 match(reg);
a61af66fc99e Initial load duke parents: diff changeset	4445
a61af66fc99e Initial load duke parents: diff changeset	4446 format %{ "EBX:ECX" %}
a61af66fc99e Initial load duke parents: diff changeset	4447 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4448 %}
a61af66fc99e Initial load duke parents: diff changeset	4449
a61af66fc99e Initial load duke parents: diff changeset	4450 // Special case for integer high multiply
a61af66fc99e Initial load duke parents: diff changeset	4451 operand eADXRegL_low_only() %{
a61af66fc99e Initial load duke parents: diff changeset	4452 constraint(ALLOC_IN_RC(eadx_reg));
a61af66fc99e Initial load duke parents: diff changeset	4453 match(RegL);
a61af66fc99e Initial load duke parents: diff changeset	4454
a61af66fc99e Initial load duke parents: diff changeset	4455 format %{ "EAX" %}
a61af66fc99e Initial load duke parents: diff changeset	4456 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4457 %}
a61af66fc99e Initial load duke parents: diff changeset	4458
a61af66fc99e Initial load duke parents: diff changeset	4459 // Flags register, used as output of compare instructions
a61af66fc99e Initial load duke parents: diff changeset	4460 operand eFlagsReg() %{
a61af66fc99e Initial load duke parents: diff changeset	4461 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load duke parents: diff changeset	4462 match(RegFlags);
a61af66fc99e Initial load duke parents: diff changeset	4463
a61af66fc99e Initial load duke parents: diff changeset	4464 format %{ "EFLAGS" %}
a61af66fc99e Initial load duke parents: diff changeset	4465 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4466 %}
a61af66fc99e Initial load duke parents: diff changeset	4467
a61af66fc99e Initial load duke parents: diff changeset	4468 // Flags register, used as output of FLOATING POINT compare instructions
a61af66fc99e Initial load duke parents: diff changeset	4469 operand eFlagsRegU() %{
a61af66fc99e Initial load duke parents: diff changeset	4470 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load duke parents: diff changeset	4471 match(RegFlags);
a61af66fc99e Initial load duke parents: diff changeset	4472
a61af66fc99e Initial load duke parents: diff changeset	4473 format %{ "EFLAGS_U" %}
a61af66fc99e Initial load duke parents: diff changeset	4474 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4475 %}
a61af66fc99e Initial load duke parents: diff changeset	4476
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4477 operand eFlagsRegUCF() %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4478 constraint(ALLOC_IN_RC(int_flags));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4479 match(RegFlags);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4480 predicate(false);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4481
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4482 format %{ "EFLAGS_U_CF" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4483 interface(REG_INTER);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4484 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4485
0 a61af66fc99e Initial load duke parents: diff changeset	4486 // Condition Code Register used by long compare
a61af66fc99e Initial load duke parents: diff changeset	4487 operand flagsReg_long_LTGE() %{
a61af66fc99e Initial load duke parents: diff changeset	4488 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load duke parents: diff changeset	4489 match(RegFlags);
a61af66fc99e Initial load duke parents: diff changeset	4490 format %{ "FLAGS_LTGE" %}
a61af66fc99e Initial load duke parents: diff changeset	4491 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4492 %}
a61af66fc99e Initial load duke parents: diff changeset	4493 operand flagsReg_long_EQNE() %{
a61af66fc99e Initial load duke parents: diff changeset	4494 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load duke parents: diff changeset	4495 match(RegFlags);
a61af66fc99e Initial load duke parents: diff changeset	4496 format %{ "FLAGS_EQNE" %}
a61af66fc99e Initial load duke parents: diff changeset	4497 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4498 %}
a61af66fc99e Initial load duke parents: diff changeset	4499 operand flagsReg_long_LEGT() %{
a61af66fc99e Initial load duke parents: diff changeset	4500 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load duke parents: diff changeset	4501 match(RegFlags);
a61af66fc99e Initial load duke parents: diff changeset	4502 format %{ "FLAGS_LEGT" %}
a61af66fc99e Initial load duke parents: diff changeset	4503 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4504 %}
a61af66fc99e Initial load duke parents: diff changeset	4505
a61af66fc99e Initial load duke parents: diff changeset	4506 // Float register operands
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4507 operand regDPR() %{
0 a61af66fc99e Initial load duke parents: diff changeset	4508 predicate( UseSSE < 2 );
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4509 constraint(ALLOC_IN_RC(fp_dbl_reg));
0 a61af66fc99e Initial load duke parents: diff changeset	4510 match(RegD);
a61af66fc99e Initial load duke parents: diff changeset	4511 match(regDPR1);
a61af66fc99e Initial load duke parents: diff changeset	4512 match(regDPR2);
a61af66fc99e Initial load duke parents: diff changeset	4513 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4514 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4515 %}
a61af66fc99e Initial load duke parents: diff changeset	4516
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4517 operand regDPR1(regDPR reg) %{
0 a61af66fc99e Initial load duke parents: diff changeset	4518 predicate( UseSSE < 2 );
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4519 constraint(ALLOC_IN_RC(fp_dbl_reg0));
0 a61af66fc99e Initial load duke parents: diff changeset	4520 match(reg);
a61af66fc99e Initial load duke parents: diff changeset	4521 format %{ "FPR1" %}
a61af66fc99e Initial load duke parents: diff changeset	4522 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4523 %}
a61af66fc99e Initial load duke parents: diff changeset	4524
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4525 operand regDPR2(regDPR reg) %{
0 a61af66fc99e Initial load duke parents: diff changeset	4526 predicate( UseSSE < 2 );
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4527 constraint(ALLOC_IN_RC(fp_dbl_reg1));
0 a61af66fc99e Initial load duke parents: diff changeset	4528 match(reg);
a61af66fc99e Initial load duke parents: diff changeset	4529 format %{ "FPR2" %}
a61af66fc99e Initial load duke parents: diff changeset	4530 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4531 %}
a61af66fc99e Initial load duke parents: diff changeset	4532
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4533 operand regnotDPR1(regDPR reg) %{
0 a61af66fc99e Initial load duke parents: diff changeset	4534 predicate( UseSSE < 2 );
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4535 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
0 a61af66fc99e Initial load duke parents: diff changeset	4536 match(reg);
a61af66fc99e Initial load duke parents: diff changeset	4537 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4538 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4539 %}
a61af66fc99e Initial load duke parents: diff changeset	4540
a61af66fc99e Initial load duke parents: diff changeset	4541 // Float register operands
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4542 operand regFPR() %{
0 a61af66fc99e Initial load duke parents: diff changeset	4543 predicate( UseSSE < 2 );
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4544 constraint(ALLOC_IN_RC(fp_flt_reg));
0 a61af66fc99e Initial load duke parents: diff changeset	4545 match(RegF);
a61af66fc99e Initial load duke parents: diff changeset	4546 match(regFPR1);
a61af66fc99e Initial load duke parents: diff changeset	4547 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4548 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4549 %}
a61af66fc99e Initial load duke parents: diff changeset	4550
a61af66fc99e Initial load duke parents: diff changeset	4551 // Float register operands
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4552 operand regFPR1(regFPR reg) %{
0 a61af66fc99e Initial load duke parents: diff changeset	4553 predicate( UseSSE < 2 );
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4554 constraint(ALLOC_IN_RC(fp_flt_reg0));
0 a61af66fc99e Initial load duke parents: diff changeset	4555 match(reg);
a61af66fc99e Initial load duke parents: diff changeset	4556 format %{ "FPR1" %}
a61af66fc99e Initial load duke parents: diff changeset	4557 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4558 %}
a61af66fc99e Initial load duke parents: diff changeset	4559
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4560 // XMM Float register operands
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	4561 operand regF() %{
0 a61af66fc99e Initial load duke parents: diff changeset	4562 predicate( UseSSE>=1 );
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4563 constraint(ALLOC_IN_RC(float_reg));
0 a61af66fc99e Initial load duke parents: diff changeset	4564 match(RegF);
a61af66fc99e Initial load duke parents: diff changeset	4565 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4566 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4567 %}
a61af66fc99e Initial load duke parents: diff changeset	4568
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4569 // XMM Double register operands
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4570 operand regD() %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4571 predicate( UseSSE>=2 );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4572 constraint(ALLOC_IN_RC(double_reg));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4573 match(RegD);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4574 format %{ %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4575 interface(REG_INTER);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4576 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4577
0 a61af66fc99e Initial load duke parents: diff changeset	4578
a61af66fc99e Initial load duke parents: diff changeset	4579 //----------Memory Operands----------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	4580 // Direct Memory Operand
a61af66fc99e Initial load duke parents: diff changeset	4581 operand direct(immP addr) %{
a61af66fc99e Initial load duke parents: diff changeset	4582 match(addr);
a61af66fc99e Initial load duke parents: diff changeset	4583
a61af66fc99e Initial load duke parents: diff changeset	4584 format %{ "[$addr]" %}
a61af66fc99e Initial load duke parents: diff changeset	4585 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4586 base(0xFFFFFFFF);
a61af66fc99e Initial load duke parents: diff changeset	4587 index(0x4);
a61af66fc99e Initial load duke parents: diff changeset	4588 scale(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4589 disp($addr);
a61af66fc99e Initial load duke parents: diff changeset	4590 %}
a61af66fc99e Initial load duke parents: diff changeset	4591 %}
a61af66fc99e Initial load duke parents: diff changeset	4592
a61af66fc99e Initial load duke parents: diff changeset	4593 // Indirect Memory Operand
a61af66fc99e Initial load duke parents: diff changeset	4594 operand indirect(eRegP reg) %{
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4595 constraint(ALLOC_IN_RC(int_reg));
0 a61af66fc99e Initial load duke parents: diff changeset	4596 match(reg);
a61af66fc99e Initial load duke parents: diff changeset	4597
a61af66fc99e Initial load duke parents: diff changeset	4598 format %{ "[$reg]" %}
a61af66fc99e Initial load duke parents: diff changeset	4599 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4600 base($reg);
a61af66fc99e Initial load duke parents: diff changeset	4601 index(0x4);
a61af66fc99e Initial load duke parents: diff changeset	4602 scale(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4603 disp(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4604 %}
a61af66fc99e Initial load duke parents: diff changeset	4605 %}
a61af66fc99e Initial load duke parents: diff changeset	4606
a61af66fc99e Initial load duke parents: diff changeset	4607 // Indirect Memory Plus Short Offset Operand
a61af66fc99e Initial load duke parents: diff changeset	4608 operand indOffset8(eRegP reg, immI8 off) %{
a61af66fc99e Initial load duke parents: diff changeset	4609 match(AddP reg off);
a61af66fc99e Initial load duke parents: diff changeset	4610
a61af66fc99e Initial load duke parents: diff changeset	4611 format %{ "[$reg + $off]" %}
a61af66fc99e Initial load duke parents: diff changeset	4612 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4613 base($reg);
a61af66fc99e Initial load duke parents: diff changeset	4614 index(0x4);
a61af66fc99e Initial load duke parents: diff changeset	4615 scale(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4616 disp($off);
a61af66fc99e Initial load duke parents: diff changeset	4617 %}
a61af66fc99e Initial load duke parents: diff changeset	4618 %}
a61af66fc99e Initial load duke parents: diff changeset	4619
a61af66fc99e Initial load duke parents: diff changeset	4620 // Indirect Memory Plus Long Offset Operand
a61af66fc99e Initial load duke parents: diff changeset	4621 operand indOffset32(eRegP reg, immI off) %{
a61af66fc99e Initial load duke parents: diff changeset	4622 match(AddP reg off);
a61af66fc99e Initial load duke parents: diff changeset	4623
a61af66fc99e Initial load duke parents: diff changeset	4624 format %{ "[$reg + $off]" %}
a61af66fc99e Initial load duke parents: diff changeset	4625 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4626 base($reg);
a61af66fc99e Initial load duke parents: diff changeset	4627 index(0x4);
a61af66fc99e Initial load duke parents: diff changeset	4628 scale(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4629 disp($off);
a61af66fc99e Initial load duke parents: diff changeset	4630 %}
a61af66fc99e Initial load duke parents: diff changeset	4631 %}
a61af66fc99e Initial load duke parents: diff changeset	4632
a61af66fc99e Initial load duke parents: diff changeset	4633 // Indirect Memory Plus Long Offset Operand
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4634 operand indOffset32X(rRegI reg, immP off) %{
0 a61af66fc99e Initial load duke parents: diff changeset	4635 match(AddP off reg);
a61af66fc99e Initial load duke parents: diff changeset	4636
a61af66fc99e Initial load duke parents: diff changeset	4637 format %{ "[$reg + $off]" %}
a61af66fc99e Initial load duke parents: diff changeset	4638 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4639 base($reg);
a61af66fc99e Initial load duke parents: diff changeset	4640 index(0x4);
a61af66fc99e Initial load duke parents: diff changeset	4641 scale(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4642 disp($off);
a61af66fc99e Initial load duke parents: diff changeset	4643 %}
a61af66fc99e Initial load duke parents: diff changeset	4644 %}
a61af66fc99e Initial load duke parents: diff changeset	4645
a61af66fc99e Initial load duke parents: diff changeset	4646 // Indirect Memory Plus Index Register Plus Offset Operand
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4647 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
0 a61af66fc99e Initial load duke parents: diff changeset	4648 match(AddP (AddP reg ireg) off);
a61af66fc99e Initial load duke parents: diff changeset	4649
a61af66fc99e Initial load duke parents: diff changeset	4650 op_cost(10);
a61af66fc99e Initial load duke parents: diff changeset	4651 format %{"[$reg + $off + $ireg]" %}
a61af66fc99e Initial load duke parents: diff changeset	4652 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4653 base($reg);
a61af66fc99e Initial load duke parents: diff changeset	4654 index($ireg);
a61af66fc99e Initial load duke parents: diff changeset	4655 scale(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4656 disp($off);
a61af66fc99e Initial load duke parents: diff changeset	4657 %}
a61af66fc99e Initial load duke parents: diff changeset	4658 %}
a61af66fc99e Initial load duke parents: diff changeset	4659
a61af66fc99e Initial load duke parents: diff changeset	4660 // Indirect Memory Plus Index Register Plus Offset Operand
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4661 operand indIndex(eRegP reg, rRegI ireg) %{
0 a61af66fc99e Initial load duke parents: diff changeset	4662 match(AddP reg ireg);
a61af66fc99e Initial load duke parents: diff changeset	4663
a61af66fc99e Initial load duke parents: diff changeset	4664 op_cost(10);
a61af66fc99e Initial load duke parents: diff changeset	4665 format %{"[$reg + $ireg]" %}
a61af66fc99e Initial load duke parents: diff changeset	4666 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4667 base($reg);
a61af66fc99e Initial load duke parents: diff changeset	4668 index($ireg);
a61af66fc99e Initial load duke parents: diff changeset	4669 scale(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4670 disp(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4671 %}
a61af66fc99e Initial load duke parents: diff changeset	4672 %}
a61af66fc99e Initial load duke parents: diff changeset	4673
a61af66fc99e Initial load duke parents: diff changeset	4674 // // -------------------------------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	4675 // // 486 architecture doesn't support "scale * index + offset" with out a base
a61af66fc99e Initial load duke parents: diff changeset	4676 // // -------------------------------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	4677 // // Scaled Memory Operands
a61af66fc99e Initial load duke parents: diff changeset	4678 // // Indirect Memory Times Scale Plus Offset Operand
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4679 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
0 a61af66fc99e Initial load duke parents: diff changeset	4680 // match(AddP off (LShiftI ireg scale));
a61af66fc99e Initial load duke parents: diff changeset	4681 //
a61af66fc99e Initial load duke parents: diff changeset	4682 // op_cost(10);
a61af66fc99e Initial load duke parents: diff changeset	4683 // format %{"[$off + $ireg << $scale]" %}
a61af66fc99e Initial load duke parents: diff changeset	4684 // interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4685 // base(0x4);
a61af66fc99e Initial load duke parents: diff changeset	4686 // index($ireg);
a61af66fc99e Initial load duke parents: diff changeset	4687 // scale($scale);
a61af66fc99e Initial load duke parents: diff changeset	4688 // disp($off);
a61af66fc99e Initial load duke parents: diff changeset	4689 // %}
a61af66fc99e Initial load duke parents: diff changeset	4690 // %}
a61af66fc99e Initial load duke parents: diff changeset	4691
a61af66fc99e Initial load duke parents: diff changeset	4692 // Indirect Memory Times Scale Plus Index Register
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4693 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
0 a61af66fc99e Initial load duke parents: diff changeset	4694 match(AddP reg (LShiftI ireg scale));
a61af66fc99e Initial load duke parents: diff changeset	4695
a61af66fc99e Initial load duke parents: diff changeset	4696 op_cost(10);
a61af66fc99e Initial load duke parents: diff changeset	4697 format %{"[$reg + $ireg << $scale]" %}
a61af66fc99e Initial load duke parents: diff changeset	4698 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4699 base($reg);
a61af66fc99e Initial load duke parents: diff changeset	4700 index($ireg);
a61af66fc99e Initial load duke parents: diff changeset	4701 scale($scale);
a61af66fc99e Initial load duke parents: diff changeset	4702 disp(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4703 %}
a61af66fc99e Initial load duke parents: diff changeset	4704 %}
a61af66fc99e Initial load duke parents: diff changeset	4705
a61af66fc99e Initial load duke parents: diff changeset	4706 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4707 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
0 a61af66fc99e Initial load duke parents: diff changeset	4708 match(AddP (AddP reg (LShiftI ireg scale)) off);
a61af66fc99e Initial load duke parents: diff changeset	4709
a61af66fc99e Initial load duke parents: diff changeset	4710 op_cost(10);
a61af66fc99e Initial load duke parents: diff changeset	4711 format %{"[$reg + $off + $ireg << $scale]" %}
a61af66fc99e Initial load duke parents: diff changeset	4712 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4713 base($reg);
a61af66fc99e Initial load duke parents: diff changeset	4714 index($ireg);
a61af66fc99e Initial load duke parents: diff changeset	4715 scale($scale);
a61af66fc99e Initial load duke parents: diff changeset	4716 disp($off);
a61af66fc99e Initial load duke parents: diff changeset	4717 %}
a61af66fc99e Initial load duke parents: diff changeset	4718 %}
a61af66fc99e Initial load duke parents: diff changeset	4719
a61af66fc99e Initial load duke parents: diff changeset	4720 //----------Load Long Memory Operands------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	4721 // The load-long idiom will use it's address expression again after loading
a61af66fc99e Initial load duke parents: diff changeset	4722 // the first word of the long. If the load-long destination overlaps with
a61af66fc99e Initial load duke parents: diff changeset	4723 // registers used in the addressing expression, the 2nd half will be loaded
a61af66fc99e Initial load duke parents: diff changeset	4724 // from a clobbered address. Fix this by requiring that load-long use
a61af66fc99e Initial load duke parents: diff changeset	4725 // address registers that do not overlap with the load-long target.
a61af66fc99e Initial load duke parents: diff changeset	4726
a61af66fc99e Initial load duke parents: diff changeset	4727 // load-long support
a61af66fc99e Initial load duke parents: diff changeset	4728 operand load_long_RegP() %{
a61af66fc99e Initial load duke parents: diff changeset	4729 constraint(ALLOC_IN_RC(esi_reg));
a61af66fc99e Initial load duke parents: diff changeset	4730 match(RegP);
a61af66fc99e Initial load duke parents: diff changeset	4731 match(eSIRegP);
a61af66fc99e Initial load duke parents: diff changeset	4732 op_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	4733 format %{ %}
a61af66fc99e Initial load duke parents: diff changeset	4734 interface(REG_INTER);
a61af66fc99e Initial load duke parents: diff changeset	4735 %}
a61af66fc99e Initial load duke parents: diff changeset	4736
a61af66fc99e Initial load duke parents: diff changeset	4737 // Indirect Memory Operand Long
a61af66fc99e Initial load duke parents: diff changeset	4738 operand load_long_indirect(load_long_RegP reg) %{
a61af66fc99e Initial load duke parents: diff changeset	4739 constraint(ALLOC_IN_RC(esi_reg));
a61af66fc99e Initial load duke parents: diff changeset	4740 match(reg);
a61af66fc99e Initial load duke parents: diff changeset	4741
a61af66fc99e Initial load duke parents: diff changeset	4742 format %{ "[$reg]" %}
a61af66fc99e Initial load duke parents: diff changeset	4743 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4744 base($reg);
a61af66fc99e Initial load duke parents: diff changeset	4745 index(0x4);
a61af66fc99e Initial load duke parents: diff changeset	4746 scale(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4747 disp(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4748 %}
a61af66fc99e Initial load duke parents: diff changeset	4749 %}
a61af66fc99e Initial load duke parents: diff changeset	4750
a61af66fc99e Initial load duke parents: diff changeset	4751 // Indirect Memory Plus Long Offset Operand
a61af66fc99e Initial load duke parents: diff changeset	4752 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
a61af66fc99e Initial load duke parents: diff changeset	4753 match(AddP reg off);
a61af66fc99e Initial load duke parents: diff changeset	4754
a61af66fc99e Initial load duke parents: diff changeset	4755 format %{ "[$reg + $off]" %}
a61af66fc99e Initial load duke parents: diff changeset	4756 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4757 base($reg);
a61af66fc99e Initial load duke parents: diff changeset	4758 index(0x4);
a61af66fc99e Initial load duke parents: diff changeset	4759 scale(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4760 disp($off);
a61af66fc99e Initial load duke parents: diff changeset	4761 %}
a61af66fc99e Initial load duke parents: diff changeset	4762 %}
a61af66fc99e Initial load duke parents: diff changeset	4763
a61af66fc99e Initial load duke parents: diff changeset	4764 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
a61af66fc99e Initial load duke parents: diff changeset	4765
a61af66fc99e Initial load duke parents: diff changeset	4766
a61af66fc99e Initial load duke parents: diff changeset	4767 //----------Special Memory Operands--------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	4768 // Stack Slot Operand - This operand is used for loading and storing temporary
a61af66fc99e Initial load duke parents: diff changeset	4769 // values on the stack where a match requires a value to
a61af66fc99e Initial load duke parents: diff changeset	4770 // flow through memory.
a61af66fc99e Initial load duke parents: diff changeset	4771 operand stackSlotP(sRegP reg) %{
a61af66fc99e Initial load duke parents: diff changeset	4772 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load duke parents: diff changeset	4773 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load duke parents: diff changeset	4774 format %{ "[$reg]" %}
a61af66fc99e Initial load duke parents: diff changeset	4775 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4776 base(0x4); // ESP
a61af66fc99e Initial load duke parents: diff changeset	4777 index(0x4); // No Index
a61af66fc99e Initial load duke parents: diff changeset	4778 scale(0x0); // No Scale
a61af66fc99e Initial load duke parents: diff changeset	4779 disp($reg); // Stack Offset
a61af66fc99e Initial load duke parents: diff changeset	4780 %}
a61af66fc99e Initial load duke parents: diff changeset	4781 %}
a61af66fc99e Initial load duke parents: diff changeset	4782
a61af66fc99e Initial load duke parents: diff changeset	4783 operand stackSlotI(sRegI reg) %{
a61af66fc99e Initial load duke parents: diff changeset	4784 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load duke parents: diff changeset	4785 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load duke parents: diff changeset	4786 format %{ "[$reg]" %}
a61af66fc99e Initial load duke parents: diff changeset	4787 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4788 base(0x4); // ESP
a61af66fc99e Initial load duke parents: diff changeset	4789 index(0x4); // No Index
a61af66fc99e Initial load duke parents: diff changeset	4790 scale(0x0); // No Scale
a61af66fc99e Initial load duke parents: diff changeset	4791 disp($reg); // Stack Offset
a61af66fc99e Initial load duke parents: diff changeset	4792 %}
a61af66fc99e Initial load duke parents: diff changeset	4793 %}
a61af66fc99e Initial load duke parents: diff changeset	4794
a61af66fc99e Initial load duke parents: diff changeset	4795 operand stackSlotF(sRegF reg) %{
a61af66fc99e Initial load duke parents: diff changeset	4796 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load duke parents: diff changeset	4797 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load duke parents: diff changeset	4798 format %{ "[$reg]" %}
a61af66fc99e Initial load duke parents: diff changeset	4799 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4800 base(0x4); // ESP
a61af66fc99e Initial load duke parents: diff changeset	4801 index(0x4); // No Index
a61af66fc99e Initial load duke parents: diff changeset	4802 scale(0x0); // No Scale
a61af66fc99e Initial load duke parents: diff changeset	4803 disp($reg); // Stack Offset
a61af66fc99e Initial load duke parents: diff changeset	4804 %}
a61af66fc99e Initial load duke parents: diff changeset	4805 %}
a61af66fc99e Initial load duke parents: diff changeset	4806
a61af66fc99e Initial load duke parents: diff changeset	4807 operand stackSlotD(sRegD reg) %{
a61af66fc99e Initial load duke parents: diff changeset	4808 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load duke parents: diff changeset	4809 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load duke parents: diff changeset	4810 format %{ "[$reg]" %}
a61af66fc99e Initial load duke parents: diff changeset	4811 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4812 base(0x4); // ESP
a61af66fc99e Initial load duke parents: diff changeset	4813 index(0x4); // No Index
a61af66fc99e Initial load duke parents: diff changeset	4814 scale(0x0); // No Scale
a61af66fc99e Initial load duke parents: diff changeset	4815 disp($reg); // Stack Offset
a61af66fc99e Initial load duke parents: diff changeset	4816 %}
a61af66fc99e Initial load duke parents: diff changeset	4817 %}
a61af66fc99e Initial load duke parents: diff changeset	4818
a61af66fc99e Initial load duke parents: diff changeset	4819 operand stackSlotL(sRegL reg) %{
a61af66fc99e Initial load duke parents: diff changeset	4820 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load duke parents: diff changeset	4821 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load duke parents: diff changeset	4822 format %{ "[$reg]" %}
a61af66fc99e Initial load duke parents: diff changeset	4823 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4824 base(0x4); // ESP
a61af66fc99e Initial load duke parents: diff changeset	4825 index(0x4); // No Index
a61af66fc99e Initial load duke parents: diff changeset	4826 scale(0x0); // No Scale
a61af66fc99e Initial load duke parents: diff changeset	4827 disp($reg); // Stack Offset
a61af66fc99e Initial load duke parents: diff changeset	4828 %}
a61af66fc99e Initial load duke parents: diff changeset	4829 %}
a61af66fc99e Initial load duke parents: diff changeset	4830
a61af66fc99e Initial load duke parents: diff changeset	4831 //----------Memory Operands - Win95 Implicit Null Variants----------------
a61af66fc99e Initial load duke parents: diff changeset	4832 // Indirect Memory Operand
a61af66fc99e Initial load duke parents: diff changeset	4833 operand indirect_win95_safe(eRegP_no_EBP reg)
a61af66fc99e Initial load duke parents: diff changeset	4834 %{
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4835 constraint(ALLOC_IN_RC(int_reg));
0 a61af66fc99e Initial load duke parents: diff changeset	4836 match(reg);
a61af66fc99e Initial load duke parents: diff changeset	4837
a61af66fc99e Initial load duke parents: diff changeset	4838 op_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	4839 format %{ "[$reg]" %}
a61af66fc99e Initial load duke parents: diff changeset	4840 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4841 base($reg);
a61af66fc99e Initial load duke parents: diff changeset	4842 index(0x4);
a61af66fc99e Initial load duke parents: diff changeset	4843 scale(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4844 disp(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4845 %}
a61af66fc99e Initial load duke parents: diff changeset	4846 %}
a61af66fc99e Initial load duke parents: diff changeset	4847
a61af66fc99e Initial load duke parents: diff changeset	4848 // Indirect Memory Plus Short Offset Operand
a61af66fc99e Initial load duke parents: diff changeset	4849 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
a61af66fc99e Initial load duke parents: diff changeset	4850 %{
a61af66fc99e Initial load duke parents: diff changeset	4851 match(AddP reg off);
a61af66fc99e Initial load duke parents: diff changeset	4852
a61af66fc99e Initial load duke parents: diff changeset	4853 op_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	4854 format %{ "[$reg + $off]" %}
a61af66fc99e Initial load duke parents: diff changeset	4855 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4856 base($reg);
a61af66fc99e Initial load duke parents: diff changeset	4857 index(0x4);
a61af66fc99e Initial load duke parents: diff changeset	4858 scale(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4859 disp($off);
a61af66fc99e Initial load duke parents: diff changeset	4860 %}
a61af66fc99e Initial load duke parents: diff changeset	4861 %}
a61af66fc99e Initial load duke parents: diff changeset	4862
a61af66fc99e Initial load duke parents: diff changeset	4863 // Indirect Memory Plus Long Offset Operand
a61af66fc99e Initial load duke parents: diff changeset	4864 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
a61af66fc99e Initial load duke parents: diff changeset	4865 %{
a61af66fc99e Initial load duke parents: diff changeset	4866 match(AddP reg off);
a61af66fc99e Initial load duke parents: diff changeset	4867
a61af66fc99e Initial load duke parents: diff changeset	4868 op_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	4869 format %{ "[$reg + $off]" %}
a61af66fc99e Initial load duke parents: diff changeset	4870 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4871 base($reg);
a61af66fc99e Initial load duke parents: diff changeset	4872 index(0x4);
a61af66fc99e Initial load duke parents: diff changeset	4873 scale(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4874 disp($off);
a61af66fc99e Initial load duke parents: diff changeset	4875 %}
a61af66fc99e Initial load duke parents: diff changeset	4876 %}
a61af66fc99e Initial load duke parents: diff changeset	4877
a61af66fc99e Initial load duke parents: diff changeset	4878 // Indirect Memory Plus Index Register Plus Offset Operand
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4879 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
0 a61af66fc99e Initial load duke parents: diff changeset	4880 %{
a61af66fc99e Initial load duke parents: diff changeset	4881 match(AddP (AddP reg ireg) off);
a61af66fc99e Initial load duke parents: diff changeset	4882
a61af66fc99e Initial load duke parents: diff changeset	4883 op_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	4884 format %{"[$reg + $off + $ireg]" %}
a61af66fc99e Initial load duke parents: diff changeset	4885 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4886 base($reg);
a61af66fc99e Initial load duke parents: diff changeset	4887 index($ireg);
a61af66fc99e Initial load duke parents: diff changeset	4888 scale(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4889 disp($off);
a61af66fc99e Initial load duke parents: diff changeset	4890 %}
a61af66fc99e Initial load duke parents: diff changeset	4891 %}
a61af66fc99e Initial load duke parents: diff changeset	4892
a61af66fc99e Initial load duke parents: diff changeset	4893 // Indirect Memory Times Scale Plus Index Register
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4894 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
0 a61af66fc99e Initial load duke parents: diff changeset	4895 %{
a61af66fc99e Initial load duke parents: diff changeset	4896 match(AddP reg (LShiftI ireg scale));
a61af66fc99e Initial load duke parents: diff changeset	4897
a61af66fc99e Initial load duke parents: diff changeset	4898 op_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	4899 format %{"[$reg + $ireg << $scale]" %}
a61af66fc99e Initial load duke parents: diff changeset	4900 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4901 base($reg);
a61af66fc99e Initial load duke parents: diff changeset	4902 index($ireg);
a61af66fc99e Initial load duke parents: diff changeset	4903 scale($scale);
a61af66fc99e Initial load duke parents: diff changeset	4904 disp(0x0);
a61af66fc99e Initial load duke parents: diff changeset	4905 %}
a61af66fc99e Initial load duke parents: diff changeset	4906 %}
a61af66fc99e Initial load duke parents: diff changeset	4907
a61af66fc99e Initial load duke parents: diff changeset	4908 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	4909 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
0 a61af66fc99e Initial load duke parents: diff changeset	4910 %{
a61af66fc99e Initial load duke parents: diff changeset	4911 match(AddP (AddP reg (LShiftI ireg scale)) off);
a61af66fc99e Initial load duke parents: diff changeset	4912
a61af66fc99e Initial load duke parents: diff changeset	4913 op_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	4914 format %{"[$reg + $off + $ireg << $scale]" %}
a61af66fc99e Initial load duke parents: diff changeset	4915 interface(MEMORY_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	4916 base($reg);
a61af66fc99e Initial load duke parents: diff changeset	4917 index($ireg);
a61af66fc99e Initial load duke parents: diff changeset	4918 scale($scale);
a61af66fc99e Initial load duke parents: diff changeset	4919 disp($off);
a61af66fc99e Initial load duke parents: diff changeset	4920 %}
a61af66fc99e Initial load duke parents: diff changeset	4921 %}
a61af66fc99e Initial load duke parents: diff changeset	4922
a61af66fc99e Initial load duke parents: diff changeset	4923 //----------Conditional Branch Operands----------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	4924 // Comparison Op - This is the operation of the comparison, and is limited to
a61af66fc99e Initial load duke parents: diff changeset	4925 // the following set of codes:
a61af66fc99e Initial load duke parents: diff changeset	4926 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
a61af66fc99e Initial load duke parents: diff changeset	4927 //
a61af66fc99e Initial load duke parents: diff changeset	4928 // Other attributes of the comparison, such as unsignedness, are specified
a61af66fc99e Initial load duke parents: diff changeset	4929 // by the comparison instruction that sets a condition code flags register.
a61af66fc99e Initial load duke parents: diff changeset	4930 // That result is represented by a flags operand whose subtype is appropriate
a61af66fc99e Initial load duke parents: diff changeset	4931 // to the unsignedness (etc.) of the comparison.
a61af66fc99e Initial load duke parents: diff changeset	4932 //
a61af66fc99e Initial load duke parents: diff changeset	4933 // Later, the instruction which matches both the Comparison Op (a Bool) and
a61af66fc99e Initial load duke parents: diff changeset	4934 // the flags (produced by the Cmp) specifies the coding of the comparison op
a61af66fc99e Initial load duke parents: diff changeset	4935 // by matching a specific subtype of Bool operand below, such as cmpOpU.
a61af66fc99e Initial load duke parents: diff changeset	4936
a61af66fc99e Initial load duke parents: diff changeset	4937 // Comparision Code
a61af66fc99e Initial load duke parents: diff changeset	4938 operand cmpOp() %{
a61af66fc99e Initial load duke parents: diff changeset	4939 match(Bool);
a61af66fc99e Initial load duke parents: diff changeset	4940
a61af66fc99e Initial load duke parents: diff changeset	4941 format %{ "" %}
a61af66fc99e Initial load duke parents: diff changeset	4942 interface(COND_INTER) %{
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4943 equal(0x4, "e");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4944 not_equal(0x5, "ne");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4945 less(0xC, "l");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4946 greater_equal(0xD, "ge");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4947 less_equal(0xE, "le");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4948 greater(0xF, "g");
12323 c9ccd7b85f20 8024924: Intrinsify java.lang.Math.addExact rbackman parents: 10169 diff changeset	4949 overflow(0x0, "o");
c9ccd7b85f20 8024924: Intrinsify java.lang.Math.addExact rbackman parents: 10169 diff changeset	4950 no_overflow(0x1, "no");
0 a61af66fc99e Initial load duke parents: diff changeset	4951 %}
a61af66fc99e Initial load duke parents: diff changeset	4952 %}
a61af66fc99e Initial load duke parents: diff changeset	4953
a61af66fc99e Initial load duke parents: diff changeset	4954 // Comparison Code, unsigned compare. Used by FP also, with
a61af66fc99e Initial load duke parents: diff changeset	4955 // C2 (unordered) turned into GT or LT already. The other bits
a61af66fc99e Initial load duke parents: diff changeset	4956 // C0 and C3 are turned into Carry & Zero flags.
a61af66fc99e Initial load duke parents: diff changeset	4957 operand cmpOpU() %{
a61af66fc99e Initial load duke parents: diff changeset	4958 match(Bool);
a61af66fc99e Initial load duke parents: diff changeset	4959
a61af66fc99e Initial load duke parents: diff changeset	4960 format %{ "" %}
a61af66fc99e Initial load duke parents: diff changeset	4961 interface(COND_INTER) %{
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4962 equal(0x4, "e");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4963 not_equal(0x5, "ne");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4964 less(0x2, "b");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4965 greater_equal(0x3, "nb");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4966 less_equal(0x6, "be");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4967 greater(0x7, "nbe");
12323 c9ccd7b85f20 8024924: Intrinsify java.lang.Math.addExact rbackman parents: 10169 diff changeset	4968 overflow(0x0, "o");
c9ccd7b85f20 8024924: Intrinsify java.lang.Math.addExact rbackman parents: 10169 diff changeset	4969 no_overflow(0x1, "no");
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4970 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4971 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4972
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4973 // Floating comparisons that don't require any fixup for the unordered case
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4974 operand cmpOpUCF() %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4975 match(Bool);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4976 predicate(n->as_Bool()->_test._test == BoolTest::lt \|\|
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4977 n->as_Bool()->_test._test == BoolTest::ge \|\|
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4978 n->as_Bool()->_test._test == BoolTest::le \|\|
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4979 n->as_Bool()->_test._test == BoolTest::gt);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4980 format %{ "" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4981 interface(COND_INTER) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4982 equal(0x4, "e");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4983 not_equal(0x5, "ne");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4984 less(0x2, "b");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4985 greater_equal(0x3, "nb");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4986 less_equal(0x6, "be");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4987 greater(0x7, "nbe");
12323 c9ccd7b85f20 8024924: Intrinsify java.lang.Math.addExact rbackman parents: 10169 diff changeset	4988 overflow(0x0, "o");
c9ccd7b85f20 8024924: Intrinsify java.lang.Math.addExact rbackman parents: 10169 diff changeset	4989 no_overflow(0x1, "no");
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4990 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4991 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4992
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4993
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4994 // Floating comparisons that can be fixed up with extra conditional jumps
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4995 operand cmpOpUCF2() %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4996 match(Bool);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4997 predicate(n->as_Bool()->_test._test == BoolTest::ne \|\|
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4998 n->as_Bool()->_test._test == BoolTest::eq);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	4999 format %{ "" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	5000 interface(COND_INTER) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	5001 equal(0x4, "e");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	5002 not_equal(0x5, "ne");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	5003 less(0x2, "b");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	5004 greater_equal(0x3, "nb");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	5005 less_equal(0x6, "be");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	5006 greater(0x7, "nbe");
12323 c9ccd7b85f20 8024924: Intrinsify java.lang.Math.addExact rbackman parents: 10169 diff changeset	5007 overflow(0x0, "o");
c9ccd7b85f20 8024924: Intrinsify java.lang.Math.addExact rbackman parents: 10169 diff changeset	5008 no_overflow(0x1, "no");
0 a61af66fc99e Initial load duke parents: diff changeset	5009 %}
a61af66fc99e Initial load duke parents: diff changeset	5010 %}
a61af66fc99e Initial load duke parents: diff changeset	5011
a61af66fc99e Initial load duke parents: diff changeset	5012 // Comparison Code for FP conditional move
a61af66fc99e Initial load duke parents: diff changeset	5013 operand cmpOp_fcmov() %{
a61af66fc99e Initial load duke parents: diff changeset	5014 match(Bool);
a61af66fc99e Initial load duke parents: diff changeset	5015
12323 c9ccd7b85f20 8024924: Intrinsify java.lang.Math.addExact rbackman parents: 10169 diff changeset	5016 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
c9ccd7b85f20 8024924: Intrinsify java.lang.Math.addExact rbackman parents: 10169 diff changeset	5017 n->as_Bool()->_test._test != BoolTest::no_overflow);
0 a61af66fc99e Initial load duke parents: diff changeset	5018 format %{ "" %}
a61af66fc99e Initial load duke parents: diff changeset	5019 interface(COND_INTER) %{
a61af66fc99e Initial load duke parents: diff changeset	5020 equal (0x0C8);
a61af66fc99e Initial load duke parents: diff changeset	5021 not_equal (0x1C8);
a61af66fc99e Initial load duke parents: diff changeset	5022 less (0x0C0);
a61af66fc99e Initial load duke parents: diff changeset	5023 greater_equal(0x1C0);
a61af66fc99e Initial load duke parents: diff changeset	5024 less_equal (0x0D0);
a61af66fc99e Initial load duke parents: diff changeset	5025 greater (0x1D0);
12323 c9ccd7b85f20 8024924: Intrinsify java.lang.Math.addExact rbackman parents: 10169 diff changeset	5026 overflow(0x0, "o"); // not really supported by the instruction
c9ccd7b85f20 8024924: Intrinsify java.lang.Math.addExact rbackman parents: 10169 diff changeset	5027 no_overflow(0x1, "no"); // not really supported by the instruction
0 a61af66fc99e Initial load duke parents: diff changeset	5028 %}
a61af66fc99e Initial load duke parents: diff changeset	5029 %}
a61af66fc99e Initial load duke parents: diff changeset	5030
a61af66fc99e Initial load duke parents: diff changeset	5031 // Comparision Code used in long compares
a61af66fc99e Initial load duke parents: diff changeset	5032 operand cmpOp_commute() %{
a61af66fc99e Initial load duke parents: diff changeset	5033 match(Bool);
a61af66fc99e Initial load duke parents: diff changeset	5034
a61af66fc99e Initial load duke parents: diff changeset	5035 format %{ "" %}
a61af66fc99e Initial load duke parents: diff changeset	5036 interface(COND_INTER) %{
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	5037 equal(0x4, "e");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	5038 not_equal(0x5, "ne");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	5039 less(0xF, "g");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	5040 greater_equal(0xE, "le");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	5041 less_equal(0xD, "ge");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	5042 greater(0xC, "l");
12323 c9ccd7b85f20 8024924: Intrinsify java.lang.Math.addExact rbackman parents: 10169 diff changeset	5043 overflow(0x0, "o");
c9ccd7b85f20 8024924: Intrinsify java.lang.Math.addExact rbackman parents: 10169 diff changeset	5044 no_overflow(0x1, "no");
0 a61af66fc99e Initial load duke parents: diff changeset	5045 %}
a61af66fc99e Initial load duke parents: diff changeset	5046 %}
a61af66fc99e Initial load duke parents: diff changeset	5047
a61af66fc99e Initial load duke parents: diff changeset	5048 //----------OPERAND CLASSES----------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	5049 // Operand Classes are groups of operands that are used as to simplify
605 98cb887364d3 6810672: Comment typos twisti parents: 570 diff changeset	5050 // instruction definitions by not requiring the AD writer to specify separate
0 a61af66fc99e Initial load duke parents: diff changeset	5051 // instructions for every form of operand when the instruction accepts
a61af66fc99e Initial load duke parents: diff changeset	5052 // multiple operand types with the same basic encoding and format. The classic
a61af66fc99e Initial load duke parents: diff changeset	5053 // case of this is memory operands.
a61af66fc99e Initial load duke parents: diff changeset	5054
a61af66fc99e Initial load duke parents: diff changeset	5055 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
a61af66fc99e Initial load duke parents: diff changeset	5056 indIndex, indIndexScale, indIndexScaleOffset);
a61af66fc99e Initial load duke parents: diff changeset	5057
a61af66fc99e Initial load duke parents: diff changeset	5058 // Long memory operations are encoded in 2 instructions and a +4 offset.
a61af66fc99e Initial load duke parents: diff changeset	5059 // This means some kind of offset is always required and you cannot use
a61af66fc99e Initial load duke parents: diff changeset	5060 // an oop as the offset (done when working on static globals).
a61af66fc99e Initial load duke parents: diff changeset	5061 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
a61af66fc99e Initial load duke parents: diff changeset	5062 indIndex, indIndexScale, indIndexScaleOffset);
a61af66fc99e Initial load duke parents: diff changeset	5063
a61af66fc99e Initial load duke parents: diff changeset	5064
a61af66fc99e Initial load duke parents: diff changeset	5065 //----------PIPELINE-----------------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	5066 // Rules which define the behavior of the target architectures pipeline.
a61af66fc99e Initial load duke parents: diff changeset	5067 pipeline %{
a61af66fc99e Initial load duke parents: diff changeset	5068
a61af66fc99e Initial load duke parents: diff changeset	5069 //----------ATTRIBUTES---------------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	5070 attributes %{
a61af66fc99e Initial load duke parents: diff changeset	5071 variable_size_instructions; // Fixed size instructions
a61af66fc99e Initial load duke parents: diff changeset	5072 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
a61af66fc99e Initial load duke parents: diff changeset	5073 instruction_unit_size = 1; // An instruction is 1 bytes long
a61af66fc99e Initial load duke parents: diff changeset	5074 instruction_fetch_unit_size = 16; // The processor fetches one line
a61af66fc99e Initial load duke parents: diff changeset	5075 instruction_fetch_units = 1; // of 16 bytes
a61af66fc99e Initial load duke parents: diff changeset	5076
a61af66fc99e Initial load duke parents: diff changeset	5077 // List of nop instructions
a61af66fc99e Initial load duke parents: diff changeset	5078 nops( MachNop );
a61af66fc99e Initial load duke parents: diff changeset	5079 %}
a61af66fc99e Initial load duke parents: diff changeset	5080
a61af66fc99e Initial load duke parents: diff changeset	5081 //----------RESOURCES----------------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	5082 // Resources are the functional units available to the machine
a61af66fc99e Initial load duke parents: diff changeset	5083
a61af66fc99e Initial load duke parents: diff changeset	5084 // Generic P2/P3 pipeline
a61af66fc99e Initial load duke parents: diff changeset	5085 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
a61af66fc99e Initial load duke parents: diff changeset	5086 // 3 instructions decoded per cycle.
a61af66fc99e Initial load duke parents: diff changeset	5087 // 2 load/store ops per cycle, 1 branch, 1 FPU,
a61af66fc99e Initial load duke parents: diff changeset	5088 // 2 ALU op, only ALU0 handles mul/div instructions.
a61af66fc99e Initial load duke parents: diff changeset	5089 resources( D0, D1, D2, DECODE = D0 \| D1 \| D2,
a61af66fc99e Initial load duke parents: diff changeset	5090 MS0, MS1, MEM = MS0 \| MS1,
a61af66fc99e Initial load duke parents: diff changeset	5091 BR, FPU,
a61af66fc99e Initial load duke parents: diff changeset	5092 ALU0, ALU1, ALU = ALU0 \| ALU1 );
a61af66fc99e Initial load duke parents: diff changeset	5093
a61af66fc99e Initial load duke parents: diff changeset	5094 //----------PIPELINE DESCRIPTION-----------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	5095 // Pipeline Description specifies the stages in the machine's pipeline
a61af66fc99e Initial load duke parents: diff changeset	5096
a61af66fc99e Initial load duke parents: diff changeset	5097 // Generic P2/P3 pipeline
a61af66fc99e Initial load duke parents: diff changeset	5098 pipe_desc(S0, S1, S2, S3, S4, S5);
a61af66fc99e Initial load duke parents: diff changeset	5099
a61af66fc99e Initial load duke parents: diff changeset	5100 //----------PIPELINE CLASSES---------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	5101 // Pipeline Classes describe the stages in which input and output are
a61af66fc99e Initial load duke parents: diff changeset	5102 // referenced by the hardware pipeline.
a61af66fc99e Initial load duke parents: diff changeset	5103
a61af66fc99e Initial load duke parents: diff changeset	5104 // Naming convention: ialu or fpu
a61af66fc99e Initial load duke parents: diff changeset	5105 // Then: _reg
a61af66fc99e Initial load duke parents: diff changeset	5106 // Then: _reg if there is a 2nd register
a61af66fc99e Initial load duke parents: diff changeset	5107 // Then: _long if it's a pair of instructions implementing a long
a61af66fc99e Initial load duke parents: diff changeset	5108 // Then: _fat if it requires the big decoder
a61af66fc99e Initial load duke parents: diff changeset	5109 // Or: _mem if it requires the big decoder and a memory unit.
a61af66fc99e Initial load duke parents: diff changeset	5110
a61af66fc99e Initial load duke parents: diff changeset	5111 // Integer ALU reg operation
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5112 pipe_class ialu_reg(rRegI dst) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5113 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5114 dst : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5115 dst : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5116 DECODE : S0; // any decoder
a61af66fc99e Initial load duke parents: diff changeset	5117 ALU : S3; // any alu
a61af66fc99e Initial load duke parents: diff changeset	5118 %}
a61af66fc99e Initial load duke parents: diff changeset	5119
a61af66fc99e Initial load duke parents: diff changeset	5120 // Long ALU reg operation
a61af66fc99e Initial load duke parents: diff changeset	5121 pipe_class ialu_reg_long(eRegL dst) %{
a61af66fc99e Initial load duke parents: diff changeset	5122 instruction_count(2);
a61af66fc99e Initial load duke parents: diff changeset	5123 dst : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5124 dst : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5125 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load duke parents: diff changeset	5126 ALU : S3(2); // both alus
a61af66fc99e Initial load duke parents: diff changeset	5127 %}
a61af66fc99e Initial load duke parents: diff changeset	5128
a61af66fc99e Initial load duke parents: diff changeset	5129 // Integer ALU reg operation using big decoder
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5130 pipe_class ialu_reg_fat(rRegI dst) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5131 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5132 dst : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5133 dst : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5134 D0 : S0; // big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5135 ALU : S3; // any alu
a61af66fc99e Initial load duke parents: diff changeset	5136 %}
a61af66fc99e Initial load duke parents: diff changeset	5137
a61af66fc99e Initial load duke parents: diff changeset	5138 // Long ALU reg operation using big decoder
a61af66fc99e Initial load duke parents: diff changeset	5139 pipe_class ialu_reg_long_fat(eRegL dst) %{
a61af66fc99e Initial load duke parents: diff changeset	5140 instruction_count(2);
a61af66fc99e Initial load duke parents: diff changeset	5141 dst : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5142 dst : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5143 D0 : S0(2); // big decoder only; twice
a61af66fc99e Initial load duke parents: diff changeset	5144 ALU : S3(2); // any 2 alus
a61af66fc99e Initial load duke parents: diff changeset	5145 %}
a61af66fc99e Initial load duke parents: diff changeset	5146
a61af66fc99e Initial load duke parents: diff changeset	5147 // Integer ALU reg-reg operation
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5148 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5149 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5150 dst : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5151 src : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5152 DECODE : S0; // any decoder
a61af66fc99e Initial load duke parents: diff changeset	5153 ALU : S3; // any alu
a61af66fc99e Initial load duke parents: diff changeset	5154 %}
a61af66fc99e Initial load duke parents: diff changeset	5155
a61af66fc99e Initial load duke parents: diff changeset	5156 // Long ALU reg-reg operation
a61af66fc99e Initial load duke parents: diff changeset	5157 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
a61af66fc99e Initial load duke parents: diff changeset	5158 instruction_count(2);
a61af66fc99e Initial load duke parents: diff changeset	5159 dst : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5160 src : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5161 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load duke parents: diff changeset	5162 ALU : S3(2); // both alus
a61af66fc99e Initial load duke parents: diff changeset	5163 %}
a61af66fc99e Initial load duke parents: diff changeset	5164
a61af66fc99e Initial load duke parents: diff changeset	5165 // Integer ALU reg-reg operation
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5166 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5167 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5168 dst : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5169 src : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5170 D0 : S0; // big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5171 ALU : S3; // any alu
a61af66fc99e Initial load duke parents: diff changeset	5172 %}
a61af66fc99e Initial load duke parents: diff changeset	5173
a61af66fc99e Initial load duke parents: diff changeset	5174 // Long ALU reg-reg operation
a61af66fc99e Initial load duke parents: diff changeset	5175 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
a61af66fc99e Initial load duke parents: diff changeset	5176 instruction_count(2);
a61af66fc99e Initial load duke parents: diff changeset	5177 dst : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5178 src : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5179 D0 : S0(2); // big decoder only; twice
a61af66fc99e Initial load duke parents: diff changeset	5180 ALU : S3(2); // both alus
a61af66fc99e Initial load duke parents: diff changeset	5181 %}
a61af66fc99e Initial load duke parents: diff changeset	5182
a61af66fc99e Initial load duke parents: diff changeset	5183 // Integer ALU reg-mem operation
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5184 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5185 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5186 dst : S5(write);
a61af66fc99e Initial load duke parents: diff changeset	5187 mem : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5188 D0 : S0; // big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5189 ALU : S4; // any alu
a61af66fc99e Initial load duke parents: diff changeset	5190 MEM : S3; // any mem
a61af66fc99e Initial load duke parents: diff changeset	5191 %}
a61af66fc99e Initial load duke parents: diff changeset	5192
a61af66fc99e Initial load duke parents: diff changeset	5193 // Long ALU reg-mem operation
a61af66fc99e Initial load duke parents: diff changeset	5194 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
a61af66fc99e Initial load duke parents: diff changeset	5195 instruction_count(2);
a61af66fc99e Initial load duke parents: diff changeset	5196 dst : S5(write);
a61af66fc99e Initial load duke parents: diff changeset	5197 mem : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5198 D0 : S0(2); // big decoder only; twice
a61af66fc99e Initial load duke parents: diff changeset	5199 ALU : S4(2); // any 2 alus
a61af66fc99e Initial load duke parents: diff changeset	5200 MEM : S3(2); // both mems
a61af66fc99e Initial load duke parents: diff changeset	5201 %}
a61af66fc99e Initial load duke parents: diff changeset	5202
a61af66fc99e Initial load duke parents: diff changeset	5203 // Integer mem operation (prefetch)
a61af66fc99e Initial load duke parents: diff changeset	5204 pipe_class ialu_mem(memory mem)
a61af66fc99e Initial load duke parents: diff changeset	5205 %{
a61af66fc99e Initial load duke parents: diff changeset	5206 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5207 mem : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5208 D0 : S0; // big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5209 MEM : S3; // any mem
a61af66fc99e Initial load duke parents: diff changeset	5210 %}
a61af66fc99e Initial load duke parents: diff changeset	5211
a61af66fc99e Initial load duke parents: diff changeset	5212 // Integer Store to Memory
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5213 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5214 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5215 mem : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5216 src : S5(read);
a61af66fc99e Initial load duke parents: diff changeset	5217 D0 : S0; // big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5218 ALU : S4; // any alu
a61af66fc99e Initial load duke parents: diff changeset	5219 MEM : S3;
a61af66fc99e Initial load duke parents: diff changeset	5220 %}
a61af66fc99e Initial load duke parents: diff changeset	5221
a61af66fc99e Initial load duke parents: diff changeset	5222 // Long Store to Memory
a61af66fc99e Initial load duke parents: diff changeset	5223 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
a61af66fc99e Initial load duke parents: diff changeset	5224 instruction_count(2);
a61af66fc99e Initial load duke parents: diff changeset	5225 mem : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5226 src : S5(read);
a61af66fc99e Initial load duke parents: diff changeset	5227 D0 : S0(2); // big decoder only; twice
a61af66fc99e Initial load duke parents: diff changeset	5228 ALU : S4(2); // any 2 alus
a61af66fc99e Initial load duke parents: diff changeset	5229 MEM : S3(2); // Both mems
a61af66fc99e Initial load duke parents: diff changeset	5230 %}
a61af66fc99e Initial load duke parents: diff changeset	5231
a61af66fc99e Initial load duke parents: diff changeset	5232 // Integer Store to Memory
a61af66fc99e Initial load duke parents: diff changeset	5233 pipe_class ialu_mem_imm(memory mem) %{
a61af66fc99e Initial load duke parents: diff changeset	5234 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5235 mem : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5236 D0 : S0; // big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5237 ALU : S4; // any alu
a61af66fc99e Initial load duke parents: diff changeset	5238 MEM : S3;
a61af66fc99e Initial load duke parents: diff changeset	5239 %}
a61af66fc99e Initial load duke parents: diff changeset	5240
a61af66fc99e Initial load duke parents: diff changeset	5241 // Integer ALU0 reg-reg operation
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5242 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5243 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5244 dst : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5245 src : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5246 D0 : S0; // Big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5247 ALU0 : S3; // only alu0
a61af66fc99e Initial load duke parents: diff changeset	5248 %}
a61af66fc99e Initial load duke parents: diff changeset	5249
a61af66fc99e Initial load duke parents: diff changeset	5250 // Integer ALU0 reg-mem operation
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5251 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5252 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5253 dst : S5(write);
a61af66fc99e Initial load duke parents: diff changeset	5254 mem : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5255 D0 : S0; // big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5256 ALU0 : S4; // ALU0 only
a61af66fc99e Initial load duke parents: diff changeset	5257 MEM : S3; // any mem
a61af66fc99e Initial load duke parents: diff changeset	5258 %}
a61af66fc99e Initial load duke parents: diff changeset	5259
a61af66fc99e Initial load duke parents: diff changeset	5260 // Integer ALU reg-reg operation
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5261 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5262 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5263 cr : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5264 src1 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5265 src2 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5266 DECODE : S0; // any decoder
a61af66fc99e Initial load duke parents: diff changeset	5267 ALU : S3; // any alu
a61af66fc99e Initial load duke parents: diff changeset	5268 %}
a61af66fc99e Initial load duke parents: diff changeset	5269
a61af66fc99e Initial load duke parents: diff changeset	5270 // Integer ALU reg-imm operation
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5271 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5272 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5273 cr : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5274 src1 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5275 DECODE : S0; // any decoder
a61af66fc99e Initial load duke parents: diff changeset	5276 ALU : S3; // any alu
a61af66fc99e Initial load duke parents: diff changeset	5277 %}
a61af66fc99e Initial load duke parents: diff changeset	5278
a61af66fc99e Initial load duke parents: diff changeset	5279 // Integer ALU reg-mem operation
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5280 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5281 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5282 cr : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5283 src1 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5284 src2 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5285 D0 : S0; // big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5286 ALU : S4; // any alu
a61af66fc99e Initial load duke parents: diff changeset	5287 MEM : S3;
a61af66fc99e Initial load duke parents: diff changeset	5288 %}
a61af66fc99e Initial load duke parents: diff changeset	5289
a61af66fc99e Initial load duke parents: diff changeset	5290 // Conditional move reg-reg
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5291 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5292 instruction_count(4);
a61af66fc99e Initial load duke parents: diff changeset	5293 y : S4(read);
a61af66fc99e Initial load duke parents: diff changeset	5294 q : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5295 p : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5296 DECODE : S0(4); // any decoder
a61af66fc99e Initial load duke parents: diff changeset	5297 %}
a61af66fc99e Initial load duke parents: diff changeset	5298
a61af66fc99e Initial load duke parents: diff changeset	5299 // Conditional move reg-reg
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5300 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5301 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5302 dst : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5303 src : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5304 cr : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5305 DECODE : S0; // any decoder
a61af66fc99e Initial load duke parents: diff changeset	5306 %}
a61af66fc99e Initial load duke parents: diff changeset	5307
a61af66fc99e Initial load duke parents: diff changeset	5308 // Conditional move reg-mem
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5309 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5310 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5311 dst : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5312 src : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5313 cr : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5314 DECODE : S0; // any decoder
a61af66fc99e Initial load duke parents: diff changeset	5315 MEM : S3;
a61af66fc99e Initial load duke parents: diff changeset	5316 %}
a61af66fc99e Initial load duke parents: diff changeset	5317
a61af66fc99e Initial load duke parents: diff changeset	5318 // Conditional move reg-reg long
a61af66fc99e Initial load duke parents: diff changeset	5319 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
a61af66fc99e Initial load duke parents: diff changeset	5320 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5321 dst : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5322 src : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5323 cr : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5324 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load duke parents: diff changeset	5325 %}
a61af66fc99e Initial load duke parents: diff changeset	5326
a61af66fc99e Initial load duke parents: diff changeset	5327 // Conditional move double reg-reg
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	5328 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5329 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5330 dst : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5331 src : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5332 cr : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5333 DECODE : S0; // any decoder
a61af66fc99e Initial load duke parents: diff changeset	5334 %}
a61af66fc99e Initial load duke parents: diff changeset	5335
a61af66fc99e Initial load duke parents: diff changeset	5336 // Float reg-reg operation
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	5337 pipe_class fpu_reg(regDPR dst) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5338 instruction_count(2);
a61af66fc99e Initial load duke parents: diff changeset	5339 dst : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5340 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load duke parents: diff changeset	5341 FPU : S3;
a61af66fc99e Initial load duke parents: diff changeset	5342 %}
a61af66fc99e Initial load duke parents: diff changeset	5343
a61af66fc99e Initial load duke parents: diff changeset	5344 // Float reg-reg operation
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	5345 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5346 instruction_count(2);
a61af66fc99e Initial load duke parents: diff changeset	5347 dst : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5348 src : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5349 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load duke parents: diff changeset	5350 FPU : S3;
a61af66fc99e Initial load duke parents: diff changeset	5351 %}
a61af66fc99e Initial load duke parents: diff changeset	5352
a61af66fc99e Initial load duke parents: diff changeset	5353 // Float reg-reg operation
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	5354 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5355 instruction_count(3);
a61af66fc99e Initial load duke parents: diff changeset	5356 dst : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5357 src1 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5358 src2 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5359 DECODE : S0(3); // any 3 decoders
a61af66fc99e Initial load duke parents: diff changeset	5360 FPU : S3(2);
a61af66fc99e Initial load duke parents: diff changeset	5361 %}
a61af66fc99e Initial load duke parents: diff changeset	5362
a61af66fc99e Initial load duke parents: diff changeset	5363 // Float reg-reg operation
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	5364 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5365 instruction_count(4);
a61af66fc99e Initial load duke parents: diff changeset	5366 dst : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5367 src1 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5368 src2 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5369 src3 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5370 DECODE : S0(4); // any 3 decoders
a61af66fc99e Initial load duke parents: diff changeset	5371 FPU : S3(2);
a61af66fc99e Initial load duke parents: diff changeset	5372 %}
a61af66fc99e Initial load duke parents: diff changeset	5373
a61af66fc99e Initial load duke parents: diff changeset	5374 // Float reg-reg operation
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	5375 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5376 instruction_count(4);
a61af66fc99e Initial load duke parents: diff changeset	5377 dst : S4(write);
a61af66fc99e Initial load duke parents: diff changeset	5378 src1 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5379 src2 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5380 src3 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5381 DECODE : S1(3); // any 3 decoders
a61af66fc99e Initial load duke parents: diff changeset	5382 D0 : S0; // Big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5383 FPU : S3(2);
a61af66fc99e Initial load duke parents: diff changeset	5384 MEM : S3;
a61af66fc99e Initial load duke parents: diff changeset	5385 %}
a61af66fc99e Initial load duke parents: diff changeset	5386
a61af66fc99e Initial load duke parents: diff changeset	5387 // Float reg-mem operation
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	5388 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5389 instruction_count(2);
a61af66fc99e Initial load duke parents: diff changeset	5390 dst : S5(write);
a61af66fc99e Initial load duke parents: diff changeset	5391 mem : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5392 D0 : S0; // big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5393 DECODE : S1; // any decoder for FPU POP
a61af66fc99e Initial load duke parents: diff changeset	5394 FPU : S4;
a61af66fc99e Initial load duke parents: diff changeset	5395 MEM : S3; // any mem
a61af66fc99e Initial load duke parents: diff changeset	5396 %}
a61af66fc99e Initial load duke parents: diff changeset	5397
a61af66fc99e Initial load duke parents: diff changeset	5398 // Float reg-mem operation
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	5399 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5400 instruction_count(3);
a61af66fc99e Initial load duke parents: diff changeset	5401 dst : S5(write);
a61af66fc99e Initial load duke parents: diff changeset	5402 src1 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5403 mem : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5404 D0 : S0; // big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5405 DECODE : S1(2); // any decoder for FPU POP
a61af66fc99e Initial load duke parents: diff changeset	5406 FPU : S4;
a61af66fc99e Initial load duke parents: diff changeset	5407 MEM : S3; // any mem
a61af66fc99e Initial load duke parents: diff changeset	5408 %}
a61af66fc99e Initial load duke parents: diff changeset	5409
a61af66fc99e Initial load duke parents: diff changeset	5410 // Float mem-reg operation
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	5411 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5412 instruction_count(2);
a61af66fc99e Initial load duke parents: diff changeset	5413 src : S5(read);
a61af66fc99e Initial load duke parents: diff changeset	5414 mem : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5415 DECODE : S0; // any decoder for FPU PUSH
a61af66fc99e Initial load duke parents: diff changeset	5416 D0 : S1; // big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5417 FPU : S4;
a61af66fc99e Initial load duke parents: diff changeset	5418 MEM : S3; // any mem
a61af66fc99e Initial load duke parents: diff changeset	5419 %}
a61af66fc99e Initial load duke parents: diff changeset	5420
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	5421 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5422 instruction_count(3);
a61af66fc99e Initial load duke parents: diff changeset	5423 src1 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5424 src2 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5425 mem : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5426 DECODE : S0(2); // any decoder for FPU PUSH
a61af66fc99e Initial load duke parents: diff changeset	5427 D0 : S1; // big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5428 FPU : S4;
a61af66fc99e Initial load duke parents: diff changeset	5429 MEM : S3; // any mem
a61af66fc99e Initial load duke parents: diff changeset	5430 %}
a61af66fc99e Initial load duke parents: diff changeset	5431
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	5432 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5433 instruction_count(3);
a61af66fc99e Initial load duke parents: diff changeset	5434 src1 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5435 src2 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5436 mem : S4(read);
a61af66fc99e Initial load duke parents: diff changeset	5437 DECODE : S0; // any decoder for FPU PUSH
a61af66fc99e Initial load duke parents: diff changeset	5438 D0 : S0(2); // big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5439 FPU : S4;
a61af66fc99e Initial load duke parents: diff changeset	5440 MEM : S3(2); // any mem
a61af66fc99e Initial load duke parents: diff changeset	5441 %}
a61af66fc99e Initial load duke parents: diff changeset	5442
a61af66fc99e Initial load duke parents: diff changeset	5443 pipe_class fpu_mem_mem(memory dst, memory src1) %{
a61af66fc99e Initial load duke parents: diff changeset	5444 instruction_count(2);
a61af66fc99e Initial load duke parents: diff changeset	5445 src1 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5446 dst : S4(read);
a61af66fc99e Initial load duke parents: diff changeset	5447 D0 : S0(2); // big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5448 MEM : S3(2); // any mem
a61af66fc99e Initial load duke parents: diff changeset	5449 %}
a61af66fc99e Initial load duke parents: diff changeset	5450
a61af66fc99e Initial load duke parents: diff changeset	5451 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
a61af66fc99e Initial load duke parents: diff changeset	5452 instruction_count(3);
a61af66fc99e Initial load duke parents: diff changeset	5453 src1 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5454 src2 : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5455 dst : S4(read);
a61af66fc99e Initial load duke parents: diff changeset	5456 D0 : S0(3); // big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5457 FPU : S4;
a61af66fc99e Initial load duke parents: diff changeset	5458 MEM : S3(3); // any mem
a61af66fc99e Initial load duke parents: diff changeset	5459 %}
a61af66fc99e Initial load duke parents: diff changeset	5460
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	5461 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5462 instruction_count(3);
a61af66fc99e Initial load duke parents: diff changeset	5463 src1 : S4(read);
a61af66fc99e Initial load duke parents: diff changeset	5464 mem : S4(read);
a61af66fc99e Initial load duke parents: diff changeset	5465 DECODE : S0; // any decoder for FPU PUSH
a61af66fc99e Initial load duke parents: diff changeset	5466 D0 : S0(2); // big decoder only
a61af66fc99e Initial load duke parents: diff changeset	5467 FPU : S4;
a61af66fc99e Initial load duke parents: diff changeset	5468 MEM : S3(2); // any mem
a61af66fc99e Initial load duke parents: diff changeset	5469 %}
a61af66fc99e Initial load duke parents: diff changeset	5470
a61af66fc99e Initial load duke parents: diff changeset	5471 // Float load constant
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	5472 pipe_class fpu_reg_con(regDPR dst) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5473 instruction_count(2);
a61af66fc99e Initial load duke parents: diff changeset	5474 dst : S5(write);
a61af66fc99e Initial load duke parents: diff changeset	5475 D0 : S0; // big decoder only for the load
a61af66fc99e Initial load duke parents: diff changeset	5476 DECODE : S1; // any decoder for FPU POP
a61af66fc99e Initial load duke parents: diff changeset	5477 FPU : S4;
a61af66fc99e Initial load duke parents: diff changeset	5478 MEM : S3; // any mem
a61af66fc99e Initial load duke parents: diff changeset	5479 %}
a61af66fc99e Initial load duke parents: diff changeset	5480
a61af66fc99e Initial load duke parents: diff changeset	5481 // Float load constant
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	5482 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5483 instruction_count(3);
a61af66fc99e Initial load duke parents: diff changeset	5484 dst : S5(write);
a61af66fc99e Initial load duke parents: diff changeset	5485 src : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5486 D0 : S0; // big decoder only for the load
a61af66fc99e Initial load duke parents: diff changeset	5487 DECODE : S1(2); // any decoder for FPU POP
a61af66fc99e Initial load duke parents: diff changeset	5488 FPU : S4;
a61af66fc99e Initial load duke parents: diff changeset	5489 MEM : S3; // any mem
a61af66fc99e Initial load duke parents: diff changeset	5490 %}
a61af66fc99e Initial load duke parents: diff changeset	5491
a61af66fc99e Initial load duke parents: diff changeset	5492 // UnConditional branch
a61af66fc99e Initial load duke parents: diff changeset	5493 pipe_class pipe_jmp( label labl ) %{
a61af66fc99e Initial load duke parents: diff changeset	5494 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5495 BR : S3;
a61af66fc99e Initial load duke parents: diff changeset	5496 %}
a61af66fc99e Initial load duke parents: diff changeset	5497
a61af66fc99e Initial load duke parents: diff changeset	5498 // Conditional branch
a61af66fc99e Initial load duke parents: diff changeset	5499 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
a61af66fc99e Initial load duke parents: diff changeset	5500 single_instruction;
a61af66fc99e Initial load duke parents: diff changeset	5501 cr : S1(read);
a61af66fc99e Initial load duke parents: diff changeset	5502 BR : S3;
a61af66fc99e Initial load duke parents: diff changeset	5503 %}
a61af66fc99e Initial load duke parents: diff changeset	5504
a61af66fc99e Initial load duke parents: diff changeset	5505 // Allocation idiom
a61af66fc99e Initial load duke parents: diff changeset	5506 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
a61af66fc99e Initial load duke parents: diff changeset	5507 instruction_count(1); force_serialization;
a61af66fc99e Initial load duke parents: diff changeset	5508 fixed_latency(6);
a61af66fc99e Initial load duke parents: diff changeset	5509 heap_ptr : S3(read);
a61af66fc99e Initial load duke parents: diff changeset	5510 DECODE : S0(3);
a61af66fc99e Initial load duke parents: diff changeset	5511 D0 : S2;
a61af66fc99e Initial load duke parents: diff changeset	5512 MEM : S3;
a61af66fc99e Initial load duke parents: diff changeset	5513 ALU : S3(2);
a61af66fc99e Initial load duke parents: diff changeset	5514 dst : S5(write);
a61af66fc99e Initial load duke parents: diff changeset	5515 BR : S5;
a61af66fc99e Initial load duke parents: diff changeset	5516 %}
a61af66fc99e Initial load duke parents: diff changeset	5517
a61af66fc99e Initial load duke parents: diff changeset	5518 // Generic big/slow expanded idiom
a61af66fc99e Initial load duke parents: diff changeset	5519 pipe_class pipe_slow( ) %{
a61af66fc99e Initial load duke parents: diff changeset	5520 instruction_count(10); multiple_bundles; force_serialization;
a61af66fc99e Initial load duke parents: diff changeset	5521 fixed_latency(100);
a61af66fc99e Initial load duke parents: diff changeset	5522 D0 : S0(2);
a61af66fc99e Initial load duke parents: diff changeset	5523 MEM : S3(2);
a61af66fc99e Initial load duke parents: diff changeset	5524 %}
a61af66fc99e Initial load duke parents: diff changeset	5525
a61af66fc99e Initial load duke parents: diff changeset	5526 // The real do-nothing guy
a61af66fc99e Initial load duke parents: diff changeset	5527 pipe_class empty( ) %{
a61af66fc99e Initial load duke parents: diff changeset	5528 instruction_count(0);
a61af66fc99e Initial load duke parents: diff changeset	5529 %}
a61af66fc99e Initial load duke parents: diff changeset	5530
a61af66fc99e Initial load duke parents: diff changeset	5531 // Define the class for the Nop node
a61af66fc99e Initial load duke parents: diff changeset	5532 define %{
a61af66fc99e Initial load duke parents: diff changeset	5533 MachNop = empty;
a61af66fc99e Initial load duke parents: diff changeset	5534 %}
a61af66fc99e Initial load duke parents: diff changeset	5535
a61af66fc99e Initial load duke parents: diff changeset	5536 %}
a61af66fc99e Initial load duke parents: diff changeset	5537
a61af66fc99e Initial load duke parents: diff changeset	5538 //----------INSTRUCTIONS-------------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	5539 //
a61af66fc99e Initial load duke parents: diff changeset	5540 // match -- States which machine-independent subtree may be replaced
a61af66fc99e Initial load duke parents: diff changeset	5541 // by this instruction.
a61af66fc99e Initial load duke parents: diff changeset	5542 // ins_cost -- The estimated cost of this instruction is used by instruction
a61af66fc99e Initial load duke parents: diff changeset	5543 // selection to identify a minimum cost tree of machine
a61af66fc99e Initial load duke parents: diff changeset	5544 // instructions that matches a tree of machine-independent
a61af66fc99e Initial load duke parents: diff changeset	5545 // instructions.
a61af66fc99e Initial load duke parents: diff changeset	5546 // format -- A string providing the disassembly for this instruction.
a61af66fc99e Initial load duke parents: diff changeset	5547 // The value of an instruction's operand may be inserted
a61af66fc99e Initial load duke parents: diff changeset	5548 // by referring to it with a '$' prefix.
a61af66fc99e Initial load duke parents: diff changeset	5549 // opcode -- Three instruction opcodes may be provided. These are referred
a61af66fc99e Initial load duke parents: diff changeset	5550 // to within an encode class as $primary, $secondary, and $tertiary
a61af66fc99e Initial load duke parents: diff changeset	5551 // respectively. The primary opcode is commonly used to
a61af66fc99e Initial load duke parents: diff changeset	5552 // indicate the type of machine instruction, while secondary
a61af66fc99e Initial load duke parents: diff changeset	5553 // and tertiary are often used for prefix options or addressing
a61af66fc99e Initial load duke parents: diff changeset	5554 // modes.
a61af66fc99e Initial load duke parents: diff changeset	5555 // ins_encode -- A list of encode classes with parameters. The encode class
a61af66fc99e Initial load duke parents: diff changeset	5556 // name must have been defined in an 'enc_class' specification
a61af66fc99e Initial load duke parents: diff changeset	5557 // in the encode section of the architecture description.
a61af66fc99e Initial load duke parents: diff changeset	5558
a61af66fc99e Initial load duke parents: diff changeset	5559 //----------BSWAP-Instruction--------------------------------------------------
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5560 instruct bytes_reverse_int(rRegI dst) %{
0 a61af66fc99e Initial load duke parents: diff changeset	5561 match(Set dst (ReverseBytesI dst));
a61af66fc99e Initial load duke parents: diff changeset	5562
a61af66fc99e Initial load duke parents: diff changeset	5563 format %{ "BSWAP $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	5564 opcode(0x0F, 0xC8);
a61af66fc99e Initial load duke parents: diff changeset	5565 ins_encode( OpcP, OpcSReg(dst) );
a61af66fc99e Initial load duke parents: diff changeset	5566 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	5567 %}
a61af66fc99e Initial load duke parents: diff changeset	5568
a61af66fc99e Initial load duke parents: diff changeset	5569 instruct bytes_reverse_long(eRegL dst) %{
a61af66fc99e Initial load duke parents: diff changeset	5570 match(Set dst (ReverseBytesL dst));
a61af66fc99e Initial load duke parents: diff changeset	5571
a61af66fc99e Initial load duke parents: diff changeset	5572 format %{ "BSWAP $dst.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	5573 "BSWAP $dst.hi\n\t"
a61af66fc99e Initial load duke parents: diff changeset	5574 "XCHG $dst.lo $dst.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	5575
a61af66fc99e Initial load duke parents: diff changeset	5576 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	5577 ins_encode( bswap_long_bytes(dst) );
a61af66fc99e Initial load duke parents: diff changeset	5578 ins_pipe( ialu_reg_reg);
a61af66fc99e Initial load duke parents: diff changeset	5579 %}
a61af66fc99e Initial load duke parents: diff changeset	5580
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5581 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
1396 d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5582 match(Set dst (ReverseBytesUS dst));
6138 ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long) twisti parents: 6084 diff changeset	5583 effect(KILL cr);
1396 d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5584
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5585 format %{ "BSWAP $dst\n\t"
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5586 "SHR $dst,16\n\t" %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5587 ins_encode %{
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5588 __ bswapl($dst$$Register);
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5589 __ shrl($dst$$Register, 16);
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5590 %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5591 ins_pipe( ialu_reg );
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5592 %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5593
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5594 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
1396 d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5595 match(Set dst (ReverseBytesS dst));
6138 ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long) twisti parents: 6084 diff changeset	5596 effect(KILL cr);
1396 d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5597
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5598 format %{ "BSWAP $dst\n\t"
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5599 "SAR $dst,16\n\t" %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5600 ins_encode %{
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5601 __ bswapl($dst$$Register);
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5602 __ sarl($dst$$Register, 16);
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5603 %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5604 ins_pipe( ialu_reg );
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5605 %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes never parents: 1274 diff changeset	5606
0 a61af66fc99e Initial load duke parents: diff changeset	5607
775 93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5608 //---------- Zeros Count Instructions ------------------------------------------
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5609
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5610 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
775 93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5611 predicate(UseCountLeadingZerosInstruction);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5612 match(Set dst (CountLeadingZerosI src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5613 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5614
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5615 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5616 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5617 __ lzcntl($dst$$Register, $src$$Register);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5618 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5619 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5620 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5621
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5622 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
775 93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5623 predicate(!UseCountLeadingZerosInstruction);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5624 match(Set dst (CountLeadingZerosI src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5625 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5626
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5627 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5628 "JNZ skip\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5629 "MOV $dst, -1\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5630 "skip:\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5631 "NEG $dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5632 "ADD $dst, 31" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5633 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5634 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5635 Register Rsrc = $src$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5636 Label skip;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5637 __ bsrl(Rdst, Rsrc);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5638 __ jccb(Assembler::notZero, skip);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5639 __ movl(Rdst, -1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5640 __ bind(skip);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5641 __ negl(Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5642 __ addl(Rdst, BitsPerInt - 1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5643 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5644 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5645 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5646
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5647 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
775 93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5648 predicate(UseCountLeadingZerosInstruction);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5649 match(Set dst (CountLeadingZerosL src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5650 effect(TEMP dst, KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5651
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5652 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5653 "JNC done\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5654 "LZCNT $dst, $src.lo\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5655 "ADD $dst, 32\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5656 "done:" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5657 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5658 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5659 Register Rsrc = $src$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5660 Label done;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5661 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5662 __ jccb(Assembler::carryClear, done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5663 __ lzcntl(Rdst, Rsrc);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5664 __ addl(Rdst, BitsPerInt);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5665 __ bind(done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5666 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5667 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5668 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5669
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5670 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
775 93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5671 predicate(!UseCountLeadingZerosInstruction);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5672 match(Set dst (CountLeadingZerosL src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5673 effect(TEMP dst, KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5674
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5675 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5676 "JZ msw_is_zero\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5677 "ADD $dst, 32\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5678 "JMP not_zero\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5679 "msw_is_zero:\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5680 "BSR $dst, $src.lo\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5681 "JNZ not_zero\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5682 "MOV $dst, -1\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5683 "not_zero:\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5684 "NEG $dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5685 "ADD $dst, 63\n" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5686 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5687 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5688 Register Rsrc = $src$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5689 Label msw_is_zero;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5690 Label not_zero;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5691 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5692 __ jccb(Assembler::zero, msw_is_zero);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5693 __ addl(Rdst, BitsPerInt);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5694 __ jmpb(not_zero);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5695 __ bind(msw_is_zero);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5696 __ bsrl(Rdst, Rsrc);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5697 __ jccb(Assembler::notZero, not_zero);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5698 __ movl(Rdst, -1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5699 __ bind(not_zero);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5700 __ negl(Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5701 __ addl(Rdst, BitsPerLong - 1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5702 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5703 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5704 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5705
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5706 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
775 93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5707 match(Set dst (CountTrailingZerosI src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5708 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5709
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5710 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5711 "JNZ done\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5712 "MOV $dst, 32\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5713 "done:" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5714 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5715 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5716 Label done;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5717 __ bsfl(Rdst, $src$$Register);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5718 __ jccb(Assembler::notZero, done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5719 __ movl(Rdst, BitsPerInt);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5720 __ bind(done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5721 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5722 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5723 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5724
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5725 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
775 93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5726 match(Set dst (CountTrailingZerosL src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5727 effect(TEMP dst, KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5728
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5729 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5730 "JNZ done\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5731 "BSF $dst, $src.hi\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5732 "JNZ msw_not_zero\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5733 "MOV $dst, 32\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5734 "msw_not_zero:\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5735 "ADD $dst, 32\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5736 "done:" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5737 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5738 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5739 Register Rsrc = $src$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5740 Label msw_not_zero;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5741 Label done;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5742 __ bsfl(Rdst, Rsrc);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5743 __ jccb(Assembler::notZero, done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5744 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5745 __ jccb(Assembler::notZero, msw_not_zero);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5746 __ movl(Rdst, BitsPerInt);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5747 __ bind(msw_not_zero);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5748 __ addl(Rdst, BitsPerInt);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5749 __ bind(done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5750 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5751 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5752 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5753
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() twisti parents: 681 diff changeset	5754
643 c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5755 //---------- Population Count Instructions -------------------------------------
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5756
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5757 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
643 c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5758 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5759 match(Set dst (PopCountI src));
6138 ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long) twisti parents: 6084 diff changeset	5760 effect(KILL cr);
643 c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5761
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5762 format %{ "POPCNT $dst, $src" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5763 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5764 __ popcntl($dst$$Register, $src$$Register);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5765 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5766 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5767 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5768
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5769 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
643 c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5770 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5771 match(Set dst (PopCountI (LoadI mem)));
6138 ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long) twisti parents: 6084 diff changeset	5772 effect(KILL cr);
643 c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5773
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5774 format %{ "POPCNT $dst, $mem" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5775 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5776 __ popcntl($dst$$Register, $mem$$Address);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5777 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5778 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5779 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5780
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5781 // Note: Long.bitCount(long) returns an int.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5782 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
643 c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5783 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5784 match(Set dst (PopCountL src));
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5785 effect(KILL cr, TEMP tmp, TEMP dst);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5786
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5787 format %{ "POPCNT $dst, $src.lo\n\t"
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5788 "POPCNT $tmp, $src.hi\n\t"
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5789 "ADD $dst, $tmp" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5790 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5791 __ popcntl($dst$$Register, $src$$Register);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5792 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5793 __ addl($dst$$Register, $tmp$$Register);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5794 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5795 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5796 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5797
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5798 // Note: Long.bitCount(long) returns an int.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5799 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
643 c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5800 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5801 match(Set dst (PopCountL (LoadL mem)));
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5802 effect(KILL cr, TEMP tmp, TEMP dst);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5803
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5804 format %{ "POPCNT $dst, $mem\n\t"
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5805 "POPCNT $tmp, $mem+4\n\t"
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5806 "ADD $dst, $tmp" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5807 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5808 //__ popcntl($dst$$Register, $mem$$Address$$first);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5809 //__ popcntl($tmp$$Register, $mem$$Address$$second);
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	5810 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	5811 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
643 c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5812 __ addl($dst$$Register, $tmp$$Register);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5813 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5814 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5815 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5816
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h twisti parents: 624 diff changeset	5817
0 a61af66fc99e Initial load duke parents: diff changeset	5818 //----------Load/Store/Move Instructions---------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	5819 //----------Load Instructions--------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	5820 // Load Byte (8bit signed)
a61af66fc99e Initial load duke parents: diff changeset	5821 instruct loadB(xRegI dst, memory mem) %{
a61af66fc99e Initial load duke parents: diff changeset	5822 match(Set dst (LoadB mem));
a61af66fc99e Initial load duke parents: diff changeset	5823
a61af66fc99e Initial load duke parents: diff changeset	5824 ins_cost(125);
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5825 format %{ "MOVSX8 $dst,$mem\t# byte" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5826
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5827 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5828 __ movsbl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5829 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5830
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5831 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5832 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5833
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5834 // Load Byte (8bit signed) into Long Register
824 18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5835 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5836 match(Set dst (ConvI2L (LoadB mem)));
824 18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5837 effect(KILL cr);
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5838
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5839 ins_cost(375);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5840 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5841 "MOV $dst.hi,$dst.lo\n\t"
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5842 "SAR $dst.hi,7" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5843
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5844 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5845 __ movsbl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5846 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5847 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5848 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5849
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5850 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5851 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5852
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5853 // Load Unsigned Byte (8bit UNsigned)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5854 instruct loadUB(xRegI dst, memory mem) %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5855 match(Set dst (LoadUB mem));
0 a61af66fc99e Initial load duke parents: diff changeset	5856
a61af66fc99e Initial load duke parents: diff changeset	5857 ins_cost(125);
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5858 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5859
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5860 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5861 __ movzbl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5862 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5863
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5864 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5865 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5866
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5867 // Load Unsigned Byte (8 bit UNsigned) into Long Register
824 18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5868 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5869 match(Set dst (ConvI2L (LoadUB mem)));
824 18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5870 effect(KILL cr);
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5871
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5872 ins_cost(250);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5873 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5874 "XOR $dst.hi,$dst.hi" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5875
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5876 ins_encode %{
824 18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5877 Register Rdst = $dst$$Register;
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5878 __ movzbl(Rdst, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5879 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5880 %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5881
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5882 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5883 %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5884
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5885 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5886 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5887 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5888 effect(KILL cr);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5889
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5890 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5891 "XOR $dst.hi,$dst.hi\n\t"
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5892 "AND $dst.lo,$mask" %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5893 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5894 Register Rdst = $dst$$Register;
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5895 __ movzbl(Rdst, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5896 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5897 __ andl(Rdst, $mask$$constant);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5898 %}
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5899 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5900 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5901
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5902 // Load Short (16bit signed)
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5903 instruct loadS(rRegI dst, memory mem) %{
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5904 match(Set dst (LoadS mem));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5905
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5906 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5907 format %{ "MOVSX $dst,$mem\t# short" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5908
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5909 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5910 __ movswl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5911 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5912
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5913 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5914 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5915
785 2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5916 // Load Short (16 bit signed) to Byte (8 bit signed)
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5917 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
785 2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5918 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5919
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5920 ins_cost(125);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5921 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5922 ins_encode %{
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5923 __ movsbl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5924 %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5925 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5926 %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5927
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5928 // Load Short (16bit signed) into Long Register
824 18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5929 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5930 match(Set dst (ConvI2L (LoadS mem)));
824 18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5931 effect(KILL cr);
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5932
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5933 ins_cost(375);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5934 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5935 "MOV $dst.hi,$dst.lo\n\t"
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5936 "SAR $dst.hi,15" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5937
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5938 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5939 __ movswl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5940 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5941 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5942 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5943
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5944 ins_pipe(ialu_reg_mem);
0 a61af66fc99e Initial load duke parents: diff changeset	5945 %}
a61af66fc99e Initial load duke parents: diff changeset	5946
558 3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short) twisti parents: 420 diff changeset	5947 // Load Unsigned Short/Char (16bit unsigned)
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5948 instruct loadUS(rRegI dst, memory mem) %{
558 3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short) twisti parents: 420 diff changeset	5949 match(Set dst (LoadUS mem));
0 a61af66fc99e Initial load duke parents: diff changeset	5950
a61af66fc99e Initial load duke parents: diff changeset	5951 ins_cost(125);
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5952 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5953
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5954 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5955 __ movzwl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5956 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5957
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5958 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5959 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5960
785 2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5961 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	5962 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
785 2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5963 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5964
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5965 ins_cost(125);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5966 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5967 ins_encode %{
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5968 __ movsbl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5969 %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5970 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5971 %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	5972
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5973 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
824 18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5974 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5975 match(Set dst (ConvI2L (LoadUS mem)));
824 18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5976 effect(KILL cr);
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5977
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5978 ins_cost(250);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5979 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5980 "XOR $dst.hi,$dst.hi" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5981
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5982 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5983 __ movzwl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5984 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5985 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5986
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	5987 ins_pipe(ialu_reg_mem);
0 a61af66fc99e Initial load duke parents: diff changeset	5988 %}
a61af66fc99e Initial load duke parents: diff changeset	5989
824 18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5990 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5991 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5992 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5993 effect(KILL cr);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5994
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5995 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5996 "XOR $dst.hi,$dst.hi" %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5997 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5998 Register Rdst = $dst$$Register;
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	5999 __ movzbl(Rdst, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6000 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6001 %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6002 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6003 %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6004
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6005 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6006 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6007 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6008 effect(KILL cr);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6009
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6010 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6011 "XOR $dst.hi,$dst.hi\n\t"
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6012 "AND $dst.lo,$mask" %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6013 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6014 Register Rdst = $dst$$Register;
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6015 __ movzwl(Rdst, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6016 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6017 __ andl(Rdst, $mask$$constant);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6018 %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6019 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6020 %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6021
0 a61af66fc99e Initial load duke parents: diff changeset	6022 // Load Integer
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	6023 instruct loadI(rRegI dst, memory mem) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6024 match(Set dst (LoadI mem));
a61af66fc99e Initial load duke parents: diff changeset	6025
a61af66fc99e Initial load duke parents: diff changeset	6026 ins_cost(125);
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6027 format %{ "MOV $dst,$mem\t# int" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6028
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6029 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6030 __ movl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6031 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6032
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6033 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6034 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6035
785 2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6036 // Load Integer (32 bit signed) to Byte (8 bit signed)
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	6037 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
785 2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6038 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6039
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6040 ins_cost(125);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6041 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6042 ins_encode %{
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6043 __ movsbl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6044 %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6045 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6046 %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6047
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6048 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	6049 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
785 2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6050 match(Set dst (AndI (LoadI mem) mask));
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6051
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6052 ins_cost(125);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6053 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6054 ins_encode %{
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6055 __ movzbl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6056 %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6057 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6058 %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6059
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6060 // Load Integer (32 bit signed) to Short (16 bit signed)
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	6061 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
785 2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6062 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6063
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6064 ins_cost(125);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6065 format %{ "MOVSX $dst, $mem\t# int -> short" %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6066 ins_encode %{
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6067 __ movswl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6068 %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6069 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6070 %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6071
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6072 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	6073 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
785 2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6074 match(Set dst (AndI (LoadI mem) mask));
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6075
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6076 ins_cost(125);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6077 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6078 ins_encode %{
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6079 __ movzwl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6080 %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6081 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6082 %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	6083
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6084 // Load Integer into Long Register
824 18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6085 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6086 match(Set dst (ConvI2L (LoadI mem)));
824 18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6087 effect(KILL cr);
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6088
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6089 ins_cost(375);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6090 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6091 "MOV $dst.hi,$dst.lo\n\t"
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6092 "SAR $dst.hi,31" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6093
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6094 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6095 __ movl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6096 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6097 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6098 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6099
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6100 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6101 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6102
824 18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6103 // Load Integer with mask 0xFF into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6104 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6105 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6106 effect(KILL cr);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6107
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6108 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6109 "XOR $dst.hi,$dst.hi" %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6110 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6111 Register Rdst = $dst$$Register;
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6112 __ movzbl(Rdst, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6113 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6114 %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6115 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6116 %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6117
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6118 // Load Integer with mask 0xFFFF into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6119 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6120 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6121 effect(KILL cr);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6122
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6123 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6124 "XOR $dst.hi,$dst.hi" %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6125 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6126 Register Rdst = $dst$$Register;
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6127 __ movzwl(Rdst, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6128 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6129 %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6130 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6131 %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6132
17524 89152779163c Merge with jdk8-b132 Gilles Duboscq <duboscq@ssw.jku.at> parents: 14909 diff changeset	6133 // Load Integer with 31-bit mask into Long Register
89152779163c Merge with jdk8-b132 Gilles Duboscq <duboscq@ssw.jku.at> parents: 14909 diff changeset	6134 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{
824 18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6135 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6136 effect(KILL cr);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6137
17524 89152779163c Merge with jdk8-b132 Gilles Duboscq <duboscq@ssw.jku.at> parents: 14909 diff changeset	6138 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t"
824 18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6139 "XOR $dst.hi,$dst.hi\n\t"
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6140 "AND $dst.lo,$mask" %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6141 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6142 Register Rdst = $dst$$Register;
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6143 __ movl(Rdst, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6144 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6145 __ andl(Rdst, $mask$$constant);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6146 %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6147 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6148 %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6149
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6150 // Load Unsigned Integer into Long Register
6849 f6badecb7ea7 7199654: Remove LoadUI2LNode vlivanov parents: 6848 diff changeset	6151 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
f6badecb7ea7 7199654: Remove LoadUI2LNode vlivanov parents: 6848 diff changeset	6152 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
824 18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6153 effect(KILL cr);
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6154
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6155 ins_cost(250);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6156 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6157 "XOR $dst.hi,$dst.hi" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6158
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6159 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6160 __ movl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6161 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6162 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6163
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6164 ins_pipe(ialu_reg_mem);
0 a61af66fc99e Initial load duke parents: diff changeset	6165 %}
a61af66fc99e Initial load duke parents: diff changeset	6166
a61af66fc99e Initial load duke parents: diff changeset	6167 // Load Long. Cannot clobber address while loading, so restrict address
a61af66fc99e Initial load duke parents: diff changeset	6168 // register to ESI
a61af66fc99e Initial load duke parents: diff changeset	6169 instruct loadL(eRegL dst, load_long_memory mem) %{
a61af66fc99e Initial load duke parents: diff changeset	6170 predicate(!((LoadLNode*)n)->require_atomic_access());
a61af66fc99e Initial load duke parents: diff changeset	6171 match(Set dst (LoadL mem));
a61af66fc99e Initial load duke parents: diff changeset	6172
a61af66fc99e Initial load duke parents: diff changeset	6173 ins_cost(250);
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6174 format %{ "MOV $dst.lo,$mem\t# long\n\t"
0 a61af66fc99e Initial load duke parents: diff changeset	6175 "MOV $dst.hi,$mem+4" %}
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6176
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6177 ins_encode %{
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	6178 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	6179 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6180 __ movl($dst$$Register, Amemlo);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6181 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6182 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6183
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	6184 ins_pipe(ialu_reg_long_mem);
0 a61af66fc99e Initial load duke parents: diff changeset	6185 %}
a61af66fc99e Initial load duke parents: diff changeset	6186
a61af66fc99e Initial load duke parents: diff changeset	6187 // Volatile Load Long. Must be atomic, so do 64-bit FILD
a61af66fc99e Initial load duke parents: diff changeset	6188 // then store it down to the stack and reload on the int
a61af66fc99e Initial load duke parents: diff changeset	6189 // side.
a61af66fc99e Initial load duke parents: diff changeset	6190 instruct loadL_volatile(stackSlotL dst, memory mem) %{
a61af66fc99e Initial load duke parents: diff changeset	6191 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
a61af66fc99e Initial load duke parents: diff changeset	6192 match(Set dst (LoadL mem));
a61af66fc99e Initial load duke parents: diff changeset	6193
a61af66fc99e Initial load duke parents: diff changeset	6194 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	6195 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6196 "FISTp $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	6197 ins_encode(enc_loadL_volatile(mem,dst));
a61af66fc99e Initial load duke parents: diff changeset	6198 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	6199 %}
a61af66fc99e Initial load duke parents: diff changeset	6200
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6201 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6202 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
a61af66fc99e Initial load duke parents: diff changeset	6203 match(Set dst (LoadL mem));
a61af66fc99e Initial load duke parents: diff changeset	6204 effect(TEMP tmp);
a61af66fc99e Initial load duke parents: diff changeset	6205 ins_cost(180);
a61af66fc99e Initial load duke parents: diff changeset	6206 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6207 "MOVSD $dst,$tmp" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6208 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6209 __ movdbl($tmp$$XMMRegister, $mem$$Address);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6210 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6211 %}
0 a61af66fc99e Initial load duke parents: diff changeset	6212 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	6213 %}
a61af66fc99e Initial load duke parents: diff changeset	6214
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6215 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6216 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
a61af66fc99e Initial load duke parents: diff changeset	6217 match(Set dst (LoadL mem));
a61af66fc99e Initial load duke parents: diff changeset	6218 effect(TEMP tmp);
a61af66fc99e Initial load duke parents: diff changeset	6219 ins_cost(160);
a61af66fc99e Initial load duke parents: diff changeset	6220 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6221 "MOVD $dst.lo,$tmp\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6222 "PSRLQ $tmp,32\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6223 "MOVD $dst.hi,$tmp" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6224 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6225 __ movdbl($tmp$$XMMRegister, $mem$$Address);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6226 __ movdl($dst$$Register, $tmp$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6227 __ psrlq($tmp$$XMMRegister, 32);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6228 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6229 %}
0 a61af66fc99e Initial load duke parents: diff changeset	6230 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	6231 %}
a61af66fc99e Initial load duke parents: diff changeset	6232
a61af66fc99e Initial load duke parents: diff changeset	6233 // Load Range
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	6234 instruct loadRange(rRegI dst, memory mem) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6235 match(Set dst (LoadRange mem));
a61af66fc99e Initial load duke parents: diff changeset	6236
a61af66fc99e Initial load duke parents: diff changeset	6237 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	6238 format %{ "MOV $dst,$mem" %}
a61af66fc99e Initial load duke parents: diff changeset	6239 opcode(0x8B);
a61af66fc99e Initial load duke parents: diff changeset	6240 ins_encode( OpcP, RegMem(dst,mem));
a61af66fc99e Initial load duke parents: diff changeset	6241 ins_pipe( ialu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	6242 %}
a61af66fc99e Initial load duke parents: diff changeset	6243
a61af66fc99e Initial load duke parents: diff changeset	6244
a61af66fc99e Initial load duke parents: diff changeset	6245 // Load Pointer
a61af66fc99e Initial load duke parents: diff changeset	6246 instruct loadP(eRegP dst, memory mem) %{
a61af66fc99e Initial load duke parents: diff changeset	6247 match(Set dst (LoadP mem));
a61af66fc99e Initial load duke parents: diff changeset	6248
a61af66fc99e Initial load duke parents: diff changeset	6249 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	6250 format %{ "MOV $dst,$mem" %}
a61af66fc99e Initial load duke parents: diff changeset	6251 opcode(0x8B);
a61af66fc99e Initial load duke parents: diff changeset	6252 ins_encode( OpcP, RegMem(dst,mem));
a61af66fc99e Initial load duke parents: diff changeset	6253 ins_pipe( ialu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	6254 %}
a61af66fc99e Initial load duke parents: diff changeset	6255
a61af66fc99e Initial load duke parents: diff changeset	6256 // Load Klass Pointer
a61af66fc99e Initial load duke parents: diff changeset	6257 instruct loadKlass(eRegP dst, memory mem) %{
a61af66fc99e Initial load duke parents: diff changeset	6258 match(Set dst (LoadKlass mem));
a61af66fc99e Initial load duke parents: diff changeset	6259
a61af66fc99e Initial load duke parents: diff changeset	6260 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	6261 format %{ "MOV $dst,$mem" %}
a61af66fc99e Initial load duke parents: diff changeset	6262 opcode(0x8B);
a61af66fc99e Initial load duke parents: diff changeset	6263 ins_encode( OpcP, RegMem(dst,mem));
a61af66fc99e Initial load duke parents: diff changeset	6264 ins_pipe( ialu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	6265 %}
a61af66fc99e Initial load duke parents: diff changeset	6266
a61af66fc99e Initial load duke parents: diff changeset	6267 // Load Double
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6268 instruct loadDPR(regDPR dst, memory mem) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6269 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	6270 match(Set dst (LoadD mem));
a61af66fc99e Initial load duke parents: diff changeset	6271
a61af66fc99e Initial load duke parents: diff changeset	6272 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	6273 format %{ "FLD_D ST,$mem\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6274 "FSTP $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	6275 opcode(0xDD); /* DD /0 */
a61af66fc99e Initial load duke parents: diff changeset	6276 ins_encode( OpcP, RMopc_Mem(0x00,mem),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6277 Pop_Reg_DPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	6278 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	6279 %}
a61af66fc99e Initial load duke parents: diff changeset	6280
a61af66fc99e Initial load duke parents: diff changeset	6281 // Load Double to XMM
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6282 instruct loadD(regD dst, memory mem) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6283 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
a61af66fc99e Initial load duke parents: diff changeset	6284 match(Set dst (LoadD mem));
a61af66fc99e Initial load duke parents: diff changeset	6285 ins_cost(145);
a61af66fc99e Initial load duke parents: diff changeset	6286 format %{ "MOVSD $dst,$mem" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6287 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6288 __ movdbl ($dst$$XMMRegister, $mem$$Address);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6289 %}
0 a61af66fc99e Initial load duke parents: diff changeset	6290 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	6291 %}
a61af66fc99e Initial load duke parents: diff changeset	6292
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6293 instruct loadD_partial(regD dst, memory mem) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6294 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
a61af66fc99e Initial load duke parents: diff changeset	6295 match(Set dst (LoadD mem));
a61af66fc99e Initial load duke parents: diff changeset	6296 ins_cost(145);
a61af66fc99e Initial load duke parents: diff changeset	6297 format %{ "MOVLPD $dst,$mem" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6298 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6299 __ movdbl ($dst$$XMMRegister, $mem$$Address);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6300 %}
0 a61af66fc99e Initial load duke parents: diff changeset	6301 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	6302 %}
a61af66fc99e Initial load duke parents: diff changeset	6303
a61af66fc99e Initial load duke parents: diff changeset	6304 // Load to XMM register (single-precision floating point)
a61af66fc99e Initial load duke parents: diff changeset	6305 // MOVSS instruction
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6306 instruct loadF(regF dst, memory mem) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6307 predicate(UseSSE>=1);
a61af66fc99e Initial load duke parents: diff changeset	6308 match(Set dst (LoadF mem));
a61af66fc99e Initial load duke parents: diff changeset	6309 ins_cost(145);
a61af66fc99e Initial load duke parents: diff changeset	6310 format %{ "MOVSS $dst,$mem" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6311 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6312 __ movflt ($dst$$XMMRegister, $mem$$Address);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6313 %}
0 a61af66fc99e Initial load duke parents: diff changeset	6314 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	6315 %}
a61af66fc99e Initial load duke parents: diff changeset	6316
a61af66fc99e Initial load duke parents: diff changeset	6317 // Load Float
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6318 instruct loadFPR(regFPR dst, memory mem) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6319 predicate(UseSSE==0);
a61af66fc99e Initial load duke parents: diff changeset	6320 match(Set dst (LoadF mem));
a61af66fc99e Initial load duke parents: diff changeset	6321
a61af66fc99e Initial load duke parents: diff changeset	6322 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	6323 format %{ "FLD_S ST,$mem\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6324 "FSTP $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	6325 opcode(0xD9); /* D9 /0 */
a61af66fc99e Initial load duke parents: diff changeset	6326 ins_encode( OpcP, RMopc_Mem(0x00,mem),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6327 Pop_Reg_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	6328 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	6329 %}
a61af66fc99e Initial load duke parents: diff changeset	6330
a61af66fc99e Initial load duke parents: diff changeset	6331 // Load Effective Address
a61af66fc99e Initial load duke parents: diff changeset	6332 instruct leaP8(eRegP dst, indOffset8 mem) %{
a61af66fc99e Initial load duke parents: diff changeset	6333 match(Set dst mem);
a61af66fc99e Initial load duke parents: diff changeset	6334
a61af66fc99e Initial load duke parents: diff changeset	6335 ins_cost(110);
a61af66fc99e Initial load duke parents: diff changeset	6336 format %{ "LEA $dst,$mem" %}
a61af66fc99e Initial load duke parents: diff changeset	6337 opcode(0x8D);
a61af66fc99e Initial load duke parents: diff changeset	6338 ins_encode( OpcP, RegMem(dst,mem));
a61af66fc99e Initial load duke parents: diff changeset	6339 ins_pipe( ialu_reg_reg_fat );
a61af66fc99e Initial load duke parents: diff changeset	6340 %}
a61af66fc99e Initial load duke parents: diff changeset	6341
a61af66fc99e Initial load duke parents: diff changeset	6342 instruct leaP32(eRegP dst, indOffset32 mem) %{
a61af66fc99e Initial load duke parents: diff changeset	6343 match(Set dst mem);
a61af66fc99e Initial load duke parents: diff changeset	6344
a61af66fc99e Initial load duke parents: diff changeset	6345 ins_cost(110);
a61af66fc99e Initial load duke parents: diff changeset	6346 format %{ "LEA $dst,$mem" %}
a61af66fc99e Initial load duke parents: diff changeset	6347 opcode(0x8D);
a61af66fc99e Initial load duke parents: diff changeset	6348 ins_encode( OpcP, RegMem(dst,mem));
a61af66fc99e Initial load duke parents: diff changeset	6349 ins_pipe( ialu_reg_reg_fat );
a61af66fc99e Initial load duke parents: diff changeset	6350 %}
a61af66fc99e Initial load duke parents: diff changeset	6351
a61af66fc99e Initial load duke parents: diff changeset	6352 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
a61af66fc99e Initial load duke parents: diff changeset	6353 match(Set dst mem);
a61af66fc99e Initial load duke parents: diff changeset	6354
a61af66fc99e Initial load duke parents: diff changeset	6355 ins_cost(110);
a61af66fc99e Initial load duke parents: diff changeset	6356 format %{ "LEA $dst,$mem" %}
a61af66fc99e Initial load duke parents: diff changeset	6357 opcode(0x8D);
a61af66fc99e Initial load duke parents: diff changeset	6358 ins_encode( OpcP, RegMem(dst,mem));
a61af66fc99e Initial load duke parents: diff changeset	6359 ins_pipe( ialu_reg_reg_fat );
a61af66fc99e Initial load duke parents: diff changeset	6360 %}
a61af66fc99e Initial load duke parents: diff changeset	6361
a61af66fc99e Initial load duke parents: diff changeset	6362 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
a61af66fc99e Initial load duke parents: diff changeset	6363 match(Set dst mem);
a61af66fc99e Initial load duke parents: diff changeset	6364
a61af66fc99e Initial load duke parents: diff changeset	6365 ins_cost(110);
a61af66fc99e Initial load duke parents: diff changeset	6366 format %{ "LEA $dst,$mem" %}
a61af66fc99e Initial load duke parents: diff changeset	6367 opcode(0x8D);
a61af66fc99e Initial load duke parents: diff changeset	6368 ins_encode( OpcP, RegMem(dst,mem));
a61af66fc99e Initial load duke parents: diff changeset	6369 ins_pipe( ialu_reg_reg_fat );
a61af66fc99e Initial load duke parents: diff changeset	6370 %}
a61af66fc99e Initial load duke parents: diff changeset	6371
a61af66fc99e Initial load duke parents: diff changeset	6372 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
a61af66fc99e Initial load duke parents: diff changeset	6373 match(Set dst mem);
a61af66fc99e Initial load duke parents: diff changeset	6374
a61af66fc99e Initial load duke parents: diff changeset	6375 ins_cost(110);
a61af66fc99e Initial load duke parents: diff changeset	6376 format %{ "LEA $dst,$mem" %}
a61af66fc99e Initial load duke parents: diff changeset	6377 opcode(0x8D);
a61af66fc99e Initial load duke parents: diff changeset	6378 ins_encode( OpcP, RegMem(dst,mem));
a61af66fc99e Initial load duke parents: diff changeset	6379 ins_pipe( ialu_reg_reg_fat );
a61af66fc99e Initial load duke parents: diff changeset	6380 %}
a61af66fc99e Initial load duke parents: diff changeset	6381
a61af66fc99e Initial load duke parents: diff changeset	6382 // Load Constant
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	6383 instruct loadConI(rRegI dst, immI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6384 match(Set dst src);
a61af66fc99e Initial load duke parents: diff changeset	6385
a61af66fc99e Initial load duke parents: diff changeset	6386 format %{ "MOV $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	6387 ins_encode( LdImmI(dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	6388 ins_pipe( ialu_reg_fat );
a61af66fc99e Initial load duke parents: diff changeset	6389 %}
a61af66fc99e Initial load duke parents: diff changeset	6390
a61af66fc99e Initial load duke parents: diff changeset	6391 // Load Constant zero
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	6392 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6393 match(Set dst src);
a61af66fc99e Initial load duke parents: diff changeset	6394 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	6395
a61af66fc99e Initial load duke parents: diff changeset	6396 ins_cost(50);
a61af66fc99e Initial load duke parents: diff changeset	6397 format %{ "XOR $dst,$dst" %}
a61af66fc99e Initial load duke parents: diff changeset	6398 opcode(0x33); /* + rd */
a61af66fc99e Initial load duke parents: diff changeset	6399 ins_encode( OpcP, RegReg( dst, dst ) );
a61af66fc99e Initial load duke parents: diff changeset	6400 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	6401 %}
a61af66fc99e Initial load duke parents: diff changeset	6402
a61af66fc99e Initial load duke parents: diff changeset	6403 instruct loadConP(eRegP dst, immP src) %{
a61af66fc99e Initial load duke parents: diff changeset	6404 match(Set dst src);
a61af66fc99e Initial load duke parents: diff changeset	6405
a61af66fc99e Initial load duke parents: diff changeset	6406 format %{ "MOV $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	6407 opcode(0xB8); /* + rd */
a61af66fc99e Initial load duke parents: diff changeset	6408 ins_encode( LdImmP(dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	6409 ins_pipe( ialu_reg_fat );
a61af66fc99e Initial load duke parents: diff changeset	6410 %}
a61af66fc99e Initial load duke parents: diff changeset	6411
a61af66fc99e Initial load duke parents: diff changeset	6412 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	6413 match(Set dst src);
a61af66fc99e Initial load duke parents: diff changeset	6414 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	6415 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	6416 format %{ "MOV $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6417 "MOV $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	6418 opcode(0xB8);
a61af66fc99e Initial load duke parents: diff changeset	6419 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	6420 ins_pipe( ialu_reg_long_fat );
a61af66fc99e Initial load duke parents: diff changeset	6421 %}
a61af66fc99e Initial load duke parents: diff changeset	6422
a61af66fc99e Initial load duke parents: diff changeset	6423 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	6424 match(Set dst src);
a61af66fc99e Initial load duke parents: diff changeset	6425 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	6426 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	6427 format %{ "XOR $dst.lo,$dst.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6428 "XOR $dst.hi,$dst.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	6429 opcode(0x33,0x33);
a61af66fc99e Initial load duke parents: diff changeset	6430 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
a61af66fc99e Initial load duke parents: diff changeset	6431 ins_pipe( ialu_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	6432 %}
a61af66fc99e Initial load duke parents: diff changeset	6433
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6434 // The instruction usage is guarded by predicate in operand immFPR().
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6435 instruct loadConFPR(regFPR dst, immFPR con) %{
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6436 match(Set dst con);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6437 ins_cost(125);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6438 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6439 "FSTP $dst" %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6440 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6441 __ fld_s($constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6442 __ fstp_d($dst$$reg);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6443 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6444 ins_pipe(fpu_reg_con);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6445 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6446
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6447 // The instruction usage is guarded by predicate in operand immFPR0().
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6448 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6449 match(Set dst con);
0 a61af66fc99e Initial load duke parents: diff changeset	6450 ins_cost(125);
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6451 format %{ "FLDZ ST\n\t"
0 a61af66fc99e Initial load duke parents: diff changeset	6452 "FSTP $dst" %}
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6453 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6454 __ fldz();
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6455 __ fstp_d($dst$$reg);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6456 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6457 ins_pipe(fpu_reg_con);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6458 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6459
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6460 // The instruction usage is guarded by predicate in operand immFPR1().
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6461 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6462 match(Set dst con);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6463 ins_cost(125);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6464 format %{ "FLD1 ST\n\t"
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6465 "FSTP $dst" %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6466 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6467 __ fld1();
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6468 __ fstp_d($dst$$reg);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6469 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6470 ins_pipe(fpu_reg_con);
0 a61af66fc99e Initial load duke parents: diff changeset	6471 %}
a61af66fc99e Initial load duke parents: diff changeset	6472
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6473 // The instruction usage is guarded by predicate in operand immF().
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6474 instruct loadConF(regF dst, immF con) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6475 match(Set dst con);
a61af66fc99e Initial load duke parents: diff changeset	6476 ins_cost(125);
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6477 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6478 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6479 __ movflt($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6480 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6481 ins_pipe(pipe_slow);
0 a61af66fc99e Initial load duke parents: diff changeset	6482 %}
a61af66fc99e Initial load duke parents: diff changeset	6483
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6484 // The instruction usage is guarded by predicate in operand immF0().
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6485 instruct loadConF0(regF dst, immF0 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6486 match(Set dst src);
a61af66fc99e Initial load duke parents: diff changeset	6487 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	6488 format %{ "XORPS $dst,$dst\t# float 0.0" %}
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6489 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6490 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6491 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6492 ins_pipe(pipe_slow);
0 a61af66fc99e Initial load duke parents: diff changeset	6493 %}
a61af66fc99e Initial load duke parents: diff changeset	6494
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6495 // The instruction usage is guarded by predicate in operand immDPR().
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6496 instruct loadConDPR(regDPR dst, immDPR con) %{
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6497 match(Set dst con);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6498 ins_cost(125);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6499
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6500 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6501 "FSTP $dst" %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6502 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6503 __ fld_d($constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6504 __ fstp_d($dst$$reg);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6505 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6506 ins_pipe(fpu_reg_con);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6507 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6508
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6509 // The instruction usage is guarded by predicate in operand immDPR0().
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6510 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6511 match(Set dst con);
0 a61af66fc99e Initial load duke parents: diff changeset	6512 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	6513
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6514 format %{ "FLDZ ST\n\t"
0 a61af66fc99e Initial load duke parents: diff changeset	6515 "FSTP $dst" %}
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6516 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6517 __ fldz();
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6518 __ fstp_d($dst$$reg);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6519 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6520 ins_pipe(fpu_reg_con);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6521 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6522
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6523 // The instruction usage is guarded by predicate in operand immDPR1().
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6524 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6525 match(Set dst con);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6526 ins_cost(125);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6527
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6528 format %{ "FLD1 ST\n\t"
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6529 "FSTP $dst" %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6530 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6531 __ fld1();
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6532 __ fstp_d($dst$$reg);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6533 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6534 ins_pipe(fpu_reg_con);
0 a61af66fc99e Initial load duke parents: diff changeset	6535 %}
a61af66fc99e Initial load duke parents: diff changeset	6536
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6537 // The instruction usage is guarded by predicate in operand immD().
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6538 instruct loadConD(regD dst, immD con) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6539 match(Set dst con);
a61af66fc99e Initial load duke parents: diff changeset	6540 ins_cost(125);
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6541 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6542 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6543 __ movdbl($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6544 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	6545 ins_pipe(pipe_slow);
0 a61af66fc99e Initial load duke parents: diff changeset	6546 %}
a61af66fc99e Initial load duke parents: diff changeset	6547
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6548 // The instruction usage is guarded by predicate in operand immD0().
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6549 instruct loadConD0(regD dst, immD0 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6550 match(Set dst src);
a61af66fc99e Initial load duke parents: diff changeset	6551 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	6552 format %{ "XORPD $dst,$dst\t# double 0.0" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6553 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6554 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6555 %}
0 a61af66fc99e Initial load duke parents: diff changeset	6556 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	6557 %}
a61af66fc99e Initial load duke parents: diff changeset	6558
a61af66fc99e Initial load duke parents: diff changeset	6559 // Load Stack Slot
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	6560 instruct loadSSI(rRegI dst, stackSlotI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6561 match(Set dst src);
a61af66fc99e Initial load duke parents: diff changeset	6562 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	6563
a61af66fc99e Initial load duke parents: diff changeset	6564 format %{ "MOV $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	6565 opcode(0x8B);
a61af66fc99e Initial load duke parents: diff changeset	6566 ins_encode( OpcP, RegMem(dst,src));
a61af66fc99e Initial load duke parents: diff changeset	6567 ins_pipe( ialu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	6568 %}
a61af66fc99e Initial load duke parents: diff changeset	6569
a61af66fc99e Initial load duke parents: diff changeset	6570 instruct loadSSL(eRegL dst, stackSlotL src) %{
a61af66fc99e Initial load duke parents: diff changeset	6571 match(Set dst src);
a61af66fc99e Initial load duke parents: diff changeset	6572
a61af66fc99e Initial load duke parents: diff changeset	6573 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	6574 format %{ "MOV $dst,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6575 "MOV $dst+4,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	6576 opcode(0x8B, 0x8B);
a61af66fc99e Initial load duke parents: diff changeset	6577 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	6578 ins_pipe( ialu_mem_long_reg );
a61af66fc99e Initial load duke parents: diff changeset	6579 %}
a61af66fc99e Initial load duke parents: diff changeset	6580
a61af66fc99e Initial load duke parents: diff changeset	6581 // Load Stack Slot
a61af66fc99e Initial load duke parents: diff changeset	6582 instruct loadSSP(eRegP dst, stackSlotP src) %{
a61af66fc99e Initial load duke parents: diff changeset	6583 match(Set dst src);
a61af66fc99e Initial load duke parents: diff changeset	6584 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	6585
a61af66fc99e Initial load duke parents: diff changeset	6586 format %{ "MOV $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	6587 opcode(0x8B);
a61af66fc99e Initial load duke parents: diff changeset	6588 ins_encode( OpcP, RegMem(dst,src));
a61af66fc99e Initial load duke parents: diff changeset	6589 ins_pipe( ialu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	6590 %}
a61af66fc99e Initial load duke parents: diff changeset	6591
a61af66fc99e Initial load duke parents: diff changeset	6592 // Load Stack Slot
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6593 instruct loadSSF(regFPR dst, stackSlotF src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6594 match(Set dst src);
a61af66fc99e Initial load duke parents: diff changeset	6595 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	6596
a61af66fc99e Initial load duke parents: diff changeset	6597 format %{ "FLD_S $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6598 "FSTP $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	6599 opcode(0xD9); /* D9 /0, FLD m32real */
a61af66fc99e Initial load duke parents: diff changeset	6600 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6601 Pop_Reg_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	6602 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	6603 %}
a61af66fc99e Initial load duke parents: diff changeset	6604
a61af66fc99e Initial load duke parents: diff changeset	6605 // Load Stack Slot
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6606 instruct loadSSD(regDPR dst, stackSlotD src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6607 match(Set dst src);
a61af66fc99e Initial load duke parents: diff changeset	6608 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	6609
a61af66fc99e Initial load duke parents: diff changeset	6610 format %{ "FLD_D $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6611 "FSTP $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	6612 opcode(0xDD); /* DD /0, FLD m64real */
a61af66fc99e Initial load duke parents: diff changeset	6613 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6614 Pop_Reg_DPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	6615 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	6616 %}
a61af66fc99e Initial load duke parents: diff changeset	6617
a61af66fc99e Initial load duke parents: diff changeset	6618 // Prefetch instructions.
a61af66fc99e Initial load duke parents: diff changeset	6619 // Must be safe to execute with invalid address (cannot fault).
a61af66fc99e Initial load duke parents: diff changeset	6620
a61af66fc99e Initial load duke parents: diff changeset	6621 instruct prefetchr0( memory mem ) %{
2479 15c9a0e16269 7035713: 3DNow Prefetch Instruction Support kvn parents: 2401 diff changeset	6622 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
0 a61af66fc99e Initial load duke parents: diff changeset	6623 match(PrefetchRead mem);
a61af66fc99e Initial load duke parents: diff changeset	6624 ins_cost(0);
a61af66fc99e Initial load duke parents: diff changeset	6625 size(0);
a61af66fc99e Initial load duke parents: diff changeset	6626 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
a61af66fc99e Initial load duke parents: diff changeset	6627 ins_encode();
a61af66fc99e Initial load duke parents: diff changeset	6628 ins_pipe(empty);
a61af66fc99e Initial load duke parents: diff changeset	6629 %}
a61af66fc99e Initial load duke parents: diff changeset	6630
a61af66fc99e Initial load duke parents: diff changeset	6631 instruct prefetchr( memory mem ) %{
2479 15c9a0e16269 7035713: 3DNow Prefetch Instruction Support kvn parents: 2401 diff changeset	6632 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() \|\| ReadPrefetchInstr==3);
0 a61af66fc99e Initial load duke parents: diff changeset	6633 match(PrefetchRead mem);
a61af66fc99e Initial load duke parents: diff changeset	6634 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	6635
a61af66fc99e Initial load duke parents: diff changeset	6636 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
3854 1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6637 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6638 __ prefetchr($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6639 %}
0 a61af66fc99e Initial load duke parents: diff changeset	6640 ins_pipe(ialu_mem);
a61af66fc99e Initial load duke parents: diff changeset	6641 %}
a61af66fc99e Initial load duke parents: diff changeset	6642
a61af66fc99e Initial load duke parents: diff changeset	6643 instruct prefetchrNTA( memory mem ) %{
a61af66fc99e Initial load duke parents: diff changeset	6644 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
a61af66fc99e Initial load duke parents: diff changeset	6645 match(PrefetchRead mem);
a61af66fc99e Initial load duke parents: diff changeset	6646 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	6647
a61af66fc99e Initial load duke parents: diff changeset	6648 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
3854 1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6649 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6650 __ prefetchnta($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6651 %}
0 a61af66fc99e Initial load duke parents: diff changeset	6652 ins_pipe(ialu_mem);
a61af66fc99e Initial load duke parents: diff changeset	6653 %}
a61af66fc99e Initial load duke parents: diff changeset	6654
a61af66fc99e Initial load duke parents: diff changeset	6655 instruct prefetchrT0( memory mem ) %{
a61af66fc99e Initial load duke parents: diff changeset	6656 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
a61af66fc99e Initial load duke parents: diff changeset	6657 match(PrefetchRead mem);
a61af66fc99e Initial load duke parents: diff changeset	6658 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	6659
a61af66fc99e Initial load duke parents: diff changeset	6660 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
3854 1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6661 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6662 __ prefetcht0($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6663 %}
0 a61af66fc99e Initial load duke parents: diff changeset	6664 ins_pipe(ialu_mem);
a61af66fc99e Initial load duke parents: diff changeset	6665 %}
a61af66fc99e Initial load duke parents: diff changeset	6666
a61af66fc99e Initial load duke parents: diff changeset	6667 instruct prefetchrT2( memory mem ) %{
a61af66fc99e Initial load duke parents: diff changeset	6668 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
a61af66fc99e Initial load duke parents: diff changeset	6669 match(PrefetchRead mem);
a61af66fc99e Initial load duke parents: diff changeset	6670 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	6671
a61af66fc99e Initial load duke parents: diff changeset	6672 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
3854 1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6673 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6674 __ prefetcht2($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6675 %}
0 a61af66fc99e Initial load duke parents: diff changeset	6676 ins_pipe(ialu_mem);
a61af66fc99e Initial load duke parents: diff changeset	6677 %}
a61af66fc99e Initial load duke parents: diff changeset	6678
a61af66fc99e Initial load duke parents: diff changeset	6679 instruct prefetchw0( memory mem ) %{
2479 15c9a0e16269 7035713: 3DNow Prefetch Instruction Support kvn parents: 2401 diff changeset	6680 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
0 a61af66fc99e Initial load duke parents: diff changeset	6681 match(PrefetchWrite mem);
a61af66fc99e Initial load duke parents: diff changeset	6682 ins_cost(0);
a61af66fc99e Initial load duke parents: diff changeset	6683 size(0);
a61af66fc99e Initial load duke parents: diff changeset	6684 format %{ "Prefetch (non-SSE is empty encoding)" %}
a61af66fc99e Initial load duke parents: diff changeset	6685 ins_encode();
a61af66fc99e Initial load duke parents: diff changeset	6686 ins_pipe(empty);
a61af66fc99e Initial load duke parents: diff changeset	6687 %}
a61af66fc99e Initial load duke parents: diff changeset	6688
a61af66fc99e Initial load duke parents: diff changeset	6689 instruct prefetchw( memory mem ) %{
3854 1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6690 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
0 a61af66fc99e Initial load duke parents: diff changeset	6691 match( PrefetchWrite mem );
a61af66fc99e Initial load duke parents: diff changeset	6692 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	6693
a61af66fc99e Initial load duke parents: diff changeset	6694 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
3854 1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6695 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6696 __ prefetchw($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6697 %}
0 a61af66fc99e Initial load duke parents: diff changeset	6698 ins_pipe(ialu_mem);
a61af66fc99e Initial load duke parents: diff changeset	6699 %}
a61af66fc99e Initial load duke parents: diff changeset	6700
a61af66fc99e Initial load duke parents: diff changeset	6701 instruct prefetchwNTA( memory mem ) %{
3854 1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6702 predicate(UseSSE>=1);
0 a61af66fc99e Initial load duke parents: diff changeset	6703 match(PrefetchWrite mem);
a61af66fc99e Initial load duke parents: diff changeset	6704 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	6705
a61af66fc99e Initial load duke parents: diff changeset	6706 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
3854 1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6707 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6708 __ prefetchnta($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6709 %}
0 a61af66fc99e Initial load duke parents: diff changeset	6710 ins_pipe(ialu_mem);
a61af66fc99e Initial load duke parents: diff changeset	6711 %}
a61af66fc99e Initial load duke parents: diff changeset	6712
3854 1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6713 // Prefetch instructions for allocation.
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6714
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6715 instruct prefetchAlloc0( memory mem ) %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6716 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6717 match(PrefetchAllocation mem);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6718 ins_cost(0);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6719 size(0);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6720 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6721 ins_encode();
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6722 ins_pipe(empty);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6723 %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6724
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6725 instruct prefetchAlloc( memory mem ) %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6726 predicate(AllocatePrefetchInstr==3);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6727 match( PrefetchAllocation mem );
0 a61af66fc99e Initial load duke parents: diff changeset	6728 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	6729
3854 1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6730 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6731 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6732 __ prefetchw($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6733 %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6734 ins_pipe(ialu_mem);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6735 %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6736
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6737 instruct prefetchAllocNTA( memory mem ) %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6738 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6739 match(PrefetchAllocation mem);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6740 ins_cost(100);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6741
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6742 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6743 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6744 __ prefetchnta($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6745 %}
0 a61af66fc99e Initial load duke parents: diff changeset	6746 ins_pipe(ialu_mem);
a61af66fc99e Initial load duke parents: diff changeset	6747 %}
a61af66fc99e Initial load duke parents: diff changeset	6748
3854 1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6749 instruct prefetchAllocT0( memory mem ) %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6750 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6751 match(PrefetchAllocation mem);
0 a61af66fc99e Initial load duke parents: diff changeset	6752 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	6753
3854 1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6754 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6755 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6756 __ prefetcht0($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6757 %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6758 ins_pipe(ialu_mem);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6759 %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6760
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6761 instruct prefetchAllocT2( memory mem ) %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6762 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6763 match(PrefetchAllocation mem);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6764 ins_cost(100);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6765
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6766 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6767 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6768 __ prefetcht2($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	6769 %}
0 a61af66fc99e Initial load duke parents: diff changeset	6770 ins_pipe(ialu_mem);
a61af66fc99e Initial load duke parents: diff changeset	6771 %}
a61af66fc99e Initial load duke parents: diff changeset	6772
a61af66fc99e Initial load duke parents: diff changeset	6773 //----------Store Instructions-------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	6774
a61af66fc99e Initial load duke parents: diff changeset	6775 // Store Byte
a61af66fc99e Initial load duke parents: diff changeset	6776 instruct storeB(memory mem, xRegI src) %{
a61af66fc99e Initial load duke parents: diff changeset	6777 match(Set mem (StoreB mem src));
a61af66fc99e Initial load duke parents: diff changeset	6778
a61af66fc99e Initial load duke parents: diff changeset	6779 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	6780 format %{ "MOV8 $mem,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	6781 opcode(0x88);
a61af66fc99e Initial load duke parents: diff changeset	6782 ins_encode( OpcP, RegMem( src, mem ) );
a61af66fc99e Initial load duke parents: diff changeset	6783 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	6784 %}
a61af66fc99e Initial load duke parents: diff changeset	6785
a61af66fc99e Initial load duke parents: diff changeset	6786 // Store Char/Short
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	6787 instruct storeC(memory mem, rRegI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6788 match(Set mem (StoreC mem src));
a61af66fc99e Initial load duke parents: diff changeset	6789
a61af66fc99e Initial load duke parents: diff changeset	6790 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	6791 format %{ "MOV16 $mem,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	6792 opcode(0x89, 0x66);
a61af66fc99e Initial load duke parents: diff changeset	6793 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
a61af66fc99e Initial load duke parents: diff changeset	6794 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	6795 %}
a61af66fc99e Initial load duke parents: diff changeset	6796
a61af66fc99e Initial load duke parents: diff changeset	6797 // Store Integer
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	6798 instruct storeI(memory mem, rRegI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6799 match(Set mem (StoreI mem src));
a61af66fc99e Initial load duke parents: diff changeset	6800
a61af66fc99e Initial load duke parents: diff changeset	6801 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	6802 format %{ "MOV $mem,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	6803 opcode(0x89);
a61af66fc99e Initial load duke parents: diff changeset	6804 ins_encode( OpcP, RegMem( src, mem ) );
a61af66fc99e Initial load duke parents: diff changeset	6805 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	6806 %}
a61af66fc99e Initial load duke parents: diff changeset	6807
a61af66fc99e Initial load duke parents: diff changeset	6808 // Store Long
a61af66fc99e Initial load duke parents: diff changeset	6809 instruct storeL(long_memory mem, eRegL src) %{
a61af66fc99e Initial load duke parents: diff changeset	6810 predicate(!((StoreLNode*)n)->require_atomic_access());
a61af66fc99e Initial load duke parents: diff changeset	6811 match(Set mem (StoreL mem src));
a61af66fc99e Initial load duke parents: diff changeset	6812
a61af66fc99e Initial load duke parents: diff changeset	6813 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	6814 format %{ "MOV $mem,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6815 "MOV $mem+4,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	6816 opcode(0x89, 0x89);
a61af66fc99e Initial load duke parents: diff changeset	6817 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
a61af66fc99e Initial load duke parents: diff changeset	6818 ins_pipe( ialu_mem_long_reg );
a61af66fc99e Initial load duke parents: diff changeset	6819 %}
a61af66fc99e Initial load duke parents: diff changeset	6820
824 18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6821 // Store Long to Integer
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6822 instruct storeL2I(memory mem, eRegL src) %{
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6823 match(Set mem (StoreI mem (ConvL2I src)));
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6824
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6825 format %{ "MOV $mem,$src.lo\t# long -> int" %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6826 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6827 __ movl($mem$$Address, $src$$Register);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6828 %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6829 ins_pipe(ialu_mem_reg);
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6830 %}
18a08a7e16b5 5057225: Remove useless I2L conversions twisti parents: 785 diff changeset	6831
0 a61af66fc99e Initial load duke parents: diff changeset	6832 // Volatile Store Long. Must be atomic, so move it into
a61af66fc99e Initial load duke parents: diff changeset	6833 // the FP TOS and then do a 64-bit FIST. Has to probe the
a61af66fc99e Initial load duke parents: diff changeset	6834 // target address before the store (for null-ptr checks)
a61af66fc99e Initial load duke parents: diff changeset	6835 // so the memory operand is used twice in the encoding.
a61af66fc99e Initial load duke parents: diff changeset	6836 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
a61af66fc99e Initial load duke parents: diff changeset	6837 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
a61af66fc99e Initial load duke parents: diff changeset	6838 match(Set mem (StoreL mem src));
a61af66fc99e Initial load duke parents: diff changeset	6839 effect( KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	6840 ins_cost(400);
a61af66fc99e Initial load duke parents: diff changeset	6841 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6842 "FILD $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6843 "FISTp $mem\t # 64-bit atomic volatile long store" %}
a61af66fc99e Initial load duke parents: diff changeset	6844 opcode(0x3B);
a61af66fc99e Initial load duke parents: diff changeset	6845 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
a61af66fc99e Initial load duke parents: diff changeset	6846 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	6847 %}
a61af66fc99e Initial load duke parents: diff changeset	6848
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6849 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6850 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
a61af66fc99e Initial load duke parents: diff changeset	6851 match(Set mem (StoreL mem src));
a61af66fc99e Initial load duke parents: diff changeset	6852 effect( TEMP tmp, KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	6853 ins_cost(380);
a61af66fc99e Initial load duke parents: diff changeset	6854 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6855 "MOVSD $tmp,$src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6856 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6857 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6858 __ cmpl(rax, $mem$$Address);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6859 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6860 __ movdbl($mem$$Address, $tmp$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6861 %}
0 a61af66fc99e Initial load duke parents: diff changeset	6862 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	6863 %}
a61af66fc99e Initial load duke parents: diff changeset	6864
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6865 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6866 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
a61af66fc99e Initial load duke parents: diff changeset	6867 match(Set mem (StoreL mem src));
a61af66fc99e Initial load duke parents: diff changeset	6868 effect( TEMP tmp2 , TEMP tmp, KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	6869 ins_cost(360);
a61af66fc99e Initial load duke parents: diff changeset	6870 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6871 "MOVD $tmp,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6872 "MOVD $tmp2,$src.hi\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6873 "PUNPCKLDQ $tmp,$tmp2\n\t"
a61af66fc99e Initial load duke parents: diff changeset	6874 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6875 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6876 __ cmpl(rax, $mem$$Address);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6877 __ movdl($tmp$$XMMRegister, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6878 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6879 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6880 __ movdbl($mem$$Address, $tmp$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6881 %}
0 a61af66fc99e Initial load duke parents: diff changeset	6882 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	6883 %}
a61af66fc99e Initial load duke parents: diff changeset	6884
a61af66fc99e Initial load duke parents: diff changeset	6885 // Store Pointer; for storing unknown oops and raw pointers
a61af66fc99e Initial load duke parents: diff changeset	6886 instruct storeP(memory mem, anyRegP src) %{
a61af66fc99e Initial load duke parents: diff changeset	6887 match(Set mem (StoreP mem src));
a61af66fc99e Initial load duke parents: diff changeset	6888
a61af66fc99e Initial load duke parents: diff changeset	6889 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	6890 format %{ "MOV $mem,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	6891 opcode(0x89);
a61af66fc99e Initial load duke parents: diff changeset	6892 ins_encode( OpcP, RegMem( src, mem ) );
a61af66fc99e Initial load duke parents: diff changeset	6893 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	6894 %}
a61af66fc99e Initial load duke parents: diff changeset	6895
a61af66fc99e Initial load duke parents: diff changeset	6896 // Store Integer Immediate
a61af66fc99e Initial load duke parents: diff changeset	6897 instruct storeImmI(memory mem, immI src) %{
a61af66fc99e Initial load duke parents: diff changeset	6898 match(Set mem (StoreI mem src));
a61af66fc99e Initial load duke parents: diff changeset	6899
a61af66fc99e Initial load duke parents: diff changeset	6900 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	6901 format %{ "MOV $mem,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	6902 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load duke parents: diff changeset	6903 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
a61af66fc99e Initial load duke parents: diff changeset	6904 ins_pipe( ialu_mem_imm );
a61af66fc99e Initial load duke parents: diff changeset	6905 %}
a61af66fc99e Initial load duke parents: diff changeset	6906
a61af66fc99e Initial load duke parents: diff changeset	6907 // Store Short/Char Immediate
a61af66fc99e Initial load duke parents: diff changeset	6908 instruct storeImmI16(memory mem, immI16 src) %{
a61af66fc99e Initial load duke parents: diff changeset	6909 predicate(UseStoreImmI16);
a61af66fc99e Initial load duke parents: diff changeset	6910 match(Set mem (StoreC mem src));
a61af66fc99e Initial load duke parents: diff changeset	6911
a61af66fc99e Initial load duke parents: diff changeset	6912 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	6913 format %{ "MOV16 $mem,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	6914 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
a61af66fc99e Initial load duke parents: diff changeset	6915 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
a61af66fc99e Initial load duke parents: diff changeset	6916 ins_pipe( ialu_mem_imm );
a61af66fc99e Initial load duke parents: diff changeset	6917 %}
a61af66fc99e Initial load duke parents: diff changeset	6918
a61af66fc99e Initial load duke parents: diff changeset	6919 // Store Pointer Immediate; null pointers or constant oops that do not
a61af66fc99e Initial load duke parents: diff changeset	6920 // need card-mark barriers.
a61af66fc99e Initial load duke parents: diff changeset	6921 instruct storeImmP(memory mem, immP src) %{
a61af66fc99e Initial load duke parents: diff changeset	6922 match(Set mem (StoreP mem src));
a61af66fc99e Initial load duke parents: diff changeset	6923
a61af66fc99e Initial load duke parents: diff changeset	6924 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	6925 format %{ "MOV $mem,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	6926 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load duke parents: diff changeset	6927 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
a61af66fc99e Initial load duke parents: diff changeset	6928 ins_pipe( ialu_mem_imm );
a61af66fc99e Initial load duke parents: diff changeset	6929 %}
a61af66fc99e Initial load duke parents: diff changeset	6930
a61af66fc99e Initial load duke parents: diff changeset	6931 // Store Byte Immediate
a61af66fc99e Initial load duke parents: diff changeset	6932 instruct storeImmB(memory mem, immI8 src) %{
a61af66fc99e Initial load duke parents: diff changeset	6933 match(Set mem (StoreB mem src));
a61af66fc99e Initial load duke parents: diff changeset	6934
a61af66fc99e Initial load duke parents: diff changeset	6935 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	6936 format %{ "MOV8 $mem,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	6937 opcode(0xC6); /* C6 /0 */
a61af66fc99e Initial load duke parents: diff changeset	6938 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
a61af66fc99e Initial load duke parents: diff changeset	6939 ins_pipe( ialu_mem_imm );
a61af66fc99e Initial load duke parents: diff changeset	6940 %}
a61af66fc99e Initial load duke parents: diff changeset	6941
a61af66fc99e Initial load duke parents: diff changeset	6942 // Store CMS card-mark Immediate
a61af66fc99e Initial load duke parents: diff changeset	6943 instruct storeImmCM(memory mem, immI8 src) %{
a61af66fc99e Initial load duke parents: diff changeset	6944 match(Set mem (StoreCM mem src));
a61af66fc99e Initial load duke parents: diff changeset	6945
a61af66fc99e Initial load duke parents: diff changeset	6946 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	6947 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
a61af66fc99e Initial load duke parents: diff changeset	6948 opcode(0xC6); /* C6 /0 */
a61af66fc99e Initial load duke parents: diff changeset	6949 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
a61af66fc99e Initial load duke parents: diff changeset	6950 ins_pipe( ialu_mem_imm );
a61af66fc99e Initial load duke parents: diff changeset	6951 %}
a61af66fc99e Initial load duke parents: diff changeset	6952
a61af66fc99e Initial load duke parents: diff changeset	6953 // Store Double
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6954 instruct storeDPR( memory mem, regDPR1 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6955 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	6956 match(Set mem (StoreD mem src));
a61af66fc99e Initial load duke parents: diff changeset	6957
a61af66fc99e Initial load duke parents: diff changeset	6958 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	6959 format %{ "FST_D $mem,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	6960 opcode(0xDD); /* DD /2 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6961 ins_encode( enc_FPR_store(mem,src) );
0 a61af66fc99e Initial load duke parents: diff changeset	6962 ins_pipe( fpu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	6963 %}
a61af66fc99e Initial load duke parents: diff changeset	6964
a61af66fc99e Initial load duke parents: diff changeset	6965 // Store double does rounding on x86
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6966 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6967 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	6968 match(Set mem (StoreD mem (RoundDouble src)));
a61af66fc99e Initial load duke parents: diff changeset	6969
a61af66fc99e Initial load duke parents: diff changeset	6970 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	6971 format %{ "FST_D $mem,$src\t# round" %}
a61af66fc99e Initial load duke parents: diff changeset	6972 opcode(0xDD); /* DD /2 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6973 ins_encode( enc_FPR_store(mem,src) );
0 a61af66fc99e Initial load duke parents: diff changeset	6974 ins_pipe( fpu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	6975 %}
a61af66fc99e Initial load duke parents: diff changeset	6976
a61af66fc99e Initial load duke parents: diff changeset	6977 // Store XMM register to memory (double-precision floating points)
a61af66fc99e Initial load duke parents: diff changeset	6978 // MOVSD instruction
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6979 instruct storeD(memory mem, regD src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6980 predicate(UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	6981 match(Set mem (StoreD mem src));
a61af66fc99e Initial load duke parents: diff changeset	6982 ins_cost(95);
a61af66fc99e Initial load duke parents: diff changeset	6983 format %{ "MOVSD $mem,$src" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6984 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6985 __ movdbl($mem$$Address, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6986 %}
0 a61af66fc99e Initial load duke parents: diff changeset	6987 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	6988 %}
a61af66fc99e Initial load duke parents: diff changeset	6989
a61af66fc99e Initial load duke parents: diff changeset	6990 // Store XMM register to memory (single-precision floating point)
a61af66fc99e Initial load duke parents: diff changeset	6991 // MOVSS instruction
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	6992 instruct storeF(memory mem, regF src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	6993 predicate(UseSSE>=1);
a61af66fc99e Initial load duke parents: diff changeset	6994 match(Set mem (StoreF mem src));
a61af66fc99e Initial load duke parents: diff changeset	6995 ins_cost(95);
a61af66fc99e Initial load duke parents: diff changeset	6996 format %{ "MOVSS $mem,$src" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6997 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6998 __ movflt($mem$$Address, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	6999 %}
0 a61af66fc99e Initial load duke parents: diff changeset	7000 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	7001 %}
a61af66fc99e Initial load duke parents: diff changeset	7002
a61af66fc99e Initial load duke parents: diff changeset	7003 // Store Float
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7004 instruct storeFPR( memory mem, regFPR1 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7005 predicate(UseSSE==0);
a61af66fc99e Initial load duke parents: diff changeset	7006 match(Set mem (StoreF mem src));
a61af66fc99e Initial load duke parents: diff changeset	7007
a61af66fc99e Initial load duke parents: diff changeset	7008 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	7009 format %{ "FST_S $mem,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7010 opcode(0xD9); /* D9 /2 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7011 ins_encode( enc_FPR_store(mem,src) );
0 a61af66fc99e Initial load duke parents: diff changeset	7012 ins_pipe( fpu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	7013 %}
a61af66fc99e Initial load duke parents: diff changeset	7014
a61af66fc99e Initial load duke parents: diff changeset	7015 // Store Float does rounding on x86
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7016 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7017 predicate(UseSSE==0);
a61af66fc99e Initial load duke parents: diff changeset	7018 match(Set mem (StoreF mem (RoundFloat src)));
a61af66fc99e Initial load duke parents: diff changeset	7019
a61af66fc99e Initial load duke parents: diff changeset	7020 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	7021 format %{ "FST_S $mem,$src\t# round" %}
a61af66fc99e Initial load duke parents: diff changeset	7022 opcode(0xD9); /* D9 /2 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7023 ins_encode( enc_FPR_store(mem,src) );
0 a61af66fc99e Initial load duke parents: diff changeset	7024 ins_pipe( fpu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	7025 %}
a61af66fc99e Initial load duke parents: diff changeset	7026
a61af66fc99e Initial load duke parents: diff changeset	7027 // Store Float does rounding on x86
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7028 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7029 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	7030 match(Set mem (StoreF mem (ConvD2F src)));
a61af66fc99e Initial load duke parents: diff changeset	7031
a61af66fc99e Initial load duke parents: diff changeset	7032 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	7033 format %{ "FST_S $mem,$src\t# D-round" %}
a61af66fc99e Initial load duke parents: diff changeset	7034 opcode(0xD9); /* D9 /2 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7035 ins_encode( enc_FPR_store(mem,src) );
0 a61af66fc99e Initial load duke parents: diff changeset	7036 ins_pipe( fpu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	7037 %}
a61af66fc99e Initial load duke parents: diff changeset	7038
a61af66fc99e Initial load duke parents: diff changeset	7039 // Store immediate Float value (it is faster than store from FPU register)
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7040 // The instruction usage is guarded by predicate in operand immFPR().
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7041 instruct storeFPR_imm( memory mem, immFPR src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7042 match(Set mem (StoreF mem src));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7043
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7044 ins_cost(50);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7045 format %{ "MOV $mem,$src\t# store float" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7046 opcode(0xC7); /* C7 /0 */
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7047 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7048 ins_pipe( ialu_mem_imm );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7049 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7050
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7051 // Store immediate Float value (it is faster than store from XMM register)
0 a61af66fc99e Initial load duke parents: diff changeset	7052 // The instruction usage is guarded by predicate in operand immF().
a61af66fc99e Initial load duke parents: diff changeset	7053 instruct storeF_imm( memory mem, immF src) %{
a61af66fc99e Initial load duke parents: diff changeset	7054 match(Set mem (StoreF mem src));
a61af66fc99e Initial load duke parents: diff changeset	7055
a61af66fc99e Initial load duke parents: diff changeset	7056 ins_cost(50);
a61af66fc99e Initial load duke parents: diff changeset	7057 format %{ "MOV $mem,$src\t# store float" %}
a61af66fc99e Initial load duke parents: diff changeset	7058 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load duke parents: diff changeset	7059 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
a61af66fc99e Initial load duke parents: diff changeset	7060 ins_pipe( ialu_mem_imm );
a61af66fc99e Initial load duke parents: diff changeset	7061 %}
a61af66fc99e Initial load duke parents: diff changeset	7062
a61af66fc99e Initial load duke parents: diff changeset	7063 // Store Integer to stack slot
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7064 instruct storeSSI(stackSlotI dst, rRegI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7065 match(Set dst src);
a61af66fc99e Initial load duke parents: diff changeset	7066
a61af66fc99e Initial load duke parents: diff changeset	7067 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	7068 format %{ "MOV $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7069 opcode(0x89);
a61af66fc99e Initial load duke parents: diff changeset	7070 ins_encode( OpcPRegSS( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	7071 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	7072 %}
a61af66fc99e Initial load duke parents: diff changeset	7073
a61af66fc99e Initial load duke parents: diff changeset	7074 // Store Integer to stack slot
a61af66fc99e Initial load duke parents: diff changeset	7075 instruct storeSSP(stackSlotP dst, eRegP src) %{
a61af66fc99e Initial load duke parents: diff changeset	7076 match(Set dst src);
a61af66fc99e Initial load duke parents: diff changeset	7077
a61af66fc99e Initial load duke parents: diff changeset	7078 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	7079 format %{ "MOV $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7080 opcode(0x89);
a61af66fc99e Initial load duke parents: diff changeset	7081 ins_encode( OpcPRegSS( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	7082 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	7083 %}
a61af66fc99e Initial load duke parents: diff changeset	7084
a61af66fc99e Initial load duke parents: diff changeset	7085 // Store Long to stack slot
a61af66fc99e Initial load duke parents: diff changeset	7086 instruct storeSSL(stackSlotL dst, eRegL src) %{
a61af66fc99e Initial load duke parents: diff changeset	7087 match(Set dst src);
a61af66fc99e Initial load duke parents: diff changeset	7088
a61af66fc99e Initial load duke parents: diff changeset	7089 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	7090 format %{ "MOV $dst,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7091 "MOV $dst+4,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	7092 opcode(0x89, 0x89);
a61af66fc99e Initial load duke parents: diff changeset	7093 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
a61af66fc99e Initial load duke parents: diff changeset	7094 ins_pipe( ialu_mem_long_reg );
a61af66fc99e Initial load duke parents: diff changeset	7095 %}
a61af66fc99e Initial load duke parents: diff changeset	7096
a61af66fc99e Initial load duke parents: diff changeset	7097 //----------MemBar Instructions-----------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	7098 // Memory barrier flavors
a61af66fc99e Initial load duke parents: diff changeset	7099
a61af66fc99e Initial load duke parents: diff changeset	7100 instruct membar_acquire() %{
a61af66fc99e Initial load duke parents: diff changeset	7101 match(MemBarAcquire);
a61af66fc99e Initial load duke parents: diff changeset	7102 ins_cost(400);
a61af66fc99e Initial load duke parents: diff changeset	7103
a61af66fc99e Initial load duke parents: diff changeset	7104 size(0);
671 d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7105 format %{ "MEMBAR-acquire ! (empty encoding)" %}
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7106 ins_encode();
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7107 ins_pipe(empty);
0 a61af66fc99e Initial load duke parents: diff changeset	7108 %}
a61af66fc99e Initial load duke parents: diff changeset	7109
a61af66fc99e Initial load duke parents: diff changeset	7110 instruct membar_acquire_lock() %{
3849 f1c12354c3f7 7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths roland parents: 3842 diff changeset	7111 match(MemBarAcquireLock);
0 a61af66fc99e Initial load duke parents: diff changeset	7112 ins_cost(0);
a61af66fc99e Initial load duke parents: diff changeset	7113
a61af66fc99e Initial load duke parents: diff changeset	7114 size(0);
a61af66fc99e Initial load duke parents: diff changeset	7115 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
a61af66fc99e Initial load duke parents: diff changeset	7116 ins_encode( );
a61af66fc99e Initial load duke parents: diff changeset	7117 ins_pipe(empty);
a61af66fc99e Initial load duke parents: diff changeset	7118 %}
a61af66fc99e Initial load duke parents: diff changeset	7119
a61af66fc99e Initial load duke parents: diff changeset	7120 instruct membar_release() %{
a61af66fc99e Initial load duke parents: diff changeset	7121 match(MemBarRelease);
a61af66fc99e Initial load duke parents: diff changeset	7122 ins_cost(400);
a61af66fc99e Initial load duke parents: diff changeset	7123
a61af66fc99e Initial load duke parents: diff changeset	7124 size(0);
671 d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7125 format %{ "MEMBAR-release ! (empty encoding)" %}
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7126 ins_encode( );
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7127 ins_pipe(empty);
0 a61af66fc99e Initial load duke parents: diff changeset	7128 %}
a61af66fc99e Initial load duke parents: diff changeset	7129
a61af66fc99e Initial load duke parents: diff changeset	7130 instruct membar_release_lock() %{
3849 f1c12354c3f7 7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths roland parents: 3842 diff changeset	7131 match(MemBarReleaseLock);
0 a61af66fc99e Initial load duke parents: diff changeset	7132 ins_cost(0);
a61af66fc99e Initial load duke parents: diff changeset	7133
a61af66fc99e Initial load duke parents: diff changeset	7134 size(0);
a61af66fc99e Initial load duke parents: diff changeset	7135 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
a61af66fc99e Initial load duke parents: diff changeset	7136 ins_encode( );
a61af66fc99e Initial load duke parents: diff changeset	7137 ins_pipe(empty);
a61af66fc99e Initial load duke parents: diff changeset	7138 %}
a61af66fc99e Initial load duke parents: diff changeset	7139
671 d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7140 instruct membar_volatile(eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7141 match(MemBarVolatile);
671 d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7142 effect(KILL cr);
0 a61af66fc99e Initial load duke parents: diff changeset	7143 ins_cost(400);
a61af66fc99e Initial load duke parents: diff changeset	7144
671 d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7145 format %{
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7146 $$template
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7147 if (os::is_MP()) {
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7148 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7149 } else {
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7150 $$emit$$"MEMBAR-volatile ! (empty encoding)"
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7151 }
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7152 %}
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7153 ins_encode %{
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7154 __ membar(Assembler::StoreLoad);
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions never parents: 647 diff changeset	7155 %}
0 a61af66fc99e Initial load duke parents: diff changeset	7156 ins_pipe(pipe_slow);
a61af66fc99e Initial load duke parents: diff changeset	7157 %}
a61af66fc99e Initial load duke parents: diff changeset	7158
a61af66fc99e Initial load duke parents: diff changeset	7159 instruct unnecessary_membar_volatile() %{
a61af66fc99e Initial load duke parents: diff changeset	7160 match(MemBarVolatile);
a61af66fc99e Initial load duke parents: diff changeset	7161 predicate(Matcher::post_store_load_barrier(n));
a61af66fc99e Initial load duke parents: diff changeset	7162 ins_cost(0);
a61af66fc99e Initial load duke parents: diff changeset	7163
a61af66fc99e Initial load duke parents: diff changeset	7164 size(0);
a61af66fc99e Initial load duke parents: diff changeset	7165 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
a61af66fc99e Initial load duke parents: diff changeset	7166 ins_encode( );
a61af66fc99e Initial load duke parents: diff changeset	7167 ins_pipe(empty);
a61af66fc99e Initial load duke parents: diff changeset	7168 %}
a61af66fc99e Initial load duke parents: diff changeset	7169
4763 1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems roland parents: 4761 diff changeset	7170 instruct membar_storestore() %{
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems roland parents: 4761 diff changeset	7171 match(MemBarStoreStore);
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems roland parents: 4761 diff changeset	7172 ins_cost(0);
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems roland parents: 4761 diff changeset	7173
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems roland parents: 4761 diff changeset	7174 size(0);
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems roland parents: 4761 diff changeset	7175 format %{ "MEMBAR-storestore (empty encoding)" %}
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems roland parents: 4761 diff changeset	7176 ins_encode( );
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems roland parents: 4761 diff changeset	7177 ins_pipe(empty);
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems roland parents: 4761 diff changeset	7178 %}
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems roland parents: 4761 diff changeset	7179
0 a61af66fc99e Initial load duke parents: diff changeset	7180 //----------Move Instructions--------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	7181 instruct castX2P(eAXRegP dst, eAXRegI src) %{
a61af66fc99e Initial load duke parents: diff changeset	7182 match(Set dst (CastX2P src));
a61af66fc99e Initial load duke parents: diff changeset	7183 format %{ "# X2P $dst, $src" %}
a61af66fc99e Initial load duke parents: diff changeset	7184 ins_encode( /empty encoding/ );
a61af66fc99e Initial load duke parents: diff changeset	7185 ins_cost(0);
a61af66fc99e Initial load duke parents: diff changeset	7186 ins_pipe(empty);
a61af66fc99e Initial load duke parents: diff changeset	7187 %}
a61af66fc99e Initial load duke parents: diff changeset	7188
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7189 instruct castP2X(rRegI dst, eRegP src ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7190 match(Set dst (CastP2X src));
a61af66fc99e Initial load duke parents: diff changeset	7191 ins_cost(50);
a61af66fc99e Initial load duke parents: diff changeset	7192 format %{ "MOV $dst, $src\t# CastP2X" %}
a61af66fc99e Initial load duke parents: diff changeset	7193 ins_encode( enc_Copy( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	7194 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	7195 %}
a61af66fc99e Initial load duke parents: diff changeset	7196
a61af66fc99e Initial load duke parents: diff changeset	7197 //----------Conditional Move---------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	7198 // Conditional move
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7199 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
4047 d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7200 predicate(!VM_Version::supports_cmov() );
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7201 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7202 ins_cost(200);
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7203 format %{ "J$cop,us skip\t# signed cmove\n\t"
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7204 "MOV $dst,$src\n"
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7205 "skip:" %}
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7206 ins_encode %{
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7207 Label Lskip;
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7208 // Invert sense of branch from sense of CMOV
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7209 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7210 __ movl($dst$$Register, $src$$Register);
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7211 __ bind(Lskip);
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7212 %}
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7213 ins_pipe( pipe_cmov_reg );
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7214 %}
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7215
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7216 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
4047 d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7217 predicate(!VM_Version::supports_cmov() );
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7218 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7219 ins_cost(200);
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7220 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7221 "MOV $dst,$src\n"
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7222 "skip:" %}
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7223 ins_encode %{
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7224 Label Lskip;
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7225 // Invert sense of branch from sense of CMOV
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7226 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7227 __ movl($dst$$Register, $src$$Register);
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7228 __ bind(Lskip);
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7229 %}
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7230 ins_pipe( pipe_cmov_reg );
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7231 %}
d8cb48376797 7097546: Optimize use of CMOVE instructions kvn parents: 3854 diff changeset	7232
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7233 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7234 predicate(VM_Version::supports_cmov() );
a61af66fc99e Initial load duke parents: diff changeset	7235 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	7236 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	7237 format %{ "CMOV$cop $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7238 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	7239 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	7240 ins_pipe( pipe_cmov_reg );
a61af66fc99e Initial load duke parents: diff changeset	7241 %}
a61af66fc99e Initial load duke parents: diff changeset	7242
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7243 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7244 predicate(VM_Version::supports_cmov() );
a61af66fc99e Initial load duke parents: diff changeset	7245 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	7246 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	7247 format %{ "CMOV$cop $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7248 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	7249 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	7250 ins_pipe( pipe_cmov_reg );
a61af66fc99e Initial load duke parents: diff changeset	7251 %}
a61af66fc99e Initial load duke parents: diff changeset	7252
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7253 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7254 predicate(VM_Version::supports_cmov() );
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7255 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7256 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7257 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7258 cmovI_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7259 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7260 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7261
0 a61af66fc99e Initial load duke parents: diff changeset	7262 // Conditional move
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7263 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7264 predicate(VM_Version::supports_cmov() );
a61af66fc99e Initial load duke parents: diff changeset	7265 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
a61af66fc99e Initial load duke parents: diff changeset	7266 ins_cost(250);
a61af66fc99e Initial load duke parents: diff changeset	7267 format %{ "CMOV$cop $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7268 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	7269 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	7270 ins_pipe( pipe_cmov_mem );
a61af66fc99e Initial load duke parents: diff changeset	7271 %}
a61af66fc99e Initial load duke parents: diff changeset	7272
a61af66fc99e Initial load duke parents: diff changeset	7273 // Conditional move
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7274 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7275 predicate(VM_Version::supports_cmov() );
a61af66fc99e Initial load duke parents: diff changeset	7276 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
a61af66fc99e Initial load duke parents: diff changeset	7277 ins_cost(250);
a61af66fc99e Initial load duke parents: diff changeset	7278 format %{ "CMOV$cop $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7279 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	7280 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	7281 ins_pipe( pipe_cmov_mem );
a61af66fc99e Initial load duke parents: diff changeset	7282 %}
a61af66fc99e Initial load duke parents: diff changeset	7283
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7284 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7285 predicate(VM_Version::supports_cmov() );
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7286 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7287 ins_cost(250);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7288 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7289 cmovI_memU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7290 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7291 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7292
0 a61af66fc99e Initial load duke parents: diff changeset	7293 // Conditional move
a61af66fc99e Initial load duke parents: diff changeset	7294 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
a61af66fc99e Initial load duke parents: diff changeset	7295 predicate(VM_Version::supports_cmov() );
a61af66fc99e Initial load duke parents: diff changeset	7296 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	7297 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	7298 format %{ "CMOV$cop $dst,$src\t# ptr" %}
a61af66fc99e Initial load duke parents: diff changeset	7299 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	7300 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	7301 ins_pipe( pipe_cmov_reg );
a61af66fc99e Initial load duke parents: diff changeset	7302 %}
a61af66fc99e Initial load duke parents: diff changeset	7303
a61af66fc99e Initial load duke parents: diff changeset	7304 // Conditional move (non-P6 version)
a61af66fc99e Initial load duke parents: diff changeset	7305 // Note: a CMoveP is generated for stubs and native wrappers
a61af66fc99e Initial load duke parents: diff changeset	7306 // regardless of whether we are on a P6, so we
a61af66fc99e Initial load duke parents: diff changeset	7307 // emulate a cmov here
a61af66fc99e Initial load duke parents: diff changeset	7308 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
a61af66fc99e Initial load duke parents: diff changeset	7309 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	7310 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	7311 format %{ "Jn$cop skip\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7312 "MOV $dst,$src\t# pointer\n"
a61af66fc99e Initial load duke parents: diff changeset	7313 "skip:" %}
a61af66fc99e Initial load duke parents: diff changeset	7314 opcode(0x8b);
a61af66fc99e Initial load duke parents: diff changeset	7315 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
a61af66fc99e Initial load duke parents: diff changeset	7316 ins_pipe( pipe_cmov_reg );
a61af66fc99e Initial load duke parents: diff changeset	7317 %}
a61af66fc99e Initial load duke parents: diff changeset	7318
a61af66fc99e Initial load duke parents: diff changeset	7319 // Conditional move
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7320 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7321 predicate(VM_Version::supports_cmov() );
a61af66fc99e Initial load duke parents: diff changeset	7322 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	7323 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	7324 format %{ "CMOV$cop $dst,$src\t# ptr" %}
a61af66fc99e Initial load duke parents: diff changeset	7325 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	7326 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	7327 ins_pipe( pipe_cmov_reg );
a61af66fc99e Initial load duke parents: diff changeset	7328 %}
a61af66fc99e Initial load duke parents: diff changeset	7329
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7330 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7331 predicate(VM_Version::supports_cmov() );
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7332 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7333 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7334 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7335 cmovP_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7336 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7337 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7338
0 a61af66fc99e Initial load duke parents: diff changeset	7339 // DISABLED: Requires the ADLC to emit a bottom_type call that
a61af66fc99e Initial load duke parents: diff changeset	7340 // correctly meets the two pointer arguments; one is an incoming
a61af66fc99e Initial load duke parents: diff changeset	7341 // register but the other is a memory operand. ALSO appears to
a61af66fc99e Initial load duke parents: diff changeset	7342 // be buggy with implicit null checks.
a61af66fc99e Initial load duke parents: diff changeset	7343 //
a61af66fc99e Initial load duke parents: diff changeset	7344 //// Conditional move
a61af66fc99e Initial load duke parents: diff changeset	7345 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
a61af66fc99e Initial load duke parents: diff changeset	7346 // predicate(VM_Version::supports_cmov() );
a61af66fc99e Initial load duke parents: diff changeset	7347 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
a61af66fc99e Initial load duke parents: diff changeset	7348 // ins_cost(250);
a61af66fc99e Initial load duke parents: diff changeset	7349 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
a61af66fc99e Initial load duke parents: diff changeset	7350 // opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	7351 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	7352 // ins_pipe( pipe_cmov_mem );
a61af66fc99e Initial load duke parents: diff changeset	7353 //%}
a61af66fc99e Initial load duke parents: diff changeset	7354 //
a61af66fc99e Initial load duke parents: diff changeset	7355 //// Conditional move
a61af66fc99e Initial load duke parents: diff changeset	7356 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
a61af66fc99e Initial load duke parents: diff changeset	7357 // predicate(VM_Version::supports_cmov() );
a61af66fc99e Initial load duke parents: diff changeset	7358 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
a61af66fc99e Initial load duke parents: diff changeset	7359 // ins_cost(250);
a61af66fc99e Initial load duke parents: diff changeset	7360 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
a61af66fc99e Initial load duke parents: diff changeset	7361 // opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	7362 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	7363 // ins_pipe( pipe_cmov_mem );
a61af66fc99e Initial load duke parents: diff changeset	7364 //%}
a61af66fc99e Initial load duke parents: diff changeset	7365
a61af66fc99e Initial load duke parents: diff changeset	7366 // Conditional move
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7367 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7368 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	7369 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	7370 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	7371 format %{ "FCMOV$cop $dst,$src\t# double" %}
a61af66fc99e Initial load duke parents: diff changeset	7372 opcode(0xDA);
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7373 ins_encode( enc_cmov_dpr(cop,src) );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7374 ins_pipe( pipe_cmovDPR_reg );
0 a61af66fc99e Initial load duke parents: diff changeset	7375 %}
a61af66fc99e Initial load duke parents: diff changeset	7376
a61af66fc99e Initial load duke parents: diff changeset	7377 // Conditional move
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7378 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7379 predicate(UseSSE==0);
a61af66fc99e Initial load duke parents: diff changeset	7380 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	7381 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	7382 format %{ "FCMOV$cop $dst,$src\t# float" %}
a61af66fc99e Initial load duke parents: diff changeset	7383 opcode(0xDA);
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7384 ins_encode( enc_cmov_dpr(cop,src) );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7385 ins_pipe( pipe_cmovDPR_reg );
0 a61af66fc99e Initial load duke parents: diff changeset	7386 %}
a61af66fc99e Initial load duke parents: diff changeset	7387
a61af66fc99e Initial load duke parents: diff changeset	7388 // Float CMOV on Intel doesn't handle signed compares, only unsigned.
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7389 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7390 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	7391 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	7392 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	7393 format %{ "Jn$cop skip\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7394 "MOV $dst,$src\t# double\n"
a61af66fc99e Initial load duke parents: diff changeset	7395 "skip:" %}
a61af66fc99e Initial load duke parents: diff changeset	7396 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7397 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7398 ins_pipe( pipe_cmovDPR_reg );
0 a61af66fc99e Initial load duke parents: diff changeset	7399 %}
a61af66fc99e Initial load duke parents: diff changeset	7400
a61af66fc99e Initial load duke parents: diff changeset	7401 // Float CMOV on Intel doesn't handle signed compares, only unsigned.
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7402 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7403 predicate(UseSSE==0);
a61af66fc99e Initial load duke parents: diff changeset	7404 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	7405 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	7406 format %{ "Jn$cop skip\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7407 "MOV $dst,$src\t# float\n"
a61af66fc99e Initial load duke parents: diff changeset	7408 "skip:" %}
a61af66fc99e Initial load duke parents: diff changeset	7409 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7410 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7411 ins_pipe( pipe_cmovDPR_reg );
0 a61af66fc99e Initial load duke parents: diff changeset	7412 %}
a61af66fc99e Initial load duke parents: diff changeset	7413
a61af66fc99e Initial load duke parents: diff changeset	7414 // No CMOVE with SSE/SSE2
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7415 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7416 predicate (UseSSE>=1);
a61af66fc99e Initial load duke parents: diff changeset	7417 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	7418 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	7419 format %{ "Jn$cop skip\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7420 "MOVSS $dst,$src\t# float\n"
a61af66fc99e Initial load duke parents: diff changeset	7421 "skip:" %}
a61af66fc99e Initial load duke parents: diff changeset	7422 ins_encode %{
a61af66fc99e Initial load duke parents: diff changeset	7423 Label skip;
a61af66fc99e Initial load duke parents: diff changeset	7424 // Invert sense of branch from sense of CMOV
a61af66fc99e Initial load duke parents: diff changeset	7425 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
a61af66fc99e Initial load duke parents: diff changeset	7426 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
a61af66fc99e Initial load duke parents: diff changeset	7427 __ bind(skip);
a61af66fc99e Initial load duke parents: diff changeset	7428 %}
a61af66fc99e Initial load duke parents: diff changeset	7429 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	7430 %}
a61af66fc99e Initial load duke parents: diff changeset	7431
a61af66fc99e Initial load duke parents: diff changeset	7432 // No CMOVE with SSE/SSE2
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7433 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7434 predicate (UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	7435 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	7436 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	7437 format %{ "Jn$cop skip\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7438 "MOVSD $dst,$src\t# float\n"
a61af66fc99e Initial load duke parents: diff changeset	7439 "skip:" %}
a61af66fc99e Initial load duke parents: diff changeset	7440 ins_encode %{
a61af66fc99e Initial load duke parents: diff changeset	7441 Label skip;
a61af66fc99e Initial load duke parents: diff changeset	7442 // Invert sense of branch from sense of CMOV
a61af66fc99e Initial load duke parents: diff changeset	7443 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
a61af66fc99e Initial load duke parents: diff changeset	7444 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
a61af66fc99e Initial load duke parents: diff changeset	7445 __ bind(skip);
a61af66fc99e Initial load duke parents: diff changeset	7446 %}
a61af66fc99e Initial load duke parents: diff changeset	7447 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	7448 %}
a61af66fc99e Initial load duke parents: diff changeset	7449
a61af66fc99e Initial load duke parents: diff changeset	7450 // unsigned version
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7451 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7452 predicate (UseSSE>=1);
a61af66fc99e Initial load duke parents: diff changeset	7453 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	7454 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	7455 format %{ "Jn$cop skip\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7456 "MOVSS $dst,$src\t# float\n"
a61af66fc99e Initial load duke parents: diff changeset	7457 "skip:" %}
a61af66fc99e Initial load duke parents: diff changeset	7458 ins_encode %{
a61af66fc99e Initial load duke parents: diff changeset	7459 Label skip;
a61af66fc99e Initial load duke parents: diff changeset	7460 // Invert sense of branch from sense of CMOV
a61af66fc99e Initial load duke parents: diff changeset	7461 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
a61af66fc99e Initial load duke parents: diff changeset	7462 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
a61af66fc99e Initial load duke parents: diff changeset	7463 __ bind(skip);
a61af66fc99e Initial load duke parents: diff changeset	7464 %}
a61af66fc99e Initial load duke parents: diff changeset	7465 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	7466 %}
a61af66fc99e Initial load duke parents: diff changeset	7467
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7468 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7469 predicate (UseSSE>=1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7470 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7471 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7472 expand %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7473 fcmovF_regU(cop, cr, dst, src);
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7474 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7475 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7476
0 a61af66fc99e Initial load duke parents: diff changeset	7477 // unsigned version
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7478 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7479 predicate (UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	7480 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	7481 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	7482 format %{ "Jn$cop skip\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7483 "MOVSD $dst,$src\t# float\n"
a61af66fc99e Initial load duke parents: diff changeset	7484 "skip:" %}
a61af66fc99e Initial load duke parents: diff changeset	7485 ins_encode %{
a61af66fc99e Initial load duke parents: diff changeset	7486 Label skip;
a61af66fc99e Initial load duke parents: diff changeset	7487 // Invert sense of branch from sense of CMOV
a61af66fc99e Initial load duke parents: diff changeset	7488 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
a61af66fc99e Initial load duke parents: diff changeset	7489 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
a61af66fc99e Initial load duke parents: diff changeset	7490 __ bind(skip);
a61af66fc99e Initial load duke parents: diff changeset	7491 %}
a61af66fc99e Initial load duke parents: diff changeset	7492 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	7493 %}
a61af66fc99e Initial load duke parents: diff changeset	7494
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7495 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7496 predicate (UseSSE>=2);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7497 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7498 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7499 expand %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	7500 fcmovD_regU(cop, cr, dst, src);
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7501 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7502 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7503
0 a61af66fc99e Initial load duke parents: diff changeset	7504 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
a61af66fc99e Initial load duke parents: diff changeset	7505 predicate(VM_Version::supports_cmov() );
a61af66fc99e Initial load duke parents: diff changeset	7506 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	7507 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	7508 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7509 "CMOV$cop $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	7510 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	7511 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	7512 ins_pipe( pipe_cmov_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	7513 %}
a61af66fc99e Initial load duke parents: diff changeset	7514
a61af66fc99e Initial load duke parents: diff changeset	7515 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
a61af66fc99e Initial load duke parents: diff changeset	7516 predicate(VM_Version::supports_cmov() );
a61af66fc99e Initial load duke parents: diff changeset	7517 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	7518 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	7519 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7520 "CMOV$cop $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	7521 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	7522 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	7523 ins_pipe( pipe_cmov_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	7524 %}
a61af66fc99e Initial load duke parents: diff changeset	7525
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7526 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7527 predicate(VM_Version::supports_cmov() );
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7528 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7529 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7530 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7531 cmovL_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7532 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7533 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	7534
0 a61af66fc99e Initial load duke parents: diff changeset	7535 //----------Arithmetic Instructions--------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	7536 //----------Addition Instructions----------------------------------------------
12323 c9ccd7b85f20 8024924: Intrinsify java.lang.Math.addExact rbackman parents: 10169 diff changeset	7537
14909 4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7538 instruct addExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7539 %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7540 match(AddExactI dst src);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7541 effect(DEF cr);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7542
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7543 format %{ "ADD $dst, $src\t# addExact int" %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7544 ins_encode %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7545 __ addl($dst$$Register, $src$$Register);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7546 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7547 ins_pipe(ialu_reg_reg);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7548 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7549
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7550 instruct addExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7551 %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7552 match(AddExactI dst src);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7553 effect(DEF cr);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7554
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7555 format %{ "ADD $dst, $src\t# addExact int" %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7556 ins_encode %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7557 __ addl($dst$$Register, $src$$constant);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7558 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7559 ins_pipe(ialu_reg_reg);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7560 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7561
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7562 instruct addExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7563 %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7564 match(AddExactI dst (LoadI src));
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7565 effect(DEF cr);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7566
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7567 ins_cost(125);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7568 format %{ "ADD $dst,$src\t# addExact int" %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7569 ins_encode %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7570 __ addl($dst$$Register, $src$$Address);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7571 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7572 ins_pipe( ialu_reg_mem );
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7573 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7574
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7575
0 a61af66fc99e Initial load duke parents: diff changeset	7576 // Integer Addition Instructions
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7577 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7578 match(Set dst (AddI dst src));
a61af66fc99e Initial load duke parents: diff changeset	7579 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	7580
a61af66fc99e Initial load duke parents: diff changeset	7581 size(2);
a61af66fc99e Initial load duke parents: diff changeset	7582 format %{ "ADD $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7583 opcode(0x03);
a61af66fc99e Initial load duke parents: diff changeset	7584 ins_encode( OpcP, RegReg( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	7585 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	7586 %}
a61af66fc99e Initial load duke parents: diff changeset	7587
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7588 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7589 match(Set dst (AddI dst src));
a61af66fc99e Initial load duke parents: diff changeset	7590 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	7591
a61af66fc99e Initial load duke parents: diff changeset	7592 format %{ "ADD $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7593 opcode(0x81, 0x00); /* /0 id */
a61af66fc99e Initial load duke parents: diff changeset	7594 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
a61af66fc99e Initial load duke parents: diff changeset	7595 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	7596 %}
a61af66fc99e Initial load duke parents: diff changeset	7597
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7598 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7599 predicate(UseIncDec);
a61af66fc99e Initial load duke parents: diff changeset	7600 match(Set dst (AddI dst src));
a61af66fc99e Initial load duke parents: diff changeset	7601 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	7602
a61af66fc99e Initial load duke parents: diff changeset	7603 size(1);
a61af66fc99e Initial load duke parents: diff changeset	7604 format %{ "INC $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	7605 opcode(0x40); /* */
a61af66fc99e Initial load duke parents: diff changeset	7606 ins_encode( Opc_plus( primary, dst ) );
a61af66fc99e Initial load duke parents: diff changeset	7607 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	7608 %}
a61af66fc99e Initial load duke parents: diff changeset	7609
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7610 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7611 match(Set dst (AddI src0 src1));
a61af66fc99e Initial load duke parents: diff changeset	7612 ins_cost(110);
a61af66fc99e Initial load duke parents: diff changeset	7613
a61af66fc99e Initial load duke parents: diff changeset	7614 format %{ "LEA $dst,[$src0 + $src1]" %}
a61af66fc99e Initial load duke parents: diff changeset	7615 opcode(0x8D); /* 0x8D /r */
a61af66fc99e Initial load duke parents: diff changeset	7616 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
a61af66fc99e Initial load duke parents: diff changeset	7617 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	7618 %}
a61af66fc99e Initial load duke parents: diff changeset	7619
a61af66fc99e Initial load duke parents: diff changeset	7620 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
a61af66fc99e Initial load duke parents: diff changeset	7621 match(Set dst (AddP src0 src1));
a61af66fc99e Initial load duke parents: diff changeset	7622 ins_cost(110);
a61af66fc99e Initial load duke parents: diff changeset	7623
a61af66fc99e Initial load duke parents: diff changeset	7624 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
a61af66fc99e Initial load duke parents: diff changeset	7625 opcode(0x8D); /* 0x8D /r */
a61af66fc99e Initial load duke parents: diff changeset	7626 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
a61af66fc99e Initial load duke parents: diff changeset	7627 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	7628 %}
a61af66fc99e Initial load duke parents: diff changeset	7629
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7630 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7631 predicate(UseIncDec);
a61af66fc99e Initial load duke parents: diff changeset	7632 match(Set dst (AddI dst src));
a61af66fc99e Initial load duke parents: diff changeset	7633 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	7634
a61af66fc99e Initial load duke parents: diff changeset	7635 size(1);
a61af66fc99e Initial load duke parents: diff changeset	7636 format %{ "DEC $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	7637 opcode(0x48); /* */
a61af66fc99e Initial load duke parents: diff changeset	7638 ins_encode( Opc_plus( primary, dst ) );
a61af66fc99e Initial load duke parents: diff changeset	7639 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	7640 %}
a61af66fc99e Initial load duke parents: diff changeset	7641
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7642 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7643 match(Set dst (AddP dst src));
a61af66fc99e Initial load duke parents: diff changeset	7644 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	7645
a61af66fc99e Initial load duke parents: diff changeset	7646 size(2);
a61af66fc99e Initial load duke parents: diff changeset	7647 format %{ "ADD $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7648 opcode(0x03);
a61af66fc99e Initial load duke parents: diff changeset	7649 ins_encode( OpcP, RegReg( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	7650 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	7651 %}
a61af66fc99e Initial load duke parents: diff changeset	7652
a61af66fc99e Initial load duke parents: diff changeset	7653 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	7654 match(Set dst (AddP dst src));
a61af66fc99e Initial load duke parents: diff changeset	7655 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	7656
a61af66fc99e Initial load duke parents: diff changeset	7657 format %{ "ADD $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7658 opcode(0x81,0x00); /* Opcode 81 /0 id */
a61af66fc99e Initial load duke parents: diff changeset	7659 // ins_encode( RegImm( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	7660 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
a61af66fc99e Initial load duke parents: diff changeset	7661 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	7662 %}
a61af66fc99e Initial load duke parents: diff changeset	7663
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7664 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7665 match(Set dst (AddI dst (LoadI src)));
a61af66fc99e Initial load duke parents: diff changeset	7666 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	7667
a61af66fc99e Initial load duke parents: diff changeset	7668 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	7669 format %{ "ADD $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7670 opcode(0x03);
a61af66fc99e Initial load duke parents: diff changeset	7671 ins_encode( OpcP, RegMem( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	7672 ins_pipe( ialu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	7673 %}
a61af66fc99e Initial load duke parents: diff changeset	7674
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7675 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7676 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
a61af66fc99e Initial load duke parents: diff changeset	7677 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	7678
a61af66fc99e Initial load duke parents: diff changeset	7679 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	7680 format %{ "ADD $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7681 opcode(0x01); /* Opcode 01 /r */
a61af66fc99e Initial load duke parents: diff changeset	7682 ins_encode( OpcP, RegMem( src, dst ) );
a61af66fc99e Initial load duke parents: diff changeset	7683 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	7684 %}
a61af66fc99e Initial load duke parents: diff changeset	7685
a61af66fc99e Initial load duke parents: diff changeset	7686 // Add Memory with Immediate
a61af66fc99e Initial load duke parents: diff changeset	7687 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	7688 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
a61af66fc99e Initial load duke parents: diff changeset	7689 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	7690
a61af66fc99e Initial load duke parents: diff changeset	7691 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	7692 format %{ "ADD $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7693 opcode(0x81); /* Opcode 81 /0 id */
a61af66fc99e Initial load duke parents: diff changeset	7694 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
a61af66fc99e Initial load duke parents: diff changeset	7695 ins_pipe( ialu_mem_imm );
a61af66fc99e Initial load duke parents: diff changeset	7696 %}
a61af66fc99e Initial load duke parents: diff changeset	7697
a61af66fc99e Initial load duke parents: diff changeset	7698 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	7699 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
a61af66fc99e Initial load duke parents: diff changeset	7700 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	7701
a61af66fc99e Initial load duke parents: diff changeset	7702 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	7703 format %{ "INC $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	7704 opcode(0xFF); /* Opcode FF /0 */
a61af66fc99e Initial load duke parents: diff changeset	7705 ins_encode( OpcP, RMopc_Mem(0x00,dst));
a61af66fc99e Initial load duke parents: diff changeset	7706 ins_pipe( ialu_mem_imm );
a61af66fc99e Initial load duke parents: diff changeset	7707 %}
a61af66fc99e Initial load duke parents: diff changeset	7708
a61af66fc99e Initial load duke parents: diff changeset	7709 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	7710 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
a61af66fc99e Initial load duke parents: diff changeset	7711 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	7712
a61af66fc99e Initial load duke parents: diff changeset	7713 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	7714 format %{ "DEC $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	7715 opcode(0xFF); /* Opcode FF /1 */
a61af66fc99e Initial load duke parents: diff changeset	7716 ins_encode( OpcP, RMopc_Mem(0x01,dst));
a61af66fc99e Initial load duke parents: diff changeset	7717 ins_pipe( ialu_mem_imm );
a61af66fc99e Initial load duke parents: diff changeset	7718 %}
a61af66fc99e Initial load duke parents: diff changeset	7719
a61af66fc99e Initial load duke parents: diff changeset	7720
a61af66fc99e Initial load duke parents: diff changeset	7721 instruct checkCastPP( eRegP dst ) %{
a61af66fc99e Initial load duke parents: diff changeset	7722 match(Set dst (CheckCastPP dst));
a61af66fc99e Initial load duke parents: diff changeset	7723
a61af66fc99e Initial load duke parents: diff changeset	7724 size(0);
a61af66fc99e Initial load duke parents: diff changeset	7725 format %{ "#checkcastPP of $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	7726 ins_encode( /empty encoding/ );
a61af66fc99e Initial load duke parents: diff changeset	7727 ins_pipe( empty );
a61af66fc99e Initial load duke parents: diff changeset	7728 %}
a61af66fc99e Initial load duke parents: diff changeset	7729
a61af66fc99e Initial load duke parents: diff changeset	7730 instruct castPP( eRegP dst ) %{
a61af66fc99e Initial load duke parents: diff changeset	7731 match(Set dst (CastPP dst));
a61af66fc99e Initial load duke parents: diff changeset	7732 format %{ "#castPP of $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	7733 ins_encode( /empty encoding/ );
a61af66fc99e Initial load duke parents: diff changeset	7734 ins_pipe( empty );
a61af66fc99e Initial load duke parents: diff changeset	7735 %}
a61af66fc99e Initial load duke parents: diff changeset	7736
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7737 instruct castII( rRegI dst ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7738 match(Set dst (CastII dst));
a61af66fc99e Initial load duke parents: diff changeset	7739 format %{ "#castII of $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	7740 ins_encode( /empty encoding/ );
a61af66fc99e Initial load duke parents: diff changeset	7741 ins_cost(0);
a61af66fc99e Initial load duke parents: diff changeset	7742 ins_pipe( empty );
a61af66fc99e Initial load duke parents: diff changeset	7743 %}
a61af66fc99e Initial load duke parents: diff changeset	7744
a61af66fc99e Initial load duke parents: diff changeset	7745
a61af66fc99e Initial load duke parents: diff changeset	7746 // Load-locked - same as a regular pointer load when used with compare-swap
a61af66fc99e Initial load duke parents: diff changeset	7747 instruct loadPLocked(eRegP dst, memory mem) %{
a61af66fc99e Initial load duke parents: diff changeset	7748 match(Set dst (LoadPLocked mem));
a61af66fc99e Initial load duke parents: diff changeset	7749
a61af66fc99e Initial load duke parents: diff changeset	7750 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	7751 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
a61af66fc99e Initial load duke parents: diff changeset	7752 opcode(0x8B);
a61af66fc99e Initial load duke parents: diff changeset	7753 ins_encode( OpcP, RegMem(dst,mem));
a61af66fc99e Initial load duke parents: diff changeset	7754 ins_pipe( ialu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	7755 %}
a61af66fc99e Initial load duke parents: diff changeset	7756
a61af66fc99e Initial load duke parents: diff changeset	7757 // Conditional-store of the updated heap-top.
a61af66fc99e Initial load duke parents: diff changeset	7758 // Used during allocation of the shared heap.
a61af66fc99e Initial load duke parents: diff changeset	7759 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
a61af66fc99e Initial load duke parents: diff changeset	7760 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
a61af66fc99e Initial load duke parents: diff changeset	7761 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
a61af66fc99e Initial load duke parents: diff changeset	7762 // EAX is killed if there is contention, but then it's also unused.
a61af66fc99e Initial load duke parents: diff changeset	7763 // In the common case of no contention, EAX holds the new oop address.
a61af66fc99e Initial load duke parents: diff changeset	7764 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
a61af66fc99e Initial load duke parents: diff changeset	7765 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
a61af66fc99e Initial load duke parents: diff changeset	7766 ins_pipe( pipe_cmpxchg );
a61af66fc99e Initial load duke parents: diff changeset	7767 %}
a61af66fc99e Initial load duke parents: diff changeset	7768
420 a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7769 // Conditional-store of an int value.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7770 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7771 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
420 a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7772 match(Set cr (StoreIConditional mem (Binary oldval newval)));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7773 effect(KILL oldval);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7774 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7775 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
0 a61af66fc99e Initial load duke parents: diff changeset	7776 ins_pipe( pipe_cmpxchg );
a61af66fc99e Initial load duke parents: diff changeset	7777 %}
a61af66fc99e Initial load duke parents: diff changeset	7778
420 a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7779 // Conditional-store of a long value.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7780 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7781 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7782 match(Set cr (StoreLConditional mem (Binary oldval newval)));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7783 effect(KILL oldval);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7784 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7785 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7786 "XCHG EBX,ECX"
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7787 %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7788 ins_encode %{
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7789 // Note: we need to swap rbx, and rcx before and after the
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7790 // cmpxchg8 instruction because the instruction uses
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7791 // rcx as the high order word of the new value to store but
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7792 // our register encoding uses rbx.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7793 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7794 if( os::is_MP() )
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7795 __ lock();
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	7796 __ cmpxchg8($mem$$Address);
420 a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7797 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	7798 %}
0 a61af66fc99e Initial load duke parents: diff changeset	7799 ins_pipe( pipe_cmpxchg );
a61af66fc99e Initial load duke parents: diff changeset	7800 %}
a61af66fc99e Initial load duke parents: diff changeset	7801
a61af66fc99e Initial load duke parents: diff changeset	7802 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
a61af66fc99e Initial load duke parents: diff changeset	7803
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7804 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
6795 7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7805 predicate(VM_Version::supports_cx8());
0 a61af66fc99e Initial load duke parents: diff changeset	7806 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
a61af66fc99e Initial load duke parents: diff changeset	7807 effect(KILL cr, KILL oldval);
a61af66fc99e Initial load duke parents: diff changeset	7808 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7809 "MOV $res,0\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7810 "JNE,s fail\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7811 "MOV $res,1\n"
a61af66fc99e Initial load duke parents: diff changeset	7812 "fail:" %}
a61af66fc99e Initial load duke parents: diff changeset	7813 ins_encode( enc_cmpxchg8(mem_ptr),
a61af66fc99e Initial load duke parents: diff changeset	7814 enc_flags_ne_to_boolean(res) );
a61af66fc99e Initial load duke parents: diff changeset	7815 ins_pipe( pipe_cmpxchg );
a61af66fc99e Initial load duke parents: diff changeset	7816 %}
a61af66fc99e Initial load duke parents: diff changeset	7817
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7818 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7819 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
a61af66fc99e Initial load duke parents: diff changeset	7820 effect(KILL cr, KILL oldval);
a61af66fc99e Initial load duke parents: diff changeset	7821 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7822 "MOV $res,0\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7823 "JNE,s fail\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7824 "MOV $res,1\n"
a61af66fc99e Initial load duke parents: diff changeset	7825 "fail:" %}
a61af66fc99e Initial load duke parents: diff changeset	7826 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
a61af66fc99e Initial load duke parents: diff changeset	7827 ins_pipe( pipe_cmpxchg );
a61af66fc99e Initial load duke parents: diff changeset	7828 %}
a61af66fc99e Initial load duke parents: diff changeset	7829
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7830 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7831 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
a61af66fc99e Initial load duke parents: diff changeset	7832 effect(KILL cr, KILL oldval);
a61af66fc99e Initial load duke parents: diff changeset	7833 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7834 "MOV $res,0\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7835 "JNE,s fail\n\t"
a61af66fc99e Initial load duke parents: diff changeset	7836 "MOV $res,1\n"
a61af66fc99e Initial load duke parents: diff changeset	7837 "fail:" %}
a61af66fc99e Initial load duke parents: diff changeset	7838 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
a61af66fc99e Initial load duke parents: diff changeset	7839 ins_pipe( pipe_cmpxchg );
a61af66fc99e Initial load duke parents: diff changeset	7840 %}
a61af66fc99e Initial load duke parents: diff changeset	7841
6795 7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7842 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7843 predicate(n->as_LoadStore()->result_not_used());
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7844 match(Set dummy (GetAndAddI mem add));
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7845 effect(KILL cr);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7846 format %{ "ADDL [$mem],$add" %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7847 ins_encode %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7848 if (os::is_MP()) { __ lock(); }
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7849 __ addl($mem$$Address, $add$$constant);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7850 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7851 ins_pipe( pipe_cmpxchg );
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7852 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7853
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7854 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7855 match(Set newval (GetAndAddI mem newval));
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7856 effect(KILL cr);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7857 format %{ "XADDL [$mem],$newval" %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7858 ins_encode %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7859 if (os::is_MP()) { __ lock(); }
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7860 __ xaddl($mem$$Address, $newval$$Register);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7861 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7862 ins_pipe( pipe_cmpxchg );
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7863 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7864
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7865 instruct xchgI( memory mem, rRegI newval) %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7866 match(Set newval (GetAndSetI mem newval));
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7867 format %{ "XCHGL $newval,[$mem]" %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7868 ins_encode %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7869 __ xchgl($newval$$Register, $mem$$Address);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7870 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7871 ins_pipe( pipe_cmpxchg );
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7872 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7873
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7874 instruct xchgP( memory mem, pRegP newval) %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7875 match(Set newval (GetAndSetP mem newval));
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7876 format %{ "XCHGL $newval,[$mem]" %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7877 ins_encode %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7878 __ xchgl($newval$$Register, $mem$$Address);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7879 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7880 ins_pipe( pipe_cmpxchg );
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7881 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() roland parents: 6725 diff changeset	7882
0 a61af66fc99e Initial load duke parents: diff changeset	7883 //----------Subtraction Instructions-------------------------------------------
12972 59e8ad757e19 8026844: Various Math functions needs intrinsification rbackman parents: 12334 diff changeset	7884
14909 4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7885 instruct subExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7886 %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7887 match(SubExactI dst src);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7888 effect(DEF cr);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7889
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7890 format %{ "SUB $dst, $src\t# subExact int" %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7891 ins_encode %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7892 __ subl($dst$$Register, $src$$Register);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7893 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7894 ins_pipe(ialu_reg_reg);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7895 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7896
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7897 instruct subExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7898 %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7899 match(SubExactI dst src);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7900 effect(DEF cr);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7901
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7902 format %{ "SUB $dst, $src\t# subExact int" %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7903 ins_encode %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7904 __ subl($dst$$Register, $src$$constant);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7905 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7906 ins_pipe(ialu_reg_reg);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7907 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7908
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7909 instruct subExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7910 %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7911 match(SubExactI dst (LoadI src));
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7912 effect(DEF cr);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7913
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7914 ins_cost(125);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7915 format %{ "SUB $dst,$src\t# subExact int" %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7916 ins_encode %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7917 __ subl($dst$$Register, $src$$Address);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7918 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7919 ins_pipe( ialu_reg_mem );
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7920 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7921
0 a61af66fc99e Initial load duke parents: diff changeset	7922 // Integer Subtraction Instructions
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7923 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7924 match(Set dst (SubI dst src));
a61af66fc99e Initial load duke parents: diff changeset	7925 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	7926
a61af66fc99e Initial load duke parents: diff changeset	7927 size(2);
a61af66fc99e Initial load duke parents: diff changeset	7928 format %{ "SUB $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7929 opcode(0x2B);
a61af66fc99e Initial load duke parents: diff changeset	7930 ins_encode( OpcP, RegReg( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	7931 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	7932 %}
a61af66fc99e Initial load duke parents: diff changeset	7933
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7934 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7935 match(Set dst (SubI dst src));
a61af66fc99e Initial load duke parents: diff changeset	7936 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	7937
a61af66fc99e Initial load duke parents: diff changeset	7938 format %{ "SUB $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7939 opcode(0x81,0x05); /* Opcode 81 /5 */
a61af66fc99e Initial load duke parents: diff changeset	7940 // ins_encode( RegImm( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	7941 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
a61af66fc99e Initial load duke parents: diff changeset	7942 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	7943 %}
a61af66fc99e Initial load duke parents: diff changeset	7944
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7945 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7946 match(Set dst (SubI dst (LoadI src)));
a61af66fc99e Initial load duke parents: diff changeset	7947 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	7948
a61af66fc99e Initial load duke parents: diff changeset	7949 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	7950 format %{ "SUB $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7951 opcode(0x2B);
a61af66fc99e Initial load duke parents: diff changeset	7952 ins_encode( OpcP, RegMem( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	7953 ins_pipe( ialu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	7954 %}
a61af66fc99e Initial load duke parents: diff changeset	7955
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7956 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7957 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
a61af66fc99e Initial load duke parents: diff changeset	7958 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	7959
a61af66fc99e Initial load duke parents: diff changeset	7960 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	7961 format %{ "SUB $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7962 opcode(0x29); /* Opcode 29 /r */
a61af66fc99e Initial load duke parents: diff changeset	7963 ins_encode( OpcP, RegMem( src, dst ) );
a61af66fc99e Initial load duke parents: diff changeset	7964 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	7965 %}
a61af66fc99e Initial load duke parents: diff changeset	7966
a61af66fc99e Initial load duke parents: diff changeset	7967 // Subtract from a pointer
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7968 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7969 match(Set dst (AddP dst (SubI zero src)));
a61af66fc99e Initial load duke parents: diff changeset	7970 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	7971
a61af66fc99e Initial load duke parents: diff changeset	7972 size(2);
a61af66fc99e Initial load duke parents: diff changeset	7973 format %{ "SUB $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	7974 opcode(0x2B);
a61af66fc99e Initial load duke parents: diff changeset	7975 ins_encode( OpcP, RegReg( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	7976 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	7977 %}
a61af66fc99e Initial load duke parents: diff changeset	7978
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	7979 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	7980 match(Set dst (SubI zero dst));
a61af66fc99e Initial load duke parents: diff changeset	7981 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	7982
a61af66fc99e Initial load duke parents: diff changeset	7983 size(2);
a61af66fc99e Initial load duke parents: diff changeset	7984 format %{ "NEG $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	7985 opcode(0xF7,0x03); // Opcode F7 /3
a61af66fc99e Initial load duke parents: diff changeset	7986 ins_encode( OpcP, RegOpc( dst ) );
a61af66fc99e Initial load duke parents: diff changeset	7987 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	7988 %}
a61af66fc99e Initial load duke parents: diff changeset	7989
14909 4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7990 instruct negExactI_eReg(eAXRegI dst, eFlagsReg cr) %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7991 match(NegExactI dst);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7992 effect(DEF cr);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7993
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7994 format %{ "NEG $dst\t# negExact int"%}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7995 ins_encode %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7996 __ negl($dst$$Register);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7997 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7998 ins_pipe(ialu_reg);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	7999 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8000
0 a61af66fc99e Initial load duke parents: diff changeset	8001 //----------Multiplication/Division Instructions-------------------------------
a61af66fc99e Initial load duke parents: diff changeset	8002 // Integer Multiplication Instructions
a61af66fc99e Initial load duke parents: diff changeset	8003 // Multiply Register
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8004 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8005 match(Set dst (MulI dst src));
a61af66fc99e Initial load duke parents: diff changeset	8006 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8007
a61af66fc99e Initial load duke parents: diff changeset	8008 size(3);
a61af66fc99e Initial load duke parents: diff changeset	8009 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	8010 format %{ "IMUL $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8011 opcode(0xAF, 0x0F);
a61af66fc99e Initial load duke parents: diff changeset	8012 ins_encode( OpcS, OpcP, RegReg( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	8013 ins_pipe( ialu_reg_reg_alu0 );
a61af66fc99e Initial load duke parents: diff changeset	8014 %}
a61af66fc99e Initial load duke parents: diff changeset	8015
a61af66fc99e Initial load duke parents: diff changeset	8016 // Multiply 32-bit Immediate
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8017 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8018 match(Set dst (MulI src imm));
a61af66fc99e Initial load duke parents: diff changeset	8019 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8020
a61af66fc99e Initial load duke parents: diff changeset	8021 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	8022 format %{ "IMUL $dst,$src,$imm" %}
a61af66fc99e Initial load duke parents: diff changeset	8023 opcode(0x69); /* 69 /r id */
a61af66fc99e Initial load duke parents: diff changeset	8024 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
a61af66fc99e Initial load duke parents: diff changeset	8025 ins_pipe( ialu_reg_reg_alu0 );
a61af66fc99e Initial load duke parents: diff changeset	8026 %}
a61af66fc99e Initial load duke parents: diff changeset	8027
a61af66fc99e Initial load duke parents: diff changeset	8028 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	8029 match(Set dst src);
a61af66fc99e Initial load duke parents: diff changeset	8030 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8031
a61af66fc99e Initial load duke parents: diff changeset	8032 // Note that this is artificially increased to make it more expensive than loadConL
a61af66fc99e Initial load duke parents: diff changeset	8033 ins_cost(250);
a61af66fc99e Initial load duke parents: diff changeset	8034 format %{ "MOV EAX,$src\t// low word only" %}
a61af66fc99e Initial load duke parents: diff changeset	8035 opcode(0xB8);
a61af66fc99e Initial load duke parents: diff changeset	8036 ins_encode( LdImmL_Lo(dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	8037 ins_pipe( ialu_reg_fat );
a61af66fc99e Initial load duke parents: diff changeset	8038 %}
a61af66fc99e Initial load duke parents: diff changeset	8039
a61af66fc99e Initial load duke parents: diff changeset	8040 // Multiply by 32-bit Immediate, taking the shifted high order results
a61af66fc99e Initial load duke parents: diff changeset	8041 // (special case for shift by 32)
a61af66fc99e Initial load duke parents: diff changeset	8042 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	8043 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
a61af66fc99e Initial load duke parents: diff changeset	8044 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
a61af66fc99e Initial load duke parents: diff changeset	8045 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
a61af66fc99e Initial load duke parents: diff changeset	8046 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
a61af66fc99e Initial load duke parents: diff changeset	8047 effect(USE src1, KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8048
a61af66fc99e Initial load duke parents: diff changeset	8049 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
a61af66fc99e Initial load duke parents: diff changeset	8050 ins_cost(0100 + 1400 - 150);
a61af66fc99e Initial load duke parents: diff changeset	8051 format %{ "IMUL EDX:EAX,$src1" %}
a61af66fc99e Initial load duke parents: diff changeset	8052 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
a61af66fc99e Initial load duke parents: diff changeset	8053 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	8054 %}
a61af66fc99e Initial load duke parents: diff changeset	8055
a61af66fc99e Initial load duke parents: diff changeset	8056 // Multiply by 32-bit Immediate, taking the shifted high order results
a61af66fc99e Initial load duke parents: diff changeset	8057 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	8058 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
a61af66fc99e Initial load duke parents: diff changeset	8059 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
a61af66fc99e Initial load duke parents: diff changeset	8060 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
a61af66fc99e Initial load duke parents: diff changeset	8061 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
a61af66fc99e Initial load duke parents: diff changeset	8062 effect(USE src1, KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8063
a61af66fc99e Initial load duke parents: diff changeset	8064 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
a61af66fc99e Initial load duke parents: diff changeset	8065 ins_cost(1100 + 1400 - 150);
a61af66fc99e Initial load duke parents: diff changeset	8066 format %{ "IMUL EDX:EAX,$src1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8067 "SAR EDX,$cnt-32" %}
a61af66fc99e Initial load duke parents: diff changeset	8068 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
a61af66fc99e Initial load duke parents: diff changeset	8069 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	8070 %}
a61af66fc99e Initial load duke parents: diff changeset	8071
a61af66fc99e Initial load duke parents: diff changeset	8072 // Multiply Memory 32-bit Immediate
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8073 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8074 match(Set dst (MulI (LoadI src) imm));
a61af66fc99e Initial load duke parents: diff changeset	8075 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8076
a61af66fc99e Initial load duke parents: diff changeset	8077 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	8078 format %{ "IMUL $dst,$src,$imm" %}
a61af66fc99e Initial load duke parents: diff changeset	8079 opcode(0x69); /* 69 /r id */
a61af66fc99e Initial load duke parents: diff changeset	8080 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
a61af66fc99e Initial load duke parents: diff changeset	8081 ins_pipe( ialu_reg_mem_alu0 );
a61af66fc99e Initial load duke parents: diff changeset	8082 %}
a61af66fc99e Initial load duke parents: diff changeset	8083
a61af66fc99e Initial load duke parents: diff changeset	8084 // Multiply Memory
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8085 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8086 match(Set dst (MulI dst (LoadI src)));
a61af66fc99e Initial load duke parents: diff changeset	8087 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8088
a61af66fc99e Initial load duke parents: diff changeset	8089 ins_cost(350);
a61af66fc99e Initial load duke parents: diff changeset	8090 format %{ "IMUL $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8091 opcode(0xAF, 0x0F);
a61af66fc99e Initial load duke parents: diff changeset	8092 ins_encode( OpcS, OpcP, RegMem( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	8093 ins_pipe( ialu_reg_mem_alu0 );
a61af66fc99e Initial load duke parents: diff changeset	8094 %}
a61af66fc99e Initial load duke parents: diff changeset	8095
a61af66fc99e Initial load duke parents: diff changeset	8096 // Multiply Register Int to Long
a61af66fc99e Initial load duke parents: diff changeset	8097 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
a61af66fc99e Initial load duke parents: diff changeset	8098 // Basic Idea: long = (long)int * (long)int
a61af66fc99e Initial load duke parents: diff changeset	8099 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
a61af66fc99e Initial load duke parents: diff changeset	8100 effect(DEF dst, USE src, USE src1, KILL flags);
a61af66fc99e Initial load duke parents: diff changeset	8101
a61af66fc99e Initial load duke parents: diff changeset	8102 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	8103 format %{ "IMUL $dst,$src1" %}
a61af66fc99e Initial load duke parents: diff changeset	8104
a61af66fc99e Initial load duke parents: diff changeset	8105 ins_encode( long_int_multiply( dst, src1 ) );
a61af66fc99e Initial load duke parents: diff changeset	8106 ins_pipe( ialu_reg_reg_alu0 );
a61af66fc99e Initial load duke parents: diff changeset	8107 %}
a61af66fc99e Initial load duke parents: diff changeset	8108
a61af66fc99e Initial load duke parents: diff changeset	8109 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
a61af66fc99e Initial load duke parents: diff changeset	8110 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
a61af66fc99e Initial load duke parents: diff changeset	8111 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
a61af66fc99e Initial load duke parents: diff changeset	8112 effect(KILL flags);
a61af66fc99e Initial load duke parents: diff changeset	8113
a61af66fc99e Initial load duke parents: diff changeset	8114 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	8115 format %{ "MUL $dst,$src1" %}
a61af66fc99e Initial load duke parents: diff changeset	8116
a61af66fc99e Initial load duke parents: diff changeset	8117 ins_encode( long_uint_multiply(dst, src1) );
a61af66fc99e Initial load duke parents: diff changeset	8118 ins_pipe( ialu_reg_reg_alu0 );
a61af66fc99e Initial load duke parents: diff changeset	8119 %}
a61af66fc99e Initial load duke parents: diff changeset	8120
a61af66fc99e Initial load duke parents: diff changeset	8121 // Multiply Register Long
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8122 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8123 match(Set dst (MulL dst src));
a61af66fc99e Initial load duke parents: diff changeset	8124 effect(KILL cr, TEMP tmp);
a61af66fc99e Initial load duke parents: diff changeset	8125 ins_cost(4100+3400);
a61af66fc99e Initial load duke parents: diff changeset	8126 // Basic idea: lo(result) = lo(x_lo * y_lo)
a61af66fc99e Initial load duke parents: diff changeset	8127 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
a61af66fc99e Initial load duke parents: diff changeset	8128 format %{ "MOV $tmp,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8129 "IMUL $tmp,EDX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8130 "MOV EDX,$src.hi\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8131 "IMUL EDX,EAX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8132 "ADD $tmp,EDX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8133 "MUL EDX:EAX,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8134 "ADD EDX,$tmp" %}
a61af66fc99e Initial load duke parents: diff changeset	8135 ins_encode( long_multiply( dst, src, tmp ) );
a61af66fc99e Initial load duke parents: diff changeset	8136 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	8137 %}
a61af66fc99e Initial load duke parents: diff changeset	8138
1209 e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8139 // Multiply Register Long where the left operand's high 32 bits are zero
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8140 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
1209 e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8141 predicate(is_operand_hi32_zero(n->in(1)));
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8142 match(Set dst (MulL dst src));
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8143 effect(KILL cr, TEMP tmp);
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8144 ins_cost(2100+2400);
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8145 // Basic idea: lo(result) = lo(x_lo * y_lo)
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8146 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8147 format %{ "MOV $tmp,$src.hi\n\t"
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8148 "IMUL $tmp,EAX\n\t"
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8149 "MUL EDX:EAX,$src.lo\n\t"
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8150 "ADD EDX,$tmp" %}
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8151 ins_encode %{
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8152 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8153 __ imull($tmp$$Register, rax);
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8154 __ mull($src$$Register);
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8155 __ addl(rdx, $tmp$$Register);
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8156 %}
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8157 ins_pipe( pipe_slow );
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8158 %}
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8159
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8160 // Multiply Register Long where the right operand's high 32 bits are zero
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8161 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
1209 e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8162 predicate(is_operand_hi32_zero(n->in(2)));
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8163 match(Set dst (MulL dst src));
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8164 effect(KILL cr, TEMP tmp);
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8165 ins_cost(2100+2400);
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8166 // Basic idea: lo(result) = lo(x_lo * y_lo)
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8167 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8168 format %{ "MOV $tmp,$src.lo\n\t"
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8169 "IMUL $tmp,EDX\n\t"
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8170 "MUL EDX:EAX,$src.lo\n\t"
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8171 "ADD EDX,$tmp" %}
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8172 ins_encode %{
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8173 __ movl($tmp$$Register, $src$$Register);
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8174 __ imull($tmp$$Register, rdx);
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8175 __ mull($src$$Register);
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8176 __ addl(rdx, $tmp$$Register);
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8177 %}
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8178 ins_pipe( pipe_slow );
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8179 %}
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8180
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8181 // Multiply Register Long where the left and the right operands' high 32 bits are zero
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8182 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8183 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8184 match(Set dst (MulL dst src));
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8185 effect(KILL cr);
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8186 ins_cost(1*400);
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8187 // Basic idea: lo(result) = lo(x_lo * y_lo)
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8188 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8189 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8190 ins_encode %{
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8191 __ mull($src$$Register);
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8192 %}
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8193 ins_pipe( pipe_slow );
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8194 %}
e8443c7be117 6921969: optimize 64 long multiply for case with high bits zero never parents: 1137 diff changeset	8195
0 a61af66fc99e Initial load duke parents: diff changeset	8196 // Multiply Register Long by small constant
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8197 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8198 match(Set dst (MulL dst src));
a61af66fc99e Initial load duke parents: diff changeset	8199 effect(KILL cr, TEMP tmp);
a61af66fc99e Initial load duke parents: diff changeset	8200 ins_cost(2100+2400);
a61af66fc99e Initial load duke parents: diff changeset	8201 size(12);
a61af66fc99e Initial load duke parents: diff changeset	8202 // Basic idea: lo(result) = lo(src * EAX)
a61af66fc99e Initial load duke parents: diff changeset	8203 // hi(result) = hi(src * EAX) + lo(src * EDX)
a61af66fc99e Initial load duke parents: diff changeset	8204 format %{ "IMUL $tmp,EDX,$src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8205 "MOV EDX,$src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8206 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8207 "ADD EDX,$tmp" %}
a61af66fc99e Initial load duke parents: diff changeset	8208 ins_encode( long_multiply_con( dst, src, tmp ) );
a61af66fc99e Initial load duke parents: diff changeset	8209 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	8210 %}
a61af66fc99e Initial load duke parents: diff changeset	8211
14909 4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8212 instruct mulExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8213 %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8214 match(MulExactI dst src);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8215 effect(DEF cr);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8216
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8217 ins_cost(300);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8218 format %{ "IMUL $dst, $src\t# mulExact int" %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8219 ins_encode %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8220 __ imull($dst$$Register, $src$$Register);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8221 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8222 ins_pipe(ialu_reg_reg_alu0);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8223 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8224
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8225 instruct mulExactI_eReg_imm(eAXRegI dst, rRegI src, immI imm, eFlagsReg cr)
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8226 %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8227 match(MulExactI src imm);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8228 effect(DEF cr);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8229
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8230 ins_cost(300);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8231 format %{ "IMUL $dst, $src, $imm\t# mulExact int" %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8232 ins_encode %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8233 __ imull($dst$$Register, $src$$Register, $imm$$constant);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8234 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8235 ins_pipe(ialu_reg_reg_alu0);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8236 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8237
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8238 instruct mulExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8239 %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8240 match(MulExactI dst (LoadI src));
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8241 effect(DEF cr);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8242
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8243 ins_cost(350);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8244 format %{ "IMUL $dst, $src\t# mulExact int" %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8245 ins_encode %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8246 __ imull($dst$$Register, $src$$Address);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8247 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8248 ins_pipe(ialu_reg_mem_alu0);
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8249 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8250
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	8251
0 a61af66fc99e Initial load duke parents: diff changeset	8252 // Integer DIV with Register
a61af66fc99e Initial load duke parents: diff changeset	8253 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	8254 match(Set rax (DivI rax div));
a61af66fc99e Initial load duke parents: diff changeset	8255 effect(KILL rdx, KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8256 size(26);
a61af66fc99e Initial load duke parents: diff changeset	8257 ins_cost(30100+10100);
a61af66fc99e Initial load duke parents: diff changeset	8258 format %{ "CMP EAX,0x80000000\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8259 "JNE,s normal\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8260 "XOR EDX,EDX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8261 "CMP ECX,-1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8262 "JE,s done\n"
a61af66fc99e Initial load duke parents: diff changeset	8263 "normal: CDQ\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8264 "IDIV $div\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8265 "done:" %}
a61af66fc99e Initial load duke parents: diff changeset	8266 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load duke parents: diff changeset	8267 ins_encode( cdq_enc, OpcP, RegOpc(div) );
a61af66fc99e Initial load duke parents: diff changeset	8268 ins_pipe( ialu_reg_reg_alu0 );
a61af66fc99e Initial load duke parents: diff changeset	8269 %}
a61af66fc99e Initial load duke parents: diff changeset	8270
a61af66fc99e Initial load duke parents: diff changeset	8271 // Divide Register Long
a61af66fc99e Initial load duke parents: diff changeset	8272 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
a61af66fc99e Initial load duke parents: diff changeset	8273 match(Set dst (DivL src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	8274 effect( KILL cr, KILL cx, KILL bx );
a61af66fc99e Initial load duke parents: diff changeset	8275 ins_cost(10000);
a61af66fc99e Initial load duke parents: diff changeset	8276 format %{ "PUSH $src1.hi\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8277 "PUSH $src1.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8278 "PUSH $src2.hi\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8279 "PUSH $src2.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8280 "CALL SharedRuntime::ldiv\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8281 "ADD ESP,16" %}
a61af66fc99e Initial load duke parents: diff changeset	8282 ins_encode( long_div(src1,src2) );
a61af66fc99e Initial load duke parents: diff changeset	8283 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	8284 %}
a61af66fc99e Initial load duke parents: diff changeset	8285
a61af66fc99e Initial load duke parents: diff changeset	8286 // Integer DIVMOD with Register, both quotient and mod results
a61af66fc99e Initial load duke parents: diff changeset	8287 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	8288 match(DivModI rax div);
a61af66fc99e Initial load duke parents: diff changeset	8289 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8290 size(26);
a61af66fc99e Initial load duke parents: diff changeset	8291 ins_cost(30100+10100);
a61af66fc99e Initial load duke parents: diff changeset	8292 format %{ "CMP EAX,0x80000000\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8293 "JNE,s normal\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8294 "XOR EDX,EDX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8295 "CMP ECX,-1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8296 "JE,s done\n"
a61af66fc99e Initial load duke parents: diff changeset	8297 "normal: CDQ\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8298 "IDIV $div\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8299 "done:" %}
a61af66fc99e Initial load duke parents: diff changeset	8300 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load duke parents: diff changeset	8301 ins_encode( cdq_enc, OpcP, RegOpc(div) );
a61af66fc99e Initial load duke parents: diff changeset	8302 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	8303 %}
a61af66fc99e Initial load duke parents: diff changeset	8304
a61af66fc99e Initial load duke parents: diff changeset	8305 // Integer MOD with Register
a61af66fc99e Initial load duke parents: diff changeset	8306 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	8307 match(Set rdx (ModI rax div));
a61af66fc99e Initial load duke parents: diff changeset	8308 effect(KILL rax, KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8309
a61af66fc99e Initial load duke parents: diff changeset	8310 size(26);
a61af66fc99e Initial load duke parents: diff changeset	8311 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	8312 format %{ "CDQ\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8313 "IDIV $div" %}
a61af66fc99e Initial load duke parents: diff changeset	8314 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load duke parents: diff changeset	8315 ins_encode( cdq_enc, OpcP, RegOpc(div) );
a61af66fc99e Initial load duke parents: diff changeset	8316 ins_pipe( ialu_reg_reg_alu0 );
a61af66fc99e Initial load duke parents: diff changeset	8317 %}
a61af66fc99e Initial load duke parents: diff changeset	8318
a61af66fc99e Initial load duke parents: diff changeset	8319 // Remainder Register Long
a61af66fc99e Initial load duke parents: diff changeset	8320 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
a61af66fc99e Initial load duke parents: diff changeset	8321 match(Set dst (ModL src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	8322 effect( KILL cr, KILL cx, KILL bx );
a61af66fc99e Initial load duke parents: diff changeset	8323 ins_cost(10000);
a61af66fc99e Initial load duke parents: diff changeset	8324 format %{ "PUSH $src1.hi\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8325 "PUSH $src1.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8326 "PUSH $src2.hi\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8327 "PUSH $src2.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8328 "CALL SharedRuntime::lrem\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8329 "ADD ESP,16" %}
a61af66fc99e Initial load duke parents: diff changeset	8330 ins_encode( long_mod(src1,src2) );
a61af66fc99e Initial load duke parents: diff changeset	8331 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	8332 %}
a61af66fc99e Initial load duke parents: diff changeset	8333
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8334 // Divide Register Long (no special case since divisor != -1)
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8335 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8336 match(Set dst (DivL dst imm));
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8337 effect( TEMP tmp, TEMP tmp2, KILL cr );
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8338 ins_cost(1000);
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8339 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8340 "XOR $tmp2,$tmp2\n\t"
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8341 "CMP $tmp,EDX\n\t"
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8342 "JA,s fast\n\t"
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8343 "MOV $tmp2,EAX\n\t"
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8344 "MOV EAX,EDX\n\t"
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8345 "MOV EDX,0\n\t"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8346 "JLE,s pos\n\t"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8347 "LNEG EAX : $tmp2\n\t"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8348 "DIV $tmp # unsigned division\n\t"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8349 "XCHG EAX,$tmp2\n\t"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8350 "DIV $tmp\n\t"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8351 "LNEG $tmp2 : EAX\n\t"
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8352 "JMP,s done\n"
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8353 "pos:\n\t"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8354 "DIV $tmp\n\t"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8355 "XCHG EAX,$tmp2\n"
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8356 "fast:\n\t"
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8357 "DIV $tmp\n"
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8358 "done:\n\t"
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8359 "MOV EDX,$tmp2\n\t"
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8360 "NEG EDX:EAX # if $imm < 0" %}
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8361 ins_encode %{
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8362 int con = (int)$imm$$constant;
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8363 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8364 int pcon = (con > 0) ? con : -con;
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8365 Label Lfast, Lpos, Ldone;
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8366
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8367 __ movl($tmp$$Register, pcon);
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8368 __ xorl($tmp2$$Register,$tmp2$$Register);
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8369 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8370 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8371
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8372 __ movl($tmp2$$Register, $dst$$Register); // save
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8373 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8374 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8375 __ jccb(Assembler::lessEqual, Lpos); // result is positive
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8376
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8377 // Negative dividend.
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8378 // convert value to positive to use unsigned division
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8379 __ lneg($dst$$Register, $tmp2$$Register);
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8380 __ divl($tmp$$Register);
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8381 __ xchgl($dst$$Register, $tmp2$$Register);
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8382 __ divl($tmp$$Register);
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8383 // revert result back to negative
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8384 __ lneg($tmp2$$Register, $dst$$Register);
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8385 __ jmpb(Ldone);
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8386
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8387 __ bind(Lpos);
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8388 __ divl($tmp$$Register); // Use unsigned division
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8389 __ xchgl($dst$$Register, $tmp2$$Register);
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8390 // Fallthrow for final divide, tmp2 has 32 bit hi result
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8391
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8392 __ bind(Lfast);
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8393 // fast path: src is positive
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8394 __ divl($tmp$$Register); // Use unsigned division
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8395
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8396 __ bind(Ldone);
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8397 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8398 if (con < 0) {
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8399 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8400 }
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8401 %}
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8402 ins_pipe( pipe_slow );
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8403 %}
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8404
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8405 // Remainder Register Long (remainder fit into 32 bits)
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8406 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8407 match(Set dst (ModL dst imm));
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8408 effect( TEMP tmp, TEMP tmp2, KILL cr );
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8409 ins_cost(1000);
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8410 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8411 "CMP $tmp,EDX\n\t"
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8412 "JA,s fast\n\t"
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8413 "MOV $tmp2,EAX\n\t"
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8414 "MOV EAX,EDX\n\t"
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8415 "MOV EDX,0\n\t"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8416 "JLE,s pos\n\t"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8417 "LNEG EAX : $tmp2\n\t"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8418 "DIV $tmp # unsigned division\n\t"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8419 "MOV EAX,$tmp2\n\t"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8420 "DIV $tmp\n\t"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8421 "NEG EDX\n\t"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8422 "JMP,s done\n"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8423 "pos:\n\t"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8424 "DIV $tmp\n\t"
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8425 "MOV EAX,$tmp2\n"
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8426 "fast:\n\t"
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8427 "DIV $tmp\n"
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8428 "done:\n\t"
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8429 "MOV EAX,EDX\n\t"
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8430 "SAR EDX,31\n\t" %}
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8431 ins_encode %{
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8432 int con = (int)$imm$$constant;
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8433 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8434 int pcon = (con > 0) ? con : -con;
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8435 Label Lfast, Lpos, Ldone;
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8436
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8437 __ movl($tmp$$Register, pcon);
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8438 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8439 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8440
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8441 __ movl($tmp2$$Register, $dst$$Register); // save
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8442 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8443 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8444 __ jccb(Assembler::lessEqual, Lpos); // result is positive
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8445
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8446 // Negative dividend.
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8447 // convert value to positive to use unsigned division
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8448 __ lneg($dst$$Register, $tmp2$$Register);
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8449 __ divl($tmp$$Register);
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8450 __ movl($dst$$Register, $tmp2$$Register);
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8451 __ divl($tmp$$Register);
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8452 // revert remainder back to negative
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8453 __ negl(HIGH_FROM_LOW($dst$$Register));
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8454 __ jmpb(Ldone);
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8455
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8456 __ bind(Lpos);
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8457 __ divl($tmp$$Register);
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8458 __ movl($dst$$Register, $tmp2$$Register);
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8459
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8460 __ bind(Lfast);
1920 2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8461 // fast path: src is positive
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8462 __ divl($tmp$$Register);
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8463
2fe998383789 6997311: SIGFPE in new long division asm code kvn parents: 1914 diff changeset	8464 __ bind(Ldone);
1914 ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8465 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8466 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8467
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8468 %}
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8469 ins_pipe( pipe_slow );
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8470 %}
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14. kvn parents: 1748 diff changeset	8471
0 a61af66fc99e Initial load duke parents: diff changeset	8472 // Integer Shift Instructions
a61af66fc99e Initial load duke parents: diff changeset	8473 // Shift Left by one
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8474 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8475 match(Set dst (LShiftI dst shift));
a61af66fc99e Initial load duke parents: diff changeset	8476 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8477
a61af66fc99e Initial load duke parents: diff changeset	8478 size(2);
a61af66fc99e Initial load duke parents: diff changeset	8479 format %{ "SHL $dst,$shift" %}
a61af66fc99e Initial load duke parents: diff changeset	8480 opcode(0xD1, 0x4); /* D1 /4 */
a61af66fc99e Initial load duke parents: diff changeset	8481 ins_encode( OpcP, RegOpc( dst ) );
a61af66fc99e Initial load duke parents: diff changeset	8482 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	8483 %}
a61af66fc99e Initial load duke parents: diff changeset	8484
a61af66fc99e Initial load duke parents: diff changeset	8485 // Shift Left by 8-bit immediate
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8486 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8487 match(Set dst (LShiftI dst shift));
a61af66fc99e Initial load duke parents: diff changeset	8488 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8489
a61af66fc99e Initial load duke parents: diff changeset	8490 size(3);
a61af66fc99e Initial load duke parents: diff changeset	8491 format %{ "SHL $dst,$shift" %}
a61af66fc99e Initial load duke parents: diff changeset	8492 opcode(0xC1, 0x4); /* C1 /4 ib */
a61af66fc99e Initial load duke parents: diff changeset	8493 ins_encode( RegOpcImm( dst, shift) );
a61af66fc99e Initial load duke parents: diff changeset	8494 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	8495 %}
a61af66fc99e Initial load duke parents: diff changeset	8496
a61af66fc99e Initial load duke parents: diff changeset	8497 // Shift Left by variable
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8498 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8499 match(Set dst (LShiftI dst shift));
a61af66fc99e Initial load duke parents: diff changeset	8500 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8501
a61af66fc99e Initial load duke parents: diff changeset	8502 size(2);
a61af66fc99e Initial load duke parents: diff changeset	8503 format %{ "SHL $dst,$shift" %}
a61af66fc99e Initial load duke parents: diff changeset	8504 opcode(0xD3, 0x4); /* D3 /4 */
a61af66fc99e Initial load duke parents: diff changeset	8505 ins_encode( OpcP, RegOpc( dst ) );
a61af66fc99e Initial load duke parents: diff changeset	8506 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	8507 %}
a61af66fc99e Initial load duke parents: diff changeset	8508
a61af66fc99e Initial load duke parents: diff changeset	8509 // Arithmetic shift right by one
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8510 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8511 match(Set dst (RShiftI dst shift));
a61af66fc99e Initial load duke parents: diff changeset	8512 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8513
a61af66fc99e Initial load duke parents: diff changeset	8514 size(2);
a61af66fc99e Initial load duke parents: diff changeset	8515 format %{ "SAR $dst,$shift" %}
a61af66fc99e Initial load duke parents: diff changeset	8516 opcode(0xD1, 0x7); /* D1 /7 */
a61af66fc99e Initial load duke parents: diff changeset	8517 ins_encode( OpcP, RegOpc( dst ) );
a61af66fc99e Initial load duke parents: diff changeset	8518 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	8519 %}
a61af66fc99e Initial load duke parents: diff changeset	8520
a61af66fc99e Initial load duke parents: diff changeset	8521 // Arithmetic shift right by one
a61af66fc99e Initial load duke parents: diff changeset	8522 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	8523 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
a61af66fc99e Initial load duke parents: diff changeset	8524 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8525 format %{ "SAR $dst,$shift" %}
a61af66fc99e Initial load duke parents: diff changeset	8526 opcode(0xD1, 0x7); /* D1 /7 */
a61af66fc99e Initial load duke parents: diff changeset	8527 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
a61af66fc99e Initial load duke parents: diff changeset	8528 ins_pipe( ialu_mem_imm );
a61af66fc99e Initial load duke parents: diff changeset	8529 %}
a61af66fc99e Initial load duke parents: diff changeset	8530
a61af66fc99e Initial load duke parents: diff changeset	8531 // Arithmetic Shift Right by 8-bit immediate
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8532 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8533 match(Set dst (RShiftI dst shift));
a61af66fc99e Initial load duke parents: diff changeset	8534 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8535
a61af66fc99e Initial load duke parents: diff changeset	8536 size(3);
a61af66fc99e Initial load duke parents: diff changeset	8537 format %{ "SAR $dst,$shift" %}
a61af66fc99e Initial load duke parents: diff changeset	8538 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load duke parents: diff changeset	8539 ins_encode( RegOpcImm( dst, shift ) );
a61af66fc99e Initial load duke parents: diff changeset	8540 ins_pipe( ialu_mem_imm );
a61af66fc99e Initial load duke parents: diff changeset	8541 %}
a61af66fc99e Initial load duke parents: diff changeset	8542
a61af66fc99e Initial load duke parents: diff changeset	8543 // Arithmetic Shift Right by 8-bit immediate
a61af66fc99e Initial load duke parents: diff changeset	8544 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	8545 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
a61af66fc99e Initial load duke parents: diff changeset	8546 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8547
a61af66fc99e Initial load duke parents: diff changeset	8548 format %{ "SAR $dst,$shift" %}
a61af66fc99e Initial load duke parents: diff changeset	8549 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load duke parents: diff changeset	8550 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
a61af66fc99e Initial load duke parents: diff changeset	8551 ins_pipe( ialu_mem_imm );
a61af66fc99e Initial load duke parents: diff changeset	8552 %}
a61af66fc99e Initial load duke parents: diff changeset	8553
a61af66fc99e Initial load duke parents: diff changeset	8554 // Arithmetic Shift Right by variable
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8555 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8556 match(Set dst (RShiftI dst shift));
a61af66fc99e Initial load duke parents: diff changeset	8557 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8558
a61af66fc99e Initial load duke parents: diff changeset	8559 size(2);
a61af66fc99e Initial load duke parents: diff changeset	8560 format %{ "SAR $dst,$shift" %}
a61af66fc99e Initial load duke parents: diff changeset	8561 opcode(0xD3, 0x7); /* D3 /7 */
a61af66fc99e Initial load duke parents: diff changeset	8562 ins_encode( OpcP, RegOpc( dst ) );
a61af66fc99e Initial load duke parents: diff changeset	8563 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	8564 %}
a61af66fc99e Initial load duke parents: diff changeset	8565
a61af66fc99e Initial load duke parents: diff changeset	8566 // Logical shift right by one
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8567 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8568 match(Set dst (URShiftI dst shift));
a61af66fc99e Initial load duke parents: diff changeset	8569 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8570
a61af66fc99e Initial load duke parents: diff changeset	8571 size(2);
a61af66fc99e Initial load duke parents: diff changeset	8572 format %{ "SHR $dst,$shift" %}
a61af66fc99e Initial load duke parents: diff changeset	8573 opcode(0xD1, 0x5); /* D1 /5 */
a61af66fc99e Initial load duke parents: diff changeset	8574 ins_encode( OpcP, RegOpc( dst ) );
a61af66fc99e Initial load duke parents: diff changeset	8575 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	8576 %}
a61af66fc99e Initial load duke parents: diff changeset	8577
a61af66fc99e Initial load duke parents: diff changeset	8578 // Logical Shift Right by 8-bit immediate
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8579 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8580 match(Set dst (URShiftI dst shift));
a61af66fc99e Initial load duke parents: diff changeset	8581 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8582
a61af66fc99e Initial load duke parents: diff changeset	8583 size(3);
a61af66fc99e Initial load duke parents: diff changeset	8584 format %{ "SHR $dst,$shift" %}
a61af66fc99e Initial load duke parents: diff changeset	8585 opcode(0xC1, 0x5); /* C1 /5 ib */
a61af66fc99e Initial load duke parents: diff changeset	8586 ins_encode( RegOpcImm( dst, shift) );
a61af66fc99e Initial load duke parents: diff changeset	8587 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	8588 %}
a61af66fc99e Initial load duke parents: diff changeset	8589
420 a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	8590
0 a61af66fc99e Initial load duke parents: diff changeset	8591 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
a61af66fc99e Initial load duke parents: diff changeset	8592 // This idiom is used by the compiler for the i2b bytecode.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8593 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8594 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
a61af66fc99e Initial load duke parents: diff changeset	8595
a61af66fc99e Initial load duke parents: diff changeset	8596 size(3);
a61af66fc99e Initial load duke parents: diff changeset	8597 format %{ "MOVSX $dst,$src :8" %}
785 2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	8598 ins_encode %{
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	8599 __ movsbl($dst$$Register, $src$$Register);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	8600 %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	8601 ins_pipe(ialu_reg_reg);
0 a61af66fc99e Initial load duke parents: diff changeset	8602 %}
a61af66fc99e Initial load duke parents: diff changeset	8603
a61af66fc99e Initial load duke parents: diff changeset	8604 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
a61af66fc99e Initial load duke parents: diff changeset	8605 // This idiom is used by the compiler the i2s bytecode.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8606 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8607 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
a61af66fc99e Initial load duke parents: diff changeset	8608
a61af66fc99e Initial load duke parents: diff changeset	8609 size(3);
a61af66fc99e Initial load duke parents: diff changeset	8610 format %{ "MOVSX $dst,$src :16" %}
785 2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	8611 ins_encode %{
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	8612 __ movswl($dst$$Register, $src$$Register);
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	8613 %}
2056494941db 6814842: Load shortening optimizations twisti parents: 775 diff changeset	8614 ins_pipe(ialu_reg_reg);
0 a61af66fc99e Initial load duke parents: diff changeset	8615 %}
a61af66fc99e Initial load duke parents: diff changeset	8616
a61af66fc99e Initial load duke parents: diff changeset	8617
a61af66fc99e Initial load duke parents: diff changeset	8618 // Logical Shift Right by variable
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8619 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8620 match(Set dst (URShiftI dst shift));
a61af66fc99e Initial load duke parents: diff changeset	8621 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8622
a61af66fc99e Initial load duke parents: diff changeset	8623 size(2);
a61af66fc99e Initial load duke parents: diff changeset	8624 format %{ "SHR $dst,$shift" %}
a61af66fc99e Initial load duke parents: diff changeset	8625 opcode(0xD3, 0x5); /* D3 /5 */
a61af66fc99e Initial load duke parents: diff changeset	8626 ins_encode( OpcP, RegOpc( dst ) );
a61af66fc99e Initial load duke parents: diff changeset	8627 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	8628 %}
a61af66fc99e Initial load duke parents: diff changeset	8629
a61af66fc99e Initial load duke parents: diff changeset	8630
a61af66fc99e Initial load duke parents: diff changeset	8631 //----------Logical Instructions-----------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	8632 //----------Integer Logical Instructions---------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	8633 // And Instructions
a61af66fc99e Initial load duke parents: diff changeset	8634 // And Register with Register
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8635 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8636 match(Set dst (AndI dst src));
a61af66fc99e Initial load duke parents: diff changeset	8637 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8638
a61af66fc99e Initial load duke parents: diff changeset	8639 size(2);
a61af66fc99e Initial load duke parents: diff changeset	8640 format %{ "AND $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8641 opcode(0x23);
a61af66fc99e Initial load duke parents: diff changeset	8642 ins_encode( OpcP, RegReg( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	8643 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	8644 %}
a61af66fc99e Initial load duke parents: diff changeset	8645
a61af66fc99e Initial load duke parents: diff changeset	8646 // And Register with Immediate
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8647 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8648 match(Set dst (AndI dst src));
a61af66fc99e Initial load duke parents: diff changeset	8649 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8650
a61af66fc99e Initial load duke parents: diff changeset	8651 format %{ "AND $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8652 opcode(0x81,0x04); /* Opcode 81 /4 */
a61af66fc99e Initial load duke parents: diff changeset	8653 // ins_encode( RegImm( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	8654 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
a61af66fc99e Initial load duke parents: diff changeset	8655 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	8656 %}
a61af66fc99e Initial load duke parents: diff changeset	8657
a61af66fc99e Initial load duke parents: diff changeset	8658 // And Register with Memory
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8659 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8660 match(Set dst (AndI dst (LoadI src)));
a61af66fc99e Initial load duke parents: diff changeset	8661 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8662
a61af66fc99e Initial load duke parents: diff changeset	8663 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	8664 format %{ "AND $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8665 opcode(0x23);
a61af66fc99e Initial load duke parents: diff changeset	8666 ins_encode( OpcP, RegMem( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	8667 ins_pipe( ialu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	8668 %}
a61af66fc99e Initial load duke parents: diff changeset	8669
a61af66fc99e Initial load duke parents: diff changeset	8670 // And Memory with Register
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8671 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8672 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
a61af66fc99e Initial load duke parents: diff changeset	8673 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8674
a61af66fc99e Initial load duke parents: diff changeset	8675 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	8676 format %{ "AND $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8677 opcode(0x21); /* Opcode 21 /r */
a61af66fc99e Initial load duke parents: diff changeset	8678 ins_encode( OpcP, RegMem( src, dst ) );
a61af66fc99e Initial load duke parents: diff changeset	8679 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	8680 %}
a61af66fc99e Initial load duke parents: diff changeset	8681
a61af66fc99e Initial load duke parents: diff changeset	8682 // And Memory with Immediate
a61af66fc99e Initial load duke parents: diff changeset	8683 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	8684 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
a61af66fc99e Initial load duke parents: diff changeset	8685 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8686
a61af66fc99e Initial load duke parents: diff changeset	8687 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	8688 format %{ "AND $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8689 opcode(0x81, 0x4); /* Opcode 81 /4 id */
a61af66fc99e Initial load duke parents: diff changeset	8690 // ins_encode( MemImm( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	8691 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
a61af66fc99e Initial load duke parents: diff changeset	8692 ins_pipe( ialu_mem_imm );
a61af66fc99e Initial load duke parents: diff changeset	8693 %}
a61af66fc99e Initial load duke parents: diff changeset	8694
a61af66fc99e Initial load duke parents: diff changeset	8695 // Or Instructions
a61af66fc99e Initial load duke parents: diff changeset	8696 // Or Register with Register
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8697 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8698 match(Set dst (OrI dst src));
a61af66fc99e Initial load duke parents: diff changeset	8699 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8700
a61af66fc99e Initial load duke parents: diff changeset	8701 size(2);
a61af66fc99e Initial load duke parents: diff changeset	8702 format %{ "OR $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8703 opcode(0x0B);
a61af66fc99e Initial load duke parents: diff changeset	8704 ins_encode( OpcP, RegReg( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	8705 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	8706 %}
a61af66fc99e Initial load duke parents: diff changeset	8707
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8708 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
420 a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	8709 match(Set dst (OrI dst (CastP2X src)));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	8710 effect(KILL cr);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	8711
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	8712 size(2);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	8713 format %{ "OR $dst,$src" %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	8714 opcode(0x0B);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	8715 ins_encode( OpcP, RegReg( dst, src) );
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	8716 ins_pipe( ialu_reg_reg );
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	8717 %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	8718
a1980da045cc 6462850: generate biased locking code in C2 ideal graph kvn parents: 415 diff changeset	8719
0 a61af66fc99e Initial load duke parents: diff changeset	8720 // Or Register with Immediate
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8721 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8722 match(Set dst (OrI dst src));
a61af66fc99e Initial load duke parents: diff changeset	8723 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8724
a61af66fc99e Initial load duke parents: diff changeset	8725 format %{ "OR $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8726 opcode(0x81,0x01); /* Opcode 81 /1 id */
a61af66fc99e Initial load duke parents: diff changeset	8727 // ins_encode( RegImm( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	8728 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
a61af66fc99e Initial load duke parents: diff changeset	8729 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	8730 %}
a61af66fc99e Initial load duke parents: diff changeset	8731
a61af66fc99e Initial load duke parents: diff changeset	8732 // Or Register with Memory
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8733 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8734 match(Set dst (OrI dst (LoadI src)));
a61af66fc99e Initial load duke parents: diff changeset	8735 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8736
a61af66fc99e Initial load duke parents: diff changeset	8737 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	8738 format %{ "OR $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8739 opcode(0x0B);
a61af66fc99e Initial load duke parents: diff changeset	8740 ins_encode( OpcP, RegMem( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	8741 ins_pipe( ialu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	8742 %}
a61af66fc99e Initial load duke parents: diff changeset	8743
a61af66fc99e Initial load duke parents: diff changeset	8744 // Or Memory with Register
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8745 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8746 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
a61af66fc99e Initial load duke parents: diff changeset	8747 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8748
a61af66fc99e Initial load duke parents: diff changeset	8749 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	8750 format %{ "OR $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8751 opcode(0x09); /* Opcode 09 /r */
a61af66fc99e Initial load duke parents: diff changeset	8752 ins_encode( OpcP, RegMem( src, dst ) );
a61af66fc99e Initial load duke parents: diff changeset	8753 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	8754 %}
a61af66fc99e Initial load duke parents: diff changeset	8755
a61af66fc99e Initial load duke parents: diff changeset	8756 // Or Memory with Immediate
a61af66fc99e Initial load duke parents: diff changeset	8757 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	8758 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
a61af66fc99e Initial load duke parents: diff changeset	8759 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8760
a61af66fc99e Initial load duke parents: diff changeset	8761 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	8762 format %{ "OR $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8763 opcode(0x81,0x1); /* Opcode 81 /1 id */
a61af66fc99e Initial load duke parents: diff changeset	8764 // ins_encode( MemImm( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	8765 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
a61af66fc99e Initial load duke parents: diff changeset	8766 ins_pipe( ialu_mem_imm );
a61af66fc99e Initial load duke parents: diff changeset	8767 %}
a61af66fc99e Initial load duke parents: diff changeset	8768
a61af66fc99e Initial load duke parents: diff changeset	8769 // ROL/ROR
a61af66fc99e Initial load duke parents: diff changeset	8770 // ROL expand
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8771 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8772 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8773
a61af66fc99e Initial load duke parents: diff changeset	8774 format %{ "ROL $dst, $shift" %}
a61af66fc99e Initial load duke parents: diff changeset	8775 opcode(0xD1, 0x0); /* Opcode D1 /0 */
a61af66fc99e Initial load duke parents: diff changeset	8776 ins_encode( OpcP, RegOpc( dst ));
a61af66fc99e Initial load duke parents: diff changeset	8777 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	8778 %}
a61af66fc99e Initial load duke parents: diff changeset	8779
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8780 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8781 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8782
a61af66fc99e Initial load duke parents: diff changeset	8783 format %{ "ROL $dst, $shift" %}
a61af66fc99e Initial load duke parents: diff changeset	8784 opcode(0xC1, 0x0); /Opcode /C1 /0 /
a61af66fc99e Initial load duke parents: diff changeset	8785 ins_encode( RegOpcImm(dst, shift) );
a61af66fc99e Initial load duke parents: diff changeset	8786 ins_pipe(ialu_reg);
a61af66fc99e Initial load duke parents: diff changeset	8787 %}
a61af66fc99e Initial load duke parents: diff changeset	8788
a61af66fc99e Initial load duke parents: diff changeset	8789 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	8790 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8791
a61af66fc99e Initial load duke parents: diff changeset	8792 format %{ "ROL $dst, $shift" %}
a61af66fc99e Initial load duke parents: diff changeset	8793 opcode(0xD3, 0x0); /* Opcode D3 /0 */
a61af66fc99e Initial load duke parents: diff changeset	8794 ins_encode(OpcP, RegOpc(dst));
a61af66fc99e Initial load duke parents: diff changeset	8795 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	8796 %}
a61af66fc99e Initial load duke parents: diff changeset	8797 // end of ROL expand
a61af66fc99e Initial load duke parents: diff changeset	8798
a61af66fc99e Initial load duke parents: diff changeset	8799 // ROL 32bit by one once
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8800 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8801 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
a61af66fc99e Initial load duke parents: diff changeset	8802
a61af66fc99e Initial load duke parents: diff changeset	8803 expand %{
a61af66fc99e Initial load duke parents: diff changeset	8804 rolI_eReg_imm1(dst, lshift, cr);
a61af66fc99e Initial load duke parents: diff changeset	8805 %}
a61af66fc99e Initial load duke parents: diff changeset	8806 %}
a61af66fc99e Initial load duke parents: diff changeset	8807
a61af66fc99e Initial load duke parents: diff changeset	8808 // ROL 32bit var by imm8 once
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8809 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8810 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
a61af66fc99e Initial load duke parents: diff changeset	8811 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
a61af66fc99e Initial load duke parents: diff changeset	8812
a61af66fc99e Initial load duke parents: diff changeset	8813 expand %{
a61af66fc99e Initial load duke parents: diff changeset	8814 rolI_eReg_imm8(dst, lshift, cr);
a61af66fc99e Initial load duke parents: diff changeset	8815 %}
a61af66fc99e Initial load duke parents: diff changeset	8816 %}
a61af66fc99e Initial load duke parents: diff changeset	8817
a61af66fc99e Initial load duke parents: diff changeset	8818 // ROL 32bit var by var once
a61af66fc99e Initial load duke parents: diff changeset	8819 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	8820 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
a61af66fc99e Initial load duke parents: diff changeset	8821
a61af66fc99e Initial load duke parents: diff changeset	8822 expand %{
a61af66fc99e Initial load duke parents: diff changeset	8823 rolI_eReg_CL(dst, shift, cr);
a61af66fc99e Initial load duke parents: diff changeset	8824 %}
a61af66fc99e Initial load duke parents: diff changeset	8825 %}
a61af66fc99e Initial load duke parents: diff changeset	8826
a61af66fc99e Initial load duke parents: diff changeset	8827 // ROL 32bit var by var once
a61af66fc99e Initial load duke parents: diff changeset	8828 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	8829 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
a61af66fc99e Initial load duke parents: diff changeset	8830
a61af66fc99e Initial load duke parents: diff changeset	8831 expand %{
a61af66fc99e Initial load duke parents: diff changeset	8832 rolI_eReg_CL(dst, shift, cr);
a61af66fc99e Initial load duke parents: diff changeset	8833 %}
a61af66fc99e Initial load duke parents: diff changeset	8834 %}
a61af66fc99e Initial load duke parents: diff changeset	8835
a61af66fc99e Initial load duke parents: diff changeset	8836 // ROR expand
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8837 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8838 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8839
a61af66fc99e Initial load duke parents: diff changeset	8840 format %{ "ROR $dst, $shift" %}
a61af66fc99e Initial load duke parents: diff changeset	8841 opcode(0xD1,0x1); /* Opcode D1 /1 */
a61af66fc99e Initial load duke parents: diff changeset	8842 ins_encode( OpcP, RegOpc( dst ) );
a61af66fc99e Initial load duke parents: diff changeset	8843 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	8844 %}
a61af66fc99e Initial load duke parents: diff changeset	8845
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8846 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8847 effect (USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8848
a61af66fc99e Initial load duke parents: diff changeset	8849 format %{ "ROR $dst, $shift" %}
a61af66fc99e Initial load duke parents: diff changeset	8850 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
a61af66fc99e Initial load duke parents: diff changeset	8851 ins_encode( RegOpcImm(dst, shift) );
a61af66fc99e Initial load duke parents: diff changeset	8852 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	8853 %}
a61af66fc99e Initial load duke parents: diff changeset	8854
a61af66fc99e Initial load duke parents: diff changeset	8855 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
a61af66fc99e Initial load duke parents: diff changeset	8856 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8857
a61af66fc99e Initial load duke parents: diff changeset	8858 format %{ "ROR $dst, $shift" %}
a61af66fc99e Initial load duke parents: diff changeset	8859 opcode(0xD3, 0x1); /* Opcode D3 /1 */
a61af66fc99e Initial load duke parents: diff changeset	8860 ins_encode(OpcP, RegOpc(dst));
a61af66fc99e Initial load duke parents: diff changeset	8861 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	8862 %}
a61af66fc99e Initial load duke parents: diff changeset	8863 // end of ROR expand
a61af66fc99e Initial load duke parents: diff changeset	8864
a61af66fc99e Initial load duke parents: diff changeset	8865 // ROR right once
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8866 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8867 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
a61af66fc99e Initial load duke parents: diff changeset	8868
a61af66fc99e Initial load duke parents: diff changeset	8869 expand %{
a61af66fc99e Initial load duke parents: diff changeset	8870 rorI_eReg_imm1(dst, rshift, cr);
a61af66fc99e Initial load duke parents: diff changeset	8871 %}
a61af66fc99e Initial load duke parents: diff changeset	8872 %}
a61af66fc99e Initial load duke parents: diff changeset	8873
a61af66fc99e Initial load duke parents: diff changeset	8874 // ROR 32bit by immI8 once
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8875 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8876 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
a61af66fc99e Initial load duke parents: diff changeset	8877 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
a61af66fc99e Initial load duke parents: diff changeset	8878
a61af66fc99e Initial load duke parents: diff changeset	8879 expand %{
a61af66fc99e Initial load duke parents: diff changeset	8880 rorI_eReg_imm8(dst, rshift, cr);
a61af66fc99e Initial load duke parents: diff changeset	8881 %}
a61af66fc99e Initial load duke parents: diff changeset	8882 %}
a61af66fc99e Initial load duke parents: diff changeset	8883
a61af66fc99e Initial load duke parents: diff changeset	8884 // ROR 32bit var by var once
a61af66fc99e Initial load duke parents: diff changeset	8885 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	8886 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
a61af66fc99e Initial load duke parents: diff changeset	8887
a61af66fc99e Initial load duke parents: diff changeset	8888 expand %{
a61af66fc99e Initial load duke parents: diff changeset	8889 rorI_eReg_CL(dst, shift, cr);
a61af66fc99e Initial load duke parents: diff changeset	8890 %}
a61af66fc99e Initial load duke parents: diff changeset	8891 %}
a61af66fc99e Initial load duke parents: diff changeset	8892
a61af66fc99e Initial load duke parents: diff changeset	8893 // ROR 32bit var by var once
a61af66fc99e Initial load duke parents: diff changeset	8894 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	8895 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
a61af66fc99e Initial load duke parents: diff changeset	8896
a61af66fc99e Initial load duke parents: diff changeset	8897 expand %{
a61af66fc99e Initial load duke parents: diff changeset	8898 rorI_eReg_CL(dst, shift, cr);
a61af66fc99e Initial load duke parents: diff changeset	8899 %}
a61af66fc99e Initial load duke parents: diff changeset	8900 %}
a61af66fc99e Initial load duke parents: diff changeset	8901
a61af66fc99e Initial load duke parents: diff changeset	8902 // Xor Instructions
a61af66fc99e Initial load duke parents: diff changeset	8903 // Xor Register with Register
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8904 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8905 match(Set dst (XorI dst src));
a61af66fc99e Initial load duke parents: diff changeset	8906 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8907
a61af66fc99e Initial load duke parents: diff changeset	8908 size(2);
a61af66fc99e Initial load duke parents: diff changeset	8909 format %{ "XOR $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8910 opcode(0x33);
a61af66fc99e Initial load duke parents: diff changeset	8911 ins_encode( OpcP, RegReg( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	8912 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	8913 %}
a61af66fc99e Initial load duke parents: diff changeset	8914
403 b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	8915 // Xor Register with Immediate -1
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8916 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
403 b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	8917 match(Set dst (XorI dst imm));
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	8918
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	8919 size(2);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	8920 format %{ "NOT $dst" %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	8921 ins_encode %{
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	8922 __ notl($dst$$Register);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	8923 %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	8924 ins_pipe( ialu_reg );
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	8925 %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	8926
0 a61af66fc99e Initial load duke parents: diff changeset	8927 // Xor Register with Immediate
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8928 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8929 match(Set dst (XorI dst src));
a61af66fc99e Initial load duke parents: diff changeset	8930 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8931
a61af66fc99e Initial load duke parents: diff changeset	8932 format %{ "XOR $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8933 opcode(0x81,0x06); /* Opcode 81 /6 id */
a61af66fc99e Initial load duke parents: diff changeset	8934 // ins_encode( RegImm( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	8935 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
a61af66fc99e Initial load duke parents: diff changeset	8936 ins_pipe( ialu_reg );
a61af66fc99e Initial load duke parents: diff changeset	8937 %}
a61af66fc99e Initial load duke parents: diff changeset	8938
a61af66fc99e Initial load duke parents: diff changeset	8939 // Xor Register with Memory
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8940 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8941 match(Set dst (XorI dst (LoadI src)));
a61af66fc99e Initial load duke parents: diff changeset	8942 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8943
a61af66fc99e Initial load duke parents: diff changeset	8944 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	8945 format %{ "XOR $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8946 opcode(0x33);
a61af66fc99e Initial load duke parents: diff changeset	8947 ins_encode( OpcP, RegMem(dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	8948 ins_pipe( ialu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	8949 %}
a61af66fc99e Initial load duke parents: diff changeset	8950
a61af66fc99e Initial load duke parents: diff changeset	8951 // Xor Memory with Register
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8952 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8953 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
a61af66fc99e Initial load duke parents: diff changeset	8954 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8955
a61af66fc99e Initial load duke parents: diff changeset	8956 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	8957 format %{ "XOR $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8958 opcode(0x31); /* Opcode 31 /r */
a61af66fc99e Initial load duke parents: diff changeset	8959 ins_encode( OpcP, RegMem( src, dst ) );
a61af66fc99e Initial load duke parents: diff changeset	8960 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	8961 %}
a61af66fc99e Initial load duke parents: diff changeset	8962
a61af66fc99e Initial load duke parents: diff changeset	8963 // Xor Memory with Immediate
a61af66fc99e Initial load duke parents: diff changeset	8964 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	8965 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
a61af66fc99e Initial load duke parents: diff changeset	8966 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	8967
a61af66fc99e Initial load duke parents: diff changeset	8968 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	8969 format %{ "XOR $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8970 opcode(0x81,0x6); /* Opcode 81 /6 id */
a61af66fc99e Initial load duke parents: diff changeset	8971 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
a61af66fc99e Initial load duke parents: diff changeset	8972 ins_pipe( ialu_mem_imm );
a61af66fc99e Initial load duke parents: diff changeset	8973 %}
a61af66fc99e Initial load duke parents: diff changeset	8974
a61af66fc99e Initial load duke parents: diff changeset	8975 //----------Convert Int to Boolean---------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	8976
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8977 instruct movI_nocopy(rRegI dst, rRegI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8978 effect( DEF dst, USE src );
a61af66fc99e Initial load duke parents: diff changeset	8979 format %{ "MOV $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8980 ins_encode( enc_Copy( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	8981 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	8982 %}
a61af66fc99e Initial load duke parents: diff changeset	8983
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8984 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8985 effect( USE_DEF dst, USE src, KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	8986
a61af66fc99e Initial load duke parents: diff changeset	8987 size(4);
a61af66fc99e Initial load duke parents: diff changeset	8988 format %{ "NEG $dst\n\t"
a61af66fc99e Initial load duke parents: diff changeset	8989 "ADC $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	8990 ins_encode( neg_reg(dst),
a61af66fc99e Initial load duke parents: diff changeset	8991 OpcRegReg(0x13,dst,src) );
a61af66fc99e Initial load duke parents: diff changeset	8992 ins_pipe( ialu_reg_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	8993 %}
a61af66fc99e Initial load duke parents: diff changeset	8994
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	8995 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	8996 match(Set dst (Conv2B src));
a61af66fc99e Initial load duke parents: diff changeset	8997
a61af66fc99e Initial load duke parents: diff changeset	8998 expand %{
a61af66fc99e Initial load duke parents: diff changeset	8999 movI_nocopy(dst,src);
a61af66fc99e Initial load duke parents: diff changeset	9000 ci2b(dst,src,cr);
a61af66fc99e Initial load duke parents: diff changeset	9001 %}
a61af66fc99e Initial load duke parents: diff changeset	9002 %}
a61af66fc99e Initial load duke parents: diff changeset	9003
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	9004 instruct movP_nocopy(rRegI dst, eRegP src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9005 effect( DEF dst, USE src );
a61af66fc99e Initial load duke parents: diff changeset	9006 format %{ "MOV $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	9007 ins_encode( enc_Copy( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	9008 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	9009 %}
a61af66fc99e Initial load duke parents: diff changeset	9010
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	9011 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9012 effect( USE_DEF dst, USE src, KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	9013 format %{ "NEG $dst\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9014 "ADC $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	9015 ins_encode( neg_reg(dst),
a61af66fc99e Initial load duke parents: diff changeset	9016 OpcRegReg(0x13,dst,src) );
a61af66fc99e Initial load duke parents: diff changeset	9017 ins_pipe( ialu_reg_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9018 %}
a61af66fc99e Initial load duke parents: diff changeset	9019
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	9020 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9021 match(Set dst (Conv2B src));
a61af66fc99e Initial load duke parents: diff changeset	9022
a61af66fc99e Initial load duke parents: diff changeset	9023 expand %{
a61af66fc99e Initial load duke parents: diff changeset	9024 movP_nocopy(dst,src);
a61af66fc99e Initial load duke parents: diff changeset	9025 cp2b(dst,src,cr);
a61af66fc99e Initial load duke parents: diff changeset	9026 %}
a61af66fc99e Initial load duke parents: diff changeset	9027 %}
a61af66fc99e Initial load duke parents: diff changeset	9028
9154 886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9029 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9030 match(Set dst (CmpLTMask p q));
9154 886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9031 effect(KILL cr);
0 a61af66fc99e Initial load duke parents: diff changeset	9032 ins_cost(400);
a61af66fc99e Initial load duke parents: diff changeset	9033
a61af66fc99e Initial load duke parents: diff changeset	9034 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
a61af66fc99e Initial load duke parents: diff changeset	9035 format %{ "XOR $dst,$dst\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9036 "CMP $p,$q\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9037 "SETlt $dst\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9038 "NEG $dst" %}
9154 886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9039 ins_encode %{
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9040 Register Rp = $p$$Register;
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9041 Register Rq = $q$$Register;
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9042 Register Rd = $dst$$Register;
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9043 Label done;
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9044 __ xorl(Rd, Rd);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9045 __ cmpl(Rp, Rq);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9046 __ setb(Assembler::less, Rd);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9047 __ negl(Rd);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9048 %}
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9049
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9050 ins_pipe(pipe_slow);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9051 %}
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9052
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9053 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9054 match(Set dst (CmpLTMask dst zero));
9154 886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9055 effect(DEF dst, KILL cr);
0 a61af66fc99e Initial load duke parents: diff changeset	9056 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	9057
9154 886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9058 format %{ "SAR $dst,31\t# cmpLTMask0" %}
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9059 ins_encode %{
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9060 __ sarl($dst$$Register, 31);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9061 %}
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9062 ins_pipe(ialu_reg);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9063 %}
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9064
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9065 /* better to save a register than avoid a branch */
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9066 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9067 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9154 886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9068 effect(KILL cr);
0 a61af66fc99e Initial load duke parents: diff changeset	9069 ins_cost(400);
9154 886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9070 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t"
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9071 "JGE done\n\t"
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9072 "ADD $p,$y\n"
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9073 "done: " %}
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9074 ins_encode %{
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9075 Register Rp = $p$$Register;
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9076 Register Rq = $q$$Register;
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9077 Register Ry = $y$$Register;
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9078 Label done;
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9079 __ subl(Rp, Rq);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9080 __ jccb(Assembler::greaterEqual, done);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9081 __ addl(Rp, Ry);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9082 __ bind(done);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9083 %}
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9084
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9085 ins_pipe(pipe_cmplt);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9086 %}
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9087
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9088 /* better to save a register than avoid a branch */
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9089 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9090 match(Set y (AndI (CmpLTMask p q) y));
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9091 effect(KILL cr);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9092
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9093 ins_cost(300);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9094
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9095 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t"
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9096 "JLT done\n\t"
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9097 "XORL $y, $y\n"
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9098 "done: " %}
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9099 ins_encode %{
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9100 Register Rp = $p$$Register;
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9101 Register Rq = $q$$Register;
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9102 Register Ry = $y$$Register;
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9103 Label done;
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9104 __ cmpl(Rp, Rq);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9105 __ jccb(Assembler::less, done);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9106 __ xorl(Ry, Ry);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9107 __ bind(done);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9108 %}
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9109
886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9110 ins_pipe(pipe_cmplt);
0 a61af66fc99e Initial load duke parents: diff changeset	9111 %}
a61af66fc99e Initial load duke parents: diff changeset	9112
a61af66fc99e Initial load duke parents: diff changeset	9113 /* If I enable this, I encourage spilling in the inner loop of compress.
9154 886d1fd67dc3 6443505: Ideal() function for CmpLTMask drchase parents: 8873 diff changeset	9114 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9115 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
a61af66fc99e Initial load duke parents: diff changeset	9116 */
a61af66fc99e Initial load duke parents: diff changeset	9117
a61af66fc99e Initial load duke parents: diff changeset	9118 //----------Long Instructions------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	9119 // Add Long Register with Register
a61af66fc99e Initial load duke parents: diff changeset	9120 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9121 match(Set dst (AddL dst src));
a61af66fc99e Initial load duke parents: diff changeset	9122 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9123 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	9124 format %{ "ADD $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9125 "ADC $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	9126 opcode(0x03, 0x13);
a61af66fc99e Initial load duke parents: diff changeset	9127 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
a61af66fc99e Initial load duke parents: diff changeset	9128 ins_pipe( ialu_reg_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9129 %}
a61af66fc99e Initial load duke parents: diff changeset	9130
a61af66fc99e Initial load duke parents: diff changeset	9131 // Add Long Register with Immediate
a61af66fc99e Initial load duke parents: diff changeset	9132 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9133 match(Set dst (AddL dst src));
a61af66fc99e Initial load duke parents: diff changeset	9134 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9135 format %{ "ADD $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9136 "ADC $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	9137 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
a61af66fc99e Initial load duke parents: diff changeset	9138 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	9139 ins_pipe( ialu_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9140 %}
a61af66fc99e Initial load duke parents: diff changeset	9141
a61af66fc99e Initial load duke parents: diff changeset	9142 // Add Long Register with Memory
a61af66fc99e Initial load duke parents: diff changeset	9143 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9144 match(Set dst (AddL dst (LoadL mem)));
a61af66fc99e Initial load duke parents: diff changeset	9145 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9146 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	9147 format %{ "ADD $dst.lo,$mem\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9148 "ADC $dst.hi,$mem+4" %}
a61af66fc99e Initial load duke parents: diff changeset	9149 opcode(0x03, 0x13);
a61af66fc99e Initial load duke parents: diff changeset	9150 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
a61af66fc99e Initial load duke parents: diff changeset	9151 ins_pipe( ialu_reg_long_mem );
a61af66fc99e Initial load duke parents: diff changeset	9152 %}
a61af66fc99e Initial load duke parents: diff changeset	9153
a61af66fc99e Initial load duke parents: diff changeset	9154 // Subtract Long Register with Register.
a61af66fc99e Initial load duke parents: diff changeset	9155 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9156 match(Set dst (SubL dst src));
a61af66fc99e Initial load duke parents: diff changeset	9157 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9158 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	9159 format %{ "SUB $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9160 "SBB $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	9161 opcode(0x2B, 0x1B);
a61af66fc99e Initial load duke parents: diff changeset	9162 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
a61af66fc99e Initial load duke parents: diff changeset	9163 ins_pipe( ialu_reg_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9164 %}
a61af66fc99e Initial load duke parents: diff changeset	9165
a61af66fc99e Initial load duke parents: diff changeset	9166 // Subtract Long Register with Immediate
a61af66fc99e Initial load duke parents: diff changeset	9167 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9168 match(Set dst (SubL dst src));
a61af66fc99e Initial load duke parents: diff changeset	9169 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9170 format %{ "SUB $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9171 "SBB $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	9172 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
a61af66fc99e Initial load duke parents: diff changeset	9173 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	9174 ins_pipe( ialu_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9175 %}
a61af66fc99e Initial load duke parents: diff changeset	9176
a61af66fc99e Initial load duke parents: diff changeset	9177 // Subtract Long Register with Memory
a61af66fc99e Initial load duke parents: diff changeset	9178 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9179 match(Set dst (SubL dst (LoadL mem)));
a61af66fc99e Initial load duke parents: diff changeset	9180 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9181 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	9182 format %{ "SUB $dst.lo,$mem\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9183 "SBB $dst.hi,$mem+4" %}
a61af66fc99e Initial load duke parents: diff changeset	9184 opcode(0x2B, 0x1B);
a61af66fc99e Initial load duke parents: diff changeset	9185 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
a61af66fc99e Initial load duke parents: diff changeset	9186 ins_pipe( ialu_reg_long_mem );
a61af66fc99e Initial load duke parents: diff changeset	9187 %}
a61af66fc99e Initial load duke parents: diff changeset	9188
a61af66fc99e Initial load duke parents: diff changeset	9189 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9190 match(Set dst (SubL zero dst));
a61af66fc99e Initial load duke parents: diff changeset	9191 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9192 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	9193 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
a61af66fc99e Initial load duke parents: diff changeset	9194 ins_encode( neg_long(dst) );
a61af66fc99e Initial load duke parents: diff changeset	9195 ins_pipe( ialu_reg_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9196 %}
a61af66fc99e Initial load duke parents: diff changeset	9197
a61af66fc99e Initial load duke parents: diff changeset	9198 // And Long Register with Register
a61af66fc99e Initial load duke parents: diff changeset	9199 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9200 match(Set dst (AndL dst src));
a61af66fc99e Initial load duke parents: diff changeset	9201 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9202 format %{ "AND $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9203 "AND $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	9204 opcode(0x23,0x23);
a61af66fc99e Initial load duke parents: diff changeset	9205 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	9206 ins_pipe( ialu_reg_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9207 %}
a61af66fc99e Initial load duke parents: diff changeset	9208
a61af66fc99e Initial load duke parents: diff changeset	9209 // And Long Register with Immediate
a61af66fc99e Initial load duke parents: diff changeset	9210 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9211 match(Set dst (AndL dst src));
a61af66fc99e Initial load duke parents: diff changeset	9212 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9213 format %{ "AND $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9214 "AND $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	9215 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
a61af66fc99e Initial load duke parents: diff changeset	9216 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	9217 ins_pipe( ialu_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9218 %}
a61af66fc99e Initial load duke parents: diff changeset	9219
a61af66fc99e Initial load duke parents: diff changeset	9220 // And Long Register with Memory
a61af66fc99e Initial load duke parents: diff changeset	9221 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9222 match(Set dst (AndL dst (LoadL mem)));
a61af66fc99e Initial load duke parents: diff changeset	9223 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9224 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	9225 format %{ "AND $dst.lo,$mem\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9226 "AND $dst.hi,$mem+4" %}
a61af66fc99e Initial load duke parents: diff changeset	9227 opcode(0x23, 0x23);
a61af66fc99e Initial load duke parents: diff changeset	9228 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
a61af66fc99e Initial load duke parents: diff changeset	9229 ins_pipe( ialu_reg_long_mem );
a61af66fc99e Initial load duke parents: diff changeset	9230 %}
a61af66fc99e Initial load duke parents: diff changeset	9231
a61af66fc99e Initial load duke parents: diff changeset	9232 // Or Long Register with Register
a61af66fc99e Initial load duke parents: diff changeset	9233 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9234 match(Set dst (OrL dst src));
a61af66fc99e Initial load duke parents: diff changeset	9235 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9236 format %{ "OR $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9237 "OR $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	9238 opcode(0x0B,0x0B);
a61af66fc99e Initial load duke parents: diff changeset	9239 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	9240 ins_pipe( ialu_reg_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9241 %}
a61af66fc99e Initial load duke parents: diff changeset	9242
a61af66fc99e Initial load duke parents: diff changeset	9243 // Or Long Register with Immediate
a61af66fc99e Initial load duke parents: diff changeset	9244 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9245 match(Set dst (OrL dst src));
a61af66fc99e Initial load duke parents: diff changeset	9246 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9247 format %{ "OR $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9248 "OR $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	9249 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
a61af66fc99e Initial load duke parents: diff changeset	9250 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	9251 ins_pipe( ialu_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9252 %}
a61af66fc99e Initial load duke parents: diff changeset	9253
a61af66fc99e Initial load duke parents: diff changeset	9254 // Or Long Register with Memory
a61af66fc99e Initial load duke parents: diff changeset	9255 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9256 match(Set dst (OrL dst (LoadL mem)));
a61af66fc99e Initial load duke parents: diff changeset	9257 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9258 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	9259 format %{ "OR $dst.lo,$mem\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9260 "OR $dst.hi,$mem+4" %}
a61af66fc99e Initial load duke parents: diff changeset	9261 opcode(0x0B,0x0B);
a61af66fc99e Initial load duke parents: diff changeset	9262 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
a61af66fc99e Initial load duke parents: diff changeset	9263 ins_pipe( ialu_reg_long_mem );
a61af66fc99e Initial load duke parents: diff changeset	9264 %}
a61af66fc99e Initial load duke parents: diff changeset	9265
a61af66fc99e Initial load duke parents: diff changeset	9266 // Xor Long Register with Register
a61af66fc99e Initial load duke parents: diff changeset	9267 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9268 match(Set dst (XorL dst src));
a61af66fc99e Initial load duke parents: diff changeset	9269 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9270 format %{ "XOR $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9271 "XOR $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	9272 opcode(0x33,0x33);
a61af66fc99e Initial load duke parents: diff changeset	9273 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	9274 ins_pipe( ialu_reg_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9275 %}
a61af66fc99e Initial load duke parents: diff changeset	9276
403 b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	9277 // Xor Long Register with Immediate -1
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	9278 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	9279 match(Set dst (XorL dst imm));
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	9280 format %{ "NOT $dst.lo\n\t"
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	9281 "NOT $dst.hi" %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	9282 ins_encode %{
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	9283 __ notl($dst$$Register);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	9284 __ notl(HIGH_FROM_LOW($dst$$Register));
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	9285 %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	9286 ins_pipe( ialu_reg_long );
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	9287 %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86 rasbold parents: 304 diff changeset	9288
0 a61af66fc99e Initial load duke parents: diff changeset	9289 // Xor Long Register with Immediate
a61af66fc99e Initial load duke parents: diff changeset	9290 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9291 match(Set dst (XorL dst src));
a61af66fc99e Initial load duke parents: diff changeset	9292 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9293 format %{ "XOR $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9294 "XOR $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	9295 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
a61af66fc99e Initial load duke parents: diff changeset	9296 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	9297 ins_pipe( ialu_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9298 %}
a61af66fc99e Initial load duke parents: diff changeset	9299
a61af66fc99e Initial load duke parents: diff changeset	9300 // Xor Long Register with Memory
a61af66fc99e Initial load duke parents: diff changeset	9301 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9302 match(Set dst (XorL dst (LoadL mem)));
a61af66fc99e Initial load duke parents: diff changeset	9303 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9304 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	9305 format %{ "XOR $dst.lo,$mem\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9306 "XOR $dst.hi,$mem+4" %}
a61af66fc99e Initial load duke parents: diff changeset	9307 opcode(0x33,0x33);
a61af66fc99e Initial load duke parents: diff changeset	9308 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
a61af66fc99e Initial load duke parents: diff changeset	9309 ins_pipe( ialu_reg_long_mem );
a61af66fc99e Initial load duke parents: diff changeset	9310 %}
a61af66fc99e Initial load duke parents: diff changeset	9311
219 ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9312 // Shift Left Long by 1
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9313 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9314 predicate(UseNewLongLShift);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9315 match(Set dst (LShiftL dst cnt));
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9316 effect(KILL cr);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9317 ins_cost(100);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9318 format %{ "ADD $dst.lo,$dst.lo\n\t"
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9319 "ADC $dst.hi,$dst.hi" %}
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9320 ins_encode %{
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9321 __ addl($dst$$Register,$dst$$Register);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9322 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9323 %}
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9324 ins_pipe( ialu_reg_long );
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9325 %}
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9326
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9327 // Shift Left Long by 2
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9328 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9329 predicate(UseNewLongLShift);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9330 match(Set dst (LShiftL dst cnt));
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9331 effect(KILL cr);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9332 ins_cost(100);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9333 format %{ "ADD $dst.lo,$dst.lo\n\t"
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9334 "ADC $dst.hi,$dst.hi\n\t"
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9335 "ADD $dst.lo,$dst.lo\n\t"
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9336 "ADC $dst.hi,$dst.hi" %}
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9337 ins_encode %{
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9338 __ addl($dst$$Register,$dst$$Register);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9339 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9340 __ addl($dst$$Register,$dst$$Register);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9341 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9342 %}
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9343 ins_pipe( ialu_reg_long );
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9344 %}
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9345
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9346 // Shift Left Long by 3
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9347 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9348 predicate(UseNewLongLShift);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9349 match(Set dst (LShiftL dst cnt));
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9350 effect(KILL cr);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9351 ins_cost(100);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9352 format %{ "ADD $dst.lo,$dst.lo\n\t"
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9353 "ADC $dst.hi,$dst.hi\n\t"
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9354 "ADD $dst.lo,$dst.lo\n\t"
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9355 "ADC $dst.hi,$dst.hi\n\t"
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9356 "ADD $dst.lo,$dst.lo\n\t"
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9357 "ADC $dst.hi,$dst.hi" %}
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9358 ins_encode %{
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9359 __ addl($dst$$Register,$dst$$Register);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9360 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9361 __ addl($dst$$Register,$dst$$Register);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9362 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9363 __ addl($dst$$Register,$dst$$Register);
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9364 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9365 %}
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9366 ins_pipe( ialu_reg_long );
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9367 %}
ab65a4c9b2e8 6708714: Optimize long LShift on 32-bits x86 kvn parents: 169 diff changeset	9368
0 a61af66fc99e Initial load duke parents: diff changeset	9369 // Shift Left Long by 1-31
a61af66fc99e Initial load duke parents: diff changeset	9370 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9371 match(Set dst (LShiftL dst cnt));
a61af66fc99e Initial load duke parents: diff changeset	9372 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9373 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	9374 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9375 "SHL $dst.lo,$cnt" %}
a61af66fc99e Initial load duke parents: diff changeset	9376 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
a61af66fc99e Initial load duke parents: diff changeset	9377 ins_encode( move_long_small_shift(dst,cnt) );
a61af66fc99e Initial load duke parents: diff changeset	9378 ins_pipe( ialu_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9379 %}
a61af66fc99e Initial load duke parents: diff changeset	9380
a61af66fc99e Initial load duke parents: diff changeset	9381 // Shift Left Long by 32-63
a61af66fc99e Initial load duke parents: diff changeset	9382 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9383 match(Set dst (LShiftL dst cnt));
a61af66fc99e Initial load duke parents: diff changeset	9384 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9385 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	9386 format %{ "MOV $dst.hi,$dst.lo\n"
a61af66fc99e Initial load duke parents: diff changeset	9387 "\tSHL $dst.hi,$cnt-32\n"
a61af66fc99e Initial load duke parents: diff changeset	9388 "\tXOR $dst.lo,$dst.lo" %}
a61af66fc99e Initial load duke parents: diff changeset	9389 opcode(0xC1, 0x4); /* C1 /4 ib */
a61af66fc99e Initial load duke parents: diff changeset	9390 ins_encode( move_long_big_shift_clr(dst,cnt) );
a61af66fc99e Initial load duke parents: diff changeset	9391 ins_pipe( ialu_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9392 %}
a61af66fc99e Initial load duke parents: diff changeset	9393
a61af66fc99e Initial load duke parents: diff changeset	9394 // Shift Left Long by variable
a61af66fc99e Initial load duke parents: diff changeset	9395 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9396 match(Set dst (LShiftL dst shift));
a61af66fc99e Initial load duke parents: diff changeset	9397 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9398 ins_cost(500+200);
a61af66fc99e Initial load duke parents: diff changeset	9399 size(17);
a61af66fc99e Initial load duke parents: diff changeset	9400 format %{ "TEST $shift,32\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9401 "JEQ,s small\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9402 "MOV $dst.hi,$dst.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9403 "XOR $dst.lo,$dst.lo\n"
a61af66fc99e Initial load duke parents: diff changeset	9404 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9405 "SHL $dst.lo,$shift" %}
a61af66fc99e Initial load duke parents: diff changeset	9406 ins_encode( shift_left_long( dst, shift ) );
a61af66fc99e Initial load duke parents: diff changeset	9407 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	9408 %}
a61af66fc99e Initial load duke parents: diff changeset	9409
a61af66fc99e Initial load duke parents: diff changeset	9410 // Shift Right Long by 1-31
a61af66fc99e Initial load duke parents: diff changeset	9411 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9412 match(Set dst (URShiftL dst cnt));
a61af66fc99e Initial load duke parents: diff changeset	9413 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9414 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	9415 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9416 "SHR $dst.hi,$cnt" %}
a61af66fc99e Initial load duke parents: diff changeset	9417 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
a61af66fc99e Initial load duke parents: diff changeset	9418 ins_encode( move_long_small_shift(dst,cnt) );
a61af66fc99e Initial load duke parents: diff changeset	9419 ins_pipe( ialu_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9420 %}
a61af66fc99e Initial load duke parents: diff changeset	9421
a61af66fc99e Initial load duke parents: diff changeset	9422 // Shift Right Long by 32-63
a61af66fc99e Initial load duke parents: diff changeset	9423 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9424 match(Set dst (URShiftL dst cnt));
a61af66fc99e Initial load duke parents: diff changeset	9425 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9426 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	9427 format %{ "MOV $dst.lo,$dst.hi\n"
a61af66fc99e Initial load duke parents: diff changeset	9428 "\tSHR $dst.lo,$cnt-32\n"
a61af66fc99e Initial load duke parents: diff changeset	9429 "\tXOR $dst.hi,$dst.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	9430 opcode(0xC1, 0x5); /* C1 /5 ib */
a61af66fc99e Initial load duke parents: diff changeset	9431 ins_encode( move_long_big_shift_clr(dst,cnt) );
a61af66fc99e Initial load duke parents: diff changeset	9432 ins_pipe( ialu_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9433 %}
a61af66fc99e Initial load duke parents: diff changeset	9434
a61af66fc99e Initial load duke parents: diff changeset	9435 // Shift Right Long by variable
a61af66fc99e Initial load duke parents: diff changeset	9436 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9437 match(Set dst (URShiftL dst shift));
a61af66fc99e Initial load duke parents: diff changeset	9438 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9439 ins_cost(600);
a61af66fc99e Initial load duke parents: diff changeset	9440 size(17);
a61af66fc99e Initial load duke parents: diff changeset	9441 format %{ "TEST $shift,32\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9442 "JEQ,s small\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9443 "MOV $dst.lo,$dst.hi\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9444 "XOR $dst.hi,$dst.hi\n"
a61af66fc99e Initial load duke parents: diff changeset	9445 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9446 "SHR $dst.hi,$shift" %}
a61af66fc99e Initial load duke parents: diff changeset	9447 ins_encode( shift_right_long( dst, shift ) );
a61af66fc99e Initial load duke parents: diff changeset	9448 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	9449 %}
a61af66fc99e Initial load duke parents: diff changeset	9450
a61af66fc99e Initial load duke parents: diff changeset	9451 // Shift Right Long by 1-31
a61af66fc99e Initial load duke parents: diff changeset	9452 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9453 match(Set dst (RShiftL dst cnt));
a61af66fc99e Initial load duke parents: diff changeset	9454 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9455 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	9456 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9457 "SAR $dst.hi,$cnt" %}
a61af66fc99e Initial load duke parents: diff changeset	9458 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
a61af66fc99e Initial load duke parents: diff changeset	9459 ins_encode( move_long_small_shift(dst,cnt) );
a61af66fc99e Initial load duke parents: diff changeset	9460 ins_pipe( ialu_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9461 %}
a61af66fc99e Initial load duke parents: diff changeset	9462
a61af66fc99e Initial load duke parents: diff changeset	9463 // Shift Right Long by 32-63
a61af66fc99e Initial load duke parents: diff changeset	9464 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9465 match(Set dst (RShiftL dst cnt));
a61af66fc99e Initial load duke parents: diff changeset	9466 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9467 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	9468 format %{ "MOV $dst.lo,$dst.hi\n"
a61af66fc99e Initial load duke parents: diff changeset	9469 "\tSAR $dst.lo,$cnt-32\n"
a61af66fc99e Initial load duke parents: diff changeset	9470 "\tSAR $dst.hi,31" %}
a61af66fc99e Initial load duke parents: diff changeset	9471 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load duke parents: diff changeset	9472 ins_encode( move_long_big_shift_sign(dst,cnt) );
a61af66fc99e Initial load duke parents: diff changeset	9473 ins_pipe( ialu_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	9474 %}
a61af66fc99e Initial load duke parents: diff changeset	9475
a61af66fc99e Initial load duke parents: diff changeset	9476 // Shift Right arithmetic Long by variable
a61af66fc99e Initial load duke parents: diff changeset	9477 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	9478 match(Set dst (RShiftL dst shift));
a61af66fc99e Initial load duke parents: diff changeset	9479 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9480 ins_cost(600);
a61af66fc99e Initial load duke parents: diff changeset	9481 size(18);
a61af66fc99e Initial load duke parents: diff changeset	9482 format %{ "TEST $shift,32\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9483 "JEQ,s small\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9484 "MOV $dst.lo,$dst.hi\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9485 "SAR $dst.hi,31\n"
a61af66fc99e Initial load duke parents: diff changeset	9486 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9487 "SAR $dst.hi,$shift" %}
a61af66fc99e Initial load duke parents: diff changeset	9488 ins_encode( shift_right_arith_long( dst, shift ) );
a61af66fc99e Initial load duke parents: diff changeset	9489 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	9490 %}
a61af66fc99e Initial load duke parents: diff changeset	9491
a61af66fc99e Initial load duke parents: diff changeset	9492
a61af66fc99e Initial load duke parents: diff changeset	9493 //----------Double Instructions------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	9494 // Double Math
a61af66fc99e Initial load duke parents: diff changeset	9495
a61af66fc99e Initial load duke parents: diff changeset	9496 // Compare & branch
a61af66fc99e Initial load duke parents: diff changeset	9497
a61af66fc99e Initial load duke parents: diff changeset	9498 // P6 version of float compare, sets condition codes in EFLAGS
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9499 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9500 predicate(VM_Version::supports_cmov() && UseSSE <=1);
a61af66fc99e Initial load duke parents: diff changeset	9501 match(Set cr (CmpD src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	9502 effect(KILL rax);
a61af66fc99e Initial load duke parents: diff changeset	9503 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	9504 format %{ "FLD $src1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9505 "FUCOMIP ST,$src2 // P6 instruction\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9506 "JNP exit\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9507 "MOV ah,1 // saw a NaN, set CF\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9508 "SAHF\n"
a61af66fc99e Initial load duke parents: diff changeset	9509 "exit:\tNOP // avoid branch to branch" %}
a61af66fc99e Initial load duke parents: diff changeset	9510 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9511 ins_encode( Push_Reg_DPR(src1),
0 a61af66fc99e Initial load duke parents: diff changeset	9512 OpcP, RegOpc(src2),
a61af66fc99e Initial load duke parents: diff changeset	9513 cmpF_P6_fixup );
a61af66fc99e Initial load duke parents: diff changeset	9514 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	9515 %}
a61af66fc99e Initial load duke parents: diff changeset	9516
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9517 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9518 predicate(VM_Version::supports_cmov() && UseSSE <=1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9519 match(Set cr (CmpD src1 src2));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9520 ins_cost(150);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9521 format %{ "FLD $src1\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9522 "FUCOMIP ST,$src2 // P6 instruction" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9523 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9524 ins_encode( Push_Reg_DPR(src1),
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9525 OpcP, RegOpc(src2));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9526 ins_pipe( pipe_slow );
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9527 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9528
0 a61af66fc99e Initial load duke parents: diff changeset	9529 // Compare & branch
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9530 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9531 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	9532 match(Set cr (CmpD src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	9533 effect(KILL rax);
a61af66fc99e Initial load duke parents: diff changeset	9534 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	9535 format %{ "FLD $src1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9536 "FCOMp $src2\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9537 "FNSTSW AX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9538 "TEST AX,0x400\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9539 "JZ,s flags\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9540 "MOV AH,1\t# unordered treat as LT\n"
a61af66fc99e Initial load duke parents: diff changeset	9541 "flags:\tSAHF" %}
a61af66fc99e Initial load duke parents: diff changeset	9542 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9543 ins_encode( Push_Reg_DPR(src1),
0 a61af66fc99e Initial load duke parents: diff changeset	9544 OpcP, RegOpc(src2),
a61af66fc99e Initial load duke parents: diff changeset	9545 fpu_flags);
a61af66fc99e Initial load duke parents: diff changeset	9546 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	9547 %}
a61af66fc99e Initial load duke parents: diff changeset	9548
a61af66fc99e Initial load duke parents: diff changeset	9549 // Compare vs zero into -1,0,1
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	9550 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9551 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	9552 match(Set dst (CmpD3 src1 zero));
a61af66fc99e Initial load duke parents: diff changeset	9553 effect(KILL cr, KILL rax);
a61af66fc99e Initial load duke parents: diff changeset	9554 ins_cost(280);
a61af66fc99e Initial load duke parents: diff changeset	9555 format %{ "FTSTD $dst,$src1" %}
a61af66fc99e Initial load duke parents: diff changeset	9556 opcode(0xE4, 0xD9);
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9557 ins_encode( Push_Reg_DPR(src1),
0 a61af66fc99e Initial load duke parents: diff changeset	9558 OpcS, OpcP, PopFPU,
a61af66fc99e Initial load duke parents: diff changeset	9559 CmpF_Result(dst));
a61af66fc99e Initial load duke parents: diff changeset	9560 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	9561 %}
a61af66fc99e Initial load duke parents: diff changeset	9562
a61af66fc99e Initial load duke parents: diff changeset	9563 // Compare into -1,0,1
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	9564 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9565 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	9566 match(Set dst (CmpD3 src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	9567 effect(KILL cr, KILL rax);
a61af66fc99e Initial load duke parents: diff changeset	9568 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	9569 format %{ "FCMPD $dst,$src1,$src2" %}
a61af66fc99e Initial load duke parents: diff changeset	9570 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9571 ins_encode( Push_Reg_DPR(src1),
0 a61af66fc99e Initial load duke parents: diff changeset	9572 OpcP, RegOpc(src2),
a61af66fc99e Initial load duke parents: diff changeset	9573 CmpF_Result(dst));
a61af66fc99e Initial load duke parents: diff changeset	9574 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	9575 %}
a61af66fc99e Initial load duke parents: diff changeset	9576
a61af66fc99e Initial load duke parents: diff changeset	9577 // float compare and set condition codes in EFLAGS by XMM regs
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9578 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9579 predicate(UseSSE>=2);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9580 match(Set cr (CmpD src1 src2));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9581 ins_cost(145);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9582 format %{ "UCOMISD $src1,$src2\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9583 "JNP,s exit\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9584 "PUSHF\t# saw NaN, set CF\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9585 "AND [rsp], #0xffffff2b\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9586 "POPF\n"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9587 "exit:" %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9588 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9589 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9590 emit_cmpfp_fixup(_masm);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9591 %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9592 ins_pipe( pipe_slow );
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9593 %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9594
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9595 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9596 predicate(UseSSE>=2);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9597 match(Set cr (CmpD src1 src2));
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9598 ins_cost(100);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9599 format %{ "UCOMISD $src1,$src2" %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9600 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9601 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9602 %}
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9603 ins_pipe( pipe_slow );
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9604 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9605
0 a61af66fc99e Initial load duke parents: diff changeset	9606 // float compare and set condition codes in EFLAGS by XMM regs
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9607 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9608 predicate(UseSSE>=2);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9609 match(Set cr (CmpD src1 (LoadD src2)));
0 a61af66fc99e Initial load duke parents: diff changeset	9610 ins_cost(145);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9611 format %{ "UCOMISD $src1,$src2\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9612 "JNP,s exit\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9613 "PUSHF\t# saw NaN, set CF\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9614 "AND [rsp], #0xffffff2b\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9615 "POPF\n"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9616 "exit:" %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9617 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9618 __ ucomisd($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9619 emit_cmpfp_fixup(_masm);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9620 %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9621 ins_pipe( pipe_slow );
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9622 %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9623
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9624 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9625 predicate(UseSSE>=2);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9626 match(Set cr (CmpD src1 (LoadD src2)));
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9627 ins_cost(100);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9628 format %{ "UCOMISD $src1,$src2" %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9629 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9630 __ ucomisd($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9631 %}
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9632 ins_pipe( pipe_slow );
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9633 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	9634
0 a61af66fc99e Initial load duke parents: diff changeset	9635 // Compare into -1,0,1 in XMM
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9636 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9637 predicate(UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	9638 match(Set dst (CmpD3 src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	9639 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9640 ins_cost(255);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9641 format %{ "UCOMISD $src1, $src2\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9642 "MOV $dst, #-1\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9643 "JP,s done\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9644 "JB,s done\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9645 "SETNE $dst\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9646 "MOVZB $dst, $dst\n"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9647 "done:" %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9648 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9649 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9650 emit_cmpfp3(_masm, $dst$$Register);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9651 %}
0 a61af66fc99e Initial load duke parents: diff changeset	9652 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	9653 %}
a61af66fc99e Initial load duke parents: diff changeset	9654
a61af66fc99e Initial load duke parents: diff changeset	9655 // Compare into -1,0,1 in XMM and memory
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9656 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9657 predicate(UseSSE>=2);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9658 match(Set dst (CmpD3 src1 (LoadD src2)));
0 a61af66fc99e Initial load duke parents: diff changeset	9659 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	9660 ins_cost(275);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9661 format %{ "UCOMISD $src1, $src2\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9662 "MOV $dst, #-1\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9663 "JP,s done\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9664 "JB,s done\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9665 "SETNE $dst\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9666 "MOVZB $dst, $dst\n"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9667 "done:" %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9668 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9669 __ ucomisd($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9670 emit_cmpfp3(_masm, $dst$$Register);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	9671 %}
0 a61af66fc99e Initial load duke parents: diff changeset	9672 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	9673 %}
a61af66fc99e Initial load duke parents: diff changeset	9674
a61af66fc99e Initial load duke parents: diff changeset	9675
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9676 instruct subDPR_reg(regDPR dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9677 predicate (UseSSE <=1);
a61af66fc99e Initial load duke parents: diff changeset	9678 match(Set dst (SubD dst src));
a61af66fc99e Initial load duke parents: diff changeset	9679
a61af66fc99e Initial load duke parents: diff changeset	9680 format %{ "FLD $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9681 "DSUBp $dst,ST" %}
a61af66fc99e Initial load duke parents: diff changeset	9682 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
a61af66fc99e Initial load duke parents: diff changeset	9683 ins_cost(150);
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9684 ins_encode( Push_Reg_DPR(src),
0 a61af66fc99e Initial load duke parents: diff changeset	9685 OpcP, RegOpc(dst) );
a61af66fc99e Initial load duke parents: diff changeset	9686 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	9687 %}
a61af66fc99e Initial load duke parents: diff changeset	9688
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9689 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9690 predicate (UseSSE <=1);
a61af66fc99e Initial load duke parents: diff changeset	9691 match(Set dst (RoundDouble (SubD src1 src2)));
a61af66fc99e Initial load duke parents: diff changeset	9692 ins_cost(250);
a61af66fc99e Initial load duke parents: diff changeset	9693
a61af66fc99e Initial load duke parents: diff changeset	9694 format %{ "FLD $src2\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9695 "DSUB ST,$src1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9696 "FSTP_D $dst\t# D-round" %}
a61af66fc99e Initial load duke parents: diff changeset	9697 opcode(0xD8, 0x5);
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9698 ins_encode( Push_Reg_DPR(src2),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9699 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	9700 ins_pipe( fpu_mem_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	9701 %}
a61af66fc99e Initial load duke parents: diff changeset	9702
a61af66fc99e Initial load duke parents: diff changeset	9703
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9704 instruct subDPR_reg_mem(regDPR dst, memory src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9705 predicate (UseSSE <=1);
a61af66fc99e Initial load duke parents: diff changeset	9706 match(Set dst (SubD dst (LoadD src)));
a61af66fc99e Initial load duke parents: diff changeset	9707 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	9708
a61af66fc99e Initial load duke parents: diff changeset	9709 format %{ "FLD $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9710 "DSUBp $dst,ST" %}
a61af66fc99e Initial load duke parents: diff changeset	9711 opcode(0xDE, 0x5, 0xDD); /* DE C0+i / / LoadD DD /0 */
a61af66fc99e Initial load duke parents: diff changeset	9712 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
a61af66fc99e Initial load duke parents: diff changeset	9713 OpcP, RegOpc(dst) );
a61af66fc99e Initial load duke parents: diff changeset	9714 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	9715 %}
a61af66fc99e Initial load duke parents: diff changeset	9716
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9717 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9718 predicate (UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	9719 match(Set dst (AbsD src));
a61af66fc99e Initial load duke parents: diff changeset	9720 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	9721 format %{ "FABS" %}
a61af66fc99e Initial load duke parents: diff changeset	9722 opcode(0xE1, 0xD9);
a61af66fc99e Initial load duke parents: diff changeset	9723 ins_encode( OpcS, OpcP );
a61af66fc99e Initial load duke parents: diff changeset	9724 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	9725 %}
a61af66fc99e Initial load duke parents: diff changeset	9726
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9727 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9728 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	9729 match(Set dst (NegD src));
a61af66fc99e Initial load duke parents: diff changeset	9730 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	9731 format %{ "FCHS" %}
a61af66fc99e Initial load duke parents: diff changeset	9732 opcode(0xE0, 0xD9);
a61af66fc99e Initial load duke parents: diff changeset	9733 ins_encode( OpcS, OpcP );
a61af66fc99e Initial load duke parents: diff changeset	9734 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	9735 %}
a61af66fc99e Initial load duke parents: diff changeset	9736
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9737 instruct addDPR_reg(regDPR dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9738 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	9739 match(Set dst (AddD dst src));
a61af66fc99e Initial load duke parents: diff changeset	9740 format %{ "FLD $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9741 "DADD $dst,ST" %}
a61af66fc99e Initial load duke parents: diff changeset	9742 size(4);
a61af66fc99e Initial load duke parents: diff changeset	9743 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	9744 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9745 ins_encode( Push_Reg_DPR(src),
0 a61af66fc99e Initial load duke parents: diff changeset	9746 OpcP, RegOpc(dst) );
a61af66fc99e Initial load duke parents: diff changeset	9747 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	9748 %}
a61af66fc99e Initial load duke parents: diff changeset	9749
a61af66fc99e Initial load duke parents: diff changeset	9750
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9751 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9752 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	9753 match(Set dst (RoundDouble (AddD src1 src2)));
a61af66fc99e Initial load duke parents: diff changeset	9754 ins_cost(250);
a61af66fc99e Initial load duke parents: diff changeset	9755
a61af66fc99e Initial load duke parents: diff changeset	9756 format %{ "FLD $src2\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9757 "DADD ST,$src1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9758 "FSTP_D $dst\t# D-round" %}
a61af66fc99e Initial load duke parents: diff changeset	9759 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9760 ins_encode( Push_Reg_DPR(src2),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9761 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	9762 ins_pipe( fpu_mem_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	9763 %}
a61af66fc99e Initial load duke parents: diff changeset	9764
a61af66fc99e Initial load duke parents: diff changeset	9765
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9766 instruct addDPR_reg_mem(regDPR dst, memory src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9767 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	9768 match(Set dst (AddD dst (LoadD src)));
a61af66fc99e Initial load duke parents: diff changeset	9769 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	9770
a61af66fc99e Initial load duke parents: diff changeset	9771 format %{ "FLD $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9772 "DADDp $dst,ST" %}
a61af66fc99e Initial load duke parents: diff changeset	9773 opcode(0xDE, 0x0, 0xDD); /* DE C0+i / / LoadD DD /0 */
a61af66fc99e Initial load duke parents: diff changeset	9774 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
a61af66fc99e Initial load duke parents: diff changeset	9775 OpcP, RegOpc(dst) );
a61af66fc99e Initial load duke parents: diff changeset	9776 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	9777 %}
a61af66fc99e Initial load duke parents: diff changeset	9778
a61af66fc99e Initial load duke parents: diff changeset	9779 // add-to-memory
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9780 instruct addDPR_mem_reg(memory dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9781 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	9782 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
a61af66fc99e Initial load duke parents: diff changeset	9783 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	9784
a61af66fc99e Initial load duke parents: diff changeset	9785 format %{ "FLD_D $dst\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9786 "DADD ST,$src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9787 "FST_D $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	9788 opcode(0xDD, 0x0);
a61af66fc99e Initial load duke parents: diff changeset	9789 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
a61af66fc99e Initial load duke parents: diff changeset	9790 Opcode(0xD8), RegOpc(src),
a61af66fc99e Initial load duke parents: diff changeset	9791 set_instruction_start,
a61af66fc99e Initial load duke parents: diff changeset	9792 Opcode(0xDD), RMopc_Mem(0x03,dst) );
a61af66fc99e Initial load duke parents: diff changeset	9793 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	9794 %}
a61af66fc99e Initial load duke parents: diff changeset	9795
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9796 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9797 predicate(UseSSE<=1);
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9798 match(Set dst (AddD dst con));
0 a61af66fc99e Initial load duke parents: diff changeset	9799 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	9800 format %{ "FLD1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9801 "DADDp $dst,ST" %}
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9802 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9803 __ fld1();
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9804 __ faddp($dst$$reg);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9805 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9806 ins_pipe(fpu_reg);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9807 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9808
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9809 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9810 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9811 match(Set dst (AddD dst con));
0 a61af66fc99e Initial load duke parents: diff changeset	9812 ins_cost(200);
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9813 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
0 a61af66fc99e Initial load duke parents: diff changeset	9814 "DADDp $dst,ST" %}
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9815 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9816 __ fld_d($constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9817 __ faddp($dst$$reg);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9818 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9819 ins_pipe(fpu_reg_mem);
0 a61af66fc99e Initial load duke parents: diff changeset	9820 %}
a61af66fc99e Initial load duke parents: diff changeset	9821
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9822 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9823 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
a61af66fc99e Initial load duke parents: diff changeset	9824 match(Set dst (RoundDouble (AddD src con)));
a61af66fc99e Initial load duke parents: diff changeset	9825 ins_cost(200);
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9826 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
0 a61af66fc99e Initial load duke parents: diff changeset	9827 "DADD ST,$src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9828 "FSTP_D $dst\t# D-round" %}
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9829 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9830 __ fld_d($constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9831 __ fadd($src$$reg);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9832 __ fstp_d(Address(rsp, $dst$$disp));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9833 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9834 ins_pipe(fpu_mem_reg_con);
0 a61af66fc99e Initial load duke parents: diff changeset	9835 %}
a61af66fc99e Initial load duke parents: diff changeset	9836
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9837 instruct mulDPR_reg(regDPR dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9838 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	9839 match(Set dst (MulD dst src));
a61af66fc99e Initial load duke parents: diff changeset	9840 format %{ "FLD $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9841 "DMULp $dst,ST" %}
a61af66fc99e Initial load duke parents: diff changeset	9842 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
a61af66fc99e Initial load duke parents: diff changeset	9843 ins_cost(150);
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9844 ins_encode( Push_Reg_DPR(src),
0 a61af66fc99e Initial load duke parents: diff changeset	9845 OpcP, RegOpc(dst) );
a61af66fc99e Initial load duke parents: diff changeset	9846 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	9847 %}
a61af66fc99e Initial load duke parents: diff changeset	9848
a61af66fc99e Initial load duke parents: diff changeset	9849 // Strict FP instruction biases argument before multiply then
a61af66fc99e Initial load duke parents: diff changeset	9850 // biases result to avoid double rounding of subnormals.
a61af66fc99e Initial load duke parents: diff changeset	9851 //
a61af66fc99e Initial load duke parents: diff changeset	9852 // scale arg1 by multiplying arg1 by 2^(-15360)
a61af66fc99e Initial load duke parents: diff changeset	9853 // load arg2
a61af66fc99e Initial load duke parents: diff changeset	9854 // multiply scaled arg1 by arg2
a61af66fc99e Initial load duke parents: diff changeset	9855 // rescale product by 2^(15360)
a61af66fc99e Initial load duke parents: diff changeset	9856 //
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9857 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9858 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
a61af66fc99e Initial load duke parents: diff changeset	9859 match(Set dst (MulD dst src));
a61af66fc99e Initial load duke parents: diff changeset	9860 ins_cost(1); // Select this instruction for all strict FP double multiplies
a61af66fc99e Initial load duke parents: diff changeset	9861
a61af66fc99e Initial load duke parents: diff changeset	9862 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9863 "DMULp $dst,ST\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9864 "FLD $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9865 "DMULp $dst,ST\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9866 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9867 "DMULp $dst,ST\n\t" %}
a61af66fc99e Initial load duke parents: diff changeset	9868 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
a61af66fc99e Initial load duke parents: diff changeset	9869 ins_encode( strictfp_bias1(dst),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9870 Push_Reg_DPR(src),
0 a61af66fc99e Initial load duke parents: diff changeset	9871 OpcP, RegOpc(dst),
a61af66fc99e Initial load duke parents: diff changeset	9872 strictfp_bias2(dst) );
a61af66fc99e Initial load duke parents: diff changeset	9873 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	9874 %}
a61af66fc99e Initial load duke parents: diff changeset	9875
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9876 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9877 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9878 match(Set dst (MulD dst con));
0 a61af66fc99e Initial load duke parents: diff changeset	9879 ins_cost(200);
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9880 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
0 a61af66fc99e Initial load duke parents: diff changeset	9881 "DMULp $dst,ST" %}
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9882 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9883 __ fld_d($constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9884 __ fmulp($dst$$reg);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9885 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	9886 ins_pipe(fpu_reg_mem);
0 a61af66fc99e Initial load duke parents: diff changeset	9887 %}
a61af66fc99e Initial load duke parents: diff changeset	9888
a61af66fc99e Initial load duke parents: diff changeset	9889
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9890 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9891 predicate( UseSSE<=1 );
a61af66fc99e Initial load duke parents: diff changeset	9892 match(Set dst (MulD dst (LoadD src)));
a61af66fc99e Initial load duke parents: diff changeset	9893 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	9894 format %{ "FLD_D $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9895 "DMULp $dst,ST" %}
a61af66fc99e Initial load duke parents: diff changeset	9896 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1/ / LoadD DD /0 */
a61af66fc99e Initial load duke parents: diff changeset	9897 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
a61af66fc99e Initial load duke parents: diff changeset	9898 OpcP, RegOpc(dst) );
a61af66fc99e Initial load duke parents: diff changeset	9899 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	9900 %}
a61af66fc99e Initial load duke parents: diff changeset	9901
a61af66fc99e Initial load duke parents: diff changeset	9902 //
a61af66fc99e Initial load duke parents: diff changeset	9903 // Cisc-alternate to reg-reg multiply
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9904 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9905 predicate( UseSSE<=1 );
a61af66fc99e Initial load duke parents: diff changeset	9906 match(Set dst (MulD src (LoadD mem)));
a61af66fc99e Initial load duke parents: diff changeset	9907 ins_cost(250);
a61af66fc99e Initial load duke parents: diff changeset	9908 format %{ "FLD_D $mem\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9909 "DMUL ST,$src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9910 "FSTP_D $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	9911 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i / / LoadD D9 /0 */
a61af66fc99e Initial load duke parents: diff changeset	9912 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9913 OpcReg_FPR(src),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9914 Pop_Reg_DPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	9915 ins_pipe( fpu_reg_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	9916 %}
a61af66fc99e Initial load duke parents: diff changeset	9917
a61af66fc99e Initial load duke parents: diff changeset	9918
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9919 // MACRO3 -- addDPR a mulDPR
0 a61af66fc99e Initial load duke parents: diff changeset	9920 // This instruction is a '2-address' instruction in that the result goes
a61af66fc99e Initial load duke parents: diff changeset	9921 // back to src2. This eliminates a move from the macro; possibly the
a61af66fc99e Initial load duke parents: diff changeset	9922 // register allocator will have to add it back (and maybe not).
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9923 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9924 predicate( UseSSE<=1 );
a61af66fc99e Initial load duke parents: diff changeset	9925 match(Set src2 (AddD (MulD src0 src1) src2));
a61af66fc99e Initial load duke parents: diff changeset	9926 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9927 "DMUL ST,$src1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9928 "DADDp $src2,ST" %}
a61af66fc99e Initial load duke parents: diff changeset	9929 ins_cost(250);
a61af66fc99e Initial load duke parents: diff changeset	9930 opcode(0xDD); /* LoadD DD /0 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9931 ins_encode( Push_Reg_FPR(src0),
0 a61af66fc99e Initial load duke parents: diff changeset	9932 FMul_ST_reg(src1),
a61af66fc99e Initial load duke parents: diff changeset	9933 FAddP_reg_ST(src2) );
a61af66fc99e Initial load duke parents: diff changeset	9934 ins_pipe( fpu_reg_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	9935 %}
a61af66fc99e Initial load duke parents: diff changeset	9936
a61af66fc99e Initial load duke parents: diff changeset	9937
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9938 // MACRO3 -- subDPR a mulDPR
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9939 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9940 predicate( UseSSE<=1 );
a61af66fc99e Initial load duke parents: diff changeset	9941 match(Set src2 (SubD (MulD src0 src1) src2));
a61af66fc99e Initial load duke parents: diff changeset	9942 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9943 "DMUL ST,$src1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9944 "DSUBRp $src2,ST" %}
a61af66fc99e Initial load duke parents: diff changeset	9945 ins_cost(250);
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9946 ins_encode( Push_Reg_FPR(src0),
0 a61af66fc99e Initial load duke parents: diff changeset	9947 FMul_ST_reg(src1),
a61af66fc99e Initial load duke parents: diff changeset	9948 Opcode(0xDE), Opc_plus(0xE0,src2));
a61af66fc99e Initial load duke parents: diff changeset	9949 ins_pipe( fpu_reg_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	9950 %}
a61af66fc99e Initial load duke parents: diff changeset	9951
a61af66fc99e Initial load duke parents: diff changeset	9952
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9953 instruct divDPR_reg(regDPR dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9954 predicate( UseSSE<=1 );
a61af66fc99e Initial load duke parents: diff changeset	9955 match(Set dst (DivD dst src));
a61af66fc99e Initial load duke parents: diff changeset	9956
a61af66fc99e Initial load duke parents: diff changeset	9957 format %{ "FLD $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9958 "FDIVp $dst,ST" %}
a61af66fc99e Initial load duke parents: diff changeset	9959 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
a61af66fc99e Initial load duke parents: diff changeset	9960 ins_cost(150);
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9961 ins_encode( Push_Reg_DPR(src),
0 a61af66fc99e Initial load duke parents: diff changeset	9962 OpcP, RegOpc(dst) );
a61af66fc99e Initial load duke parents: diff changeset	9963 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	9964 %}
a61af66fc99e Initial load duke parents: diff changeset	9965
a61af66fc99e Initial load duke parents: diff changeset	9966 // Strict FP instruction biases argument before division then
a61af66fc99e Initial load duke parents: diff changeset	9967 // biases result, to avoid double rounding of subnormals.
a61af66fc99e Initial load duke parents: diff changeset	9968 //
a61af66fc99e Initial load duke parents: diff changeset	9969 // scale dividend by multiplying dividend by 2^(-15360)
a61af66fc99e Initial load duke parents: diff changeset	9970 // load divisor
a61af66fc99e Initial load duke parents: diff changeset	9971 // divide scaled dividend by divisor
a61af66fc99e Initial load duke parents: diff changeset	9972 // rescale quotient by 2^(15360)
a61af66fc99e Initial load duke parents: diff changeset	9973 //
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9974 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9975 predicate (UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	9976 match(Set dst (DivD dst src));
a61af66fc99e Initial load duke parents: diff changeset	9977 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
a61af66fc99e Initial load duke parents: diff changeset	9978 ins_cost(01);
a61af66fc99e Initial load duke parents: diff changeset	9979
a61af66fc99e Initial load duke parents: diff changeset	9980 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9981 "DMULp $dst,ST\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9982 "FLD $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9983 "FDIVp $dst,ST\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9984 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9985 "DMULp $dst,ST\n\t" %}
a61af66fc99e Initial load duke parents: diff changeset	9986 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
a61af66fc99e Initial load duke parents: diff changeset	9987 ins_encode( strictfp_bias1(dst),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9988 Push_Reg_DPR(src),
0 a61af66fc99e Initial load duke parents: diff changeset	9989 OpcP, RegOpc(dst),
a61af66fc99e Initial load duke parents: diff changeset	9990 strictfp_bias2(dst) );
a61af66fc99e Initial load duke parents: diff changeset	9991 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	9992 %}
a61af66fc99e Initial load duke parents: diff changeset	9993
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	9994 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	9995 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
a61af66fc99e Initial load duke parents: diff changeset	9996 match(Set dst (RoundDouble (DivD src1 src2)));
a61af66fc99e Initial load duke parents: diff changeset	9997
a61af66fc99e Initial load duke parents: diff changeset	9998 format %{ "FLD $src1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	9999 "FDIV ST,$src2\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10000 "FSTP_D $dst\t# D-round" %}
a61af66fc99e Initial load duke parents: diff changeset	10001 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10002 ins_encode( Push_Reg_DPR(src1),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10003 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	10004 ins_pipe( fpu_mem_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	10005 %}
a61af66fc99e Initial load duke parents: diff changeset	10006
a61af66fc99e Initial load duke parents: diff changeset	10007
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10008 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10009 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	10010 match(Set dst (ModD dst src));
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10011 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
0 a61af66fc99e Initial load duke parents: diff changeset	10012
a61af66fc99e Initial load duke parents: diff changeset	10013 format %{ "DMOD $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	10014 ins_cost(250);
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10015 ins_encode(Push_Reg_Mod_DPR(dst, src),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10016 emitModDPR(),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10017 Push_Result_Mod_DPR(src),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10018 Pop_Reg_DPR(dst));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10019 ins_pipe( pipe_slow );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10020 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10021
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10022 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10023 predicate(UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	10024 match(Set dst (ModD src0 src1));
a61af66fc99e Initial load duke parents: diff changeset	10025 effect(KILL rax, KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	10026
a61af66fc99e Initial load duke parents: diff changeset	10027 format %{ "SUB ESP,8\t # DMOD\n"
a61af66fc99e Initial load duke parents: diff changeset	10028 "\tMOVSD [ESP+0],$src1\n"
a61af66fc99e Initial load duke parents: diff changeset	10029 "\tFLD_D [ESP+0]\n"
a61af66fc99e Initial load duke parents: diff changeset	10030 "\tMOVSD [ESP+0],$src0\n"
a61af66fc99e Initial load duke parents: diff changeset	10031 "\tFLD_D [ESP+0]\n"
a61af66fc99e Initial load duke parents: diff changeset	10032 "loop:\tFPREM\n"
a61af66fc99e Initial load duke parents: diff changeset	10033 "\tFWAIT\n"
a61af66fc99e Initial load duke parents: diff changeset	10034 "\tFNSTSW AX\n"
a61af66fc99e Initial load duke parents: diff changeset	10035 "\tSAHF\n"
a61af66fc99e Initial load duke parents: diff changeset	10036 "\tJP loop\n"
a61af66fc99e Initial load duke parents: diff changeset	10037 "\tFSTP_D [ESP+0]\n"
a61af66fc99e Initial load duke parents: diff changeset	10038 "\tMOVSD $dst,[ESP+0]\n"
a61af66fc99e Initial load duke parents: diff changeset	10039 "\tADD ESP,8\n"
a61af66fc99e Initial load duke parents: diff changeset	10040 "\tFSTP ST0\t # Restore FPU Stack"
a61af66fc99e Initial load duke parents: diff changeset	10041 %}
a61af66fc99e Initial load duke parents: diff changeset	10042 ins_cost(250);
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10043 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10044 ins_pipe( pipe_slow );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10045 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10046
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10047 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10048 predicate (UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	10049 match(Set dst (SinD src));
a61af66fc99e Initial load duke parents: diff changeset	10050 ins_cost(1800);
a61af66fc99e Initial load duke parents: diff changeset	10051 format %{ "DSIN $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	10052 opcode(0xD9, 0xFE);
a61af66fc99e Initial load duke parents: diff changeset	10053 ins_encode( OpcP, OpcS );
a61af66fc99e Initial load duke parents: diff changeset	10054 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10055 %}
a61af66fc99e Initial load duke parents: diff changeset	10056
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10057 instruct sinD_reg(regD dst, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10058 predicate (UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	10059 match(Set dst (SinD dst));
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10060 effect(KILL cr); // Push_{Src\|Result}D() uses "{SUB\|ADD} ESP,8"
0 a61af66fc99e Initial load duke parents: diff changeset	10061 ins_cost(1800);
a61af66fc99e Initial load duke parents: diff changeset	10062 format %{ "DSIN $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	10063 opcode(0xD9, 0xFE);
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10064 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10065 ins_pipe( pipe_slow );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10066 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10067
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10068 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10069 predicate (UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	10070 match(Set dst (CosD src));
a61af66fc99e Initial load duke parents: diff changeset	10071 ins_cost(1800);
a61af66fc99e Initial load duke parents: diff changeset	10072 format %{ "DCOS $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	10073 opcode(0xD9, 0xFF);
a61af66fc99e Initial load duke parents: diff changeset	10074 ins_encode( OpcP, OpcS );
a61af66fc99e Initial load duke parents: diff changeset	10075 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10076 %}
a61af66fc99e Initial load duke parents: diff changeset	10077
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10078 instruct cosD_reg(regD dst, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10079 predicate (UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	10080 match(Set dst (CosD dst));
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10081 effect(KILL cr); // Push_{Src\|Result}D() uses "{SUB\|ADD} ESP,8"
0 a61af66fc99e Initial load duke parents: diff changeset	10082 ins_cost(1800);
a61af66fc99e Initial load duke parents: diff changeset	10083 format %{ "DCOS $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	10084 opcode(0xD9, 0xFF);
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10085 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10086 ins_pipe( pipe_slow );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10087 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10088
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10089 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10090 predicate (UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	10091 match(Set dst(TanD src));
a61af66fc99e Initial load duke parents: diff changeset	10092 format %{ "DTAN $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	10093 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
a61af66fc99e Initial load duke parents: diff changeset	10094 Opcode(0xDD), Opcode(0xD8)); // fstp st
a61af66fc99e Initial load duke parents: diff changeset	10095 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10096 %}
a61af66fc99e Initial load duke parents: diff changeset	10097
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10098 instruct tanD_reg(regD dst, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10099 predicate (UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	10100 match(Set dst(TanD dst));
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10101 effect(KILL cr); // Push_{Src\|Result}D() uses "{SUB\|ADD} ESP,8"
0 a61af66fc99e Initial load duke parents: diff changeset	10102 format %{ "DTAN $dst" %}
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10103 ins_encode( Push_SrcD(dst),
0 a61af66fc99e Initial load duke parents: diff changeset	10104 Opcode(0xD9), Opcode(0xF2), // fptan
a61af66fc99e Initial load duke parents: diff changeset	10105 Opcode(0xDD), Opcode(0xD8), // fstp st
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10106 Push_ResultD(dst) );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10107 ins_pipe( pipe_slow );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10108 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10109
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10110 instruct atanDPR_reg(regDPR dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10111 predicate (UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	10112 match(Set dst(AtanD dst src));
a61af66fc99e Initial load duke parents: diff changeset	10113 format %{ "DATA $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	10114 opcode(0xD9, 0xF3);
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10115 ins_encode( Push_Reg_DPR(src),
0 a61af66fc99e Initial load duke parents: diff changeset	10116 OpcP, OpcS, RegOpc(dst) );
a61af66fc99e Initial load duke parents: diff changeset	10117 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10118 %}
a61af66fc99e Initial load duke parents: diff changeset	10119
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10120 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10121 predicate (UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	10122 match(Set dst(AtanD dst src));
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10123 effect(KILL cr); // Push_{Src\|Result}D() uses "{SUB\|ADD} ESP,8"
0 a61af66fc99e Initial load duke parents: diff changeset	10124 format %{ "DATA $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	10125 opcode(0xD9, 0xF3);
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10126 ins_encode( Push_SrcD(src),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10127 OpcP, OpcS, Push_ResultD(dst) );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10128 ins_pipe( pipe_slow );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10129 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10130
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10131 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10132 predicate (UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	10133 match(Set dst (SqrtD src));
a61af66fc99e Initial load duke parents: diff changeset	10134 format %{ "DSQRT $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	10135 opcode(0xFA, 0xD9);
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10136 ins_encode( Push_Reg_DPR(src),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10137 OpcS, OpcP, Pop_Reg_DPR(dst) );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10138 ins_pipe( pipe_slow );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10139 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10140
6084 6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10141 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10142 predicate (UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	10143 match(Set Y (PowD X Y)); // Raise X to the Yth power
6084 6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10144 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10145 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10146 ins_encode %{
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10147 __ subptr(rsp, 8);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10148 __ fld_s($X$$reg - 1);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10149 __ fast_pow();
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10150 __ addptr(rsp, 8);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10151 %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10152 ins_pipe( pipe_slow );
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10153 %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10154
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10155 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10156 predicate (UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	10157 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
6084 6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10158 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10159 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10160 ins_encode %{
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10161 __ subptr(rsp, 8);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10162 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10163 __ fld_d(Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10164 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10165 __ fld_d(Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10166 __ fast_pow();
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10167 __ fstp_d(Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10168 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10169 __ addptr(rsp, 8);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10170 %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10171 ins_pipe( pipe_slow );
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10172 %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10173
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10174
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10175 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10176 predicate (UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	10177 match(Set dpr1 (ExpD dpr1));
6084 6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10178 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10179 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10180 ins_encode %{
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10181 __ fast_exp();
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10182 %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10183 ins_pipe( pipe_slow );
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10184 %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10185
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10186 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10187 predicate (UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	10188 match(Set dst (ExpD src));
6084 6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10189 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10190 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10191 ins_encode %{
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10192 __ subptr(rsp, 8);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10193 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10194 __ fld_d(Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10195 __ fast_exp();
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10196 __ fstp_d(Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10197 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10198 __ addptr(rsp, 8);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10199 %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10200 ins_pipe( pipe_slow );
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86 roland parents: 5934 diff changeset	10201 %}
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10202
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10203 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10204 predicate (UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	10205 // The source Double operand on FPU stack
a61af66fc99e Initial load duke parents: diff changeset	10206 match(Set dst (Log10D src));
a61af66fc99e Initial load duke parents: diff changeset	10207 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
a61af66fc99e Initial load duke parents: diff changeset	10208 // fxch ; swap ST(0) with ST(1)
a61af66fc99e Initial load duke parents: diff changeset	10209 // fyl2x ; compute log_10(2) * log_2(x)
a61af66fc99e Initial load duke parents: diff changeset	10210 format %{ "FLDLG2 \t\t\t#Log10\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10211 "FXCH \n\t"
a61af66fc99e Initial load duke parents: diff changeset	10212 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
a61af66fc99e Initial load duke parents: diff changeset	10213 %}
a61af66fc99e Initial load duke parents: diff changeset	10214 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
a61af66fc99e Initial load duke parents: diff changeset	10215 Opcode(0xD9), Opcode(0xC9), // fxch
a61af66fc99e Initial load duke parents: diff changeset	10216 Opcode(0xD9), Opcode(0xF1)); // fyl2x
a61af66fc99e Initial load duke parents: diff changeset	10217
a61af66fc99e Initial load duke parents: diff changeset	10218 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10219 %}
a61af66fc99e Initial load duke parents: diff changeset	10220
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10221 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10222 predicate (UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	10223 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	10224 match(Set dst (Log10D src));
a61af66fc99e Initial load duke parents: diff changeset	10225 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
a61af66fc99e Initial load duke parents: diff changeset	10226 // fyl2x ; compute log_10(2) * log_2(x)
a61af66fc99e Initial load duke parents: diff changeset	10227 format %{ "FLDLG2 \t\t\t#Log10\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10228 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
a61af66fc99e Initial load duke parents: diff changeset	10229 %}
a61af66fc99e Initial load duke parents: diff changeset	10230 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10231 Push_SrcD(src),
0 a61af66fc99e Initial load duke parents: diff changeset	10232 Opcode(0xD9), Opcode(0xF1), // fyl2x
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10233 Push_ResultD(dst));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10234
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10235 ins_pipe( pipe_slow );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10236 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10237
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10238 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10239 predicate (UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	10240 // The source Double operand on FPU stack
a61af66fc99e Initial load duke parents: diff changeset	10241 match(Set dst (LogD src));
a61af66fc99e Initial load duke parents: diff changeset	10242 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
a61af66fc99e Initial load duke parents: diff changeset	10243 // fxch ; swap ST(0) with ST(1)
a61af66fc99e Initial load duke parents: diff changeset	10244 // fyl2x ; compute log_e(2) * log_2(x)
a61af66fc99e Initial load duke parents: diff changeset	10245 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10246 "FXCH \n\t"
a61af66fc99e Initial load duke parents: diff changeset	10247 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
a61af66fc99e Initial load duke parents: diff changeset	10248 %}
a61af66fc99e Initial load duke parents: diff changeset	10249 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
a61af66fc99e Initial load duke parents: diff changeset	10250 Opcode(0xD9), Opcode(0xC9), // fxch
a61af66fc99e Initial load duke parents: diff changeset	10251 Opcode(0xD9), Opcode(0xF1)); // fyl2x
a61af66fc99e Initial load duke parents: diff changeset	10252
a61af66fc99e Initial load duke parents: diff changeset	10253 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10254 %}
a61af66fc99e Initial load duke parents: diff changeset	10255
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10256 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10257 predicate (UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	10258 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	10259 // The source and result Double operands in XMM registers
a61af66fc99e Initial load duke parents: diff changeset	10260 match(Set dst (LogD src));
a61af66fc99e Initial load duke parents: diff changeset	10261 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
a61af66fc99e Initial load duke parents: diff changeset	10262 // fyl2x ; compute log_e(2) * log_2(x)
a61af66fc99e Initial load duke parents: diff changeset	10263 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10264 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
a61af66fc99e Initial load duke parents: diff changeset	10265 %}
a61af66fc99e Initial load duke parents: diff changeset	10266 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10267 Push_SrcD(src),
0 a61af66fc99e Initial load duke parents: diff changeset	10268 Opcode(0xD9), Opcode(0xF1), // fyl2x
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10269 Push_ResultD(dst));
0 a61af66fc99e Initial load duke parents: diff changeset	10270 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10271 %}
a61af66fc99e Initial load duke parents: diff changeset	10272
a61af66fc99e Initial load duke parents: diff changeset	10273 //-------------Float Instructions-------------------------------
a61af66fc99e Initial load duke parents: diff changeset	10274 // Float Math
a61af66fc99e Initial load duke parents: diff changeset	10275
a61af66fc99e Initial load duke parents: diff changeset	10276 // Code for float compare:
a61af66fc99e Initial load duke parents: diff changeset	10277 // fcompp();
a61af66fc99e Initial load duke parents: diff changeset	10278 // fwait(); fnstsw_ax();
a61af66fc99e Initial load duke parents: diff changeset	10279 // sahf();
a61af66fc99e Initial load duke parents: diff changeset	10280 // movl(dst, unordered_result);
a61af66fc99e Initial load duke parents: diff changeset	10281 // jcc(Assembler::parity, exit);
a61af66fc99e Initial load duke parents: diff changeset	10282 // movl(dst, less_result);
a61af66fc99e Initial load duke parents: diff changeset	10283 // jcc(Assembler::below, exit);
a61af66fc99e Initial load duke parents: diff changeset	10284 // movl(dst, equal_result);
a61af66fc99e Initial load duke parents: diff changeset	10285 // jcc(Assembler::equal, exit);
a61af66fc99e Initial load duke parents: diff changeset	10286 // movl(dst, greater_result);
a61af66fc99e Initial load duke parents: diff changeset	10287 // exit:
a61af66fc99e Initial load duke parents: diff changeset	10288
a61af66fc99e Initial load duke parents: diff changeset	10289 // P6 version of float compare, sets condition codes in EFLAGS
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10290 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10291 predicate(VM_Version::supports_cmov() && UseSSE == 0);
a61af66fc99e Initial load duke parents: diff changeset	10292 match(Set cr (CmpF src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	10293 effect(KILL rax);
a61af66fc99e Initial load duke parents: diff changeset	10294 ins_cost(150);
a61af66fc99e Initial load duke parents: diff changeset	10295 format %{ "FLD $src1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10296 "FUCOMIP ST,$src2 // P6 instruction\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10297 "JNP exit\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10298 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10299 "SAHF\n"
a61af66fc99e Initial load duke parents: diff changeset	10300 "exit:\tNOP // avoid branch to branch" %}
a61af66fc99e Initial load duke parents: diff changeset	10301 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10302 ins_encode( Push_Reg_DPR(src1),
0 a61af66fc99e Initial load duke parents: diff changeset	10303 OpcP, RegOpc(src2),
a61af66fc99e Initial load duke parents: diff changeset	10304 cmpF_P6_fixup );
a61af66fc99e Initial load duke parents: diff changeset	10305 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10306 %}
a61af66fc99e Initial load duke parents: diff changeset	10307
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10308 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10309 predicate(VM_Version::supports_cmov() && UseSSE == 0);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10310 match(Set cr (CmpF src1 src2));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10311 ins_cost(100);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10312 format %{ "FLD $src1\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10313 "FUCOMIP ST,$src2 // P6 instruction" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10314 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10315 ins_encode( Push_Reg_DPR(src1),
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10316 OpcP, RegOpc(src2));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10317 ins_pipe( pipe_slow );
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10318 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10319
0 a61af66fc99e Initial load duke parents: diff changeset	10320
a61af66fc99e Initial load duke parents: diff changeset	10321 // Compare & branch
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10322 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10323 predicate(UseSSE == 0);
a61af66fc99e Initial load duke parents: diff changeset	10324 match(Set cr (CmpF src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	10325 effect(KILL rax);
a61af66fc99e Initial load duke parents: diff changeset	10326 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	10327 format %{ "FLD $src1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10328 "FCOMp $src2\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10329 "FNSTSW AX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10330 "TEST AX,0x400\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10331 "JZ,s flags\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10332 "MOV AH,1\t# unordered treat as LT\n"
a61af66fc99e Initial load duke parents: diff changeset	10333 "flags:\tSAHF" %}
a61af66fc99e Initial load duke parents: diff changeset	10334 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10335 ins_encode( Push_Reg_DPR(src1),
0 a61af66fc99e Initial load duke parents: diff changeset	10336 OpcP, RegOpc(src2),
a61af66fc99e Initial load duke parents: diff changeset	10337 fpu_flags);
a61af66fc99e Initial load duke parents: diff changeset	10338 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10339 %}
a61af66fc99e Initial load duke parents: diff changeset	10340
a61af66fc99e Initial load duke parents: diff changeset	10341 // Compare vs zero into -1,0,1
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	10342 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10343 predicate(UseSSE == 0);
a61af66fc99e Initial load duke parents: diff changeset	10344 match(Set dst (CmpF3 src1 zero));
a61af66fc99e Initial load duke parents: diff changeset	10345 effect(KILL cr, KILL rax);
a61af66fc99e Initial load duke parents: diff changeset	10346 ins_cost(280);
a61af66fc99e Initial load duke parents: diff changeset	10347 format %{ "FTSTF $dst,$src1" %}
a61af66fc99e Initial load duke parents: diff changeset	10348 opcode(0xE4, 0xD9);
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10349 ins_encode( Push_Reg_DPR(src1),
0 a61af66fc99e Initial load duke parents: diff changeset	10350 OpcS, OpcP, PopFPU,
a61af66fc99e Initial load duke parents: diff changeset	10351 CmpF_Result(dst));
a61af66fc99e Initial load duke parents: diff changeset	10352 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10353 %}
a61af66fc99e Initial load duke parents: diff changeset	10354
a61af66fc99e Initial load duke parents: diff changeset	10355 // Compare into -1,0,1
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	10356 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10357 predicate(UseSSE == 0);
a61af66fc99e Initial load duke parents: diff changeset	10358 match(Set dst (CmpF3 src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	10359 effect(KILL cr, KILL rax);
a61af66fc99e Initial load duke parents: diff changeset	10360 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	10361 format %{ "FCMPF $dst,$src1,$src2" %}
a61af66fc99e Initial load duke parents: diff changeset	10362 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10363 ins_encode( Push_Reg_DPR(src1),
0 a61af66fc99e Initial load duke parents: diff changeset	10364 OpcP, RegOpc(src2),
a61af66fc99e Initial load duke parents: diff changeset	10365 CmpF_Result(dst));
a61af66fc99e Initial load duke parents: diff changeset	10366 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10367 %}
a61af66fc99e Initial load duke parents: diff changeset	10368
a61af66fc99e Initial load duke parents: diff changeset	10369 // float compare and set condition codes in EFLAGS by XMM regs
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10370 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10371 predicate(UseSSE>=1);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10372 match(Set cr (CmpF src1 src2));
0 a61af66fc99e Initial load duke parents: diff changeset	10373 ins_cost(145);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10374 format %{ "UCOMISS $src1,$src2\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10375 "JNP,s exit\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10376 "PUSHF\t# saw NaN, set CF\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10377 "AND [rsp], #0xffffff2b\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10378 "POPF\n"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10379 "exit:" %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10380 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10381 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10382 emit_cmpfp_fixup(_masm);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10383 %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10384 ins_pipe( pipe_slow );
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10385 %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10386
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10387 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10388 predicate(UseSSE>=1);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10389 match(Set cr (CmpF src1 src2));
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10390 ins_cost(100);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10391 format %{ "UCOMISS $src1,$src2" %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10392 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10393 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10394 %}
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10395 ins_pipe( pipe_slow );
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10396 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10397
0 a61af66fc99e Initial load duke parents: diff changeset	10398 // float compare and set condition codes in EFLAGS by XMM regs
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10399 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10400 predicate(UseSSE>=1);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10401 match(Set cr (CmpF src1 (LoadF src2)));
0 a61af66fc99e Initial load duke parents: diff changeset	10402 ins_cost(165);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10403 format %{ "UCOMISS $src1,$src2\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10404 "JNP,s exit\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10405 "PUSHF\t# saw NaN, set CF\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10406 "AND [rsp], #0xffffff2b\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10407 "POPF\n"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10408 "exit:" %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10409 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10410 __ ucomiss($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10411 emit_cmpfp_fixup(_masm);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10412 %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10413 ins_pipe( pipe_slow );
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10414 %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10415
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10416 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10417 predicate(UseSSE>=1);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10418 match(Set cr (CmpF src1 (LoadF src2)));
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10419 ins_cost(100);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10420 format %{ "UCOMISS $src1,$src2" %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10421 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10422 __ ucomiss($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10423 %}
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10424 ins_pipe( pipe_slow );
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10425 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	10426
0 a61af66fc99e Initial load duke parents: diff changeset	10427 // Compare into -1,0,1 in XMM
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10428 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10429 predicate(UseSSE>=1);
a61af66fc99e Initial load duke parents: diff changeset	10430 match(Set dst (CmpF3 src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	10431 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	10432 ins_cost(255);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10433 format %{ "UCOMISS $src1, $src2\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10434 "MOV $dst, #-1\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10435 "JP,s done\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10436 "JB,s done\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10437 "SETNE $dst\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10438 "MOVZB $dst, $dst\n"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10439 "done:" %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10440 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10441 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10442 emit_cmpfp3(_masm, $dst$$Register);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10443 %}
0 a61af66fc99e Initial load duke parents: diff changeset	10444 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10445 %}
a61af66fc99e Initial load duke parents: diff changeset	10446
a61af66fc99e Initial load duke parents: diff changeset	10447 // Compare into -1,0,1 in XMM and memory
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10448 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10449 predicate(UseSSE>=1);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10450 match(Set dst (CmpF3 src1 (LoadF src2)));
0 a61af66fc99e Initial load duke parents: diff changeset	10451 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	10452 ins_cost(275);
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10453 format %{ "UCOMISS $src1, $src2\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10454 "MOV $dst, #-1\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10455 "JP,s done\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10456 "JB,s done\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10457 "SETNE $dst\n\t"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10458 "MOVZB $dst, $dst\n"
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10459 "done:" %}
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10460 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10461 __ ucomiss($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10462 emit_cmpfp3(_masm, $dst$$Register);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10463 %}
0 a61af66fc99e Initial load duke parents: diff changeset	10464 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10465 %}
a61af66fc99e Initial load duke parents: diff changeset	10466
a61af66fc99e Initial load duke parents: diff changeset	10467 // Spill to obtain 24-bit precision
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10468 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10469 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10470 match(Set dst (SubF src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	10471
a61af66fc99e Initial load duke parents: diff changeset	10472 format %{ "FSUB $dst,$src1 - $src2" %}
a61af66fc99e Initial load duke parents: diff changeset	10473 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10474 ins_encode( Push_Reg_FPR(src1),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10475 OpcReg_FPR(src2),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10476 Pop_Mem_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	10477 ins_pipe( fpu_mem_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	10478 %}
a61af66fc99e Initial load duke parents: diff changeset	10479 //
a61af66fc99e Initial load duke parents: diff changeset	10480 // This instruction does not round to 24-bits
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10481 instruct subFPR_reg(regFPR dst, regFPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10482 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10483 match(Set dst (SubF dst src));
a61af66fc99e Initial load duke parents: diff changeset	10484
a61af66fc99e Initial load duke parents: diff changeset	10485 format %{ "FSUB $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	10486 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10487 ins_encode( Push_Reg_FPR(src),
0 a61af66fc99e Initial load duke parents: diff changeset	10488 OpcP, RegOpc(dst) );
a61af66fc99e Initial load duke parents: diff changeset	10489 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	10490 %}
a61af66fc99e Initial load duke parents: diff changeset	10491
a61af66fc99e Initial load duke parents: diff changeset	10492 // Spill to obtain 24-bit precision
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10493 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10494 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10495 match(Set dst (AddF src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	10496
a61af66fc99e Initial load duke parents: diff changeset	10497 format %{ "FADD $dst,$src1,$src2" %}
a61af66fc99e Initial load duke parents: diff changeset	10498 opcode(0xD8, 0x0); /* D8 C0+i */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10499 ins_encode( Push_Reg_FPR(src2),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10500 OpcReg_FPR(src1),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10501 Pop_Mem_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	10502 ins_pipe( fpu_mem_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	10503 %}
a61af66fc99e Initial load duke parents: diff changeset	10504 //
a61af66fc99e Initial load duke parents: diff changeset	10505 // This instruction does not round to 24-bits
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10506 instruct addFPR_reg(regFPR dst, regFPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10507 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10508 match(Set dst (AddF dst src));
a61af66fc99e Initial load duke parents: diff changeset	10509
a61af66fc99e Initial load duke parents: diff changeset	10510 format %{ "FLD $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10511 "FADDp $dst,ST" %}
a61af66fc99e Initial load duke parents: diff changeset	10512 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10513 ins_encode( Push_Reg_FPR(src),
0 a61af66fc99e Initial load duke parents: diff changeset	10514 OpcP, RegOpc(dst) );
a61af66fc99e Initial load duke parents: diff changeset	10515 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	10516 %}
a61af66fc99e Initial load duke parents: diff changeset	10517
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10518 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10519 predicate(UseSSE==0);
a61af66fc99e Initial load duke parents: diff changeset	10520 match(Set dst (AbsF src));
a61af66fc99e Initial load duke parents: diff changeset	10521 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	10522 format %{ "FABS" %}
a61af66fc99e Initial load duke parents: diff changeset	10523 opcode(0xE1, 0xD9);
a61af66fc99e Initial load duke parents: diff changeset	10524 ins_encode( OpcS, OpcP );
a61af66fc99e Initial load duke parents: diff changeset	10525 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	10526 %}
a61af66fc99e Initial load duke parents: diff changeset	10527
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10528 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10529 predicate(UseSSE==0);
a61af66fc99e Initial load duke parents: diff changeset	10530 match(Set dst (NegF src));
a61af66fc99e Initial load duke parents: diff changeset	10531 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	10532 format %{ "FCHS" %}
a61af66fc99e Initial load duke parents: diff changeset	10533 opcode(0xE0, 0xD9);
a61af66fc99e Initial load duke parents: diff changeset	10534 ins_encode( OpcS, OpcP );
a61af66fc99e Initial load duke parents: diff changeset	10535 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	10536 %}
a61af66fc99e Initial load duke parents: diff changeset	10537
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10538 // Cisc-alternate to addFPR_reg
0 a61af66fc99e Initial load duke parents: diff changeset	10539 // Spill to obtain 24-bit precision
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10540 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10541 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10542 match(Set dst (AddF src1 (LoadF src2)));
a61af66fc99e Initial load duke parents: diff changeset	10543
a61af66fc99e Initial load duke parents: diff changeset	10544 format %{ "FLD $src2\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10545 "FADD ST,$src1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10546 "FSTP_S $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	10547 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i / / LoadF D9 /0 */
a61af66fc99e Initial load duke parents: diff changeset	10548 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10549 OpcReg_FPR(src1),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10550 Pop_Mem_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	10551 ins_pipe( fpu_mem_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	10552 %}
a61af66fc99e Initial load duke parents: diff changeset	10553 //
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10554 // Cisc-alternate to addFPR_reg
0 a61af66fc99e Initial load duke parents: diff changeset	10555 // This instruction does not round to 24-bits
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10556 instruct addFPR_reg_mem(regFPR dst, memory src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10557 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10558 match(Set dst (AddF dst (LoadF src)));
a61af66fc99e Initial load duke parents: diff changeset	10559
a61af66fc99e Initial load duke parents: diff changeset	10560 format %{ "FADD $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	10561 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0/ / LoadF D9 /0 */
a61af66fc99e Initial load duke parents: diff changeset	10562 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
a61af66fc99e Initial load duke parents: diff changeset	10563 OpcP, RegOpc(dst) );
a61af66fc99e Initial load duke parents: diff changeset	10564 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	10565 %}
a61af66fc99e Initial load duke parents: diff changeset	10566
a61af66fc99e Initial load duke parents: diff changeset	10567 // // Following two instructions for _222_mpegaudio
a61af66fc99e Initial load duke parents: diff changeset	10568 // Spill to obtain 24-bit precision
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10569 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10570 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10571 match(Set dst (AddF src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	10572
a61af66fc99e Initial load duke parents: diff changeset	10573 format %{ "FADD $dst,$src1,$src2" %}
a61af66fc99e Initial load duke parents: diff changeset	10574 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i / / LoadF D9 /0 */
a61af66fc99e Initial load duke parents: diff changeset	10575 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10576 OpcReg_FPR(src2),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10577 Pop_Mem_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	10578 ins_pipe( fpu_mem_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	10579 %}
a61af66fc99e Initial load duke parents: diff changeset	10580
a61af66fc99e Initial load duke parents: diff changeset	10581 // Cisc-spill variant
a61af66fc99e Initial load duke parents: diff changeset	10582 // Spill to obtain 24-bit precision
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10583 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10584 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10585 match(Set dst (AddF src1 (LoadF src2)));
a61af66fc99e Initial load duke parents: diff changeset	10586
a61af66fc99e Initial load duke parents: diff changeset	10587 format %{ "FADD $dst,$src1,$src2 cisc" %}
a61af66fc99e Initial load duke parents: diff changeset	10588 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i / / LoadF D9 /0 */
a61af66fc99e Initial load duke parents: diff changeset	10589 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
a61af66fc99e Initial load duke parents: diff changeset	10590 set_instruction_start,
a61af66fc99e Initial load duke parents: diff changeset	10591 OpcP, RMopc_Mem(secondary,src1),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10592 Pop_Mem_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	10593 ins_pipe( fpu_mem_mem_mem );
a61af66fc99e Initial load duke parents: diff changeset	10594 %}
a61af66fc99e Initial load duke parents: diff changeset	10595
a61af66fc99e Initial load duke parents: diff changeset	10596 // Spill to obtain 24-bit precision
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10597 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10598 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10599 match(Set dst (AddF src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	10600
a61af66fc99e Initial load duke parents: diff changeset	10601 format %{ "FADD $dst,$src1,$src2" %}
a61af66fc99e Initial load duke parents: diff changeset	10602 opcode(0xD8, 0x0, 0xD9); /* D8 /0 / / LoadF D9 /0 */
a61af66fc99e Initial load duke parents: diff changeset	10603 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
a61af66fc99e Initial load duke parents: diff changeset	10604 set_instruction_start,
a61af66fc99e Initial load duke parents: diff changeset	10605 OpcP, RMopc_Mem(secondary,src1),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10606 Pop_Mem_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	10607 ins_pipe( fpu_mem_mem_mem );
a61af66fc99e Initial load duke parents: diff changeset	10608 %}
a61af66fc99e Initial load duke parents: diff changeset	10609
a61af66fc99e Initial load duke parents: diff changeset	10610
a61af66fc99e Initial load duke parents: diff changeset	10611 // Spill to obtain 24-bit precision
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10612 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10613 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10614 match(Set dst (AddF src con));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10615 format %{ "FLD $src\n\t"
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10616 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
0 a61af66fc99e Initial load duke parents: diff changeset	10617 "FSTP_S $dst" %}
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10618 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10619 __ fld_s($src$$reg - 1); // FLD ST(i-1)
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10620 __ fadd_s($constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10621 __ fstp_s(Address(rsp, $dst$$disp));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10622 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10623 ins_pipe(fpu_mem_reg_con);
0 a61af66fc99e Initial load duke parents: diff changeset	10624 %}
a61af66fc99e Initial load duke parents: diff changeset	10625 //
a61af66fc99e Initial load duke parents: diff changeset	10626 // This instruction does not round to 24-bits
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10627 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10628 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10629 match(Set dst (AddF src con));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10630 format %{ "FLD $src\n\t"
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10631 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10632 "FSTP $dst" %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10633 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10634 __ fld_s($src$$reg - 1); // FLD ST(i-1)
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10635 __ fadd_s($constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10636 __ fstp_d($dst$$reg);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10637 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10638 ins_pipe(fpu_reg_reg_con);
0 a61af66fc99e Initial load duke parents: diff changeset	10639 %}
a61af66fc99e Initial load duke parents: diff changeset	10640
a61af66fc99e Initial load duke parents: diff changeset	10641 // Spill to obtain 24-bit precision
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10642 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10643 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10644 match(Set dst (MulF src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	10645
a61af66fc99e Initial load duke parents: diff changeset	10646 format %{ "FLD $src1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10647 "FMUL $src2\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10648 "FSTP_S $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	10649 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10650 ins_encode( Push_Reg_FPR(src1),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10651 OpcReg_FPR(src2),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10652 Pop_Mem_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	10653 ins_pipe( fpu_mem_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	10654 %}
a61af66fc99e Initial load duke parents: diff changeset	10655 //
a61af66fc99e Initial load duke parents: diff changeset	10656 // This instruction does not round to 24-bits
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10657 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10658 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10659 match(Set dst (MulF src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	10660
a61af66fc99e Initial load duke parents: diff changeset	10661 format %{ "FLD $src1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10662 "FMUL $src2\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10663 "FSTP_S $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	10664 opcode(0xD8, 0x1); /* D8 C8+i */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10665 ins_encode( Push_Reg_FPR(src2),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10666 OpcReg_FPR(src1),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10667 Pop_Reg_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	10668 ins_pipe( fpu_reg_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	10669 %}
a61af66fc99e Initial load duke parents: diff changeset	10670
a61af66fc99e Initial load duke parents: diff changeset	10671
a61af66fc99e Initial load duke parents: diff changeset	10672 // Spill to obtain 24-bit precision
a61af66fc99e Initial load duke parents: diff changeset	10673 // Cisc-alternate to reg-reg multiply
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10674 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10675 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10676 match(Set dst (MulF src1 (LoadF src2)));
a61af66fc99e Initial load duke parents: diff changeset	10677
a61af66fc99e Initial load duke parents: diff changeset	10678 format %{ "FLD_S $src2\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10679 "FMUL $src1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10680 "FSTP_S $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	10681 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1/ / LoadF D9 /0 */
a61af66fc99e Initial load duke parents: diff changeset	10682 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10683 OpcReg_FPR(src1),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10684 Pop_Mem_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	10685 ins_pipe( fpu_mem_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	10686 %}
a61af66fc99e Initial load duke parents: diff changeset	10687 //
a61af66fc99e Initial load duke parents: diff changeset	10688 // This instruction does not round to 24-bits
a61af66fc99e Initial load duke parents: diff changeset	10689 // Cisc-alternate to reg-reg multiply
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10690 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10691 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10692 match(Set dst (MulF src1 (LoadF src2)));
a61af66fc99e Initial load duke parents: diff changeset	10693
a61af66fc99e Initial load duke parents: diff changeset	10694 format %{ "FMUL $dst,$src1,$src2" %}
a61af66fc99e Initial load duke parents: diff changeset	10695 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i / / LoadF D9 /0 */
a61af66fc99e Initial load duke parents: diff changeset	10696 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10697 OpcReg_FPR(src1),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10698 Pop_Reg_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	10699 ins_pipe( fpu_reg_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	10700 %}
a61af66fc99e Initial load duke parents: diff changeset	10701
a61af66fc99e Initial load duke parents: diff changeset	10702 // Spill to obtain 24-bit precision
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10703 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10704 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10705 match(Set dst (MulF src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	10706
a61af66fc99e Initial load duke parents: diff changeset	10707 format %{ "FMUL $dst,$src1,$src2" %}
a61af66fc99e Initial load duke parents: diff changeset	10708 opcode(0xD8, 0x1, 0xD9); /* D8 /1 / / LoadF D9 /0 */
a61af66fc99e Initial load duke parents: diff changeset	10709 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
a61af66fc99e Initial load duke parents: diff changeset	10710 set_instruction_start,
a61af66fc99e Initial load duke parents: diff changeset	10711 OpcP, RMopc_Mem(secondary,src1),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10712 Pop_Mem_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	10713 ins_pipe( fpu_mem_mem_mem );
a61af66fc99e Initial load duke parents: diff changeset	10714 %}
a61af66fc99e Initial load duke parents: diff changeset	10715
a61af66fc99e Initial load duke parents: diff changeset	10716 // Spill to obtain 24-bit precision
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10717 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10718 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10719 match(Set dst (MulF src con));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10720
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10721 format %{ "FLD $src\n\t"
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10722 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10723 "FSTP_S $dst" %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10724 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10725 __ fld_s($src$$reg - 1); // FLD ST(i-1)
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10726 __ fmul_s($constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10727 __ fstp_s(Address(rsp, $dst$$disp));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10728 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10729 ins_pipe(fpu_mem_reg_con);
0 a61af66fc99e Initial load duke parents: diff changeset	10730 %}
a61af66fc99e Initial load duke parents: diff changeset	10731 //
a61af66fc99e Initial load duke parents: diff changeset	10732 // This instruction does not round to 24-bits
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10733 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10734 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10735 match(Set dst (MulF src con));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10736
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10737 format %{ "FLD $src\n\t"
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10738 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10739 "FSTP $dst" %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10740 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10741 __ fld_s($src$$reg - 1); // FLD ST(i-1)
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10742 __ fmul_s($constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10743 __ fstp_d($dst$$reg);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10744 %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	10745 ins_pipe(fpu_reg_reg_con);
0 a61af66fc99e Initial load duke parents: diff changeset	10746 %}
a61af66fc99e Initial load duke parents: diff changeset	10747
a61af66fc99e Initial load duke parents: diff changeset	10748
a61af66fc99e Initial load duke parents: diff changeset	10749 //
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10750 // MACRO1 -- subsume unshared load into mulFPR
0 a61af66fc99e Initial load duke parents: diff changeset	10751 // This instruction does not round to 24-bits
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10752 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10753 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10754 match(Set dst (MulF (LoadF mem1) src));
a61af66fc99e Initial load duke parents: diff changeset	10755
a61af66fc99e Initial load duke parents: diff changeset	10756 format %{ "FLD $mem1 ===MACRO1===\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10757 "FMUL ST,$src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10758 "FSTP $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	10759 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 / / LoadF D9 /0 */
a61af66fc99e Initial load duke parents: diff changeset	10760 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10761 OpcReg_FPR(src),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10762 Pop_Reg_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	10763 ins_pipe( fpu_reg_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	10764 %}
a61af66fc99e Initial load duke parents: diff changeset	10765 //
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10766 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
0 a61af66fc99e Initial load duke parents: diff changeset	10767 // This instruction does not round to 24-bits
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10768 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10769 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10770 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
a61af66fc99e Initial load duke parents: diff changeset	10771 ins_cost(95);
a61af66fc99e Initial load duke parents: diff changeset	10772
a61af66fc99e Initial load duke parents: diff changeset	10773 format %{ "FLD $mem1 ===MACRO2===\n\t"
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10774 "FMUL ST,$src1 subsume mulFPR left load\n\t"
0 a61af66fc99e Initial load duke parents: diff changeset	10775 "FADD ST,$src2\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10776 "FSTP $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	10777 opcode(0xD9); /* LoadF D9 /0 */
a61af66fc99e Initial load duke parents: diff changeset	10778 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
a61af66fc99e Initial load duke parents: diff changeset	10779 FMul_ST_reg(src1),
a61af66fc99e Initial load duke parents: diff changeset	10780 FAdd_ST_reg(src2),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10781 Pop_Reg_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	10782 ins_pipe( fpu_reg_mem_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	10783 %}
a61af66fc99e Initial load duke parents: diff changeset	10784
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10785 // MACRO3 -- addFPR a mulFPR
0 a61af66fc99e Initial load duke parents: diff changeset	10786 // This instruction does not round to 24-bits. It is a '2-address'
a61af66fc99e Initial load duke parents: diff changeset	10787 // instruction in that the result goes back to src2. This eliminates
a61af66fc99e Initial load duke parents: diff changeset	10788 // a move from the macro; possibly the register allocator will have
a61af66fc99e Initial load duke parents: diff changeset	10789 // to add it back (and maybe not).
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10790 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10791 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10792 match(Set src2 (AddF (MulF src0 src1) src2));
a61af66fc99e Initial load duke parents: diff changeset	10793
a61af66fc99e Initial load duke parents: diff changeset	10794 format %{ "FLD $src0 ===MACRO3===\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10795 "FMUL ST,$src1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10796 "FADDP $src2,ST" %}
a61af66fc99e Initial load duke parents: diff changeset	10797 opcode(0xD9); /* LoadF D9 /0 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10798 ins_encode( Push_Reg_FPR(src0),
0 a61af66fc99e Initial load duke parents: diff changeset	10799 FMul_ST_reg(src1),
a61af66fc99e Initial load duke parents: diff changeset	10800 FAddP_reg_ST(src2) );
a61af66fc99e Initial load duke parents: diff changeset	10801 ins_pipe( fpu_reg_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	10802 %}
a61af66fc99e Initial load duke parents: diff changeset	10803
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10804 // MACRO4 -- divFPR subFPR
0 a61af66fc99e Initial load duke parents: diff changeset	10805 // This instruction does not round to 24-bits
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10806 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10807 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10808 match(Set dst (DivF (SubF src2 src1) src3));
a61af66fc99e Initial load duke parents: diff changeset	10809
a61af66fc99e Initial load duke parents: diff changeset	10810 format %{ "FLD $src2 ===MACRO4===\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10811 "FSUB ST,$src1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10812 "FDIV ST,$src3\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10813 "FSTP $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	10814 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10815 ins_encode( Push_Reg_FPR(src2),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10816 subFPR_divFPR_encode(src1,src3),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10817 Pop_Reg_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	10818 ins_pipe( fpu_reg_reg_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	10819 %}
a61af66fc99e Initial load duke parents: diff changeset	10820
a61af66fc99e Initial load duke parents: diff changeset	10821 // Spill to obtain 24-bit precision
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10822 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10823 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10824 match(Set dst (DivF src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	10825
a61af66fc99e Initial load duke parents: diff changeset	10826 format %{ "FDIV $dst,$src1,$src2" %}
a61af66fc99e Initial load duke parents: diff changeset	10827 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10828 ins_encode( Push_Reg_FPR(src1),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10829 OpcReg_FPR(src2),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10830 Pop_Mem_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	10831 ins_pipe( fpu_mem_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	10832 %}
a61af66fc99e Initial load duke parents: diff changeset	10833 //
a61af66fc99e Initial load duke parents: diff changeset	10834 // This instruction does not round to 24-bits
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10835 instruct divFPR_reg(regFPR dst, regFPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10836 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10837 match(Set dst (DivF dst src));
a61af66fc99e Initial load duke parents: diff changeset	10838
a61af66fc99e Initial load duke parents: diff changeset	10839 format %{ "FDIV $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	10840 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10841 ins_encode( Push_Reg_FPR(src),
0 a61af66fc99e Initial load duke parents: diff changeset	10842 OpcP, RegOpc(dst) );
a61af66fc99e Initial load duke parents: diff changeset	10843 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	10844 %}
a61af66fc99e Initial load duke parents: diff changeset	10845
a61af66fc99e Initial load duke parents: diff changeset	10846
a61af66fc99e Initial load duke parents: diff changeset	10847 // Spill to obtain 24-bit precision
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10848 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10849 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10850 match(Set dst (ModF src1 src2));
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10851 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
0 a61af66fc99e Initial load duke parents: diff changeset	10852
a61af66fc99e Initial load duke parents: diff changeset	10853 format %{ "FMOD $dst,$src1,$src2" %}
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10854 ins_encode( Push_Reg_Mod_DPR(src1, src2),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10855 emitModDPR(),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10856 Push_Result_Mod_DPR(src2),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10857 Pop_Mem_FPR(dst));
0 a61af66fc99e Initial load duke parents: diff changeset	10858 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10859 %}
a61af66fc99e Initial load duke parents: diff changeset	10860 //
a61af66fc99e Initial load duke parents: diff changeset	10861 // This instruction does not round to 24-bits
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10862 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10863 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	10864 match(Set dst (ModF dst src));
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10865 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
0 a61af66fc99e Initial load duke parents: diff changeset	10866
a61af66fc99e Initial load duke parents: diff changeset	10867 format %{ "FMOD $dst,$src" %}
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10868 ins_encode(Push_Reg_Mod_DPR(dst, src),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10869 emitModDPR(),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10870 Push_Result_Mod_DPR(src),
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10871 Pop_Reg_FPR(dst));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10872 ins_pipe( pipe_slow );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10873 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10874
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10875 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10876 predicate(UseSSE>=1);
a61af66fc99e Initial load duke parents: diff changeset	10877 match(Set dst (ModF src0 src1));
a61af66fc99e Initial load duke parents: diff changeset	10878 effect(KILL rax, KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	10879 format %{ "SUB ESP,4\t # FMOD\n"
a61af66fc99e Initial load duke parents: diff changeset	10880 "\tMOVSS [ESP+0],$src1\n"
a61af66fc99e Initial load duke parents: diff changeset	10881 "\tFLD_S [ESP+0]\n"
a61af66fc99e Initial load duke parents: diff changeset	10882 "\tMOVSS [ESP+0],$src0\n"
a61af66fc99e Initial load duke parents: diff changeset	10883 "\tFLD_S [ESP+0]\n"
a61af66fc99e Initial load duke parents: diff changeset	10884 "loop:\tFPREM\n"
a61af66fc99e Initial load duke parents: diff changeset	10885 "\tFWAIT\n"
a61af66fc99e Initial load duke parents: diff changeset	10886 "\tFNSTSW AX\n"
a61af66fc99e Initial load duke parents: diff changeset	10887 "\tSAHF\n"
a61af66fc99e Initial load duke parents: diff changeset	10888 "\tJP loop\n"
a61af66fc99e Initial load duke parents: diff changeset	10889 "\tFSTP_S [ESP+0]\n"
a61af66fc99e Initial load duke parents: diff changeset	10890 "\tMOVSS $dst,[ESP+0]\n"
a61af66fc99e Initial load duke parents: diff changeset	10891 "\tADD ESP,4\n"
a61af66fc99e Initial load duke parents: diff changeset	10892 "\tFSTP ST0\t # Restore FPU Stack"
a61af66fc99e Initial load duke parents: diff changeset	10893 %}
a61af66fc99e Initial load duke parents: diff changeset	10894 ins_cost(250);
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10895 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
0 a61af66fc99e Initial load duke parents: diff changeset	10896 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10897 %}
a61af66fc99e Initial load duke parents: diff changeset	10898
a61af66fc99e Initial load duke parents: diff changeset	10899
a61af66fc99e Initial load duke parents: diff changeset	10900 //----------Arithmetic Conversion Instructions---------------------------------
a61af66fc99e Initial load duke parents: diff changeset	10901 // The conversions operations are all Alpha sorted. Please keep it that way!
a61af66fc99e Initial load duke parents: diff changeset	10902
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10903 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10904 predicate(UseSSE==0);
a61af66fc99e Initial load duke parents: diff changeset	10905 match(Set dst (RoundFloat src));
a61af66fc99e Initial load duke parents: diff changeset	10906 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	10907 format %{ "FST_S $dst,$src\t# F-round" %}
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10908 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
0 a61af66fc99e Initial load duke parents: diff changeset	10909 ins_pipe( fpu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	10910 %}
a61af66fc99e Initial load duke parents: diff changeset	10911
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10912 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10913 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	10914 match(Set dst (RoundDouble src));
a61af66fc99e Initial load duke parents: diff changeset	10915 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	10916 format %{ "FST_D $dst,$src\t# D-round" %}
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10917 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
0 a61af66fc99e Initial load duke parents: diff changeset	10918 ins_pipe( fpu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	10919 %}
a61af66fc99e Initial load duke parents: diff changeset	10920
a61af66fc99e Initial load duke parents: diff changeset	10921 // Force rounding to 24-bit precision and 6-bit exponent
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10922 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10923 predicate(UseSSE==0);
a61af66fc99e Initial load duke parents: diff changeset	10924 match(Set dst (ConvD2F src));
a61af66fc99e Initial load duke parents: diff changeset	10925 format %{ "FST_S $dst,$src\t# F-round" %}
a61af66fc99e Initial load duke parents: diff changeset	10926 expand %{
a61af66fc99e Initial load duke parents: diff changeset	10927 roundFloat_mem_reg(dst,src);
a61af66fc99e Initial load duke parents: diff changeset	10928 %}
a61af66fc99e Initial load duke parents: diff changeset	10929 %}
a61af66fc99e Initial load duke parents: diff changeset	10930
a61af66fc99e Initial load duke parents: diff changeset	10931 // Force rounding to 24-bit precision and 6-bit exponent
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10932 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10933 predicate(UseSSE==1);
a61af66fc99e Initial load duke parents: diff changeset	10934 match(Set dst (ConvD2F src));
a61af66fc99e Initial load duke parents: diff changeset	10935 effect( KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	10936 format %{ "SUB ESP,4\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10937 "FST_S [ESP],$src\t# F-round\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10938 "MOVSS $dst,[ESP]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10939 "ADD ESP,4" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10940 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10941 __ subptr(rsp, 4);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10942 if ($src$$reg != FPR1L_enc) {
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10943 __ fld_s($src$$reg-1);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10944 __ fstp_s(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10945 } else {
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10946 __ fst_s(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10947 }
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10948 __ movflt($dst$$XMMRegister, Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10949 __ addptr(rsp, 4);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10950 %}
0 a61af66fc99e Initial load duke parents: diff changeset	10951 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10952 %}
a61af66fc99e Initial load duke parents: diff changeset	10953
a61af66fc99e Initial load duke parents: diff changeset	10954 // Force rounding double precision to single precision
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10955 instruct convD2F_reg(regF dst, regD src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10956 predicate(UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	10957 match(Set dst (ConvD2F src));
a61af66fc99e Initial load duke parents: diff changeset	10958 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10959 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10960 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10961 %}
0 a61af66fc99e Initial load duke parents: diff changeset	10962 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10963 %}
a61af66fc99e Initial load duke parents: diff changeset	10964
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10965 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10966 predicate(UseSSE==0);
a61af66fc99e Initial load duke parents: diff changeset	10967 match(Set dst (ConvF2D src));
a61af66fc99e Initial load duke parents: diff changeset	10968 format %{ "FST_S $dst,$src\t# D-round" %}
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10969 ins_encode( Pop_Reg_Reg_DPR(dst, src));
0 a61af66fc99e Initial load duke parents: diff changeset	10970 ins_pipe( fpu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	10971 %}
a61af66fc99e Initial load duke parents: diff changeset	10972
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10973 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10974 predicate(UseSSE==1);
a61af66fc99e Initial load duke parents: diff changeset	10975 match(Set dst (ConvF2D src));
a61af66fc99e Initial load duke parents: diff changeset	10976 format %{ "FST_D $dst,$src\t# D-round" %}
a61af66fc99e Initial load duke parents: diff changeset	10977 expand %{
a61af66fc99e Initial load duke parents: diff changeset	10978 roundDouble_mem_reg(dst,src);
a61af66fc99e Initial load duke parents: diff changeset	10979 %}
a61af66fc99e Initial load duke parents: diff changeset	10980 %}
a61af66fc99e Initial load duke parents: diff changeset	10981
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	10982 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	10983 predicate(UseSSE==1);
a61af66fc99e Initial load duke parents: diff changeset	10984 match(Set dst (ConvF2D src));
a61af66fc99e Initial load duke parents: diff changeset	10985 effect( KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	10986 format %{ "SUB ESP,4\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10987 "MOVSS [ESP] $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10988 "FLD_S [ESP]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10989 "ADD ESP,4\n\t"
a61af66fc99e Initial load duke parents: diff changeset	10990 "FSTP $dst\t# D-round" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10991 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10992 __ subptr(rsp, 4);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10993 __ movflt(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10994 __ fld_s(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10995 __ addptr(rsp, 4);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10996 __ fstp_d($dst$$reg);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	10997 %}
0 a61af66fc99e Initial load duke parents: diff changeset	10998 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	10999 %}
a61af66fc99e Initial load duke parents: diff changeset	11000
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11001 instruct convF2D_reg(regD dst, regF src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11002 predicate(UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	11003 match(Set dst (ConvF2D src));
a61af66fc99e Initial load duke parents: diff changeset	11004 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11005 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11006 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11007 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11008 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11009 %}
a61af66fc99e Initial load duke parents: diff changeset	11010
a61af66fc99e Initial load duke parents: diff changeset	11011 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11012 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11013 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	11014 match(Set dst (ConvD2I src));
a61af66fc99e Initial load duke parents: diff changeset	11015 effect( KILL tmp, KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	11016 format %{ "FLD $src\t# Convert double to int \n\t"
a61af66fc99e Initial load duke parents: diff changeset	11017 "FLDCW trunc mode\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11018 "SUB ESP,4\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11019 "FISTp [ESP + #0]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11020 "FLDCW std/24-bit mode\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11021 "POP EAX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11022 "CMP EAX,0x80000000\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11023 "JNE,s fast\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11024 "FLD_D $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11025 "CALL d2i_wrapper\n"
a61af66fc99e Initial load duke parents: diff changeset	11026 "fast:" %}
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11027 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
0 a61af66fc99e Initial load duke parents: diff changeset	11028 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11029 %}
a61af66fc99e Initial load duke parents: diff changeset	11030
a61af66fc99e Initial load duke parents: diff changeset	11031 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11032 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11033 predicate(UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	11034 match(Set dst (ConvD2I src));
a61af66fc99e Initial load duke parents: diff changeset	11035 effect( KILL tmp, KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	11036 format %{ "CVTTSD2SI $dst, $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11037 "CMP $dst,0x80000000\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11038 "JNE,s fast\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11039 "SUB ESP, 8\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11040 "MOVSD [ESP], $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11041 "FLD_D [ESP]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11042 "ADD ESP, 8\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11043 "CALL d2i_wrapper\n"
a61af66fc99e Initial load duke parents: diff changeset	11044 "fast:" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11045 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11046 Label fast;
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11047 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11048 __ cmpl($dst$$Register, 0x80000000);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11049 __ jccb(Assembler::notEqual, fast);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11050 __ subptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11051 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11052 __ fld_d(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11053 __ addptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11054 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11055 __ bind(fast);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11056 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11057 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11058 %}
a61af66fc99e Initial load duke parents: diff changeset	11059
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11060 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11061 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	11062 match(Set dst (ConvD2L src));
a61af66fc99e Initial load duke parents: diff changeset	11063 effect( KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	11064 format %{ "FLD $src\t# Convert double to long\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11065 "FLDCW trunc mode\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11066 "SUB ESP,8\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11067 "FISTp [ESP + #0]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11068 "FLDCW std/24-bit mode\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11069 "POP EAX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11070 "POP EDX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11071 "CMP EDX,0x80000000\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11072 "JNE,s fast\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11073 "TEST EAX,EAX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11074 "JNE,s fast\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11075 "FLD $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11076 "CALL d2l_wrapper\n"
a61af66fc99e Initial load duke parents: diff changeset	11077 "fast:" %}
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11078 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
0 a61af66fc99e Initial load duke parents: diff changeset	11079 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11080 %}
a61af66fc99e Initial load duke parents: diff changeset	11081
a61af66fc99e Initial load duke parents: diff changeset	11082 // XMM lacks a float/double->long conversion, so use the old FPU stack.
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11083 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11084 predicate (UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	11085 match(Set dst (ConvD2L src));
a61af66fc99e Initial load duke parents: diff changeset	11086 effect( KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	11087 format %{ "SUB ESP,8\t# Convert double to long\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11088 "MOVSD [ESP],$src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11089 "FLD_D [ESP]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11090 "FLDCW trunc mode\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11091 "FISTp [ESP + #0]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11092 "FLDCW std/24-bit mode\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11093 "POP EAX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11094 "POP EDX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11095 "CMP EDX,0x80000000\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11096 "JNE,s fast\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11097 "TEST EAX,EAX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11098 "JNE,s fast\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11099 "SUB ESP,8\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11100 "MOVSD [ESP],$src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11101 "FLD_D [ESP]\n\t"
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11102 "ADD ESP,8\n\t"
0 a61af66fc99e Initial load duke parents: diff changeset	11103 "CALL d2l_wrapper\n"
a61af66fc99e Initial load duke parents: diff changeset	11104 "fast:" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11105 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11106 Label fast;
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11107 __ subptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11108 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11109 __ fld_d(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11110 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11111 __ fistp_d(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11112 // Restore the rounding mode, mask the exception
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11113 if (Compile::current()->in_24_bit_fp_mode()) {
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11114 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11115 } else {
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11116 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11117 }
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11118 // Load the converted long, adjust CPU stack
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11119 __ pop(rax);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11120 __ pop(rdx);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11121 __ cmpl(rdx, 0x80000000);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11122 __ jccb(Assembler::notEqual, fast);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11123 __ testl(rax, rax);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11124 __ jccb(Assembler::notEqual, fast);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11125 __ subptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11126 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11127 __ fld_d(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11128 __ addptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11129 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11130 __ bind(fast);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11131 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11132 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11133 %}
a61af66fc99e Initial load duke parents: diff changeset	11134
a61af66fc99e Initial load duke parents: diff changeset	11135 // Convert a double to an int. Java semantics require we do complex
a61af66fc99e Initial load duke parents: diff changeset	11136 // manglations in the corner cases. So we set the rounding mode to
a61af66fc99e Initial load duke parents: diff changeset	11137 // 'zero', store the darned double down as an int, and reset the
a61af66fc99e Initial load duke parents: diff changeset	11138 // rounding mode to 'nearest'. The hardware stores a flag value down
a61af66fc99e Initial load duke parents: diff changeset	11139 // if we would overflow or converted a NAN; we check for this and
a61af66fc99e Initial load duke parents: diff changeset	11140 // and go the slow path if needed.
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11141 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11142 predicate(UseSSE==0);
a61af66fc99e Initial load duke parents: diff changeset	11143 match(Set dst (ConvF2I src));
a61af66fc99e Initial load duke parents: diff changeset	11144 effect( KILL tmp, KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	11145 format %{ "FLD $src\t# Convert float to int \n\t"
a61af66fc99e Initial load duke parents: diff changeset	11146 "FLDCW trunc mode\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11147 "SUB ESP,4\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11148 "FISTp [ESP + #0]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11149 "FLDCW std/24-bit mode\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11150 "POP EAX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11151 "CMP EAX,0x80000000\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11152 "JNE,s fast\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11153 "FLD $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11154 "CALL d2i_wrapper\n"
a61af66fc99e Initial load duke parents: diff changeset	11155 "fast:" %}
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11156 // DPR2I_encoding works for FPR2I
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11157 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
0 a61af66fc99e Initial load duke parents: diff changeset	11158 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11159 %}
a61af66fc99e Initial load duke parents: diff changeset	11160
a61af66fc99e Initial load duke parents: diff changeset	11161 // Convert a float in xmm to an int reg.
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11162 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11163 predicate(UseSSE>=1);
a61af66fc99e Initial load duke parents: diff changeset	11164 match(Set dst (ConvF2I src));
a61af66fc99e Initial load duke parents: diff changeset	11165 effect( KILL tmp, KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	11166 format %{ "CVTTSS2SI $dst, $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11167 "CMP $dst,0x80000000\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11168 "JNE,s fast\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11169 "SUB ESP, 4\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11170 "MOVSS [ESP], $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11171 "FLD [ESP]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11172 "ADD ESP, 4\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11173 "CALL d2i_wrapper\n"
a61af66fc99e Initial load duke parents: diff changeset	11174 "fast:" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11175 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11176 Label fast;
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11177 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11178 __ cmpl($dst$$Register, 0x80000000);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11179 __ jccb(Assembler::notEqual, fast);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11180 __ subptr(rsp, 4);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11181 __ movflt(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11182 __ fld_s(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11183 __ addptr(rsp, 4);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11184 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11185 __ bind(fast);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11186 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11187 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11188 %}
a61af66fc99e Initial load duke parents: diff changeset	11189
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11190 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11191 predicate(UseSSE==0);
a61af66fc99e Initial load duke parents: diff changeset	11192 match(Set dst (ConvF2L src));
a61af66fc99e Initial load duke parents: diff changeset	11193 effect( KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	11194 format %{ "FLD $src\t# Convert float to long\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11195 "FLDCW trunc mode\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11196 "SUB ESP,8\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11197 "FISTp [ESP + #0]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11198 "FLDCW std/24-bit mode\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11199 "POP EAX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11200 "POP EDX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11201 "CMP EDX,0x80000000\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11202 "JNE,s fast\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11203 "TEST EAX,EAX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11204 "JNE,s fast\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11205 "FLD $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11206 "CALL d2l_wrapper\n"
a61af66fc99e Initial load duke parents: diff changeset	11207 "fast:" %}
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11208 // DPR2L_encoding works for FPR2L
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11209 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
0 a61af66fc99e Initial load duke parents: diff changeset	11210 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11211 %}
a61af66fc99e Initial load duke parents: diff changeset	11212
a61af66fc99e Initial load duke parents: diff changeset	11213 // XMM lacks a float/double->long conversion, so use the old FPU stack.
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11214 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11215 predicate (UseSSE>=1);
a61af66fc99e Initial load duke parents: diff changeset	11216 match(Set dst (ConvF2L src));
a61af66fc99e Initial load duke parents: diff changeset	11217 effect( KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	11218 format %{ "SUB ESP,8\t# Convert float to long\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11219 "MOVSS [ESP],$src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11220 "FLD_S [ESP]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11221 "FLDCW trunc mode\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11222 "FISTp [ESP + #0]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11223 "FLDCW std/24-bit mode\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11224 "POP EAX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11225 "POP EDX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11226 "CMP EDX,0x80000000\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11227 "JNE,s fast\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11228 "TEST EAX,EAX\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11229 "JNE,s fast\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11230 "SUB ESP,4\t# Convert float to long\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11231 "MOVSS [ESP],$src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11232 "FLD_S [ESP]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11233 "ADD ESP,4\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11234 "CALL d2l_wrapper\n"
a61af66fc99e Initial load duke parents: diff changeset	11235 "fast:" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11236 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11237 Label fast;
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11238 __ subptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11239 __ movflt(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11240 __ fld_s(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11241 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11242 __ fistp_d(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11243 // Restore the rounding mode, mask the exception
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11244 if (Compile::current()->in_24_bit_fp_mode()) {
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11245 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11246 } else {
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11247 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11248 }
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11249 // Load the converted long, adjust CPU stack
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11250 __ pop(rax);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11251 __ pop(rdx);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11252 __ cmpl(rdx, 0x80000000);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11253 __ jccb(Assembler::notEqual, fast);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11254 __ testl(rax, rax);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11255 __ jccb(Assembler::notEqual, fast);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11256 __ subptr(rsp, 4);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11257 __ movflt(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11258 __ fld_s(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11259 __ addptr(rsp, 4);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11260 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11261 __ bind(fast);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11262 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11263 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11264 %}
a61af66fc99e Initial load duke parents: diff changeset	11265
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11266 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11267 predicate( UseSSE<=1 );
a61af66fc99e Initial load duke parents: diff changeset	11268 match(Set dst (ConvI2D src));
a61af66fc99e Initial load duke parents: diff changeset	11269 format %{ "FILD $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11270 "FSTP $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	11271 opcode(0xDB, 0x0); /* DB /0 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11272 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
0 a61af66fc99e Initial load duke parents: diff changeset	11273 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	11274 %}
a61af66fc99e Initial load duke parents: diff changeset	11275
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11276 instruct convI2D_reg(regD dst, rRegI src) %{
71 3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11277 predicate( UseSSE>=2 && !UseXmmI2D );
0 a61af66fc99e Initial load duke parents: diff changeset	11278 match(Set dst (ConvI2D src));
a61af66fc99e Initial load duke parents: diff changeset	11279 format %{ "CVTSI2SD $dst,$src" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11280 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11281 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11282 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11283 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11284 %}
a61af66fc99e Initial load duke parents: diff changeset	11285
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11286 instruct convI2D_mem(regD dst, memory mem) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11287 predicate( UseSSE>=2 );
a61af66fc99e Initial load duke parents: diff changeset	11288 match(Set dst (ConvI2D (LoadI mem)));
a61af66fc99e Initial load duke parents: diff changeset	11289 format %{ "CVTSI2SD $dst,$mem" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11290 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11291 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11292 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11293 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11294 %}
a61af66fc99e Initial load duke parents: diff changeset	11295
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11296 instruct convXI2D_reg(regD dst, rRegI src)
71 3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11297 %{
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11298 predicate( UseSSE>=2 && UseXmmI2D );
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11299 match(Set dst (ConvI2D src));
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11300
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11301 format %{ "MOVD $dst,$src\n\t"
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11302 "CVTDQ2PD $dst,$dst\t# i2d" %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11303 ins_encode %{
304 dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories never parents: 235 diff changeset	11304 __ movdl($dst$$XMMRegister, $src$$Register);
71 3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11305 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11306 %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11307 ins_pipe(pipe_slow); // XXX
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11308 %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11309
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11310 instruct convI2DPR_mem(regDPR dst, memory mem) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11311 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	11312 match(Set dst (ConvI2D (LoadI mem)));
a61af66fc99e Initial load duke parents: diff changeset	11313 format %{ "FILD $mem\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11314 "FSTP $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	11315 opcode(0xDB); /* DB /0 */
a61af66fc99e Initial load duke parents: diff changeset	11316 ins_encode( OpcP, RMopc_Mem(0x00,mem),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11317 Pop_Reg_DPR(dst));
0 a61af66fc99e Initial load duke parents: diff changeset	11318 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	11319 %}
a61af66fc99e Initial load duke parents: diff changeset	11320
a61af66fc99e Initial load duke parents: diff changeset	11321 // Convert a byte to a float; no rounding step needed.
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11322 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11323 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
a61af66fc99e Initial load duke parents: diff changeset	11324 match(Set dst (ConvI2F src));
a61af66fc99e Initial load duke parents: diff changeset	11325 format %{ "FILD $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11326 "FSTP $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	11327
a61af66fc99e Initial load duke parents: diff changeset	11328 opcode(0xDB, 0x0); /* DB /0 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11329 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
0 a61af66fc99e Initial load duke parents: diff changeset	11330 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	11331 %}
a61af66fc99e Initial load duke parents: diff changeset	11332
a61af66fc99e Initial load duke parents: diff changeset	11333 // In 24-bit mode, force exponent rounding by storing back out
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11334 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11335 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	11336 match(Set dst (ConvI2F src));
a61af66fc99e Initial load duke parents: diff changeset	11337 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	11338 format %{ "FILD $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11339 "FSTP_S $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	11340 opcode(0xDB, 0x0); /* DB /0 */
a61af66fc99e Initial load duke parents: diff changeset	11341 ins_encode( Push_Mem_I(src),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11342 Pop_Mem_FPR(dst));
0 a61af66fc99e Initial load duke parents: diff changeset	11343 ins_pipe( fpu_mem_mem );
a61af66fc99e Initial load duke parents: diff changeset	11344 %}
a61af66fc99e Initial load duke parents: diff changeset	11345
a61af66fc99e Initial load duke parents: diff changeset	11346 // In 24-bit mode, force exponent rounding by storing back out
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11347 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11348 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	11349 match(Set dst (ConvI2F (LoadI mem)));
a61af66fc99e Initial load duke parents: diff changeset	11350 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	11351 format %{ "FILD $mem\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11352 "FSTP_S $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	11353 opcode(0xDB); /* DB /0 */
a61af66fc99e Initial load duke parents: diff changeset	11354 ins_encode( OpcP, RMopc_Mem(0x00,mem),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11355 Pop_Mem_FPR(dst));
0 a61af66fc99e Initial load duke parents: diff changeset	11356 ins_pipe( fpu_mem_mem );
a61af66fc99e Initial load duke parents: diff changeset	11357 %}
a61af66fc99e Initial load duke parents: diff changeset	11358
a61af66fc99e Initial load duke parents: diff changeset	11359 // This instruction does not round to 24-bits
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11360 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11361 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	11362 match(Set dst (ConvI2F src));
a61af66fc99e Initial load duke parents: diff changeset	11363 format %{ "FILD $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11364 "FSTP $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	11365 opcode(0xDB, 0x0); /* DB /0 */
a61af66fc99e Initial load duke parents: diff changeset	11366 ins_encode( Push_Mem_I(src),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11367 Pop_Reg_FPR(dst));
0 a61af66fc99e Initial load duke parents: diff changeset	11368 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	11369 %}
a61af66fc99e Initial load duke parents: diff changeset	11370
a61af66fc99e Initial load duke parents: diff changeset	11371 // This instruction does not round to 24-bits
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11372 instruct convI2FPR_mem(regFPR dst, memory mem) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11373 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
a61af66fc99e Initial load duke parents: diff changeset	11374 match(Set dst (ConvI2F (LoadI mem)));
a61af66fc99e Initial load duke parents: diff changeset	11375 format %{ "FILD $mem\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11376 "FSTP $dst" %}
a61af66fc99e Initial load duke parents: diff changeset	11377 opcode(0xDB); /* DB /0 */
a61af66fc99e Initial load duke parents: diff changeset	11378 ins_encode( OpcP, RMopc_Mem(0x00,mem),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11379 Pop_Reg_FPR(dst));
0 a61af66fc99e Initial load duke parents: diff changeset	11380 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	11381 %}
a61af66fc99e Initial load duke parents: diff changeset	11382
a61af66fc99e Initial load duke parents: diff changeset	11383 // Convert an int to a float in xmm; no rounding step needed.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11384 instruct convI2F_reg(regF dst, rRegI src) %{
71 3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11385 predicate( UseSSE==1 \|\| UseSSE>=2 && !UseXmmI2F );
0 a61af66fc99e Initial load duke parents: diff changeset	11386 match(Set dst (ConvI2F src));
a61af66fc99e Initial load duke parents: diff changeset	11387 format %{ "CVTSI2SS $dst, $src" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11388 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11389 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11390 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11391 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11392 %}
a61af66fc99e Initial load duke parents: diff changeset	11393
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11394 instruct convXI2F_reg(regF dst, rRegI src)
71 3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11395 %{
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11396 predicate( UseSSE>=2 && UseXmmI2F );
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11397 match(Set dst (ConvI2F src));
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11398
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11399 format %{ "MOVD $dst,$src\n\t"
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11400 "CVTDQ2PS $dst,$dst\t# i2f" %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11401 ins_encode %{
304 dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories never parents: 235 diff changeset	11402 __ movdl($dst$$XMMRegister, $src$$Register);
71 3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11403 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11404 %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11405 ins_pipe(pipe_slow); // XXX
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11406 %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86 kvn parents: 0 diff changeset	11407
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11408 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11409 match(Set dst (ConvI2L src));
a61af66fc99e Initial load duke parents: diff changeset	11410 effect(KILL cr);
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	11411 ins_cost(375);
0 a61af66fc99e Initial load duke parents: diff changeset	11412 format %{ "MOV $dst.lo,$src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11413 "MOV $dst.hi,$src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11414 "SAR $dst.hi,31" %}
a61af66fc99e Initial load duke parents: diff changeset	11415 ins_encode(convert_int_long(dst,src));
a61af66fc99e Initial load duke parents: diff changeset	11416 ins_pipe( ialu_reg_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	11417 %}
a61af66fc99e Initial load duke parents: diff changeset	11418
a61af66fc99e Initial load duke parents: diff changeset	11419 // Zero-extend convert int to long
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11420 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11421 match(Set dst (AndL (ConvI2L src) mask) );
a61af66fc99e Initial load duke parents: diff changeset	11422 effect( KILL flags );
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	11423 ins_cost(250);
0 a61af66fc99e Initial load duke parents: diff changeset	11424 format %{ "MOV $dst.lo,$src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11425 "XOR $dst.hi,$dst.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	11426 opcode(0x33); // XOR
a61af66fc99e Initial load duke parents: diff changeset	11427 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
a61af66fc99e Initial load duke parents: diff changeset	11428 ins_pipe( ialu_reg_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	11429 %}
a61af66fc99e Initial load duke parents: diff changeset	11430
a61af66fc99e Initial load duke parents: diff changeset	11431 // Zero-extend long
a61af66fc99e Initial load duke parents: diff changeset	11432 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
a61af66fc99e Initial load duke parents: diff changeset	11433 match(Set dst (AndL src mask) );
a61af66fc99e Initial load duke parents: diff changeset	11434 effect( KILL flags );
624 337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class twisti parents: 622 diff changeset	11435 ins_cost(250);
0 a61af66fc99e Initial load duke parents: diff changeset	11436 format %{ "MOV $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11437 "XOR $dst.hi,$dst.hi\n\t" %}
a61af66fc99e Initial load duke parents: diff changeset	11438 opcode(0x33); // XOR
a61af66fc99e Initial load duke parents: diff changeset	11439 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
a61af66fc99e Initial load duke parents: diff changeset	11440 ins_pipe( ialu_reg_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	11441 %}
a61af66fc99e Initial load duke parents: diff changeset	11442
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11443 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11444 predicate (UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	11445 match(Set dst (ConvL2D src));
a61af66fc99e Initial load duke parents: diff changeset	11446 effect( KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	11447 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11448 "PUSH $src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11449 "FILD ST,[ESP + #0]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11450 "ADD ESP,8\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11451 "FSTP_D $dst\t# D-round" %}
a61af66fc99e Initial load duke parents: diff changeset	11452 opcode(0xDF, 0x5); /* DF /5 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11453 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11454 ins_pipe( pipe_slow );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11455 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11456
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11457 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11458 predicate (UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	11459 match(Set dst (ConvL2D src));
a61af66fc99e Initial load duke parents: diff changeset	11460 effect( KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	11461 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11462 "PUSH $src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11463 "FILD_D [ESP]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11464 "FSTP_D [ESP]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11465 "MOVSD $dst,[ESP]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11466 "ADD ESP,8" %}
a61af66fc99e Initial load duke parents: diff changeset	11467 opcode(0xDF, 0x5); /* DF /5 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11468 ins_encode(convert_long_double2(src), Push_ResultD(dst));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11469 ins_pipe( pipe_slow );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11470 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11471
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11472 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11473 predicate (UseSSE>=1);
a61af66fc99e Initial load duke parents: diff changeset	11474 match(Set dst (ConvL2F src));
a61af66fc99e Initial load duke parents: diff changeset	11475 effect( KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	11476 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11477 "PUSH $src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11478 "FILD_D [ESP]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11479 "FSTP_S [ESP]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11480 "MOVSS $dst,[ESP]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11481 "ADD ESP,8" %}
a61af66fc99e Initial load duke parents: diff changeset	11482 opcode(0xDF, 0x5); /* DF /5 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11483 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11484 ins_pipe( pipe_slow );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11485 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11486
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11487 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11488 match(Set dst (ConvL2F src));
a61af66fc99e Initial load duke parents: diff changeset	11489 effect( KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	11490 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11491 "PUSH $src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11492 "FILD ST,[ESP + #0]\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11493 "ADD ESP,8\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11494 "FSTP_S $dst\t# F-round" %}
a61af66fc99e Initial load duke parents: diff changeset	11495 opcode(0xDF, 0x5); /* DF /5 */
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11496 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
0 a61af66fc99e Initial load duke parents: diff changeset	11497 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11498 %}
a61af66fc99e Initial load duke parents: diff changeset	11499
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11500 instruct convL2I_reg( rRegI dst, eRegL src ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11501 match(Set dst (ConvL2I src));
a61af66fc99e Initial load duke parents: diff changeset	11502 effect( DEF dst, USE src );
a61af66fc99e Initial load duke parents: diff changeset	11503 format %{ "MOV $dst,$src.lo" %}
a61af66fc99e Initial load duke parents: diff changeset	11504 ins_encode(enc_CopyL_Lo(dst,src));
a61af66fc99e Initial load duke parents: diff changeset	11505 ins_pipe( ialu_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	11506 %}
a61af66fc99e Initial load duke parents: diff changeset	11507
a61af66fc99e Initial load duke parents: diff changeset	11508
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11509 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11510 match(Set dst (MoveF2I src));
a61af66fc99e Initial load duke parents: diff changeset	11511 effect( DEF dst, USE src );
a61af66fc99e Initial load duke parents: diff changeset	11512 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	11513 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11514 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11515 __ movl($dst$$Register, Address(rsp, $src$$disp));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11516 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11517 ins_pipe( ialu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	11518 %}
a61af66fc99e Initial load duke parents: diff changeset	11519
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11520 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11521 predicate(UseSSE==0);
a61af66fc99e Initial load duke parents: diff changeset	11522 match(Set dst (MoveF2I src));
a61af66fc99e Initial load duke parents: diff changeset	11523 effect( DEF dst, USE src );
a61af66fc99e Initial load duke parents: diff changeset	11524
a61af66fc99e Initial load duke parents: diff changeset	11525 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	11526 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11527 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
0 a61af66fc99e Initial load duke parents: diff changeset	11528 ins_pipe( fpu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	11529 %}
a61af66fc99e Initial load duke parents: diff changeset	11530
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11531 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11532 predicate(UseSSE>=1);
a61af66fc99e Initial load duke parents: diff changeset	11533 match(Set dst (MoveF2I src));
a61af66fc99e Initial load duke parents: diff changeset	11534 effect( DEF dst, USE src );
a61af66fc99e Initial load duke parents: diff changeset	11535
a61af66fc99e Initial load duke parents: diff changeset	11536 ins_cost(95);
a61af66fc99e Initial load duke parents: diff changeset	11537 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11538 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11539 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11540 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11541 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11542 %}
a61af66fc99e Initial load duke parents: diff changeset	11543
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11544 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11545 predicate(UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	11546 match(Set dst (MoveF2I src));
a61af66fc99e Initial load duke parents: diff changeset	11547 effect( DEF dst, USE src );
a61af66fc99e Initial load duke parents: diff changeset	11548 ins_cost(85);
a61af66fc99e Initial load duke parents: diff changeset	11549 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11550 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11551 __ movdl($dst$$Register, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11552 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11553 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11554 %}
a61af66fc99e Initial load duke parents: diff changeset	11555
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11556 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11557 match(Set dst (MoveI2F src));
a61af66fc99e Initial load duke parents: diff changeset	11558 effect( DEF dst, USE src );
a61af66fc99e Initial load duke parents: diff changeset	11559
a61af66fc99e Initial load duke parents: diff changeset	11560 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	11561 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11562 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11563 __ movl(Address(rsp, $dst$$disp), $src$$Register);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11564 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11565 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	11566 %}
a61af66fc99e Initial load duke parents: diff changeset	11567
a61af66fc99e Initial load duke parents: diff changeset	11568
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11569 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11570 predicate(UseSSE==0);
a61af66fc99e Initial load duke parents: diff changeset	11571 match(Set dst (MoveI2F src));
a61af66fc99e Initial load duke parents: diff changeset	11572 effect(DEF dst, USE src);
a61af66fc99e Initial load duke parents: diff changeset	11573
a61af66fc99e Initial load duke parents: diff changeset	11574 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	11575 format %{ "FLD_S $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11576 "FSTP $dst\t# MoveI2F_stack_reg" %}
a61af66fc99e Initial load duke parents: diff changeset	11577 opcode(0xD9); /* D9 /0, FLD m32real */
a61af66fc99e Initial load duke parents: diff changeset	11578 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11579 Pop_Reg_FPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	11580 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	11581 %}
a61af66fc99e Initial load duke parents: diff changeset	11582
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11583 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11584 predicate(UseSSE>=1);
a61af66fc99e Initial load duke parents: diff changeset	11585 match(Set dst (MoveI2F src));
a61af66fc99e Initial load duke parents: diff changeset	11586 effect( DEF dst, USE src );
a61af66fc99e Initial load duke parents: diff changeset	11587
a61af66fc99e Initial load duke parents: diff changeset	11588 ins_cost(95);
a61af66fc99e Initial load duke parents: diff changeset	11589 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11590 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11591 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11592 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11593 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11594 %}
a61af66fc99e Initial load duke parents: diff changeset	11595
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11596 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11597 predicate(UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	11598 match(Set dst (MoveI2F src));
a61af66fc99e Initial load duke parents: diff changeset	11599 effect( DEF dst, USE src );
a61af66fc99e Initial load duke parents: diff changeset	11600
a61af66fc99e Initial load duke parents: diff changeset	11601 ins_cost(85);
a61af66fc99e Initial load duke parents: diff changeset	11602 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11603 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11604 __ movdl($dst$$XMMRegister, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11605 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11606 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11607 %}
a61af66fc99e Initial load duke parents: diff changeset	11608
a61af66fc99e Initial load duke parents: diff changeset	11609 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
a61af66fc99e Initial load duke parents: diff changeset	11610 match(Set dst (MoveD2L src));
a61af66fc99e Initial load duke parents: diff changeset	11611 effect(DEF dst, USE src);
a61af66fc99e Initial load duke parents: diff changeset	11612
a61af66fc99e Initial load duke parents: diff changeset	11613 ins_cost(250);
a61af66fc99e Initial load duke parents: diff changeset	11614 format %{ "MOV $dst.lo,$src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11615 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
a61af66fc99e Initial load duke parents: diff changeset	11616 opcode(0x8B, 0x8B);
a61af66fc99e Initial load duke parents: diff changeset	11617 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
a61af66fc99e Initial load duke parents: diff changeset	11618 ins_pipe( ialu_mem_long_reg );
a61af66fc99e Initial load duke parents: diff changeset	11619 %}
a61af66fc99e Initial load duke parents: diff changeset	11620
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11621 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11622 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	11623 match(Set dst (MoveD2L src));
a61af66fc99e Initial load duke parents: diff changeset	11624 effect(DEF dst, USE src);
a61af66fc99e Initial load duke parents: diff changeset	11625
a61af66fc99e Initial load duke parents: diff changeset	11626 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	11627 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11628 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
0 a61af66fc99e Initial load duke parents: diff changeset	11629 ins_pipe( fpu_mem_reg );
a61af66fc99e Initial load duke parents: diff changeset	11630 %}
a61af66fc99e Initial load duke parents: diff changeset	11631
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11632 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11633 predicate(UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	11634 match(Set dst (MoveD2L src));
a61af66fc99e Initial load duke parents: diff changeset	11635 effect(DEF dst, USE src);
a61af66fc99e Initial load duke parents: diff changeset	11636 ins_cost(95);
a61af66fc99e Initial load duke parents: diff changeset	11637 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11638 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11639 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11640 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11641 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11642 %}
a61af66fc99e Initial load duke parents: diff changeset	11643
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11644 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11645 predicate(UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	11646 match(Set dst (MoveD2L src));
a61af66fc99e Initial load duke parents: diff changeset	11647 effect(DEF dst, USE src, TEMP tmp);
a61af66fc99e Initial load duke parents: diff changeset	11648 ins_cost(85);
a61af66fc99e Initial load duke parents: diff changeset	11649 format %{ "MOVD $dst.lo,$src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11650 "PSHUFLW $tmp,$src,0x4E\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11651 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11652 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11653 __ movdl($dst$$Register, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11654 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11655 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11656 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11657 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11658 %}
a61af66fc99e Initial load duke parents: diff changeset	11659
a61af66fc99e Initial load duke parents: diff changeset	11660 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
a61af66fc99e Initial load duke parents: diff changeset	11661 match(Set dst (MoveL2D src));
a61af66fc99e Initial load duke parents: diff changeset	11662 effect(DEF dst, USE src);
a61af66fc99e Initial load duke parents: diff changeset	11663
a61af66fc99e Initial load duke parents: diff changeset	11664 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	11665 format %{ "MOV $dst,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11666 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
a61af66fc99e Initial load duke parents: diff changeset	11667 opcode(0x89, 0x89);
a61af66fc99e Initial load duke parents: diff changeset	11668 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
a61af66fc99e Initial load duke parents: diff changeset	11669 ins_pipe( ialu_mem_long_reg );
a61af66fc99e Initial load duke parents: diff changeset	11670 %}
a61af66fc99e Initial load duke parents: diff changeset	11671
a61af66fc99e Initial load duke parents: diff changeset	11672
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11673 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11674 predicate(UseSSE<=1);
a61af66fc99e Initial load duke parents: diff changeset	11675 match(Set dst (MoveL2D src));
a61af66fc99e Initial load duke parents: diff changeset	11676 effect(DEF dst, USE src);
a61af66fc99e Initial load duke parents: diff changeset	11677 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	11678
a61af66fc99e Initial load duke parents: diff changeset	11679 format %{ "FLD_D $src\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11680 "FSTP $dst\t# MoveL2D_stack_reg" %}
a61af66fc99e Initial load duke parents: diff changeset	11681 opcode(0xDD); /* DD /0, FLD m64real */
a61af66fc99e Initial load duke parents: diff changeset	11682 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11683 Pop_Reg_DPR(dst) );
0 a61af66fc99e Initial load duke parents: diff changeset	11684 ins_pipe( fpu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	11685 %}
a61af66fc99e Initial load duke parents: diff changeset	11686
a61af66fc99e Initial load duke parents: diff changeset	11687
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11688 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11689 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
a61af66fc99e Initial load duke parents: diff changeset	11690 match(Set dst (MoveL2D src));
a61af66fc99e Initial load duke parents: diff changeset	11691 effect(DEF dst, USE src);
a61af66fc99e Initial load duke parents: diff changeset	11692
a61af66fc99e Initial load duke parents: diff changeset	11693 ins_cost(95);
a61af66fc99e Initial load duke parents: diff changeset	11694 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11695 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11696 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11697 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11698 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11699 %}
a61af66fc99e Initial load duke parents: diff changeset	11700
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11701 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11702 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
a61af66fc99e Initial load duke parents: diff changeset	11703 match(Set dst (MoveL2D src));
a61af66fc99e Initial load duke parents: diff changeset	11704 effect(DEF dst, USE src);
a61af66fc99e Initial load duke parents: diff changeset	11705
a61af66fc99e Initial load duke parents: diff changeset	11706 ins_cost(95);
a61af66fc99e Initial load duke parents: diff changeset	11707 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11708 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11709 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11710 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11711 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11712 %}
a61af66fc99e Initial load duke parents: diff changeset	11713
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11714 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11715 predicate(UseSSE>=2);
a61af66fc99e Initial load duke parents: diff changeset	11716 match(Set dst (MoveL2D src));
a61af66fc99e Initial load duke parents: diff changeset	11717 effect(TEMP dst, USE src, TEMP tmp);
a61af66fc99e Initial load duke parents: diff changeset	11718 ins_cost(85);
a61af66fc99e Initial load duke parents: diff changeset	11719 format %{ "MOVD $dst,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11720 "MOVD $tmp,$src.hi\n\t"
a61af66fc99e Initial load duke parents: diff changeset	11721 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
4759 127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11722 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11723 __ movdl($dst$$XMMRegister, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11724 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11725 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions kvn parents: 4121 diff changeset	11726 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11727 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11728 %}
a61af66fc99e Initial load duke parents: diff changeset	11729
a61af66fc99e Initial load duke parents: diff changeset	11730
a61af66fc99e Initial load duke parents: diff changeset	11731 // =======================================================================
a61af66fc99e Initial load duke parents: diff changeset	11732 // fast clearing of an array
a61af66fc99e Initial load duke parents: diff changeset	11733 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
7474 00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11734 predicate(!UseFastStosb);
0 a61af66fc99e Initial load duke parents: diff changeset	11735 match(Set dummy (ClearArray cnt base));
a61af66fc99e Initial load duke parents: diff changeset	11736 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
7474 00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11737 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11738 "SHL ECX,1\t# Convert doublewords to words\n\t"
0 a61af66fc99e Initial load duke parents: diff changeset	11739 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
7474 00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11740 ins_encode %{
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11741 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11742 %}
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11743 ins_pipe( pipe_slow );
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11744 %}
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11745
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11746 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11747 predicate(UseFastStosb);
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11748 match(Set dummy (ClearArray cnt base));
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11749 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11750 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11751 "SHL ECX,3\t# Convert doublewords to bytes\n\t"
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11752 "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11753 ins_encode %{
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11754 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing kvn parents: 6853 diff changeset	11755 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11756 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11757 %}
a61af66fc99e Initial load duke parents: diff changeset	11758
2262 6bbaedb03534 7016474: string compare intrinsic improvements never parents: 2008 diff changeset	11759 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11760 eAXRegI result, regD tmp1, eFlagsReg cr) %{
986 62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11761 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
2262 6bbaedb03534 7016474: string compare intrinsic improvements never parents: 2008 diff changeset	11762 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
6bbaedb03534 7016474: string compare intrinsic improvements never parents: 2008 diff changeset	11763
6bbaedb03534 7016474: string compare intrinsic improvements never parents: 2008 diff changeset	11764 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
986 62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11765 ins_encode %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11766 __ string_compare($str1$$Register, $str2$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11767 $cnt1$$Register, $cnt2$$Register, $result$$Register,
2262 6bbaedb03534 7016474: string compare intrinsic improvements never parents: 2008 diff changeset	11768 $tmp1$$XMMRegister);
986 62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11769 %}
681 fbde8ec322d0 6761600: Use sse 4.2 in intrinsics cfang parents: 671 diff changeset	11770 ins_pipe( pipe_slow );
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics cfang parents: 671 diff changeset	11771 %}
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics cfang parents: 671 diff changeset	11772
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics cfang parents: 671 diff changeset	11773 // fast string equals
986 62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11774 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11775 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
986 62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11776 match(Set result (StrEquals (Binary str1 str2) cnt));
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11777 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11778
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11779 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11780 ins_encode %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11781 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11782 $cnt$$Register, $result$$Register, $tmp3$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11783 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11784 %}
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11785 ins_pipe( pipe_slow );
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11786 %}
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11787
2320 41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11788 // fast search of substring with known size.
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11789 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11790 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
2320 41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11791 predicate(UseSSE42Intrinsics);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11792 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11793 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11794
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11795 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11796 ins_encode %{
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11797 int icnt2 = (int)$int_cnt2$$constant;
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11798 if (icnt2 >= 8) {
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11799 // IndexOf for constant substrings with size >= 8 elements
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11800 // which don't need to be loaded through stack.
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11801 __ string_indexofC8($str1$$Register, $str2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11802 $cnt1$$Register, $cnt2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11803 icnt2, $result$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11804 $vec$$XMMRegister, $tmp$$Register);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11805 } else {
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11806 // Small strings are loaded through stack if they cross page boundary.
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11807 __ string_indexof($str1$$Register, $str2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11808 $cnt1$$Register, $cnt2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11809 icnt2, $result$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11810 $vec$$XMMRegister, $tmp$$Register);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11811 }
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11812 %}
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11813 ins_pipe( pipe_slow );
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11814 %}
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11815
986 62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11816 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11817 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
681 fbde8ec322d0 6761600: Use sse 4.2 in intrinsics cfang parents: 671 diff changeset	11818 predicate(UseSSE42Intrinsics);
986 62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11819 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
2320 41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11820 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11821
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11822 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
986 62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11823 ins_encode %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11824 __ string_indexof($str1$$Register, $str2$$Register,
2320 41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11825 $cnt1$$Register, $cnt2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11826 (-1), $result$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space kvn parents: 2262 diff changeset	11827 $vec$$XMMRegister, $tmp$$Register);
986 62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11828 %}
0 a61af66fc99e Initial load duke parents: diff changeset	11829 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	11830 %}
a61af66fc99e Initial load duke parents: diff changeset	11831
169 9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals rasbold parents: 113 diff changeset	11832 // fast array equals
986 62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11833 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	11834 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
986 62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11835 %{
169 9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals rasbold parents: 113 diff changeset	11836 match(Set result (AryEq ary1 ary2));
681 fbde8ec322d0 6761600: Use sse 4.2 in intrinsics cfang parents: 671 diff changeset	11837 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
169 9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals rasbold parents: 113 diff changeset	11838 //ins_cost(300);
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals rasbold parents: 113 diff changeset	11839
986 62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11840 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11841 ins_encode %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11842 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11843 $tmp3$$Register, $result$$Register, $tmp4$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11844 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement kvn parents: 824 diff changeset	11845 %}
169 9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals rasbold parents: 113 diff changeset	11846 ins_pipe( pipe_slow );
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals rasbold parents: 113 diff changeset	11847 %}
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals rasbold parents: 113 diff changeset	11848
7637 b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86 kvn parents: 7474 diff changeset	11849 // encode char[] to byte[] in ISO_8859_1
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86 kvn parents: 7474 diff changeset	11850 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86 kvn parents: 7474 diff changeset	11851 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86 kvn parents: 7474 diff changeset	11852 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86 kvn parents: 7474 diff changeset	11853 match(Set result (EncodeISOArray src (Binary dst len)));
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86 kvn parents: 7474 diff changeset	11854 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86 kvn parents: 7474 diff changeset	11855
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86 kvn parents: 7474 diff changeset	11856 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86 kvn parents: 7474 diff changeset	11857 ins_encode %{
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86 kvn parents: 7474 diff changeset	11858 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86 kvn parents: 7474 diff changeset	11859 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86 kvn parents: 7474 diff changeset	11860 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86 kvn parents: 7474 diff changeset	11861 %}
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86 kvn parents: 7474 diff changeset	11862 ins_pipe( pipe_slow );
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86 kvn parents: 7474 diff changeset	11863 %}
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86 kvn parents: 7474 diff changeset	11864
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86 kvn parents: 7474 diff changeset	11865
0 a61af66fc99e Initial load duke parents: diff changeset	11866 //----------Control Flow Instructions------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	11867 // Signed compare Instructions
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11868 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11869 match(Set cr (CmpI op1 op2));
a61af66fc99e Initial load duke parents: diff changeset	11870 effect( DEF cr, USE op1, USE op2 );
a61af66fc99e Initial load duke parents: diff changeset	11871 format %{ "CMP $op1,$op2" %}
a61af66fc99e Initial load duke parents: diff changeset	11872 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load duke parents: diff changeset	11873 ins_encode( OpcP, RegReg( op1, op2) );
a61af66fc99e Initial load duke parents: diff changeset	11874 ins_pipe( ialu_cr_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	11875 %}
a61af66fc99e Initial load duke parents: diff changeset	11876
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11877 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11878 match(Set cr (CmpI op1 op2));
a61af66fc99e Initial load duke parents: diff changeset	11879 effect( DEF cr, USE op1 );
a61af66fc99e Initial load duke parents: diff changeset	11880 format %{ "CMP $op1,$op2" %}
a61af66fc99e Initial load duke parents: diff changeset	11881 opcode(0x81,0x07); /* Opcode 81 /7 */
a61af66fc99e Initial load duke parents: diff changeset	11882 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
a61af66fc99e Initial load duke parents: diff changeset	11883 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
a61af66fc99e Initial load duke parents: diff changeset	11884 ins_pipe( ialu_cr_reg_imm );
a61af66fc99e Initial load duke parents: diff changeset	11885 %}
a61af66fc99e Initial load duke parents: diff changeset	11886
a61af66fc99e Initial load duke parents: diff changeset	11887 // Cisc-spilled version of cmpI_eReg
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11888 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11889 match(Set cr (CmpI op1 (LoadI op2)));
a61af66fc99e Initial load duke parents: diff changeset	11890
a61af66fc99e Initial load duke parents: diff changeset	11891 format %{ "CMP $op1,$op2" %}
a61af66fc99e Initial load duke parents: diff changeset	11892 ins_cost(500);
a61af66fc99e Initial load duke parents: diff changeset	11893 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load duke parents: diff changeset	11894 ins_encode( OpcP, RegMem( op1, op2) );
a61af66fc99e Initial load duke parents: diff changeset	11895 ins_pipe( ialu_cr_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	11896 %}
a61af66fc99e Initial load duke parents: diff changeset	11897
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11898 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11899 match(Set cr (CmpI src zero));
a61af66fc99e Initial load duke parents: diff changeset	11900 effect( DEF cr, USE src );
a61af66fc99e Initial load duke parents: diff changeset	11901
a61af66fc99e Initial load duke parents: diff changeset	11902 format %{ "TEST $src,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	11903 opcode(0x85);
a61af66fc99e Initial load duke parents: diff changeset	11904 ins_encode( OpcP, RegReg( src, src ) );
a61af66fc99e Initial load duke parents: diff changeset	11905 ins_pipe( ialu_cr_reg_imm );
a61af66fc99e Initial load duke parents: diff changeset	11906 %}
a61af66fc99e Initial load duke parents: diff changeset	11907
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11908 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11909 match(Set cr (CmpI (AndI src con) zero));
a61af66fc99e Initial load duke parents: diff changeset	11910
a61af66fc99e Initial load duke parents: diff changeset	11911 format %{ "TEST $src,$con" %}
a61af66fc99e Initial load duke parents: diff changeset	11912 opcode(0xF7,0x00);
a61af66fc99e Initial load duke parents: diff changeset	11913 ins_encode( OpcP, RegOpc(src), Con32(con) );
a61af66fc99e Initial load duke parents: diff changeset	11914 ins_pipe( ialu_cr_reg_imm );
a61af66fc99e Initial load duke parents: diff changeset	11915 %}
a61af66fc99e Initial load duke parents: diff changeset	11916
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11917 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11918 match(Set cr (CmpI (AndI src mem) zero));
a61af66fc99e Initial load duke parents: diff changeset	11919
a61af66fc99e Initial load duke parents: diff changeset	11920 format %{ "TEST $src,$mem" %}
a61af66fc99e Initial load duke parents: diff changeset	11921 opcode(0x85);
a61af66fc99e Initial load duke parents: diff changeset	11922 ins_encode( OpcP, RegMem( src, mem ) );
a61af66fc99e Initial load duke parents: diff changeset	11923 ins_pipe( ialu_cr_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	11924 %}
a61af66fc99e Initial load duke parents: diff changeset	11925
a61af66fc99e Initial load duke parents: diff changeset	11926 // Unsigned compare Instructions; really, same as signed except they
a61af66fc99e Initial load duke parents: diff changeset	11927 // produce an eFlagsRegU instead of eFlagsReg.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11928 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11929 match(Set cr (CmpU op1 op2));
a61af66fc99e Initial load duke parents: diff changeset	11930
a61af66fc99e Initial load duke parents: diff changeset	11931 format %{ "CMPu $op1,$op2" %}
a61af66fc99e Initial load duke parents: diff changeset	11932 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load duke parents: diff changeset	11933 ins_encode( OpcP, RegReg( op1, op2) );
a61af66fc99e Initial load duke parents: diff changeset	11934 ins_pipe( ialu_cr_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	11935 %}
a61af66fc99e Initial load duke parents: diff changeset	11936
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11937 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11938 match(Set cr (CmpU op1 op2));
a61af66fc99e Initial load duke parents: diff changeset	11939
a61af66fc99e Initial load duke parents: diff changeset	11940 format %{ "CMPu $op1,$op2" %}
a61af66fc99e Initial load duke parents: diff changeset	11941 opcode(0x81,0x07); /* Opcode 81 /7 */
a61af66fc99e Initial load duke parents: diff changeset	11942 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
a61af66fc99e Initial load duke parents: diff changeset	11943 ins_pipe( ialu_cr_reg_imm );
a61af66fc99e Initial load duke parents: diff changeset	11944 %}
a61af66fc99e Initial load duke parents: diff changeset	11945
a61af66fc99e Initial load duke parents: diff changeset	11946 // // Cisc-spilled version of cmpU_eReg
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11947 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11948 match(Set cr (CmpU op1 (LoadI op2)));
a61af66fc99e Initial load duke parents: diff changeset	11949
a61af66fc99e Initial load duke parents: diff changeset	11950 format %{ "CMPu $op1,$op2" %}
a61af66fc99e Initial load duke parents: diff changeset	11951 ins_cost(500);
a61af66fc99e Initial load duke parents: diff changeset	11952 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load duke parents: diff changeset	11953 ins_encode( OpcP, RegMem( op1, op2) );
a61af66fc99e Initial load duke parents: diff changeset	11954 ins_pipe( ialu_cr_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	11955 %}
a61af66fc99e Initial load duke parents: diff changeset	11956
a61af66fc99e Initial load duke parents: diff changeset	11957 // // Cisc-spilled version of cmpU_eReg
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11958 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11959 // match(Set cr (CmpU (LoadI op1) op2));
a61af66fc99e Initial load duke parents: diff changeset	11960 //
a61af66fc99e Initial load duke parents: diff changeset	11961 // format %{ "CMPu $op1,$op2" %}
a61af66fc99e Initial load duke parents: diff changeset	11962 // ins_cost(500);
a61af66fc99e Initial load duke parents: diff changeset	11963 // opcode(0x39); /* Opcode 39 /r */
a61af66fc99e Initial load duke parents: diff changeset	11964 // ins_encode( OpcP, RegMem( op1, op2) );
a61af66fc99e Initial load duke parents: diff changeset	11965 //%}
a61af66fc99e Initial load duke parents: diff changeset	11966
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	11967 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	11968 match(Set cr (CmpU src zero));
a61af66fc99e Initial load duke parents: diff changeset	11969
a61af66fc99e Initial load duke parents: diff changeset	11970 format %{ "TESTu $src,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	11971 opcode(0x85);
a61af66fc99e Initial load duke parents: diff changeset	11972 ins_encode( OpcP, RegReg( src, src ) );
a61af66fc99e Initial load duke parents: diff changeset	11973 ins_pipe( ialu_cr_reg_imm );
a61af66fc99e Initial load duke parents: diff changeset	11974 %}
a61af66fc99e Initial load duke parents: diff changeset	11975
a61af66fc99e Initial load duke parents: diff changeset	11976 // Unsigned pointer compare Instructions
a61af66fc99e Initial load duke parents: diff changeset	11977 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
a61af66fc99e Initial load duke parents: diff changeset	11978 match(Set cr (CmpP op1 op2));
a61af66fc99e Initial load duke parents: diff changeset	11979
a61af66fc99e Initial load duke parents: diff changeset	11980 format %{ "CMPu $op1,$op2" %}
a61af66fc99e Initial load duke parents: diff changeset	11981 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load duke parents: diff changeset	11982 ins_encode( OpcP, RegReg( op1, op2) );
a61af66fc99e Initial load duke parents: diff changeset	11983 ins_pipe( ialu_cr_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	11984 %}
a61af66fc99e Initial load duke parents: diff changeset	11985
a61af66fc99e Initial load duke parents: diff changeset	11986 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
a61af66fc99e Initial load duke parents: diff changeset	11987 match(Set cr (CmpP op1 op2));
a61af66fc99e Initial load duke parents: diff changeset	11988
a61af66fc99e Initial load duke parents: diff changeset	11989 format %{ "CMPu $op1,$op2" %}
a61af66fc99e Initial load duke parents: diff changeset	11990 opcode(0x81,0x07); /* Opcode 81 /7 */
a61af66fc99e Initial load duke parents: diff changeset	11991 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
a61af66fc99e Initial load duke parents: diff changeset	11992 ins_pipe( ialu_cr_reg_imm );
a61af66fc99e Initial load duke parents: diff changeset	11993 %}
a61af66fc99e Initial load duke parents: diff changeset	11994
a61af66fc99e Initial load duke parents: diff changeset	11995 // // Cisc-spilled version of cmpP_eReg
a61af66fc99e Initial load duke parents: diff changeset	11996 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
a61af66fc99e Initial load duke parents: diff changeset	11997 match(Set cr (CmpP op1 (LoadP op2)));
a61af66fc99e Initial load duke parents: diff changeset	11998
a61af66fc99e Initial load duke parents: diff changeset	11999 format %{ "CMPu $op1,$op2" %}
a61af66fc99e Initial load duke parents: diff changeset	12000 ins_cost(500);
a61af66fc99e Initial load duke parents: diff changeset	12001 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load duke parents: diff changeset	12002 ins_encode( OpcP, RegMem( op1, op2) );
a61af66fc99e Initial load duke parents: diff changeset	12003 ins_pipe( ialu_cr_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	12004 %}
a61af66fc99e Initial load duke parents: diff changeset	12005
a61af66fc99e Initial load duke parents: diff changeset	12006 // // Cisc-spilled version of cmpP_eReg
a61af66fc99e Initial load duke parents: diff changeset	12007 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
a61af66fc99e Initial load duke parents: diff changeset	12008 // match(Set cr (CmpP (LoadP op1) op2));
a61af66fc99e Initial load duke parents: diff changeset	12009 //
a61af66fc99e Initial load duke parents: diff changeset	12010 // format %{ "CMPu $op1,$op2" %}
a61af66fc99e Initial load duke parents: diff changeset	12011 // ins_cost(500);
a61af66fc99e Initial load duke parents: diff changeset	12012 // opcode(0x39); /* Opcode 39 /r */
a61af66fc99e Initial load duke parents: diff changeset	12013 // ins_encode( OpcP, RegMem( op1, op2) );
a61af66fc99e Initial load duke parents: diff changeset	12014 //%}
a61af66fc99e Initial load duke parents: diff changeset	12015
a61af66fc99e Initial load duke parents: diff changeset	12016 // Compare raw pointer (used in out-of-heap check).
a61af66fc99e Initial load duke parents: diff changeset	12017 // Only works because non-oop pointers must be raw pointers
a61af66fc99e Initial load duke parents: diff changeset	12018 // and raw pointers have no anti-dependencies.
a61af66fc99e Initial load duke parents: diff changeset	12019 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
6725 da91efe96a93 6964458: Reimplement class meta-data storage to use native memory coleenp parents: 6614 diff changeset	12020 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
0 a61af66fc99e Initial load duke parents: diff changeset	12021 match(Set cr (CmpP op1 (LoadP op2)));
a61af66fc99e Initial load duke parents: diff changeset	12022
a61af66fc99e Initial load duke parents: diff changeset	12023 format %{ "CMPu $op1,$op2" %}
a61af66fc99e Initial load duke parents: diff changeset	12024 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load duke parents: diff changeset	12025 ins_encode( OpcP, RegMem( op1, op2) );
a61af66fc99e Initial load duke parents: diff changeset	12026 ins_pipe( ialu_cr_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	12027 %}
a61af66fc99e Initial load duke parents: diff changeset	12028
a61af66fc99e Initial load duke parents: diff changeset	12029 //
a61af66fc99e Initial load duke parents: diff changeset	12030 // This will generate a signed flags result. This should be ok
a61af66fc99e Initial load duke parents: diff changeset	12031 // since any compare to a zero should be eq/neq.
a61af66fc99e Initial load duke parents: diff changeset	12032 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
a61af66fc99e Initial load duke parents: diff changeset	12033 match(Set cr (CmpP src zero));
a61af66fc99e Initial load duke parents: diff changeset	12034
a61af66fc99e Initial load duke parents: diff changeset	12035 format %{ "TEST $src,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	12036 opcode(0x85);
a61af66fc99e Initial load duke parents: diff changeset	12037 ins_encode( OpcP, RegReg( src, src ) );
a61af66fc99e Initial load duke parents: diff changeset	12038 ins_pipe( ialu_cr_reg_imm );
a61af66fc99e Initial load duke parents: diff changeset	12039 %}
a61af66fc99e Initial load duke parents: diff changeset	12040
a61af66fc99e Initial load duke parents: diff changeset	12041 // Cisc-spilled version of testP_reg
a61af66fc99e Initial load duke parents: diff changeset	12042 // This will generate a signed flags result. This should be ok
a61af66fc99e Initial load duke parents: diff changeset	12043 // since any compare to a zero should be eq/neq.
a61af66fc99e Initial load duke parents: diff changeset	12044 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
a61af66fc99e Initial load duke parents: diff changeset	12045 match(Set cr (CmpP (LoadP op) zero));
a61af66fc99e Initial load duke parents: diff changeset	12046
a61af66fc99e Initial load duke parents: diff changeset	12047 format %{ "TEST $op,0xFFFFFFFF" %}
a61af66fc99e Initial load duke parents: diff changeset	12048 ins_cost(500);
a61af66fc99e Initial load duke parents: diff changeset	12049 opcode(0xF7); /* Opcode F7 /0 */
a61af66fc99e Initial load duke parents: diff changeset	12050 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
a61af66fc99e Initial load duke parents: diff changeset	12051 ins_pipe( ialu_cr_reg_imm );
a61af66fc99e Initial load duke parents: diff changeset	12052 %}
a61af66fc99e Initial load duke parents: diff changeset	12053
a61af66fc99e Initial load duke parents: diff changeset	12054 // Yanked all unsigned pointer compare operations.
a61af66fc99e Initial load duke parents: diff changeset	12055 // Pointer compares are done with CmpP which is already unsigned.
a61af66fc99e Initial load duke parents: diff changeset	12056
a61af66fc99e Initial load duke parents: diff changeset	12057 //----------Max and Min--------------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	12058 // Min Instructions
a61af66fc99e Initial load duke parents: diff changeset	12059 ////
a61af66fc99e Initial load duke parents: diff changeset	12060 // *** Min and Max using the conditional move are slower than the
a61af66fc99e Initial load duke parents: diff changeset	12061 // *** branch version on a Pentium III.
a61af66fc99e Initial load duke parents: diff changeset	12062 // // Conditional move for min
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	12063 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12064 // effect( USE_DEF op2, USE op1, USE cr );
a61af66fc99e Initial load duke parents: diff changeset	12065 // format %{ "CMOVlt $op2,$op1\t! min" %}
a61af66fc99e Initial load duke parents: diff changeset	12066 // opcode(0x4C,0x0F);
a61af66fc99e Initial load duke parents: diff changeset	12067 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
a61af66fc99e Initial load duke parents: diff changeset	12068 // ins_pipe( pipe_cmov_reg );
a61af66fc99e Initial load duke parents: diff changeset	12069 //%}
a61af66fc99e Initial load duke parents: diff changeset	12070 //
a61af66fc99e Initial load duke parents: diff changeset	12071 //// Min Register with Register (P6 version)
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	12072 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12073 // predicate(VM_Version::supports_cmov() );
a61af66fc99e Initial load duke parents: diff changeset	12074 // match(Set op2 (MinI op1 op2));
a61af66fc99e Initial load duke parents: diff changeset	12075 // ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12076 // expand %{
a61af66fc99e Initial load duke parents: diff changeset	12077 // eFlagsReg cr;
a61af66fc99e Initial load duke parents: diff changeset	12078 // compI_eReg(cr,op1,op2);
a61af66fc99e Initial load duke parents: diff changeset	12079 // cmovI_reg_lt(op2,op1,cr);
a61af66fc99e Initial load duke parents: diff changeset	12080 // %}
a61af66fc99e Initial load duke parents: diff changeset	12081 //%}
a61af66fc99e Initial load duke parents: diff changeset	12082
a61af66fc99e Initial load duke parents: diff changeset	12083 // Min Register with Register (generic version)
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	12084 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12085 match(Set dst (MinI dst src));
a61af66fc99e Initial load duke parents: diff changeset	12086 effect(KILL flags);
a61af66fc99e Initial load duke parents: diff changeset	12087 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	12088
a61af66fc99e Initial load duke parents: diff changeset	12089 format %{ "MIN $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	12090 opcode(0xCC);
a61af66fc99e Initial load duke parents: diff changeset	12091 ins_encode( min_enc(dst,src) );
a61af66fc99e Initial load duke parents: diff changeset	12092 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	12093 %}
a61af66fc99e Initial load duke parents: diff changeset	12094
a61af66fc99e Initial load duke parents: diff changeset	12095 // Max Register with Register
a61af66fc99e Initial load duke parents: diff changeset	12096 // *** Min and Max using the conditional move are slower than the
a61af66fc99e Initial load duke parents: diff changeset	12097 // *** branch version on a Pentium III.
a61af66fc99e Initial load duke parents: diff changeset	12098 // // Conditional move for max
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	12099 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12100 // effect( USE_DEF op2, USE op1, USE cr );
a61af66fc99e Initial load duke parents: diff changeset	12101 // format %{ "CMOVgt $op2,$op1\t! max" %}
a61af66fc99e Initial load duke parents: diff changeset	12102 // opcode(0x4F,0x0F);
a61af66fc99e Initial load duke parents: diff changeset	12103 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
a61af66fc99e Initial load duke parents: diff changeset	12104 // ins_pipe( pipe_cmov_reg );
a61af66fc99e Initial load duke parents: diff changeset	12105 //%}
a61af66fc99e Initial load duke parents: diff changeset	12106 //
a61af66fc99e Initial load duke parents: diff changeset	12107 // // Max Register with Register (P6 version)
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	12108 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12109 // predicate(VM_Version::supports_cmov() );
a61af66fc99e Initial load duke parents: diff changeset	12110 // match(Set op2 (MaxI op1 op2));
a61af66fc99e Initial load duke parents: diff changeset	12111 // ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12112 // expand %{
a61af66fc99e Initial load duke parents: diff changeset	12113 // eFlagsReg cr;
a61af66fc99e Initial load duke parents: diff changeset	12114 // compI_eReg(cr,op1,op2);
a61af66fc99e Initial load duke parents: diff changeset	12115 // cmovI_reg_gt(op2,op1,cr);
a61af66fc99e Initial load duke parents: diff changeset	12116 // %}
a61af66fc99e Initial load duke parents: diff changeset	12117 //%}
a61af66fc99e Initial load duke parents: diff changeset	12118
a61af66fc99e Initial load duke parents: diff changeset	12119 // Max Register with Register (generic version)
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	12120 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12121 match(Set dst (MaxI dst src));
a61af66fc99e Initial load duke parents: diff changeset	12122 effect(KILL flags);
a61af66fc99e Initial load duke parents: diff changeset	12123 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	12124
a61af66fc99e Initial load duke parents: diff changeset	12125 format %{ "MAX $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	12126 opcode(0xCC);
a61af66fc99e Initial load duke parents: diff changeset	12127 ins_encode( max_enc(dst,src) );
a61af66fc99e Initial load duke parents: diff changeset	12128 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	12129 %}
a61af66fc99e Initial load duke parents: diff changeset	12130
a61af66fc99e Initial load duke parents: diff changeset	12131 // ============================================================================
3345 bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12132 // Counted Loop limit node which represents exact final iterator value.
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12133 // Note: the resulting value should fit into integer range since
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12134 // counted loops have limit check on overflow.
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12135 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12136 match(Set limit (LoopLimit (Binary init limit) stride));
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12137 effect(TEMP limit_hi, TEMP tmp, KILL flags);
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12138 ins_cost(300);
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12139
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12140 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12141 ins_encode %{
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12142 int strd = (int)$stride$$constant;
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12143 assert(strd != 1 && strd != -1, "sanity");
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12144 int m1 = (strd > 0) ? 1 : -1;
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12145 // Convert limit to long (EAX:EDX)
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12146 __ cdql();
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12147 // Convert init to long (init:tmp)
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12148 __ movl($tmp$$Register, $init$$Register);
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12149 __ sarl($tmp$$Register, 31);
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12150 // $limit - $init
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12151 __ subl($limit$$Register, $init$$Register);
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12152 __ sbbl($limit_hi$$Register, $tmp$$Register);
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12153 // + ($stride - 1)
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12154 if (strd > 0) {
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12155 __ addl($limit$$Register, (strd - 1));
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12156 __ adcl($limit_hi$$Register, 0);
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12157 __ movl($tmp$$Register, strd);
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12158 } else {
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12159 __ addl($limit$$Register, (strd + 1));
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12160 __ adcl($limit_hi$$Register, -1);
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12161 __ lneg($limit_hi$$Register, $limit$$Register);
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12162 __ movl($tmp$$Register, -strd);
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12163 }
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12164 // signed devision: (EAX:EDX) / pos_stride
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12165 __ idivl($tmp$$Register);
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12166 if (strd < 0) {
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12167 // restore sign
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12168 __ negl($tmp$$Register);
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12169 }
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12170 // (EAX) * stride
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12171 __ mull($tmp$$Register);
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12172 // + init (ignore upper bits)
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12173 __ addl($limit$$Register, $init$$Register);
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12174 %}
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12175 ins_pipe( pipe_slow );
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12176 %}
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12177
bad7ecd0b6ed 5091921: Sign flip issues in loop optimizer kvn parents: 2479 diff changeset	12178 // ============================================================================
0 a61af66fc99e Initial load duke parents: diff changeset	12179 // Branch Instructions
a61af66fc99e Initial load duke parents: diff changeset	12180 // Jump Table
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	12181 instruct jumpXtnd(rRegI switch_val) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12182 match(Jump switch_val);
a61af66fc99e Initial load duke parents: diff changeset	12183 ins_cost(350);
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	12184 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	12185 ins_encode %{
0 a61af66fc99e Initial load duke parents: diff changeset	12186 // Jump to Address(table_base + switch_reg)
a61af66fc99e Initial load duke parents: diff changeset	12187 Address index(noreg, $switch_val$$Register, Address::times_1);
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1920 diff changeset	12188 __ jump(ArrayAddress($constantaddress, index));
0 a61af66fc99e Initial load duke parents: diff changeset	12189 %}
a61af66fc99e Initial load duke parents: diff changeset	12190 ins_pipe(pipe_jmp);
a61af66fc99e Initial load duke parents: diff changeset	12191 %}
a61af66fc99e Initial load duke parents: diff changeset	12192
a61af66fc99e Initial load duke parents: diff changeset	12193 // Jump Direct - Label defines a relative address from JMP+1
a61af66fc99e Initial load duke parents: diff changeset	12194 instruct jmpDir(label labl) %{
a61af66fc99e Initial load duke parents: diff changeset	12195 match(Goto);
a61af66fc99e Initial load duke parents: diff changeset	12196 effect(USE labl);
a61af66fc99e Initial load duke parents: diff changeset	12197
a61af66fc99e Initial load duke parents: diff changeset	12198 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	12199 format %{ "JMP $labl" %}
a61af66fc99e Initial load duke parents: diff changeset	12200 size(5);
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12201 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12202 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12203 __ jmp(*L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12204 %}
0 a61af66fc99e Initial load duke parents: diff changeset	12205 ins_pipe( pipe_jmp );
a61af66fc99e Initial load duke parents: diff changeset	12206 %}
a61af66fc99e Initial load duke parents: diff changeset	12207
a61af66fc99e Initial load duke parents: diff changeset	12208 // Jump Direct Conditional - Label defines a relative address from Jcc+1
a61af66fc99e Initial load duke parents: diff changeset	12209 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
a61af66fc99e Initial load duke parents: diff changeset	12210 match(If cop cr);
a61af66fc99e Initial load duke parents: diff changeset	12211 effect(USE labl);
a61af66fc99e Initial load duke parents: diff changeset	12212
a61af66fc99e Initial load duke parents: diff changeset	12213 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	12214 format %{ "J$cop $labl" %}
a61af66fc99e Initial load duke parents: diff changeset	12215 size(6);
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12216 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12217 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12218 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12219 %}
0 a61af66fc99e Initial load duke parents: diff changeset	12220 ins_pipe( pipe_jcc );
a61af66fc99e Initial load duke parents: diff changeset	12221 %}
a61af66fc99e Initial load duke parents: diff changeset	12222
a61af66fc99e Initial load duke parents: diff changeset	12223 // Jump Direct Conditional - Label defines a relative address from Jcc+1
a61af66fc99e Initial load duke parents: diff changeset	12224 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
a61af66fc99e Initial load duke parents: diff changeset	12225 match(CountedLoopEnd cop cr);
a61af66fc99e Initial load duke parents: diff changeset	12226 effect(USE labl);
a61af66fc99e Initial load duke parents: diff changeset	12227
a61af66fc99e Initial load duke parents: diff changeset	12228 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	12229 format %{ "J$cop $labl\t# Loop end" %}
a61af66fc99e Initial load duke parents: diff changeset	12230 size(6);
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12231 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12232 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12233 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12234 %}
0 a61af66fc99e Initial load duke parents: diff changeset	12235 ins_pipe( pipe_jcc );
a61af66fc99e Initial load duke parents: diff changeset	12236 %}
a61af66fc99e Initial load duke parents: diff changeset	12237
a61af66fc99e Initial load duke parents: diff changeset	12238 // Jump Direct Conditional - Label defines a relative address from Jcc+1
a61af66fc99e Initial load duke parents: diff changeset	12239 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
a61af66fc99e Initial load duke parents: diff changeset	12240 match(CountedLoopEnd cop cmp);
a61af66fc99e Initial load duke parents: diff changeset	12241 effect(USE labl);
a61af66fc99e Initial load duke parents: diff changeset	12242
a61af66fc99e Initial load duke parents: diff changeset	12243 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	12244 format %{ "J$cop,u $labl\t# Loop end" %}
a61af66fc99e Initial load duke parents: diff changeset	12245 size(6);
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12246 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12247 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12248 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12249 %}
0 a61af66fc99e Initial load duke parents: diff changeset	12250 ins_pipe( pipe_jcc );
a61af66fc99e Initial load duke parents: diff changeset	12251 %}
a61af66fc99e Initial load duke parents: diff changeset	12252
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12253 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12254 match(CountedLoopEnd cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12255 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12256
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12257 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12258 format %{ "J$cop,u $labl\t# Loop end" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12259 size(6);
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12260 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12261 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12262 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12263 %}
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12264 ins_pipe( pipe_jcc );
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12265 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12266
0 a61af66fc99e Initial load duke parents: diff changeset	12267 // Jump Direct Conditional - using unsigned comparison
a61af66fc99e Initial load duke parents: diff changeset	12268 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
a61af66fc99e Initial load duke parents: diff changeset	12269 match(If cop cmp);
a61af66fc99e Initial load duke parents: diff changeset	12270 effect(USE labl);
a61af66fc99e Initial load duke parents: diff changeset	12271
a61af66fc99e Initial load duke parents: diff changeset	12272 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	12273 format %{ "J$cop,u $labl" %}
a61af66fc99e Initial load duke parents: diff changeset	12274 size(6);
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12275 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12276 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12277 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12278 %}
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12279 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12280 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12281
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12282 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12283 match(If cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12284 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12285
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12286 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12287 format %{ "J$cop,u $labl" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12288 size(6);
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12289 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12290 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12291 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12292 %}
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12293 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12294 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12295
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12296 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12297 match(If cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12298 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12299
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12300 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12301 format %{ $$template
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12302 if ($cop$$cmpcode == Assembler::notEqual) {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12303 $$emit$$"JP,u $labl\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12304 $$emit$$"J$cop,u $labl"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12305 } else {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12306 $$emit$$"JP,u done\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12307 $$emit$$"J$cop,u $labl\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12308 $$emit$$"done:"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12309 }
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12310 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12311 ins_encode %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12312 Label* l = $labl$$label;
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12313 if ($cop$$cmpcode == Assembler::notEqual) {
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12314 __ jcc(Assembler::parity, *l, false);
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12315 __ jcc(Assembler::notEqual, *l, false);
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12316 } else if ($cop$$cmpcode == Assembler::equal) {
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12317 Label done;
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12318 __ jccb(Assembler::parity, done);
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12319 __ jcc(Assembler::equal, *l, false);
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12320 __ bind(done);
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12321 } else {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12322 ShouldNotReachHere();
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12323 }
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12324 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12325 ins_pipe(pipe_jcc);
0 a61af66fc99e Initial load duke parents: diff changeset	12326 %}
a61af66fc99e Initial load duke parents: diff changeset	12327
a61af66fc99e Initial load duke parents: diff changeset	12328 // ============================================================================
a61af66fc99e Initial load duke parents: diff changeset	12329 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
a61af66fc99e Initial load duke parents: diff changeset	12330 // array for an instance of the superklass. Set a hidden internal cache on a
a61af66fc99e Initial load duke parents: diff changeset	12331 // hit (cache is checked with exposed code in gen_subtype_check()). Return
a61af66fc99e Initial load duke parents: diff changeset	12332 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
a61af66fc99e Initial load duke parents: diff changeset	12333 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
a61af66fc99e Initial load duke parents: diff changeset	12334 match(Set result (PartialSubtypeCheck sub super));
a61af66fc99e Initial load duke parents: diff changeset	12335 effect( KILL rcx, KILL cr );
a61af66fc99e Initial load duke parents: diff changeset	12336
a61af66fc99e Initial load duke parents: diff changeset	12337 ins_cost(1100); // slightly larger than the next version
644 c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638) jrose parents: 643 diff changeset	12338 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
6831 d8ce2825b193 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass coleenp parents: 6795 diff changeset	12339 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
d8ce2825b193 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass coleenp parents: 6795 diff changeset	12340 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
0 a61af66fc99e Initial load duke parents: diff changeset	12341 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12342 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12343 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12344 "XOR $result,$result\t\t Hit: EDI zero\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12345 "miss:\t" %}
a61af66fc99e Initial load duke parents: diff changeset	12346
a61af66fc99e Initial load duke parents: diff changeset	12347 opcode(0x1); // Force a XOR of EDI
a61af66fc99e Initial load duke parents: diff changeset	12348 ins_encode( enc_PartialSubtypeCheck() );
a61af66fc99e Initial load duke parents: diff changeset	12349 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	12350 %}
a61af66fc99e Initial load duke parents: diff changeset	12351
a61af66fc99e Initial load duke parents: diff changeset	12352 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
a61af66fc99e Initial load duke parents: diff changeset	12353 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
a61af66fc99e Initial load duke parents: diff changeset	12354 effect( KILL rcx, KILL result );
a61af66fc99e Initial load duke parents: diff changeset	12355
a61af66fc99e Initial load duke parents: diff changeset	12356 ins_cost(1000);
644 c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638) jrose parents: 643 diff changeset	12357 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
6831 d8ce2825b193 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass coleenp parents: 6795 diff changeset	12358 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
d8ce2825b193 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass coleenp parents: 6795 diff changeset	12359 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
0 a61af66fc99e Initial load duke parents: diff changeset	12360 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12361 "JNE,s miss\t\t# Missed: flags NZ\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12362 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12363 "miss:\t" %}
a61af66fc99e Initial load duke parents: diff changeset	12364
a61af66fc99e Initial load duke parents: diff changeset	12365 opcode(0x0); // No need to XOR EDI
a61af66fc99e Initial load duke parents: diff changeset	12366 ins_encode( enc_PartialSubtypeCheck() );
a61af66fc99e Initial load duke parents: diff changeset	12367 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	12368 %}
a61af66fc99e Initial load duke parents: diff changeset	12369
a61af66fc99e Initial load duke parents: diff changeset	12370 // ============================================================================
a61af66fc99e Initial load duke parents: diff changeset	12371 // Branch Instructions -- short offset versions
a61af66fc99e Initial load duke parents: diff changeset	12372 //
a61af66fc99e Initial load duke parents: diff changeset	12373 // These instructions are used to replace jumps of a long offset (the default
a61af66fc99e Initial load duke parents: diff changeset	12374 // match) with jumps of a shorter offset. These instructions are all tagged
a61af66fc99e Initial load duke parents: diff changeset	12375 // with the ins_short_branch attribute, which causes the ADLC to suppress the
a61af66fc99e Initial load duke parents: diff changeset	12376 // match rules in general matching. Instead, the ADLC generates a conversion
a61af66fc99e Initial load duke parents: diff changeset	12377 // method in the MachNode which can be used to do in-place replacement of the
a61af66fc99e Initial load duke parents: diff changeset	12378 // long variant with the shorter variant. The compiler will determine if a
a61af66fc99e Initial load duke parents: diff changeset	12379 // branch can be taken by the is_short_branch_offset() predicate in the machine
a61af66fc99e Initial load duke parents: diff changeset	12380 // specific code section of the file.
a61af66fc99e Initial load duke parents: diff changeset	12381
a61af66fc99e Initial load duke parents: diff changeset	12382 // Jump Direct - Label defines a relative address from JMP+1
a61af66fc99e Initial load duke parents: diff changeset	12383 instruct jmpDir_short(label labl) %{
a61af66fc99e Initial load duke parents: diff changeset	12384 match(Goto);
a61af66fc99e Initial load duke parents: diff changeset	12385 effect(USE labl);
a61af66fc99e Initial load duke parents: diff changeset	12386
a61af66fc99e Initial load duke parents: diff changeset	12387 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	12388 format %{ "JMP,s $labl" %}
a61af66fc99e Initial load duke parents: diff changeset	12389 size(2);
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12390 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12391 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12392 __ jmpb(*L);
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12393 %}
0 a61af66fc99e Initial load duke parents: diff changeset	12394 ins_pipe( pipe_jmp );
a61af66fc99e Initial load duke parents: diff changeset	12395 ins_short_branch(1);
a61af66fc99e Initial load duke parents: diff changeset	12396 %}
a61af66fc99e Initial load duke parents: diff changeset	12397
a61af66fc99e Initial load duke parents: diff changeset	12398 // Jump Direct Conditional - Label defines a relative address from Jcc+1
a61af66fc99e Initial load duke parents: diff changeset	12399 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
a61af66fc99e Initial load duke parents: diff changeset	12400 match(If cop cr);
a61af66fc99e Initial load duke parents: diff changeset	12401 effect(USE labl);
a61af66fc99e Initial load duke parents: diff changeset	12402
a61af66fc99e Initial load duke parents: diff changeset	12403 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	12404 format %{ "J$cop,s $labl" %}
a61af66fc99e Initial load duke parents: diff changeset	12405 size(2);
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12406 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12407 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12408 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12409 %}
0 a61af66fc99e Initial load duke parents: diff changeset	12410 ins_pipe( pipe_jcc );
a61af66fc99e Initial load duke parents: diff changeset	12411 ins_short_branch(1);
a61af66fc99e Initial load duke parents: diff changeset	12412 %}
a61af66fc99e Initial load duke parents: diff changeset	12413
a61af66fc99e Initial load duke parents: diff changeset	12414 // Jump Direct Conditional - Label defines a relative address from Jcc+1
a61af66fc99e Initial load duke parents: diff changeset	12415 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
a61af66fc99e Initial load duke parents: diff changeset	12416 match(CountedLoopEnd cop cr);
a61af66fc99e Initial load duke parents: diff changeset	12417 effect(USE labl);
a61af66fc99e Initial load duke parents: diff changeset	12418
a61af66fc99e Initial load duke parents: diff changeset	12419 ins_cost(300);
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12420 format %{ "J$cop,s $labl\t# Loop end" %}
0 a61af66fc99e Initial load duke parents: diff changeset	12421 size(2);
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12422 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12423 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12424 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12425 %}
0 a61af66fc99e Initial load duke parents: diff changeset	12426 ins_pipe( pipe_jcc );
a61af66fc99e Initial load duke parents: diff changeset	12427 ins_short_branch(1);
a61af66fc99e Initial load duke parents: diff changeset	12428 %}
a61af66fc99e Initial load duke parents: diff changeset	12429
a61af66fc99e Initial load duke parents: diff changeset	12430 // Jump Direct Conditional - Label defines a relative address from Jcc+1
a61af66fc99e Initial load duke parents: diff changeset	12431 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
a61af66fc99e Initial load duke parents: diff changeset	12432 match(CountedLoopEnd cop cmp);
a61af66fc99e Initial load duke parents: diff changeset	12433 effect(USE labl);
a61af66fc99e Initial load duke parents: diff changeset	12434
a61af66fc99e Initial load duke parents: diff changeset	12435 ins_cost(300);
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12436 format %{ "J$cop,us $labl\t# Loop end" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12437 size(2);
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12438 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12439 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12440 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12441 %}
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12442 ins_pipe( pipe_jcc );
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12443 ins_short_branch(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12444 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12445
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12446 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12447 match(CountedLoopEnd cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12448 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12449
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12450 ins_cost(300);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12451 format %{ "J$cop,us $labl\t# Loop end" %}
0 a61af66fc99e Initial load duke parents: diff changeset	12452 size(2);
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12453 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12454 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12455 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12456 %}
0 a61af66fc99e Initial load duke parents: diff changeset	12457 ins_pipe( pipe_jcc );
a61af66fc99e Initial load duke parents: diff changeset	12458 ins_short_branch(1);
a61af66fc99e Initial load duke parents: diff changeset	12459 %}
a61af66fc99e Initial load duke parents: diff changeset	12460
a61af66fc99e Initial load duke parents: diff changeset	12461 // Jump Direct Conditional - using unsigned comparison
a61af66fc99e Initial load duke parents: diff changeset	12462 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
a61af66fc99e Initial load duke parents: diff changeset	12463 match(If cop cmp);
a61af66fc99e Initial load duke parents: diff changeset	12464 effect(USE labl);
a61af66fc99e Initial load duke parents: diff changeset	12465
a61af66fc99e Initial load duke parents: diff changeset	12466 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	12467 format %{ "J$cop,us $labl" %}
a61af66fc99e Initial load duke parents: diff changeset	12468 size(2);
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12469 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12470 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12471 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12472 %}
0 a61af66fc99e Initial load duke parents: diff changeset	12473 ins_pipe( pipe_jcc );
a61af66fc99e Initial load duke parents: diff changeset	12474 ins_short_branch(1);
a61af66fc99e Initial load duke parents: diff changeset	12475 %}
a61af66fc99e Initial load duke parents: diff changeset	12476
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12477 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12478 match(If cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12479 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12480
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12481 ins_cost(300);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12482 format %{ "J$cop,us $labl" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12483 size(2);
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12484 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12485 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12486 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12487 %}
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12488 ins_pipe( pipe_jcc );
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12489 ins_short_branch(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12490 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12491
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12492 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12493 match(If cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12494 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12495
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12496 ins_cost(300);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12497 format %{ $$template
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12498 if ($cop$$cmpcode == Assembler::notEqual) {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12499 $$emit$$"JP,u,s $labl\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12500 $$emit$$"J$cop,u,s $labl"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12501 } else {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12502 $$emit$$"JP,u,s done\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12503 $$emit$$"J$cop,u,s $labl\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12504 $$emit$$"done:"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12505 }
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12506 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12507 size(4);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12508 ins_encode %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12509 Label* l = $labl$$label;
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12510 if ($cop$$cmpcode == Assembler::notEqual) {
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12511 __ jccb(Assembler::parity, *l);
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12512 __ jccb(Assembler::notEqual, *l);
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12513 } else if ($cop$$cmpcode == Assembler::equal) {
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12514 Label done;
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12515 __ jccb(Assembler::parity, done);
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12516 __ jccb(Assembler::equal, *l);
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12517 __ bind(done);
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12518 } else {
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12519 ShouldNotReachHere();
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3849 diff changeset	12520 }
415 4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12521 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12522 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12523 ins_short_branch(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12524 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it never parents: 403 diff changeset	12525
0 a61af66fc99e Initial load duke parents: diff changeset	12526 // ============================================================================
a61af66fc99e Initial load duke parents: diff changeset	12527 // Long Compare
a61af66fc99e Initial load duke parents: diff changeset	12528 //
a61af66fc99e Initial load duke parents: diff changeset	12529 // Currently we hold longs in 2 registers. Comparing such values efficiently
a61af66fc99e Initial load duke parents: diff changeset	12530 // is tricky. The flavor of compare used depends on whether we are testing
a61af66fc99e Initial load duke parents: diff changeset	12531 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
a61af66fc99e Initial load duke parents: diff changeset	12532 // The GE test is the negated LT test. The LE test can be had by commuting
a61af66fc99e Initial load duke parents: diff changeset	12533 // the operands (yielding a GE test) and then negating; negate again for the
a61af66fc99e Initial load duke parents: diff changeset	12534 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
a61af66fc99e Initial load duke parents: diff changeset	12535 // NE test is negated from that.
a61af66fc99e Initial load duke parents: diff changeset	12536
a61af66fc99e Initial load duke parents: diff changeset	12537 // Due to a shortcoming in the ADLC, it mixes up expressions like:
a61af66fc99e Initial load duke parents: diff changeset	12538 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
a61af66fc99e Initial load duke parents: diff changeset	12539 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
a61af66fc99e Initial load duke parents: diff changeset	12540 // are collapsed internally in the ADLC's dfa-gen code. The match for
a61af66fc99e Initial load duke parents: diff changeset	12541 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
a61af66fc99e Initial load duke parents: diff changeset	12542 // foo match ends up with the wrong leaf. One fix is to not match both
a61af66fc99e Initial load duke parents: diff changeset	12543 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
a61af66fc99e Initial load duke parents: diff changeset	12544 // both forms beat the trinary form of long-compare and both are very useful
a61af66fc99e Initial load duke parents: diff changeset	12545 // on Intel which has so few registers.
a61af66fc99e Initial load duke parents: diff changeset	12546
a61af66fc99e Initial load duke parents: diff changeset	12547 // Manifest a CmpL result in an integer register. Very painful.
a61af66fc99e Initial load duke parents: diff changeset	12548 // This is the test to avoid.
a61af66fc99e Initial load duke parents: diff changeset	12549 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
a61af66fc99e Initial load duke parents: diff changeset	12550 match(Set dst (CmpL3 src1 src2));
a61af66fc99e Initial load duke parents: diff changeset	12551 effect( KILL flags );
a61af66fc99e Initial load duke parents: diff changeset	12552 ins_cost(1000);
a61af66fc99e Initial load duke parents: diff changeset	12553 format %{ "XOR $dst,$dst\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12554 "CMP $src1.hi,$src2.hi\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12555 "JLT,s m_one\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12556 "JGT,s p_one\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12557 "CMP $src1.lo,$src2.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12558 "JB,s m_one\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12559 "JEQ,s done\n"
a61af66fc99e Initial load duke parents: diff changeset	12560 "p_one:\tINC $dst\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12561 "JMP,s done\n"
a61af66fc99e Initial load duke parents: diff changeset	12562 "m_one:\tDEC $dst\n"
a61af66fc99e Initial load duke parents: diff changeset	12563 "done:" %}
a61af66fc99e Initial load duke parents: diff changeset	12564 ins_encode %{
a61af66fc99e Initial load duke parents: diff changeset	12565 Label p_one, m_one, done;
304 dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories never parents: 235 diff changeset	12566 __ xorptr($dst$$Register, $dst$$Register);
0 a61af66fc99e Initial load duke parents: diff changeset	12567 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
a61af66fc99e Initial load duke parents: diff changeset	12568 __ jccb(Assembler::less, m_one);
a61af66fc99e Initial load duke parents: diff changeset	12569 __ jccb(Assembler::greater, p_one);
a61af66fc99e Initial load duke parents: diff changeset	12570 __ cmpl($src1$$Register, $src2$$Register);
a61af66fc99e Initial load duke parents: diff changeset	12571 __ jccb(Assembler::below, m_one);
a61af66fc99e Initial load duke parents: diff changeset	12572 __ jccb(Assembler::equal, done);
a61af66fc99e Initial load duke parents: diff changeset	12573 __ bind(p_one);
304 dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories never parents: 235 diff changeset	12574 __ incrementl($dst$$Register);
0 a61af66fc99e Initial load duke parents: diff changeset	12575 __ jmpb(done);
a61af66fc99e Initial load duke parents: diff changeset	12576 __ bind(m_one);
304 dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories never parents: 235 diff changeset	12577 __ decrementl($dst$$Register);
0 a61af66fc99e Initial load duke parents: diff changeset	12578 __ bind(done);
a61af66fc99e Initial load duke parents: diff changeset	12579 %}
a61af66fc99e Initial load duke parents: diff changeset	12580 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	12581 %}
a61af66fc99e Initial load duke parents: diff changeset	12582
a61af66fc99e Initial load duke parents: diff changeset	12583 //======
a61af66fc99e Initial load duke parents: diff changeset	12584 // Manifest a CmpL result in the normal flags. Only good for LT or GE
a61af66fc99e Initial load duke parents: diff changeset	12585 // compares. Can be used for LE or GT compares by reversing arguments.
a61af66fc99e Initial load duke parents: diff changeset	12586 // NOT GOOD FOR EQ/NE tests.
a61af66fc99e Initial load duke parents: diff changeset	12587 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
a61af66fc99e Initial load duke parents: diff changeset	12588 match( Set flags (CmpL src zero ));
a61af66fc99e Initial load duke parents: diff changeset	12589 ins_cost(100);
a61af66fc99e Initial load duke parents: diff changeset	12590 format %{ "TEST $src.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	12591 opcode(0x85);
a61af66fc99e Initial load duke parents: diff changeset	12592 ins_encode( OpcP, RegReg_Hi2( src, src ) );
a61af66fc99e Initial load duke parents: diff changeset	12593 ins_pipe( ialu_cr_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	12594 %}
a61af66fc99e Initial load duke parents: diff changeset	12595
a61af66fc99e Initial load duke parents: diff changeset	12596 // Manifest a CmpL result in the normal flags. Only good for LT or GE
a61af66fc99e Initial load duke parents: diff changeset	12597 // compares. Can be used for LE or GT compares by reversing arguments.
a61af66fc99e Initial load duke parents: diff changeset	12598 // NOT GOOD FOR EQ/NE tests.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	12599 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12600 match( Set flags (CmpL src1 src2 ));
a61af66fc99e Initial load duke parents: diff changeset	12601 effect( TEMP tmp );
a61af66fc99e Initial load duke parents: diff changeset	12602 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	12603 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12604 "MOV $tmp,$src1.hi\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12605 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
a61af66fc99e Initial load duke parents: diff changeset	12606 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
a61af66fc99e Initial load duke parents: diff changeset	12607 ins_pipe( ialu_cr_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	12608 %}
a61af66fc99e Initial load duke parents: diff changeset	12609
a61af66fc99e Initial load duke parents: diff changeset	12610 // Long compares reg < zero/req OR reg >= zero/req.
a61af66fc99e Initial load duke parents: diff changeset	12611 // Just a wrapper for a normal branch, plus the predicate test.
a61af66fc99e Initial load duke parents: diff changeset	12612 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
a61af66fc99e Initial load duke parents: diff changeset	12613 match(If cmp flags);
a61af66fc99e Initial load duke parents: diff changeset	12614 effect(USE labl);
a61af66fc99e Initial load duke parents: diff changeset	12615 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt \|\| _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
a61af66fc99e Initial load duke parents: diff changeset	12616 expand %{
a61af66fc99e Initial load duke parents: diff changeset	12617 jmpCon(cmp,flags,labl); // JLT or JGE...
a61af66fc99e Initial load duke parents: diff changeset	12618 %}
a61af66fc99e Initial load duke parents: diff changeset	12619 %}
a61af66fc99e Initial load duke parents: diff changeset	12620
a61af66fc99e Initial load duke parents: diff changeset	12621 // Compare 2 longs and CMOVE longs.
a61af66fc99e Initial load duke parents: diff changeset	12622 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
a61af66fc99e Initial load duke parents: diff changeset	12623 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12624 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
a61af66fc99e Initial load duke parents: diff changeset	12625 ins_cost(400);
a61af66fc99e Initial load duke parents: diff changeset	12626 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12627 "CMOV$cmp $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	12628 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	12629 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	12630 ins_pipe( pipe_cmov_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	12631 %}
a61af66fc99e Initial load duke parents: diff changeset	12632
a61af66fc99e Initial load duke parents: diff changeset	12633 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
a61af66fc99e Initial load duke parents: diff changeset	12634 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
a61af66fc99e Initial load duke parents: diff changeset	12635 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
a61af66fc99e Initial load duke parents: diff changeset	12636 ins_cost(500);
a61af66fc99e Initial load duke parents: diff changeset	12637 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12638 "CMOV$cmp $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	12639 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	12640 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	12641 ins_pipe( pipe_cmov_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	12642 %}
a61af66fc99e Initial load duke parents: diff changeset	12643
a61af66fc99e Initial load duke parents: diff changeset	12644 // Compare 2 longs and CMOVE ints.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	12645 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12646 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
a61af66fc99e Initial load duke parents: diff changeset	12647 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12648 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12649 format %{ "CMOV$cmp $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	12650 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	12651 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	12652 ins_pipe( pipe_cmov_reg );
a61af66fc99e Initial load duke parents: diff changeset	12653 %}
a61af66fc99e Initial load duke parents: diff changeset	12654
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	12655 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12656 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
a61af66fc99e Initial load duke parents: diff changeset	12657 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
a61af66fc99e Initial load duke parents: diff changeset	12658 ins_cost(250);
a61af66fc99e Initial load duke parents: diff changeset	12659 format %{ "CMOV$cmp $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	12660 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	12661 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	12662 ins_pipe( pipe_cmov_mem );
a61af66fc99e Initial load duke parents: diff changeset	12663 %}
a61af66fc99e Initial load duke parents: diff changeset	12664
a61af66fc99e Initial load duke parents: diff changeset	12665 // Compare 2 longs and CMOVE ints.
a61af66fc99e Initial load duke parents: diff changeset	12666 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
a61af66fc99e Initial load duke parents: diff changeset	12667 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
a61af66fc99e Initial load duke parents: diff changeset	12668 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12669 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12670 format %{ "CMOV$cmp $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	12671 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	12672 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	12673 ins_pipe( pipe_cmov_reg );
a61af66fc99e Initial load duke parents: diff changeset	12674 %}
a61af66fc99e Initial load duke parents: diff changeset	12675
a61af66fc99e Initial load duke parents: diff changeset	12676 // Compare 2 longs and CMOVE doubles
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12677 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12678 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
a61af66fc99e Initial load duke parents: diff changeset	12679 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12680 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12681 expand %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12682 fcmovDPR_regS(cmp,flags,dst,src);
0 a61af66fc99e Initial load duke parents: diff changeset	12683 %}
a61af66fc99e Initial load duke parents: diff changeset	12684 %}
a61af66fc99e Initial load duke parents: diff changeset	12685
a61af66fc99e Initial load duke parents: diff changeset	12686 // Compare 2 longs and CMOVE doubles
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12687 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12688 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
a61af66fc99e Initial load duke parents: diff changeset	12689 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12690 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12691 expand %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12692 fcmovD_regS(cmp,flags,dst,src);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12693 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12694 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12695
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12696 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12697 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12698 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12699 ins_cost(200);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12700 expand %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12701 fcmovFPR_regS(cmp,flags,dst,src);
0 a61af66fc99e Initial load duke parents: diff changeset	12702 %}
a61af66fc99e Initial load duke parents: diff changeset	12703 %}
a61af66fc99e Initial load duke parents: diff changeset	12704
a61af66fc99e Initial load duke parents: diff changeset	12705 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12706 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
0 a61af66fc99e Initial load duke parents: diff changeset	12707 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12708 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12709 expand %{
a61af66fc99e Initial load duke parents: diff changeset	12710 fcmovF_regS(cmp,flags,dst,src);
a61af66fc99e Initial load duke parents: diff changeset	12711 %}
a61af66fc99e Initial load duke parents: diff changeset	12712 %}
a61af66fc99e Initial load duke parents: diff changeset	12713
a61af66fc99e Initial load duke parents: diff changeset	12714 //======
a61af66fc99e Initial load duke parents: diff changeset	12715 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	12716 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12717 match( Set flags (CmpL src zero ));
a61af66fc99e Initial load duke parents: diff changeset	12718 effect(TEMP tmp);
a61af66fc99e Initial load duke parents: diff changeset	12719 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12720 format %{ "MOV $tmp,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12721 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
a61af66fc99e Initial load duke parents: diff changeset	12722 ins_encode( long_cmp_flags0( src, tmp ) );
a61af66fc99e Initial load duke parents: diff changeset	12723 ins_pipe( ialu_reg_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	12724 %}
a61af66fc99e Initial load duke parents: diff changeset	12725
a61af66fc99e Initial load duke parents: diff changeset	12726 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
a61af66fc99e Initial load duke parents: diff changeset	12727 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
a61af66fc99e Initial load duke parents: diff changeset	12728 match( Set flags (CmpL src1 src2 ));
a61af66fc99e Initial load duke parents: diff changeset	12729 ins_cost(200+300);
a61af66fc99e Initial load duke parents: diff changeset	12730 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12731 "JNE,s skip\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12732 "CMP $src1.hi,$src2.hi\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12733 "skip:\t" %}
a61af66fc99e Initial load duke parents: diff changeset	12734 ins_encode( long_cmp_flags1( src1, src2 ) );
a61af66fc99e Initial load duke parents: diff changeset	12735 ins_pipe( ialu_cr_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	12736 %}
a61af66fc99e Initial load duke parents: diff changeset	12737
a61af66fc99e Initial load duke parents: diff changeset	12738 // Long compare reg == zero/reg OR reg != zero/reg
a61af66fc99e Initial load duke parents: diff changeset	12739 // Just a wrapper for a normal branch, plus the predicate test.
a61af66fc99e Initial load duke parents: diff changeset	12740 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
a61af66fc99e Initial load duke parents: diff changeset	12741 match(If cmp flags);
a61af66fc99e Initial load duke parents: diff changeset	12742 effect(USE labl);
a61af66fc99e Initial load duke parents: diff changeset	12743 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq \|\| _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
a61af66fc99e Initial load duke parents: diff changeset	12744 expand %{
a61af66fc99e Initial load duke parents: diff changeset	12745 jmpCon(cmp,flags,labl); // JEQ or JNE...
a61af66fc99e Initial load duke parents: diff changeset	12746 %}
a61af66fc99e Initial load duke parents: diff changeset	12747 %}
a61af66fc99e Initial load duke parents: diff changeset	12748
a61af66fc99e Initial load duke parents: diff changeset	12749 // Compare 2 longs and CMOVE longs.
a61af66fc99e Initial load duke parents: diff changeset	12750 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
a61af66fc99e Initial load duke parents: diff changeset	12751 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12752 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
a61af66fc99e Initial load duke parents: diff changeset	12753 ins_cost(400);
a61af66fc99e Initial load duke parents: diff changeset	12754 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12755 "CMOV$cmp $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	12756 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	12757 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	12758 ins_pipe( pipe_cmov_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	12759 %}
a61af66fc99e Initial load duke parents: diff changeset	12760
a61af66fc99e Initial load duke parents: diff changeset	12761 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
a61af66fc99e Initial load duke parents: diff changeset	12762 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
a61af66fc99e Initial load duke parents: diff changeset	12763 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
a61af66fc99e Initial load duke parents: diff changeset	12764 ins_cost(500);
a61af66fc99e Initial load duke parents: diff changeset	12765 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12766 "CMOV$cmp $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	12767 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	12768 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	12769 ins_pipe( pipe_cmov_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	12770 %}
a61af66fc99e Initial load duke parents: diff changeset	12771
a61af66fc99e Initial load duke parents: diff changeset	12772 // Compare 2 longs and CMOVE ints.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	12773 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12774 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
a61af66fc99e Initial load duke parents: diff changeset	12775 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12776 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12777 format %{ "CMOV$cmp $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	12778 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	12779 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	12780 ins_pipe( pipe_cmov_reg );
a61af66fc99e Initial load duke parents: diff changeset	12781 %}
a61af66fc99e Initial load duke parents: diff changeset	12782
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	12783 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12784 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
a61af66fc99e Initial load duke parents: diff changeset	12785 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
a61af66fc99e Initial load duke parents: diff changeset	12786 ins_cost(250);
a61af66fc99e Initial load duke parents: diff changeset	12787 format %{ "CMOV$cmp $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	12788 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	12789 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	12790 ins_pipe( pipe_cmov_mem );
a61af66fc99e Initial load duke parents: diff changeset	12791 %}
a61af66fc99e Initial load duke parents: diff changeset	12792
a61af66fc99e Initial load duke parents: diff changeset	12793 // Compare 2 longs and CMOVE ints.
a61af66fc99e Initial load duke parents: diff changeset	12794 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
a61af66fc99e Initial load duke parents: diff changeset	12795 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
a61af66fc99e Initial load duke parents: diff changeset	12796 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12797 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12798 format %{ "CMOV$cmp $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	12799 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	12800 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	12801 ins_pipe( pipe_cmov_reg );
a61af66fc99e Initial load duke parents: diff changeset	12802 %}
a61af66fc99e Initial load duke parents: diff changeset	12803
a61af66fc99e Initial load duke parents: diff changeset	12804 // Compare 2 longs and CMOVE doubles
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12805 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12806 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
a61af66fc99e Initial load duke parents: diff changeset	12807 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12808 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12809 expand %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12810 fcmovDPR_regS(cmp,flags,dst,src);
0 a61af66fc99e Initial load duke parents: diff changeset	12811 %}
a61af66fc99e Initial load duke parents: diff changeset	12812 %}
a61af66fc99e Initial load duke parents: diff changeset	12813
a61af66fc99e Initial load duke parents: diff changeset	12814 // Compare 2 longs and CMOVE doubles
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12815 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12816 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
a61af66fc99e Initial load duke parents: diff changeset	12817 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12818 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12819 expand %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12820 fcmovD_regS(cmp,flags,dst,src);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12821 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12822 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12823
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12824 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12825 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12826 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12827 ins_cost(200);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12828 expand %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12829 fcmovFPR_regS(cmp,flags,dst,src);
0 a61af66fc99e Initial load duke parents: diff changeset	12830 %}
a61af66fc99e Initial load duke parents: diff changeset	12831 %}
a61af66fc99e Initial load duke parents: diff changeset	12832
a61af66fc99e Initial load duke parents: diff changeset	12833 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12834 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
0 a61af66fc99e Initial load duke parents: diff changeset	12835 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12836 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12837 expand %{
a61af66fc99e Initial load duke parents: diff changeset	12838 fcmovF_regS(cmp,flags,dst,src);
a61af66fc99e Initial load duke parents: diff changeset	12839 %}
a61af66fc99e Initial load duke parents: diff changeset	12840 %}
a61af66fc99e Initial load duke parents: diff changeset	12841
a61af66fc99e Initial load duke parents: diff changeset	12842 //======
a61af66fc99e Initial load duke parents: diff changeset	12843 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
a61af66fc99e Initial load duke parents: diff changeset	12844 // Same as cmpL_reg_flags_LEGT except must negate src
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	12845 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12846 match( Set flags (CmpL src zero ));
a61af66fc99e Initial load duke parents: diff changeset	12847 effect( TEMP tmp );
a61af66fc99e Initial load duke parents: diff changeset	12848 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	12849 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12850 "CMP $tmp,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12851 "SBB $tmp,$src.hi\n\t" %}
a61af66fc99e Initial load duke parents: diff changeset	12852 ins_encode( long_cmp_flags3(src, tmp) );
a61af66fc99e Initial load duke parents: diff changeset	12853 ins_pipe( ialu_reg_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	12854 %}
a61af66fc99e Initial load duke parents: diff changeset	12855
a61af66fc99e Initial load duke parents: diff changeset	12856 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
a61af66fc99e Initial load duke parents: diff changeset	12857 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
a61af66fc99e Initial load duke parents: diff changeset	12858 // requires a commuted test to get the same result.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	12859 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12860 match( Set flags (CmpL src1 src2 ));
a61af66fc99e Initial load duke parents: diff changeset	12861 effect( TEMP tmp );
a61af66fc99e Initial load duke parents: diff changeset	12862 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	12863 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12864 "MOV $tmp,$src2.hi\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12865 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
a61af66fc99e Initial load duke parents: diff changeset	12866 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
a61af66fc99e Initial load duke parents: diff changeset	12867 ins_pipe( ialu_cr_reg_reg );
a61af66fc99e Initial load duke parents: diff changeset	12868 %}
a61af66fc99e Initial load duke parents: diff changeset	12869
a61af66fc99e Initial load duke parents: diff changeset	12870 // Long compares reg < zero/req OR reg >= zero/req.
a61af66fc99e Initial load duke parents: diff changeset	12871 // Just a wrapper for a normal branch, plus the predicate test
a61af66fc99e Initial load duke parents: diff changeset	12872 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
a61af66fc99e Initial load duke parents: diff changeset	12873 match(If cmp flags);
a61af66fc99e Initial load duke parents: diff changeset	12874 effect(USE labl);
a61af66fc99e Initial load duke parents: diff changeset	12875 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt \|\| _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
a61af66fc99e Initial load duke parents: diff changeset	12876 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	12877 expand %{
a61af66fc99e Initial load duke parents: diff changeset	12878 jmpCon(cmp,flags,labl); // JGT or JLE...
a61af66fc99e Initial load duke parents: diff changeset	12879 %}
a61af66fc99e Initial load duke parents: diff changeset	12880 %}
a61af66fc99e Initial load duke parents: diff changeset	12881
a61af66fc99e Initial load duke parents: diff changeset	12882 // Compare 2 longs and CMOVE longs.
a61af66fc99e Initial load duke parents: diff changeset	12883 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
a61af66fc99e Initial load duke parents: diff changeset	12884 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12885 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
a61af66fc99e Initial load duke parents: diff changeset	12886 ins_cost(400);
a61af66fc99e Initial load duke parents: diff changeset	12887 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12888 "CMOV$cmp $dst.hi,$src.hi" %}
a61af66fc99e Initial load duke parents: diff changeset	12889 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	12890 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	12891 ins_pipe( pipe_cmov_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	12892 %}
a61af66fc99e Initial load duke parents: diff changeset	12893
a61af66fc99e Initial load duke parents: diff changeset	12894 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
a61af66fc99e Initial load duke parents: diff changeset	12895 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
a61af66fc99e Initial load duke parents: diff changeset	12896 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
a61af66fc99e Initial load duke parents: diff changeset	12897 ins_cost(500);
a61af66fc99e Initial load duke parents: diff changeset	12898 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
a61af66fc99e Initial load duke parents: diff changeset	12899 "CMOV$cmp $dst.hi,$src.hi+4" %}
a61af66fc99e Initial load duke parents: diff changeset	12900 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	12901 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
a61af66fc99e Initial load duke parents: diff changeset	12902 ins_pipe( pipe_cmov_reg_long );
a61af66fc99e Initial load duke parents: diff changeset	12903 %}
a61af66fc99e Initial load duke parents: diff changeset	12904
a61af66fc99e Initial load duke parents: diff changeset	12905 // Compare 2 longs and CMOVE ints.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	12906 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12907 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
a61af66fc99e Initial load duke parents: diff changeset	12908 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12909 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12910 format %{ "CMOV$cmp $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	12911 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	12912 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	12913 ins_pipe( pipe_cmov_reg );
a61af66fc99e Initial load duke parents: diff changeset	12914 %}
a61af66fc99e Initial load duke parents: diff changeset	12915
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	12916 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12917 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
a61af66fc99e Initial load duke parents: diff changeset	12918 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
a61af66fc99e Initial load duke parents: diff changeset	12919 ins_cost(250);
a61af66fc99e Initial load duke parents: diff changeset	12920 format %{ "CMOV$cmp $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	12921 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	12922 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	12923 ins_pipe( pipe_cmov_mem );
a61af66fc99e Initial load duke parents: diff changeset	12924 %}
a61af66fc99e Initial load duke parents: diff changeset	12925
a61af66fc99e Initial load duke parents: diff changeset	12926 // Compare 2 longs and CMOVE ptrs.
a61af66fc99e Initial load duke parents: diff changeset	12927 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
a61af66fc99e Initial load duke parents: diff changeset	12928 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
a61af66fc99e Initial load duke parents: diff changeset	12929 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12930 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12931 format %{ "CMOV$cmp $dst,$src" %}
a61af66fc99e Initial load duke parents: diff changeset	12932 opcode(0x0F,0x40);
a61af66fc99e Initial load duke parents: diff changeset	12933 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
a61af66fc99e Initial load duke parents: diff changeset	12934 ins_pipe( pipe_cmov_reg );
a61af66fc99e Initial load duke parents: diff changeset	12935 %}
a61af66fc99e Initial load duke parents: diff changeset	12936
a61af66fc99e Initial load duke parents: diff changeset	12937 // Compare 2 longs and CMOVE doubles
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12938 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12939 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
a61af66fc99e Initial load duke parents: diff changeset	12940 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12941 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12942 expand %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12943 fcmovDPR_regS(cmp,flags,dst,src);
0 a61af66fc99e Initial load duke parents: diff changeset	12944 %}
a61af66fc99e Initial load duke parents: diff changeset	12945 %}
a61af66fc99e Initial load duke parents: diff changeset	12946
a61af66fc99e Initial load duke parents: diff changeset	12947 // Compare 2 longs and CMOVE doubles
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12948 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	12949 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
a61af66fc99e Initial load duke parents: diff changeset	12950 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12951 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12952 expand %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12953 fcmovD_regS(cmp,flags,dst,src);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12954 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12955 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12956
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12957 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12958 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12959 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12960 ins_cost(200);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12961 expand %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12962 fcmovFPR_regS(cmp,flags,dst,src);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12963 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12964 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12965
0 a61af66fc99e Initial load duke parents: diff changeset	12966
a61af66fc99e Initial load duke parents: diff changeset	12967 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: 4759 diff changeset	12968 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le \|\| _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
0 a61af66fc99e Initial load duke parents: diff changeset	12969 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
a61af66fc99e Initial load duke parents: diff changeset	12970 ins_cost(200);
a61af66fc99e Initial load duke parents: diff changeset	12971 expand %{
a61af66fc99e Initial load duke parents: diff changeset	12972 fcmovF_regS(cmp,flags,dst,src);
a61af66fc99e Initial load duke parents: diff changeset	12973 %}
a61af66fc99e Initial load duke parents: diff changeset	12974 %}
a61af66fc99e Initial load duke parents: diff changeset	12975
a61af66fc99e Initial load duke parents: diff changeset	12976
a61af66fc99e Initial load duke parents: diff changeset	12977 // ============================================================================
a61af66fc99e Initial load duke parents: diff changeset	12978 // Procedure Call/Return Instructions
a61af66fc99e Initial load duke parents: diff changeset	12979 // Call Java Static Instruction
a61af66fc99e Initial load duke parents: diff changeset	12980 // Note: If this code changes, the corresponding ret_addr_offset() and
a61af66fc99e Initial load duke parents: diff changeset	12981 // compute_padding() functions will have to be adjusted.
a61af66fc99e Initial load duke parents: diff changeset	12982 instruct CallStaticJavaDirect(method meth) %{
a61af66fc99e Initial load duke parents: diff changeset	12983 match(CallStaticJava);
1137 97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	12984 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
0 a61af66fc99e Initial load duke parents: diff changeset	12985 effect(USE meth);
a61af66fc99e Initial load duke parents: diff changeset	12986
a61af66fc99e Initial load duke parents: diff changeset	12987 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	12988 format %{ "CALL,static " %}
a61af66fc99e Initial load duke parents: diff changeset	12989 opcode(0xE8); /* E8 cd */
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	12990 ins_encode( pre_call_resets,
0 a61af66fc99e Initial load duke parents: diff changeset	12991 Java_Static_Call( meth ),
a61af66fc99e Initial load duke parents: diff changeset	12992 call_epilog,
a61af66fc99e Initial load duke parents: diff changeset	12993 post_call_FPU );
a61af66fc99e Initial load duke parents: diff changeset	12994 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	12995 ins_alignment(4);
a61af66fc99e Initial load duke parents: diff changeset	12996 %}
a61af66fc99e Initial load duke parents: diff changeset	12997
1137 97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	12998 // Call Java Static Instruction (method handle version)
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	12999 // Note: If this code changes, the corresponding ret_addr_offset() and
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13000 // compute_padding() functions will have to be adjusted.
1567 110501f54a99 6934104: JSR 292 needs to support SPARC C2 twisti parents: 1396 diff changeset	13001 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
1137 97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13002 match(CallStaticJava);
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13003 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13004 effect(USE meth);
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13005 // EBP is saved by all callees (for interpreter stack correction).
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13006 // We use it here for a similar purpose, in {preserve,restore}_SP.
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13007
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13008 ins_cost(300);
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13009 format %{ "CALL,static/MethodHandle " %}
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13010 opcode(0xE8); /* E8 cd */
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	13011 ins_encode( pre_call_resets,
1137 97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13012 preserve_SP,
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13013 Java_Static_Call( meth ),
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13014 restore_SP,
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13015 call_epilog,
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13016 post_call_FPU );
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13017 ins_pipe( pipe_slow );
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13018 ins_alignment(4);
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13019 %}
97125851f396 6829187: compiler optimizations required for JSR 292 twisti parents: 989 diff changeset	13020
0 a61af66fc99e Initial load duke parents: diff changeset	13021 // Call Java Dynamic Instruction
a61af66fc99e Initial load duke parents: diff changeset	13022 // Note: If this code changes, the corresponding ret_addr_offset() and
a61af66fc99e Initial load duke parents: diff changeset	13023 // compute_padding() functions will have to be adjusted.
a61af66fc99e Initial load duke parents: diff changeset	13024 instruct CallDynamicJavaDirect(method meth) %{
a61af66fc99e Initial load duke parents: diff changeset	13025 match(CallDynamicJava);
a61af66fc99e Initial load duke parents: diff changeset	13026 effect(USE meth);
a61af66fc99e Initial load duke parents: diff changeset	13027
a61af66fc99e Initial load duke parents: diff changeset	13028 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	13029 format %{ "MOV EAX,(oop)-1\n\t"
a61af66fc99e Initial load duke parents: diff changeset	13030 "CALL,dynamic" %}
a61af66fc99e Initial load duke parents: diff changeset	13031 opcode(0xE8); /* E8 cd */
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	13032 ins_encode( pre_call_resets,
0 a61af66fc99e Initial load duke parents: diff changeset	13033 Java_Dynamic_Call( meth ),
a61af66fc99e Initial load duke parents: diff changeset	13034 call_epilog,
a61af66fc99e Initial load duke parents: diff changeset	13035 post_call_FPU );
a61af66fc99e Initial load duke parents: diff changeset	13036 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	13037 ins_alignment(4);
a61af66fc99e Initial load duke parents: diff changeset	13038 %}
a61af66fc99e Initial load duke parents: diff changeset	13039
a61af66fc99e Initial load duke parents: diff changeset	13040 // Call Runtime Instruction
a61af66fc99e Initial load duke parents: diff changeset	13041 instruct CallRuntimeDirect(method meth) %{
a61af66fc99e Initial load duke parents: diff changeset	13042 match(CallRuntime );
a61af66fc99e Initial load duke parents: diff changeset	13043 effect(USE meth);
a61af66fc99e Initial load duke parents: diff changeset	13044
a61af66fc99e Initial load duke parents: diff changeset	13045 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	13046 format %{ "CALL,runtime " %}
a61af66fc99e Initial load duke parents: diff changeset	13047 opcode(0xE8); /* E8 cd */
a61af66fc99e Initial load duke parents: diff changeset	13048 // Use FFREEs to clear entries in float stack
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	13049 ins_encode( pre_call_resets,
0 a61af66fc99e Initial load duke parents: diff changeset	13050 FFree_Float_Stack_All,
a61af66fc99e Initial load duke parents: diff changeset	13051 Java_To_Runtime( meth ),
a61af66fc99e Initial load duke parents: diff changeset	13052 post_call_FPU );
a61af66fc99e Initial load duke parents: diff changeset	13053 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	13054 %}
a61af66fc99e Initial load duke parents: diff changeset	13055
a61af66fc99e Initial load duke parents: diff changeset	13056 // Call runtime without safepoint
a61af66fc99e Initial load duke parents: diff changeset	13057 instruct CallLeafDirect(method meth) %{
a61af66fc99e Initial load duke parents: diff changeset	13058 match(CallLeaf);
a61af66fc99e Initial load duke parents: diff changeset	13059 effect(USE meth);
a61af66fc99e Initial load duke parents: diff changeset	13060
a61af66fc99e Initial load duke parents: diff changeset	13061 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	13062 format %{ "CALL_LEAF,runtime " %}
a61af66fc99e Initial load duke parents: diff changeset	13063 opcode(0xE8); /* E8 cd */
8873 e961c11b85fe 8011102: Clear AVX registers after return from JNI call kvn parents: 7637 diff changeset	13064 ins_encode( pre_call_resets,
0 a61af66fc99e Initial load duke parents: diff changeset	13065 FFree_Float_Stack_All,
a61af66fc99e Initial load duke parents: diff changeset	13066 Java_To_Runtime( meth ),
a61af66fc99e Initial load duke parents: diff changeset	13067 Verify_FPU_For_Leaf, post_call_FPU );
a61af66fc99e Initial load duke parents: diff changeset	13068 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	13069 %}
a61af66fc99e Initial load duke parents: diff changeset	13070
a61af66fc99e Initial load duke parents: diff changeset	13071 instruct CallLeafNoFPDirect(method meth) %{
a61af66fc99e Initial load duke parents: diff changeset	13072 match(CallLeafNoFP);
a61af66fc99e Initial load duke parents: diff changeset	13073 effect(USE meth);
a61af66fc99e Initial load duke parents: diff changeset	13074
a61af66fc99e Initial load duke parents: diff changeset	13075 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	13076 format %{ "CALL_LEAF_NOFP,runtime " %}
a61af66fc99e Initial load duke parents: diff changeset	13077 opcode(0xE8); /* E8 cd */
a61af66fc99e Initial load duke parents: diff changeset	13078 ins_encode(Java_To_Runtime(meth));
a61af66fc99e Initial load duke parents: diff changeset	13079 ins_pipe( pipe_slow );
a61af66fc99e Initial load duke parents: diff changeset	13080 %}
a61af66fc99e Initial load duke parents: diff changeset	13081
a61af66fc99e Initial load duke parents: diff changeset	13082
a61af66fc99e Initial load duke parents: diff changeset	13083 // Return Instruction
a61af66fc99e Initial load duke parents: diff changeset	13084 // Remove the return address & jump to it.
a61af66fc99e Initial load duke parents: diff changeset	13085 instruct Ret() %{
a61af66fc99e Initial load duke parents: diff changeset	13086 match(Return);
a61af66fc99e Initial load duke parents: diff changeset	13087 format %{ "RET" %}
a61af66fc99e Initial load duke parents: diff changeset	13088 opcode(0xC3);
a61af66fc99e Initial load duke parents: diff changeset	13089 ins_encode(OpcP);
a61af66fc99e Initial load duke parents: diff changeset	13090 ins_pipe( pipe_jmp );
a61af66fc99e Initial load duke parents: diff changeset	13091 %}
a61af66fc99e Initial load duke parents: diff changeset	13092
a61af66fc99e Initial load duke parents: diff changeset	13093 // Tail Call; Jump from runtime stub to Java code.
a61af66fc99e Initial load duke parents: diff changeset	13094 // Also known as an 'interprocedural jump'.
a61af66fc99e Initial load duke parents: diff changeset	13095 // Target of jump will eventually return to caller.
a61af66fc99e Initial load duke parents: diff changeset	13096 // TailJump below removes the return address.
a61af66fc99e Initial load duke parents: diff changeset	13097 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
a61af66fc99e Initial load duke parents: diff changeset	13098 match(TailCall jump_target method_oop );
a61af66fc99e Initial load duke parents: diff changeset	13099 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	13100 format %{ "JMP $jump_target \t# EBX holds method oop" %}
a61af66fc99e Initial load duke parents: diff changeset	13101 opcode(0xFF, 0x4); /* Opcode FF /4 */
a61af66fc99e Initial load duke parents: diff changeset	13102 ins_encode( OpcP, RegOpc(jump_target) );
a61af66fc99e Initial load duke parents: diff changeset	13103 ins_pipe( pipe_jmp );
a61af66fc99e Initial load duke parents: diff changeset	13104 %}
a61af66fc99e Initial load duke parents: diff changeset	13105
a61af66fc99e Initial load duke parents: diff changeset	13106
a61af66fc99e Initial load duke parents: diff changeset	13107 // Tail Jump; remove the return address; jump to target.
a61af66fc99e Initial load duke parents: diff changeset	13108 // TailCall above leaves the return address around.
a61af66fc99e Initial load duke parents: diff changeset	13109 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
a61af66fc99e Initial load duke parents: diff changeset	13110 match( TailJump jump_target ex_oop );
a61af66fc99e Initial load duke parents: diff changeset	13111 ins_cost(300);
a61af66fc99e Initial load duke parents: diff changeset	13112 format %{ "POP EDX\t# pop return address into dummy\n\t"
a61af66fc99e Initial load duke parents: diff changeset	13113 "JMP $jump_target " %}
a61af66fc99e Initial load duke parents: diff changeset	13114 opcode(0xFF, 0x4); /* Opcode FF /4 */
a61af66fc99e Initial load duke parents: diff changeset	13115 ins_encode( enc_pop_rdx,
a61af66fc99e Initial load duke parents: diff changeset	13116 OpcP, RegOpc(jump_target) );
a61af66fc99e Initial load duke parents: diff changeset	13117 ins_pipe( pipe_jmp );
a61af66fc99e Initial load duke parents: diff changeset	13118 %}
a61af66fc99e Initial load duke parents: diff changeset	13119
a61af66fc99e Initial load duke parents: diff changeset	13120 // Create exception oop: created by stack-crawling runtime code.
a61af66fc99e Initial load duke parents: diff changeset	13121 // Created exception is now available to this handler, and is setup
a61af66fc99e Initial load duke parents: diff changeset	13122 // just prior to jumping to this handler. No code emitted.
a61af66fc99e Initial load duke parents: diff changeset	13123 instruct CreateException( eAXRegP ex_oop )
a61af66fc99e Initial load duke parents: diff changeset	13124 %{
a61af66fc99e Initial load duke parents: diff changeset	13125 match(Set ex_oop (CreateEx));
a61af66fc99e Initial load duke parents: diff changeset	13126
a61af66fc99e Initial load duke parents: diff changeset	13127 size(0);
a61af66fc99e Initial load duke parents: diff changeset	13128 // use the following format syntax
a61af66fc99e Initial load duke parents: diff changeset	13129 format %{ "# exception oop is in EAX; no code emitted" %}
a61af66fc99e Initial load duke parents: diff changeset	13130 ins_encode();
a61af66fc99e Initial load duke parents: diff changeset	13131 ins_pipe( empty );
a61af66fc99e Initial load duke parents: diff changeset	13132 %}
a61af66fc99e Initial load duke parents: diff changeset	13133
a61af66fc99e Initial load duke parents: diff changeset	13134
a61af66fc99e Initial load duke parents: diff changeset	13135 // Rethrow exception:
a61af66fc99e Initial load duke parents: diff changeset	13136 // The exception oop will come in the first argument position.
a61af66fc99e Initial load duke parents: diff changeset	13137 // Then JUMP (not call) to the rethrow stub code.
a61af66fc99e Initial load duke parents: diff changeset	13138 instruct RethrowException()
a61af66fc99e Initial load duke parents: diff changeset	13139 %{
a61af66fc99e Initial load duke parents: diff changeset	13140 match(Rethrow);
a61af66fc99e Initial load duke parents: diff changeset	13141
a61af66fc99e Initial load duke parents: diff changeset	13142 // use the following format syntax
a61af66fc99e Initial load duke parents: diff changeset	13143 format %{ "JMP rethrow_stub" %}
a61af66fc99e Initial load duke parents: diff changeset	13144 ins_encode(enc_rethrow);
a61af66fc99e Initial load duke parents: diff changeset	13145 ins_pipe( pipe_jmp );
a61af66fc99e Initial load duke parents: diff changeset	13146 %}
a61af66fc99e Initial load duke parents: diff changeset	13147
a61af66fc99e Initial load duke parents: diff changeset	13148 // inlined locking and unlocking
a61af66fc99e Initial load duke parents: diff changeset	13149
14909 4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	13150
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	13151 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	13152 match( Set cr (FastLock object box) );
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	13153 effect( TEMP tmp, TEMP scr, USE_KILL box );
0 a61af66fc99e Initial load duke parents: diff changeset	13154 ins_cost(300);
4777 e9a5e0a812c8 7125896: Eliminate nested locks kvn parents: 4763 diff changeset	13155 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
14909 4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	13156 ins_encode( Fast_Lock(object,box,tmp,scr) );
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	13157 ins_pipe( pipe_slow );
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	13158 %}
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	13159
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	13160 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	13161 match( Set cr (FastUnlock object box) );
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	13162 effect( TEMP tmp, USE_KILL box );
0 a61af66fc99e Initial load duke parents: diff changeset	13163 ins_cost(300);
4777 e9a5e0a812c8 7125896: Eliminate nested locks kvn parents: 4763 diff changeset	13164 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
14909 4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	13165 ins_encode( Fast_Unlock(object,box,tmp) );
4ca6dc0799b6 Backout jdk9 merge Gilles Duboscq <duboscq@ssw.jku.at> parents: 14495 diff changeset	13166 ins_pipe( pipe_slow );
0 a61af66fc99e Initial load duke parents: diff changeset	13167 %}
a61af66fc99e Initial load duke parents: diff changeset	13168
a61af66fc99e Initial load duke parents: diff changeset	13169
a61af66fc99e Initial load duke parents: diff changeset	13170
a61af66fc99e Initial load duke parents: diff changeset	13171 // ============================================================================
a61af66fc99e Initial load duke parents: diff changeset	13172 // Safepoint Instruction
a61af66fc99e Initial load duke parents: diff changeset	13173 instruct safePoint_poll(eFlagsReg cr) %{
a61af66fc99e Initial load duke parents: diff changeset	13174 match(SafePoint);
a61af66fc99e Initial load duke parents: diff changeset	13175 effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	13176
a61af66fc99e Initial load duke parents: diff changeset	13177 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
a61af66fc99e Initial load duke parents: diff changeset	13178 // On SPARC that might be acceptable as we can generate the address with
a61af66fc99e Initial load duke parents: diff changeset	13179 // just a sethi, saving an or. By polling at offset 0 we can end up
a61af66fc99e Initial load duke parents: diff changeset	13180 // putting additional pressure on the index-0 in the D$. Because of
a61af66fc99e Initial load duke parents: diff changeset	13181 // alignment (just like the situation at hand) the lower indices tend
a61af66fc99e Initial load duke parents: diff changeset	13182 // to see more traffic. It'd be better to change the polling address
a61af66fc99e Initial load duke parents: diff changeset	13183 // to offset 0 of the last $line in the polling page.
a61af66fc99e Initial load duke parents: diff changeset	13184
a61af66fc99e Initial load duke parents: diff changeset	13185 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
a61af66fc99e Initial load duke parents: diff changeset	13186 ins_cost(125);
a61af66fc99e Initial load duke parents: diff changeset	13187 size(6) ;
a61af66fc99e Initial load duke parents: diff changeset	13188 ins_encode( Safepoint_Poll() );
a61af66fc99e Initial load duke parents: diff changeset	13189 ins_pipe( ialu_reg_mem );
a61af66fc99e Initial load duke parents: diff changeset	13190 %}
a61af66fc99e Initial load duke parents: diff changeset	13191
4950 9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13192
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13193 // ============================================================================
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13194 // This name is KNOWN by the ADLC and cannot be changed.
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13195 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13196 // for this guy.
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13197 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13198 match(Set dst (ThreadLocal));
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13199 effect(DEF dst, KILL cr);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13200
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13201 format %{ "MOV $dst, Thread::current()" %}
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13202 ins_encode %{
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13203 Register dstReg = as_Register($dst$$reg);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13204 __ get_thread(dstReg);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13205 %}
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13206 ins_pipe( ialu_reg_fat );
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13207 %}
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13208
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13209
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4947 diff changeset	13210
0 a61af66fc99e Initial load duke parents: diff changeset	13211 //----------PEEPHOLE RULES-----------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	13212 // These must follow all instruction definitions as they use the names
a61af66fc99e Initial load duke parents: diff changeset	13213 // defined in the instructions definitions.
a61af66fc99e Initial load duke parents: diff changeset	13214 //
605 98cb887364d3 6810672: Comment typos twisti parents: 570 diff changeset	13215 // peepmatch ( root_instr_name [preceding_instruction]* );
0 a61af66fc99e Initial load duke parents: diff changeset	13216 //
a61af66fc99e Initial load duke parents: diff changeset	13217 // peepconstraint %{
a61af66fc99e Initial load duke parents: diff changeset	13218 // (instruction_number.operand_name relational_op instruction_number.operand_name
a61af66fc99e Initial load duke parents: diff changeset	13219 // [, ...] );
a61af66fc99e Initial load duke parents: diff changeset	13220 // // instruction numbers are zero-based using left to right order in peepmatch
a61af66fc99e Initial load duke parents: diff changeset	13221 //
a61af66fc99e Initial load duke parents: diff changeset	13222 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
a61af66fc99e Initial load duke parents: diff changeset	13223 // // provide an instruction_number.operand_name for each operand that appears
a61af66fc99e Initial load duke parents: diff changeset	13224 // // in the replacement instruction's match rule
a61af66fc99e Initial load duke parents: diff changeset	13225 //
a61af66fc99e Initial load duke parents: diff changeset	13226 // ---------VM FLAGS---------------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	13227 //
a61af66fc99e Initial load duke parents: diff changeset	13228 // All peephole optimizations can be turned off using -XX:-OptoPeephole
a61af66fc99e Initial load duke parents: diff changeset	13229 //
a61af66fc99e Initial load duke parents: diff changeset	13230 // Each peephole rule is given an identifying number starting with zero and
a61af66fc99e Initial load duke parents: diff changeset	13231 // increasing by one in the order seen by the parser. An individual peephole
a61af66fc99e Initial load duke parents: diff changeset	13232 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
a61af66fc99e Initial load duke parents: diff changeset	13233 // on the command-line.
a61af66fc99e Initial load duke parents: diff changeset	13234 //
a61af66fc99e Initial load duke parents: diff changeset	13235 // ---------CURRENT LIMITATIONS----------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	13236 //
a61af66fc99e Initial load duke parents: diff changeset	13237 // Only match adjacent instructions in same basic block
a61af66fc99e Initial load duke parents: diff changeset	13238 // Only equality constraints
a61af66fc99e Initial load duke parents: diff changeset	13239 // Only constraints between operands, not (0.dest_reg == EAX_enc)
a61af66fc99e Initial load duke parents: diff changeset	13240 // Only one replacement instruction
a61af66fc99e Initial load duke parents: diff changeset	13241 //
a61af66fc99e Initial load duke parents: diff changeset	13242 // ---------EXAMPLE----------------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	13243 //
a61af66fc99e Initial load duke parents: diff changeset	13244 // // pertinent parts of existing instructions in architecture description
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	13245 // instruct movI(rRegI dst, rRegI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	13246 // match(Set dst (CopyI src));
a61af66fc99e Initial load duke parents: diff changeset	13247 // %}
a61af66fc99e Initial load duke parents: diff changeset	13248 //
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	13249 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
0 a61af66fc99e Initial load duke parents: diff changeset	13250 // match(Set dst (AddI dst src));
a61af66fc99e Initial load duke parents: diff changeset	13251 // effect(KILL cr);
a61af66fc99e Initial load duke parents: diff changeset	13252 // %}
a61af66fc99e Initial load duke parents: diff changeset	13253 //
a61af66fc99e Initial load duke parents: diff changeset	13254 // // Change (inc mov) to lea
a61af66fc99e Initial load duke parents: diff changeset	13255 // peephole %{
a61af66fc99e Initial load duke parents: diff changeset	13256 // // increment preceeded by register-register move
a61af66fc99e Initial load duke parents: diff changeset	13257 // peepmatch ( incI_eReg movI );
a61af66fc99e Initial load duke parents: diff changeset	13258 // // require that the destination register of the increment
a61af66fc99e Initial load duke parents: diff changeset	13259 // // match the destination register of the move
a61af66fc99e Initial load duke parents: diff changeset	13260 // peepconstraint ( 0.dst == 1.dst );
a61af66fc99e Initial load duke parents: diff changeset	13261 // // construct a replacement instruction that sets
a61af66fc99e Initial load duke parents: diff changeset	13262 // // the destination to ( move's source register + one )
a61af66fc99e Initial load duke parents: diff changeset	13263 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
a61af66fc99e Initial load duke parents: diff changeset	13264 // %}
a61af66fc99e Initial load duke parents: diff changeset	13265 //
a61af66fc99e Initial load duke parents: diff changeset	13266 // Implementation no longer uses movX instructions since
a61af66fc99e Initial load duke parents: diff changeset	13267 // machine-independent system no longer uses CopyX nodes.
a61af66fc99e Initial load duke parents: diff changeset	13268 //
a61af66fc99e Initial load duke parents: diff changeset	13269 // peephole %{
a61af66fc99e Initial load duke parents: diff changeset	13270 // peepmatch ( incI_eReg movI );
a61af66fc99e Initial load duke parents: diff changeset	13271 // peepconstraint ( 0.dst == 1.dst );
a61af66fc99e Initial load duke parents: diff changeset	13272 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
a61af66fc99e Initial load duke parents: diff changeset	13273 // %}
a61af66fc99e Initial load duke parents: diff changeset	13274 //
a61af66fc99e Initial load duke parents: diff changeset	13275 // peephole %{
a61af66fc99e Initial load duke parents: diff changeset	13276 // peepmatch ( decI_eReg movI );
a61af66fc99e Initial load duke parents: diff changeset	13277 // peepconstraint ( 0.dst == 1.dst );
a61af66fc99e Initial load duke parents: diff changeset	13278 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
a61af66fc99e Initial load duke parents: diff changeset	13279 // %}
a61af66fc99e Initial load duke parents: diff changeset	13280 //
a61af66fc99e Initial load duke parents: diff changeset	13281 // peephole %{
a61af66fc99e Initial load duke parents: diff changeset	13282 // peepmatch ( addI_eReg_imm movI );
a61af66fc99e Initial load duke parents: diff changeset	13283 // peepconstraint ( 0.dst == 1.dst );
a61af66fc99e Initial load duke parents: diff changeset	13284 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
a61af66fc99e Initial load duke parents: diff changeset	13285 // %}
a61af66fc99e Initial load duke parents: diff changeset	13286 //
a61af66fc99e Initial load duke parents: diff changeset	13287 // peephole %{
a61af66fc99e Initial load duke parents: diff changeset	13288 // peepmatch ( addP_eReg_imm movP );
a61af66fc99e Initial load duke parents: diff changeset	13289 // peepconstraint ( 0.dst == 1.dst );
a61af66fc99e Initial load duke parents: diff changeset	13290 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
a61af66fc99e Initial load duke parents: diff changeset	13291 // %}
a61af66fc99e Initial load duke parents: diff changeset	13292
a61af66fc99e Initial load duke parents: diff changeset	13293 // // Change load of spilled value to only a spill
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	13294 // instruct storeI(memory mem, rRegI src) %{
0 a61af66fc99e Initial load duke parents: diff changeset	13295 // match(Set mem (StoreI mem src));
a61af66fc99e Initial load duke parents: diff changeset	13296 // %}
a61af66fc99e Initial load duke parents: diff changeset	13297 //
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 6143 diff changeset	13298 // instruct loadI(rRegI dst, memory mem) %{
0 a61af66fc99e Initial load duke parents: diff changeset	13299 // match(Set dst (LoadI mem));
a61af66fc99e Initial load duke parents: diff changeset	13300 // %}
a61af66fc99e Initial load duke parents: diff changeset	13301 //
a61af66fc99e Initial load duke parents: diff changeset	13302 peephole %{
a61af66fc99e Initial load duke parents: diff changeset	13303 peepmatch ( loadI storeI );
a61af66fc99e Initial load duke parents: diff changeset	13304 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
a61af66fc99e Initial load duke parents: diff changeset	13305 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
a61af66fc99e Initial load duke parents: diff changeset	13306 %}
a61af66fc99e Initial load duke parents: diff changeset	13307
a61af66fc99e Initial load duke parents: diff changeset	13308 //----------SMARTSPILL RULES---------------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	13309 // These must follow all instruction definitions as they use the names
a61af66fc99e Initial load duke parents: diff changeset	13310 // defined in the instructions definitions.

Mercurial > hg > truffle

annotate src/cpu/x86/vm/x86_32.ad @ 17524:89152779163c