Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sparc.ad @ 19299:8e4f683e16d9
Truffle-DSL: fixed warning
author | Christian Humer <christian.humer@gmail.com> |
---|---|
date | Wed, 11 Feb 2015 18:10:02 +0100 |
parents | 52b4284cb496 |
children | 7848fc12602b |
rev | line source |
---|---|
0 | 1 // |
9154 | 2 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved. |
0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 // | |
5 // This code is free software; you can redistribute it and/or modify it | |
6 // under the terms of the GNU General Public License version 2 only, as | |
7 // published by the Free Software Foundation. | |
8 // | |
9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 // version 2 for more details (a copy is included in the LICENSE file that | |
13 // accompanied this code). | |
14 // | |
15 // You should have received a copy of the GNU General Public License version | |
16 // 2 along with this work; if not, write to the Free Software Foundation, | |
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 // | |
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
20 // or visit www.oracle.com if you need additional information or have any |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
21 // questions. |
0 | 22 // |
23 // | |
24 | |
25 // SPARC Architecture Description File | |
26 | |
27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
28 // This information is used by the matcher and the register allocator to | |
29 // describe individual registers and classes of registers within the target | |
30 // archtecture. | |
31 register %{ | |
32 //----------Architecture Description Register Definitions---------------------- | |
33 // General Registers | |
34 // "reg_def" name ( register save type, C convention save type, | |
35 // ideal register type, encoding, vm name ); | |
36 // Register Save Types: | |
37 // | |
38 // NS = No-Save: The register allocator assumes that these registers | |
39 // can be used without saving upon entry to the method, & | |
40 // that they do not need to be saved at call sites. | |
41 // | |
42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
43 // can be used without saving upon entry to the method, | |
44 // but that they must be saved at call sites. | |
45 // | |
46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
47 // must be saved before using them upon entry to the | |
48 // method, but they do not need to be saved at call | |
49 // sites. | |
50 // | |
51 // AS = Always-Save: The register allocator assumes that these registers | |
52 // must be saved before using them upon entry to the | |
53 // method, & that they must be saved at call sites. | |
54 // | |
55 // Ideal Register Type is used to determine how to save & restore a | |
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
58 // | |
59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
60 | |
61 | |
62 // ---------------------------- | |
63 // Integer/Long Registers | |
64 // ---------------------------- | |
65 | |
66 // Need to expose the hi/lo aspect of 64-bit registers | |
67 // This register set is used for both the 64-bit build and | |
68 // the 32-bit build with 1-register longs. | |
69 | |
70 // Global Registers 0-7 | |
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
87 | |
88 // Output Registers 0-7 | |
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
105 | |
106 // Local Registers 0-7 | |
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
123 | |
124 // Input Registers 0-7 | |
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
141 | |
142 // ---------------------------- | |
143 // Float/Double Registers | |
144 // ---------------------------- | |
145 | |
146 // Float Registers | |
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
179 | |
180 // Double Registers | |
181 // The rules of ADL require that double registers be defined in pairs. | |
182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
183 // single float registers. In each pair, ADLC-assigned register numbers | |
184 // must be adjacent, with the lower number even. Finally, when the | |
185 // CPU stores such a register pair to memory, the word associated with | |
186 // the lower ADLC-assigned number must be stored to the lower address. | |
187 | |
188 // These definitions specify the actual bit encodings of the sparc | |
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
190 // wants 0-63, so we have to convert every time we want to use fp regs | |
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
605 | 192 // 255 is a flag meaning "don't go here". |
0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
194 // the place in the sparc stack crawler that asserts on the 255 is | |
195 // fixed up. | |
1007
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
1ce3281a8e93
6880034: SIGBUS during deoptimisation at a safepoint on 64bit-SPARC
kvn
parents:
986
diff
changeset
|
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
0 | 228 |
229 | |
230 // ---------------------------- | |
231 // Special Registers | |
232 // Condition Codes Flag Registers | |
233 // I tried to break out ICC and XCC but it's not very pretty. | |
234 // Every Sparc instruction which defs/kills one also kills the other. | |
235 // Hence every compare instruction which defs one kind of flags ends | |
236 // up needing a kill of the other. | |
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
238 | |
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
243 | |
244 // ---------------------------- | |
245 // Specify the enum values for the registers. These enums are only used by the | |
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
247 // for visibility to the rest of the vm. The order of this enum influences the | |
248 // register allocator so having the freedom to set this order and not be stuck | |
249 // with the order that is natural for the rest of the vm is worth it. | |
250 alloc_class chunk0( | |
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
255 | |
256 // Note that a register is not allocatable unless it is also mentioned | |
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
258 | |
259 alloc_class chunk1( | |
260 // The first registers listed here are those most likely to be used | |
261 // as temporaries. We move F0..F7 away from the front of the list, | |
262 // to reduce the likelihood of interferences with parameters and | |
263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
264 // since they are used for return values. | |
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
274 | |
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
276 | |
277 //----------Architecture Description Register Classes-------------------------- | |
278 // Several register classes are automatically defined based upon information in | |
279 // this architecture description. | |
280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
283 // | |
284 | |
285 // G0 is not included in integer class since it has special meaning. | |
286 reg_class g0_reg(R_G0); | |
287 | |
288 // ---------------------------- | |
289 // Integer Register Classes | |
290 // ---------------------------- | |
291 // Exclusions from i_reg: | |
292 // R_G0: hardwired zero | |
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
294 // R_G6: reserved by Solaris ABI to tools | |
295 // R_G7: reserved by Solaris ABI to libthread | |
296 // R_O7: Used as a temp in many encodings | |
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
298 | |
299 // Class for all integer registers, except the G registers. This is used for | |
300 // encodings which use G registers as temps. The regular inputs to such | |
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
302 // will not put an input into a temp register. | |
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
304 | |
305 reg_class g1_regI(R_G1); | |
306 reg_class g3_regI(R_G3); | |
307 reg_class g4_regI(R_G4); | |
308 reg_class o0_regI(R_O0); | |
309 reg_class o7_regI(R_O7); | |
310 | |
311 // ---------------------------- | |
312 // Pointer Register Classes | |
313 // ---------------------------- | |
314 #ifdef _LP64 | |
315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
320 // Lock encodings use G3 and G4 internally | |
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
326 // It is also used for memory addressing, allowing direct TLS addressing. | |
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
332 // We use it to save R_G2 across calls out of Java. | |
333 reg_class l7_regP(R_L7H,R_L7); | |
334 | |
335 // Other special pointer regs | |
336 reg_class g1_regP(R_G1H,R_G1); | |
337 reg_class g2_regP(R_G2H,R_G2); | |
338 reg_class g3_regP(R_G3H,R_G3); | |
339 reg_class g4_regP(R_G4H,R_G4); | |
340 reg_class g5_regP(R_G5H,R_G5); | |
341 reg_class i0_regP(R_I0H,R_I0); | |
342 reg_class o0_regP(R_O0H,R_O0); | |
343 reg_class o1_regP(R_O1H,R_O1); | |
344 reg_class o2_regP(R_O2H,R_O2); | |
345 reg_class o7_regP(R_O7H,R_O7); | |
346 | |
347 #else // _LP64 | |
348 // 32-bit build means 32-bit pointers means 1 register. | |
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
353 // Lock encodings use G3 and G4 internally | |
354 reg_class lock_ptr_reg(R_G1, R_G5, | |
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
359 // It is also used for memory addressing, allowing direct TLS addressing. | |
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
365 // We use it to save R_G2 across calls out of Java. | |
366 reg_class l7_regP(R_L7); | |
367 | |
368 // Other special pointer regs | |
369 reg_class g1_regP(R_G1); | |
370 reg_class g2_regP(R_G2); | |
371 reg_class g3_regP(R_G3); | |
372 reg_class g4_regP(R_G4); | |
373 reg_class g5_regP(R_G5); | |
374 reg_class i0_regP(R_I0); | |
375 reg_class o0_regP(R_O0); | |
376 reg_class o1_regP(R_O1); | |
377 reg_class o2_regP(R_O2); | |
378 reg_class o7_regP(R_O7); | |
379 #endif // _LP64 | |
380 | |
381 | |
382 // ---------------------------- | |
383 // Long Register Classes | |
384 // ---------------------------- | |
385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
389 #ifdef _LP64 | |
390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
394 #endif // _LP64 | |
395 ); | |
396 | |
397 reg_class g1_regL(R_G1H,R_G1); | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
398 reg_class g3_regL(R_G3H,R_G3); |
0 | 399 reg_class o2_regL(R_O2H,R_O2); |
400 reg_class o7_regL(R_O7H,R_O7); | |
401 | |
402 // ---------------------------- | |
403 // Special Class for Condition Code Flags Register | |
404 reg_class int_flags(CCR); | |
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
406 reg_class float_flag0(FCC0); | |
407 | |
408 | |
409 // ---------------------------- | |
410 // Float Point Register Classes | |
411 // ---------------------------- | |
412 // Skip F30/F31, they are reserved for mem-mem copies | |
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
414 | |
415 // Paired floating point registers--they show up in the same order as the floats, | |
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
422 ); | |
423 | |
424 // Paired floating point registers--they show up in the same order as the floats, | |
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
3804 | 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); |
0 | 429 %} |
430 | |
431 //----------DEFINITION BLOCK--------------------------------------------------- | |
432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
434 // Format: | |
435 // int_def <name> ( <int_value>, <expression>); | |
436 // Generated Code in ad_<arch>.hpp | |
437 // #define <name> (<expression>) | |
438 // // value == <int_value> | |
439 // Generated code in ad_<arch>.cpp adlc_verification() | |
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
441 // | |
442 definitions %{ | |
443 // The default cost (of an ALU instruction). | |
444 int_def DEFAULT_COST ( 100, 100); | |
445 int_def HUGE_COST (1000000, 1000000); | |
446 | |
447 // Memory refs are twice as expensive as run-of-the-mill. | |
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
449 | |
450 // Branches are even more expensive. | |
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
453 %} | |
454 | |
455 | |
456 //----------SOURCE BLOCK------------------------------------------------------- | |
457 // This is a block of C++ code which provides values, functions, and | |
458 // definitions necessary in the rest of the architecture description | |
459 source_hpp %{ | |
17809
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
460 // Header information of the source block. |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
461 // Method declarations/definitions which are used outside |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
462 // the ad-scope can conveniently be defined here. |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
463 // |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
464 // To keep related declarations/definitions/uses close together, |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
465 // we switch between source %{ }% and source_hpp %{ }% freely as needed. |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
466 |
0 | 467 // Must be visible to the DFA in dfa_sparc.cpp |
468 extern bool can_branch_register( Node *bol, Node *cmp ); | |
469 | |
3892 | 470 extern bool use_block_zeroing(Node* count); |
471 | |
0 | 472 // Macros to extract hi & lo halves from a long pair. |
473 // G0 is not part of any long pair, so assert on that. | |
605 | 474 // Prevents accidentally using G1 instead of G0. |
0 | 475 #define LONG_HI_REG(x) (x) |
476 #define LONG_LO_REG(x) (x) | |
477 | |
17809
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
478 class CallStubImpl { |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
479 |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
480 //-------------------------------------------------------------- |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
481 //---< Used for optimization in Compile::Shorten_branches >--- |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
482 //-------------------------------------------------------------- |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
483 |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
484 public: |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
485 // Size of call trampoline stub. |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
486 static uint size_call_trampoline() { |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
487 return 0; // no call trampolines on this platform |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
488 } |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
489 |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
490 // number of relocations needed by a call trampoline stub |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
491 static uint reloc_call_trampoline() { |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
492 return 0; // no call trampolines on this platform |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
493 } |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
494 }; |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
495 |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
496 class HandlerImpl { |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
497 |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
498 public: |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
499 |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
500 static int emit_exception_handler(CodeBuffer &cbuf); |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
501 static int emit_deopt_handler(CodeBuffer& cbuf); |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
502 |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
503 static uint size_exception_handler() { |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
504 if (TraceJumps) { |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
505 return (400); // just a guess |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
506 } |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
507 return ( NativeJump::instruction_size ); // sethi;jmp;nop |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
508 } |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
509 |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
510 static uint size_deopt_handler() { |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
511 if (TraceJumps) { |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
512 return (400); // just a guess |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
513 } |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
514 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
515 } |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
516 }; |
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
517 |
0 | 518 %} |
519 | |
520 source %{ | |
521 #define __ _masm. | |
522 | |
523 // tertiary op of a LoadP or StoreP encoding | |
524 #define REGP_OP true | |
525 | |
526 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
527 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
528 static Register reg_to_register_object(int register_encoding); | |
529 | |
530 // Used by the DFA in dfa_sparc.cpp. | |
531 // Check for being able to use a V9 branch-on-register. Requires a | |
532 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
533 // extended. Doesn't work following an integer ADD, for example, because of | |
534 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
535 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
536 // replace them with zero, which could become sign-extension in a different OS | |
537 // release. There's no obvious reason why an interrupt will ever fill these | |
538 // bits with non-zero junk (the registers are reloaded with standard LD | |
539 // instructions which either zero-fill or sign-fill). | |
540 bool can_branch_register( Node *bol, Node *cmp ) { | |
541 if( !BranchOnRegister ) return false; | |
542 #ifdef _LP64 | |
543 if( cmp->Opcode() == Op_CmpP ) | |
544 return true; // No problems with pointer compares | |
545 #endif | |
546 if( cmp->Opcode() == Op_CmpL ) | |
547 return true; // No problems with long compares | |
548 | |
549 if( !SparcV9RegsHiBitsZero ) return false; | |
550 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
551 bol->as_Bool()->_test._test != BoolTest::eq ) | |
552 return false; | |
553 | |
554 // Check for comparing against a 'safe' value. Any operation which | |
555 // clears out the high word is safe. Thus, loads and certain shifts | |
556 // are safe, as are non-negative constants. Any operation which | |
557 // preserves zero bits in the high word is safe as long as each of its | |
558 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
559 // inputs are safe. At present, the only important case to recognize | |
560 // seems to be loads. Constants should fold away, and shifts & | |
561 // logicals can use the 'cc' forms. | |
562 Node *x = cmp->in(1); | |
563 if( x->is_Load() ) return true; | |
564 if( x->is_Phi() ) { | |
565 for( uint i = 1; i < x->req(); i++ ) | |
566 if( !x->in(i)->is_Load() ) | |
567 return false; | |
568 return true; | |
569 } | |
570 return false; | |
571 } | |
572 | |
3892 | 573 bool use_block_zeroing(Node* count) { |
574 // Use BIS for zeroing if count is not constant | |
575 // or it is >= BlockZeroingLowLimit. | |
576 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit); | |
577 } | |
578 | |
0 | 579 // **************************************************************************** |
580 | |
581 // REQUIRED FUNCTIONALITY | |
582 | |
583 // !!!!! Special hack to get all type of calls to specify the byte offset | |
584 // from the start of the call to the point where the return address | |
585 // will point. | |
586 // The "return address" is the address of the call instruction, plus 8. | |
587 | |
588 int MachCallStaticJavaNode::ret_addr_offset() { | |
1567 | 589 int offset = NativeCall::instruction_size; // call; delay slot |
590 if (_method_handle_invoke) | |
591 offset += 4; // restore SP | |
592 return offset; | |
0 | 593 } |
594 | |
595 int MachCallDynamicJavaNode::ret_addr_offset() { | |
596 int vtable_index = this->_vtable_index; | |
597 if (vtable_index < 0) { | |
598 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
599 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
0 | 600 return (NativeMovConstReg::instruction_size + |
601 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
602 } else { | |
603 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
604 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
0 | 605 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
606 int klass_load_size; |
12226
7944aba7ba41
8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents:
12056
diff
changeset
|
607 if (UseCompressedClassPointers) { |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
608 assert(Universe::heap() != NULL, "java heap should be initialized"); |
12056
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
10997
diff
changeset
|
609 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
610 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
611 klass_load_size = 1*BytesPerInstWord; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
612 } |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
613 if (Assembler::is_simm13(v_off)) { |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
614 return klass_load_size + |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
615 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
0 | 616 NativeCall::instruction_size); // call; delay slot |
617 } else { | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
618 return klass_load_size + |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
619 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
0 | 620 NativeCall::instruction_size); // call; delay slot |
621 } | |
622 } | |
623 } | |
624 | |
625 int MachCallRuntimeNode::ret_addr_offset() { | |
626 #ifdef _LP64 | |
2121
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
627 if (MacroAssembler::is_far_target(entry_point())) { |
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
628 return NativeFarCall::instruction_size; |
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
629 } else { |
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
630 return NativeCall::instruction_size; |
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
631 } |
0 | 632 #else |
633 return NativeCall::instruction_size; // call; delay slot | |
634 #endif | |
635 } | |
636 | |
637 // Indicate if the safepoint node needs the polling page as an input. | |
638 // Since Sparc does not have absolute addressing, it does. | |
639 bool SafePointNode::needs_polling_address_input() { | |
640 return true; | |
641 } | |
642 | |
643 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
644 void emit_break(CodeBuffer &cbuf) { | |
645 MacroAssembler _masm(&cbuf); | |
646 __ breakpoint_trap(); | |
647 } | |
648 | |
649 #ifndef PRODUCT | |
650 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
651 st->print("TA"); | |
652 } | |
653 #endif | |
654 | |
655 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
656 emit_break(cbuf); | |
657 } | |
658 | |
659 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
660 return MachNode::size(ra_); | |
661 } | |
662 | |
663 // Traceable jump | |
664 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
665 MacroAssembler _masm(&cbuf); | |
666 Register rdest = reg_to_register_object(jump_target); | |
667 __ JMP(rdest, 0); | |
668 __ delayed()->nop(); | |
669 } | |
670 | |
671 // Traceable jump and set exception pc | |
672 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
673 MacroAssembler _masm(&cbuf); | |
674 Register rdest = reg_to_register_object(jump_target); | |
675 __ JMP(rdest, 0); | |
676 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
677 } | |
678 | |
679 void emit_nop(CodeBuffer &cbuf) { | |
680 MacroAssembler _masm(&cbuf); | |
681 __ nop(); | |
682 } | |
683 | |
684 void emit_illtrap(CodeBuffer &cbuf) { | |
685 MacroAssembler _masm(&cbuf); | |
686 __ illtrap(0); | |
687 } | |
688 | |
689 | |
690 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
691 assert(n->rule() != loadUB_rule, ""); | |
692 | |
693 intptr_t offset = 0; | |
694 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
695 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
696 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
697 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
698 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
699 atype = atype->add_offset(offset); | |
700 assert(disp32 == offset, "wrong disp32"); | |
701 return atype->_offset; | |
702 } | |
703 | |
704 | |
705 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
706 assert(n->rule() != loadUB_rule, ""); | |
707 | |
708 intptr_t offset = 0; | |
709 Node* addr = n->in(2); | |
710 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
711 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
712 Node* a = addr->in(2/*AddPNode::Address*/); | |
713 Node* o = addr->in(3/*AddPNode::Offset*/); | |
714 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
715 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
716 assert(atype->isa_oop_ptr(), "still an oop"); | |
717 } | |
718 offset = atype->is_ptr()->_offset; | |
719 if (offset != Type::OffsetBot) offset += disp32; | |
720 return offset; | |
721 } | |
722 | |
2008 | 723 static inline jdouble replicate_immI(int con, int count, int width) { |
724 // Load a constant replicated "count" times with width "width" | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
725 assert(count*width == 8 && width <= 4, "sanity"); |
2008 | 726 int bit_width = width * 8; |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
727 jlong val = con; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
728 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits |
2008 | 729 for (int i = 0; i < count - 1; i++) { |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
730 val |= (val << bit_width); |
2008 | 731 } |
732 jdouble dval = *((jdouble*) &val); // coerce to double type | |
733 return dval; | |
734 } | |
735 | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
736 static inline jdouble replicate_immF(float con) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
737 // Replicate float con 2 times and pack into vector. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
738 int val = *((int*)&con); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
739 jlong lval = val; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
740 lval = (lval << 32) | (lval & 0xFFFFFFFFl); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
741 jdouble dval = *((jdouble*) &lval); // coerce to double type |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
742 return dval; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
743 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
744 |
0 | 745 // Standard Sparc opcode form2 field breakdown |
746 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
747 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
748 int op = (f30 << 30) | | |
749 (f29 << 29) | | |
750 (f25 << 25) | | |
751 (f22 << 22) | | |
752 (f20 << 20) | | |
753 (f19 << 19) | | |
754 (f0 << 0); | |
1748 | 755 cbuf.insts()->emit_int32(op); |
0 | 756 } |
757 | |
758 // Standard Sparc opcode form2 field breakdown | |
759 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
760 f0 >>= 10; // Drop 10 bits | |
761 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
762 int op = (f30 << 30) | | |
763 (f25 << 25) | | |
764 (f22 << 22) | | |
765 (f0 << 0); | |
1748 | 766 cbuf.insts()->emit_int32(op); |
0 | 767 } |
768 | |
769 // Standard Sparc opcode form3 field breakdown | |
770 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
771 int op = (f30 << 30) | | |
772 (f25 << 25) | | |
773 (f19 << 19) | | |
774 (f14 << 14) | | |
775 (f5 << 5) | | |
776 (f0 << 0); | |
1748 | 777 cbuf.insts()->emit_int32(op); |
0 | 778 } |
779 | |
780 // Standard Sparc opcode form3 field breakdown | |
781 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
782 simm13 &= (1<<13)-1; // Mask to 13 bits | |
783 int op = (f30 << 30) | | |
784 (f25 << 25) | | |
785 (f19 << 19) | | |
786 (f14 << 14) | | |
787 (1 << 13) | // bit to indicate immediate-mode | |
788 (simm13<<0); | |
1748 | 789 cbuf.insts()->emit_int32(op); |
0 | 790 } |
791 | |
792 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
793 simm10 &= (1<<10)-1; // Mask to 10 bits | |
794 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
795 } | |
796 | |
797 #ifdef ASSERT | |
798 // Helper function for VerifyOops in emit_form3_mem_reg | |
799 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
800 warning("VerifyOops encountered unexpected instruction:"); | |
801 n->dump(2); | |
802 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
803 } | |
804 #endif | |
805 | |
806 | |
14217
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
807 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary, |
0 | 808 int src1_enc, int disp32, int src2_enc, int dst_enc) { |
809 | |
810 #ifdef ASSERT | |
811 // The following code implements the +VerifyOops feature. | |
812 // It verifies oop values which are loaded into or stored out of | |
813 // the current method activation. +VerifyOops complements techniques | |
814 // like ScavengeALot, because it eagerly inspects oops in transit, | |
815 // as they enter or leave the stack, as opposed to ScavengeALot, | |
816 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
817 // For this reason, +VerifyOops can sometimes detect bugs very close | |
818 // to their point of creation. It can also serve as a cross-check | |
819 // on the validity of oop maps, when used toegether with ScavengeALot. | |
820 | |
821 // It would be good to verify oops at other points, especially | |
822 // when an oop is used as a base pointer for a load or store. | |
823 // This is presently difficult, because it is hard to know when | |
824 // a base address is biased or not. (If we had such information, | |
825 // it would be easy and useful to make a two-argument version of | |
826 // verify_oop which unbiases the base, and performs verification.) | |
827 | |
828 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
829 bool is_verified_oop_base = false; | |
830 bool is_verified_oop_load = false; | |
831 bool is_verified_oop_store = false; | |
832 int tmp_enc = -1; | |
833 if (VerifyOops && src1_enc != R_SP_enc) { | |
834 // classify the op, mainly for an assert check | |
835 int st_op = 0, ld_op = 0; | |
836 switch (primary) { | |
837 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
838 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
839 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
840 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
841 case Assembler::std_op3: st_op = Op_StoreL; break; | |
842 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
843 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
844 | |
845 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
846 case Assembler::ldub_op3: ld_op = Op_LoadUB; break; |
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
551
diff
changeset
|
847 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
0 | 848 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
849 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
850 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
851 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
852 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
853 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
854 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
855 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
856 | |
857 default: ShouldNotReachHere(); | |
858 } | |
859 if (tertiary == REGP_OP) { | |
860 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
861 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
862 else ShouldNotReachHere(); | |
863 if (st_op) { | |
864 // a store | |
865 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
866 Node* n2 = n->in(3); | |
867 if (n2 != NULL) { | |
868 const Type* t = n2->bottom_type(); | |
869 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
870 } | |
871 } else { | |
872 // a load | |
873 const Type* t = n->bottom_type(); | |
874 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
875 } | |
876 } | |
877 | |
878 if (ld_op) { | |
879 // a Load | |
880 // inputs are (0:control, 1:memory, 2:address) | |
881 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
882 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
883 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
884 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
885 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
886 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
887 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
888 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
889 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
890 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
891 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
892 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
893 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
3898 | 894 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) && |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
895 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) && |
0 | 896 !(n->rule() == loadUB_rule)) { |
897 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
898 } | |
899 } else if (st_op) { | |
900 // a Store | |
901 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
902 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
903 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
904 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
905 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
906 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
907 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) && |
0 | 908 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { |
909 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
910 } | |
911 } | |
912 | |
913 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
914 Node* addr = n->in(2); | |
915 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
916 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
917 if (atype != NULL) { | |
918 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
919 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
920 if (offset != offset_2) { | |
921 get_offset_from_base(n, atype, disp32); | |
922 get_offset_from_base_2(n, atype, disp32); | |
923 } | |
924 assert(offset == offset_2, "different offsets"); | |
925 if (offset == disp32) { | |
926 // we now know that src1 is a true oop pointer | |
927 is_verified_oop_base = true; | |
928 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
929 if( primary == Assembler::ldd_op3 ) { | |
930 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
931 } else { | |
932 tmp_enc = dst_enc; | |
933 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
934 assert(src1_enc != dst_enc, ""); | |
935 } | |
936 } | |
937 } | |
938 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
939 || offset == oopDesc::mark_offset_in_bytes())) { | |
940 // loading the mark should not be allowed either, but | |
941 // we don't check this since it conflicts with InlineObjectHash | |
942 // usage of LoadINode to get the mark. We could keep the | |
943 // check if we create a new LoadMarkNode | |
944 // but do not verify the object before its header is initialized | |
945 ShouldNotReachHere(); | |
946 } | |
947 } | |
948 } | |
949 } | |
950 } | |
951 #endif | |
952 | |
953 uint instr; | |
954 instr = (Assembler::ldst_op << 30) | |
955 | (dst_enc << 25) | |
956 | (primary << 19) | |
957 | (src1_enc << 14); | |
958 | |
959 uint index = src2_enc; | |
960 int disp = disp32; | |
961 | |
14217
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
962 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) { |
0 | 963 disp += STACK_BIAS; |
14217
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
964 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not |
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
965 if (!Assembler::is_simm13(disp)) { |
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
966 ra->C->record_method_not_compilable("unable to handle large constant offsets"); |
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
967 return; |
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
968 } |
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
969 } |
0 | 970 |
971 // We should have a compiler bailout here rather than a guarantee. | |
972 // Better yet would be some mechanism to handle variable-size matches correctly. | |
973 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
974 | |
975 if( disp == 0 ) { | |
976 // use reg-reg form | |
977 // bit 13 is already zero | |
978 instr |= index; | |
979 } else { | |
980 // use reg-imm form | |
981 instr |= 0x00002000; // set bit 13 to one | |
982 instr |= disp & 0x1FFF; | |
983 } | |
984 | |
1748 | 985 cbuf.insts()->emit_int32(instr); |
0 | 986 |
987 #ifdef ASSERT | |
988 { | |
989 MacroAssembler _masm(&cbuf); | |
990 if (is_verified_oop_base) { | |
991 __ verify_oop(reg_to_register_object(src1_enc)); | |
992 } | |
993 if (is_verified_oop_store) { | |
994 __ verify_oop(reg_to_register_object(dst_enc)); | |
995 } | |
996 if (tmp_enc != -1) { | |
997 __ mov(O7, reg_to_register_object(tmp_enc)); | |
998 } | |
999 if (is_verified_oop_load) { | |
1000 __ verify_oop(reg_to_register_object(dst_enc)); | |
1001 } | |
1002 } | |
1003 #endif | |
1004 } | |
1005 | |
2121
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
1006 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) { |
0 | 1007 // The method which records debug information at every safepoint |
1008 // expects the call to be the first instruction in the snippet as | |
1009 // it creates a PcDesc structure which tracks the offset of a call | |
1010 // from the start of the codeBlob. This offset is computed as | |
1011 // code_end() - code_begin() of the code which has been emitted | |
1012 // so far. | |
1013 // In this particular case we have skirted around the problem by | |
1014 // putting the "mov" instruction in the delay slot but the problem | |
1015 // may bite us again at some other point and a cleaner/generic | |
1016 // solution using relocations would be needed. | |
1017 MacroAssembler _masm(&cbuf); | |
1018 __ set_inst_mark(); | |
1019 | |
1020 // We flush the current window just so that there is a valid stack copy | |
1021 // the fact that the current window becomes active again instantly is | |
1022 // not a problem there is nothing live in it. | |
1023 | |
1024 #ifdef ASSERT | |
1025 int startpos = __ offset(); | |
1026 #endif /* ASSERT */ | |
1027 | |
2121
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
1028 __ call((address)entry_point, rtype); |
0 | 1029 |
1030 if (preserve_g2) __ delayed()->mov(G2, L7); | |
1031 else __ delayed()->nop(); | |
1032 | |
1033 if (preserve_g2) __ mov(L7, G2); | |
1034 | |
1035 #ifdef ASSERT | |
1036 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
1037 #ifdef _LP64 | |
1038 // Trash argument dump slots. | |
1039 __ set(0xb0b8ac0db0b8ac0d, G1); | |
1040 __ mov(G1, G5); | |
1041 __ stx(G1, SP, STACK_BIAS + 0x80); | |
1042 __ stx(G1, SP, STACK_BIAS + 0x88); | |
1043 __ stx(G1, SP, STACK_BIAS + 0x90); | |
1044 __ stx(G1, SP, STACK_BIAS + 0x98); | |
1045 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
1046 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
1047 #else // _LP64 | |
1048 // this is also a native call, so smash the first 7 stack locations, | |
1049 // and the various registers | |
1050 | |
1051 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
1052 // while [SP+0x44..0x58] are the argument dump slots. | |
1053 __ set((intptr_t)0xbaadf00d, G1); | |
1054 __ mov(G1, G5); | |
1055 __ sllx(G1, 32, G1); | |
1056 __ or3(G1, G5, G1); | |
1057 __ mov(G1, G5); | |
1058 __ stx(G1, SP, 0x40); | |
1059 __ stx(G1, SP, 0x48); | |
1060 __ stx(G1, SP, 0x50); | |
1061 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
1062 #endif // _LP64 | |
1063 } | |
1064 #endif /*ASSERT*/ | |
1065 } | |
1066 | |
1067 //============================================================================= | |
1068 // REQUIRED FUNCTIONALITY for encoding | |
1069 void emit_lo(CodeBuffer &cbuf, int val) { } | |
1070 void emit_hi(CodeBuffer &cbuf, int val) { } | |
1071 | |
1072 | |
1073 //============================================================================= | |
4121
db2e64ca2d5a
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
4114
diff
changeset
|
1074 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask(); |
2008 | 1075 |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1076 int Compile::ConstantTable::calculate_table_base_offset() const { |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1077 if (UseRDPCForConstantTableBase) { |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1078 // The table base offset might be less but then it fits into |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1079 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit). |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1080 return Assembler::min_simm13(); |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1081 } else { |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1082 int offset = -(size() / 2); |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1083 if (!Assembler::is_simm13(offset)) { |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1084 offset = Assembler::min_simm13(); |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1085 } |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1086 return offset; |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1087 } |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1088 } |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1089 |
14428
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
1090 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } |
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
1091 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { |
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
1092 ShouldNotReachHere(); |
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
1093 } |
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
1094 |
2008 | 1095 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
1096 Compile* C = ra_->C; | |
1097 Compile::ConstantTable& constant_table = C->constant_table(); | |
1098 MacroAssembler _masm(&cbuf); | |
1099 | |
1100 Register r = as_Register(ra_->get_encode(this)); | |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1101 CodeSection* consts_section = __ code()->consts(); |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1102 int consts_size = consts_section->align_at_start(consts_section->size()); |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1103 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); |
2008 | 1104 |
1105 if (UseRDPCForConstantTableBase) { | |
1106 // For the following RDPC logic to work correctly the consts | |
1107 // section must be allocated right before the insts section. This | |
1108 // assert checks for that. The layout and the SECT_* constants | |
1109 // are defined in src/share/vm/asm/codeBuffer.hpp. | |
1110 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); | |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1111 int insts_offset = __ offset(); |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1112 |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1113 // Layout: |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1114 // |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1115 // |----------- consts section ------------|----------- insts section -----------... |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1116 // |------ constant table -----|- padding -|------------------x---- |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1117 // \ current PC (RDPC instruction) |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1118 // |<------------- consts_size ----------->|<- insts_offset ->| |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1119 // \ table base |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1120 // The table base offset is later added to the load displacement |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1121 // so it has to be negative. |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1122 int table_base_offset = -(consts_size + insts_offset); |
2008 | 1123 int disp; |
1124 | |
1125 // If the displacement from the current PC to the constant table | |
1126 // base fits into simm13 we set the constant table base to the | |
1127 // current PC. | |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1128 if (Assembler::is_simm13(table_base_offset)) { |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1129 constant_table.set_table_base_offset(table_base_offset); |
2008 | 1130 disp = 0; |
1131 } else { | |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1132 // Otherwise we set the constant table base offset to the |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1133 // maximum negative displacement of load instructions to keep |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1134 // the disp as small as possible: |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1135 // |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1136 // |<------------- consts_size ----------->|<- insts_offset ->| |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1137 // |<--------- min_simm13 --------->|<-------- disp --------->| |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1138 // \ table base |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1139 table_base_offset = Assembler::min_simm13(); |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1140 constant_table.set_table_base_offset(table_base_offset); |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1141 disp = (consts_size + insts_offset) + table_base_offset; |
2008 | 1142 } |
1143 | |
1144 __ rdpc(r); | |
1145 | |
1146 if (disp != 0) { | |
1147 assert(r != O7, "need temporary"); | |
1148 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); | |
1149 } | |
1150 } | |
1151 else { | |
1152 // Materialize the constant table base. | |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1153 address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); |
2008 | 1154 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); |
1155 AddressLiteral base(baseaddr, rspec); | |
1156 __ set(base, r); | |
1157 } | |
1158 } | |
1159 | |
1160 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { | |
1161 if (UseRDPCForConstantTableBase) { | |
1162 // This is really the worst case but generally it's only 1 instruction. | |
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
1163 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; |
2008 | 1164 } else { |
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
1165 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; |
2008 | 1166 } |
1167 } | |
1168 | |
1169 #ifndef PRODUCT | |
1170 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
1171 char reg[128]; | |
1172 ra_->dump_register(this, reg); | |
1173 if (UseRDPCForConstantTableBase) { | |
1174 st->print("RDPC %s\t! constant table base", reg); | |
1175 } else { | |
1176 st->print("SET &constanttable,%s\t! constant table base", reg); | |
1177 } | |
1178 } | |
1179 #endif | |
1180 | |
1181 | |
1182 //============================================================================= | |
0 | 1183 |
1184 #ifndef PRODUCT | |
1185 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1186 Compile* C = ra_->C; | |
1187 | |
1188 for (int i = 0; i < OptoPrologueNops; i++) { | |
1189 st->print_cr("NOP"); st->print("\t"); | |
1190 } | |
1191 | |
1192 if( VerifyThread ) { | |
1193 st->print_cr("Verify_Thread"); st->print("\t"); | |
1194 } | |
1195 | |
17980
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17877
diff
changeset
|
1196 size_t framesize = C->frame_size_in_bytes(); |
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17877
diff
changeset
|
1197 int bangsize = C->bang_size_in_bytes(); |
0 | 1198 |
1199 // Calls to C2R adapters often do not accept exceptional returns. | |
1200 // We require that their callers must bang for them. But be careful, because | |
1201 // some VM calls (such as call site linkage) can use several kilobytes of | |
1202 // stack. But the stack safety zone should account for that. | |
1203 // See bugs 4446381, 4468289, 4497237. | |
17980
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17877
diff
changeset
|
1204 if (C->need_stack_bang(bangsize)) { |
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17877
diff
changeset
|
1205 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t"); |
0 | 1206 } |
1207 | |
1208 if (Assembler::is_simm13(-framesize)) { | |
1209 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
1210 } else { | |
1211 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
1212 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
1213 st->print ("SAVE R_SP,R_G3,R_SP"); | |
1214 } | |
1215 | |
1216 } | |
1217 #endif | |
1218 | |
1219 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1220 Compile* C = ra_->C; | |
1221 MacroAssembler _masm(&cbuf); | |
1222 | |
1223 for (int i = 0; i < OptoPrologueNops; i++) { | |
1224 __ nop(); | |
1225 } | |
1226 | |
1227 __ verify_thread(); | |
1228 | |
17980
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17877
diff
changeset
|
1229 size_t framesize = C->frame_size_in_bytes(); |
0 | 1230 assert(framesize >= 16*wordSize, "must have room for reg. save area"); |
1231 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
17980
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17877
diff
changeset
|
1232 int bangsize = C->bang_size_in_bytes(); |
0 | 1233 |
1234 // Calls to C2R adapters often do not accept exceptional returns. | |
1235 // We require that their callers must bang for them. But be careful, because | |
1236 // some VM calls (such as call site linkage) can use several kilobytes of | |
1237 // stack. But the stack safety zone should account for that. | |
1238 // See bugs 4446381, 4468289, 4497237. | |
17980
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17877
diff
changeset
|
1239 if (C->need_stack_bang(bangsize)) { |
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17877
diff
changeset
|
1240 __ generate_stack_overflow_check(bangsize); |
0 | 1241 } |
1242 | |
1243 if (Assembler::is_simm13(-framesize)) { | |
1244 __ save(SP, -framesize, SP); | |
1245 } else { | |
1246 __ sethi(-framesize & ~0x3ff, G3); | |
1247 __ add(G3, -framesize & 0x3ff, G3); | |
1248 __ save(SP, G3, SP); | |
1249 } | |
1250 C->set_frame_complete( __ offset() ); | |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1251 |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1252 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) { |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1253 // NOTE: We set the table base offset here because users might be |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1254 // emitted before MachConstantBaseNode. |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1255 Compile::ConstantTable& constant_table = C->constant_table(); |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1256 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1257 } |
0 | 1258 } |
1259 | |
1260 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
1261 return MachNode::size(ra_); | |
1262 } | |
1263 | |
1264 int MachPrologNode::reloc() const { | |
1265 return 10; // a large enough number | |
1266 } | |
1267 | |
1268 //============================================================================= | |
1269 #ifndef PRODUCT | |
1270 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1271 Compile* C = ra_->C; | |
1272 | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
1273 if(do_polling() && ra_->C->is_method_compilation()) { |
0 | 1274 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); |
1275 #ifdef _LP64 | |
1276 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
1277 #else | |
1278 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
1279 #endif | |
1280 } | |
1281 | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
1282 if(do_polling()) { |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
1283 if (UseCBCond && !ra_->C->is_method_compilation()) { |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
1284 st->print("NOP\n\t"); |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
1285 } |
0 | 1286 st->print("RET\n\t"); |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
1287 } |
0 | 1288 |
1289 st->print("RESTORE"); | |
1290 } | |
1291 #endif | |
1292 | |
1293 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1294 MacroAssembler _masm(&cbuf); | |
1295 Compile* C = ra_->C; | |
1296 | |
1297 __ verify_thread(); | |
1298 | |
1299 // If this does safepoint polling, then do it here | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
1300 if(do_polling() && ra_->C->is_method_compilation()) { |
727 | 1301 AddressLiteral polling_page(os::get_polling_page()); |
1302 __ sethi(polling_page, L0); | |
0 | 1303 __ relocate(relocInfo::poll_return_type); |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
1304 __ ld_ptr(L0, 0, G0); |
0 | 1305 } |
1306 | |
1307 // If this is a return, then stuff the restore in the delay slot | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
1308 if(do_polling()) { |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
1309 if (UseCBCond && !ra_->C->is_method_compilation()) { |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
1310 // Insert extra padding for the case when the epilogue is preceded by |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
1311 // a cbcond jump, which can't be followed by a CTI instruction |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
1312 __ nop(); |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
1313 } |
0 | 1314 __ ret(); |
1315 __ delayed()->restore(); | |
1316 } else { | |
1317 __ restore(); | |
1318 } | |
1319 } | |
1320 | |
1321 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
1322 return MachNode::size(ra_); | |
1323 } | |
1324 | |
1325 int MachEpilogNode::reloc() const { | |
1326 return 16; // a large enough number | |
1327 } | |
1328 | |
1329 const Pipeline * MachEpilogNode::pipeline() const { | |
1330 return MachNode::pipeline_class(); | |
1331 } | |
1332 | |
1333 int MachEpilogNode::safepoint_offset() const { | |
1334 assert( do_polling(), "no return for this epilog node"); | |
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
1335 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; |
0 | 1336 } |
1337 | |
1338 //============================================================================= | |
1339 | |
1340 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
1341 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
1342 static enum RC rc_class( OptoReg::Name reg ) { | |
1343 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
1344 if (OptoReg::is_stack(reg)) return rc_stack; | |
1345 VMReg r = OptoReg::as_VMReg(reg); | |
1346 if (r->is_Register()) return rc_int; | |
1347 assert(r->is_FloatRegister(), "must be"); | |
1348 return rc_float; | |
1349 } | |
1350 | |
14217
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
1351 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { |
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
1352 if (cbuf) { |
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
1353 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); |
0 | 1354 } |
1355 #ifndef PRODUCT | |
14217
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
1356 else if (!do_size) { |
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
1357 if (size != 0) st->print("\n\t"); |
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
1358 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); |
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
1359 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); |
0 | 1360 } |
1361 #endif | |
1362 return size+4; | |
1363 } | |
1364 | |
1365 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
1366 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
1367 #ifndef PRODUCT | |
1368 else if( !do_size ) { | |
1369 if( size != 0 ) st->print("\n\t"); | |
1370 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
1371 } | |
1372 #endif | |
1373 return size+4; | |
1374 } | |
1375 | |
1376 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
1377 PhaseRegAlloc *ra_, | |
1378 bool do_size, | |
1379 outputStream* st ) const { | |
1380 // Get registers to move | |
1381 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
1382 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
1383 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
1384 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
1385 | |
1386 enum RC src_second_rc = rc_class(src_second); | |
1387 enum RC src_first_rc = rc_class(src_first); | |
1388 enum RC dst_second_rc = rc_class(dst_second); | |
1389 enum RC dst_first_rc = rc_class(dst_first); | |
1390 | |
1391 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
1392 | |
1393 // Generate spill code! | |
1394 int size = 0; | |
1395 | |
1396 if( src_first == dst_first && src_second == dst_second ) | |
1397 return size; // Self copy, no move | |
1398 | |
1399 // -------------------------------------- | |
1400 // Check for mem-mem move. Load into unused float registers and fall into | |
1401 // the float-store case. | |
1402 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
1403 int offset = ra_->reg2offset(src_first); | |
1404 // Further check for aligned-adjacent pair, so we can use a double load | |
1405 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
1406 src_second = OptoReg::Name(R_F31_num); | |
1407 src_second_rc = rc_float; | |
1408 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
1409 } else { | |
1410 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
1411 } | |
1412 src_first = OptoReg::Name(R_F30_num); | |
1413 src_first_rc = rc_float; | |
1414 } | |
1415 | |
1416 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
1417 int offset = ra_->reg2offset(src_second); | |
1418 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
1419 src_second = OptoReg::Name(R_F31_num); | |
1420 src_second_rc = rc_float; | |
1421 } | |
1422 | |
1423 // -------------------------------------- | |
1424 // Check for float->int copy; requires a trip through memory | |
3804 | 1425 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { |
0 | 1426 int offset = frame::register_save_words*wordSize; |
3804 | 1427 if (cbuf) { |
0 | 1428 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); |
1429 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1430 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1431 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
1432 } | |
1433 #ifndef PRODUCT | |
3804 | 1434 else if (!do_size) { |
1435 if (size != 0) st->print("\n\t"); | |
0 | 1436 st->print( "SUB R_SP,16,R_SP\n"); |
1437 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1438 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1439 st->print("\tADD R_SP,16,R_SP\n"); | |
1440 } | |
1441 #endif | |
1442 size += 16; | |
1443 } | |
1444 | |
3804 | 1445 // Check for float->int copy on T4 |
1446 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { | |
1447 // Further check for aligned-adjacent pair, so we can use a double move | |
1448 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
1449 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st); | |
1450 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st); | |
1451 } | |
1452 // Check for int->float copy on T4 | |
1453 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { | |
1454 // Further check for aligned-adjacent pair, so we can use a double move | |
1455 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
1456 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st); | |
1457 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st); | |
1458 } | |
1459 | |
0 | 1460 // -------------------------------------- |
1461 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
1462 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
1463 // hardware does the flop for me. Doubles are always aligned, so no problem | |
1464 // there. Misaligned sources only come from native-long-returns (handled | |
1465 // special below). | |
1466 #ifndef _LP64 | |
1467 if( src_first_rc == rc_int && // source is already big-endian | |
1468 src_second_rc != rc_bad && // 64-bit move | |
1469 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
1470 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
1471 // Do the big-endian flop. | |
1472 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
1473 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
1474 } | |
1475 #endif | |
1476 | |
1477 // -------------------------------------- | |
1478 // Check for integer reg-reg copy | |
1479 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
1480 #ifndef _LP64 | |
1481 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
1482 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1483 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1484 // operand contains the least significant word of the 64-bit value and vice versa. | |
1485 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
1486 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
1487 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
1488 if( cbuf ) { | |
1489 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
1490 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
1491 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
1492 #ifndef PRODUCT | |
1493 } else if( !do_size ) { | |
1494 if( size != 0 ) st->print("\n\t"); | |
1495 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
1496 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
1497 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
1498 #endif | |
1499 } | |
1500 return size+12; | |
1501 } | |
1502 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
1503 // returning a long value in I0/I1 | |
1504 // a SpillCopy must be able to target a return instruction's reg_class | |
1505 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1506 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1507 // operand contains the least significant word of the 64-bit value and vice versa. | |
1508 OptoReg::Name tdest = dst_first; | |
1509 | |
1510 if (src_first == dst_first) { | |
1511 tdest = OptoReg::Name(R_O7_num); | |
1512 size += 4; | |
1513 } | |
1514 | |
1515 if( cbuf ) { | |
1516 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
1517 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
1518 // ShrL_reg_imm6 | |
1519 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
1520 // ShrR_reg_imm6 src, 0, dst | |
1521 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
1522 if (tdest != dst_first) { | |
1523 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
1524 } | |
1525 } | |
1526 #ifndef PRODUCT | |
1527 else if( !do_size ) { | |
1528 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
1529 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
1530 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
1531 if (tdest != dst_first) { | |
1532 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
1533 } | |
1534 } | |
1535 #endif // PRODUCT | |
1536 return size+8; | |
1537 } | |
1538 #endif // !_LP64 | |
1539 // Else normal reg-reg copy | |
1540 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
1541 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
1542 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
1543 // This moves an aligned adjacent pair. | |
1544 // See if we are done. | |
1545 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
1546 return size; | |
1547 } | |
1548 | |
1549 // Check for integer store | |
1550 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
1551 int offset = ra_->reg2offset(dst_first); | |
1552 // Further check for aligned-adjacent pair, so we can use a double store | |
1553 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1554 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
1555 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
1556 } | |
1557 | |
1558 // Check for integer load | |
1559 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
1560 int offset = ra_->reg2offset(src_first); | |
1561 // Further check for aligned-adjacent pair, so we can use a double load | |
1562 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1563 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
1564 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1565 } | |
1566 | |
1567 // Check for float reg-reg copy | |
1568 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
1569 // Further check for aligned-adjacent pair, so we can use a double move | |
1570 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1571 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
1572 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
1573 } | |
1574 | |
1575 // Check for float store | |
1576 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
1577 int offset = ra_->reg2offset(dst_first); | |
1578 // Further check for aligned-adjacent pair, so we can use a double store | |
1579 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1580 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
1581 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1582 } | |
1583 | |
1584 // Check for float load | |
1585 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
1586 int offset = ra_->reg2offset(src_first); | |
1587 // Further check for aligned-adjacent pair, so we can use a double load | |
1588 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1589 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
1590 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
1591 } | |
1592 | |
1593 // -------------------------------------------------------------------- | |
1594 // Check for hi bits still needing moving. Only happens for misaligned | |
1595 // arguments to native calls. | |
1596 if( src_second == dst_second ) | |
1597 return size; // Self copy; no move | |
1598 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
1599 | |
1600 #ifndef _LP64 | |
1601 // In the LP64 build, all registers can be moved as aligned/adjacent | |
605 | 1602 // pairs, so there's never any need to move the high bits separately. |
0 | 1603 // The 32-bit builds have to deal with the 32-bit ABI which can force |
1604 // all sorts of silly alignment problems. | |
1605 | |
1606 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
1607 // 32-bits of a 64-bit register, but are needed in low bits of another | |
1608 // register (else it's a hi-bits-to-hi-bits copy which should have | |
1609 // happened already as part of a 64-bit move) | |
1610 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
1611 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
1612 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
1613 // Shift src_second down to dst_second's low bits. | |
1614 if( cbuf ) { | |
1615 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1616 #ifndef PRODUCT | |
1617 } else if( !do_size ) { | |
1618 if( size != 0 ) st->print("\n\t"); | |
1619 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
1620 #endif | |
1621 } | |
1622 return size+4; | |
1623 } | |
1624 | |
1625 // Check for high word integer store. Must down-shift the hi bits | |
1626 // into a temp register, then fall into the case of storing int bits. | |
1627 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
1628 // Shift src_second down to dst_second's low bits. | |
1629 if( cbuf ) { | |
1630 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1631 #ifndef PRODUCT | |
1632 } else if( !do_size ) { | |
1633 if( size != 0 ) st->print("\n\t"); | |
1634 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
1635 #endif | |
1636 } | |
1637 size+=4; | |
1638 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
1639 } | |
1640 | |
1641 // Check for high word integer load | |
1642 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
1643 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
1644 | |
1645 // Check for high word integer store | |
1646 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
1647 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
1648 | |
1649 // Check for high word float store | |
1650 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
1651 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
1652 | |
1653 #endif // !_LP64 | |
1654 | |
1655 Unimplemented(); | |
1656 } | |
1657 | |
1658 #ifndef PRODUCT | |
1659 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1660 implementation( NULL, ra_, false, st ); | |
1661 } | |
1662 #endif | |
1663 | |
1664 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1665 implementation( &cbuf, ra_, false, NULL ); | |
1666 } | |
1667 | |
1668 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
1669 return implementation( NULL, ra_, true, NULL ); | |
1670 } | |
1671 | |
1672 //============================================================================= | |
1673 #ifndef PRODUCT | |
1674 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
1675 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
1676 } | |
1677 #endif | |
1678 | |
1679 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
1680 MacroAssembler _masm(&cbuf); | |
1681 for(int i = 0; i < _count; i += 1) { | |
1682 __ nop(); | |
1683 } | |
1684 } | |
1685 | |
1686 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
1687 return 4 * _count; | |
1688 } | |
1689 | |
1690 | |
1691 //============================================================================= | |
1692 #ifndef PRODUCT | |
1693 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1694 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
1695 int reg = ra_->get_reg_first(this); | |
1696 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
1697 } | |
1698 #endif | |
1699 | |
1700 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1701 MacroAssembler _masm(&cbuf); | |
1702 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
1703 int reg = ra_->get_encode(this); | |
1704 | |
1705 if (Assembler::is_simm13(offset)) { | |
1706 __ add(SP, offset, reg_to_register_object(reg)); | |
1707 } else { | |
1708 __ set(offset, O7); | |
1709 __ add(SP, O7, reg_to_register_object(reg)); | |
1710 } | |
1711 } | |
1712 | |
1713 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
1714 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
1715 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
1716 return ra_->C->scratch_emit_size(this); | |
1717 } | |
1718 | |
1719 //============================================================================= | |
1720 #ifndef PRODUCT | |
1721 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1722 st->print_cr("\nUEP:"); | |
1723 #ifdef _LP64 | |
12226
7944aba7ba41
8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents:
12056
diff
changeset
|
1724 if (UseCompressedClassPointers) { |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
1725 assert(Universe::heap() != NULL, "java heap should be initialized"); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1726 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
13000
209aa13ab8c0
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
12323
diff
changeset
|
1727 if (Universe::narrow_klass_base() != 0) { |
209aa13ab8c0
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
12323
diff
changeset
|
1728 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base"); |
209aa13ab8c0
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
12323
diff
changeset
|
1729 if (Universe::narrow_klass_shift() != 0) { |
209aa13ab8c0
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
12323
diff
changeset
|
1730 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); |
209aa13ab8c0
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
12323
diff
changeset
|
1731 } |
209aa13ab8c0
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
12323
diff
changeset
|
1732 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
209aa13ab8c0
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
12323
diff
changeset
|
1733 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base"); |
209aa13ab8c0
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
12323
diff
changeset
|
1734 } else { |
209aa13ab8c0
8024927: Nashorn performance regression with CompressedOops
coleenp
parents:
12323
diff
changeset
|
1735 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); |
12056
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
10997
diff
changeset
|
1736 } |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1737 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1738 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1739 } |
0 | 1740 st->print_cr("\tCMP R_G5,R_G3" ); |
1741 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1742 #else // _LP64 | |
1743 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
1744 st->print_cr("\tCMP R_G5,R_G3" ); | |
1745 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1746 #endif // _LP64 | |
1747 } | |
1748 #endif | |
1749 | |
1750 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1751 MacroAssembler _masm(&cbuf); | |
1752 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
1753 Register temp_reg = G3; | |
1754 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
1755 | |
605 | 1756 // Load klass from receiver |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1757 __ load_klass(O0, temp_reg); |
0 | 1758 // Compare against expected klass |
1759 __ cmp(temp_reg, G5_ic_reg); | |
1760 // Branch to miss code, checks xcc or icc depending | |
1761 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
1762 } | |
1763 | |
1764 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
1765 return MachNode::size(ra_); | |
1766 } | |
1767 | |
1768 | |
1769 //============================================================================= | |
1770 | |
1771 | |
1772 // Emit exception handler code. | |
17809
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
1773 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) { |
0 | 1774 Register temp_reg = G3; |
1748 | 1775 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); |
0 | 1776 MacroAssembler _masm(&cbuf); |
1777 | |
1778 address base = | |
1779 __ start_a_stub(size_exception_handler()); | |
1780 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1781 | |
1782 int offset = __ offset(); | |
1783 | |
727 | 1784 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
0 | 1785 __ delayed()->nop(); |
1786 | |
1787 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
1788 | |
1789 __ end_a_stub(); | |
1790 | |
1791 return offset; | |
1792 } | |
1793 | |
17809
a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
17799
diff
changeset
|
1794 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { |
0 | 1795 // Can't use any of the current frame's registers as we may have deopted |
1796 // at a poll and everything (including G3) can be live. | |
1797 Register temp_reg = L0; | |
727 | 1798 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
0 | 1799 MacroAssembler _masm(&cbuf); |
1800 | |
1801 address base = | |
1802 __ start_a_stub(size_deopt_handler()); | |
1803 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1804 | |
1805 int offset = __ offset(); | |
1806 __ save_frame(0); | |
727 | 1807 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
0 | 1808 __ delayed()->restore(); |
1809 | |
1810 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
1811 | |
1812 __ end_a_stub(); | |
1813 return offset; | |
1814 | |
1815 } | |
1816 | |
1817 // Given a register encoding, produce a Integer Register object | |
1818 static Register reg_to_register_object(int register_encoding) { | |
1819 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
1820 return as_Register(register_encoding); | |
1821 } | |
1822 | |
1823 // Given a register encoding, produce a single-precision Float Register object | |
1824 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
1825 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
1826 return as_SingleFloatRegister(register_encoding); | |
1827 } | |
1828 | |
1829 // Given a register encoding, produce a double-precision Float Register object | |
1830 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
1831 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
1832 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
1833 return as_DoubleFloatRegister(register_encoding); | |
1834 } | |
1835 | |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1836 const bool Matcher::match_rule_supported(int opcode) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1837 if (!has_match_rule(opcode)) |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1838 return false; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1839 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1840 switch (opcode) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1841 case Op_CountLeadingZerosI: |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1842 case Op_CountLeadingZerosL: |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1843 case Op_CountTrailingZerosI: |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1844 case Op_CountTrailingZerosL: |
5934
61b82be3b1ff
7152957: VM crashes with assert(false) failed: bad AD file
never
parents:
4777
diff
changeset
|
1845 case Op_PopCountI: |
61b82be3b1ff
7152957: VM crashes with assert(false) failed: bad AD file
never
parents:
4777
diff
changeset
|
1846 case Op_PopCountL: |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1847 if (!UsePopCountInstruction) |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1848 return false; |
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
1849 case Op_CompareAndSwapL: |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
1850 #ifdef _LP64 |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
1851 case Op_CompareAndSwapP: |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
1852 #endif |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
1853 if (!VM_Version::supports_cx8()) |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
1854 return false; |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1855 break; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1856 } |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1857 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1858 return true; // Per default match rules are supported. |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1859 } |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
1860 |
0 | 1861 int Matcher::regnum_to_fpu_offset(int regnum) { |
1862 return regnum - 32; // The FP registers are in the second chunk | |
1863 } | |
1864 | |
1865 #ifdef ASSERT | |
1866 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
1867 #endif | |
1868 | |
1869 // Vector width in bytes | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1870 const int Matcher::vector_width_in_bytes(BasicType bt) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1871 assert(MaxVectorSize == 8, ""); |
0 | 1872 return 8; |
1873 } | |
1874 | |
1875 // Vector ideal reg | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1876 const int Matcher::vector_ideal_reg(int size) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1877 assert(MaxVectorSize == 8, ""); |
0 | 1878 return Op_RegD; |
1879 } | |
1880 | |
6823 | 1881 const int Matcher::vector_shift_count_ideal_reg(int size) { |
1882 fatal("vector shift is not supported"); | |
1883 return Node::NotAMachineReg; | |
1884 } | |
1885 | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1886 // Limits on vector size (number of elements) loaded into vector. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1887 const int Matcher::max_vector_size(const BasicType bt) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1888 assert(is_java_primitive(bt), "only primitive type vectors"); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1889 return vector_width_in_bytes(bt)/type2aelembytes(bt); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1890 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1891 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1892 const int Matcher::min_vector_size(const BasicType bt) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1893 return max_vector_size(bt); // Same as max. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1894 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1895 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1896 // SPARC doesn't support misaligned vectors store/load. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1897 const bool Matcher::misaligned_vectors_ok() { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1898 return false; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1899 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1900 |
14261 | 1901 // Current (2013) SPARC platforms need to read original key |
1902 // to construct decryption expanded key | |
1903 const bool Matcher::pass_original_key_for_aes() { | |
1904 return true; | |
1905 } | |
1906 | |
0 | 1907 // USII supports fxtof through the whole range of number, USIII doesn't |
1908 const bool Matcher::convL2FSupported(void) { | |
1909 return VM_Version::has_fast_fxtof(); | |
1910 } | |
1911 | |
1912 // Is this branch offset short enough that a short branch can be used? | |
1913 // | |
1914 // NOTE: If the platform does not provide any short branch variants, then | |
1915 // this method should return false for offset 0. | |
3851 | 1916 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
1917 // The passed offset is relative to address of the branch. | |
1918 // Don't need to adjust the offset. | |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
1919 return UseCBCond && Assembler::is_simm12(offset); |
0 | 1920 } |
1921 | |
1922 const bool Matcher::isSimpleConstant64(jlong value) { | |
1923 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
1924 // Depends on optimizations in MacroAssembler::setx. | |
1925 int hi = (int)(value >> 32); | |
1926 int lo = (int)(value & ~0); | |
1927 return (hi == 0) || (hi == -1) || (lo == 0); | |
1928 } | |
1929 | |
1930 // No scaling for the parameter the ClearArray node. | |
1931 const bool Matcher::init_array_count_is_in_bytes = true; | |
1932 | |
1933 // Threshold size for cleararray. | |
1934 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
1935 | |
4047 | 1936 // No additional cost for CMOVL. |
1937 const int Matcher::long_cmove_cost() { return 0; } | |
1938 | |
1939 // CMOVF/CMOVD are expensive on T4 and on SPARC64. | |
1940 const int Matcher::float_cmove_cost() { | |
1941 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; | |
1942 } | |
1943 | |
14428
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
1944 // Does the CPU require late expand (see block.cpp for description of late expand)? |
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
1945 const bool Matcher::require_postalloc_expand = false; |
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
1946 |
0 | 1947 // Should the Matcher clone shifts on addressing modes, expecting them to |
1948 // be subsumed into complex addressing expressions or compute them into | |
1949 // registers? True for Intel but false for most RISCs | |
1950 const bool Matcher::clone_shift_expressions = false; | |
1951 | |
2401
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2254
diff
changeset
|
1952 // Do we need to mask the count passed to shift instructions or does |
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2254
diff
changeset
|
1953 // the cpu only look at the lower 5/6 bits anyway? |
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2254
diff
changeset
|
1954 const bool Matcher::need_masked_shift_count = false; |
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2254
diff
changeset
|
1955 |
1575
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1956 bool Matcher::narrow_oop_use_complex_address() { |
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1957 NOT_LP64(ShouldNotCallThis()); |
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1958 assert(UseCompressedOops, "only for compressed oops code"); |
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1959 return false; |
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1960 } |
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1961 |
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
1962 bool Matcher::narrow_klass_use_complex_address() { |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
1963 NOT_LP64(ShouldNotCallThis()); |
12226
7944aba7ba41
8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents:
12056
diff
changeset
|
1964 assert(UseCompressedClassPointers, "only for compressed klass code"); |
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
1965 return false; |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
1966 } |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
1967 |
0 | 1968 // Is it better to copy float constants, or load them directly from memory? |
1969 // Intel can load a float constant from a direct address, requiring no | |
1970 // extra registers. Most RISCs will have to materialize an address into a | |
1971 // register first, so they would do better to copy the constant from stack. | |
1972 const bool Matcher::rematerialize_float_constants = false; | |
1973 | |
1974 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
1975 // needed. Else we split the double into 2 integer pieces and move it | |
1976 // piece-by-piece. Only happens when passing doubles into C code as the | |
1977 // Java calling convention forces doubles to be aligned. | |
1978 #ifdef _LP64 | |
1979 const bool Matcher::misaligned_doubles_ok = true; | |
1980 #else | |
1981 const bool Matcher::misaligned_doubles_ok = false; | |
1982 #endif | |
1983 | |
1984 // No-op on SPARC. | |
1985 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
1986 } | |
1987 | |
1988 // Advertise here if the CPU requires explicit rounding operations | |
1989 // to implement the UseStrictFP mode. | |
1990 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
1991 | |
1274
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1160
diff
changeset
|
1992 // Are floats conerted to double when stored to stack during deoptimization? |
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1160
diff
changeset
|
1993 // Sparc does not handle callee-save floats. |
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1160
diff
changeset
|
1994 bool Matcher::float_in_double() { return false; } |
0 | 1995 |
1996 // Do ints take an entire long register or just half? | |
1997 // Note that we if-def off of _LP64. | |
1998 // The relevant question is how the int is callee-saved. In _LP64 | |
1999 // the whole long is written but de-opt'ing will have to extract | |
2000 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
2001 #ifdef _LP64 | |
2002 const bool Matcher::int_in_long = true; | |
2003 #else | |
2004 const bool Matcher::int_in_long = false; | |
2005 #endif | |
2006 | |
2007 // Return whether or not this register is ever used as an argument. This | |
2008 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
2009 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
2010 // arguments in those registers not be available to the callee. | |
2011 bool Matcher::can_be_java_arg( int reg ) { | |
2012 // Standard sparc 6 args in registers | |
2013 if( reg == R_I0_num || | |
2014 reg == R_I1_num || | |
2015 reg == R_I2_num || | |
2016 reg == R_I3_num || | |
2017 reg == R_I4_num || | |
2018 reg == R_I5_num ) return true; | |
2019 #ifdef _LP64 | |
2020 // 64-bit builds can pass 64-bit pointers and longs in | |
2021 // the high I registers | |
2022 if( reg == R_I0H_num || | |
2023 reg == R_I1H_num || | |
2024 reg == R_I2H_num || | |
2025 reg == R_I3H_num || | |
2026 reg == R_I4H_num || | |
2027 reg == R_I5H_num ) return true; | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2028 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2029 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2030 return true; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2031 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2032 |
0 | 2033 #else |
2034 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
2035 // Longs cannot be passed in O regs, because O regs become I regs | |
2036 // after a 'save' and I regs get their high bits chopped off on | |
2037 // interrupt. | |
2038 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
2039 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
2040 #endif | |
2041 // A few float args in registers | |
2042 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
2043 | |
2044 return false; | |
2045 } | |
2046 | |
2047 bool Matcher::is_spillable_arg( int reg ) { | |
2048 return can_be_java_arg(reg); | |
2049 } | |
2050 | |
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2051 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2052 // Use hardware SDIVX instruction when it is |
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2053 // faster than a code which use multiply. |
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2054 return VM_Version::has_fast_idiv(); |
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2055 } |
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2056 |
0 | 2057 // Register for DIVI projection of divmodI |
2058 RegMask Matcher::divI_proj_mask() { | |
2059 ShouldNotReachHere(); | |
2060 return RegMask(); | |
2061 } | |
2062 | |
2063 // Register for MODI projection of divmodI | |
2064 RegMask Matcher::modI_proj_mask() { | |
2065 ShouldNotReachHere(); | |
2066 return RegMask(); | |
2067 } | |
2068 | |
2069 // Register for DIVL projection of divmodL | |
2070 RegMask Matcher::divL_proj_mask() { | |
2071 ShouldNotReachHere(); | |
2072 return RegMask(); | |
2073 } | |
2074 | |
2075 // Register for MODL projection of divmodL | |
2076 RegMask Matcher::modL_proj_mask() { | |
2077 ShouldNotReachHere(); | |
2078 return RegMask(); | |
2079 } | |
2080 | |
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1041
diff
changeset
|
2081 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
4121
db2e64ca2d5a
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
4114
diff
changeset
|
2082 return L7_REGP_mask(); |
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1041
diff
changeset
|
2083 } |
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1041
diff
changeset
|
2084 |
0 | 2085 %} |
2086 | |
2087 | |
2088 // The intptr_t operand types, defined by textual substitution. | |
2089 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
2090 #ifdef _LP64 | |
824 | 2091 #define immX immL |
2092 #define immX13 immL13 | |
2093 #define immX13m7 immL13m7 | |
2094 #define iRegX iRegL | |
2095 #define g1RegX g1RegL | |
0 | 2096 #else |
824 | 2097 #define immX immI |
2098 #define immX13 immI13 | |
2099 #define immX13m7 immI13m7 | |
2100 #define iRegX iRegI | |
2101 #define g1RegX g1RegI | |
0 | 2102 #endif |
2103 | |
2104 //----------ENCODING BLOCK----------------------------------------------------- | |
2105 // This block specifies the encoding classes used by the compiler to output | |
2106 // byte streams. Encoding classes are parameterized macros used by | |
2107 // Machine Instruction Nodes in order to generate the bit encoding of the | |
2108 // instruction. Operands specify their base encoding interface with the | |
2109 // interface keyword. There are currently supported four interfaces, | |
2110 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
2111 // operand to generate a function which returns its register number when | |
2112 // queried. CONST_INTER causes an operand to generate a function which | |
2113 // returns the value of the constant when queried. MEMORY_INTER causes an | |
2114 // operand to generate four functions which return the Base Register, the | |
2115 // Index Register, the Scale Value, and the Offset Value of the operand when | |
2116 // queried. COND_INTER causes an operand to generate six functions which | |
2117 // return the encoding code (ie - encoding bits for the instruction) | |
2118 // associated with each basic boolean condition for a conditional instruction. | |
2119 // | |
2120 // Instructions specify two basic values for encoding. Again, a function | |
2121 // is available to check if the constant displacement is an oop. They use the | |
2122 // ins_encode keyword to specify their encoding classes (which must be | |
2123 // a sequence of enc_class names, and their parameters, specified in | |
2124 // the encoding block), and they use the | |
2125 // opcode keyword to specify, in order, their primary, secondary, and | |
2126 // tertiary opcode. Only the opcode sections which a particular instruction | |
2127 // needs for encoding need to be specified. | |
2128 encode %{ | |
2129 enc_class enc_untested %{ | |
2130 #ifdef ASSERT | |
2131 MacroAssembler _masm(&cbuf); | |
2132 __ untested("encoding"); | |
2133 #endif | |
2134 %} | |
2135 | |
2136 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
14217
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
2137 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary, |
0 | 2138 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
2139 %} | |
2140 | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2141 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
14217
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
2142 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2143 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2144 %} |
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
2145 |
0 | 2146 enc_class form3_mem_prefetch_read( memory mem ) %{ |
14217
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
2147 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, |
0 | 2148 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
2149 %} | |
2150 | |
2151 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
14217
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
2152 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, |
0 | 2153 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
2154 %} | |
2155 | |
2156 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
2157 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
2158 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
0 | 2159 guarantee($mem$$index == R_G0_enc, "double index?"); |
14217
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
2160 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
2161 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
0 | 2162 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
2163 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
2164 %} | |
2165 | |
2166 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
2167 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
2168 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
0 | 2169 guarantee($mem$$index == R_G0_enc, "double index?"); |
2170 // Load long with 2 instructions | |
14217
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
2171 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
2172 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
0 | 2173 %} |
2174 | |
2175 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
2176 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
2177 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
14217
f3e0bcfff3ab
8029668: Kithcensink crashed with guarantee(Assembler::is_simm13(disp)) failed: Do not match large constant offsets
iveresov
parents:
13042
diff
changeset
|
2178 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
0 | 2179 %} |
2180 | |
2181 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
2182 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2183 if( $rs2$$reg != $rd$$reg ) | |
2184 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
2185 %} | |
2186 | |
2187 // Target lo half of long | |
2188 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
2189 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2190 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
2191 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
2192 %} | |
2193 | |
2194 // Source lo half of long | |
2195 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
2196 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2197 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
2198 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
2199 %} | |
2200 | |
2201 // Target hi half of long | |
2202 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
2203 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
2204 %} | |
2205 | |
2206 // Source lo half of long, and leave it sign extended. | |
2207 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
2208 // Sign extend low half | |
2209 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
2210 %} | |
2211 | |
2212 // Source hi half of long, and leave it sign extended. | |
2213 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
2214 // Shift high half to low half | |
2215 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
2216 %} | |
2217 | |
2218 // Source hi half of long | |
2219 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
2220 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2221 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
2222 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
2223 %} | |
2224 | |
2225 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
2226 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
2227 %} | |
2228 | |
2229 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
2230 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
2231 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
2232 %} | |
2233 | |
2234 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
2235 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
2236 // clear if nothing else is happening | |
2237 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
2238 // blt,a,pn done | |
2239 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
2240 // mov dst,-1 in delay slot | |
2241 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2242 %} | |
2243 | |
2244 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
2245 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
2246 %} | |
2247 | |
2248 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
2249 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
2250 %} | |
2251 | |
2252 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
2253 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
2254 %} | |
2255 | |
2256 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
2257 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
2258 %} | |
2259 | |
2260 enc_class move_return_pc_to_o1() %{ | |
2261 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
2262 %} | |
2263 | |
2264 #ifdef _LP64 | |
2265 /* %%% merge with enc_to_bool */ | |
2266 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
2267 MacroAssembler _masm(&cbuf); | |
2268 | |
2269 Register src_reg = reg_to_register_object($src$$reg); | |
2270 Register dst_reg = reg_to_register_object($dst$$reg); | |
2271 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
2272 %} | |
2273 #endif | |
2274 | |
2275 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
2276 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
2277 MacroAssembler _masm(&cbuf); | |
2278 | |
2279 Register p_reg = reg_to_register_object($p$$reg); | |
2280 Register q_reg = reg_to_register_object($q$$reg); | |
2281 Register y_reg = reg_to_register_object($y$$reg); | |
2282 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
2283 | |
2284 __ subcc( p_reg, q_reg, p_reg ); | |
2285 __ add ( p_reg, y_reg, tmp_reg ); | |
2286 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
2287 %} | |
2288 | |
2289 enc_class form_d2i_helper(regD src, regF dst) %{ | |
2290 // fcmp %fcc0,$src,$src | |
2291 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2292 // branch %fcc0 not-nan, predict taken | |
2293 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2294 // fdtoi $src,$dst | |
2295 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
2296 // fitos $dst,$dst (if nan) | |
2297 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2298 // clear $dst (if nan) | |
2299 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2300 // carry on here... | |
2301 %} | |
2302 | |
2303 enc_class form_d2l_helper(regD src, regD dst) %{ | |
2304 // fcmp %fcc0,$src,$src check for NAN | |
2305 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2306 // branch %fcc0 not-nan, predict taken | |
2307 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2308 // fdtox $src,$dst convert in delay slot | |
2309 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
2310 // fxtod $dst,$dst (if nan) | |
2311 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2312 // clear $dst (if nan) | |
2313 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2314 // carry on here... | |
2315 %} | |
2316 | |
2317 enc_class form_f2i_helper(regF src, regF dst) %{ | |
2318 // fcmps %fcc0,$src,$src | |
2319 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2320 // branch %fcc0 not-nan, predict taken | |
2321 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2322 // fstoi $src,$dst | |
2323 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
2324 // fitos $dst,$dst (if nan) | |
2325 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2326 // clear $dst (if nan) | |
2327 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2328 // carry on here... | |
2329 %} | |
2330 | |
2331 enc_class form_f2l_helper(regF src, regD dst) %{ | |
2332 // fcmps %fcc0,$src,$src | |
2333 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2334 // branch %fcc0 not-nan, predict taken | |
2335 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2336 // fstox $src,$dst | |
2337 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
2338 // fxtod $dst,$dst (if nan) | |
2339 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2340 // clear $dst (if nan) | |
2341 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2342 // carry on here... | |
2343 %} | |
2344 | |
2345 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2346 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2347 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2348 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2349 | |
2350 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2351 | |
2352 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2353 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2354 | |
2355 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
2356 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2357 %} | |
2358 | |
2359 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
2360 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2361 %} | |
2362 | |
2363 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
2364 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2365 %} | |
2366 | |
2367 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
2368 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2369 %} | |
2370 | |
2371 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
2372 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
2373 %} | |
2374 | |
2375 // Encloding class for traceable jumps | |
2376 enc_class form_jmpl(g3RegP dest) %{ | |
2377 emit_jmpl(cbuf, $dest$$reg); | |
2378 %} | |
2379 | |
2380 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
2381 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
2382 %} | |
2383 | |
2384 enc_class form2_nop() %{ | |
2385 emit_nop(cbuf); | |
2386 %} | |
2387 | |
2388 enc_class form2_illtrap() %{ | |
2389 emit_illtrap(cbuf); | |
2390 %} | |
2391 | |
2392 | |
2393 // Compare longs and convert into -1, 0, 1. | |
2394 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
2395 // CMP $src1,$src2 | |
2396 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
2397 // blt,a,pn done | |
2398 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
2399 // mov dst,-1 in delay slot | |
2400 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2401 // bgt,a,pn done | |
2402 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
2403 // mov dst,1 in delay slot | |
2404 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
2405 // CLR $dst | |
2406 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
2407 %} | |
2408 | |
2409 enc_class enc_PartialSubtypeCheck() %{ | |
2410 MacroAssembler _masm(&cbuf); | |
2411 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
2412 __ delayed()->nop(); | |
2413 %} | |
2414 | |
3839 | 2415 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ |
0 | 2416 MacroAssembler _masm(&cbuf); |
3839 | 2417 Label* L = $labl$$label; |
0 | 2418 Assembler::Predict predict_taken = |
3839 | 2419 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
2420 | |
2421 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
0 | 2422 __ delayed()->nop(); |
2423 %} | |
2424 | |
3839 | 2425 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ |
0 | 2426 MacroAssembler _masm(&cbuf); |
3839 | 2427 Label* L = $labl$$label; |
0 | 2428 Assembler::Predict predict_taken = |
3839 | 2429 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
2430 | |
2431 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); | |
0 | 2432 __ delayed()->nop(); |
2433 %} | |
2434 | |
2435 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
2436 int op = (Assembler::arith_op << 30) | | |
2437 ($dst$$reg << 25) | | |
2438 (Assembler::movcc_op3 << 19) | | |
2439 (1 << 18) | // cc2 bit for 'icc' | |
2440 ($cmp$$cmpcode << 14) | | |
2441 (0 << 13) | // select register move | |
2442 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
2443 ($src$$reg << 0); | |
1748 | 2444 cbuf.insts()->emit_int32(op); |
0 | 2445 %} |
2446 | |
2447 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
2448 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2449 int op = (Assembler::arith_op << 30) | | |
2450 ($dst$$reg << 25) | | |
2451 (Assembler::movcc_op3 << 19) | | |
2452 (1 << 18) | // cc2 bit for 'icc' | |
2453 ($cmp$$cmpcode << 14) | | |
2454 (1 << 13) | // select immediate move | |
2455 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
2456 (simm11 << 0); | |
1748 | 2457 cbuf.insts()->emit_int32(op); |
0 | 2458 %} |
2459 | |
2460 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
2461 int op = (Assembler::arith_op << 30) | | |
2462 ($dst$$reg << 25) | | |
2463 (Assembler::movcc_op3 << 19) | | |
2464 (0 << 18) | // cc2 bit for 'fccX' | |
2465 ($cmp$$cmpcode << 14) | | |
2466 (0 << 13) | // select register move | |
2467 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2468 ($src$$reg << 0); | |
1748 | 2469 cbuf.insts()->emit_int32(op); |
0 | 2470 %} |
2471 | |
2472 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
2473 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2474 int op = (Assembler::arith_op << 30) | | |
2475 ($dst$$reg << 25) | | |
2476 (Assembler::movcc_op3 << 19) | | |
2477 (0 << 18) | // cc2 bit for 'fccX' | |
2478 ($cmp$$cmpcode << 14) | | |
2479 (1 << 13) | // select immediate move | |
2480 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2481 (simm11 << 0); | |
1748 | 2482 cbuf.insts()->emit_int32(op); |
0 | 2483 %} |
2484 | |
2485 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
2486 int op = (Assembler::arith_op << 30) | | |
2487 ($dst$$reg << 25) | | |
2488 (Assembler::fpop2_op3 << 19) | | |
2489 (0 << 18) | | |
2490 ($cmp$$cmpcode << 14) | | |
2491 (1 << 13) | // select register move | |
2492 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
2493 ($primary << 5) | // select single, double or quad | |
2494 ($src$$reg << 0); | |
1748 | 2495 cbuf.insts()->emit_int32(op); |
0 | 2496 %} |
2497 | |
2498 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
2499 int op = (Assembler::arith_op << 30) | | |
2500 ($dst$$reg << 25) | | |
2501 (Assembler::fpop2_op3 << 19) | | |
2502 (0 << 18) | | |
2503 ($cmp$$cmpcode << 14) | | |
2504 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
2505 ($primary << 5) | // select single, double or quad | |
2506 ($src$$reg << 0); | |
1748 | 2507 cbuf.insts()->emit_int32(op); |
0 | 2508 %} |
2509 | |
2510 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
2511 // the condition comes from opcode-field instead of an argument. | |
2512 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
2513 int op = (Assembler::arith_op << 30) | | |
2514 ($dst$$reg << 25) | | |
2515 (Assembler::movcc_op3 << 19) | | |
2516 (1 << 18) | // cc2 bit for 'icc' | |
2517 ($primary << 14) | | |
2518 (0 << 13) | // select register move | |
2519 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2520 ($src$$reg << 0); | |
1748 | 2521 cbuf.insts()->emit_int32(op); |
0 | 2522 %} |
2523 | |
2524 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
2525 int op = (Assembler::arith_op << 30) | | |
2526 ($dst$$reg << 25) | | |
2527 (Assembler::movcc_op3 << 19) | | |
2528 (6 << 16) | // cc2 bit for 'xcc' | |
2529 ($primary << 14) | | |
2530 (0 << 13) | // select register move | |
2531 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2532 ($src$$reg << 0); | |
1748 | 2533 cbuf.insts()->emit_int32(op); |
0 | 2534 %} |
2535 | |
2536 enc_class Set13( immI13 src, iRegI rd ) %{ | |
2537 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
2538 %} | |
2539 | |
2540 enc_class SetHi22( immI src, iRegI rd ) %{ | |
2541 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
2542 %} | |
2543 | |
2544 enc_class Set32( immI src, iRegI rd ) %{ | |
2545 MacroAssembler _masm(&cbuf); | |
2546 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
2547 %} | |
2548 | |
2549 enc_class call_epilog %{ | |
2550 if( VerifyStackAtCalls ) { | |
2551 MacroAssembler _masm(&cbuf); | |
17980
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17877
diff
changeset
|
2552 int framesize = ra_->C->frame_size_in_bytes(); |
0 | 2553 Register temp_reg = G3; |
2554 __ add(SP, framesize, temp_reg); | |
2555 __ cmp(temp_reg, FP); | |
2556 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
2557 } | |
2558 %} | |
2559 | |
2560 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
2561 // to G1 so the register allocator will not have to deal with the misaligned register | |
2562 // pair. | |
2563 enc_class adjust_long_from_native_call %{ | |
2564 #ifndef _LP64 | |
2565 if (returns_long()) { | |
2566 // sllx O0,32,O0 | |
2567 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
2568 // srl O1,0,O1 | |
2569 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
2570 // or O0,O1,G1 | |
2571 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
2572 } | |
2573 #endif | |
2574 %} | |
2575 | |
2576 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
2577 // CALL directly to the runtime | |
2578 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
2579 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
2121
c17b998c5926
7011627: C1: call_RT must support targets that don't fit in wdisp30
iveresov
parents:
2080
diff
changeset
|
2580 /*preserve_g2=*/true); |
0 | 2581 %} |
2582 | |
1567 | 2583 enc_class preserve_SP %{ |
2584 MacroAssembler _masm(&cbuf); | |
2585 __ mov(SP, L7_mh_SP_save); | |
2586 %} | |
2587 | |
2588 enc_class restore_SP %{ | |
2589 MacroAssembler _masm(&cbuf); | |
2590 __ mov(L7_mh_SP_save, SP); | |
2591 %} | |
2592 | |
0 | 2593 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
2594 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
2595 // who we intended to call. | |
10168
a6e09d6dd8e5
8003853: specify offset of IC load in java_to_interp stub
dlong
parents:
7426
diff
changeset
|
2596 if (!_method) { |
0 | 2597 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); |
2598 } else if (_optimized_virtual) { | |
2599 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
2600 } else { | |
2601 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
2602 } | |
10168
a6e09d6dd8e5
8003853: specify offset of IC load in java_to_interp stub
dlong
parents:
7426
diff
changeset
|
2603 if (_method) { // Emit stub for static call. |
a6e09d6dd8e5
8003853: specify offset of IC load in java_to_interp stub
dlong
parents:
7426
diff
changeset
|
2604 CompiledStaticCall::emit_to_interp_stub(cbuf); |
0 | 2605 } |
2606 %} | |
2607 | |
2608 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
2609 MacroAssembler _masm(&cbuf); | |
2610 __ set_inst_mark(); | |
2611 int vtable_index = this->_vtable_index; | |
2612 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
2613 if (vtable_index < 0) { | |
2614 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
2615 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
0 | 2616 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); |
2617 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
2618 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
2619 __ ic_call((address)$meth$$method); |
0 | 2620 } else { |
2621 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
2622 // Just go thru the vtable | |
2623 // get receiver klass (receiver already checked for non-null) | |
2624 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
2625 int off = __ offset(); | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2626 __ load_klass(O0, G3_scratch); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2627 int klass_load_size; |
12226
7944aba7ba41
8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents:
12056
diff
changeset
|
2628 if (UseCompressedClassPointers) { |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2629 assert(Universe::heap() != NULL, "java heap should be initialized"); |
12056
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
10997
diff
changeset
|
2630 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2631 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2632 klass_load_size = 1*BytesPerInstWord; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2633 } |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
2634 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
0 | 2635 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
2636 if (Assembler::is_simm13(v_off)) { |
0 | 2637 __ ld_ptr(G3, v_off, G5_method); |
2638 } else { | |
2639 // Generate 2 instructions | |
2640 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
2641 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
2642 // ld_ptr, set_hi, set | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2643 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2644 "Unexpected instruction size(s)"); |
0 | 2645 __ ld_ptr(G3, G5_method, G5_method); |
2646 } | |
2647 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
2648 // However it may very well end up in handle_wrong_method if the | |
2649 // method is abstract for the particular class. | |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
2650 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch); |
0 | 2651 // jump to target (either compiled code or c2iadapter) |
2652 __ jmpl(G3_scratch, G0, O7); | |
2653 __ delayed()->nop(); | |
2654 } | |
2655 %} | |
2656 | |
2657 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
2658 MacroAssembler _masm(&cbuf); | |
2659 | |
2660 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
2661 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
2662 // we might be calling a C2I adapter which needs it. | |
2663 | |
2664 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
2665 // Load nmethod | |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
2666 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg); |
0 | 2667 |
2668 // CALL to compiled java, indirect the contents of G3 | |
2669 __ set_inst_mark(); | |
2670 __ callr(temp_reg, G0); | |
2671 __ delayed()->nop(); | |
2672 %} | |
2673 | |
2674 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
2675 MacroAssembler _masm(&cbuf); | |
2676 Register Rdividend = reg_to_register_object($src1$$reg); | |
2677 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2678 Register Rresult = reg_to_register_object($dst$$reg); | |
2679 | |
2680 __ sra(Rdivisor, 0, Rdivisor); | |
2681 __ sra(Rdividend, 0, Rdividend); | |
2682 __ sdivx(Rdividend, Rdivisor, Rresult); | |
2683 %} | |
2684 | |
2685 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
2686 MacroAssembler _masm(&cbuf); | |
2687 | |
2688 Register Rdividend = reg_to_register_object($src1$$reg); | |
2689 int divisor = $imm$$constant; | |
2690 Register Rresult = reg_to_register_object($dst$$reg); | |
2691 | |
2692 __ sra(Rdividend, 0, Rdividend); | |
2693 __ sdivx(Rdividend, divisor, Rresult); | |
2694 %} | |
2695 | |
2696 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
2697 MacroAssembler _masm(&cbuf); | |
2698 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
2699 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
2700 Register Rdst = reg_to_register_object($dst$$reg); | |
2701 | |
2702 __ sra( Rsrc1, 0, Rsrc1 ); | |
2703 __ sra( Rsrc2, 0, Rsrc2 ); | |
2704 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
2705 __ srlx( Rdst, 32, Rdst ); | |
2706 %} | |
2707 | |
2708 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
2709 MacroAssembler _masm(&cbuf); | |
2710 Register Rdividend = reg_to_register_object($src1$$reg); | |
2711 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2712 Register Rresult = reg_to_register_object($dst$$reg); | |
2713 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2714 | |
2715 assert(Rdividend != Rscratch, ""); | |
2716 assert(Rdivisor != Rscratch, ""); | |
2717 | |
2718 __ sra(Rdividend, 0, Rdividend); | |
2719 __ sra(Rdivisor, 0, Rdivisor); | |
2720 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
2721 __ mulx(Rscratch, Rdivisor, Rscratch); | |
2722 __ sub(Rdividend, Rscratch, Rresult); | |
2723 %} | |
2724 | |
2725 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
2726 MacroAssembler _masm(&cbuf); | |
2727 | |
2728 Register Rdividend = reg_to_register_object($src1$$reg); | |
2729 int divisor = $imm$$constant; | |
2730 Register Rresult = reg_to_register_object($dst$$reg); | |
2731 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2732 | |
2733 assert(Rdividend != Rscratch, ""); | |
2734 | |
2735 __ sra(Rdividend, 0, Rdividend); | |
2736 __ sdivx(Rdividend, divisor, Rscratch); | |
2737 __ mulx(Rscratch, divisor, Rscratch); | |
2738 __ sub(Rdividend, Rscratch, Rresult); | |
2739 %} | |
2740 | |
2741 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
2742 MacroAssembler _masm(&cbuf); | |
2743 | |
2744 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2745 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2746 | |
2747 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
2748 %} | |
2749 | |
2750 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
2751 MacroAssembler _masm(&cbuf); | |
2752 | |
2753 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2754 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2755 | |
2756 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
2757 %} | |
2758 | |
2759 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
2760 MacroAssembler _masm(&cbuf); | |
2761 | |
2762 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2763 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2764 | |
2765 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
2766 %} | |
2767 | |
2768 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
2769 MacroAssembler _masm(&cbuf); | |
2770 | |
2771 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2772 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2773 | |
2774 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
2775 %} | |
2776 | |
2777 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
2778 MacroAssembler _masm(&cbuf); | |
2779 | |
2780 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2781 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2782 | |
2783 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
2784 %} | |
2785 | |
2786 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
2787 MacroAssembler _masm(&cbuf); | |
2788 | |
2789 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2790 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2791 | |
2792 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
2793 %} | |
2794 | |
2795 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
2796 MacroAssembler _masm(&cbuf); | |
2797 | |
2798 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2799 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2800 | |
2801 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
2802 %} | |
2803 | |
2804 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2805 MacroAssembler _masm(&cbuf); | |
2806 | |
2807 Register Roop = reg_to_register_object($oop$$reg); | |
2808 Register Rbox = reg_to_register_object($box$$reg); | |
2809 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2810 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2811 | |
2812 assert(Roop != Rscratch, ""); | |
2813 assert(Roop != Rmark, ""); | |
2814 assert(Rbox != Rscratch, ""); | |
2815 assert(Rbox != Rmark, ""); | |
2816 | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
2817 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2818 %} |
2819 | |
2820 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2821 MacroAssembler _masm(&cbuf); | |
2822 | |
2823 Register Roop = reg_to_register_object($oop$$reg); | |
2824 Register Rbox = reg_to_register_object($box$$reg); | |
2825 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2826 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2827 | |
2828 assert(Roop != Rscratch, ""); | |
2829 assert(Roop != Rmark, ""); | |
2830 assert(Rbox != Rscratch, ""); | |
2831 assert(Rbox != Rmark, ""); | |
2832 | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
2833 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2834 %} |
2835 | |
2836 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
2837 MacroAssembler _masm(&cbuf); | |
2838 Register Rmem = reg_to_register_object($mem$$reg); | |
2839 Register Rold = reg_to_register_object($old$$reg); | |
2840 Register Rnew = reg_to_register_object($new$$reg); | |
2841 | |
10997 | 2842 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
0 | 2843 __ cmp( Rold, Rnew ); |
2844 %} | |
2845 | |
2846 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
2847 Register Rmem = reg_to_register_object($mem$$reg); | |
2848 Register Rold = reg_to_register_object($old$$reg); | |
2849 Register Rnew = reg_to_register_object($new$$reg); | |
2850 | |
2851 MacroAssembler _masm(&cbuf); | |
2852 __ mov(Rnew, O7); | |
2853 __ casx(Rmem, Rold, O7); | |
2854 __ cmp( Rold, O7 ); | |
2855 %} | |
2856 | |
2857 // raw int cas, used for compareAndSwap | |
2858 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
2859 Register Rmem = reg_to_register_object($mem$$reg); | |
2860 Register Rold = reg_to_register_object($old$$reg); | |
2861 Register Rnew = reg_to_register_object($new$$reg); | |
2862 | |
2863 MacroAssembler _masm(&cbuf); | |
2864 __ mov(Rnew, O7); | |
2865 __ cas(Rmem, Rold, O7); | |
2866 __ cmp( Rold, O7 ); | |
2867 %} | |
2868 | |
2869 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
2870 Register Rres = reg_to_register_object($res$$reg); | |
2871 | |
2872 MacroAssembler _masm(&cbuf); | |
2873 __ mov(1, Rres); | |
2874 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
2875 %} | |
2876 | |
2877 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
2878 Register Rres = reg_to_register_object($res$$reg); | |
2879 | |
2880 MacroAssembler _masm(&cbuf); | |
2881 __ mov(1, Rres); | |
2882 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
2883 %} | |
2884 | |
2885 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
2886 MacroAssembler _masm(&cbuf); | |
2887 Register Rdst = reg_to_register_object($dst$$reg); | |
2888 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
2889 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
2890 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
2891 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
2892 | |
2893 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
2894 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
2895 %} | |
2896 | |
2897 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2898 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
0 | 2899 Label Ldone, Lloop; |
2900 MacroAssembler _masm(&cbuf); | |
2901 | |
2902 Register str1_reg = reg_to_register_object($str1$$reg); | |
2903 Register str2_reg = reg_to_register_object($str2$$reg); | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2904 Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2905 Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
0 | 2906 Register result_reg = reg_to_register_object($result$$reg); |
2907 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2908 assert(result_reg != str1_reg && |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2909 result_reg != str2_reg && |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2910 result_reg != cnt1_reg && |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2911 result_reg != cnt2_reg , |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2912 "need different registers"); |
0 | 2913 |
2914 // Compute the minimum of the string lengths(str1_reg) and the | |
2915 // difference of the string lengths (stack) | |
2916 | |
2917 // See if the lengths are different, and calculate min in str1_reg. | |
2918 // Stash diff in O7 in case we need it for a tie-breaker. | |
2919 Label Lskip; | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2920 __ subcc(cnt1_reg, cnt2_reg, O7); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2921 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
0 | 2922 __ br(Assembler::greater, true, Assembler::pt, Lskip); |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2923 // cnt2 is shorter, so use its count: |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2924 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
0 | 2925 __ bind(Lskip); |
2926 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2927 // reallocate cnt1_reg, cnt2_reg, result_reg |
0 | 2928 // Note: limit_reg holds the string length pre-scaled by 2 |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2929 Register limit_reg = cnt1_reg; |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2930 Register chr2_reg = cnt2_reg; |
0 | 2931 Register chr1_reg = result_reg; |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2932 // str{12} are the base pointers |
0 | 2933 |
2934 // Is the minimum length zero? | |
2935 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
2936 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2937 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2938 | |
2939 // Load first characters | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2940 __ lduh(str1_reg, 0, chr1_reg); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2941 __ lduh(str2_reg, 0, chr2_reg); |
0 | 2942 |
2943 // Compare first characters | |
2944 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
2945 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2946 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2947 __ delayed()->nop(); | |
2948 | |
2949 { | |
2950 // Check after comparing first character to see if strings are equivalent | |
2951 Label LSkip2; | |
2952 // Check if the strings start at same location | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2953 __ cmp(str1_reg, str2_reg); |
0 | 2954 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
2955 __ delayed()->nop(); | |
2956 | |
2957 // Check if the length difference is zero (in O7) | |
2958 __ cmp(G0, O7); | |
2959 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2960 __ delayed()->mov(G0, result_reg); // result is zero | |
2961 | |
2962 // Strings might not be equal | |
2963 __ bind(LSkip2); | |
2964 } | |
2965 | |
13042
208ebea980f8
8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents:
13001
diff
changeset
|
2966 // We have no guarantee that on 64 bit the higher half of limit_reg is 0 |
208ebea980f8
8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents:
13001
diff
changeset
|
2967 __ signx(limit_reg); |
208ebea980f8
8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents:
13001
diff
changeset
|
2968 |
0 | 2969 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); |
2970 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2971 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2972 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2973 // Shift str1_reg and str2_reg to the end of the arrays, negate limit |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2974 __ add(str1_reg, limit_reg, str1_reg); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2975 __ add(str2_reg, limit_reg, str2_reg); |
0 | 2976 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
2977 | |
2978 // Compare the rest of the characters | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2979 __ lduh(str1_reg, limit_reg, chr1_reg); |
0 | 2980 __ bind(Lloop); |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2981 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2982 __ lduh(str2_reg, limit_reg, chr2_reg); |
0 | 2983 __ subcc(chr1_reg, chr2_reg, chr1_reg); |
2984 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2985 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2986 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
2987 // annul LDUH if branch is not taken to prevent access past end of string | |
2988 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2989 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
0 | 2990 |
2991 // If strings are equal up to min length, return the length difference. | |
2992 __ mov(O7, result_reg); | |
2993 | |
2994 // Otherwise, return the difference between the first mismatched chars. | |
2995 __ bind(Ldone); | |
2996 %} | |
2997 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2998 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
2999 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
681 | 3000 MacroAssembler _masm(&cbuf); |
3001 | |
3002 Register str1_reg = reg_to_register_object($str1$$reg); | |
3003 Register str2_reg = reg_to_register_object($str2$$reg); | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3004 Register cnt_reg = reg_to_register_object($cnt$$reg); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3005 Register tmp1_reg = O7; |
681 | 3006 Register result_reg = reg_to_register_object($result$$reg); |
3007 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3008 assert(result_reg != str1_reg && |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3009 result_reg != str2_reg && |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3010 result_reg != cnt_reg && |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3011 result_reg != tmp1_reg , |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3012 "need different registers"); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3013 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3014 __ cmp(str1_reg, str2_reg); //same char[] ? |
681 | 3015 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
3016 __ delayed()->add(G0, 1, result_reg); | |
3017 | |
3839 | 3018 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn); |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3019 __ delayed()->add(G0, 1, result_reg); // count == 0 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3020 |
681 | 3021 //rename registers |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3022 Register limit_reg = cnt_reg; |
681 | 3023 Register chr1_reg = result_reg; |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3024 Register chr2_reg = tmp1_reg; |
681 | 3025 |
13042
208ebea980f8
8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents:
13001
diff
changeset
|
3026 // We have no guarantee that on 64 bit the higher half of limit_reg is 0 |
208ebea980f8
8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents:
13001
diff
changeset
|
3027 __ signx(limit_reg); |
208ebea980f8
8027445: SIGSEGV at TestFloatingDecimal.testAppendToDouble()I
roland
parents:
13001
diff
changeset
|
3028 |
681 | 3029 //check for alignment and position the pointers to the ends |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3030 __ or3(str1_reg, str2_reg, chr1_reg); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3031 __ andcc(chr1_reg, 0x3, chr1_reg); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3032 // notZero means at least one not 4-byte aligned. |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3033 // We could optimize the case when both arrays are not aligned |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3034 // but it is not frequent case and it requires additional checks. |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3035 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3036 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3037 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3038 // Compare char[] arrays aligned to 4 bytes. |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3039 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3040 chr1_reg, chr2_reg, Ldone); |
3839 | 3041 __ ba(Ldone); |
681 | 3042 __ delayed()->add(G0, 1, result_reg); |
3043 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3044 // char by char compare |
681 | 3045 __ bind(Lchar); |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3046 __ add(str1_reg, limit_reg, str1_reg); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3047 __ add(str2_reg, limit_reg, str2_reg); |
681 | 3048 __ neg(limit_reg); //negate count |
3049 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3050 __ lduh(str1_reg, limit_reg, chr1_reg); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3051 // Lchar_loop |
681 | 3052 __ bind(Lchar_loop); |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3053 __ lduh(str2_reg, limit_reg, chr2_reg); |
681 | 3054 __ cmp(chr1_reg, chr2_reg); |
3055 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
3056 __ delayed()->mov(G0, result_reg); //not equal | |
3057 __ inccc(limit_reg, sizeof(jchar)); | |
3058 // annul LDUH if branch is not taken to prevent access past end of string | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3059 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3060 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
681 | 3061 |
3062 __ add(G0, 1, result_reg); //equal | |
3063 | |
3064 __ bind(Ldone); | |
3065 %} | |
3066 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3067 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
681 | 3068 Label Lvector, Ldone, Lloop; |
3069 MacroAssembler _masm(&cbuf); | |
3070 | |
3071 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
3072 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
3073 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3074 Register tmp2_reg = O7; |
681 | 3075 Register result_reg = reg_to_register_object($result$$reg); |
3076 | |
3077 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
3078 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
3079 | |
3080 // return true if the same array | |
3081 __ cmp(ary1_reg, ary2_reg); | |
1016 | 3082 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
681 | 3083 __ delayed()->add(G0, 1, result_reg); // equal |
3084 | |
3085 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
3086 __ delayed()->mov(G0, result_reg); // not equal | |
3087 | |
3088 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
3089 __ delayed()->mov(G0, result_reg); // not equal | |
3090 | |
3091 //load the lengths of arrays | |
727 | 3092 __ ld(Address(ary1_reg, length_offset), tmp1_reg); |
3093 __ ld(Address(ary2_reg, length_offset), tmp2_reg); | |
681 | 3094 |
3095 // return false if the two arrays are not equal length | |
3096 __ cmp(tmp1_reg, tmp2_reg); | |
3097 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
3098 __ delayed()->mov(G0, result_reg); // not equal | |
3099 | |
3839 | 3100 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn); |
681 | 3101 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
3102 | |
3103 // load array addresses | |
3104 __ add(ary1_reg, base_offset, ary1_reg); | |
3105 __ add(ary2_reg, base_offset, ary2_reg); | |
3106 | |
3107 // renaming registers | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3108 Register chr1_reg = result_reg; // for characters in ary1 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3109 Register chr2_reg = tmp2_reg; // for characters in ary2 |
681 | 3110 Register limit_reg = tmp1_reg; // length |
3111 | |
3112 // set byte count | |
3113 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3114 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3115 // Compare char[] arrays aligned to 4 bytes. |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3116 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
3117 chr1_reg, chr2_reg, Ldone); |
681 | 3118 __ add(G0, 1, result_reg); // equals |
3119 | |
3120 __ bind(Ldone); | |
3121 %} | |
3122 | |
0 | 3123 enc_class enc_rethrow() %{ |
1748 | 3124 cbuf.set_insts_mark(); |
0 | 3125 Register temp_reg = G3; |
727 | 3126 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
0 | 3127 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
3128 MacroAssembler _masm(&cbuf); | |
3129 #ifdef ASSERT | |
3130 __ save_frame(0); | |
727 | 3131 AddressLiteral last_rethrow_addrlit(&last_rethrow); |
3132 __ sethi(last_rethrow_addrlit, L1); | |
3133 Address addr(L1, last_rethrow_addrlit.low10()); | |
10997 | 3134 __ rdpc(L2); |
0 | 3135 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to |
727 | 3136 __ st_ptr(L2, addr); |
0 | 3137 __ restore(); |
3138 #endif | |
727 | 3139 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
0 | 3140 __ delayed()->nop(); |
3141 %} | |
3142 | |
3143 enc_class emit_mem_nop() %{ | |
3144 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
1748 | 3145 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); |
0 | 3146 %} |
3147 | |
3148 enc_class emit_fadd_nop() %{ | |
3149 // Generates the instruction FMOVS f31,f31 | |
1748 | 3150 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); |
0 | 3151 %} |
3152 | |
3153 enc_class emit_br_nop() %{ | |
3154 // Generates the instruction BPN,PN . | |
1748 | 3155 cbuf.insts()->emit_int32((unsigned int) 0x00400000); |
0 | 3156 %} |
3157 | |
3158 enc_class enc_membar_acquire %{ | |
3159 MacroAssembler _masm(&cbuf); | |
3160 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
3161 %} | |
3162 | |
3163 enc_class enc_membar_release %{ | |
3164 MacroAssembler _masm(&cbuf); | |
3165 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
3166 %} | |
3167 | |
3168 enc_class enc_membar_volatile %{ | |
3169 MacroAssembler _masm(&cbuf); | |
3170 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
3171 %} | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3172 |
0 | 3173 %} |
3174 | |
3175 //----------FRAME-------------------------------------------------------------- | |
3176 // Definition of frame structure and management information. | |
3177 // | |
3178 // S T A C K L A Y O U T Allocators stack-slot number | |
3179 // | (to get allocators register number | |
3180 // G Owned by | | v add VMRegImpl::stack0) | |
3181 // r CALLER | | | |
3182 // o | +--------+ pad to even-align allocators stack-slot | |
3183 // w V | pad0 | numbers; owned by CALLER | |
3184 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
3185 // h ^ | in | 5 | |
3186 // | | args | 4 Holes in incoming args owned by SELF | |
3187 // | | | | 3 | |
3188 // | | +--------+ | |
3189 // V | | old out| Empty on Intel, window on Sparc | |
3190 // | old |preserve| Must be even aligned. | |
3191 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
3192 // | | in | 3 area for Intel ret address | |
3193 // Owned by |preserve| Empty on Sparc. | |
3194 // SELF +--------+ | |
3195 // | | pad2 | 2 pad to align old SP | |
3196 // | +--------+ 1 | |
3197 // | | locks | 0 | |
3198 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
3199 // | | pad1 | 11 pad to align new SP | |
3200 // | +--------+ | |
3201 // | | | 10 | |
3202 // | | spills | 9 spills | |
3203 // V | | 8 (pad0 slot for callee) | |
3204 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
3205 // ^ | out | 7 | |
3206 // | | args | 6 Holes in outgoing args owned by CALLEE | |
3207 // Owned by +--------+ | |
3208 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
3209 // | new |preserve| Must be even-aligned. | |
3210 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
3211 // | | | | |
3212 // | |
3213 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
3214 // known from SELF's arguments and the Java calling convention. | |
3215 // Region 6-7 is determined per call site. | |
3216 // Note 2: If the calling convention leaves holes in the incoming argument | |
3217 // area, those holes are owned by SELF. Holes in the outgoing area | |
3218 // are owned by the CALLEE. Holes should not be nessecary in the | |
3219 // incoming area, as the Java calling convention is completely under | |
3220 // the control of the AD file. Doubles can be sorted and packed to | |
3221 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
3222 // varargs C calling conventions. | |
3223 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
3224 // even aligned with pad0 as needed. | |
3225 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
3226 // region 6-11 is even aligned; it may be padded out more so that | |
3227 // the region from SP to FP meets the minimum stack alignment. | |
3228 | |
3229 frame %{ | |
3230 // What direction does stack grow in (assumed to be same for native & Java) | |
3231 stack_direction(TOWARDS_LOW); | |
3232 | |
3233 // These two registers define part of the calling convention | |
3234 // between compiled code and the interpreter. | |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
3235 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C |
0 | 3236 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter |
3237 | |
3238 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
3239 cisc_spilling_operand_name(indOffset); | |
3240 | |
3241 // Number of stack slots consumed by a Monitor enter | |
3242 #ifdef _LP64 | |
3243 sync_stack_slots(2); | |
3244 #else | |
3245 sync_stack_slots(1); | |
3246 #endif | |
3247 | |
3248 // Compiled code's Frame Pointer | |
3249 frame_pointer(R_SP); | |
3250 | |
3251 // Stack alignment requirement | |
3252 stack_alignment(StackAlignmentInBytes); | |
3253 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
3254 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
3255 | |
3256 // Number of stack slots between incoming argument block and the start of | |
3257 // a new frame. The PROLOG must add this many slots to the stack. The | |
3258 // EPILOG must remove this many slots. | |
3259 in_preserve_stack_slots(0); | |
3260 | |
3261 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
3262 // for calls to C. Supports the var-args backing area for register parms. | |
3263 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
3264 #ifdef _LP64 | |
3265 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
3266 varargs_C_out_slots_killed(12); | |
3267 #else | |
3268 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
3269 varargs_C_out_slots_killed( 7); | |
3270 #endif | |
3271 | |
3272 // The after-PROLOG location of the return address. Location of | |
3273 // return address specifies a type (REG or STACK) and a number | |
3274 // representing the register number (i.e. - use a register name) or | |
3275 // stack slot. | |
3276 return_addr(REG R_I7); // Ret Addr is in register I7 | |
3277 | |
3278 // Body of function which returns an OptoRegs array locating | |
3279 // arguments either in registers or in stack slots for calling | |
3280 // java | |
3281 calling_convention %{ | |
3282 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
3283 | |
3284 %} | |
3285 | |
3286 // Body of function which returns an OptoRegs array locating | |
3287 // arguments either in registers or in stack slots for callin | |
3288 // C. | |
3289 c_calling_convention %{ | |
3290 // This is obviously always outgoing | |
14416
6a936747b569
8024344: PPC64 (part 112): C argument in register AND stack slot.
goetz
parents:
12056
diff
changeset
|
3291 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); |
0 | 3292 %} |
3293 | |
3294 // Location of native (C/C++) and interpreter return values. This is specified to | |
3295 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
3296 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
3297 // to and from the register pairs is done by the appropriate call and epilog | |
3298 // opcodes. This simplifies the register allocator. | |
3299 c_return_value %{ | |
3300 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3301 #ifdef _LP64 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3302 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3303 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3304 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3305 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3306 #else // !_LP64 |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3307 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3308 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3309 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3310 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
0 | 3311 #endif |
3312 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3313 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3314 %} | |
3315 | |
3316 // Location of compiled Java return values. Same as C | |
3317 return_value %{ | |
3318 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3319 #ifdef _LP64 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3320 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3321 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3322 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3323 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3324 #else // !_LP64 |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3325 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3326 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3327 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3328 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
0 | 3329 #endif |
3330 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3331 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3332 %} | |
3333 | |
3334 %} | |
3335 | |
3336 | |
3337 //----------ATTRIBUTES--------------------------------------------------------- | |
3338 //----------Operand Attributes------------------------------------------------- | |
3339 op_attrib op_cost(1); // Required cost attribute | |
3340 | |
3341 //----------Instruction Attributes--------------------------------------------- | |
3342 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
3842 | 3343 ins_attrib ins_size(32); // Required size attribute (in bits) |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
3344 |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
3345 // avoid_back_to_back attribute is an expression that must return |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
3346 // one of the following values defined in MachNode: |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
3347 // AVOID_NONE - instruction can be placed anywhere |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
3348 // AVOID_BEFORE - instruction cannot be placed after an |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
3349 // instruction with MachNode::AVOID_AFTER |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
3350 // AVOID_AFTER - the next instruction cannot be the one |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
3351 // with MachNode::AVOID_BEFORE |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
3352 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
3353 // the same time |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
3354 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE); |
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
3355 |
3842 | 3356 ins_attrib ins_short_branch(0); // Required flag: is this instruction a |
3357 // non-matching short branch variant of some | |
0 | 3358 // long branch? |
3359 | |
3360 //----------OPERANDS----------------------------------------------------------- | |
3361 // Operand definitions must precede instruction definitions for correct parsing | |
3362 // in the ADLC because operands constitute user defined types which are used in | |
3363 // instruction definitions. | |
3364 | |
3365 //----------Simple Operands---------------------------------------------------- | |
3366 // Immediate Operands | |
3367 // Integer Immediate: 32-bit | |
3368 operand immI() %{ | |
3369 match(ConI); | |
3370 | |
3371 op_cost(0); | |
3372 // formats are generated automatically for constants and base registers | |
3373 format %{ %} | |
3374 interface(CONST_INTER); | |
3375 %} | |
3376 | |
824 | 3377 // Integer Immediate: 8-bit |
3378 operand immI8() %{ | |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
3379 predicate(Assembler::is_simm8(n->get_int())); |
824 | 3380 match(ConI); |
3381 op_cost(0); | |
3382 format %{ %} | |
3383 interface(CONST_INTER); | |
3384 %} | |
3385 | |
0 | 3386 // Integer Immediate: 13-bit |
3387 operand immI13() %{ | |
3388 predicate(Assembler::is_simm13(n->get_int())); | |
3389 match(ConI); | |
3390 op_cost(0); | |
3391 | |
3392 format %{ %} | |
3393 interface(CONST_INTER); | |
3394 %} | |
3395 | |
785 | 3396 // Integer Immediate: 13-bit minus 7 |
3397 operand immI13m7() %{ | |
3398 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); | |
3399 match(ConI); | |
3400 op_cost(0); | |
3401 | |
3402 format %{ %} | |
3403 interface(CONST_INTER); | |
3404 %} | |
3405 | |
824 | 3406 // Integer Immediate: 16-bit |
3407 operand immI16() %{ | |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
3408 predicate(Assembler::is_simm16(n->get_int())); |
824 | 3409 match(ConI); |
3410 op_cost(0); | |
3411 format %{ %} | |
3412 interface(CONST_INTER); | |
3413 %} | |
3414 | |
17506
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
3415 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13) |
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
3416 operand immU12() %{ |
0 | 3417 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); |
3418 match(ConI); | |
3419 op_cost(0); | |
3420 | |
3421 format %{ %} | |
3422 interface(CONST_INTER); | |
3423 %} | |
3424 | |
3425 // Integer Immediate: 6-bit | |
3426 operand immU6() %{ | |
3427 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
3428 match(ConI); | |
3429 op_cost(0); | |
3430 format %{ %} | |
3431 interface(CONST_INTER); | |
3432 %} | |
3433 | |
3434 // Integer Immediate: 11-bit | |
3435 operand immI11() %{ | |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
3436 predicate(Assembler::is_simm11(n->get_int())); |
0 | 3437 match(ConI); |
3438 op_cost(0); | |
3439 format %{ %} | |
3440 interface(CONST_INTER); | |
3441 %} | |
3442 | |
3851 | 3443 // Integer Immediate: 5-bit |
3444 operand immI5() %{ | |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
3445 predicate(Assembler::is_simm5(n->get_int())); |
3851 | 3446 match(ConI); |
3447 op_cost(0); | |
3448 format %{ %} | |
3449 interface(CONST_INTER); | |
3450 %} | |
3451 | |
17506
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
3452 // Int Immediate non-negative |
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
3453 operand immU31() |
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
3454 %{ |
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
3455 predicate(n->get_int() >= 0); |
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
3456 match(ConI); |
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
3457 |
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
3458 op_cost(0); |
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
3459 format %{ %} |
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
3460 interface(CONST_INTER); |
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
3461 %} |
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
3462 |
0 | 3463 // Integer Immediate: 0-bit |
3464 operand immI0() %{ | |
3465 predicate(n->get_int() == 0); | |
3466 match(ConI); | |
3467 op_cost(0); | |
3468 | |
3469 format %{ %} | |
3470 interface(CONST_INTER); | |
3471 %} | |
3472 | |
3473 // Integer Immediate: the value 10 | |
3474 operand immI10() %{ | |
3475 predicate(n->get_int() == 10); | |
3476 match(ConI); | |
3477 op_cost(0); | |
3478 | |
3479 format %{ %} | |
3480 interface(CONST_INTER); | |
3481 %} | |
3482 | |
3483 // Integer Immediate: the values 0-31 | |
3484 operand immU5() %{ | |
3485 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
3486 match(ConI); | |
3487 op_cost(0); | |
3488 | |
3489 format %{ %} | |
3490 interface(CONST_INTER); | |
3491 %} | |
3492 | |
3493 // Integer Immediate: the values 1-31 | |
3494 operand immI_1_31() %{ | |
3495 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
3496 match(ConI); | |
3497 op_cost(0); | |
3498 | |
3499 format %{ %} | |
3500 interface(CONST_INTER); | |
3501 %} | |
3502 | |
3503 // Integer Immediate: the values 32-63 | |
3504 operand immI_32_63() %{ | |
3505 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
3506 match(ConI); | |
3507 op_cost(0); | |
3508 | |
3509 format %{ %} | |
3510 interface(CONST_INTER); | |
3511 %} | |
3512 | |
785 | 3513 // Immediates for special shifts (sign extend) |
3514 | |
3515 // Integer Immediate: the value 16 | |
3516 operand immI_16() %{ | |
3517 predicate(n->get_int() == 16); | |
3518 match(ConI); | |
3519 op_cost(0); | |
3520 | |
3521 format %{ %} | |
3522 interface(CONST_INTER); | |
3523 %} | |
3524 | |
3525 // Integer Immediate: the value 24 | |
3526 operand immI_24() %{ | |
3527 predicate(n->get_int() == 24); | |
3528 match(ConI); | |
3529 op_cost(0); | |
3530 | |
3531 format %{ %} | |
3532 interface(CONST_INTER); | |
3533 %} | |
3534 | |
0 | 3535 // Integer Immediate: the value 255 |
3536 operand immI_255() %{ | |
3537 predicate( n->get_int() == 255 ); | |
3538 match(ConI); | |
3539 op_cost(0); | |
3540 | |
3541 format %{ %} | |
3542 interface(CONST_INTER); | |
3543 %} | |
3544 | |
785 | 3545 // Integer Immediate: the value 65535 |
3546 operand immI_65535() %{ | |
3547 predicate(n->get_int() == 65535); | |
3548 match(ConI); | |
3549 op_cost(0); | |
3550 | |
3551 format %{ %} | |
3552 interface(CONST_INTER); | |
3553 %} | |
3554 | |
0 | 3555 // Long Immediate: the value FF |
3556 operand immL_FF() %{ | |
3557 predicate( n->get_long() == 0xFFL ); | |
3558 match(ConL); | |
3559 op_cost(0); | |
3560 | |
3561 format %{ %} | |
3562 interface(CONST_INTER); | |
3563 %} | |
3564 | |
3565 // Long Immediate: the value FFFF | |
3566 operand immL_FFFF() %{ | |
3567 predicate( n->get_long() == 0xFFFFL ); | |
3568 match(ConL); | |
3569 op_cost(0); | |
3570 | |
3571 format %{ %} | |
3572 interface(CONST_INTER); | |
3573 %} | |
3574 | |
3575 // Pointer Immediate: 32 or 64-bit | |
3576 operand immP() %{ | |
3577 match(ConP); | |
3578 | |
3579 op_cost(5); | |
3580 // formats are generated automatically for constants and base registers | |
3581 format %{ %} | |
3582 interface(CONST_INTER); | |
3583 %} | |
3584 | |
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3585 #ifdef _LP64 |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3586 // Pointer Immediate: 64-bit |
2008 | 3587 operand immP_set() %{ |
2080 | 3588 predicate(!VM_Version::is_niagara_plus()); |
2008 | 3589 match(ConP); |
3590 | |
3591 op_cost(5); | |
3592 // formats are generated automatically for constants and base registers | |
3593 format %{ %} | |
3594 interface(CONST_INTER); | |
3595 %} | |
3596 | |
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3597 // Pointer Immediate: 64-bit |
2008 | 3598 // From Niagara2 processors on a load should be better than materializing. |
3599 operand immP_load() %{ | |
2080 | 3600 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); |
2008 | 3601 match(ConP); |
3602 | |
3603 op_cost(5); | |
3604 // formats are generated automatically for constants and base registers | |
3605 format %{ %} | |
3606 interface(CONST_INTER); | |
3607 %} | |
3608 | |
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3609 // Pointer Immediate: 64-bit |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3610 operand immP_no_oop_cheap() %{ |
2080 | 3611 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); |
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3612 match(ConP); |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3613 |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3614 op_cost(5); |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3615 // formats are generated automatically for constants and base registers |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3616 format %{ %} |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3617 interface(CONST_INTER); |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3618 %} |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3619 #endif |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
3620 |
0 | 3621 operand immP13() %{ |
3622 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
3623 match(ConP); | |
3624 op_cost(0); | |
3625 | |
3626 format %{ %} | |
3627 interface(CONST_INTER); | |
3628 %} | |
3629 | |
3630 operand immP0() %{ | |
3631 predicate(n->get_ptr() == 0); | |
3632 match(ConP); | |
3633 op_cost(0); | |
3634 | |
3635 format %{ %} | |
3636 interface(CONST_INTER); | |
3637 %} | |
3638 | |
3639 operand immP_poll() %{ | |
3640 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
3641 match(ConP); | |
3642 | |
3643 // formats are generated automatically for constants and base registers | |
3644 format %{ %} | |
3645 interface(CONST_INTER); | |
3646 %} | |
3647 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3648 // Pointer Immediate |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3649 operand immN() |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3650 %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3651 match(ConN); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3652 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3653 op_cost(10); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3654 format %{ %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3655 interface(CONST_INTER); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3656 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3657 |
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
3658 operand immNKlass() |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
3659 %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
3660 match(ConNKlass); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
3661 |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
3662 op_cost(10); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
3663 format %{ %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
3664 interface(CONST_INTER); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
3665 %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
3666 |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3667 // NULL Pointer Immediate |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3668 operand immN0() |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3669 %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3670 predicate(n->get_narrowcon() == 0); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3671 match(ConN); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3672 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3673 op_cost(0); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3674 format %{ %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3675 interface(CONST_INTER); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3676 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3677 |
0 | 3678 operand immL() %{ |
3679 match(ConL); | |
3680 op_cost(40); | |
3681 // formats are generated automatically for constants and base registers | |
3682 format %{ %} | |
3683 interface(CONST_INTER); | |
3684 %} | |
3685 | |
3686 operand immL0() %{ | |
3687 predicate(n->get_long() == 0L); | |
3688 match(ConL); | |
3689 op_cost(0); | |
3690 // formats are generated automatically for constants and base registers | |
3691 format %{ %} | |
3692 interface(CONST_INTER); | |
3693 %} | |
3694 | |
3851 | 3695 // Integer Immediate: 5-bit |
3696 operand immL5() %{ | |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
3697 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long())); |
3851 | 3698 match(ConL); |
3699 op_cost(0); | |
3700 format %{ %} | |
3701 interface(CONST_INTER); | |
3702 %} | |
3703 | |
0 | 3704 // Long Immediate: 13-bit |
3705 operand immL13() %{ | |
3706 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
3707 match(ConL); | |
3708 op_cost(0); | |
3709 | |
3710 format %{ %} | |
3711 interface(CONST_INTER); | |
3712 %} | |
3713 | |
785 | 3714 // Long Immediate: 13-bit minus 7 |
3715 operand immL13m7() %{ | |
3716 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); | |
3717 match(ConL); | |
3718 op_cost(0); | |
3719 | |
3720 format %{ %} | |
3721 interface(CONST_INTER); | |
3722 %} | |
3723 | |
0 | 3724 // Long Immediate: low 32-bit mask |
3725 operand immL_32bits() %{ | |
3726 predicate(n->get_long() == 0xFFFFFFFFL); | |
3727 match(ConL); | |
3728 op_cost(0); | |
3729 | |
3730 format %{ %} | |
3731 interface(CONST_INTER); | |
3732 %} | |
3733 | |
2008 | 3734 // Long Immediate: cheap (materialize in <= 3 instructions) |
3735 operand immL_cheap() %{ | |
2080 | 3736 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); |
2008 | 3737 match(ConL); |
3738 op_cost(0); | |
3739 | |
3740 format %{ %} | |
3741 interface(CONST_INTER); | |
3742 %} | |
3743 | |
3744 // Long Immediate: expensive (materialize in > 3 instructions) | |
3745 operand immL_expensive() %{ | |
2080 | 3746 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3); |
2008 | 3747 match(ConL); |
3748 op_cost(0); | |
3749 | |
3750 format %{ %} | |
3751 interface(CONST_INTER); | |
3752 %} | |
3753 | |
0 | 3754 // Double Immediate |
3755 operand immD() %{ | |
3756 match(ConD); | |
3757 | |
3758 op_cost(40); | |
3759 format %{ %} | |
3760 interface(CONST_INTER); | |
3761 %} | |
3762 | |
3763 operand immD0() %{ | |
3764 #ifdef _LP64 | |
3765 // on 64-bit architectures this comparision is faster | |
3766 predicate(jlong_cast(n->getd()) == 0); | |
3767 #else | |
3768 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
3769 #endif | |
3770 match(ConD); | |
3771 | |
3772 op_cost(0); | |
3773 format %{ %} | |
3774 interface(CONST_INTER); | |
3775 %} | |
3776 | |
3777 // Float Immediate | |
3778 operand immF() %{ | |
3779 match(ConF); | |
3780 | |
3781 op_cost(20); | |
3782 format %{ %} | |
3783 interface(CONST_INTER); | |
3784 %} | |
3785 | |
3786 // Float Immediate: 0 | |
3787 operand immF0() %{ | |
3788 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
3789 match(ConF); | |
3790 | |
3791 op_cost(0); | |
3792 format %{ %} | |
3793 interface(CONST_INTER); | |
3794 %} | |
3795 | |
3796 // Integer Register Operands | |
3797 // Integer Register | |
3798 operand iRegI() %{ | |
3799 constraint(ALLOC_IN_RC(int_reg)); | |
3800 match(RegI); | |
3801 | |
3802 match(notemp_iRegI); | |
3803 match(g1RegI); | |
3804 match(o0RegI); | |
3805 match(iRegIsafe); | |
3806 | |
3807 format %{ %} | |
3808 interface(REG_INTER); | |
3809 %} | |
3810 | |
3811 operand notemp_iRegI() %{ | |
3812 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
3813 match(RegI); | |
3814 | |
3815 match(o0RegI); | |
3816 | |
3817 format %{ %} | |
3818 interface(REG_INTER); | |
3819 %} | |
3820 | |
3821 operand o0RegI() %{ | |
3822 constraint(ALLOC_IN_RC(o0_regI)); | |
3823 match(iRegI); | |
3824 | |
3825 format %{ %} | |
3826 interface(REG_INTER); | |
3827 %} | |
3828 | |
3829 // Pointer Register | |
3830 operand iRegP() %{ | |
3831 constraint(ALLOC_IN_RC(ptr_reg)); | |
3832 match(RegP); | |
3833 | |
3834 match(lock_ptr_RegP); | |
3835 match(g1RegP); | |
3836 match(g2RegP); | |
3837 match(g3RegP); | |
3838 match(g4RegP); | |
3839 match(i0RegP); | |
3840 match(o0RegP); | |
3841 match(o1RegP); | |
3842 match(l7RegP); | |
3843 | |
3844 format %{ %} | |
3845 interface(REG_INTER); | |
3846 %} | |
3847 | |
3848 operand sp_ptr_RegP() %{ | |
3849 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
3850 match(RegP); | |
3851 match(iRegP); | |
3852 | |
3853 format %{ %} | |
3854 interface(REG_INTER); | |
3855 %} | |
3856 | |
3857 operand lock_ptr_RegP() %{ | |
3858 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
3859 match(RegP); | |
3860 match(i0RegP); | |
3861 match(o0RegP); | |
3862 match(o1RegP); | |
3863 match(l7RegP); | |
3864 | |
3865 format %{ %} | |
3866 interface(REG_INTER); | |
3867 %} | |
3868 | |
3869 operand g1RegP() %{ | |
3870 constraint(ALLOC_IN_RC(g1_regP)); | |
3871 match(iRegP); | |
3872 | |
3873 format %{ %} | |
3874 interface(REG_INTER); | |
3875 %} | |
3876 | |
3877 operand g2RegP() %{ | |
3878 constraint(ALLOC_IN_RC(g2_regP)); | |
3879 match(iRegP); | |
3880 | |
3881 format %{ %} | |
3882 interface(REG_INTER); | |
3883 %} | |
3884 | |
3885 operand g3RegP() %{ | |
3886 constraint(ALLOC_IN_RC(g3_regP)); | |
3887 match(iRegP); | |
3888 | |
3889 format %{ %} | |
3890 interface(REG_INTER); | |
3891 %} | |
3892 | |
3893 operand g1RegI() %{ | |
3894 constraint(ALLOC_IN_RC(g1_regI)); | |
3895 match(iRegI); | |
3896 | |
3897 format %{ %} | |
3898 interface(REG_INTER); | |
3899 %} | |
3900 | |
3901 operand g3RegI() %{ | |
3902 constraint(ALLOC_IN_RC(g3_regI)); | |
3903 match(iRegI); | |
3904 | |
3905 format %{ %} | |
3906 interface(REG_INTER); | |
3907 %} | |
3908 | |
3909 operand g4RegI() %{ | |
3910 constraint(ALLOC_IN_RC(g4_regI)); | |
3911 match(iRegI); | |
3912 | |
3913 format %{ %} | |
3914 interface(REG_INTER); | |
3915 %} | |
3916 | |
3917 operand g4RegP() %{ | |
3918 constraint(ALLOC_IN_RC(g4_regP)); | |
3919 match(iRegP); | |
3920 | |
3921 format %{ %} | |
3922 interface(REG_INTER); | |
3923 %} | |
3924 | |
3925 operand i0RegP() %{ | |
3926 constraint(ALLOC_IN_RC(i0_regP)); | |
3927 match(iRegP); | |
3928 | |
3929 format %{ %} | |
3930 interface(REG_INTER); | |
3931 %} | |
3932 | |
3933 operand o0RegP() %{ | |
3934 constraint(ALLOC_IN_RC(o0_regP)); | |
3935 match(iRegP); | |
3936 | |
3937 format %{ %} | |
3938 interface(REG_INTER); | |
3939 %} | |
3940 | |
3941 operand o1RegP() %{ | |
3942 constraint(ALLOC_IN_RC(o1_regP)); | |
3943 match(iRegP); | |
3944 | |
3945 format %{ %} | |
3946 interface(REG_INTER); | |
3947 %} | |
3948 | |
3949 operand o2RegP() %{ | |
3950 constraint(ALLOC_IN_RC(o2_regP)); | |
3951 match(iRegP); | |
3952 | |
3953 format %{ %} | |
3954 interface(REG_INTER); | |
3955 %} | |
3956 | |
3957 operand o7RegP() %{ | |
3958 constraint(ALLOC_IN_RC(o7_regP)); | |
3959 match(iRegP); | |
3960 | |
3961 format %{ %} | |
3962 interface(REG_INTER); | |
3963 %} | |
3964 | |
3965 operand l7RegP() %{ | |
3966 constraint(ALLOC_IN_RC(l7_regP)); | |
3967 match(iRegP); | |
3968 | |
3969 format %{ %} | |
3970 interface(REG_INTER); | |
3971 %} | |
3972 | |
3973 operand o7RegI() %{ | |
3974 constraint(ALLOC_IN_RC(o7_regI)); | |
3975 match(iRegI); | |
3976 | |
3977 format %{ %} | |
3978 interface(REG_INTER); | |
3979 %} | |
3980 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3981 operand iRegN() %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3982 constraint(ALLOC_IN_RC(int_reg)); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3983 match(RegN); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3984 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3985 format %{ %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3986 interface(REG_INTER); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3987 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3988 |
0 | 3989 // Long Register |
3990 operand iRegL() %{ | |
3991 constraint(ALLOC_IN_RC(long_reg)); | |
3992 match(RegL); | |
3993 | |
3994 format %{ %} | |
3995 interface(REG_INTER); | |
3996 %} | |
3997 | |
3998 operand o2RegL() %{ | |
3999 constraint(ALLOC_IN_RC(o2_regL)); | |
4000 match(iRegL); | |
4001 | |
4002 format %{ %} | |
4003 interface(REG_INTER); | |
4004 %} | |
4005 | |
4006 operand o7RegL() %{ | |
4007 constraint(ALLOC_IN_RC(o7_regL)); | |
4008 match(iRegL); | |
4009 | |
4010 format %{ %} | |
4011 interface(REG_INTER); | |
4012 %} | |
4013 | |
4014 operand g1RegL() %{ | |
4015 constraint(ALLOC_IN_RC(g1_regL)); | |
4016 match(iRegL); | |
4017 | |
4018 format %{ %} | |
4019 interface(REG_INTER); | |
4020 %} | |
4021 | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
4022 operand g3RegL() %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
4023 constraint(ALLOC_IN_RC(g3_regL)); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
4024 match(iRegL); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
4025 |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
4026 format %{ %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
4027 interface(REG_INTER); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
4028 %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
4029 |
0 | 4030 // Int Register safe |
4031 // This is 64bit safe | |
4032 operand iRegIsafe() %{ | |
4033 constraint(ALLOC_IN_RC(long_reg)); | |
4034 | |
4035 match(iRegI); | |
4036 | |
4037 format %{ %} | |
4038 interface(REG_INTER); | |
4039 %} | |
4040 | |
4041 // Condition Code Flag Register | |
4042 operand flagsReg() %{ | |
4043 constraint(ALLOC_IN_RC(int_flags)); | |
4044 match(RegFlags); | |
4045 | |
4046 format %{ "ccr" %} // both ICC and XCC | |
4047 interface(REG_INTER); | |
4048 %} | |
4049 | |
4050 // Condition Code Register, unsigned comparisons. | |
4051 operand flagsRegU() %{ | |
4052 constraint(ALLOC_IN_RC(int_flags)); | |
4053 match(RegFlags); | |
4054 | |
4055 format %{ "icc_U" %} | |
4056 interface(REG_INTER); | |
4057 %} | |
4058 | |
4059 // Condition Code Register, pointer comparisons. | |
4060 operand flagsRegP() %{ | |
4061 constraint(ALLOC_IN_RC(int_flags)); | |
4062 match(RegFlags); | |
4063 | |
4064 #ifdef _LP64 | |
4065 format %{ "xcc_P" %} | |
4066 #else | |
4067 format %{ "icc_P" %} | |
4068 #endif | |
4069 interface(REG_INTER); | |
4070 %} | |
4071 | |
4072 // Condition Code Register, long comparisons. | |
4073 operand flagsRegL() %{ | |
4074 constraint(ALLOC_IN_RC(int_flags)); | |
4075 match(RegFlags); | |
4076 | |
4077 format %{ "xcc_L" %} | |
4078 interface(REG_INTER); | |
4079 %} | |
4080 | |
4081 // Condition Code Register, floating comparisons, unordered same as "less". | |
4082 operand flagsRegF() %{ | |
4083 constraint(ALLOC_IN_RC(float_flags)); | |
4084 match(RegFlags); | |
4085 match(flagsRegF0); | |
4086 | |
4087 format %{ %} | |
4088 interface(REG_INTER); | |
4089 %} | |
4090 | |
4091 operand flagsRegF0() %{ | |
4092 constraint(ALLOC_IN_RC(float_flag0)); | |
4093 match(RegFlags); | |
4094 | |
4095 format %{ %} | |
4096 interface(REG_INTER); | |
4097 %} | |
4098 | |
4099 | |
4100 // Condition Code Flag Register used by long compare | |
4101 operand flagsReg_long_LTGE() %{ | |
4102 constraint(ALLOC_IN_RC(int_flags)); | |
4103 match(RegFlags); | |
4104 format %{ "icc_LTGE" %} | |
4105 interface(REG_INTER); | |
4106 %} | |
4107 operand flagsReg_long_EQNE() %{ | |
4108 constraint(ALLOC_IN_RC(int_flags)); | |
4109 match(RegFlags); | |
4110 format %{ "icc_EQNE" %} | |
4111 interface(REG_INTER); | |
4112 %} | |
4113 operand flagsReg_long_LEGT() %{ | |
4114 constraint(ALLOC_IN_RC(int_flags)); | |
4115 match(RegFlags); | |
4116 format %{ "icc_LEGT" %} | |
4117 interface(REG_INTER); | |
4118 %} | |
4119 | |
4120 | |
4121 operand regD() %{ | |
4122 constraint(ALLOC_IN_RC(dflt_reg)); | |
4123 match(RegD); | |
4124 | |
551 | 4125 match(regD_low); |
4126 | |
0 | 4127 format %{ %} |
4128 interface(REG_INTER); | |
4129 %} | |
4130 | |
4131 operand regF() %{ | |
4132 constraint(ALLOC_IN_RC(sflt_reg)); | |
4133 match(RegF); | |
4134 | |
4135 format %{ %} | |
4136 interface(REG_INTER); | |
4137 %} | |
4138 | |
4139 operand regD_low() %{ | |
4140 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
551 | 4141 match(regD); |
0 | 4142 |
4143 format %{ %} | |
4144 interface(REG_INTER); | |
4145 %} | |
4146 | |
4147 // Special Registers | |
4148 | |
4149 // Method Register | |
4150 operand inline_cache_regP(iRegP reg) %{ | |
4151 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
4152 match(reg); | |
4153 format %{ %} | |
4154 interface(REG_INTER); | |
4155 %} | |
4156 | |
4157 operand interpreter_method_oop_regP(iRegP reg) %{ | |
4158 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
4159 match(reg); | |
4160 format %{ %} | |
4161 interface(REG_INTER); | |
4162 %} | |
4163 | |
4164 | |
4165 //----------Complex Operands--------------------------------------------------- | |
4166 // Indirect Memory Reference | |
4167 operand indirect(sp_ptr_RegP reg) %{ | |
4168 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4169 match(reg); | |
4170 | |
4171 op_cost(100); | |
4172 format %{ "[$reg]" %} | |
4173 interface(MEMORY_INTER) %{ | |
4174 base($reg); | |
4175 index(0x0); | |
4176 scale(0x0); | |
4177 disp(0x0); | |
4178 %} | |
4179 %} | |
4180 | |
785 | 4181 // Indirect with simm13 Offset |
0 | 4182 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
4183 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4184 match(AddP reg offset); | |
4185 | |
4186 op_cost(100); | |
4187 format %{ "[$reg + $offset]" %} | |
4188 interface(MEMORY_INTER) %{ | |
4189 base($reg); | |
4190 index(0x0); | |
4191 scale(0x0); | |
4192 disp($offset); | |
4193 %} | |
4194 %} | |
4195 | |
785 | 4196 // Indirect with simm13 Offset minus 7 |
4197 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ | |
4198 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4199 match(AddP reg offset); | |
4200 | |
4201 op_cost(100); | |
4202 format %{ "[$reg + $offset]" %} | |
4203 interface(MEMORY_INTER) %{ | |
4204 base($reg); | |
4205 index(0x0); | |
4206 scale(0x0); | |
4207 disp($offset); | |
4208 %} | |
4209 %} | |
4210 | |
0 | 4211 // Note: Intel has a swapped version also, like this: |
4212 //operand indOffsetX(iRegI reg, immP offset) %{ | |
4213 // constraint(ALLOC_IN_RC(int_reg)); | |
4214 // match(AddP offset reg); | |
4215 // | |
4216 // op_cost(100); | |
4217 // format %{ "[$reg + $offset]" %} | |
4218 // interface(MEMORY_INTER) %{ | |
4219 // base($reg); | |
4220 // index(0x0); | |
4221 // scale(0x0); | |
4222 // disp($offset); | |
4223 // %} | |
4224 //%} | |
4225 //// However, it doesn't make sense for SPARC, since | |
4226 // we have no particularly good way to embed oops in | |
4227 // single instructions. | |
4228 | |
4229 // Indirect with Register Index | |
4230 operand indIndex(iRegP addr, iRegX index) %{ | |
4231 constraint(ALLOC_IN_RC(ptr_reg)); | |
4232 match(AddP addr index); | |
4233 | |
4234 op_cost(100); | |
4235 format %{ "[$addr + $index]" %} | |
4236 interface(MEMORY_INTER) %{ | |
4237 base($addr); | |
4238 index($index); | |
4239 scale(0x0); | |
4240 disp(0x0); | |
4241 %} | |
4242 %} | |
4243 | |
4244 //----------Special Memory Operands-------------------------------------------- | |
4245 // Stack Slot Operand - This operand is used for loading and storing temporary | |
4246 // values on the stack where a match requires a value to | |
4247 // flow through memory. | |
4248 operand stackSlotI(sRegI reg) %{ | |
4249 constraint(ALLOC_IN_RC(stack_slots)); | |
4250 op_cost(100); | |
4251 //match(RegI); | |
4252 format %{ "[$reg]" %} | |
4253 interface(MEMORY_INTER) %{ | |
4254 base(0xE); // R_SP | |
4255 index(0x0); | |
4256 scale(0x0); | |
4257 disp($reg); // Stack Offset | |
4258 %} | |
4259 %} | |
4260 | |
4261 operand stackSlotP(sRegP reg) %{ | |
4262 constraint(ALLOC_IN_RC(stack_slots)); | |
4263 op_cost(100); | |
4264 //match(RegP); | |
4265 format %{ "[$reg]" %} | |
4266 interface(MEMORY_INTER) %{ | |
4267 base(0xE); // R_SP | |
4268 index(0x0); | |
4269 scale(0x0); | |
4270 disp($reg); // Stack Offset | |
4271 %} | |
4272 %} | |
4273 | |
4274 operand stackSlotF(sRegF reg) %{ | |
4275 constraint(ALLOC_IN_RC(stack_slots)); | |
4276 op_cost(100); | |
4277 //match(RegF); | |
4278 format %{ "[$reg]" %} | |
4279 interface(MEMORY_INTER) %{ | |
4280 base(0xE); // R_SP | |
4281 index(0x0); | |
4282 scale(0x0); | |
4283 disp($reg); // Stack Offset | |
4284 %} | |
4285 %} | |
4286 operand stackSlotD(sRegD reg) %{ | |
4287 constraint(ALLOC_IN_RC(stack_slots)); | |
4288 op_cost(100); | |
4289 //match(RegD); | |
4290 format %{ "[$reg]" %} | |
4291 interface(MEMORY_INTER) %{ | |
4292 base(0xE); // R_SP | |
4293 index(0x0); | |
4294 scale(0x0); | |
4295 disp($reg); // Stack Offset | |
4296 %} | |
4297 %} | |
4298 operand stackSlotL(sRegL reg) %{ | |
4299 constraint(ALLOC_IN_RC(stack_slots)); | |
4300 op_cost(100); | |
4301 //match(RegL); | |
4302 format %{ "[$reg]" %} | |
4303 interface(MEMORY_INTER) %{ | |
4304 base(0xE); // R_SP | |
4305 index(0x0); | |
4306 scale(0x0); | |
4307 disp($reg); // Stack Offset | |
4308 %} | |
4309 %} | |
4310 | |
4311 // Operands for expressing Control Flow | |
4312 // NOTE: Label is a predefined operand which should not be redefined in | |
4313 // the AD file. It is generically handled within the ADLC. | |
4314 | |
4315 //----------Conditional Branch Operands---------------------------------------- | |
4316 // Comparison Op - This is the operation of the comparison, and is limited to | |
4317 // the following set of codes: | |
4318 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
4319 // | |
4320 // Other attributes of the comparison, such as unsignedness, are specified | |
4321 // by the comparison instruction that sets a condition code flags register. | |
4322 // That result is represented by a flags operand whose subtype is appropriate | |
4323 // to the unsignedness (etc.) of the comparison. | |
4324 // | |
4325 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
4326 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
4327 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
4328 | |
4329 operand cmpOp() %{ | |
4330 match(Bool); | |
4331 | |
4332 format %{ "" %} | |
4333 interface(COND_INTER) %{ | |
4334 equal(0x1); | |
4335 not_equal(0x9); | |
4336 less(0x3); | |
4337 greater_equal(0xB); | |
4338 less_equal(0x2); | |
4339 greater(0xA); | |
12323 | 4340 overflow(0x7); |
4341 no_overflow(0xF); | |
0 | 4342 %} |
4343 %} | |
4344 | |
4345 // Comparison Op, unsigned | |
4346 operand cmpOpU() %{ | |
4347 match(Bool); | |
12323 | 4348 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4349 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
0 | 4350 |
4351 format %{ "u" %} | |
4352 interface(COND_INTER) %{ | |
4353 equal(0x1); | |
4354 not_equal(0x9); | |
4355 less(0x5); | |
4356 greater_equal(0xD); | |
4357 less_equal(0x4); | |
4358 greater(0xC); | |
12323 | 4359 overflow(0x7); |
4360 no_overflow(0xF); | |
0 | 4361 %} |
4362 %} | |
4363 | |
4364 // Comparison Op, pointer (same as unsigned) | |
4365 operand cmpOpP() %{ | |
4366 match(Bool); | |
12323 | 4367 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4368 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
0 | 4369 |
4370 format %{ "p" %} | |
4371 interface(COND_INTER) %{ | |
4372 equal(0x1); | |
4373 not_equal(0x9); | |
4374 less(0x5); | |
4375 greater_equal(0xD); | |
4376 less_equal(0x4); | |
4377 greater(0xC); | |
12323 | 4378 overflow(0x7); |
4379 no_overflow(0xF); | |
0 | 4380 %} |
4381 %} | |
4382 | |
4383 // Comparison Op, branch-register encoding | |
4384 operand cmpOp_reg() %{ | |
4385 match(Bool); | |
12323 | 4386 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4387 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
0 | 4388 |
4389 format %{ "" %} | |
4390 interface(COND_INTER) %{ | |
4391 equal (0x1); | |
4392 not_equal (0x5); | |
4393 less (0x3); | |
4394 greater_equal(0x7); | |
4395 less_equal (0x2); | |
4396 greater (0x6); | |
12323 | 4397 overflow(0x7); // not supported |
4398 no_overflow(0xF); // not supported | |
0 | 4399 %} |
4400 %} | |
4401 | |
4402 // Comparison Code, floating, unordered same as less | |
4403 operand cmpOpF() %{ | |
4404 match(Bool); | |
12323 | 4405 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4406 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
0 | 4407 |
4408 format %{ "fl" %} | |
4409 interface(COND_INTER) %{ | |
4410 equal(0x9); | |
4411 not_equal(0x1); | |
4412 less(0x3); | |
4413 greater_equal(0xB); | |
4414 less_equal(0xE); | |
4415 greater(0x6); | |
12323 | 4416 |
4417 overflow(0x7); // not supported | |
4418 no_overflow(0xF); // not supported | |
0 | 4419 %} |
4420 %} | |
4421 | |
4422 // Used by long compare | |
4423 operand cmpOp_commute() %{ | |
4424 match(Bool); | |
12323 | 4425 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
4426 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
0 | 4427 |
4428 format %{ "" %} | |
4429 interface(COND_INTER) %{ | |
4430 equal(0x1); | |
4431 not_equal(0x9); | |
4432 less(0xA); | |
4433 greater_equal(0x2); | |
4434 less_equal(0xB); | |
4435 greater(0x3); | |
12323 | 4436 overflow(0x7); |
4437 no_overflow(0xF); | |
0 | 4438 %} |
4439 %} | |
4440 | |
4441 //----------OPERAND CLASSES---------------------------------------------------- | |
4442 // Operand Classes are groups of operands that are used to simplify | |
605 | 4443 // instruction definitions by not requiring the AD writer to specify separate |
0 | 4444 // instructions for every form of operand when the instruction accepts |
4445 // multiple operand types with the same basic encoding and format. The classic | |
4446 // case of this is memory operands. | |
4447 opclass memory( indirect, indOffset13, indIndex ); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
4448 opclass indIndexMemory( indIndex ); |
0 | 4449 |
4450 //----------PIPELINE----------------------------------------------------------- | |
4451 pipeline %{ | |
4452 | |
4453 //----------ATTRIBUTES--------------------------------------------------------- | |
4454 attributes %{ | |
4455 fixed_size_instructions; // Fixed size instructions | |
4456 branch_has_delay_slot; // Branch has delay slot following | |
4457 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
4458 instruction_unit_size = 4; // An instruction is 4 bytes long | |
4459 instruction_fetch_unit_size = 16; // The processor fetches one line | |
4460 instruction_fetch_units = 1; // of 16 bytes | |
4461 | |
4462 // List of nop instructions | |
4463 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
4464 %} | |
4465 | |
4466 //----------RESOURCES---------------------------------------------------------- | |
4467 // Resources are the functional units available to the machine | |
4468 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
4469 | |
4470 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
4471 // Pipeline Description specifies the stages in the machine's pipeline | |
4472 | |
4473 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
4474 | |
4475 //----------PIPELINE CLASSES--------------------------------------------------- | |
4476 // Pipeline Classes describe the stages in which input and output are | |
4477 // referenced by the hardware pipeline. | |
4478 | |
4479 // Integer ALU reg-reg operation | |
4480 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4481 single_instruction; | |
4482 dst : E(write); | |
4483 src1 : R(read); | |
4484 src2 : R(read); | |
4485 IALU : R; | |
4486 %} | |
4487 | |
4488 // Integer ALU reg-reg long operation | |
4489 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
4490 instruction_count(2); | |
4491 dst : E(write); | |
4492 src1 : R(read); | |
4493 src2 : R(read); | |
4494 IALU : R; | |
4495 IALU : R; | |
4496 %} | |
4497 | |
4498 // Integer ALU reg-reg long dependent operation | |
4499 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
4500 instruction_count(1); multiple_bundles; | |
4501 dst : E(write); | |
4502 src1 : R(read); | |
4503 src2 : R(read); | |
4504 cr : E(write); | |
4505 IALU : R(2); | |
4506 %} | |
4507 | |
4508 // Integer ALU reg-imm operaion | |
4509 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4510 single_instruction; | |
4511 dst : E(write); | |
4512 src1 : R(read); | |
4513 IALU : R; | |
4514 %} | |
4515 | |
4516 // Integer ALU reg-reg operation with condition code | |
4517 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
4518 single_instruction; | |
4519 dst : E(write); | |
4520 cr : E(write); | |
4521 src1 : R(read); | |
4522 src2 : R(read); | |
4523 IALU : R; | |
4524 %} | |
4525 | |
4526 // Integer ALU reg-imm operation with condition code | |
4527 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
4528 single_instruction; | |
4529 dst : E(write); | |
4530 cr : E(write); | |
4531 src1 : R(read); | |
4532 IALU : R; | |
4533 %} | |
4534 | |
4535 // Integer ALU zero-reg operation | |
4536 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
4537 single_instruction; | |
4538 dst : E(write); | |
4539 src2 : R(read); | |
4540 IALU : R; | |
4541 %} | |
4542 | |
4543 // Integer ALU zero-reg operation with condition code only | |
4544 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
4545 single_instruction; | |
4546 cr : E(write); | |
4547 src : R(read); | |
4548 IALU : R; | |
4549 %} | |
4550 | |
4551 // Integer ALU reg-reg operation with condition code only | |
4552 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4553 single_instruction; | |
4554 cr : E(write); | |
4555 src1 : R(read); | |
4556 src2 : R(read); | |
4557 IALU : R; | |
4558 %} | |
4559 | |
4560 // Integer ALU reg-imm operation with condition code only | |
4561 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4562 single_instruction; | |
4563 cr : E(write); | |
4564 src1 : R(read); | |
4565 IALU : R; | |
4566 %} | |
4567 | |
4568 // Integer ALU reg-reg-zero operation with condition code only | |
4569 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
4570 single_instruction; | |
4571 cr : E(write); | |
4572 src1 : R(read); | |
4573 src2 : R(read); | |
4574 IALU : R; | |
4575 %} | |
4576 | |
4577 // Integer ALU reg-imm-zero operation with condition code only | |
4578 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
4579 single_instruction; | |
4580 cr : E(write); | |
4581 src1 : R(read); | |
4582 IALU : R; | |
4583 %} | |
4584 | |
4585 // Integer ALU reg-reg operation with condition code, src1 modified | |
4586 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4587 single_instruction; | |
4588 cr : E(write); | |
4589 src1 : E(write); | |
4590 src1 : R(read); | |
4591 src2 : R(read); | |
4592 IALU : R; | |
4593 %} | |
4594 | |
4595 // Integer ALU reg-imm operation with condition code, src1 modified | |
4596 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4597 single_instruction; | |
4598 cr : E(write); | |
4599 src1 : E(write); | |
4600 src1 : R(read); | |
4601 IALU : R; | |
4602 %} | |
4603 | |
4604 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
4605 multiple_bundles; | |
4606 dst : E(write)+4; | |
4607 cr : E(write); | |
4608 src1 : R(read); | |
4609 src2 : R(read); | |
4610 IALU : R(3); | |
4611 BR : R(2); | |
4612 %} | |
4613 | |
4614 // Integer ALU operation | |
4615 pipe_class ialu_none(iRegI dst) %{ | |
4616 single_instruction; | |
4617 dst : E(write); | |
4618 IALU : R; | |
4619 %} | |
4620 | |
4621 // Integer ALU reg operation | |
4622 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
4623 single_instruction; may_have_no_code; | |
4624 dst : E(write); | |
4625 src : R(read); | |
4626 IALU : R; | |
4627 %} | |
4628 | |
4629 // Integer ALU reg conditional operation | |
4630 // This instruction has a 1 cycle stall, and cannot execute | |
4631 // in the same cycle as the instruction setting the condition | |
4632 // code. We kludge this by pretending to read the condition code | |
4633 // 1 cycle earlier, and by marking the functional units as busy | |
4634 // for 2 cycles with the result available 1 cycle later than | |
4635 // is really the case. | |
4636 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
4637 single_instruction; | |
4638 op2_out : C(write); | |
4639 op1 : R(read); | |
4640 cr : R(read); // This is really E, with a 1 cycle stall | |
4641 BR : R(2); | |
4642 MS : R(2); | |
4643 %} | |
4644 | |
4645 #ifdef _LP64 | |
4646 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
4647 instruction_count(1); multiple_bundles; | |
4648 dst : C(write)+1; | |
4649 src : R(read)+1; | |
4650 IALU : R(1); | |
4651 BR : E(2); | |
4652 MS : E(2); | |
4653 %} | |
4654 #endif | |
4655 | |
4656 // Integer ALU reg operation | |
4657 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
4658 single_instruction; may_have_no_code; | |
4659 dst : E(write); | |
4660 src : R(read); | |
4661 IALU : R; | |
4662 %} | |
4663 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
4664 single_instruction; may_have_no_code; | |
4665 dst : E(write); | |
4666 src : R(read); | |
4667 IALU : R; | |
4668 %} | |
4669 | |
4670 // Two integer ALU reg operations | |
4671 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
4672 instruction_count(2); | |
4673 dst : E(write); | |
4674 src : R(read); | |
4675 A0 : R; | |
4676 A1 : R; | |
4677 %} | |
4678 | |
4679 // Two integer ALU reg operations | |
4680 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
4681 instruction_count(2); may_have_no_code; | |
4682 dst : E(write); | |
4683 src : R(read); | |
4684 A0 : R; | |
4685 A1 : R; | |
4686 %} | |
4687 | |
4688 // Integer ALU imm operation | |
4689 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
4690 single_instruction; | |
4691 dst : E(write); | |
4692 IALU : R; | |
4693 %} | |
4694 | |
4695 // Integer ALU reg-reg with carry operation | |
4696 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
4697 single_instruction; | |
4698 dst : E(write); | |
4699 src1 : R(read); | |
4700 src2 : R(read); | |
4701 IALU : R; | |
4702 %} | |
4703 | |
4704 // Integer ALU cc operation | |
4705 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
4706 single_instruction; | |
4707 dst : E(write); | |
4708 cc : R(read); | |
4709 IALU : R; | |
4710 %} | |
4711 | |
4712 // Integer ALU cc / second IALU operation | |
4713 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
4714 instruction_count(1); multiple_bundles; | |
4715 dst : E(write)+1; | |
4716 src : R(read); | |
4717 IALU : R; | |
4718 %} | |
4719 | |
4720 // Integer ALU cc / second IALU operation | |
4721 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
4722 instruction_count(1); multiple_bundles; | |
4723 dst : E(write)+1; | |
4724 p : R(read); | |
4725 q : R(read); | |
4726 IALU : R; | |
4727 %} | |
4728 | |
4729 // Integer ALU hi-lo-reg operation | |
4730 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
4731 instruction_count(1); multiple_bundles; | |
4732 dst : E(write)+1; | |
4733 IALU : R(2); | |
4734 %} | |
4735 | |
4736 // Float ALU hi-lo-reg operation (with temp) | |
4737 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
4738 instruction_count(1); multiple_bundles; | |
4739 dst : E(write)+1; | |
4740 IALU : R(2); | |
4741 %} | |
4742 | |
4743 // Long Constant | |
4744 pipe_class loadConL( iRegL dst, immL src ) %{ | |
4745 instruction_count(2); multiple_bundles; | |
4746 dst : E(write)+1; | |
4747 IALU : R(2); | |
4748 IALU : R(2); | |
4749 %} | |
4750 | |
4751 // Pointer Constant | |
4752 pipe_class loadConP( iRegP dst, immP src ) %{ | |
4753 instruction_count(0); multiple_bundles; | |
4754 fixed_latency(6); | |
4755 %} | |
4756 | |
4757 // Polling Address | |
4758 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
4759 #ifdef _LP64 | |
4760 instruction_count(0); multiple_bundles; | |
4761 fixed_latency(6); | |
4762 #else | |
4763 dst : E(write); | |
4764 IALU : R; | |
4765 #endif | |
4766 %} | |
4767 | |
4768 // Long Constant small | |
4769 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
4770 instruction_count(2); | |
4771 dst : E(write); | |
4772 IALU : R; | |
4773 IALU : R; | |
4774 %} | |
4775 | |
4776 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
4777 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
4778 instruction_count(1); multiple_bundles; | |
4779 src : R(read); | |
4780 dst : M(write)+1; | |
4781 IALU : R; | |
4782 MS : E; | |
4783 %} | |
4784 | |
4785 // Integer ALU nop operation | |
4786 pipe_class ialu_nop() %{ | |
4787 single_instruction; | |
4788 IALU : R; | |
4789 %} | |
4790 | |
4791 // Integer ALU nop operation | |
4792 pipe_class ialu_nop_A0() %{ | |
4793 single_instruction; | |
4794 A0 : R; | |
4795 %} | |
4796 | |
4797 // Integer ALU nop operation | |
4798 pipe_class ialu_nop_A1() %{ | |
4799 single_instruction; | |
4800 A1 : R; | |
4801 %} | |
4802 | |
4803 // Integer Multiply reg-reg operation | |
4804 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4805 single_instruction; | |
4806 dst : E(write); | |
4807 src1 : R(read); | |
4808 src2 : R(read); | |
4809 MS : R(5); | |
4810 %} | |
4811 | |
4812 // Integer Multiply reg-imm operation | |
4813 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4814 single_instruction; | |
4815 dst : E(write); | |
4816 src1 : R(read); | |
4817 MS : R(5); | |
4818 %} | |
4819 | |
4820 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4821 single_instruction; | |
4822 dst : E(write)+4; | |
4823 src1 : R(read); | |
4824 src2 : R(read); | |
4825 MS : R(6); | |
4826 %} | |
4827 | |
4828 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4829 single_instruction; | |
4830 dst : E(write)+4; | |
4831 src1 : R(read); | |
4832 MS : R(6); | |
4833 %} | |
4834 | |
4835 // Integer Divide reg-reg | |
4836 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
4837 instruction_count(1); multiple_bundles; | |
4838 dst : E(write); | |
4839 temp : E(write); | |
4840 src1 : R(read); | |
4841 src2 : R(read); | |
4842 temp : R(read); | |
4843 MS : R(38); | |
4844 %} | |
4845 | |
4846 // Integer Divide reg-imm | |
4847 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
4848 instruction_count(1); multiple_bundles; | |
4849 dst : E(write); | |
4850 temp : E(write); | |
4851 src1 : R(read); | |
4852 temp : R(read); | |
4853 MS : R(38); | |
4854 %} | |
4855 | |
4856 // Long Divide | |
4857 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4858 dst : E(write)+71; | |
4859 src1 : R(read); | |
4860 src2 : R(read)+1; | |
4861 MS : R(70); | |
4862 %} | |
4863 | |
4864 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4865 dst : E(write)+71; | |
4866 src1 : R(read); | |
4867 MS : R(70); | |
4868 %} | |
4869 | |
4870 // Floating Point Add Float | |
4871 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4872 single_instruction; | |
4873 dst : X(write); | |
4874 src1 : E(read); | |
4875 src2 : E(read); | |
4876 FA : R; | |
4877 %} | |
4878 | |
4879 // Floating Point Add Double | |
4880 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4881 single_instruction; | |
4882 dst : X(write); | |
4883 src1 : E(read); | |
4884 src2 : E(read); | |
4885 FA : R; | |
4886 %} | |
4887 | |
4888 // Floating Point Conditional Move based on integer flags | |
4889 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
4890 single_instruction; | |
4891 dst : X(write); | |
4892 src : E(read); | |
4893 cr : R(read); | |
4894 FA : R(2); | |
4895 BR : R(2); | |
4896 %} | |
4897 | |
4898 // Floating Point Conditional Move based on integer flags | |
4899 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
4900 single_instruction; | |
4901 dst : X(write); | |
4902 src : E(read); | |
4903 cr : R(read); | |
4904 FA : R(2); | |
4905 BR : R(2); | |
4906 %} | |
4907 | |
4908 // Floating Point Multiply Float | |
4909 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4910 single_instruction; | |
4911 dst : X(write); | |
4912 src1 : E(read); | |
4913 src2 : E(read); | |
4914 FM : R; | |
4915 %} | |
4916 | |
4917 // Floating Point Multiply Double | |
4918 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4919 single_instruction; | |
4920 dst : X(write); | |
4921 src1 : E(read); | |
4922 src2 : E(read); | |
4923 FM : R; | |
4924 %} | |
4925 | |
4926 // Floating Point Divide Float | |
4927 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4928 single_instruction; | |
4929 dst : X(write); | |
4930 src1 : E(read); | |
4931 src2 : E(read); | |
4932 FM : R; | |
4933 FDIV : C(14); | |
4934 %} | |
4935 | |
4936 // Floating Point Divide Double | |
4937 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4938 single_instruction; | |
4939 dst : X(write); | |
4940 src1 : E(read); | |
4941 src2 : E(read); | |
4942 FM : R; | |
4943 FDIV : C(17); | |
4944 %} | |
4945 | |
4946 // Floating Point Move/Negate/Abs Float | |
4947 pipe_class faddF_reg(regF dst, regF src) %{ | |
4948 single_instruction; | |
4949 dst : W(write); | |
4950 src : E(read); | |
4951 FA : R(1); | |
4952 %} | |
4953 | |
4954 // Floating Point Move/Negate/Abs Double | |
4955 pipe_class faddD_reg(regD dst, regD src) %{ | |
4956 single_instruction; | |
4957 dst : W(write); | |
4958 src : E(read); | |
4959 FA : R; | |
4960 %} | |
4961 | |
4962 // Floating Point Convert F->D | |
4963 pipe_class fcvtF2D(regD dst, regF src) %{ | |
4964 single_instruction; | |
4965 dst : X(write); | |
4966 src : E(read); | |
4967 FA : R; | |
4968 %} | |
4969 | |
4970 // Floating Point Convert I->D | |
4971 pipe_class fcvtI2D(regD dst, regF src) %{ | |
4972 single_instruction; | |
4973 dst : X(write); | |
4974 src : E(read); | |
4975 FA : R; | |
4976 %} | |
4977 | |
4978 // Floating Point Convert LHi->D | |
4979 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
4980 single_instruction; | |
4981 dst : X(write); | |
4982 src : E(read); | |
4983 FA : R; | |
4984 %} | |
4985 | |
4986 // Floating Point Convert L->D | |
4987 pipe_class fcvtL2D(regD dst, regF src) %{ | |
4988 single_instruction; | |
4989 dst : X(write); | |
4990 src : E(read); | |
4991 FA : R; | |
4992 %} | |
4993 | |
4994 // Floating Point Convert L->F | |
4995 pipe_class fcvtL2F(regD dst, regF src) %{ | |
4996 single_instruction; | |
4997 dst : X(write); | |
4998 src : E(read); | |
4999 FA : R; | |
5000 %} | |
5001 | |
5002 // Floating Point Convert D->F | |
5003 pipe_class fcvtD2F(regD dst, regF src) %{ | |
5004 single_instruction; | |
5005 dst : X(write); | |
5006 src : E(read); | |
5007 FA : R; | |
5008 %} | |
5009 | |
5010 // Floating Point Convert I->L | |
5011 pipe_class fcvtI2L(regD dst, regF src) %{ | |
5012 single_instruction; | |
5013 dst : X(write); | |
5014 src : E(read); | |
5015 FA : R; | |
5016 %} | |
5017 | |
5018 // Floating Point Convert D->F | |
5019 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
5020 instruction_count(1); multiple_bundles; | |
5021 dst : X(write)+6; | |
5022 src : E(read); | |
5023 FA : R; | |
5024 %} | |
5025 | |
5026 // Floating Point Convert D->L | |
5027 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
5028 instruction_count(1); multiple_bundles; | |
5029 dst : X(write)+6; | |
5030 src : E(read); | |
5031 FA : R; | |
5032 %} | |
5033 | |
5034 // Floating Point Convert F->I | |
5035 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
5036 instruction_count(1); multiple_bundles; | |
5037 dst : X(write)+6; | |
5038 src : E(read); | |
5039 FA : R; | |
5040 %} | |
5041 | |
5042 // Floating Point Convert F->L | |
5043 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
5044 instruction_count(1); multiple_bundles; | |
5045 dst : X(write)+6; | |
5046 src : E(read); | |
5047 FA : R; | |
5048 %} | |
5049 | |
5050 // Floating Point Convert I->F | |
5051 pipe_class fcvtI2F(regF dst, regF src) %{ | |
5052 single_instruction; | |
5053 dst : X(write); | |
5054 src : E(read); | |
5055 FA : R; | |
5056 %} | |
5057 | |
5058 // Floating Point Compare | |
5059 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
5060 single_instruction; | |
5061 cr : X(write); | |
5062 src1 : E(read); | |
5063 src2 : E(read); | |
5064 FA : R; | |
5065 %} | |
5066 | |
5067 // Floating Point Compare | |
5068 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
5069 single_instruction; | |
5070 cr : X(write); | |
5071 src1 : E(read); | |
5072 src2 : E(read); | |
5073 FA : R; | |
5074 %} | |
5075 | |
5076 // Floating Add Nop | |
5077 pipe_class fadd_nop() %{ | |
5078 single_instruction; | |
5079 FA : R; | |
5080 %} | |
5081 | |
5082 // Integer Store to Memory | |
5083 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
5084 single_instruction; | |
5085 mem : R(read); | |
5086 src : C(read); | |
5087 MS : R; | |
5088 %} | |
5089 | |
5090 // Integer Store to Memory | |
5091 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
5092 single_instruction; | |
5093 mem : R(read); | |
5094 src : C(read); | |
5095 MS : R; | |
5096 %} | |
5097 | |
5098 // Integer Store Zero to Memory | |
5099 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
5100 single_instruction; | |
5101 mem : R(read); | |
5102 MS : R; | |
5103 %} | |
5104 | |
5105 // Special Stack Slot Store | |
5106 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
5107 single_instruction; | |
5108 stkSlot : R(read); | |
5109 src : C(read); | |
5110 MS : R; | |
5111 %} | |
5112 | |
5113 // Special Stack Slot Store | |
5114 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
5115 instruction_count(2); multiple_bundles; | |
5116 stkSlot : R(read); | |
5117 src : C(read); | |
5118 MS : R(2); | |
5119 %} | |
5120 | |
5121 // Float Store | |
5122 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
5123 single_instruction; | |
5124 mem : R(read); | |
5125 src : C(read); | |
5126 MS : R; | |
5127 %} | |
5128 | |
5129 // Float Store | |
5130 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
5131 single_instruction; | |
5132 mem : R(read); | |
5133 MS : R; | |
5134 %} | |
5135 | |
5136 // Double Store | |
5137 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
5138 instruction_count(1); | |
5139 mem : R(read); | |
5140 src : C(read); | |
5141 MS : R; | |
5142 %} | |
5143 | |
5144 // Double Store | |
5145 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
5146 single_instruction; | |
5147 mem : R(read); | |
5148 MS : R; | |
5149 %} | |
5150 | |
5151 // Special Stack Slot Float Store | |
5152 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
5153 single_instruction; | |
5154 stkSlot : R(read); | |
5155 src : C(read); | |
5156 MS : R; | |
5157 %} | |
5158 | |
5159 // Special Stack Slot Double Store | |
5160 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
5161 single_instruction; | |
5162 stkSlot : R(read); | |
5163 src : C(read); | |
5164 MS : R; | |
5165 %} | |
5166 | |
5167 // Integer Load (when sign bit propagation not needed) | |
5168 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
5169 single_instruction; | |
5170 mem : R(read); | |
5171 dst : C(write); | |
5172 MS : R; | |
5173 %} | |
5174 | |
5175 // Integer Load from stack operand | |
5176 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
5177 single_instruction; | |
5178 mem : R(read); | |
5179 dst : C(write); | |
5180 MS : R; | |
5181 %} | |
5182 | |
5183 // Integer Load (when sign bit propagation or masking is needed) | |
5184 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
5185 single_instruction; | |
5186 mem : R(read); | |
5187 dst : M(write); | |
5188 MS : R; | |
5189 %} | |
5190 | |
5191 // Float Load | |
5192 pipe_class floadF_mem(regF dst, memory mem) %{ | |
5193 single_instruction; | |
5194 mem : R(read); | |
5195 dst : M(write); | |
5196 MS : R; | |
5197 %} | |
5198 | |
5199 // Float Load | |
5200 pipe_class floadD_mem(regD dst, memory mem) %{ | |
5201 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
5202 mem : R(read); | |
5203 dst : M(write); | |
5204 MS : R; | |
5205 %} | |
5206 | |
5207 // Float Load | |
5208 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
5209 single_instruction; | |
5210 stkSlot : R(read); | |
5211 dst : M(write); | |
5212 MS : R; | |
5213 %} | |
5214 | |
5215 // Float Load | |
5216 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
5217 single_instruction; | |
5218 stkSlot : R(read); | |
5219 dst : M(write); | |
5220 MS : R; | |
5221 %} | |
5222 | |
5223 // Memory Nop | |
5224 pipe_class mem_nop() %{ | |
5225 single_instruction; | |
5226 MS : R; | |
5227 %} | |
5228 | |
5229 pipe_class sethi(iRegP dst, immI src) %{ | |
5230 single_instruction; | |
5231 dst : E(write); | |
5232 IALU : R; | |
5233 %} | |
5234 | |
5235 pipe_class loadPollP(iRegP poll) %{ | |
5236 single_instruction; | |
5237 poll : R(read); | |
5238 MS : R; | |
5239 %} | |
5240 | |
5241 pipe_class br(Universe br, label labl) %{ | |
5242 single_instruction_with_delay_slot; | |
5243 BR : R; | |
5244 %} | |
5245 | |
5246 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
5247 single_instruction_with_delay_slot; | |
5248 cr : E(read); | |
5249 BR : R; | |
5250 %} | |
5251 | |
5252 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
5253 single_instruction_with_delay_slot; | |
5254 op1 : E(read); | |
5255 BR : R; | |
5256 MS : R; | |
5257 %} | |
5258 | |
3851 | 5259 // Compare and branch |
5260 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ | |
5261 instruction_count(2); has_delay_slot; | |
5262 cr : E(write); | |
5263 src1 : R(read); | |
5264 src2 : R(read); | |
5265 IALU : R; | |
5266 BR : R; | |
5267 %} | |
5268 | |
5269 // Compare and branch | |
5270 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ | |
5271 instruction_count(2); has_delay_slot; | |
5272 cr : E(write); | |
5273 src1 : R(read); | |
5274 IALU : R; | |
5275 BR : R; | |
5276 %} | |
5277 | |
5278 // Compare and branch using cbcond | |
5279 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ | |
5280 single_instruction; | |
5281 src1 : E(read); | |
5282 src2 : E(read); | |
5283 IALU : R; | |
5284 BR : R; | |
5285 %} | |
5286 | |
5287 // Compare and branch using cbcond | |
5288 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ | |
5289 single_instruction; | |
5290 src1 : E(read); | |
5291 IALU : R; | |
5292 BR : R; | |
5293 %} | |
5294 | |
0 | 5295 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ |
5296 single_instruction_with_delay_slot; | |
5297 cr : E(read); | |
5298 BR : R; | |
5299 %} | |
5300 | |
5301 pipe_class br_nop() %{ | |
5302 single_instruction; | |
5303 BR : R; | |
5304 %} | |
5305 | |
5306 pipe_class simple_call(method meth) %{ | |
5307 instruction_count(2); multiple_bundles; force_serialization; | |
5308 fixed_latency(100); | |
5309 BR : R(1); | |
5310 MS : R(1); | |
5311 A0 : R(1); | |
5312 %} | |
5313 | |
5314 pipe_class compiled_call(method meth) %{ | |
5315 instruction_count(1); multiple_bundles; force_serialization; | |
5316 fixed_latency(100); | |
5317 MS : R(1); | |
5318 %} | |
5319 | |
5320 pipe_class call(method meth) %{ | |
5321 instruction_count(0); multiple_bundles; force_serialization; | |
5322 fixed_latency(100); | |
5323 %} | |
5324 | |
5325 pipe_class tail_call(Universe ignore, label labl) %{ | |
5326 single_instruction; has_delay_slot; | |
5327 fixed_latency(100); | |
5328 BR : R(1); | |
5329 MS : R(1); | |
5330 %} | |
5331 | |
5332 pipe_class ret(Universe ignore) %{ | |
5333 single_instruction; has_delay_slot; | |
5334 BR : R(1); | |
5335 MS : R(1); | |
5336 %} | |
5337 | |
5338 pipe_class ret_poll(g3RegP poll) %{ | |
5339 instruction_count(3); has_delay_slot; | |
5340 poll : E(read); | |
5341 MS : R; | |
5342 %} | |
5343 | |
5344 // The real do-nothing guy | |
5345 pipe_class empty( ) %{ | |
5346 instruction_count(0); | |
5347 %} | |
5348 | |
5349 pipe_class long_memory_op() %{ | |
5350 instruction_count(0); multiple_bundles; force_serialization; | |
5351 fixed_latency(25); | |
5352 MS : R(1); | |
5353 %} | |
5354 | |
5355 // Check-cast | |
5356 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
5357 array : R(read); | |
5358 match : R(read); | |
5359 IALU : R(2); | |
5360 BR : R(2); | |
5361 MS : R; | |
5362 %} | |
5363 | |
5364 // Convert FPU flags into +1,0,-1 | |
5365 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
5366 src1 : E(read); | |
5367 src2 : E(read); | |
5368 dst : E(write); | |
5369 FA : R; | |
5370 MS : R(2); | |
5371 BR : R(2); | |
5372 %} | |
5373 | |
5374 // Compare for p < q, and conditionally add y | |
5375 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
5376 p : E(read); | |
5377 q : E(read); | |
5378 y : E(read); | |
5379 IALU : R(3) | |
5380 %} | |
5381 | |
5382 // Perform a compare, then move conditionally in a branch delay slot. | |
5383 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
5384 src2 : E(read); | |
5385 srcdst : E(read); | |
5386 IALU : R; | |
5387 BR : R; | |
5388 %} | |
5389 | |
5390 // Define the class for the Nop node | |
5391 define %{ | |
5392 MachNop = ialu_nop; | |
5393 %} | |
5394 | |
5395 %} | |
5396 | |
5397 //----------INSTRUCTIONS------------------------------------------------------- | |
5398 | |
5399 //------------Special Stack Slot instructions - no match rules----------------- | |
5400 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
5401 // No match rule to avoid chain rule match. | |
5402 effect(DEF dst, USE src); | |
5403 ins_cost(MEMORY_REF_COST); | |
5404 size(4); | |
5405 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
5406 opcode(Assembler::ldf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5407 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5408 ins_pipe(floadF_stk); |
5409 %} | |
5410 | |
5411 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
5412 // No match rule to avoid chain rule match. | |
5413 effect(DEF dst, USE src); | |
5414 ins_cost(MEMORY_REF_COST); | |
5415 size(4); | |
5416 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
5417 opcode(Assembler::lddf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5418 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5419 ins_pipe(floadD_stk); |
5420 %} | |
5421 | |
5422 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
5423 // No match rule to avoid chain rule match. | |
5424 effect(DEF dst, USE src); | |
5425 ins_cost(MEMORY_REF_COST); | |
5426 size(4); | |
5427 format %{ "STF $src,$dst\t! regF to stkI" %} | |
5428 opcode(Assembler::stf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5429 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5430 ins_pipe(fstoreF_stk_reg); |
5431 %} | |
5432 | |
5433 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
5434 // No match rule to avoid chain rule match. | |
5435 effect(DEF dst, USE src); | |
5436 ins_cost(MEMORY_REF_COST); | |
5437 size(4); | |
5438 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
5439 opcode(Assembler::stdf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5440 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5441 ins_pipe(fstoreD_stk_reg); |
5442 %} | |
5443 | |
5444 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
5445 effect(DEF dst, USE src); | |
5446 ins_cost(MEMORY_REF_COST*2); | |
5447 size(8); | |
5448 format %{ "STW $src,$dst.hi\t! long\n\t" | |
5449 "STW R_G0,$dst.lo" %} | |
5450 opcode(Assembler::stw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5451 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
0 | 5452 ins_pipe(lstoreI_stk_reg); |
5453 %} | |
5454 | |
5455 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
5456 // No match rule to avoid chain rule match. | |
5457 effect(DEF dst, USE src); | |
5458 ins_cost(MEMORY_REF_COST); | |
5459 size(4); | |
5460 format %{ "STX $src,$dst\t! regL to stkD" %} | |
5461 opcode(Assembler::stx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5462 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5463 ins_pipe(istore_stk_reg); |
5464 %} | |
5465 | |
5466 //---------- Chain stack slots between similar types -------- | |
5467 | |
5468 // Load integer from stack slot | |
5469 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
5470 match(Set dst src); | |
5471 ins_cost(MEMORY_REF_COST); | |
5472 | |
5473 size(4); | |
5474 format %{ "LDUW $src,$dst\t!stk" %} | |
5475 opcode(Assembler::lduw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5476 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5477 ins_pipe(iload_mem); |
5478 %} | |
5479 | |
5480 // Store integer to stack slot | |
5481 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
5482 match(Set dst src); | |
5483 ins_cost(MEMORY_REF_COST); | |
5484 | |
5485 size(4); | |
5486 format %{ "STW $src,$dst\t!stk" %} | |
5487 opcode(Assembler::stw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5488 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5489 ins_pipe(istore_mem_reg); |
5490 %} | |
5491 | |
5492 // Load long from stack slot | |
5493 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
5494 match(Set dst src); | |
5495 | |
5496 ins_cost(MEMORY_REF_COST); | |
5497 size(4); | |
5498 format %{ "LDX $src,$dst\t! long" %} | |
5499 opcode(Assembler::ldx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5500 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5501 ins_pipe(iload_mem); |
5502 %} | |
5503 | |
5504 // Store long to stack slot | |
5505 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
5506 match(Set dst src); | |
5507 | |
5508 ins_cost(MEMORY_REF_COST); | |
5509 size(4); | |
5510 format %{ "STX $src,$dst\t! long" %} | |
5511 opcode(Assembler::stx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5512 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5513 ins_pipe(istore_mem_reg); |
5514 %} | |
5515 | |
5516 #ifdef _LP64 | |
5517 // Load pointer from stack slot, 64-bit encoding | |
5518 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5519 match(Set dst src); | |
5520 ins_cost(MEMORY_REF_COST); | |
5521 size(4); | |
5522 format %{ "LDX $src,$dst\t!ptr" %} | |
5523 opcode(Assembler::ldx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5524 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5525 ins_pipe(iload_mem); |
5526 %} | |
5527 | |
5528 // Store pointer to stack slot | |
5529 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5530 match(Set dst src); | |
5531 ins_cost(MEMORY_REF_COST); | |
5532 size(4); | |
5533 format %{ "STX $src,$dst\t!ptr" %} | |
5534 opcode(Assembler::stx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5535 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5536 ins_pipe(istore_mem_reg); |
5537 %} | |
5538 #else // _LP64 | |
5539 // Load pointer from stack slot, 32-bit encoding | |
5540 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5541 match(Set dst src); | |
5542 ins_cost(MEMORY_REF_COST); | |
5543 format %{ "LDUW $src,$dst\t!ptr" %} | |
5544 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5545 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5546 ins_pipe(iload_mem); |
5547 %} | |
5548 | |
5549 // Store pointer to stack slot | |
5550 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5551 match(Set dst src); | |
5552 ins_cost(MEMORY_REF_COST); | |
5553 format %{ "STW $src,$dst\t!ptr" %} | |
5554 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5555 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5556 ins_pipe(istore_mem_reg); |
5557 %} | |
5558 #endif // _LP64 | |
5559 | |
5560 //------------Special Nop instructions for bundling - no match rules----------- | |
5561 // Nop using the A0 functional unit | |
5562 instruct Nop_A0() %{ | |
5563 ins_cost(0); | |
5564 | |
5565 format %{ "NOP ! Alu Pipeline" %} | |
5566 opcode(Assembler::or_op3, Assembler::arith_op); | |
5567 ins_encode( form2_nop() ); | |
5568 ins_pipe(ialu_nop_A0); | |
5569 %} | |
5570 | |
5571 // Nop using the A1 functional unit | |
5572 instruct Nop_A1( ) %{ | |
5573 ins_cost(0); | |
5574 | |
5575 format %{ "NOP ! Alu Pipeline" %} | |
5576 opcode(Assembler::or_op3, Assembler::arith_op); | |
5577 ins_encode( form2_nop() ); | |
5578 ins_pipe(ialu_nop_A1); | |
5579 %} | |
5580 | |
5581 // Nop using the memory functional unit | |
5582 instruct Nop_MS( ) %{ | |
5583 ins_cost(0); | |
5584 | |
5585 format %{ "NOP ! Memory Pipeline" %} | |
5586 ins_encode( emit_mem_nop ); | |
5587 ins_pipe(mem_nop); | |
5588 %} | |
5589 | |
5590 // Nop using the floating add functional unit | |
5591 instruct Nop_FA( ) %{ | |
5592 ins_cost(0); | |
5593 | |
5594 format %{ "NOP ! Floating Add Pipeline" %} | |
5595 ins_encode( emit_fadd_nop ); | |
5596 ins_pipe(fadd_nop); | |
5597 %} | |
5598 | |
5599 // Nop using the branch functional unit | |
5600 instruct Nop_BR( ) %{ | |
5601 ins_cost(0); | |
5602 | |
5603 format %{ "NOP ! Branch Pipeline" %} | |
5604 ins_encode( emit_br_nop ); | |
5605 ins_pipe(br_nop); | |
5606 %} | |
5607 | |
5608 //----------Load/Store/Move Instructions--------------------------------------- | |
5609 //----------Load Instructions-------------------------------------------------- | |
5610 // Load Byte (8bit signed) | |
5611 instruct loadB(iRegI dst, memory mem) %{ | |
5612 match(Set dst (LoadB mem)); | |
5613 ins_cost(MEMORY_REF_COST); | |
5614 | |
5615 size(4); | |
624 | 5616 format %{ "LDSB $mem,$dst\t! byte" %} |
727 | 5617 ins_encode %{ |
5618 __ ldsb($mem$$Address, $dst$$Register); | |
5619 %} | |
624 | 5620 ins_pipe(iload_mask_mem); |
5621 %} | |
5622 | |
5623 // Load Byte (8bit signed) into a Long Register | |
5624 instruct loadB2L(iRegL dst, memory mem) %{ | |
5625 match(Set dst (ConvI2L (LoadB mem))); | |
5626 ins_cost(MEMORY_REF_COST); | |
5627 | |
5628 size(4); | |
5629 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
727 | 5630 ins_encode %{ |
5631 __ ldsb($mem$$Address, $dst$$Register); | |
5632 %} | |
0 | 5633 ins_pipe(iload_mask_mem); |
5634 %} | |
5635 | |
624 | 5636 // Load Unsigned Byte (8bit UNsigned) into an int reg |
5637 instruct loadUB(iRegI dst, memory mem) %{ | |
5638 match(Set dst (LoadUB mem)); | |
0 | 5639 ins_cost(MEMORY_REF_COST); |
5640 | |
5641 size(4); | |
624 | 5642 format %{ "LDUB $mem,$dst\t! ubyte" %} |
727 | 5643 ins_encode %{ |
5644 __ ldub($mem$$Address, $dst$$Register); | |
5645 %} | |
824 | 5646 ins_pipe(iload_mem); |
624 | 5647 %} |
5648 | |
5649 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
5650 instruct loadUB2L(iRegL dst, memory mem) %{ | |
5651 match(Set dst (ConvI2L (LoadUB mem))); | |
5652 ins_cost(MEMORY_REF_COST); | |
5653 | |
5654 size(4); | |
5655 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
727 | 5656 ins_encode %{ |
5657 __ ldub($mem$$Address, $dst$$Register); | |
5658 %} | |
824 | 5659 ins_pipe(iload_mem); |
5660 %} | |
5661 | |
5662 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register | |
5663 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ | |
5664 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
5665 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5666 | |
5667 size(2*4); | |
5668 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" | |
5669 "AND $dst,$mask,$dst" %} | |
5670 ins_encode %{ | |
5671 __ ldub($mem$$Address, $dst$$Register); | |
5672 __ and3($dst$$Register, $mask$$constant, $dst$$Register); | |
5673 %} | |
5674 ins_pipe(iload_mem); | |
0 | 5675 %} |
5676 | |
624 | 5677 // Load Short (16bit signed) |
5678 instruct loadS(iRegI dst, memory mem) %{ | |
5679 match(Set dst (LoadS mem)); | |
5680 ins_cost(MEMORY_REF_COST); | |
5681 | |
5682 size(4); | |
5683 format %{ "LDSH $mem,$dst\t! short" %} | |
727 | 5684 ins_encode %{ |
5685 __ ldsh($mem$$Address, $dst$$Register); | |
5686 %} | |
624 | 5687 ins_pipe(iload_mask_mem); |
5688 %} | |
5689 | |
785 | 5690 // Load Short (16 bit signed) to Byte (8 bit signed) |
5691 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5692 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
5693 ins_cost(MEMORY_REF_COST); | |
5694 | |
5695 size(4); | |
5696 | |
5697 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} | |
5698 ins_encode %{ | |
5699 __ ldsb($mem$$Address, $dst$$Register, 1); | |
5700 %} | |
5701 ins_pipe(iload_mask_mem); | |
5702 %} | |
5703 | |
624 | 5704 // Load Short (16bit signed) into a Long Register |
5705 instruct loadS2L(iRegL dst, memory mem) %{ | |
5706 match(Set dst (ConvI2L (LoadS mem))); | |
0 | 5707 ins_cost(MEMORY_REF_COST); |
5708 | |
5709 size(4); | |
624 | 5710 format %{ "LDSH $mem,$dst\t! short -> long" %} |
727 | 5711 ins_encode %{ |
5712 __ ldsh($mem$$Address, $dst$$Register); | |
5713 %} | |
624 | 5714 ins_pipe(iload_mask_mem); |
5715 %} | |
5716 | |
5717 // Load Unsigned Short/Char (16bit UNsigned) | |
5718 instruct loadUS(iRegI dst, memory mem) %{ | |
5719 match(Set dst (LoadUS mem)); | |
5720 ins_cost(MEMORY_REF_COST); | |
5721 | |
5722 size(4); | |
5723 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
727 | 5724 ins_encode %{ |
5725 __ lduh($mem$$Address, $dst$$Register); | |
5726 %} | |
824 | 5727 ins_pipe(iload_mem); |
0 | 5728 %} |
5729 | |
785 | 5730 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
5731 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5732 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
5733 ins_cost(MEMORY_REF_COST); | |
5734 | |
5735 size(4); | |
5736 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} | |
5737 ins_encode %{ | |
5738 __ ldsb($mem$$Address, $dst$$Register, 1); | |
5739 %} | |
5740 ins_pipe(iload_mask_mem); | |
5741 %} | |
5742 | |
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
551
diff
changeset
|
5743 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
624 | 5744 instruct loadUS2L(iRegL dst, memory mem) %{ |
5745 match(Set dst (ConvI2L (LoadUS mem))); | |
0 | 5746 ins_cost(MEMORY_REF_COST); |
5747 | |
5748 size(4); | |
624 | 5749 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
727 | 5750 ins_encode %{ |
5751 __ lduh($mem$$Address, $dst$$Register); | |
5752 %} | |
824 | 5753 ins_pipe(iload_mem); |
5754 %} | |
5755 | |
5756 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register | |
5757 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
5758 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5759 ins_cost(MEMORY_REF_COST); | |
5760 | |
5761 size(4); | |
5762 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} | |
5763 ins_encode %{ | |
5764 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE | |
5765 %} | |
5766 ins_pipe(iload_mem); | |
5767 %} | |
5768 | |
5769 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register | |
5770 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
5771 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5772 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5773 | |
5774 size(2*4); | |
5775 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" | |
5776 "AND $dst,$mask,$dst" %} | |
5777 ins_encode %{ | |
5778 Register Rdst = $dst$$Register; | |
5779 __ lduh($mem$$Address, Rdst); | |
5780 __ and3(Rdst, $mask$$constant, Rdst); | |
5781 %} | |
5782 ins_pipe(iload_mem); | |
5783 %} | |
5784 | |
5785 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register | |
5786 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | |
5787 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5788 effect(TEMP dst, TEMP tmp); | |
5789 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
5790 | |
5791 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" | |
5792 "SET $mask,$tmp\n\t" | |
5793 "AND $dst,$tmp,$dst" %} | |
5794 ins_encode %{ | |
5795 Register Rdst = $dst$$Register; | |
5796 Register Rtmp = $tmp$$Register; | |
5797 __ lduh($mem$$Address, Rdst); | |
5798 __ set($mask$$constant, Rtmp); | |
5799 __ and3(Rdst, Rtmp, Rdst); | |
5800 %} | |
5801 ins_pipe(iload_mem); | |
0 | 5802 %} |
5803 | |
5804 // Load Integer | |
5805 instruct loadI(iRegI dst, memory mem) %{ | |
5806 match(Set dst (LoadI mem)); | |
5807 ins_cost(MEMORY_REF_COST); | |
624 | 5808 |
5809 size(4); | |
5810 format %{ "LDUW $mem,$dst\t! int" %} | |
727 | 5811 ins_encode %{ |
5812 __ lduw($mem$$Address, $dst$$Register); | |
5813 %} | |
624 | 5814 ins_pipe(iload_mem); |
5815 %} | |
5816 | |
785 | 5817 // Load Integer to Byte (8 bit signed) |
5818 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5819 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
5820 ins_cost(MEMORY_REF_COST); | |
5821 | |
5822 size(4); | |
5823 | |
5824 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} | |
5825 ins_encode %{ | |
5826 __ ldsb($mem$$Address, $dst$$Register, 3); | |
5827 %} | |
5828 ins_pipe(iload_mask_mem); | |
5829 %} | |
5830 | |
5831 // Load Integer to Unsigned Byte (8 bit UNsigned) | |
5832 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ | |
5833 match(Set dst (AndI (LoadI mem) mask)); | |
5834 ins_cost(MEMORY_REF_COST); | |
5835 | |
5836 size(4); | |
5837 | |
5838 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} | |
5839 ins_encode %{ | |
5840 __ ldub($mem$$Address, $dst$$Register, 3); | |
5841 %} | |
5842 ins_pipe(iload_mask_mem); | |
5843 %} | |
5844 | |
5845 // Load Integer to Short (16 bit signed) | |
5846 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ | |
5847 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
5848 ins_cost(MEMORY_REF_COST); | |
5849 | |
5850 size(4); | |
5851 | |
5852 format %{ "LDSH $mem+2,$dst\t! int -> short" %} | |
5853 ins_encode %{ | |
5854 __ ldsh($mem$$Address, $dst$$Register, 2); | |
5855 %} | |
5856 ins_pipe(iload_mask_mem); | |
5857 %} | |
5858 | |
5859 // Load Integer to Unsigned Short (16 bit UNsigned) | |
5860 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ | |
5861 match(Set dst (AndI (LoadI mem) mask)); | |
5862 ins_cost(MEMORY_REF_COST); | |
5863 | |
5864 size(4); | |
5865 | |
5866 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} | |
5867 ins_encode %{ | |
5868 __ lduh($mem$$Address, $dst$$Register, 2); | |
5869 %} | |
5870 ins_pipe(iload_mask_mem); | |
5871 %} | |
5872 | |
624 | 5873 // Load Integer into a Long Register |
5874 instruct loadI2L(iRegL dst, memory mem) %{ | |
5875 match(Set dst (ConvI2L (LoadI mem))); | |
5876 ins_cost(MEMORY_REF_COST); | |
5877 | |
5878 size(4); | |
5879 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
727 | 5880 ins_encode %{ |
5881 __ ldsw($mem$$Address, $dst$$Register); | |
5882 %} | |
824 | 5883 ins_pipe(iload_mask_mem); |
5884 %} | |
5885 | |
5886 // Load Integer with mask 0xFF into a Long Register | |
5887 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
5888 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5889 ins_cost(MEMORY_REF_COST); | |
5890 | |
5891 size(4); | |
5892 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} | |
5893 ins_encode %{ | |
5894 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE | |
5895 %} | |
5896 ins_pipe(iload_mem); | |
5897 %} | |
5898 | |
5899 // Load Integer with mask 0xFFFF into a Long Register | |
5900 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ | |
5901 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5902 ins_cost(MEMORY_REF_COST); | |
5903 | |
5904 size(4); | |
5905 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} | |
5906 ins_encode %{ | |
5907 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | |
5908 %} | |
5909 ins_pipe(iload_mem); | |
5910 %} | |
5911 | |
17506
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
5912 // Load Integer with a 12-bit mask into a Long Register |
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
5913 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{ |
824 | 5914 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
5915 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5916 | |
5917 size(2*4); | |
17506
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
5918 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t" |
824 | 5919 "AND $dst,$mask,$dst" %} |
5920 ins_encode %{ | |
5921 Register Rdst = $dst$$Register; | |
5922 __ lduw($mem$$Address, Rdst); | |
5923 __ and3(Rdst, $mask$$constant, Rdst); | |
5924 %} | |
5925 ins_pipe(iload_mem); | |
5926 %} | |
5927 | |
17506
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
5928 // Load Integer with a 31-bit mask into a Long Register |
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
5929 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{ |
824 | 5930 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
5931 effect(TEMP dst, TEMP tmp); | |
5932 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
5933 | |
17506
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
5934 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t" |
824 | 5935 "SET $mask,$tmp\n\t" |
5936 "AND $dst,$tmp,$dst" %} | |
5937 ins_encode %{ | |
5938 Register Rdst = $dst$$Register; | |
5939 Register Rtmp = $tmp$$Register; | |
5940 __ lduw($mem$$Address, Rdst); | |
5941 __ set($mask$$constant, Rtmp); | |
5942 __ and3(Rdst, Rtmp, Rdst); | |
5943 %} | |
624 | 5944 ins_pipe(iload_mem); |
5945 %} | |
5946 | |
5947 // Load Unsigned Integer into a Long Register | |
6849 | 5948 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{ |
5949 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
624 | 5950 ins_cost(MEMORY_REF_COST); |
5951 | |
5952 size(4); | |
5953 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
727 | 5954 ins_encode %{ |
5955 __ lduw($mem$$Address, $dst$$Register); | |
5956 %} | |
0 | 5957 ins_pipe(iload_mem); |
5958 %} | |
5959 | |
5960 // Load Long - aligned | |
5961 instruct loadL(iRegL dst, memory mem ) %{ | |
5962 match(Set dst (LoadL mem)); | |
5963 ins_cost(MEMORY_REF_COST); | |
624 | 5964 |
0 | 5965 size(4); |
5966 format %{ "LDX $mem,$dst\t! long" %} | |
727 | 5967 ins_encode %{ |
5968 __ ldx($mem$$Address, $dst$$Register); | |
5969 %} | |
0 | 5970 ins_pipe(iload_mem); |
5971 %} | |
5972 | |
5973 // Load Long - UNaligned | |
5974 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
5975 match(Set dst (LoadL_unaligned mem)); | |
5976 effect(KILL tmp); | |
5977 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
5978 size(16); | |
5979 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
5980 "\tLDUW $mem ,$dst\n" | |
5981 "\tSLLX #32, $dst, $dst\n" | |
5982 "\tOR $dst, R_O7, $dst" %} | |
5983 opcode(Assembler::lduw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5984 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
0 | 5985 ins_pipe(iload_mem); |
5986 %} | |
5987 | |
5988 // Load Range | |
5989 instruct loadRange(iRegI dst, memory mem) %{ | |
5990 match(Set dst (LoadRange mem)); | |
5991 ins_cost(MEMORY_REF_COST); | |
5992 | |
5993 size(4); | |
5994 format %{ "LDUW $mem,$dst\t! range" %} | |
5995 opcode(Assembler::lduw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5996 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5997 ins_pipe(iload_mem); |
5998 %} | |
5999 | |
6000 // Load Integer into %f register (for fitos/fitod) | |
6001 instruct loadI_freg(regF dst, memory mem) %{ | |
6002 match(Set dst (LoadI mem)); | |
6003 ins_cost(MEMORY_REF_COST); | |
6004 size(4); | |
6005 | |
6006 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
6007 opcode(Assembler::ldf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6008 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 6009 ins_pipe(floadF_mem); |
6010 %} | |
6011 | |
6012 // Load Pointer | |
6013 instruct loadP(iRegP dst, memory mem) %{ | |
6014 match(Set dst (LoadP mem)); | |
6015 ins_cost(MEMORY_REF_COST); | |
6016 size(4); | |
6017 | |
6018 #ifndef _LP64 | |
6019 format %{ "LDUW $mem,$dst\t! ptr" %} | |
727 | 6020 ins_encode %{ |
6021 __ lduw($mem$$Address, $dst$$Register); | |
6022 %} | |
0 | 6023 #else |
6024 format %{ "LDX $mem,$dst\t! ptr" %} | |
727 | 6025 ins_encode %{ |
6026 __ ldx($mem$$Address, $dst$$Register); | |
6027 %} | |
0 | 6028 #endif |
6029 ins_pipe(iload_mem); | |
6030 %} | |
6031 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6032 // Load Compressed Pointer |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6033 instruct loadN(iRegN dst, memory mem) %{ |
727 | 6034 match(Set dst (LoadN mem)); |
6035 ins_cost(MEMORY_REF_COST); | |
6036 size(4); | |
6037 | |
6038 format %{ "LDUW $mem,$dst\t! compressed ptr" %} | |
6039 ins_encode %{ | |
6040 __ lduw($mem$$Address, $dst$$Register); | |
6041 %} | |
6042 ins_pipe(iload_mem); | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6043 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6044 |
0 | 6045 // Load Klass Pointer |
6046 instruct loadKlass(iRegP dst, memory mem) %{ | |
6047 match(Set dst (LoadKlass mem)); | |
6048 ins_cost(MEMORY_REF_COST); | |
6049 size(4); | |
6050 | |
6051 #ifndef _LP64 | |
6052 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
727 | 6053 ins_encode %{ |
6054 __ lduw($mem$$Address, $dst$$Register); | |
6055 %} | |
0 | 6056 #else |
6057 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
727 | 6058 ins_encode %{ |
6059 __ ldx($mem$$Address, $dst$$Register); | |
6060 %} | |
0 | 6061 #endif |
6062 ins_pipe(iload_mem); | |
6063 %} | |
6064 | |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6065 // Load narrow Klass Pointer |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6066 instruct loadNKlass(iRegN dst, memory mem) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6067 match(Set dst (LoadNKlass mem)); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6068 ins_cost(MEMORY_REF_COST); |
165
437d03ea40b1
6703888: Compressed Oops: use the 32-bits gap after klass in a object
kvn
parents:
164
diff
changeset
|
6069 size(4); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6070 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6071 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6072 ins_encode %{ |
727 | 6073 __ lduw($mem$$Address, $dst$$Register); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6074 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6075 ins_pipe(iload_mem); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6076 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6077 |
0 | 6078 // Load Double |
6079 instruct loadD(regD dst, memory mem) %{ | |
6080 match(Set dst (LoadD mem)); | |
6081 ins_cost(MEMORY_REF_COST); | |
6082 | |
6083 size(4); | |
6084 format %{ "LDDF $mem,$dst" %} | |
6085 opcode(Assembler::lddf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6086 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 6087 ins_pipe(floadD_mem); |
6088 %} | |
6089 | |
6090 // Load Double - UNaligned | |
6091 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
6092 match(Set dst (LoadD_unaligned mem)); | |
6093 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
6094 size(8); | |
6095 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
6096 "\tLDF $mem+4,$dst.lo\t!" %} | |
6097 opcode(Assembler::ldf_op3); | |
6098 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
6099 ins_pipe(iload_mem); | |
6100 %} | |
6101 | |
6102 // Load Float | |
6103 instruct loadF(regF dst, memory mem) %{ | |
6104 match(Set dst (LoadF mem)); | |
6105 ins_cost(MEMORY_REF_COST); | |
6106 | |
6107 size(4); | |
6108 format %{ "LDF $mem,$dst" %} | |
6109 opcode(Assembler::ldf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6110 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 6111 ins_pipe(floadF_mem); |
6112 %} | |
6113 | |
6114 // Load Constant | |
6115 instruct loadConI( iRegI dst, immI src ) %{ | |
6116 match(Set dst src); | |
6117 ins_cost(DEFAULT_COST * 3/2); | |
6118 format %{ "SET $src,$dst" %} | |
6119 ins_encode( Set32(src, dst) ); | |
6120 ins_pipe(ialu_hi_lo_reg); | |
6121 %} | |
6122 | |
6123 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
6124 match(Set dst src); | |
6125 | |
6126 size(4); | |
6127 format %{ "MOV $src,$dst" %} | |
6128 ins_encode( Set13( src, dst ) ); | |
6129 ins_pipe(ialu_imm); | |
6130 %} | |
6131 | |
2008 | 6132 #ifndef _LP64 |
6133 instruct loadConP(iRegP dst, immP con) %{ | |
6134 match(Set dst con); | |
6135 ins_cost(DEFAULT_COST * 3/2); | |
6136 format %{ "SET $con,$dst\t!ptr" %} | |
6137 ins_encode %{ | |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
6138 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); |
2008 | 6139 intptr_t val = $con$$constant; |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
6140 if (constant_reloc == relocInfo::oop_type) { |
2008 | 6141 __ set_oop_constant((jobject) val, $dst$$Register); |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
6142 } else if (constant_reloc == relocInfo::metadata_type) { |
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
6143 __ set_metadata_constant((Metadata*)val, $dst$$Register); |
2008 | 6144 } else { // non-oop pointers, e.g. card mark base, heap top |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
6145 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); |
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
6146 __ set(val, $dst$$Register); |
2008 | 6147 } |
6148 %} | |
6149 ins_pipe(loadConP); | |
6150 %} | |
6151 #else | |
6152 instruct loadConP_set(iRegP dst, immP_set con) %{ | |
6153 match(Set dst con); | |
0 | 6154 ins_cost(DEFAULT_COST * 3/2); |
2008 | 6155 format %{ "SET $con,$dst\t! ptr" %} |
6156 ins_encode %{ | |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
6157 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); |
2008 | 6158 intptr_t val = $con$$constant; |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
6159 if (constant_reloc == relocInfo::oop_type) { |
2008 | 6160 __ set_oop_constant((jobject) val, $dst$$Register); |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
6161 } else if (constant_reloc == relocInfo::metadata_type) { |
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
6162 __ set_metadata_constant((Metadata*)val, $dst$$Register); |
2008 | 6163 } else { // non-oop pointers, e.g. card mark base, heap top |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
6164 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); |
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6179
diff
changeset
|
6165 __ set(val, $dst$$Register); |
2008 | 6166 } |
6167 %} | |
0 | 6168 ins_pipe(loadConP); |
2008 | 6169 %} |
6170 | |
6171 instruct loadConP_load(iRegP dst, immP_load con) %{ | |
6172 match(Set dst con); | |
6173 ins_cost(MEMORY_REF_COST); | |
6174 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} | |
6175 ins_encode %{ | |
2076
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6176 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6177 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6178 %} |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6179 ins_pipe(loadConP); |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6180 %} |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6181 |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6182 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6183 match(Set dst con); |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6184 ins_cost(DEFAULT_COST * 3/2); |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6185 format %{ "SET $con,$dst\t! non-oop ptr" %} |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6186 ins_encode %{ |
7737fa7ec2b5
7006044: materialize cheap non-oop pointers on 64-bit SPARC
twisti
parents:
2012
diff
changeset
|
6187 __ set($con$$constant, $dst$$Register); |
2008 | 6188 %} |
6189 ins_pipe(loadConP); | |
6190 %} | |
6191 #endif // _LP64 | |
0 | 6192 |
6193 instruct loadConP0(iRegP dst, immP0 src) %{ | |
6194 match(Set dst src); | |
6195 | |
6196 size(4); | |
6197 format %{ "CLR $dst\t!ptr" %} | |
2008 | 6198 ins_encode %{ |
6199 __ clr($dst$$Register); | |
6200 %} | |
0 | 6201 ins_pipe(ialu_imm); |
6202 %} | |
6203 | |
6204 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
6205 match(Set dst src); | |
6206 ins_cost(DEFAULT_COST); | |
6207 format %{ "SET $src,$dst\t!ptr" %} | |
6208 ins_encode %{ | |
727 | 6209 AddressLiteral polling_page(os::get_polling_page()); |
6210 __ sethi(polling_page, reg_to_register_object($dst$$reg)); | |
0 | 6211 %} |
6212 ins_pipe(loadConP_poll); | |
6213 %} | |
6214 | |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6215 instruct loadConN0(iRegN dst, immN0 src) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6216 match(Set dst src); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6217 |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6218 size(4); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6219 format %{ "CLR $dst\t! compressed NULL ptr" %} |
2008 | 6220 ins_encode %{ |
6221 __ clr($dst$$Register); | |
6222 %} | |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6223 ins_pipe(ialu_imm); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6224 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6225 |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6226 instruct loadConN(iRegN dst, immN src) %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6227 match(Set dst src); |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6228 ins_cost(DEFAULT_COST * 3/2); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6229 format %{ "SET $src,$dst\t! compressed ptr" %} |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6230 ins_encode %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6231 Register dst = $dst$$Register; |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6232 __ set_narrow_oop((jobject)$src$$constant, dst); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6233 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6234 ins_pipe(ialu_hi_lo_reg); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6235 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6236 |
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6237 instruct loadConNKlass(iRegN dst, immNKlass src) %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6238 match(Set dst src); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6239 ins_cost(DEFAULT_COST * 3/2); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6240 format %{ "SET $src,$dst\t! compressed klass ptr" %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6241 ins_encode %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6242 Register dst = $dst$$Register; |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6243 __ set_narrow_klass((Klass*)$src$$constant, dst); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6244 %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6245 ins_pipe(ialu_hi_lo_reg); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6246 %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6247 |
2008 | 6248 // Materialize long value (predicated by immL_cheap). |
6249 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ | |
6250 match(Set dst con); | |
0 | 6251 effect(KILL tmp); |
2008 | 6252 ins_cost(DEFAULT_COST * 3); |
6253 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} | |
6254 ins_encode %{ | |
6255 __ set64($con$$constant, $dst$$Register, $tmp$$Register); | |
6256 %} | |
6257 ins_pipe(loadConL); | |
6258 %} | |
6259 | |
6260 // Load long value from constant table (predicated by immL_expensive). | |
6261 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ | |
6262 match(Set dst con); | |
6263 ins_cost(MEMORY_REF_COST); | |
6264 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} | |
6265 ins_encode %{ | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6266 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6267 __ ldx($constanttablebase, con_offset, $dst$$Register); |
2008 | 6268 %} |
0 | 6269 ins_pipe(loadConL); |
6270 %} | |
6271 | |
6272 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
6273 match(Set dst src); | |
6274 ins_cost(DEFAULT_COST); | |
6275 size(4); | |
6276 format %{ "CLR $dst\t! long" %} | |
6277 ins_encode( Set13( src, dst ) ); | |
6278 ins_pipe(ialu_imm); | |
6279 %} | |
6280 | |
6281 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
6282 match(Set dst src); | |
6283 ins_cost(DEFAULT_COST * 2); | |
6284 | |
6285 size(4); | |
6286 format %{ "MOV $src,$dst\t! long" %} | |
6287 ins_encode( Set13( src, dst ) ); | |
6288 ins_pipe(ialu_imm); | |
6289 %} | |
6290 | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6291 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ |
2008 | 6292 match(Set dst con); |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6293 effect(KILL tmp); |
2008 | 6294 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} |
727 | 6295 ins_encode %{ |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6296 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6297 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); |
727 | 6298 %} |
0 | 6299 ins_pipe(loadConFD); |
6300 %} | |
6301 | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6302 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ |
2008 | 6303 match(Set dst con); |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6304 effect(KILL tmp); |
2008 | 6305 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} |
727 | 6306 ins_encode %{ |
732
fb4c18a2ec66
6833573: C2 sparc: assert(c < 64 && (c & 1) == 0,"bad double float register")
never
parents:
727
diff
changeset
|
6307 // XXX This is a quick fix for 6833573. |
2008 | 6308 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6309 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
6310 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
727 | 6311 %} |
0 | 6312 ins_pipe(loadConFD); |
6313 %} | |
6314 | |
6315 // Prefetch instructions. | |
6316 // Must be safe to execute with invalid address (cannot fault). | |
6317 | |
6318 instruct prefetchr( memory mem ) %{ | |
6319 match( PrefetchRead mem ); | |
6320 ins_cost(MEMORY_REF_COST); | |
3854 | 6321 size(4); |
0 | 6322 |
6323 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
6324 opcode(Assembler::prefetch_op3); | |
6325 ins_encode( form3_mem_prefetch_read( mem ) ); | |
6326 ins_pipe(iload_mem); | |
6327 %} | |
6328 | |
6329 instruct prefetchw( memory mem ) %{ | |
6330 match( PrefetchWrite mem ); | |
6331 ins_cost(MEMORY_REF_COST); | |
3854 | 6332 size(4); |
0 | 6333 |
6334 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
6335 opcode(Assembler::prefetch_op3); | |
6336 ins_encode( form3_mem_prefetch_write( mem ) ); | |
6337 ins_pipe(iload_mem); | |
6338 %} | |
6339 | |
3854 | 6340 // Prefetch instructions for allocation. |
6341 | |
6342 instruct prefetchAlloc( memory mem ) %{ | |
6343 predicate(AllocatePrefetchInstr == 0); | |
6344 match( PrefetchAllocation mem ); | |
6345 ins_cost(MEMORY_REF_COST); | |
6346 size(4); | |
6347 | |
6348 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %} | |
6349 opcode(Assembler::prefetch_op3); | |
6350 ins_encode( form3_mem_prefetch_write( mem ) ); | |
6351 ins_pipe(iload_mem); | |
6352 %} | |
6353 | |
6354 // Use BIS instruction to prefetch for allocation. | |
6355 // Could fault, need space at the end of TLAB. | |
6356 instruct prefetchAlloc_bis( iRegP dst ) %{ | |
6357 predicate(AllocatePrefetchInstr == 1); | |
6358 match( PrefetchAllocation dst ); | |
6359 ins_cost(MEMORY_REF_COST); | |
6360 size(4); | |
6361 | |
6362 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %} | |
6363 ins_encode %{ | |
6364 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); | |
1367
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6365 %} |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6366 ins_pipe(istore_mem_reg); |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1274
diff
changeset
|
6367 %} |
0 | 6368 |
3854 | 6369 // Next code is used for finding next cache line address to prefetch. |
6370 #ifndef _LP64 | |
6371 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{ | |
6372 match(Set dst (CastX2P (AndI (CastP2X src) mask))); | |
6373 ins_cost(DEFAULT_COST); | |
6374 size(4); | |
6375 | |
6376 format %{ "AND $src,$mask,$dst\t! next cache line address" %} | |
6377 ins_encode %{ | |
6378 __ and3($src$$Register, $mask$$constant, $dst$$Register); | |
6379 %} | |
6380 ins_pipe(ialu_reg_imm); | |
6381 %} | |
6382 #else | |
6383 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{ | |
6384 match(Set dst (CastX2P (AndL (CastP2X src) mask))); | |
6385 ins_cost(DEFAULT_COST); | |
6386 size(4); | |
6387 | |
6388 format %{ "AND $src,$mask,$dst\t! next cache line address" %} | |
6389 ins_encode %{ | |
6390 __ and3($src$$Register, $mask$$constant, $dst$$Register); | |
6391 %} | |
6392 ins_pipe(ialu_reg_imm); | |
6393 %} | |
6394 #endif | |
6395 | |
0 | 6396 //----------Store Instructions------------------------------------------------- |
6397 // Store Byte | |
6398 instruct storeB(memory mem, iRegI src) %{ | |
6399 match(Set mem (StoreB mem src)); | |
6400 ins_cost(MEMORY_REF_COST); | |
6401 | |
6402 size(4); | |
6403 format %{ "STB $src,$mem\t! byte" %} | |
6404 opcode(Assembler::stb_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6405 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6406 ins_pipe(istore_mem_reg); |
6407 %} | |
6408 | |
6409 instruct storeB0(memory mem, immI0 src) %{ | |
6410 match(Set mem (StoreB mem src)); | |
6411 ins_cost(MEMORY_REF_COST); | |
6412 | |
6413 size(4); | |
6414 format %{ "STB $src,$mem\t! byte" %} | |
6415 opcode(Assembler::stb_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6416 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6417 ins_pipe(istore_mem_zero); |
6418 %} | |
6419 | |
6420 instruct storeCM0(memory mem, immI0 src) %{ | |
6421 match(Set mem (StoreCM mem src)); | |
6422 ins_cost(MEMORY_REF_COST); | |
6423 | |
6424 size(4); | |
6425 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
6426 opcode(Assembler::stb_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6427 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6428 ins_pipe(istore_mem_zero); |
6429 %} | |
6430 | |
6431 // Store Char/Short | |
6432 instruct storeC(memory mem, iRegI src) %{ | |
6433 match(Set mem (StoreC mem src)); | |
6434 ins_cost(MEMORY_REF_COST); | |
6435 | |
6436 size(4); | |
6437 format %{ "STH $src,$mem\t! short" %} | |
6438 opcode(Assembler::sth_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6439 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6440 ins_pipe(istore_mem_reg); |
6441 %} | |
6442 | |
6443 instruct storeC0(memory mem, immI0 src) %{ | |
6444 match(Set mem (StoreC mem src)); | |
6445 ins_cost(MEMORY_REF_COST); | |
6446 | |
6447 size(4); | |
6448 format %{ "STH $src,$mem\t! short" %} | |
6449 opcode(Assembler::sth_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6450 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6451 ins_pipe(istore_mem_zero); |
6452 %} | |
6453 | |
6454 // Store Integer | |
6455 instruct storeI(memory mem, iRegI src) %{ | |
6456 match(Set mem (StoreI mem src)); | |
6457 ins_cost(MEMORY_REF_COST); | |
6458 | |
6459 size(4); | |
6460 format %{ "STW $src,$mem" %} | |
6461 opcode(Assembler::stw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6462 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6463 ins_pipe(istore_mem_reg); |
6464 %} | |
6465 | |
6466 // Store Long | |
6467 instruct storeL(memory mem, iRegL src) %{ | |
6468 match(Set mem (StoreL mem src)); | |
6469 ins_cost(MEMORY_REF_COST); | |
6470 size(4); | |
6471 format %{ "STX $src,$mem\t! long" %} | |
6472 opcode(Assembler::stx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6473 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6474 ins_pipe(istore_mem_reg); |
6475 %} | |
6476 | |
6477 instruct storeI0(memory mem, immI0 src) %{ | |
6478 match(Set mem (StoreI mem src)); | |
6479 ins_cost(MEMORY_REF_COST); | |
6480 | |
6481 size(4); | |
6482 format %{ "STW $src,$mem" %} | |
6483 opcode(Assembler::stw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6484 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6485 ins_pipe(istore_mem_zero); |
6486 %} | |
6487 | |
6488 instruct storeL0(memory mem, immL0 src) %{ | |
6489 match(Set mem (StoreL mem src)); | |
6490 ins_cost(MEMORY_REF_COST); | |
6491 | |
6492 size(4); | |
6493 format %{ "STX $src,$mem" %} | |
6494 opcode(Assembler::stx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6495 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6496 ins_pipe(istore_mem_zero); |
6497 %} | |
6498 | |
6499 // Store Integer from float register (used after fstoi) | |
6500 instruct storeI_Freg(memory mem, regF src) %{ | |
6501 match(Set mem (StoreI mem src)); | |
6502 ins_cost(MEMORY_REF_COST); | |
6503 | |
6504 size(4); | |
6505 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
6506 opcode(Assembler::stf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6507 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6508 ins_pipe(fstoreF_mem_reg); |
6509 %} | |
6510 | |
6511 // Store Pointer | |
6512 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
6513 match(Set dst (StoreP dst src)); | |
6514 ins_cost(MEMORY_REF_COST); | |
6515 size(4); | |
6516 | |
6517 #ifndef _LP64 | |
6518 format %{ "STW $src,$dst\t! ptr" %} | |
6519 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6520 #else | |
6521 format %{ "STX $src,$dst\t! ptr" %} | |
6522 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6523 #endif | |
6524 ins_encode( form3_mem_reg( dst, src ) ); | |
6525 ins_pipe(istore_mem_spORreg); | |
6526 %} | |
6527 | |
6528 instruct storeP0(memory dst, immP0 src) %{ | |
6529 match(Set dst (StoreP dst src)); | |
6530 ins_cost(MEMORY_REF_COST); | |
6531 size(4); | |
6532 | |
6533 #ifndef _LP64 | |
6534 format %{ "STW $src,$dst\t! ptr" %} | |
6535 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6536 #else | |
6537 format %{ "STX $src,$dst\t! ptr" %} | |
6538 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6539 #endif | |
6540 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
6541 ins_pipe(istore_mem_zero); | |
6542 %} | |
6543 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6544 // Store Compressed Pointer |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6545 instruct storeN(memory dst, iRegN src) %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6546 match(Set dst (StoreN dst src)); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6547 ins_cost(MEMORY_REF_COST); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6548 size(4); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6549 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6550 format %{ "STW $src,$dst\t! compressed ptr" %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6551 ins_encode %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6552 Register base = as_Register($dst$$base); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6553 Register index = as_Register($dst$$index); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6554 Register src = $src$$Register; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6555 if (index != G0) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6556 __ stw(src, base, index); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6557 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6558 __ stw(src, base, $dst$$disp); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6559 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6560 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6561 ins_pipe(istore_mem_spORreg); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6562 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6563 |
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6564 instruct storeNKlass(memory dst, iRegN src) %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6565 match(Set dst (StoreNKlass dst src)); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6566 ins_cost(MEMORY_REF_COST); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6567 size(4); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6568 |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6569 format %{ "STW $src,$dst\t! compressed klass ptr" %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6570 ins_encode %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6571 Register base = as_Register($dst$$base); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6572 Register index = as_Register($dst$$index); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6573 Register src = $src$$Register; |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6574 if (index != G0) { |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6575 __ stw(src, base, index); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6576 } else { |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6577 __ stw(src, base, $dst$$disp); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6578 } |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6579 %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6580 ins_pipe(istore_mem_spORreg); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6581 %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6582 |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6583 instruct storeN0(memory dst, immN0 src) %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6584 match(Set dst (StoreN dst src)); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6585 ins_cost(MEMORY_REF_COST); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6586 size(4); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6587 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6588 format %{ "STW $src,$dst\t! compressed ptr" %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6589 ins_encode %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6590 Register base = as_Register($dst$$base); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6591 Register index = as_Register($dst$$index); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6592 if (index != G0) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6593 __ stw(0, base, index); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6594 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6595 __ stw(0, base, $dst$$disp); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6596 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6597 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6598 ins_pipe(istore_mem_zero); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6599 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6600 |
0 | 6601 // Store Double |
6602 instruct storeD( memory mem, regD src) %{ | |
6603 match(Set mem (StoreD mem src)); | |
6604 ins_cost(MEMORY_REF_COST); | |
6605 | |
6606 size(4); | |
6607 format %{ "STDF $src,$mem" %} | |
6608 opcode(Assembler::stdf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6609 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6610 ins_pipe(fstoreD_mem_reg); |
6611 %} | |
6612 | |
6613 instruct storeD0( memory mem, immD0 src) %{ | |
6614 match(Set mem (StoreD mem src)); | |
6615 ins_cost(MEMORY_REF_COST); | |
6616 | |
6617 size(4); | |
6618 format %{ "STX $src,$mem" %} | |
6619 opcode(Assembler::stx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6620 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6621 ins_pipe(fstoreD_mem_zero); |
6622 %} | |
6623 | |
6624 // Store Float | |
6625 instruct storeF( memory mem, regF src) %{ | |
6626 match(Set mem (StoreF mem src)); | |
6627 ins_cost(MEMORY_REF_COST); | |
6628 | |
6629 size(4); | |
6630 format %{ "STF $src,$mem" %} | |
6631 opcode(Assembler::stf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6632 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6633 ins_pipe(fstoreF_mem_reg); |
6634 %} | |
6635 | |
6636 instruct storeF0( memory mem, immF0 src) %{ | |
6637 match(Set mem (StoreF mem src)); | |
6638 ins_cost(MEMORY_REF_COST); | |
6639 | |
6640 size(4); | |
6641 format %{ "STW $src,$mem\t! storeF0" %} | |
6642 opcode(Assembler::stw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6643 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6644 ins_pipe(fstoreF_mem_zero); |
6645 %} | |
6646 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6647 // Convert oop pointer into compressed form |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6648 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6649 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6650 match(Set dst (EncodeP src)); |
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6651 format %{ "encode_heap_oop $src, $dst" %} |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6652 ins_encode %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6653 __ encode_heap_oop($src$$Register, $dst$$Register); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6654 %} |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
6655 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6656 ins_pipe(ialu_reg); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6657 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6658 |
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6659 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6660 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6661 match(Set dst (EncodeP src)); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6662 format %{ "encode_heap_oop_not_null $src, $dst" %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6663 ins_encode %{ |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6664 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6665 %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6666 ins_pipe(ialu_reg); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6667 %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6668 |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6669 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
182
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6670 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6671 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6672 match(Set dst (DecodeN src)); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6673 format %{ "decode_heap_oop $src, $dst" %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6674 ins_encode %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6675 __ decode_heap_oop($src$$Register, $dst$$Register); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6676 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6677 ins_pipe(ialu_reg); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6678 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6679 |
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6680 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
182
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6681 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6682 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6683 match(Set dst (DecodeN src)); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6684 format %{ "decode_heap_oop_not_null $src, $dst" %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6685 ins_encode %{ |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6686 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6687 %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6688 ins_pipe(ialu_reg); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6689 %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6690 |
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6691 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6692 match(Set dst (EncodePKlass src)); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6693 format %{ "encode_klass_not_null $src, $dst" %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6694 ins_encode %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6695 __ encode_klass_not_null($src$$Register, $dst$$Register); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6696 %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6697 ins_pipe(ialu_reg); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6698 %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6699 |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6700 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6701 match(Set dst (DecodeNKlass src)); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6702 format %{ "decode_klass_not_null $src, $dst" %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6703 ins_encode %{ |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6704 __ decode_klass_not_null($src$$Register, $dst$$Register); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6705 %} |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6706 ins_pipe(ialu_reg); |
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6823
diff
changeset
|
6707 %} |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6708 |
0 | 6709 //----------MemBar Instructions----------------------------------------------- |
6710 // Memory barrier flavors | |
6711 | |
6712 instruct membar_acquire() %{ | |
6713 match(MemBarAcquire); | |
14439
50fdb38839eb
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
14435
diff
changeset
|
6714 match(LoadFence); |
0 | 6715 ins_cost(4*MEMORY_REF_COST); |
6716 | |
6717 size(0); | |
6718 format %{ "MEMBAR-acquire" %} | |
6719 ins_encode( enc_membar_acquire ); | |
6720 ins_pipe(long_memory_op); | |
6721 %} | |
6722 | |
6723 instruct membar_acquire_lock() %{ | |
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6724 match(MemBarAcquireLock); |
0 | 6725 ins_cost(0); |
6726 | |
6727 size(0); | |
6728 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
6729 ins_encode( ); | |
6730 ins_pipe(empty); | |
6731 %} | |
6732 | |
6733 instruct membar_release() %{ | |
6734 match(MemBarRelease); | |
14439
50fdb38839eb
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
14435
diff
changeset
|
6735 match(StoreFence); |
0 | 6736 ins_cost(4*MEMORY_REF_COST); |
6737 | |
6738 size(0); | |
6739 format %{ "MEMBAR-release" %} | |
6740 ins_encode( enc_membar_release ); | |
6741 ins_pipe(long_memory_op); | |
6742 %} | |
6743 | |
6744 instruct membar_release_lock() %{ | |
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6745 match(MemBarReleaseLock); |
0 | 6746 ins_cost(0); |
6747 | |
6748 size(0); | |
6749 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
6750 ins_encode( ); | |
6751 ins_pipe(empty); | |
6752 %} | |
6753 | |
6754 instruct membar_volatile() %{ | |
6755 match(MemBarVolatile); | |
6756 ins_cost(4*MEMORY_REF_COST); | |
6757 | |
6758 size(4); | |
6759 format %{ "MEMBAR-volatile" %} | |
6760 ins_encode( enc_membar_volatile ); | |
6761 ins_pipe(long_memory_op); | |
6762 %} | |
6763 | |
6764 instruct unnecessary_membar_volatile() %{ | |
6765 match(MemBarVolatile); | |
6766 predicate(Matcher::post_store_load_barrier(n)); | |
6767 ins_cost(0); | |
6768 | |
6769 size(0); | |
6770 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
6771 ins_encode( ); | |
6772 ins_pipe(empty); | |
6773 %} | |
6774 | |
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6775 instruct membar_storestore() %{ |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6776 match(MemBarStoreStore); |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6777 ins_cost(0); |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6778 |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6779 size(0); |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6780 format %{ "!MEMBAR-storestore (empty encoding)" %} |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6781 ins_encode( ); |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6782 ins_pipe(empty); |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6783 %} |
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4121
diff
changeset
|
6784 |
0 | 6785 //----------Register Move Instructions----------------------------------------- |
6786 instruct roundDouble_nop(regD dst) %{ | |
6787 match(Set dst (RoundDouble dst)); | |
6788 ins_cost(0); | |
6789 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6790 ins_encode( ); | |
6791 ins_pipe(empty); | |
6792 %} | |
6793 | |
6794 | |
6795 instruct roundFloat_nop(regF dst) %{ | |
6796 match(Set dst (RoundFloat dst)); | |
6797 ins_cost(0); | |
6798 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6799 ins_encode( ); | |
6800 ins_pipe(empty); | |
6801 %} | |
6802 | |
6803 | |
6804 // Cast Index to Pointer for unsafe natives | |
6805 instruct castX2P(iRegX src, iRegP dst) %{ | |
6806 match(Set dst (CastX2P src)); | |
6807 | |
6808 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
6809 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6810 ins_pipe(ialu_reg); | |
6811 %} | |
6812 | |
6813 // Cast Pointer to Index for unsafe natives | |
6814 instruct castP2X(iRegP src, iRegX dst) %{ | |
6815 match(Set dst (CastP2X src)); | |
6816 | |
6817 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
6818 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6819 ins_pipe(ialu_reg); | |
6820 %} | |
6821 | |
6822 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
6823 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6824 match(Set stkSlot src); // chain rule | |
6825 ins_cost(MEMORY_REF_COST); | |
6826 format %{ "STDF $src,$stkSlot\t!stk" %} | |
6827 opcode(Assembler::stdf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6828 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6829 ins_pipe(fstoreD_stk_reg); |
6830 %} | |
6831 | |
6832 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
6833 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6834 match(Set dst stkSlot); // chain rule | |
6835 ins_cost(MEMORY_REF_COST); | |
6836 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
6837 opcode(Assembler::lddf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6838 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
0 | 6839 ins_pipe(floadD_stk); |
6840 %} | |
6841 | |
6842 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
6843 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6844 match(Set stkSlot src); // chain rule | |
6845 ins_cost(MEMORY_REF_COST); | |
6846 format %{ "STF $src,$stkSlot\t!stk" %} | |
6847 opcode(Assembler::stf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6848 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6849 ins_pipe(fstoreF_stk_reg); |
6850 %} | |
6851 | |
6852 //----------Conditional Move--------------------------------------------------- | |
6853 // Conditional move | |
6854 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
6855 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6856 ins_cost(150); | |
6857 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6858 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6859 ins_pipe(ialu_reg); | |
6860 %} | |
6861 | |
6862 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
6863 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6864 ins_cost(140); | |
6865 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6866 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6867 ins_pipe(ialu_imm); | |
6868 %} | |
6869 | |
6870 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
6871 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6872 ins_cost(150); | |
6873 size(4); | |
6874 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6875 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6876 ins_pipe(ialu_reg); | |
6877 %} | |
6878 | |
6879 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
6880 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6881 ins_cost(140); | |
6882 size(4); | |
6883 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6884 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6885 ins_pipe(ialu_imm); | |
6886 %} | |
6887 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6888 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
0 | 6889 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6890 ins_cost(150); | |
6891 size(4); | |
6892 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6893 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6894 ins_pipe(ialu_reg); | |
6895 %} | |
6896 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6897 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
0 | 6898 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6899 ins_cost(140); | |
6900 size(4); | |
6901 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6902 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6903 ins_pipe(ialu_imm); | |
6904 %} | |
6905 | |
6906 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
6907 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6908 ins_cost(150); | |
6909 size(4); | |
6910 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6911 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6912 ins_pipe(ialu_reg); | |
6913 %} | |
6914 | |
6915 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
6916 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6917 ins_cost(140); | |
6918 size(4); | |
6919 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6920 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
6921 ins_pipe(ialu_imm); | |
6922 %} | |
6923 | |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6924 // Conditional move for RegN. Only cmov(reg,reg). |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6925 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6926 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6927 ins_cost(150); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6928 format %{ "MOV$cmp $pcc,$src,$dst" %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6929 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6930 ins_pipe(ialu_reg); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6931 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6932 |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6933 // This instruction also works with CmpN so we don't need cmovNN_reg. |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6934 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6935 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6936 ins_cost(150); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6937 size(4); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6938 format %{ "MOV$cmp $icc,$src,$dst" %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6939 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6940 ins_pipe(ialu_reg); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6941 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6942 |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6943 // This instruction also works with CmpN so we don't need cmovNN_reg. |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6944 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6945 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6946 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6947 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6948 format %{ "MOV$cmp $icc,$src,$dst" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6949 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6950 ins_pipe(ialu_reg); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6951 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6952 |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6953 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6954 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6955 ins_cost(150); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6956 size(4); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6957 format %{ "MOV$cmp $fcc,$src,$dst" %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6958 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6959 ins_pipe(ialu_reg); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6960 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6961 |
0 | 6962 // Conditional move |
6963 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
6964 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6965 ins_cost(150); | |
6966 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6967 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6968 ins_pipe(ialu_reg); | |
6969 %} | |
6970 | |
6971 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
6972 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6973 ins_cost(140); | |
6974 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6975 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6976 ins_pipe(ialu_imm); | |
6977 %} | |
6978 | |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6979 // This instruction also works with CmpN so we don't need cmovPN_reg. |
0 | 6980 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
6981 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
6982 ins_cost(150); | |
6983 | |
6984 size(4); | |
6985 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
6986 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6987 ins_pipe(ialu_reg); | |
6988 %} | |
6989 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6990 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6991 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6992 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6993 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6994 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6995 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6996 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6997 ins_pipe(ialu_reg); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6998 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6999 |
0 | 7000 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ |
7001 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
7002 ins_cost(140); | |
7003 | |
7004 size(4); | |
7005 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
7006 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
7007 ins_pipe(ialu_imm); | |
7008 %} | |
7009 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7010 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7011 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7012 ins_cost(140); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7013 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7014 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7015 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7016 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7017 ins_pipe(ialu_imm); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7018 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7019 |
0 | 7020 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ |
7021 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
7022 ins_cost(150); | |
7023 size(4); | |
7024 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
7025 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
7026 ins_pipe(ialu_imm); | |
7027 %} | |
7028 | |
7029 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
7030 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
7031 ins_cost(140); | |
7032 size(4); | |
7033 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
7034 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
7035 ins_pipe(ialu_imm); | |
7036 %} | |
7037 | |
7038 // Conditional move | |
7039 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
7040 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
7041 ins_cost(150); | |
7042 opcode(0x101); | |
7043 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
7044 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
7045 ins_pipe(int_conditional_float_move); | |
7046 %} | |
7047 | |
7048 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
7049 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
7050 ins_cost(150); | |
7051 | |
7052 size(4); | |
7053 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
7054 opcode(0x101); | |
7055 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
7056 ins_pipe(int_conditional_float_move); | |
7057 %} | |
7058 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7059 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7060 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7061 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7062 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7063 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7064 format %{ "FMOVS$cmp $icc,$src,$dst" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7065 opcode(0x101); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7066 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7067 ins_pipe(int_conditional_float_move); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7068 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7069 |
0 | 7070 // Conditional move, |
7071 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
7072 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
7073 ins_cost(150); | |
7074 size(4); | |
7075 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
7076 opcode(0x1); | |
7077 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
7078 ins_pipe(int_conditional_double_move); | |
7079 %} | |
7080 | |
7081 // Conditional move | |
7082 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
7083 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
7084 ins_cost(150); | |
7085 size(4); | |
7086 opcode(0x102); | |
7087 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
7088 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
7089 ins_pipe(int_conditional_double_move); | |
7090 %} | |
7091 | |
7092 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
7093 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
7094 ins_cost(150); | |
7095 | |
7096 size(4); | |
7097 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
7098 opcode(0x102); | |
7099 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
7100 ins_pipe(int_conditional_double_move); | |
7101 %} | |
7102 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7103 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7104 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7105 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7106 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7107 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7108 format %{ "FMOVD$cmp $icc,$src,$dst" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7109 opcode(0x102); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7110 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7111 ins_pipe(int_conditional_double_move); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7112 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7113 |
0 | 7114 // Conditional move, |
7115 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
7116 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
7117 ins_cost(150); | |
7118 size(4); | |
7119 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
7120 opcode(0x2); | |
7121 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
7122 ins_pipe(int_conditional_double_move); | |
7123 %} | |
7124 | |
7125 // Conditional move | |
7126 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
7127 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
7128 ins_cost(150); | |
7129 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
7130 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
7131 ins_pipe(ialu_reg); | |
7132 %} | |
7133 | |
7134 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
7135 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
7136 ins_cost(140); | |
7137 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
7138 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
7139 ins_pipe(ialu_imm); | |
7140 %} | |
7141 | |
7142 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
7143 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
7144 ins_cost(150); | |
7145 | |
7146 size(4); | |
7147 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
7148 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
7149 ins_pipe(ialu_reg); | |
7150 %} | |
7151 | |
7152 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7153 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7154 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7155 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7156 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7157 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7158 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7159 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7160 ins_pipe(ialu_reg); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7161 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7162 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
7163 |
0 | 7164 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ |
7165 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
7166 ins_cost(150); | |
7167 | |
7168 size(4); | |
7169 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
7170 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
7171 ins_pipe(ialu_reg); | |
7172 %} | |
7173 | |
7174 | |
7175 | |
7176 //----------OS and Locking Instructions---------------------------------------- | |
7177 | |
7178 // This name is KNOWN by the ADLC and cannot be changed. | |
7179 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
7180 // for this guy. | |
7181 instruct tlsLoadP(g2RegP dst) %{ | |
7182 match(Set dst (ThreadLocal)); | |
7183 | |
7184 size(0); | |
7185 ins_cost(0); | |
7186 format %{ "# TLS is in G2" %} | |
7187 ins_encode( /*empty encoding*/ ); | |
7188 ins_pipe(ialu_none); | |
7189 %} | |
7190 | |
7191 instruct checkCastPP( iRegP dst ) %{ | |
7192 match(Set dst (CheckCastPP dst)); | |
7193 | |
7194 size(0); | |
7195 format %{ "# checkcastPP of $dst" %} | |
7196 ins_encode( /*empty encoding*/ ); | |
7197 ins_pipe(empty); | |
7198 %} | |
7199 | |
7200 | |
7201 instruct castPP( iRegP dst ) %{ | |
7202 match(Set dst (CastPP dst)); | |
7203 format %{ "# castPP of $dst" %} | |
7204 ins_encode( /*empty encoding*/ ); | |
7205 ins_pipe(empty); | |
7206 %} | |
7207 | |
7208 instruct castII( iRegI dst ) %{ | |
7209 match(Set dst (CastII dst)); | |
7210 format %{ "# castII of $dst" %} | |
7211 ins_encode( /*empty encoding*/ ); | |
7212 ins_cost(0); | |
7213 ins_pipe(empty); | |
7214 %} | |
7215 | |
7216 //----------Arithmetic Instructions-------------------------------------------- | |
7217 // Addition Instructions | |
7218 // Register Addition | |
7219 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7220 match(Set dst (AddI src1 src2)); | |
7221 | |
7222 size(4); | |
7223 format %{ "ADD $src1,$src2,$dst" %} | |
7224 ins_encode %{ | |
7225 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
7226 %} | |
7227 ins_pipe(ialu_reg_reg); | |
7228 %} | |
7229 | |
7230 // Immediate Addition | |
7231 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7232 match(Set dst (AddI src1 src2)); | |
7233 | |
7234 size(4); | |
7235 format %{ "ADD $src1,$src2,$dst" %} | |
7236 opcode(Assembler::add_op3, Assembler::arith_op); | |
7237 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7238 ins_pipe(ialu_reg_imm); | |
7239 %} | |
7240 | |
7241 // Pointer Register Addition | |
7242 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
7243 match(Set dst (AddP src1 src2)); | |
7244 | |
7245 size(4); | |
7246 format %{ "ADD $src1,$src2,$dst" %} | |
7247 opcode(Assembler::add_op3, Assembler::arith_op); | |
7248 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7249 ins_pipe(ialu_reg_reg); | |
7250 %} | |
7251 | |
7252 // Pointer Immediate Addition | |
7253 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
7254 match(Set dst (AddP src1 src2)); | |
7255 | |
7256 size(4); | |
7257 format %{ "ADD $src1,$src2,$dst" %} | |
7258 opcode(Assembler::add_op3, Assembler::arith_op); | |
7259 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7260 ins_pipe(ialu_reg_imm); | |
7261 %} | |
7262 | |
7263 // Long Addition | |
7264 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7265 match(Set dst (AddL src1 src2)); | |
7266 | |
7267 size(4); | |
7268 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
7269 opcode(Assembler::add_op3, Assembler::arith_op); | |
7270 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7271 ins_pipe(ialu_reg_reg); | |
7272 %} | |
7273 | |
7274 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7275 match(Set dst (AddL src1 con)); | |
7276 | |
7277 size(4); | |
7278 format %{ "ADD $src1,$con,$dst" %} | |
7279 opcode(Assembler::add_op3, Assembler::arith_op); | |
7280 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7281 ins_pipe(ialu_reg_imm); | |
7282 %} | |
7283 | |
7284 //----------Conditional_store-------------------------------------------------- | |
7285 // Conditional-store of the updated heap-top. | |
7286 // Used during allocation of the shared heap. | |
7287 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
7288 | |
7289 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
7290 instruct loadPLocked(iRegP dst, memory mem) %{ | |
7291 match(Set dst (LoadPLocked mem)); | |
7292 ins_cost(MEMORY_REF_COST); | |
7293 | |
7294 #ifndef _LP64 | |
7295 size(4); | |
7296 format %{ "LDUW $mem,$dst\t! ptr" %} | |
7297 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
7298 #else | |
7299 format %{ "LDX $mem,$dst\t! ptr" %} | |
7300 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
7301 #endif | |
7302 ins_encode( form3_mem_reg( mem, dst ) ); | |
7303 ins_pipe(iload_mem); | |
7304 %} | |
7305 | |
7306 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
7307 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
7308 effect( KILL newval ); | |
7309 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
7310 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
7311 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
7312 ins_pipe( long_memory_op ); | |
7313 %} | |
7314 | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7315 // Conditional-store of an int value. |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7316 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7317 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7318 effect( KILL newval ); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7319 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7320 "CMP $oldval,$newval\t\t! See if we made progress" %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7321 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 7322 ins_pipe( long_memory_op ); |
7323 %} | |
7324 | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7325 // Conditional-store of a long value. |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7326 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7327 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7328 effect( KILL newval ); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7329 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7330 "CMP $oldval,$newval\t\t! See if we made progress" %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7331 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 7332 ins_pipe( long_memory_op ); |
7333 %} | |
7334 | |
7335 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
7336 | |
7337 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7338 predicate(VM_Version::supports_cx8()); |
0 | 7339 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
7340 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7341 format %{ | |
7342 "MOV $newval,O7\n\t" | |
7343 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7344 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7345 "MOV 1,$res\n\t" | |
7346 "MOVne xcc,R_G0,$res" | |
7347 %} | |
7348 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
7349 enc_lflags_ne_to_boolean(res) ); | |
7350 ins_pipe( long_memory_op ); | |
7351 %} | |
7352 | |
7353 | |
7354 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
7355 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
7356 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7357 format %{ | |
7358 "MOV $newval,O7\n\t" | |
7359 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7360 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7361 "MOV 1,$res\n\t" | |
7362 "MOVne icc,R_G0,$res" | |
7363 %} | |
7364 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
7365 enc_iflags_ne_to_boolean(res) ); | |
7366 ins_pipe( long_memory_op ); | |
7367 %} | |
7368 | |
7369 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7370 #ifdef _LP64 |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7371 predicate(VM_Version::supports_cx8()); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7372 #endif |
0 | 7373 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
7374 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7375 format %{ | |
7376 "MOV $newval,O7\n\t" | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7377 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
0 | 7378 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
7379 "MOV 1,$res\n\t" | |
7380 "MOVne xcc,R_G0,$res" | |
7381 %} | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7382 #ifdef _LP64 |
0 | 7383 ins_encode( enc_casx(mem_ptr, oldval, newval), |
7384 enc_lflags_ne_to_boolean(res) ); | |
7385 #else | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7386 ins_encode( enc_casi(mem_ptr, oldval, newval), |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7387 enc_iflags_ne_to_boolean(res) ); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7388 #endif |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7389 ins_pipe( long_memory_op ); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7390 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7391 |
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7392 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
7393 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7394 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
0 | 7395 format %{ |
7396 "MOV $newval,O7\n\t" | |
7397 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7398 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7399 "MOV 1,$res\n\t" | |
7400 "MOVne icc,R_G0,$res" | |
7401 %} | |
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7402 ins_encode( enc_casi(mem_ptr, oldval, newval), |
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7403 enc_iflags_ne_to_boolean(res) ); |
0 | 7404 ins_pipe( long_memory_op ); |
7405 %} | |
7406 | |
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7407 instruct xchgI( memory mem, iRegI newval) %{ |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7408 match(Set newval (GetAndSetI mem newval)); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7409 format %{ "SWAP [$mem],$newval" %} |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7410 size(4); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7411 ins_encode %{ |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7412 __ swap($mem$$Address, $newval$$Register); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7413 %} |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7414 ins_pipe( long_memory_op ); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7415 %} |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7416 |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7417 #ifndef _LP64 |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7418 instruct xchgP( memory mem, iRegP newval) %{ |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7419 match(Set newval (GetAndSetP mem newval)); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7420 format %{ "SWAP [$mem],$newval" %} |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7421 size(4); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7422 ins_encode %{ |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7423 __ swap($mem$$Address, $newval$$Register); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7424 %} |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7425 ins_pipe( long_memory_op ); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7426 %} |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7427 #endif |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7428 |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7429 instruct xchgN( memory mem, iRegN newval) %{ |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7430 match(Set newval (GetAndSetN mem newval)); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7431 format %{ "SWAP [$mem],$newval" %} |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7432 size(4); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7433 ins_encode %{ |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7434 __ swap($mem$$Address, $newval$$Register); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7435 %} |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7436 ins_pipe( long_memory_op ); |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7437 %} |
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7438 |
0 | 7439 //--------------------- |
7440 // Subtraction Instructions | |
7441 // Register Subtraction | |
7442 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7443 match(Set dst (SubI src1 src2)); | |
7444 | |
7445 size(4); | |
7446 format %{ "SUB $src1,$src2,$dst" %} | |
7447 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7448 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7449 ins_pipe(ialu_reg_reg); | |
7450 %} | |
7451 | |
7452 // Immediate Subtraction | |
7453 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7454 match(Set dst (SubI src1 src2)); | |
7455 | |
7456 size(4); | |
7457 format %{ "SUB $src1,$src2,$dst" %} | |
7458 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7459 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7460 ins_pipe(ialu_reg_imm); | |
7461 %} | |
7462 | |
7463 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
7464 match(Set dst (SubI zero src2)); | |
7465 | |
7466 size(4); | |
7467 format %{ "NEG $src2,$dst" %} | |
7468 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7469 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
7470 ins_pipe(ialu_zero_reg); | |
7471 %} | |
7472 | |
7473 // Long subtraction | |
7474 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7475 match(Set dst (SubL src1 src2)); | |
7476 | |
7477 size(4); | |
7478 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7479 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7480 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7481 ins_pipe(ialu_reg_reg); | |
7482 %} | |
7483 | |
7484 // Immediate Subtraction | |
7485 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7486 match(Set dst (SubL src1 con)); | |
7487 | |
7488 size(4); | |
7489 format %{ "SUB $src1,$con,$dst\t! long" %} | |
7490 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7491 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7492 ins_pipe(ialu_reg_imm); | |
7493 %} | |
7494 | |
7495 // Long negation | |
7496 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
7497 match(Set dst (SubL zero src2)); | |
7498 | |
7499 size(4); | |
7500 format %{ "NEG $src2,$dst\t! long" %} | |
7501 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7502 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
7503 ins_pipe(ialu_zero_reg); | |
7504 %} | |
7505 | |
7506 // Multiplication Instructions | |
7507 // Integer Multiplication | |
7508 // Register Multiplication | |
7509 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7510 match(Set dst (MulI src1 src2)); | |
7511 | |
7512 size(4); | |
7513 format %{ "MULX $src1,$src2,$dst" %} | |
7514 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7515 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7516 ins_pipe(imul_reg_reg); | |
7517 %} | |
7518 | |
7519 // Immediate Multiplication | |
7520 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7521 match(Set dst (MulI src1 src2)); | |
7522 | |
7523 size(4); | |
7524 format %{ "MULX $src1,$src2,$dst" %} | |
7525 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7526 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7527 ins_pipe(imul_reg_imm); | |
7528 %} | |
7529 | |
7530 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7531 match(Set dst (MulL src1 src2)); | |
7532 ins_cost(DEFAULT_COST * 5); | |
7533 size(4); | |
7534 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7535 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7536 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7537 ins_pipe(mulL_reg_reg); | |
7538 %} | |
7539 | |
7540 // Immediate Multiplication | |
7541 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7542 match(Set dst (MulL src1 src2)); | |
7543 ins_cost(DEFAULT_COST * 5); | |
7544 size(4); | |
7545 format %{ "MULX $src1,$src2,$dst" %} | |
7546 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7547 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7548 ins_pipe(mulL_reg_imm); | |
7549 %} | |
7550 | |
7551 // Integer Division | |
7552 // Register Division | |
7553 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
7554 match(Set dst (DivI src1 src2)); | |
7555 ins_cost((2+71)*DEFAULT_COST); | |
7556 | |
7557 format %{ "SRA $src2,0,$src2\n\t" | |
7558 "SRA $src1,0,$src1\n\t" | |
7559 "SDIVX $src1,$src2,$dst" %} | |
7560 ins_encode( idiv_reg( src1, src2, dst ) ); | |
7561 ins_pipe(sdiv_reg_reg); | |
7562 %} | |
7563 | |
7564 // Immediate Division | |
7565 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
7566 match(Set dst (DivI src1 src2)); | |
7567 ins_cost((2+71)*DEFAULT_COST); | |
7568 | |
7569 format %{ "SRA $src1,0,$src1\n\t" | |
7570 "SDIVX $src1,$src2,$dst" %} | |
7571 ins_encode( idiv_imm( src1, src2, dst ) ); | |
7572 ins_pipe(sdiv_reg_imm); | |
7573 %} | |
7574 | |
7575 //----------Div-By-10-Expansion------------------------------------------------ | |
7576 // Extract hi bits of a 32x32->64 bit multiply. | |
7577 // Expand rule only, not matched | |
7578 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
7579 effect( DEF dst, USE src1, USE src2 ); | |
7580 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
7581 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
7582 ins_encode( enc_mul_hi(dst,src1,src2)); | |
7583 ins_pipe(sdiv_reg_reg); | |
7584 %} | |
7585 | |
605 | 7586 // Magic constant, reciprocal of 10 |
0 | 7587 instruct loadConI_x66666667(iRegIsafe dst) %{ |
7588 effect( DEF dst ); | |
7589 | |
7590 size(8); | |
7591 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
7592 ins_encode( Set32(0x66666667, dst) ); | |
7593 ins_pipe(ialu_hi_lo_reg); | |
7594 %} | |
7595 | |
605 | 7596 // Register Shift Right Arithmetic Long by 32-63 |
0 | 7597 instruct sra_31( iRegI dst, iRegI src ) %{ |
7598 effect( DEF dst, USE src ); | |
7599 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
7600 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
7601 ins_pipe(ialu_reg_reg); | |
7602 %} | |
7603 | |
7604 // Arithmetic Shift Right by 8-bit immediate | |
7605 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
7606 effect( DEF dst, USE src ); | |
7607 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
7608 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7609 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
7610 ins_pipe(ialu_reg_imm); | |
7611 %} | |
7612 | |
7613 // Integer DIV with 10 | |
7614 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
7615 match(Set dst (DivI src div)); | |
7616 ins_cost((6+6)*DEFAULT_COST); | |
7617 expand %{ | |
7618 iRegIsafe tmp1; // Killed temps; | |
7619 iRegIsafe tmp2; // Killed temps; | |
7620 iRegI tmp3; // Killed temps; | |
7621 iRegI tmp4; // Killed temps; | |
7622 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
7623 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
7624 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
7625 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
7626 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
7627 %} | |
7628 %} | |
7629 | |
7630 // Register Long Division | |
7631 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7632 match(Set dst (DivL src1 src2)); | |
7633 ins_cost(DEFAULT_COST*71); | |
7634 size(4); | |
7635 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7636 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7637 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7638 ins_pipe(divL_reg_reg); | |
7639 %} | |
7640 | |
7641 // Register Long Division | |
7642 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7643 match(Set dst (DivL src1 src2)); | |
7644 ins_cost(DEFAULT_COST*71); | |
7645 size(4); | |
7646 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7647 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7648 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7649 ins_pipe(divL_reg_imm); | |
7650 %} | |
7651 | |
7652 // Integer Remainder | |
7653 // Register Remainder | |
7654 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
7655 match(Set dst (ModI src1 src2)); | |
7656 effect( KILL ccr, KILL temp); | |
7657 | |
7658 format %{ "SREM $src1,$src2,$dst" %} | |
7659 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
7660 ins_pipe(sdiv_reg_reg); | |
7661 %} | |
7662 | |
7663 // Immediate Remainder | |
7664 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
7665 match(Set dst (ModI src1 src2)); | |
7666 effect( KILL ccr, KILL temp); | |
7667 | |
7668 format %{ "SREM $src1,$src2,$dst" %} | |
7669 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
7670 ins_pipe(sdiv_reg_imm); | |
7671 %} | |
7672 | |
7673 // Register Long Remainder | |
7674 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7675 effect(DEF dst, USE src1, USE src2); | |
7676 size(4); | |
7677 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7678 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7679 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7680 ins_pipe(divL_reg_reg); | |
7681 %} | |
7682 | |
7683 // Register Long Division | |
7684 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7685 effect(DEF dst, USE src1, USE src2); | |
7686 size(4); | |
7687 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7688 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7689 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7690 ins_pipe(divL_reg_imm); | |
7691 %} | |
7692 | |
7693 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7694 effect(DEF dst, USE src1, USE src2); | |
7695 size(4); | |
7696 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7697 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7698 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7699 ins_pipe(mulL_reg_reg); | |
7700 %} | |
7701 | |
7702 // Immediate Multiplication | |
7703 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7704 effect(DEF dst, USE src1, USE src2); | |
7705 size(4); | |
7706 format %{ "MULX $src1,$src2,$dst" %} | |
7707 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7708 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7709 ins_pipe(mulL_reg_imm); | |
7710 %} | |
7711 | |
7712 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7713 effect(DEF dst, USE src1, USE src2); | |
7714 size(4); | |
7715 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7716 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7717 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7718 ins_pipe(ialu_reg_reg); | |
7719 %} | |
7720 | |
7721 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
7722 effect(DEF dst, USE src1, USE src2); | |
7723 size(4); | |
7724 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7725 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7726 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7727 ins_pipe(ialu_reg_reg); | |
7728 %} | |
7729 | |
7730 // Register Long Remainder | |
7731 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7732 match(Set dst (ModL src1 src2)); | |
7733 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7734 expand %{ | |
7735 iRegL tmp1; | |
7736 iRegL tmp2; | |
7737 divL_reg_reg_1(tmp1, src1, src2); | |
7738 mulL_reg_reg_1(tmp2, tmp1, src2); | |
7739 subL_reg_reg_1(dst, src1, tmp2); | |
7740 %} | |
7741 %} | |
7742 | |
7743 // Register Long Remainder | |
7744 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7745 match(Set dst (ModL src1 src2)); | |
7746 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7747 expand %{ | |
7748 iRegL tmp1; | |
7749 iRegL tmp2; | |
7750 divL_reg_imm13_1(tmp1, src1, src2); | |
7751 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
7752 subL_reg_reg_2 (dst, src1, tmp2); | |
7753 %} | |
7754 %} | |
7755 | |
7756 // Integer Shift Instructions | |
7757 // Register Shift Left | |
7758 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7759 match(Set dst (LShiftI src1 src2)); | |
7760 | |
7761 size(4); | |
7762 format %{ "SLL $src1,$src2,$dst" %} | |
7763 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7764 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7765 ins_pipe(ialu_reg_reg); | |
7766 %} | |
7767 | |
7768 // Register Shift Left Immediate | |
7769 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7770 match(Set dst (LShiftI src1 src2)); | |
7771 | |
7772 size(4); | |
7773 format %{ "SLL $src1,$src2,$dst" %} | |
7774 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7775 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7776 ins_pipe(ialu_reg_imm); | |
7777 %} | |
7778 | |
7779 // Register Shift Left | |
7780 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7781 match(Set dst (LShiftL src1 src2)); | |
7782 | |
7783 size(4); | |
7784 format %{ "SLLX $src1,$src2,$dst" %} | |
7785 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7786 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7787 ins_pipe(ialu_reg_reg); | |
7788 %} | |
7789 | |
7790 // Register Shift Left Immediate | |
7791 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7792 match(Set dst (LShiftL src1 src2)); | |
7793 | |
7794 size(4); | |
7795 format %{ "SLLX $src1,$src2,$dst" %} | |
7796 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7797 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7798 ins_pipe(ialu_reg_imm); | |
7799 %} | |
7800 | |
7801 // Register Arithmetic Shift Right | |
7802 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7803 match(Set dst (RShiftI src1 src2)); | |
7804 size(4); | |
7805 format %{ "SRA $src1,$src2,$dst" %} | |
7806 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7807 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7808 ins_pipe(ialu_reg_reg); | |
7809 %} | |
7810 | |
7811 // Register Arithmetic Shift Right Immediate | |
7812 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7813 match(Set dst (RShiftI src1 src2)); | |
7814 | |
7815 size(4); | |
7816 format %{ "SRA $src1,$src2,$dst" %} | |
7817 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7818 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7819 ins_pipe(ialu_reg_imm); | |
7820 %} | |
7821 | |
7822 // Register Shift Right Arithmatic Long | |
7823 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7824 match(Set dst (RShiftL src1 src2)); | |
7825 | |
7826 size(4); | |
7827 format %{ "SRAX $src1,$src2,$dst" %} | |
7828 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7829 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7830 ins_pipe(ialu_reg_reg); | |
7831 %} | |
7832 | |
7833 // Register Shift Left Immediate | |
7834 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7835 match(Set dst (RShiftL src1 src2)); | |
7836 | |
7837 size(4); | |
7838 format %{ "SRAX $src1,$src2,$dst" %} | |
7839 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7840 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7841 ins_pipe(ialu_reg_imm); | |
7842 %} | |
7843 | |
7844 // Register Shift Right | |
7845 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7846 match(Set dst (URShiftI src1 src2)); | |
7847 | |
7848 size(4); | |
7849 format %{ "SRL $src1,$src2,$dst" %} | |
7850 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7851 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7852 ins_pipe(ialu_reg_reg); | |
7853 %} | |
7854 | |
7855 // Register Shift Right Immediate | |
7856 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7857 match(Set dst (URShiftI src1 src2)); | |
7858 | |
7859 size(4); | |
7860 format %{ "SRL $src1,$src2,$dst" %} | |
7861 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7862 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7863 ins_pipe(ialu_reg_imm); | |
7864 %} | |
7865 | |
7866 // Register Shift Right | |
7867 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7868 match(Set dst (URShiftL src1 src2)); | |
7869 | |
7870 size(4); | |
7871 format %{ "SRLX $src1,$src2,$dst" %} | |
7872 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7873 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7874 ins_pipe(ialu_reg_reg); | |
7875 %} | |
7876 | |
7877 // Register Shift Right Immediate | |
7878 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7879 match(Set dst (URShiftL src1 src2)); | |
7880 | |
7881 size(4); | |
7882 format %{ "SRLX $src1,$src2,$dst" %} | |
7883 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7884 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7885 ins_pipe(ialu_reg_imm); | |
7886 %} | |
7887 | |
7888 // Register Shift Right Immediate with a CastP2X | |
7889 #ifdef _LP64 | |
7890 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
7891 match(Set dst (URShiftL (CastP2X src1) src2)); | |
7892 size(4); | |
7893 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
7894 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7895 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7896 ins_pipe(ialu_reg_imm); | |
7897 %} | |
7898 #else | |
7899 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
7900 match(Set dst (URShiftI (CastP2X src1) src2)); | |
7901 size(4); | |
7902 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
7903 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7904 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7905 ins_pipe(ialu_reg_imm); | |
7906 %} | |
7907 #endif | |
7908 | |
7909 | |
7910 //----------Floating Point Arithmetic Instructions----------------------------- | |
7911 | |
7912 // Add float single precision | |
7913 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7914 match(Set dst (AddF src1 src2)); | |
7915 | |
7916 size(4); | |
7917 format %{ "FADDS $src1,$src2,$dst" %} | |
7918 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
7919 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7920 ins_pipe(faddF_reg_reg); | |
7921 %} | |
7922 | |
7923 // Add float double precision | |
7924 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7925 match(Set dst (AddD src1 src2)); | |
7926 | |
7927 size(4); | |
7928 format %{ "FADDD $src1,$src2,$dst" %} | |
7929 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
7930 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7931 ins_pipe(faddD_reg_reg); | |
7932 %} | |
7933 | |
7934 // Sub float single precision | |
7935 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7936 match(Set dst (SubF src1 src2)); | |
7937 | |
7938 size(4); | |
7939 format %{ "FSUBS $src1,$src2,$dst" %} | |
7940 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
7941 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7942 ins_pipe(faddF_reg_reg); | |
7943 %} | |
7944 | |
7945 // Sub float double precision | |
7946 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7947 match(Set dst (SubD src1 src2)); | |
7948 | |
7949 size(4); | |
7950 format %{ "FSUBD $src1,$src2,$dst" %} | |
7951 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
7952 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7953 ins_pipe(faddD_reg_reg); | |
7954 %} | |
7955 | |
7956 // Mul float single precision | |
7957 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7958 match(Set dst (MulF src1 src2)); | |
7959 | |
7960 size(4); | |
7961 format %{ "FMULS $src1,$src2,$dst" %} | |
7962 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
7963 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7964 ins_pipe(fmulF_reg_reg); | |
7965 %} | |
7966 | |
7967 // Mul float double precision | |
7968 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7969 match(Set dst (MulD src1 src2)); | |
7970 | |
7971 size(4); | |
7972 format %{ "FMULD $src1,$src2,$dst" %} | |
7973 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
7974 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7975 ins_pipe(fmulD_reg_reg); | |
7976 %} | |
7977 | |
7978 // Div float single precision | |
7979 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7980 match(Set dst (DivF src1 src2)); | |
7981 | |
7982 size(4); | |
7983 format %{ "FDIVS $src1,$src2,$dst" %} | |
7984 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
7985 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7986 ins_pipe(fdivF_reg_reg); | |
7987 %} | |
7988 | |
7989 // Div float double precision | |
7990 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7991 match(Set dst (DivD src1 src2)); | |
7992 | |
7993 size(4); | |
7994 format %{ "FDIVD $src1,$src2,$dst" %} | |
7995 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
7996 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7997 ins_pipe(fdivD_reg_reg); | |
7998 %} | |
7999 | |
8000 // Absolute float double precision | |
8001 instruct absD_reg(regD dst, regD src) %{ | |
8002 match(Set dst (AbsD src)); | |
8003 | |
8004 format %{ "FABSd $src,$dst" %} | |
8005 ins_encode(fabsd(dst, src)); | |
8006 ins_pipe(faddD_reg); | |
8007 %} | |
8008 | |
8009 // Absolute float single precision | |
8010 instruct absF_reg(regF dst, regF src) %{ | |
8011 match(Set dst (AbsF src)); | |
8012 | |
8013 format %{ "FABSs $src,$dst" %} | |
8014 ins_encode(fabss(dst, src)); | |
8015 ins_pipe(faddF_reg); | |
8016 %} | |
8017 | |
8018 instruct negF_reg(regF dst, regF src) %{ | |
8019 match(Set dst (NegF src)); | |
8020 | |
8021 size(4); | |
8022 format %{ "FNEGs $src,$dst" %} | |
8023 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
8024 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
8025 ins_pipe(faddF_reg); | |
8026 %} | |
8027 | |
8028 instruct negD_reg(regD dst, regD src) %{ | |
8029 match(Set dst (NegD src)); | |
8030 | |
8031 format %{ "FNEGd $src,$dst" %} | |
8032 ins_encode(fnegd(dst, src)); | |
8033 ins_pipe(faddD_reg); | |
8034 %} | |
8035 | |
8036 // Sqrt float double precision | |
8037 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
8038 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
8039 | |
8040 size(4); | |
8041 format %{ "FSQRTS $src,$dst" %} | |
8042 ins_encode(fsqrts(dst, src)); | |
8043 ins_pipe(fdivF_reg_reg); | |
8044 %} | |
8045 | |
8046 // Sqrt float double precision | |
8047 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
8048 match(Set dst (SqrtD src)); | |
8049 | |
8050 size(4); | |
8051 format %{ "FSQRTD $src,$dst" %} | |
8052 ins_encode(fsqrtd(dst, src)); | |
8053 ins_pipe(fdivD_reg_reg); | |
8054 %} | |
8055 | |
8056 //----------Logical Instructions----------------------------------------------- | |
8057 // And Instructions | |
8058 // Register And | |
8059 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
8060 match(Set dst (AndI src1 src2)); | |
8061 | |
8062 size(4); | |
8063 format %{ "AND $src1,$src2,$dst" %} | |
8064 opcode(Assembler::and_op3, Assembler::arith_op); | |
8065 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8066 ins_pipe(ialu_reg_reg); | |
8067 %} | |
8068 | |
8069 // Immediate And | |
8070 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
8071 match(Set dst (AndI src1 src2)); | |
8072 | |
8073 size(4); | |
8074 format %{ "AND $src1,$src2,$dst" %} | |
8075 opcode(Assembler::and_op3, Assembler::arith_op); | |
8076 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
8077 ins_pipe(ialu_reg_imm); | |
8078 %} | |
8079 | |
8080 // Register And Long | |
8081 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
8082 match(Set dst (AndL src1 src2)); | |
8083 | |
8084 ins_cost(DEFAULT_COST); | |
8085 size(4); | |
8086 format %{ "AND $src1,$src2,$dst\t! long" %} | |
8087 opcode(Assembler::and_op3, Assembler::arith_op); | |
8088 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8089 ins_pipe(ialu_reg_reg); | |
8090 %} | |
8091 | |
8092 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
8093 match(Set dst (AndL src1 con)); | |
8094 | |
8095 ins_cost(DEFAULT_COST); | |
8096 size(4); | |
8097 format %{ "AND $src1,$con,$dst\t! long" %} | |
8098 opcode(Assembler::and_op3, Assembler::arith_op); | |
8099 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
8100 ins_pipe(ialu_reg_imm); | |
8101 %} | |
8102 | |
8103 // Or Instructions | |
8104 // Register Or | |
8105 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
8106 match(Set dst (OrI src1 src2)); | |
8107 | |
8108 size(4); | |
8109 format %{ "OR $src1,$src2,$dst" %} | |
8110 opcode(Assembler::or_op3, Assembler::arith_op); | |
8111 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8112 ins_pipe(ialu_reg_reg); | |
8113 %} | |
8114 | |
8115 // Immediate Or | |
8116 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
8117 match(Set dst (OrI src1 src2)); | |
8118 | |
8119 size(4); | |
8120 format %{ "OR $src1,$src2,$dst" %} | |
8121 opcode(Assembler::or_op3, Assembler::arith_op); | |
8122 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
8123 ins_pipe(ialu_reg_imm); | |
8124 %} | |
8125 | |
8126 // Register Or Long | |
8127 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
8128 match(Set dst (OrL src1 src2)); | |
8129 | |
8130 ins_cost(DEFAULT_COST); | |
8131 size(4); | |
8132 format %{ "OR $src1,$src2,$dst\t! long" %} | |
8133 opcode(Assembler::or_op3, Assembler::arith_op); | |
8134 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8135 ins_pipe(ialu_reg_reg); | |
8136 %} | |
8137 | |
8138 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
8139 match(Set dst (OrL src1 con)); | |
8140 ins_cost(DEFAULT_COST*2); | |
8141 | |
8142 ins_cost(DEFAULT_COST); | |
8143 size(4); | |
8144 format %{ "OR $src1,$con,$dst\t! long" %} | |
8145 opcode(Assembler::or_op3, Assembler::arith_op); | |
8146 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
8147 ins_pipe(ialu_reg_imm); | |
8148 %} | |
8149 | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8150 #ifndef _LP64 |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8151 |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8152 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8153 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8154 match(Set dst (OrI src1 (CastP2X src2))); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8155 |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8156 size(4); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8157 format %{ "OR $src1,$src2,$dst" %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8158 opcode(Assembler::or_op3, Assembler::arith_op); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8159 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8160 ins_pipe(ialu_reg_reg); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8161 %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8162 |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8163 #else |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8164 |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8165 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8166 match(Set dst (OrL src1 (CastP2X src2))); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8167 |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8168 ins_cost(DEFAULT_COST); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8169 size(4); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8170 format %{ "OR $src1,$src2,$dst\t! long" %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8171 opcode(Assembler::or_op3, Assembler::arith_op); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8172 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8173 ins_pipe(ialu_reg_reg); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8174 %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8175 |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8176 #endif |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8177 |
0 | 8178 // Xor Instructions |
8179 // Register Xor | |
8180 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
8181 match(Set dst (XorI src1 src2)); | |
8182 | |
8183 size(4); | |
8184 format %{ "XOR $src1,$src2,$dst" %} | |
8185 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8186 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8187 ins_pipe(ialu_reg_reg); | |
8188 %} | |
8189 | |
8190 // Immediate Xor | |
8191 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
8192 match(Set dst (XorI src1 src2)); | |
8193 | |
8194 size(4); | |
8195 format %{ "XOR $src1,$src2,$dst" %} | |
8196 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8197 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
8198 ins_pipe(ialu_reg_imm); | |
8199 %} | |
8200 | |
8201 // Register Xor Long | |
8202 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
8203 match(Set dst (XorL src1 src2)); | |
8204 | |
8205 ins_cost(DEFAULT_COST); | |
8206 size(4); | |
8207 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
8208 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8209 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
8210 ins_pipe(ialu_reg_reg); | |
8211 %} | |
8212 | |
8213 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
8214 match(Set dst (XorL src1 con)); | |
8215 | |
8216 ins_cost(DEFAULT_COST); | |
8217 size(4); | |
8218 format %{ "XOR $src1,$con,$dst\t! long" %} | |
8219 opcode(Assembler::xor_op3, Assembler::arith_op); | |
8220 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
8221 ins_pipe(ialu_reg_imm); | |
8222 %} | |
8223 | |
8224 //----------Convert to Boolean------------------------------------------------- | |
8225 // Nice hack for 32-bit tests but doesn't work for | |
8226 // 64-bit pointers. | |
8227 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
8228 match(Set dst (Conv2B src)); | |
8229 effect( KILL ccr ); | |
8230 ins_cost(DEFAULT_COST*2); | |
8231 format %{ "CMP R_G0,$src\n\t" | |
8232 "ADDX R_G0,0,$dst" %} | |
8233 ins_encode( enc_to_bool( src, dst ) ); | |
8234 ins_pipe(ialu_reg_ialu); | |
8235 %} | |
8236 | |
8237 #ifndef _LP64 | |
8238 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
8239 match(Set dst (Conv2B src)); | |
8240 effect( KILL ccr ); | |
8241 ins_cost(DEFAULT_COST*2); | |
8242 format %{ "CMP R_G0,$src\n\t" | |
8243 "ADDX R_G0,0,$dst" %} | |
8244 ins_encode( enc_to_bool( src, dst ) ); | |
8245 ins_pipe(ialu_reg_ialu); | |
8246 %} | |
8247 #else | |
8248 instruct convP2B( iRegI dst, iRegP src ) %{ | |
8249 match(Set dst (Conv2B src)); | |
8250 ins_cost(DEFAULT_COST*2); | |
8251 format %{ "MOV $src,$dst\n\t" | |
8252 "MOVRNZ $src,1,$dst" %} | |
8253 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
8254 ins_pipe(ialu_clr_and_mover); | |
8255 %} | |
8256 #endif | |
8257 | |
2254
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8258 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8259 match(Set dst (CmpLTMask src zero)); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8260 effect(KILL ccr); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8261 size(4); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8262 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8263 ins_encode %{ |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8264 __ sra($src$$Register, 31, $dst$$Register); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8265 %} |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8266 ins_pipe(ialu_reg_imm); |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8267 %} |
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8268 |
0 | 8269 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ |
8270 match(Set dst (CmpLTMask p q)); | |
8271 effect( KILL ccr ); | |
8272 ins_cost(DEFAULT_COST*4); | |
8273 format %{ "CMP $p,$q\n\t" | |
8274 "MOV #0,$dst\n\t" | |
8275 "BLT,a .+8\n\t" | |
8276 "MOV #-1,$dst" %} | |
8277 ins_encode( enc_ltmask(p,q,dst) ); | |
8278 ins_pipe(ialu_reg_reg_ialu); | |
8279 %} | |
8280 | |
8281 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
8282 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
8283 effect(KILL ccr, TEMP tmp); | |
8284 ins_cost(DEFAULT_COST*3); | |
8285 | |
8286 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
8287 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
2254
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
parents:
2121
diff
changeset
|
8288 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} |
9154 | 8289 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp)); |
8290 ins_pipe(cadd_cmpltmask); | |
8291 %} | |
8292 | |
8293 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{ | |
8294 match(Set p (AndI (CmpLTMask p q) y)); | |
8295 effect(KILL ccr); | |
8296 ins_cost(DEFAULT_COST*3); | |
8297 | |
8298 format %{ "CMP $p,$q\n\t" | |
8299 "MOV $y,$p\n\t" | |
8300 "MOVge G0,$p" %} | |
8301 ins_encode %{ | |
8302 __ cmp($p$$Register, $q$$Register); | |
8303 __ mov($y$$Register, $p$$Register); | |
8304 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register); | |
8305 %} | |
8306 ins_pipe(ialu_reg_reg_ialu); | |
8307 %} | |
3804 | 8308 |
8309 //----------------------------------------------------------------- | |
8310 // Direct raw moves between float and general registers using VIS3. | |
8311 | |
8312 // ins_pipe(faddF_reg); | |
8313 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ | |
8314 predicate(UseVIS >= 3); | |
8315 match(Set dst (MoveF2I src)); | |
8316 | |
8317 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} | |
8318 ins_encode %{ | |
8319 __ movstouw($src$$FloatRegister, $dst$$Register); | |
8320 %} | |
8321 ins_pipe(ialu_reg_reg); | |
8322 %} | |
8323 | |
8324 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ | |
8325 predicate(UseVIS >= 3); | |
8326 match(Set dst (MoveI2F src)); | |
8327 | |
8328 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} | |
8329 ins_encode %{ | |
8330 __ movwtos($src$$Register, $dst$$FloatRegister); | |
8331 %} | |
0 | 8332 ins_pipe(ialu_reg_reg); |
8333 %} | |
8334 | |
3804 | 8335 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ |
8336 predicate(UseVIS >= 3); | |
8337 match(Set dst (MoveD2L src)); | |
8338 | |
8339 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} | |
8340 ins_encode %{ | |
8341 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); | |
8342 %} | |
0 | 8343 ins_pipe(ialu_reg_reg); |
8344 %} | |
8345 | |
3804 | 8346 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ |
8347 predicate(UseVIS >= 3); | |
8348 match(Set dst (MoveL2D src)); | |
8349 | |
8350 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} | |
8351 ins_encode %{ | |
8352 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); | |
8353 %} | |
0 | 8354 ins_pipe(ialu_reg_reg); |
8355 %} | |
8356 | |
3804 | 8357 |
8358 // Raw moves between float and general registers using stack. | |
8359 | |
0 | 8360 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ |
8361 match(Set dst (MoveF2I src)); | |
8362 effect(DEF dst, USE src); | |
8363 ins_cost(MEMORY_REF_COST); | |
8364 | |
8365 size(4); | |
8366 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
8367 opcode(Assembler::lduw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8368 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8369 ins_pipe(iload_mem); |
8370 %} | |
8371 | |
8372 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
8373 match(Set dst (MoveI2F src)); | |
8374 effect(DEF dst, USE src); | |
8375 ins_cost(MEMORY_REF_COST); | |
8376 | |
8377 size(4); | |
8378 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
8379 opcode(Assembler::ldf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8380 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8381 ins_pipe(floadF_stk); |
8382 %} | |
8383 | |
8384 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
8385 match(Set dst (MoveD2L src)); | |
8386 effect(DEF dst, USE src); | |
8387 ins_cost(MEMORY_REF_COST); | |
8388 | |
8389 size(4); | |
8390 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
8391 opcode(Assembler::ldx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8392 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8393 ins_pipe(iload_mem); |
8394 %} | |
8395 | |
8396 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
8397 match(Set dst (MoveL2D src)); | |
8398 effect(DEF dst, USE src); | |
8399 ins_cost(MEMORY_REF_COST); | |
8400 | |
8401 size(4); | |
8402 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
8403 opcode(Assembler::lddf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8404 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8405 ins_pipe(floadD_stk); |
8406 %} | |
8407 | |
8408 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
8409 match(Set dst (MoveF2I src)); | |
8410 effect(DEF dst, USE src); | |
8411 ins_cost(MEMORY_REF_COST); | |
8412 | |
8413 size(4); | |
3804 | 8414 format %{ "STF $src,$dst\t! MoveF2I" %} |
0 | 8415 opcode(Assembler::stf_op3); |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8416 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8417 ins_pipe(fstoreF_stk_reg); |
8418 %} | |
8419 | |
8420 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
8421 match(Set dst (MoveI2F src)); | |
8422 effect(DEF dst, USE src); | |
8423 ins_cost(MEMORY_REF_COST); | |
8424 | |
8425 size(4); | |
3804 | 8426 format %{ "STW $src,$dst\t! MoveI2F" %} |
0 | 8427 opcode(Assembler::stw_op3); |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8428 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8429 ins_pipe(istore_mem_reg); |
8430 %} | |
8431 | |
8432 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
8433 match(Set dst (MoveD2L src)); | |
8434 effect(DEF dst, USE src); | |
8435 ins_cost(MEMORY_REF_COST); | |
8436 | |
8437 size(4); | |
3804 | 8438 format %{ "STDF $src,$dst\t! MoveD2L" %} |
0 | 8439 opcode(Assembler::stdf_op3); |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8440 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8441 ins_pipe(fstoreD_stk_reg); |
8442 %} | |
8443 | |
8444 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
8445 match(Set dst (MoveL2D src)); | |
8446 effect(DEF dst, USE src); | |
8447 ins_cost(MEMORY_REF_COST); | |
8448 | |
8449 size(4); | |
3804 | 8450 format %{ "STX $src,$dst\t! MoveL2D" %} |
0 | 8451 opcode(Assembler::stx_op3); |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8452 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8453 ins_pipe(istore_mem_reg); |
8454 %} | |
8455 | |
8456 | |
3804 | 8457 //----------Arithmetic Conversion Instructions--------------------------------- |
8458 // The conversions operations are all Alpha sorted. Please keep it that way! | |
8459 | |
8460 instruct convD2F_reg(regF dst, regD src) %{ | |
8461 match(Set dst (ConvD2F src)); | |
8462 size(4); | |
8463 format %{ "FDTOS $src,$dst" %} | |
8464 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
8465 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
8466 ins_pipe(fcvtD2F); | |
8467 %} | |
8468 | |
8469 | |
8470 // Convert a double to an int in a float register. | |
8471 // If the double is a NAN, stuff a zero in instead. | |
8472 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
8473 effect(DEF dst, USE src, KILL fcc0); | |
8474 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
8475 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8476 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
8477 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
8478 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
8479 "skip:" %} | |
8480 ins_encode(form_d2i_helper(src,dst)); | |
8481 ins_pipe(fcvtD2I); | |
8482 %} | |
8483 | |
8484 instruct convD2I_stk(stackSlotI dst, regD src) %{ | |
8485 match(Set dst (ConvD2I src)); | |
8486 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8487 expand %{ | |
8488 regF tmp; | |
8489 convD2I_helper(tmp, src); | |
8490 regF_to_stkI(dst, tmp); | |
8491 %} | |
8492 %} | |
8493 | |
8494 instruct convD2I_reg(iRegI dst, regD src) %{ | |
8495 predicate(UseVIS >= 3); | |
8496 match(Set dst (ConvD2I src)); | |
8497 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
8498 expand %{ | |
8499 regF tmp; | |
8500 convD2I_helper(tmp, src); | |
8501 MoveF2I_reg_reg(dst, tmp); | |
8502 %} | |
8503 %} | |
8504 | |
8505 | |
8506 // Convert a double to a long in a double register. | |
8507 // If the double is a NAN, stuff a zero in instead. | |
8508 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
8509 effect(DEF dst, USE src, KILL fcc0); | |
8510 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
8511 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8512 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
8513 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
8514 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
8515 "skip:" %} | |
8516 ins_encode(form_d2l_helper(src,dst)); | |
8517 ins_pipe(fcvtD2L); | |
8518 %} | |
8519 | |
8520 instruct convD2L_stk(stackSlotL dst, regD src) %{ | |
8521 match(Set dst (ConvD2L src)); | |
8522 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8523 expand %{ | |
8524 regD tmp; | |
8525 convD2L_helper(tmp, src); | |
8526 regD_to_stkL(dst, tmp); | |
8527 %} | |
8528 %} | |
8529 | |
8530 instruct convD2L_reg(iRegL dst, regD src) %{ | |
8531 predicate(UseVIS >= 3); | |
8532 match(Set dst (ConvD2L src)); | |
8533 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
8534 expand %{ | |
8535 regD tmp; | |
8536 convD2L_helper(tmp, src); | |
8537 MoveD2L_reg_reg(dst, tmp); | |
8538 %} | |
8539 %} | |
8540 | |
8541 | |
8542 instruct convF2D_reg(regD dst, regF src) %{ | |
8543 match(Set dst (ConvF2D src)); | |
8544 format %{ "FSTOD $src,$dst" %} | |
8545 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
8546 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
8547 ins_pipe(fcvtF2D); | |
8548 %} | |
8549 | |
8550 | |
8551 // Convert a float to an int in a float register. | |
8552 // If the float is a NAN, stuff a zero in instead. | |
8553 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
8554 effect(DEF dst, USE src, KILL fcc0); | |
8555 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
8556 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8557 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
8558 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
8559 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
8560 "skip:" %} | |
8561 ins_encode(form_f2i_helper(src,dst)); | |
8562 ins_pipe(fcvtF2I); | |
8563 %} | |
8564 | |
8565 instruct convF2I_stk(stackSlotI dst, regF src) %{ | |
8566 match(Set dst (ConvF2I src)); | |
8567 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8568 expand %{ | |
8569 regF tmp; | |
8570 convF2I_helper(tmp, src); | |
8571 regF_to_stkI(dst, tmp); | |
8572 %} | |
8573 %} | |
8574 | |
8575 instruct convF2I_reg(iRegI dst, regF src) %{ | |
8576 predicate(UseVIS >= 3); | |
8577 match(Set dst (ConvF2I src)); | |
8578 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
8579 expand %{ | |
8580 regF tmp; | |
8581 convF2I_helper(tmp, src); | |
8582 MoveF2I_reg_reg(dst, tmp); | |
8583 %} | |
8584 %} | |
8585 | |
8586 | |
8587 // Convert a float to a long in a float register. | |
8588 // If the float is a NAN, stuff a zero in instead. | |
8589 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
8590 effect(DEF dst, USE src, KILL fcc0); | |
8591 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
8592 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8593 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
8594 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
8595 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
8596 "skip:" %} | |
8597 ins_encode(form_f2l_helper(src,dst)); | |
8598 ins_pipe(fcvtF2L); | |
8599 %} | |
8600 | |
8601 instruct convF2L_stk(stackSlotL dst, regF src) %{ | |
8602 match(Set dst (ConvF2L src)); | |
8603 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8604 expand %{ | |
8605 regD tmp; | |
8606 convF2L_helper(tmp, src); | |
8607 regD_to_stkL(dst, tmp); | |
8608 %} | |
8609 %} | |
8610 | |
8611 instruct convF2L_reg(iRegL dst, regF src) %{ | |
8612 predicate(UseVIS >= 3); | |
8613 match(Set dst (ConvF2L src)); | |
8614 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
8615 expand %{ | |
8616 regD tmp; | |
8617 convF2L_helper(tmp, src); | |
8618 MoveD2L_reg_reg(dst, tmp); | |
8619 %} | |
8620 %} | |
8621 | |
8622 | |
8623 instruct convI2D_helper(regD dst, regF tmp) %{ | |
8624 effect(USE tmp, DEF dst); | |
8625 format %{ "FITOD $tmp,$dst" %} | |
8626 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
8627 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
8628 ins_pipe(fcvtI2D); | |
8629 %} | |
8630 | |
8631 instruct convI2D_stk(stackSlotI src, regD dst) %{ | |
8632 match(Set dst (ConvI2D src)); | |
8633 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8634 expand %{ | |
8635 regF tmp; | |
8636 stkI_to_regF(tmp, src); | |
8637 convI2D_helper(dst, tmp); | |
8638 %} | |
8639 %} | |
8640 | |
8641 instruct convI2D_reg(regD_low dst, iRegI src) %{ | |
8642 predicate(UseVIS >= 3); | |
8643 match(Set dst (ConvI2D src)); | |
8644 expand %{ | |
8645 regF tmp; | |
8646 MoveI2F_reg_reg(tmp, src); | |
8647 convI2D_helper(dst, tmp); | |
8648 %} | |
8649 %} | |
8650 | |
8651 instruct convI2D_mem(regD_low dst, memory mem) %{ | |
8652 match(Set dst (ConvI2D (LoadI mem))); | |
8653 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8654 size(8); | |
8655 format %{ "LDF $mem,$dst\n\t" | |
8656 "FITOD $dst,$dst" %} | |
8657 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
8658 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
8659 ins_pipe(floadF_mem); | |
8660 %} | |
8661 | |
8662 | |
8663 instruct convI2F_helper(regF dst, regF tmp) %{ | |
8664 effect(DEF dst, USE tmp); | |
8665 format %{ "FITOS $tmp,$dst" %} | |
8666 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
8667 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
8668 ins_pipe(fcvtI2F); | |
8669 %} | |
8670 | |
8671 instruct convI2F_stk(regF dst, stackSlotI src) %{ | |
8672 match(Set dst (ConvI2F src)); | |
8673 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8674 expand %{ | |
8675 regF tmp; | |
8676 stkI_to_regF(tmp,src); | |
8677 convI2F_helper(dst, tmp); | |
8678 %} | |
8679 %} | |
8680 | |
8681 instruct convI2F_reg(regF dst, iRegI src) %{ | |
8682 predicate(UseVIS >= 3); | |
8683 match(Set dst (ConvI2F src)); | |
8684 ins_cost(DEFAULT_COST); | |
8685 expand %{ | |
8686 regF tmp; | |
8687 MoveI2F_reg_reg(tmp, src); | |
8688 convI2F_helper(dst, tmp); | |
8689 %} | |
8690 %} | |
8691 | |
8692 instruct convI2F_mem( regF dst, memory mem ) %{ | |
8693 match(Set dst (ConvI2F (LoadI mem))); | |
8694 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8695 size(8); | |
8696 format %{ "LDF $mem,$dst\n\t" | |
8697 "FITOS $dst,$dst" %} | |
8698 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
8699 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
8700 ins_pipe(floadF_mem); | |
8701 %} | |
8702 | |
8703 | |
8704 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
8705 match(Set dst (ConvI2L src)); | |
8706 size(4); | |
8707 format %{ "SRA $src,0,$dst\t! int->long" %} | |
8708 opcode(Assembler::sra_op3, Assembler::arith_op); | |
8709 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8710 ins_pipe(ialu_reg_reg); | |
8711 %} | |
8712 | |
8713 // Zero-extend convert int to long | |
8714 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
8715 match(Set dst (AndL (ConvI2L src) mask) ); | |
8716 size(4); | |
8717 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
8718 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8719 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8720 ins_pipe(ialu_reg_reg); | |
8721 %} | |
8722 | |
8723 // Zero-extend long | |
8724 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
8725 match(Set dst (AndL src mask) ); | |
8726 size(4); | |
8727 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
8728 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8729 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8730 ins_pipe(ialu_reg_reg); | |
8731 %} | |
8732 | |
8733 | |
0 | 8734 //----------- |
8735 // Long to Double conversion using V8 opcodes. | |
8736 // Still useful because cheetah traps and becomes | |
8737 // amazingly slow for some common numbers. | |
8738 | |
8739 // Magic constant, 0x43300000 | |
8740 instruct loadConI_x43300000(iRegI dst) %{ | |
8741 effect(DEF dst); | |
8742 size(4); | |
8743 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
8744 ins_encode(SetHi22(0x43300000, dst)); | |
8745 ins_pipe(ialu_none); | |
8746 %} | |
8747 | |
8748 // Magic constant, 0x41f00000 | |
8749 instruct loadConI_x41f00000(iRegI dst) %{ | |
8750 effect(DEF dst); | |
8751 size(4); | |
8752 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
8753 ins_encode(SetHi22(0x41f00000, dst)); | |
8754 ins_pipe(ialu_none); | |
8755 %} | |
8756 | |
8757 // Construct a double from two float halves | |
8758 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
8759 effect(DEF dst, USE src1, USE src2); | |
8760 size(8); | |
8761 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
8762 "FMOVS $src2.lo,$dst.lo" %} | |
8763 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
8764 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
8765 ins_pipe(faddD_reg_reg); | |
8766 %} | |
8767 | |
8768 // Convert integer in high half of a double register (in the lower half of | |
8769 // the double register file) to double | |
8770 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
8771 effect(DEF dst, USE src); | |
8772 size(4); | |
8773 format %{ "FITOD $src,$dst" %} | |
8774 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
8775 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
8776 ins_pipe(fcvtLHi2D); | |
8777 %} | |
8778 | |
8779 // Add float double precision | |
8780 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8781 effect(DEF dst, USE src1, USE src2); | |
8782 size(4); | |
8783 format %{ "FADDD $src1,$src2,$dst" %} | |
8784 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
8785 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8786 ins_pipe(faddD_reg_reg); | |
8787 %} | |
8788 | |
8789 // Sub float double precision | |
8790 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8791 effect(DEF dst, USE src1, USE src2); | |
8792 size(4); | |
8793 format %{ "FSUBD $src1,$src2,$dst" %} | |
8794 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
8795 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8796 ins_pipe(faddD_reg_reg); | |
8797 %} | |
8798 | |
8799 // Mul float double precision | |
8800 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8801 effect(DEF dst, USE src1, USE src2); | |
8802 size(4); | |
8803 format %{ "FMULD $src1,$src2,$dst" %} | |
8804 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
8805 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8806 ins_pipe(fmulD_reg_reg); | |
8807 %} | |
8808 | |
8809 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
8810 match(Set dst (ConvL2D src)); | |
8811 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
8812 | |
8813 expand %{ | |
8814 regD_low tmpsrc; | |
8815 iRegI ix43300000; | |
8816 iRegI ix41f00000; | |
8817 stackSlotL lx43300000; | |
8818 stackSlotL lx41f00000; | |
8819 regD_low dx43300000; | |
8820 regD dx41f00000; | |
8821 regD tmp1; | |
8822 regD_low tmp2; | |
8823 regD tmp3; | |
8824 regD tmp4; | |
8825 | |
8826 stkL_to_regD(tmpsrc, src); | |
8827 | |
8828 loadConI_x43300000(ix43300000); | |
8829 loadConI_x41f00000(ix41f00000); | |
8830 regI_to_stkLHi(lx43300000, ix43300000); | |
8831 regI_to_stkLHi(lx41f00000, ix41f00000); | |
8832 stkL_to_regD(dx43300000, lx43300000); | |
8833 stkL_to_regD(dx41f00000, lx41f00000); | |
8834 | |
8835 convI2D_regDHi_regD(tmp1, tmpsrc); | |
8836 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
8837 subD_regD_regD(tmp3, tmp2, dx43300000); | |
8838 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
8839 addD_regD_regD(dst, tmp3, tmp4); | |
8840 %} | |
8841 %} | |
8842 | |
8843 // Long to Double conversion using fast fxtof | |
8844 instruct convL2D_helper(regD dst, regD tmp) %{ | |
8845 effect(DEF dst, USE tmp); | |
8846 size(4); | |
8847 format %{ "FXTOD $tmp,$dst" %} | |
8848 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
8849 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
8850 ins_pipe(fcvtL2D); | |
8851 %} | |
8852 | |
3804 | 8853 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ |
0 | 8854 predicate(VM_Version::has_fast_fxtof()); |
8855 match(Set dst (ConvL2D src)); | |
8856 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
8857 expand %{ | |
8858 regD tmp; | |
8859 stkL_to_regD(tmp, src); | |
8860 convL2D_helper(dst, tmp); | |
8861 %} | |
8862 %} | |
8863 | |
3804 | 8864 instruct convL2D_reg(regD dst, iRegL src) %{ |
8865 predicate(UseVIS >= 3); | |
8866 match(Set dst (ConvL2D src)); | |
8867 expand %{ | |
8868 regD tmp; | |
8869 MoveL2D_reg_reg(tmp, src); | |
8870 convL2D_helper(dst, tmp); | |
8871 %} | |
8872 %} | |
0 | 8873 |
8874 // Long to Float conversion using fast fxtof | |
8875 instruct convL2F_helper(regF dst, regD tmp) %{ | |
8876 effect(DEF dst, USE tmp); | |
8877 size(4); | |
8878 format %{ "FXTOS $tmp,$dst" %} | |
8879 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
8880 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
8881 ins_pipe(fcvtL2F); | |
8882 %} | |
8883 | |
3804 | 8884 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ |
0 | 8885 match(Set dst (ConvL2F src)); |
8886 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8887 expand %{ | |
8888 regD tmp; | |
8889 stkL_to_regD(tmp, src); | |
8890 convL2F_helper(dst, tmp); | |
8891 %} | |
8892 %} | |
3804 | 8893 |
8894 instruct convL2F_reg(regF dst, iRegL src) %{ | |
8895 predicate(UseVIS >= 3); | |
8896 match(Set dst (ConvL2F src)); | |
8897 ins_cost(DEFAULT_COST); | |
8898 expand %{ | |
8899 regD tmp; | |
8900 MoveL2D_reg_reg(tmp, src); | |
8901 convL2F_helper(dst, tmp); | |
8902 %} | |
8903 %} | |
8904 | |
0 | 8905 //----------- |
8906 | |
8907 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
8908 match(Set dst (ConvL2I src)); | |
8909 #ifndef _LP64 | |
8910 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
8911 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
8912 ins_pipe(ialu_move_reg_I_to_L); | |
8913 #else | |
8914 size(4); | |
8915 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
8916 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
8917 ins_pipe(ialu_reg); | |
8918 #endif | |
8919 %} | |
8920 | |
8921 // Register Shift Right Immediate | |
8922 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
8923 match(Set dst (ConvL2I (RShiftL src cnt))); | |
8924 | |
8925 size(4); | |
8926 format %{ "SRAX $src,$cnt,$dst" %} | |
8927 opcode(Assembler::srax_op3, Assembler::arith_op); | |
8928 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
8929 ins_pipe(ialu_reg_imm); | |
8930 %} | |
8931 | |
8932 //----------Control Flow Instructions------------------------------------------ | |
8933 // Compare Instructions | |
8934 // Compare Integers | |
8935 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
8936 match(Set icc (CmpI op1 op2)); | |
8937 effect( DEF icc, USE op1, USE op2 ); | |
8938 | |
8939 size(4); | |
8940 format %{ "CMP $op1,$op2" %} | |
8941 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8942 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8943 ins_pipe(ialu_cconly_reg_reg); | |
8944 %} | |
8945 | |
8946 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
8947 match(Set icc (CmpU op1 op2)); | |
8948 | |
8949 size(4); | |
8950 format %{ "CMP $op1,$op2\t! unsigned" %} | |
8951 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8952 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8953 ins_pipe(ialu_cconly_reg_reg); | |
8954 %} | |
8955 | |
8956 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
8957 match(Set icc (CmpI op1 op2)); | |
8958 effect( DEF icc, USE op1 ); | |
8959 | |
8960 size(4); | |
8961 format %{ "CMP $op1,$op2" %} | |
8962 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8963 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8964 ins_pipe(ialu_cconly_reg_imm); | |
8965 %} | |
8966 | |
8967 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
8968 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8969 | |
8970 size(4); | |
8971 format %{ "BTST $op2,$op1" %} | |
8972 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8973 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8974 ins_pipe(ialu_cconly_reg_reg_zero); | |
8975 %} | |
8976 | |
8977 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
8978 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8979 | |
8980 size(4); | |
8981 format %{ "BTST $op2,$op1" %} | |
8982 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8983 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8984 ins_pipe(ialu_cconly_reg_imm_zero); | |
8985 %} | |
8986 | |
8987 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
8988 match(Set xcc (CmpL op1 op2)); | |
8989 effect( DEF xcc, USE op1, USE op2 ); | |
8990 | |
8991 size(4); | |
8992 format %{ "CMP $op1,$op2\t\t! long" %} | |
8993 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8994 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8995 ins_pipe(ialu_cconly_reg_reg); | |
8996 %} | |
8997 | |
8998 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
8999 match(Set xcc (CmpL op1 con)); | |
9000 effect( DEF xcc, USE op1, USE con ); | |
9001 | |
9002 size(4); | |
9003 format %{ "CMP $op1,$con\t\t! long" %} | |
9004 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
9005 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
9006 ins_pipe(ialu_cconly_reg_reg); | |
9007 %} | |
9008 | |
9009 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
9010 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
9011 effect( DEF xcc, USE op1, USE op2 ); | |
9012 | |
9013 size(4); | |
9014 format %{ "BTST $op1,$op2\t\t! long" %} | |
9015 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
9016 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
9017 ins_pipe(ialu_cconly_reg_reg); | |
9018 %} | |
9019 | |
9020 // useful for checking the alignment of a pointer: | |
9021 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
9022 match(Set xcc (CmpL (AndL op1 con) zero)); | |
9023 effect( DEF xcc, USE op1, USE con ); | |
9024 | |
9025 size(4); | |
9026 format %{ "BTST $op1,$con\t\t! long" %} | |
9027 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
9028 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
9029 ins_pipe(ialu_cconly_reg_reg); | |
9030 %} | |
9031 | |
17506
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
17505
diff
changeset
|
9032 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{ |
0 | 9033 match(Set icc (CmpU op1 op2)); |
9034 | |
9035 size(4); | |
9036 format %{ "CMP $op1,$op2\t! unsigned" %} | |
9037 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
9038 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
9039 ins_pipe(ialu_cconly_reg_imm); | |
9040 %} | |
9041 | |
9042 // Compare Pointers | |
9043 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
9044 match(Set pcc (CmpP op1 op2)); | |
9045 | |
9046 size(4); | |
9047 format %{ "CMP $op1,$op2\t! ptr" %} | |
9048 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
9049 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
9050 ins_pipe(ialu_cconly_reg_reg); | |
9051 %} | |
9052 | |
9053 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
9054 match(Set pcc (CmpP op1 op2)); | |
9055 | |
9056 size(4); | |
9057 format %{ "CMP $op1,$op2\t! ptr" %} | |
9058 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
9059 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
9060 ins_pipe(ialu_cconly_reg_imm); | |
9061 %} | |
9062 | |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9063 // Compare Narrow oops |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9064 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9065 match(Set icc (CmpN op1 op2)); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9066 |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9067 size(4); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9068 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9069 opcode(Assembler::subcc_op3, Assembler::arith_op); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9070 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9071 ins_pipe(ialu_cconly_reg_reg); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9072 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9073 |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9074 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9075 match(Set icc (CmpN op1 op2)); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9076 |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9077 size(4); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9078 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9079 opcode(Assembler::subcc_op3, Assembler::arith_op); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9080 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9081 ins_pipe(ialu_cconly_reg_imm); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9082 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9083 |
0 | 9084 //----------Max and Min-------------------------------------------------------- |
9085 // Min Instructions | |
9086 // Conditional move for min | |
9087 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
9088 effect( USE_DEF op2, USE op1, USE icc ); | |
9089 | |
9090 size(4); | |
9091 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
9092 opcode(Assembler::less); | |
9093 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
9094 ins_pipe(ialu_reg_flags); | |
9095 %} | |
9096 | |
9097 // Min Register with Register. | |
9098 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
9099 match(Set op2 (MinI op1 op2)); | |
9100 ins_cost(DEFAULT_COST*2); | |
9101 expand %{ | |
9102 flagsReg icc; | |
9103 compI_iReg(icc,op1,op2); | |
9104 cmovI_reg_lt(op2,op1,icc); | |
9105 %} | |
9106 %} | |
9107 | |
9108 // Max Instructions | |
9109 // Conditional move for max | |
9110 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
9111 effect( USE_DEF op2, USE op1, USE icc ); | |
9112 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
9113 opcode(Assembler::greater); | |
9114 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
9115 ins_pipe(ialu_reg_flags); | |
9116 %} | |
9117 | |
9118 // Max Register with Register | |
9119 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
9120 match(Set op2 (MaxI op1 op2)); | |
9121 ins_cost(DEFAULT_COST*2); | |
9122 expand %{ | |
9123 flagsReg icc; | |
9124 compI_iReg(icc,op1,op2); | |
9125 cmovI_reg_gt(op2,op1,icc); | |
9126 %} | |
9127 %} | |
9128 | |
9129 | |
9130 //----------Float Compares---------------------------------------------------- | |
9131 // Compare floating, generate condition code | |
9132 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
9133 match(Set fcc (CmpF src1 src2)); | |
9134 | |
9135 size(4); | |
9136 format %{ "FCMPs $fcc,$src1,$src2" %} | |
9137 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
9138 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
9139 ins_pipe(faddF_fcc_reg_reg_zero); | |
9140 %} | |
9141 | |
9142 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
9143 match(Set fcc (CmpD src1 src2)); | |
9144 | |
9145 size(4); | |
9146 format %{ "FCMPd $fcc,$src1,$src2" %} | |
9147 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
9148 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
9149 ins_pipe(faddD_fcc_reg_reg_zero); | |
9150 %} | |
9151 | |
9152 | |
9153 // Compare floating, generate -1,0,1 | |
9154 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
9155 match(Set dst (CmpF3 src1 src2)); | |
9156 effect(KILL fcc0); | |
9157 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
9158 format %{ "fcmpl $dst,$src1,$src2" %} | |
9159 // Primary = float | |
9160 opcode( true ); | |
9161 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
9162 ins_pipe( floating_cmp ); | |
9163 %} | |
9164 | |
9165 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
9166 match(Set dst (CmpD3 src1 src2)); | |
9167 effect(KILL fcc0); | |
9168 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
9169 format %{ "dcmpl $dst,$src1,$src2" %} | |
9170 // Primary = double (not float) | |
9171 opcode( false ); | |
9172 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
9173 ins_pipe( floating_cmp ); | |
9174 %} | |
9175 | |
9176 //----------Branches--------------------------------------------------------- | |
9177 // Jump | |
9178 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
9179 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
9180 match(Jump switch_val); | |
4776
5da7201222d5
7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM
kvn
parents:
4763
diff
changeset
|
9181 effect(TEMP table); |
0 | 9182 |
9183 ins_cost(350); | |
9184 | |
2008 | 9185 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" |
9186 "LD [O7 + $switch_val], O7\n\t" | |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
9187 "JUMP O7" %} |
2008 | 9188 ins_encode %{ |
9189 // Calculate table address into a register. | |
9190 Register table_reg; | |
9191 Register label_reg = O7; | |
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
9192 // If we are calculating the size of this instruction don't trust |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
9193 // zero offsets because they might change when |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
9194 // MachConstantBaseNode decides to optimize the constant table |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
9195 // base. |
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
9196 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) { |
2008 | 9197 table_reg = $constanttablebase; |
9198 } else { | |
9199 table_reg = O7; | |
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
9200 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); |
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
9201 __ add($constanttablebase, con_offset, table_reg); |
2008 | 9202 } |
9203 | |
9204 // Jump to base address + switch value | |
9205 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); | |
9206 __ jmp(label_reg, G0); | |
9207 __ delayed()->nop(); | |
9208 %} | |
0 | 9209 ins_pipe(ialu_reg_reg); |
9210 %} | |
9211 | |
9212 // Direct Branch. Use V8 version with longer range. | |
9213 instruct branch(label labl) %{ | |
9214 match(Goto); | |
9215 effect(USE labl); | |
9216 | |
9217 size(8); | |
9218 ins_cost(BRANCH_COST); | |
9219 format %{ "BA $labl" %} | |
3839 | 9220 ins_encode %{ |
9221 Label* L = $labl$$label; | |
9222 __ ba(*L); | |
9223 __ delayed()->nop(); | |
9224 %} | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9225 ins_avoid_back_to_back(AVOID_BEFORE); |
0 | 9226 ins_pipe(br); |
9227 %} | |
9228 | |
3851 | 9229 // Direct Branch, short with no delay slot |
9230 instruct branch_short(label labl) %{ | |
9231 match(Goto); | |
9232 predicate(UseCBCond); | |
9233 effect(USE labl); | |
9234 | |
9235 size(4); | |
9236 ins_cost(BRANCH_COST); | |
9237 format %{ "BA $labl\t! short branch" %} | |
14416
6a936747b569
8024344: PPC64 (part 112): C argument in register AND stack slot.
goetz
parents:
12056
diff
changeset
|
9238 ins_encode %{ |
3851 | 9239 Label* L = $labl$$label; |
9240 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9241 __ ba_short(*L); | |
9242 %} | |
9243 ins_short_branch(1); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9244 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
3851 | 9245 ins_pipe(cbcond_reg_imm); |
9246 %} | |
9247 | |
0 | 9248 // Conditional Direct Branch |
9249 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
9250 match(If cmp icc); | |
9251 effect(USE labl); | |
9252 | |
9253 size(8); | |
9254 ins_cost(BRANCH_COST); | |
9255 format %{ "BP$cmp $icc,$labl" %} | |
9256 // Prim = bits 24-22, Secnd = bits 31-30 | |
9257 ins_encode( enc_bp( labl, cmp, icc ) ); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9258 ins_avoid_back_to_back(AVOID_BEFORE); |
0 | 9259 ins_pipe(br_cc); |
9260 %} | |
9261 | |
9262 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9263 match(If cmp icc); | |
9264 effect(USE labl); | |
9265 | |
3851 | 9266 ins_cost(BRANCH_COST); |
0 | 9267 format %{ "BP$cmp $icc,$labl" %} |
9268 // Prim = bits 24-22, Secnd = bits 31-30 | |
9269 ins_encode( enc_bp( labl, cmp, icc ) ); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9270 ins_avoid_back_to_back(AVOID_BEFORE); |
0 | 9271 ins_pipe(br_cc); |
9272 %} | |
9273 | |
9274 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
9275 match(If cmp pcc); | |
9276 effect(USE labl); | |
9277 | |
9278 size(8); | |
9279 ins_cost(BRANCH_COST); | |
9280 format %{ "BP$cmp $pcc,$labl" %} | |
3839 | 9281 ins_encode %{ |
9282 Label* L = $labl$$label; | |
9283 Assembler::Predict predict_taken = | |
9284 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9285 | |
9286 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
9287 __ delayed()->nop(); | |
9288 %} | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9289 ins_avoid_back_to_back(AVOID_BEFORE); |
0 | 9290 ins_pipe(br_cc); |
9291 %} | |
9292 | |
9293 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
9294 match(If cmp fcc); | |
9295 effect(USE labl); | |
9296 | |
9297 size(8); | |
9298 ins_cost(BRANCH_COST); | |
9299 format %{ "FBP$cmp $fcc,$labl" %} | |
3839 | 9300 ins_encode %{ |
9301 Label* L = $labl$$label; | |
9302 Assembler::Predict predict_taken = | |
9303 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9304 | |
9305 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); | |
9306 __ delayed()->nop(); | |
9307 %} | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9308 ins_avoid_back_to_back(AVOID_BEFORE); |
0 | 9309 ins_pipe(br_fcc); |
9310 %} | |
9311 | |
9312 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
9313 match(CountedLoopEnd cmp icc); | |
9314 effect(USE labl); | |
9315 | |
9316 size(8); | |
9317 ins_cost(BRANCH_COST); | |
9318 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9319 // Prim = bits 24-22, Secnd = bits 31-30 | |
9320 ins_encode( enc_bp( labl, cmp, icc ) ); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9321 ins_avoid_back_to_back(AVOID_BEFORE); |
0 | 9322 ins_pipe(br_cc); |
9323 %} | |
9324 | |
9325 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9326 match(CountedLoopEnd cmp icc); | |
9327 effect(USE labl); | |
9328 | |
9329 size(8); | |
9330 ins_cost(BRANCH_COST); | |
9331 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9332 // Prim = bits 24-22, Secnd = bits 31-30 | |
9333 ins_encode( enc_bp( labl, cmp, icc ) ); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9334 ins_avoid_back_to_back(AVOID_BEFORE); |
0 | 9335 ins_pipe(br_cc); |
9336 %} | |
9337 | |
3851 | 9338 // Compare and branch instructions |
9339 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9340 match(If cmp (CmpI op1 op2)); | |
9341 effect(USE labl, KILL icc); | |
9342 | |
9343 size(12); | |
9344 ins_cost(BRANCH_COST); | |
9345 format %{ "CMP $op1,$op2\t! int\n\t" | |
9346 "BP$cmp $labl" %} | |
9347 ins_encode %{ | |
9348 Label* L = $labl$$label; | |
9349 Assembler::Predict predict_taken = | |
9350 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9351 __ cmp($op1$$Register, $op2$$Register); | |
9352 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9353 __ delayed()->nop(); | |
9354 %} | |
9355 ins_pipe(cmp_br_reg_reg); | |
9356 %} | |
9357 | |
9358 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9359 match(If cmp (CmpI op1 op2)); | |
9360 effect(USE labl, KILL icc); | |
9361 | |
9362 size(12); | |
9363 ins_cost(BRANCH_COST); | |
9364 format %{ "CMP $op1,$op2\t! int\n\t" | |
9365 "BP$cmp $labl" %} | |
9366 ins_encode %{ | |
9367 Label* L = $labl$$label; | |
9368 Assembler::Predict predict_taken = | |
9369 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9370 __ cmp($op1$$Register, $op2$$constant); | |
9371 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9372 __ delayed()->nop(); | |
9373 %} | |
9374 ins_pipe(cmp_br_reg_imm); | |
9375 %} | |
9376 | |
9377 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
9378 match(If cmp (CmpU op1 op2)); | |
9379 effect(USE labl, KILL icc); | |
9380 | |
9381 size(12); | |
9382 ins_cost(BRANCH_COST); | |
9383 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
9384 "BP$cmp $labl" %} | |
9385 ins_encode %{ | |
9386 Label* L = $labl$$label; | |
9387 Assembler::Predict predict_taken = | |
9388 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9389 __ cmp($op1$$Register, $op2$$Register); | |
9390 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9391 __ delayed()->nop(); | |
9392 %} | |
9393 ins_pipe(cmp_br_reg_reg); | |
9394 %} | |
9395 | |
9396 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
9397 match(If cmp (CmpU op1 op2)); | |
9398 effect(USE labl, KILL icc); | |
9399 | |
9400 size(12); | |
9401 ins_cost(BRANCH_COST); | |
9402 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
9403 "BP$cmp $labl" %} | |
9404 ins_encode %{ | |
9405 Label* L = $labl$$label; | |
9406 Assembler::Predict predict_taken = | |
9407 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9408 __ cmp($op1$$Register, $op2$$constant); | |
9409 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9410 __ delayed()->nop(); | |
9411 %} | |
9412 ins_pipe(cmp_br_reg_imm); | |
9413 %} | |
9414 | |
9415 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
9416 match(If cmp (CmpL op1 op2)); | |
9417 effect(USE labl, KILL xcc); | |
9418 | |
9419 size(12); | |
9420 ins_cost(BRANCH_COST); | |
9421 format %{ "CMP $op1,$op2\t! long\n\t" | |
9422 "BP$cmp $labl" %} | |
9423 ins_encode %{ | |
9424 Label* L = $labl$$label; | |
9425 Assembler::Predict predict_taken = | |
9426 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9427 __ cmp($op1$$Register, $op2$$Register); | |
9428 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
9429 __ delayed()->nop(); | |
9430 %} | |
9431 ins_pipe(cmp_br_reg_reg); | |
9432 %} | |
9433 | |
9434 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
9435 match(If cmp (CmpL op1 op2)); | |
9436 effect(USE labl, KILL xcc); | |
9437 | |
9438 size(12); | |
9439 ins_cost(BRANCH_COST); | |
9440 format %{ "CMP $op1,$op2\t! long\n\t" | |
9441 "BP$cmp $labl" %} | |
9442 ins_encode %{ | |
9443 Label* L = $labl$$label; | |
9444 Assembler::Predict predict_taken = | |
9445 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9446 __ cmp($op1$$Register, $op2$$constant); | |
9447 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
9448 __ delayed()->nop(); | |
9449 %} | |
9450 ins_pipe(cmp_br_reg_imm); | |
9451 %} | |
9452 | |
9453 // Compare Pointers and branch | |
9454 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
9455 match(If cmp (CmpP op1 op2)); | |
9456 effect(USE labl, KILL pcc); | |
9457 | |
9458 size(12); | |
9459 ins_cost(BRANCH_COST); | |
9460 format %{ "CMP $op1,$op2\t! ptr\n\t" | |
9461 "B$cmp $labl" %} | |
9462 ins_encode %{ | |
9463 Label* L = $labl$$label; | |
9464 Assembler::Predict predict_taken = | |
9465 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9466 __ cmp($op1$$Register, $op2$$Register); | |
9467 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
9468 __ delayed()->nop(); | |
9469 %} | |
9470 ins_pipe(cmp_br_reg_reg); | |
9471 %} | |
9472 | |
9473 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
9474 match(If cmp (CmpP op1 null)); | |
9475 effect(USE labl, KILL pcc); | |
9476 | |
9477 size(12); | |
9478 ins_cost(BRANCH_COST); | |
9479 format %{ "CMP $op1,0\t! ptr\n\t" | |
9480 "B$cmp $labl" %} | |
9481 ins_encode %{ | |
9482 Label* L = $labl$$label; | |
9483 Assembler::Predict predict_taken = | |
9484 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9485 __ cmp($op1$$Register, G0); | |
9486 // bpr() is not used here since it has shorter distance. | |
9487 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
9488 __ delayed()->nop(); | |
9489 %} | |
9490 ins_pipe(cmp_br_reg_reg); | |
9491 %} | |
9492 | |
9493 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
9494 match(If cmp (CmpN op1 op2)); | |
9495 effect(USE labl, KILL icc); | |
9496 | |
9497 size(12); | |
9498 ins_cost(BRANCH_COST); | |
9499 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" | |
9500 "BP$cmp $labl" %} | |
9501 ins_encode %{ | |
9502 Label* L = $labl$$label; | |
9503 Assembler::Predict predict_taken = | |
9504 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9505 __ cmp($op1$$Register, $op2$$Register); | |
9506 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9507 __ delayed()->nop(); | |
9508 %} | |
9509 ins_pipe(cmp_br_reg_reg); | |
9510 %} | |
9511 | |
9512 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
9513 match(If cmp (CmpN op1 null)); | |
9514 effect(USE labl, KILL icc); | |
9515 | |
9516 size(12); | |
9517 ins_cost(BRANCH_COST); | |
9518 format %{ "CMP $op1,0\t! compressed ptr\n\t" | |
9519 "BP$cmp $labl" %} | |
9520 ins_encode %{ | |
9521 Label* L = $labl$$label; | |
9522 Assembler::Predict predict_taken = | |
9523 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9524 __ cmp($op1$$Register, G0); | |
9525 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9526 __ delayed()->nop(); | |
9527 %} | |
9528 ins_pipe(cmp_br_reg_reg); | |
9529 %} | |
9530 | |
9531 // Loop back branch | |
9532 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9533 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9534 effect(USE labl, KILL icc); | |
9535 | |
9536 size(12); | |
9537 ins_cost(BRANCH_COST); | |
9538 format %{ "CMP $op1,$op2\t! int\n\t" | |
9539 "BP$cmp $labl\t! Loop end" %} | |
9540 ins_encode %{ | |
9541 Label* L = $labl$$label; | |
9542 Assembler::Predict predict_taken = | |
9543 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9544 __ cmp($op1$$Register, $op2$$Register); | |
9545 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9546 __ delayed()->nop(); | |
9547 %} | |
9548 ins_pipe(cmp_br_reg_reg); | |
9549 %} | |
9550 | |
9551 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9552 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9553 effect(USE labl, KILL icc); | |
9554 | |
9555 size(12); | |
9556 ins_cost(BRANCH_COST); | |
9557 format %{ "CMP $op1,$op2\t! int\n\t" | |
9558 "BP$cmp $labl\t! Loop end" %} | |
9559 ins_encode %{ | |
9560 Label* L = $labl$$label; | |
9561 Assembler::Predict predict_taken = | |
9562 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9563 __ cmp($op1$$Register, $op2$$constant); | |
9564 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9565 __ delayed()->nop(); | |
9566 %} | |
9567 ins_pipe(cmp_br_reg_imm); | |
9568 %} | |
9569 | |
9570 // Short compare and branch instructions | |
9571 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9572 match(If cmp (CmpI op1 op2)); | |
9573 predicate(UseCBCond); | |
9574 effect(USE labl, KILL icc); | |
9575 | |
9576 size(4); | |
9577 ins_cost(BRANCH_COST); | |
9578 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
9579 ins_encode %{ | |
9580 Label* L = $labl$$label; | |
9581 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9582 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9583 %} | |
9584 ins_short_branch(1); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9585 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
3851 | 9586 ins_pipe(cbcond_reg_reg); |
9587 %} | |
9588 | |
9589 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9590 match(If cmp (CmpI op1 op2)); | |
9591 predicate(UseCBCond); | |
9592 effect(USE labl, KILL icc); | |
9593 | |
9594 size(4); | |
9595 ins_cost(BRANCH_COST); | |
9596 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
9597 ins_encode %{ | |
9598 Label* L = $labl$$label; | |
9599 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9600 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
9601 %} | |
9602 ins_short_branch(1); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9603 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
3851 | 9604 ins_pipe(cbcond_reg_imm); |
9605 %} | |
9606 | |
9607 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
9608 match(If cmp (CmpU op1 op2)); | |
9609 predicate(UseCBCond); | |
9610 effect(USE labl, KILL icc); | |
9611 | |
9612 size(4); | |
9613 ins_cost(BRANCH_COST); | |
9614 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
9615 ins_encode %{ | |
9616 Label* L = $labl$$label; | |
9617 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9618 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9619 %} | |
9620 ins_short_branch(1); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9621 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
3851 | 9622 ins_pipe(cbcond_reg_reg); |
9623 %} | |
9624 | |
9625 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
9626 match(If cmp (CmpU op1 op2)); | |
9627 predicate(UseCBCond); | |
9628 effect(USE labl, KILL icc); | |
9629 | |
9630 size(4); | |
9631 ins_cost(BRANCH_COST); | |
9632 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
9633 ins_encode %{ | |
9634 Label* L = $labl$$label; | |
9635 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9636 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
9637 %} | |
9638 ins_short_branch(1); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9639 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
3851 | 9640 ins_pipe(cbcond_reg_imm); |
9641 %} | |
9642 | |
9643 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
9644 match(If cmp (CmpL op1 op2)); | |
9645 predicate(UseCBCond); | |
9646 effect(USE labl, KILL xcc); | |
9647 | |
9648 size(4); | |
9649 ins_cost(BRANCH_COST); | |
9650 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
9651 ins_encode %{ | |
9652 Label* L = $labl$$label; | |
9653 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9654 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); | |
9655 %} | |
9656 ins_short_branch(1); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9657 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
3851 | 9658 ins_pipe(cbcond_reg_reg); |
9659 %} | |
9660 | |
9661 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
9662 match(If cmp (CmpL op1 op2)); | |
9663 predicate(UseCBCond); | |
9664 effect(USE labl, KILL xcc); | |
9665 | |
9666 size(4); | |
9667 ins_cost(BRANCH_COST); | |
9668 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
9669 ins_encode %{ | |
9670 Label* L = $labl$$label; | |
9671 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9672 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); | |
9673 %} | |
9674 ins_short_branch(1); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9675 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
3851 | 9676 ins_pipe(cbcond_reg_imm); |
9677 %} | |
9678 | |
9679 // Compare Pointers and branch | |
9680 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
9681 match(If cmp (CmpP op1 op2)); | |
9682 predicate(UseCBCond); | |
9683 effect(USE labl, KILL pcc); | |
9684 | |
9685 size(4); | |
9686 ins_cost(BRANCH_COST); | |
9687 #ifdef _LP64 | |
9688 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} | |
9689 #else | |
9690 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %} | |
9691 #endif | |
9692 ins_encode %{ | |
9693 Label* L = $labl$$label; | |
9694 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9695 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); | |
9696 %} | |
9697 ins_short_branch(1); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9698 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
3851 | 9699 ins_pipe(cbcond_reg_reg); |
9700 %} | |
9701 | |
9702 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
9703 match(If cmp (CmpP op1 null)); | |
9704 predicate(UseCBCond); | |
9705 effect(USE labl, KILL pcc); | |
9706 | |
9707 size(4); | |
9708 ins_cost(BRANCH_COST); | |
9709 #ifdef _LP64 | |
9710 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} | |
9711 #else | |
9712 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %} | |
9713 #endif | |
9714 ins_encode %{ | |
9715 Label* L = $labl$$label; | |
9716 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9717 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); | |
9718 %} | |
9719 ins_short_branch(1); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9720 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
3851 | 9721 ins_pipe(cbcond_reg_reg); |
9722 %} | |
9723 | |
9724 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
9725 match(If cmp (CmpN op1 op2)); | |
9726 predicate(UseCBCond); | |
9727 effect(USE labl, KILL icc); | |
9728 | |
9729 size(4); | |
9730 ins_cost(BRANCH_COST); | |
9731 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %} | |
9732 ins_encode %{ | |
9733 Label* L = $labl$$label; | |
9734 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9735 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9736 %} | |
9737 ins_short_branch(1); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9738 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
3851 | 9739 ins_pipe(cbcond_reg_reg); |
9740 %} | |
9741 | |
9742 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
9743 match(If cmp (CmpN op1 null)); | |
9744 predicate(UseCBCond); | |
9745 effect(USE labl, KILL icc); | |
9746 | |
9747 size(4); | |
9748 ins_cost(BRANCH_COST); | |
9749 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} | |
9750 ins_encode %{ | |
9751 Label* L = $labl$$label; | |
9752 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9753 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); | |
9754 %} | |
9755 ins_short_branch(1); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9756 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
3851 | 9757 ins_pipe(cbcond_reg_reg); |
9758 %} | |
9759 | |
9760 // Loop back branch | |
9761 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9762 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9763 predicate(UseCBCond); | |
9764 effect(USE labl, KILL icc); | |
9765 | |
9766 size(4); | |
9767 ins_cost(BRANCH_COST); | |
9768 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
9769 ins_encode %{ | |
9770 Label* L = $labl$$label; | |
9771 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9772 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9773 %} | |
9774 ins_short_branch(1); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9775 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
3851 | 9776 ins_pipe(cbcond_reg_reg); |
9777 %} | |
9778 | |
9779 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9780 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9781 predicate(UseCBCond); | |
9782 effect(USE labl, KILL icc); | |
9783 | |
9784 size(4); | |
9785 ins_cost(BRANCH_COST); | |
9786 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
9787 ins_encode %{ | |
9788 Label* L = $labl$$label; | |
9789 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9790 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
9791 %} | |
9792 ins_short_branch(1); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9793 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); |
3851 | 9794 ins_pipe(cbcond_reg_imm); |
9795 %} | |
9796 | |
9797 // Branch-on-register tests all 64 bits. We assume that values | |
9798 // in 64-bit registers always remains zero or sign extended | |
9799 // unless our code munges the high bits. Interrupts can chop | |
9800 // the high order bits to zero or sign at any time. | |
9801 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
9802 match(If cmp (CmpI op1 zero)); | |
9803 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
9804 effect(USE labl); | |
9805 | |
9806 size(8); | |
9807 ins_cost(BRANCH_COST); | |
9808 format %{ "BR$cmp $op1,$labl" %} | |
9809 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9810 ins_avoid_back_to_back(AVOID_BEFORE); |
3851 | 9811 ins_pipe(br_reg); |
9812 %} | |
9813 | |
9814 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
9815 match(If cmp (CmpP op1 null)); | |
9816 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
9817 effect(USE labl); | |
9818 | |
9819 size(8); | |
9820 ins_cost(BRANCH_COST); | |
9821 format %{ "BR$cmp $op1,$labl" %} | |
9822 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9823 ins_avoid_back_to_back(AVOID_BEFORE); |
3851 | 9824 ins_pipe(br_reg); |
9825 %} | |
9826 | |
9827 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
9828 match(If cmp (CmpL op1 zero)); | |
9829 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
9830 effect(USE labl); | |
9831 | |
9832 size(8); | |
9833 ins_cost(BRANCH_COST); | |
9834 format %{ "BR$cmp $op1,$labl" %} | |
9835 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9836 ins_avoid_back_to_back(AVOID_BEFORE); |
3851 | 9837 ins_pipe(br_reg); |
9838 %} | |
9839 | |
9840 | |
0 | 9841 // ============================================================================ |
9842 // Long Compare | |
9843 // | |
9844 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
9845 // is tricky. The flavor of compare used depends on whether we are testing | |
9846 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
9847 // The GE test is the negated LT test. The LE test can be had by commuting | |
9848 // the operands (yielding a GE test) and then negating; negate again for the | |
9849 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
9850 // NE test is negated from that. | |
9851 | |
9852 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
9853 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
9854 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
9855 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
9856 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
9857 // foo match ends up with the wrong leaf. One fix is to not match both | |
9858 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
9859 // both forms beat the trinary form of long-compare and both are very useful | |
9860 // on Intel which has so few registers. | |
9861 | |
9862 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
9863 match(If cmp xcc); | |
9864 effect(USE labl); | |
9865 | |
9866 size(8); | |
9867 ins_cost(BRANCH_COST); | |
9868 format %{ "BP$cmp $xcc,$labl" %} | |
3839 | 9869 ins_encode %{ |
9870 Label* L = $labl$$label; | |
9871 Assembler::Predict predict_taken = | |
9872 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9873 | |
9874 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
9875 __ delayed()->nop(); | |
9876 %} | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
9877 ins_avoid_back_to_back(AVOID_BEFORE); |
0 | 9878 ins_pipe(br_cc); |
9879 %} | |
9880 | |
9881 // Manifest a CmpL3 result in an integer register. Very painful. | |
9882 // This is the test to avoid. | |
9883 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
9884 match(Set dst (CmpL3 src1 src2) ); | |
9885 effect( KILL ccr ); | |
9886 ins_cost(6*DEFAULT_COST); | |
9887 size(24); | |
9888 format %{ "CMP $src1,$src2\t\t! long\n" | |
9889 "\tBLT,a,pn done\n" | |
9890 "\tMOV -1,$dst\t! delay slot\n" | |
9891 "\tBGT,a,pn done\n" | |
9892 "\tMOV 1,$dst\t! delay slot\n" | |
9893 "\tCLR $dst\n" | |
9894 "done:" %} | |
9895 ins_encode( cmpl_flag(src1,src2,dst) ); | |
9896 ins_pipe(cmpL_reg); | |
9897 %} | |
9898 | |
9899 // Conditional move | |
9900 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
9901 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
9902 ins_cost(150); | |
9903 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
9904 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9905 ins_pipe(ialu_reg); | |
9906 %} | |
9907 | |
9908 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
9909 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
9910 ins_cost(140); | |
9911 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
9912 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9913 ins_pipe(ialu_imm); | |
9914 %} | |
9915 | |
9916 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
9917 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
9918 ins_cost(150); | |
9919 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9920 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9921 ins_pipe(ialu_reg); | |
9922 %} | |
9923 | |
9924 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
9925 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
9926 ins_cost(140); | |
9927 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9928 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9929 ins_pipe(ialu_imm); | |
9930 %} | |
9931 | |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9932 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9933 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9934 ins_cost(150); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9935 format %{ "MOV$cmp $xcc,$src,$dst" %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9936 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9937 ins_pipe(ialu_reg); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9938 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
9939 |
0 | 9940 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
9941 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
9942 ins_cost(150); | |
9943 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9944 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9945 ins_pipe(ialu_reg); | |
9946 %} | |
9947 | |
9948 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
9949 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
9950 ins_cost(140); | |
9951 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9952 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9953 ins_pipe(ialu_imm); | |
9954 %} | |
9955 | |
9956 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
9957 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
9958 ins_cost(150); | |
9959 opcode(0x101); | |
9960 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
9961 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9962 ins_pipe(int_conditional_float_move); | |
9963 %} | |
9964 | |
9965 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
9966 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
9967 ins_cost(150); | |
9968 opcode(0x102); | |
9969 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
9970 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9971 ins_pipe(int_conditional_float_move); | |
9972 %} | |
9973 | |
9974 // ============================================================================ | |
9975 // Safepoint Instruction | |
9976 instruct safePoint_poll(iRegP poll) %{ | |
9977 match(SafePoint poll); | |
9978 effect(USE poll); | |
9979 | |
9980 size(4); | |
9981 #ifdef _LP64 | |
9982 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
9983 #else | |
9984 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
9985 #endif | |
9986 ins_encode %{ | |
9987 __ relocate(relocInfo::poll_type); | |
9988 __ ld_ptr($poll$$Register, 0, G0); | |
9989 %} | |
9990 ins_pipe(loadPollP); | |
9991 %} | |
9992 | |
9993 // ============================================================================ | |
9994 // Call Instructions | |
9995 // Call Java Static Instruction | |
9996 instruct CallStaticJavaDirect( method meth ) %{ | |
9997 match(CallStaticJava); | |
1567 | 9998 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
0 | 9999 effect(USE meth); |
10000 | |
10001 size(8); | |
10002 ins_cost(CALL_COST); | |
10003 format %{ "CALL,static ; NOP ==> " %} | |
10004 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
10005 ins_avoid_back_to_back(AVOID_BEFORE); |
0 | 10006 ins_pipe(simple_call); |
10007 %} | |
10008 | |
1567 | 10009 // Call Java Static Instruction (method handle version) |
10010 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ | |
10011 match(CallStaticJava); | |
10012 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); | |
10013 effect(USE meth, KILL l7_mh_SP_save); | |
10014 | |
3856
bd87c0dcaba5
7079769: JSR 292: incorrect size() for CallStaticJavaHandle on sparc
twisti
parents:
3854
diff
changeset
|
10015 size(16); |
1567 | 10016 ins_cost(CALL_COST); |
10017 format %{ "CALL,static/MethodHandle" %} | |
10018 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); | |
10019 ins_pipe(simple_call); | |
10020 %} | |
10021 | |
0 | 10022 // Call Java Dynamic Instruction |
10023 instruct CallDynamicJavaDirect( method meth ) %{ | |
10024 match(CallDynamicJava); | |
10025 effect(USE meth); | |
10026 | |
10027 ins_cost(CALL_COST); | |
10028 format %{ "SET (empty),R_G5\n\t" | |
10029 "CALL,dynamic ; NOP ==> " %} | |
10030 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
10031 ins_pipe(call); | |
10032 %} | |
10033 | |
10034 // Call Runtime Instruction | |
10035 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
10036 match(CallRuntime); | |
10037 effect(USE meth, KILL l7); | |
10038 ins_cost(CALL_COST); | |
10039 format %{ "CALL,runtime" %} | |
10040 ins_encode( Java_To_Runtime( meth ), | |
10041 call_epilog, adjust_long_from_native_call ); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
10042 ins_avoid_back_to_back(AVOID_BEFORE); |
0 | 10043 ins_pipe(simple_call); |
10044 %} | |
10045 | |
10046 // Call runtime without safepoint - same as CallRuntime | |
10047 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
10048 match(CallLeaf); | |
10049 effect(USE meth, KILL l7); | |
10050 ins_cost(CALL_COST); | |
10051 format %{ "CALL,runtime leaf" %} | |
10052 ins_encode( Java_To_Runtime( meth ), | |
10053 call_epilog, | |
10054 adjust_long_from_native_call ); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
10055 ins_avoid_back_to_back(AVOID_BEFORE); |
0 | 10056 ins_pipe(simple_call); |
10057 %} | |
10058 | |
10059 // Call runtime without safepoint - same as CallLeaf | |
10060 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
10061 match(CallLeafNoFP); | |
10062 effect(USE meth, KILL l7); | |
10063 ins_cost(CALL_COST); | |
10064 format %{ "CALL,runtime leaf nofp" %} | |
10065 ins_encode( Java_To_Runtime( meth ), | |
10066 call_epilog, | |
10067 adjust_long_from_native_call ); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
10068 ins_avoid_back_to_back(AVOID_BEFORE); |
0 | 10069 ins_pipe(simple_call); |
10070 %} | |
10071 | |
10072 // Tail Call; Jump from runtime stub to Java code. | |
10073 // Also known as an 'interprocedural jump'. | |
10074 // Target of jump will eventually return to caller. | |
10075 // TailJump below removes the return address. | |
10076 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
10077 match(TailCall jump_target method_oop ); | |
10078 | |
10079 ins_cost(CALL_COST); | |
10080 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
10081 ins_encode(form_jmpl(jump_target)); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
10082 ins_avoid_back_to_back(AVOID_BEFORE); |
0 | 10083 ins_pipe(tail_call); |
10084 %} | |
10085 | |
10086 | |
10087 // Return Instruction | |
10088 instruct Ret() %{ | |
10089 match(Return); | |
10090 | |
10091 // The epilogue node did the ret already. | |
10092 size(0); | |
10093 format %{ "! return" %} | |
10094 ins_encode(); | |
10095 ins_pipe(empty); | |
10096 %} | |
10097 | |
10098 | |
10099 // Tail Jump; remove the return address; jump to target. | |
10100 // TailCall above leaves the return address around. | |
10101 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
10102 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
10103 // "restore" before this instruction (in Epilogue), we need to materialize it | |
10104 // in %i0. | |
10105 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
10106 match( TailJump jump_target ex_oop ); | |
10107 ins_cost(CALL_COST); | |
10108 format %{ "! discard R_O7\n\t" | |
10109 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
10110 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
10111 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
10112 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
10113 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
10114 ins_avoid_back_to_back(AVOID_BEFORE); |
0 | 10115 ins_pipe(tail_call); |
10116 %} | |
10117 | |
10118 // Create exception oop: created by stack-crawling runtime code. | |
10119 // Created exception is now available to this handler, and is setup | |
10120 // just prior to jumping to this handler. No code emitted. | |
10121 instruct CreateException( o0RegP ex_oop ) | |
10122 %{ | |
10123 match(Set ex_oop (CreateEx)); | |
10124 ins_cost(0); | |
10125 | |
10126 size(0); | |
10127 // use the following format syntax | |
10128 format %{ "! exception oop is in R_O0; no code emitted" %} | |
10129 ins_encode(); | |
10130 ins_pipe(empty); | |
10131 %} | |
10132 | |
10133 | |
10134 // Rethrow exception: | |
10135 // The exception oop will come in the first argument position. | |
10136 // Then JUMP (not call) to the rethrow stub code. | |
10137 instruct RethrowException() | |
10138 %{ | |
10139 match(Rethrow); | |
10140 ins_cost(CALL_COST); | |
10141 | |
10142 // use the following format syntax | |
10143 format %{ "Jmp rethrow_stub" %} | |
10144 ins_encode(enc_rethrow); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
10145 ins_avoid_back_to_back(AVOID_BEFORE); |
0 | 10146 ins_pipe(tail_call); |
10147 %} | |
10148 | |
10149 | |
10150 // Die now | |
10151 instruct ShouldNotReachHere( ) | |
10152 %{ | |
10153 match(Halt); | |
10154 ins_cost(CALL_COST); | |
10155 | |
10156 size(4); | |
10157 // Use the following format syntax | |
10158 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
10159 ins_encode( form2_illtrap() ); | |
10160 ins_pipe(tail_call); | |
10161 %} | |
10162 | |
10163 // ============================================================================ | |
10164 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
10165 // array for an instance of the superklass. Set a hidden internal cache on a | |
10166 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
10167 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
10168 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
10169 match(Set index (PartialSubtypeCheck sub super)); | |
10170 effect( KILL pcc, KILL o7 ); | |
10171 ins_cost(DEFAULT_COST*10); | |
10172 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
10173 ins_encode( enc_PartialSubtypeCheck() ); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
10174 ins_avoid_back_to_back(AVOID_BEFORE); |
0 | 10175 ins_pipe(partial_subtype_check_pipe); |
10176 %} | |
10177 | |
10178 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
10179 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
10180 effect( KILL idx, KILL o7 ); | |
10181 ins_cost(DEFAULT_COST*10); | |
10182 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
10183 ins_encode( enc_PartialSubtypeCheck() ); | |
17877
17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
iveresov
parents:
17810
diff
changeset
|
10184 ins_avoid_back_to_back(AVOID_BEFORE); |
0 | 10185 ins_pipe(partial_subtype_check_pipe); |
10186 %} | |
10187 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
10188 |
0 | 10189 // ============================================================================ |
10190 // inlined locking and unlocking | |
10191 | |
4777 | 10192 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ |
0 | 10193 match(Set pcc (FastLock object box)); |
10194 | |
4777 | 10195 effect(TEMP scratch2, USE_KILL box, KILL scratch); |
0 | 10196 ins_cost(100); |
10197 | |
4777 | 10198 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} |
0 | 10199 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); |
10200 ins_pipe(long_memory_op); | |
10201 %} | |
10202 | |
10203 | |
4777 | 10204 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ |
0 | 10205 match(Set pcc (FastUnlock object box)); |
4777 | 10206 effect(TEMP scratch2, USE_KILL box, KILL scratch); |
0 | 10207 ins_cost(100); |
10208 | |
4777 | 10209 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} |
0 | 10210 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); |
10211 ins_pipe(long_memory_op); | |
10212 %} | |
10213 | |
3892 | 10214 // The encodings are generic. |
0 | 10215 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ |
3892 | 10216 predicate(!use_block_zeroing(n->in(2)) ); |
0 | 10217 match(Set dummy (ClearArray cnt base)); |
10218 effect(TEMP temp, KILL ccr); | |
10219 ins_cost(300); | |
10220 format %{ "MOV $cnt,$temp\n" | |
10221 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
10222 " BRge loop\t\t! Clearing loop\n" | |
10223 " STX G0,[$base+$temp]\t! delay slot" %} | |
3892 | 10224 |
10225 ins_encode %{ | |
10226 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
10227 Register nof_bytes_arg = $cnt$$Register; | |
10228 Register nof_bytes_tmp = $temp$$Register; | |
10229 Register base_pointer_arg = $base$$Register; | |
10230 | |
10231 Label loop; | |
10232 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
10233 | |
10234 // Loop and clear, walking backwards through the array. | |
10235 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
10236 __ bind(loop); | |
10237 __ deccc(nof_bytes_tmp, 8); | |
10238 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
10239 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
10240 // %%%% this mini-loop must not cross a cache boundary! | |
10241 %} | |
10242 ins_pipe(long_memory_op); | |
10243 %} | |
10244 | |
10245 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{ | |
10246 predicate(use_block_zeroing(n->in(2))); | |
10247 match(Set dummy (ClearArray cnt base)); | |
10248 effect(USE_KILL cnt, USE_KILL base, KILL ccr); | |
10249 ins_cost(300); | |
10250 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} | |
10251 | |
10252 ins_encode %{ | |
10253 | |
10254 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); | |
10255 Register to = $base$$Register; | |
10256 Register count = $cnt$$Register; | |
10257 | |
10258 Label Ldone; | |
10259 __ nop(); // Separate short branches | |
10260 // Use BIS for zeroing (temp is not used). | |
10261 __ bis_zeroing(to, count, G0, Ldone); | |
10262 __ bind(Ldone); | |
10263 | |
10264 %} | |
10265 ins_pipe(long_memory_op); | |
10266 %} | |
10267 | |
10268 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{ | |
10269 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit)); | |
10270 match(Set dummy (ClearArray cnt base)); | |
10271 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr); | |
10272 ins_cost(300); | |
10273 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} | |
10274 | |
10275 ins_encode %{ | |
10276 | |
10277 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); | |
10278 Register to = $base$$Register; | |
10279 Register count = $cnt$$Register; | |
10280 Register temp = $tmp$$Register; | |
10281 | |
10282 Label Ldone; | |
10283 __ nop(); // Separate short branches | |
10284 // Use BIS for zeroing | |
10285 __ bis_zeroing(to, count, temp, Ldone); | |
10286 __ bind(Ldone); | |
10287 | |
10288 %} | |
0 | 10289 ins_pipe(long_memory_op); |
10290 %} | |
10291 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10292 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10293 o7RegI tmp, flagsReg ccr) %{ |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10294 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10295 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
0 | 10296 ins_cost(300); |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10297 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10298 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
0 | 10299 ins_pipe(long_memory_op); |
10300 %} | |
10301 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10302 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10303 o7RegI tmp, flagsReg ccr) %{ |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10304 match(Set result (StrEquals (Binary str1 str2) cnt)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10305 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
681 | 10306 ins_cost(300); |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10307 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10308 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
681 | 10309 ins_pipe(long_memory_op); |
10310 %} | |
10311 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10312 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10313 o7RegI tmp2, flagsReg ccr) %{ |
681 | 10314 match(Set result (AryEq ary1 ary2)); |
10315 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
10316 ins_cost(300); | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10317 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10318 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
681 | 10319 ins_pipe(long_memory_op); |
10320 %} | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10321 |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10322 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10323 //---------- Zeros Count Instructions ------------------------------------------ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10324 |
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10325 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10326 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10327 match(Set dst (CountLeadingZerosI src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10328 effect(TEMP dst, TEMP tmp, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10329 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10330 // x |= (x >> 1); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10331 // x |= (x >> 2); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10332 // x |= (x >> 4); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10333 // x |= (x >> 8); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10334 // x |= (x >> 16); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10335 // return (WORDBITS - popc(x)); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10336 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10337 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10338 "OR $dst,$tmp,$dst\n\t" |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10339 "SRL $dst,2,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10340 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10341 "SRL $dst,4,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10342 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10343 "SRL $dst,8,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10344 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10345 "SRL $dst,16,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10346 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10347 "POPC $dst,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10348 "MOV 32,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10349 "SUB $tmp,$dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10350 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10351 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10352 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10353 Register Rtmp = $tmp$$Register; |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10354 __ srl(Rsrc, 1, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10355 __ srl(Rsrc, 0, Rdst); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10356 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10357 __ srl(Rdst, 2, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10358 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10359 __ srl(Rdst, 4, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10360 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10361 __ srl(Rdst, 8, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10362 __ or3(Rdst, Rtmp, Rdst); |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10363 __ srl(Rdst, 16, Rtmp); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10364 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10365 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10366 __ mov(BitsPerInt, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10367 __ sub(Rtmp, Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10368 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10369 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10370 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10371 |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10372 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10373 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10374 match(Set dst (CountLeadingZerosL src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10375 effect(TEMP dst, TEMP tmp, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10376 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10377 // x |= (x >> 1); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10378 // x |= (x >> 2); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10379 // x |= (x >> 4); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10380 // x |= (x >> 8); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10381 // x |= (x >> 16); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10382 // x |= (x >> 32); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10383 // return (WORDBITS - popc(x)); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10384 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10385 "OR $src,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10386 "SRLX $dst,2,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10387 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10388 "SRLX $dst,4,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10389 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10390 "SRLX $dst,8,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10391 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10392 "SRLX $dst,16,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10393 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10394 "SRLX $dst,32,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10395 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10396 "POPC $dst,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10397 "MOV 64,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10398 "SUB $tmp,$dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10399 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10400 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10401 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10402 Register Rtmp = $tmp$$Register; |
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10403 __ srlx(Rsrc, 1, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10404 __ or3( Rsrc, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10405 __ srlx(Rdst, 2, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10406 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10407 __ srlx(Rdst, 4, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10408 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10409 __ srlx(Rdst, 8, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10410 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10411 __ srlx(Rdst, 16, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10412 __ or3( Rdst, Rtmp, Rdst); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10413 __ srlx(Rdst, 32, Rtmp); |
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10414 __ or3( Rdst, Rtmp, Rdst); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10415 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10416 __ mov(BitsPerLong, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10417 __ sub(Rtmp, Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10418 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10419 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10420 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10421 |
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10422 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{ |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10423 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10424 match(Set dst (CountTrailingZerosI src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10425 effect(TEMP dst, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10426 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10427 // return popc(~x & (x - 1)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10428 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10429 "ANDN $dst,$src,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10430 "SRL $dst,R_G0,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10431 "POPC $dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10432 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10433 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10434 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10435 __ sub(Rsrc, 1, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10436 __ andn(Rdst, Rsrc, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10437 __ srl(Rdst, G0, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10438 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10439 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10440 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10441 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10442 |
4003
4bac06a82bc3
7100757: The BitSet.nextSetBit() produces incorrect result in 32bit VM on Sparc
kvn
parents:
3898
diff
changeset
|
10443 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{ |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10444 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10445 match(Set dst (CountTrailingZerosL src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10446 effect(TEMP dst, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10447 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10448 // return popc(~x & (x - 1)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10449 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10450 "ANDN $dst,$src,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10451 "POPC $dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10452 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10453 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10454 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10455 __ sub(Rsrc, 1, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10456 __ andn(Rdst, Rsrc, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10457 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10458 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10459 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10460 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10461 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10462 |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10463 //---------- Population Count Instructions ------------------------------------- |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10464 |
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10465 instruct popCountI(iRegIsafe dst, iRegI src) %{ |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10466 predicate(UsePopCountInstruction); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10467 match(Set dst (PopCountI src)); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10468 |
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10469 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t" |
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10470 "POPC $dst, $dst" %} |
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10471 ins_encode %{ |
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10472 __ srl($src$$Register, G0, $dst$$Register); |
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10473 __ popc($dst$$Register, $dst$$Register); |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10474 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10475 ins_pipe(ialu_reg); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10476 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10477 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10478 // Note: Long.bitCount(long) returns an int. |
7426
65c8342f726a
8005033: clear high word for integer pop count on SPARC
twisti
parents:
6849
diff
changeset
|
10479 instruct popCountL(iRegIsafe dst, iRegL src) %{ |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10480 predicate(UsePopCountInstruction); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10481 match(Set dst (PopCountL src)); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10482 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10483 format %{ "POPC $src, $dst" %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10484 ins_encode %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10485 __ popc($src$$Register, $dst$$Register); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10486 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10487 ins_pipe(ialu_reg); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10488 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10489 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10490 |
0 | 10491 // ============================================================================ |
10492 //------------Bytes reverse-------------------------------------------------- | |
10493 | |
10494 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
10495 match(Set dst (ReverseBytesI src)); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10496 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10497 // Op cost is artificially doubled to make sure that load or store |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10498 // instructions are preferred over this one which requires a spill |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10499 // onto a stack slot. |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10500 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10501 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10502 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10503 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10504 __ set($src$$disp + STACK_BIAS, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10505 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10506 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10507 ins_pipe( iload_mem ); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10508 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10509 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10510 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10511 match(Set dst (ReverseBytesL src)); |
0 | 10512 |
10513 // Op cost is artificially doubled to make sure that load or store | |
10514 // instructions are preferred over this one which requires a spill | |
10515 // onto a stack slot. | |
10516 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10517 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10518 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10519 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10520 __ set($src$$disp + STACK_BIAS, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10521 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10522 %} |
0 | 10523 ins_pipe( iload_mem ); |
10524 %} | |
10525 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10526 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10527 match(Set dst (ReverseBytesUS src)); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10528 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10529 // Op cost is artificially doubled to make sure that load or store |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10530 // instructions are preferred over this one which requires a spill |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10531 // onto a stack slot. |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10532 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10533 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10534 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10535 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10536 // the value was spilled as an int so bias the load |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10537 __ set($src$$disp + STACK_BIAS + 2, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10538 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10539 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10540 ins_pipe( iload_mem ); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10541 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10542 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10543 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10544 match(Set dst (ReverseBytesS src)); |
0 | 10545 |
10546 // Op cost is artificially doubled to make sure that load or store | |
10547 // instructions are preferred over this one which requires a spill | |
10548 // onto a stack slot. | |
10549 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10550 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10551 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10552 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10553 // the value was spilled as an int so bias the load |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10554 __ set($src$$disp + STACK_BIAS + 2, O7); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10555 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10556 %} |
0 | 10557 ins_pipe( iload_mem ); |
10558 %} | |
10559 | |
10560 // Load Integer reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10561 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ |
0 | 10562 match(Set dst (ReverseBytesI (LoadI src))); |
10563 | |
10564 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10565 size(4); |
0 | 10566 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
10567 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10568 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10569 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10570 %} |
0 | 10571 ins_pipe(iload_mem); |
10572 %} | |
10573 | |
10574 // Load Long - aligned and reversed | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10575 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ |
0 | 10576 match(Set dst (ReverseBytesL (LoadL src))); |
10577 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10578 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10579 size(4); |
0 | 10580 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
10581 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10582 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10583 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10584 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10585 ins_pipe(iload_mem); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10586 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10587 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10588 // Load unsigned short / char reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10589 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10590 match(Set dst (ReverseBytesUS (LoadUS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10591 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10592 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10593 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10594 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10595 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10596 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10597 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10598 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10599 ins_pipe(iload_mem); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10600 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10601 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10602 // Load short reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10603 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10604 match(Set dst (ReverseBytesS (LoadS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10605 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10606 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10607 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10608 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10609 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10610 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10611 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10612 %} |
0 | 10613 ins_pipe(iload_mem); |
10614 %} | |
10615 | |
10616 // Store Integer reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10617 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ |
0 | 10618 match(Set dst (StoreI dst (ReverseBytesI src))); |
10619 | |
10620 ins_cost(MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10621 size(4); |
0 | 10622 format %{ "STWA $src, $dst\t!asi=primary_little" %} |
10623 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10624 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10625 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10626 %} |
0 | 10627 ins_pipe(istore_mem_reg); |
10628 %} | |
10629 | |
10630 // Store Long reversed byte order | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10631 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ |
0 | 10632 match(Set dst (StoreL dst (ReverseBytesL src))); |
10633 | |
10634 ins_cost(MEMORY_REF_COST); | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10635 size(4); |
0 | 10636 format %{ "STXA $src, $dst\t!asi=primary_little" %} |
10637 | |
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10638 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10639 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10640 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10641 ins_pipe(istore_mem_reg); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10642 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10643 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10644 // Store unsighed short/char reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10645 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10646 match(Set dst (StoreC dst (ReverseBytesUS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10647 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10648 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10649 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10650 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10651 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10652 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10653 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10654 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10655 ins_pipe(istore_mem_reg); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10656 %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10657 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10658 // Store short reversed byte order |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10659 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10660 match(Set dst (StoreC dst (ReverseBytesS src))); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10661 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10662 ins_cost(MEMORY_REF_COST); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10663 size(4); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10664 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10665 |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10666 ins_encode %{ |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10667 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10668 %} |
0 | 10669 ins_pipe(istore_mem_reg); |
10670 %} | |
10671 | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10672 // ====================VECTOR INSTRUCTIONS===================================== |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10673 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10674 // Load Aligned Packed values into a Double Register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10675 instruct loadV8(regD dst, memory mem) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10676 predicate(n->as_LoadVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10677 match(Set dst (LoadVector mem)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10678 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10679 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10680 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10681 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10682 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10683 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10684 ins_pipe(floadD_mem); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10685 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10686 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10687 // Store Vector in Double register to memory |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10688 instruct storeV8(memory mem, regD src) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10689 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10690 match(Set mem (StoreVector mem src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10691 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10692 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10693 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10694 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10695 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10696 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10697 ins_pipe(fstoreD_mem_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10698 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10699 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10700 // Store Zero into vector in memory |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10701 instruct storeV8B_zero(memory mem, immI0 zero) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10702 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10703 match(Set mem (StoreVector mem (ReplicateB zero))); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10704 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10705 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10706 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10707 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10708 __ stx(G0, $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10709 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10710 ins_pipe(fstoreD_mem_zero); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10711 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10712 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10713 instruct storeV4S_zero(memory mem, immI0 zero) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10714 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10715 match(Set mem (StoreVector mem (ReplicateS zero))); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10716 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10717 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10718 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10719 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10720 __ stx(G0, $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10721 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10722 ins_pipe(fstoreD_mem_zero); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10723 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10724 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10725 instruct storeV2I_zero(memory mem, immI0 zero) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10726 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10727 match(Set mem (StoreVector mem (ReplicateI zero))); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10728 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10729 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10730 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10731 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10732 __ stx(G0, $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10733 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10734 ins_pipe(fstoreD_mem_zero); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10735 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10736 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10737 instruct storeV2F_zero(memory mem, immF0 zero) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10738 predicate(n->as_StoreVector()->memory_size() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10739 match(Set mem (StoreVector mem (ReplicateF zero))); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10740 ins_cost(MEMORY_REF_COST); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10741 size(4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10742 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10743 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10744 __ stx(G0, $mem$$Address); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10745 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10746 ins_pipe(fstoreD_mem_zero); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10747 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10748 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10749 // Replicate scalar to packed byte values into Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10750 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10751 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10752 match(Set dst (ReplicateB src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10753 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10754 format %{ "SLLX $src,56,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10755 "SRLX $tmp, 8,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10756 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10757 "SRLX $tmp,16,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10758 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10759 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10760 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10761 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10762 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10763 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10764 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10765 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10766 __ sllx(Rsrc, 56, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10767 __ srlx(Rtmp, 8, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10768 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10769 __ srlx(Rtmp, 16, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10770 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10771 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10772 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10773 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10774 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10775 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10776 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10777 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10778 // Replicate scalar to packed byte values into Double stack |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10779 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10780 predicate(n->as_Vector()->length() == 8 && UseVIS < 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10781 match(Set dst (ReplicateB src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10782 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10783 format %{ "SLLX $src,56,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10784 "SRLX $tmp, 8,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10785 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10786 "SRLX $tmp,16,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10787 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10788 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10789 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10790 "STX $tmp,$dst\t! regL to stkD" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10791 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10792 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10793 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10794 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10795 __ sllx(Rsrc, 56, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10796 __ srlx(Rtmp, 8, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10797 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10798 __ srlx(Rtmp, 16, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10799 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10800 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10801 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10802 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10803 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10804 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10805 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10806 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10807 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10808 // Replicate scalar constant to packed byte values in Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10809 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10810 predicate(n->as_Vector()->length() == 8); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10811 match(Set dst (ReplicateB con)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10812 effect(KILL tmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10813 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10814 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10815 // XXX This is a quick fix for 6833573. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10816 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10817 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10818 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10819 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10820 ins_pipe(loadConFD); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10821 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10822 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10823 // Replicate scalar to packed char/short values into Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10824 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10825 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10826 match(Set dst (ReplicateS src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10827 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10828 format %{ "SLLX $src,48,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10829 "SRLX $tmp,16,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10830 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10831 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10832 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10833 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10834 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10835 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10836 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10837 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10838 __ sllx(Rsrc, 48, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10839 __ srlx(Rtmp, 16, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10840 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10841 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10842 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10843 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10844 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10845 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10846 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10847 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10848 // Replicate scalar to packed char/short values into Double stack |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10849 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10850 predicate(n->as_Vector()->length() == 4 && UseVIS < 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10851 match(Set dst (ReplicateS src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10852 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10853 format %{ "SLLX $src,48,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10854 "SRLX $tmp,16,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10855 "OR $tmp,$tmp2,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10856 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10857 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10858 "STX $tmp,$dst\t! regL to stkD" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10859 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10860 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10861 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10862 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10863 __ sllx(Rsrc, 48, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10864 __ srlx(Rtmp, 16, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10865 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10866 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10867 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10868 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10869 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10870 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10871 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10872 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10873 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10874 // Replicate scalar constant to packed char/short values in Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10875 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10876 predicate(n->as_Vector()->length() == 4); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10877 match(Set dst (ReplicateS con)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10878 effect(KILL tmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10879 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10880 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10881 // XXX This is a quick fix for 6833573. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10882 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10883 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10884 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10885 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10886 ins_pipe(loadConFD); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10887 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10888 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10889 // Replicate scalar to packed int values into Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10890 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10891 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10892 match(Set dst (ReplicateI src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10893 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10894 format %{ "SLLX $src,32,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10895 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10896 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10897 "MOVXTOD $tmp,$dst\t! MoveL2D" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10898 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10899 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10900 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10901 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10902 __ sllx(Rsrc, 32, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10903 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10904 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10905 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10906 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10907 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10908 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10909 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10910 // Replicate scalar to packed int values into Double stack |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10911 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10912 predicate(n->as_Vector()->length() == 2 && UseVIS < 3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10913 match(Set dst (ReplicateI src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10914 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10915 format %{ "SLLX $src,32,$tmp\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10916 "SRLX $tmp,32,$tmp2\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10917 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10918 "STX $tmp,$dst\t! regL to stkD" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10919 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10920 Register Rsrc = $src$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10921 Register Rtmp = $tmp$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10922 Register Rtmp2 = $tmp2$$Register; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10923 __ sllx(Rsrc, 32, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10924 __ srlx(Rtmp, 32, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10925 __ or3 (Rtmp, Rtmp2, Rtmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10926 __ set ($dst$$disp + STACK_BIAS, Rtmp2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10927 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10928 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10929 ins_pipe(ialu_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10930 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10931 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10932 // Replicate scalar zero constant to packed int values in Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10933 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10934 predicate(n->as_Vector()->length() == 2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10935 match(Set dst (ReplicateI con)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10936 effect(KILL tmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10937 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10938 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10939 // XXX This is a quick fix for 6833573. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10940 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10941 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10942 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10943 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10944 ins_pipe(loadConFD); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10945 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10946 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10947 // Replicate scalar to packed float values into Double stack |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10948 instruct Repl2F_stk(stackSlotD dst, regF src) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10949 predicate(n->as_Vector()->length() == 2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10950 match(Set dst (ReplicateF src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10951 ins_cost(MEMORY_REF_COST*2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10952 format %{ "STF $src,$dst.hi\t! packed2F\n\t" |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10953 "STF $src,$dst.lo" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10954 opcode(Assembler::stf_op3); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10955 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10956 ins_pipe(fstoreF_stk_reg); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10957 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10958 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10959 // Replicate scalar zero constant to packed float values in Double register |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10960 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10961 predicate(n->as_Vector()->length() == 2); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10962 match(Set dst (ReplicateF con)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10963 effect(KILL tmp); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10964 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10965 ins_encode %{ |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10966 // XXX This is a quick fix for 6833573. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10967 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10968 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10969 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10970 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10971 ins_pipe(loadConFD); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10972 %} |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10973 |
0 | 10974 //----------PEEPHOLE RULES----------------------------------------------------- |
10975 // These must follow all instruction definitions as they use the names | |
10976 // defined in the instructions definitions. | |
10977 // | |
605 | 10978 // peepmatch ( root_instr_name [preceding_instruction]* ); |
0 | 10979 // |
10980 // peepconstraint %{ | |
10981 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
10982 // [, ...] ); | |
10983 // // instruction numbers are zero-based using left to right order in peepmatch | |
10984 // | |
10985 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
10986 // // provide an instruction_number.operand_name for each operand that appears | |
10987 // // in the replacement instruction's match rule | |
10988 // | |
10989 // ---------VM FLAGS--------------------------------------------------------- | |
10990 // | |
10991 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
10992 // | |
10993 // Each peephole rule is given an identifying number starting with zero and | |
10994 // increasing by one in the order seen by the parser. An individual peephole | |
10995 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
10996 // on the command-line. | |
10997 // | |
10998 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
10999 // | |
11000 // Only match adjacent instructions in same basic block | |
11001 // Only equality constraints | |
11002 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
11003 // Only one replacement instruction | |
11004 // | |
11005 // ---------EXAMPLE---------------------------------------------------------- | |
11006 // | |
11007 // // pertinent parts of existing instructions in architecture description | |
11008 // instruct movI(eRegI dst, eRegI src) %{ | |
11009 // match(Set dst (CopyI src)); | |
11010 // %} | |
11011 // | |
11012 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
11013 // match(Set dst (AddI dst src)); | |
11014 // effect(KILL cr); | |
11015 // %} | |
11016 // | |
11017 // // Change (inc mov) to lea | |
11018 // peephole %{ | |
11019 // // increment preceeded by register-register move | |
11020 // peepmatch ( incI_eReg movI ); | |
11021 // // require that the destination register of the increment | |
11022 // // match the destination register of the move | |
11023 // peepconstraint ( 0.dst == 1.dst ); | |
11024 // // construct a replacement instruction that sets | |
11025 // // the destination to ( move's source register + one ) | |
11026 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
11027 // %} | |
11028 // | |
11029 | |
11030 // // Change load of spilled value to only a spill | |
11031 // instruct storeI(memory mem, eRegI src) %{ | |
11032 // match(Set mem (StoreI mem src)); | |
11033 // %} | |
11034 // | |
11035 // instruct loadI(eRegI dst, memory mem) %{ | |
11036 // match(Set dst (LoadI mem)); | |
11037 // %} | |
11038 // | |
11039 // peephole %{ | |
11040 // peepmatch ( loadI storeI ); | |
11041 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
11042 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
11043 // %} | |
11044 | |
11045 //----------SMARTSPILL RULES--------------------------------------------------- | |
11046 // These must follow all instruction definitions as they use the names | |
11047 // defined in the instructions definitions. | |
11048 // | |
11049 // SPARC will probably not have any of these rules due to RISC instruction set. | |
11050 | |
11051 //----------PIPELINE----------------------------------------------------------- | |
11052 // Rules which define the behavior of the target architectures pipeline. |