Mercurial > hg > truffle
annotate src/cpu/x86/vm/assembler_x86.cpp @ 18452:94b184d89f11
FrameMappingToolImpl: inline TrackedVirtualStackSlot.transform().
author | Josef Eisl <josef.eisl@jku.at> |
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date | Mon, 17 Nov 2014 19:32:05 +0100 |
parents | 52b4284cb496 |
children | 7848fc12602b |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/assembler.hpp" |
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27 #include "asm/assembler.inline.hpp" |
1972 | 28 #include "gc_interface/collectedHeap.inline.hpp" |
29 #include "interpreter/interpreter.hpp" | |
30 #include "memory/cardTableModRefBS.hpp" | |
31 #include "memory/resourceArea.hpp" | |
32 #include "prims/methodHandles.hpp" | |
33 #include "runtime/biasedLocking.hpp" | |
34 #include "runtime/interfaceSupport.hpp" | |
35 #include "runtime/objectMonitor.hpp" | |
36 #include "runtime/os.hpp" | |
37 #include "runtime/sharedRuntime.hpp" | |
38 #include "runtime/stubRoutines.hpp" | |
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39 #include "utilities/macros.hpp" |
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40 #if INCLUDE_ALL_GCS |
1972 | 41 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" |
42 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" | |
43 #include "gc_implementation/g1/heapRegion.hpp" | |
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44 #endif // INCLUDE_ALL_GCS |
0 | 45 |
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46 #ifdef PRODUCT |
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47 #define BLOCK_COMMENT(str) /* nothing */ |
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48 #define STOP(error) stop(error) |
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49 #else |
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50 #define BLOCK_COMMENT(str) block_comment(str) |
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51 #define STOP(error) block_comment(error); stop(error) |
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52 #endif |
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53 |
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54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") |
0 | 55 // Implementation of AddressLiteral |
56 | |
57 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { | |
58 _is_lval = false; | |
59 _target = target; | |
60 switch (rtype) { | |
61 case relocInfo::oop_type: | |
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62 case relocInfo::metadata_type: |
0 | 63 // Oops are a special case. Normally they would be their own section |
64 // but in cases like icBuffer they are literals in the code stream that | |
65 // we don't have a section for. We use none so that we get a literal address | |
66 // which is always patchable. | |
67 break; | |
68 case relocInfo::external_word_type: | |
69 _rspec = external_word_Relocation::spec(target); | |
70 break; | |
71 case relocInfo::internal_word_type: | |
72 _rspec = internal_word_Relocation::spec(target); | |
73 break; | |
74 case relocInfo::opt_virtual_call_type: | |
75 _rspec = opt_virtual_call_Relocation::spec(); | |
76 break; | |
77 case relocInfo::static_call_type: | |
78 _rspec = static_call_Relocation::spec(); | |
79 break; | |
80 case relocInfo::runtime_call_type: | |
81 _rspec = runtime_call_Relocation::spec(); | |
82 break; | |
83 case relocInfo::poll_type: | |
84 case relocInfo::poll_return_type: | |
85 _rspec = Relocation::spec_simple(rtype); | |
86 break; | |
87 case relocInfo::none: | |
88 break; | |
89 default: | |
90 ShouldNotReachHere(); | |
91 break; | |
92 } | |
93 } | |
94 | |
95 // Implementation of Address | |
96 | |
304 | 97 #ifdef _LP64 |
98 | |
0 | 99 Address Address::make_array(ArrayAddress adr) { |
100 // Not implementable on 64bit machines | |
101 // Should have been handled higher up the call chain. | |
102 ShouldNotReachHere(); | |
304 | 103 return Address(); |
104 } | |
105 | |
106 // exceedingly dangerous constructor | |
107 Address::Address(int disp, address loc, relocInfo::relocType rtype) { | |
108 _base = noreg; | |
109 _index = noreg; | |
110 _scale = no_scale; | |
111 _disp = disp; | |
112 switch (rtype) { | |
113 case relocInfo::external_word_type: | |
114 _rspec = external_word_Relocation::spec(loc); | |
115 break; | |
116 case relocInfo::internal_word_type: | |
117 _rspec = internal_word_Relocation::spec(loc); | |
118 break; | |
119 case relocInfo::runtime_call_type: | |
120 // HMM | |
121 _rspec = runtime_call_Relocation::spec(); | |
122 break; | |
123 case relocInfo::poll_type: | |
124 case relocInfo::poll_return_type: | |
125 _rspec = Relocation::spec_simple(rtype); | |
126 break; | |
127 case relocInfo::none: | |
128 break; | |
129 default: | |
130 ShouldNotReachHere(); | |
131 } | |
132 } | |
133 #else // LP64 | |
134 | |
135 Address Address::make_array(ArrayAddress adr) { | |
0 | 136 AddressLiteral base = adr.base(); |
137 Address index = adr.index(); | |
138 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
139 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); | |
140 array._rspec = base._rspec; | |
141 return array; | |
304 | 142 } |
0 | 143 |
144 // exceedingly dangerous constructor | |
145 Address::Address(address loc, RelocationHolder spec) { | |
146 _base = noreg; | |
147 _index = noreg; | |
148 _scale = no_scale; | |
149 _disp = (intptr_t) loc; | |
150 _rspec = spec; | |
151 } | |
304 | 152 |
0 | 153 #endif // _LP64 |
154 | |
304 | 155 |
156 | |
0 | 157 // Convert the raw encoding form into the form expected by the constructor for |
158 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
159 // that to noreg for the Address constructor. | |
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160 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) { |
624 | 161 RelocationHolder rspec; |
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162 if (disp_reloc != relocInfo::none) { |
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163 rspec = Relocation::spec_simple(disp_reloc); |
624 | 164 } |
0 | 165 bool valid_index = index != rsp->encoding(); |
166 if (valid_index) { | |
167 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); | |
624 | 168 madr._rspec = rspec; |
0 | 169 return madr; |
170 } else { | |
171 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); | |
624 | 172 madr._rspec = rspec; |
0 | 173 return madr; |
174 } | |
175 } | |
176 | |
177 // Implementation of Assembler | |
178 | |
179 int AbstractAssembler::code_fill_byte() { | |
180 return (u_char)'\xF4'; // hlt | |
181 } | |
182 | |
183 // make this go away someday | |
184 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { | |
185 if (rtype == relocInfo::none) | |
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186 emit_int32(data); |
0 | 187 else emit_data(data, Relocation::spec_simple(rtype), format); |
188 } | |
189 | |
190 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { | |
304 | 191 assert(imm_operand == 0, "default format must be immediate in this file"); |
0 | 192 assert(inst_mark() != NULL, "must be inside InstructionMark"); |
193 if (rspec.type() != relocInfo::none) { | |
194 #ifdef ASSERT | |
195 check_relocation(rspec, format); | |
196 #endif | |
197 // Do not use AbstractAssembler::relocate, which is not intended for | |
198 // embedded words. Instead, relocate to the enclosing instruction. | |
199 | |
200 // hack. call32 is too wide for mask so use disp32 | |
201 if (format == call32_operand) | |
202 code_section()->relocate(inst_mark(), rspec, disp32_operand); | |
203 else | |
204 code_section()->relocate(inst_mark(), rspec, format); | |
205 } | |
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206 emit_int32(data); |
0 | 207 } |
208 | |
304 | 209 static int encode(Register r) { |
210 int enc = r->encoding(); | |
211 if (enc >= 8) { | |
212 enc -= 8; | |
213 } | |
214 return enc; | |
215 } | |
216 | |
0 | 217 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { |
218 assert(dst->has_byte_register(), "must have byte register"); | |
219 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
220 assert(isByte(imm8), "not a byte"); | |
221 assert((op1 & 0x01) == 0, "should be 8bit operation"); | |
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222 emit_int8(op1); |
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223 emit_int8(op2 | encode(dst)); |
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224 emit_int8(imm8); |
0 | 225 } |
226 | |
227 | |
304 | 228 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { |
0 | 229 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
230 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
231 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
232 if (is8bit(imm32)) { | |
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233 emit_int8(op1 | 0x02); // set sign bit |
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234 emit_int8(op2 | encode(dst)); |
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235 emit_int8(imm32 & 0xFF); |
0 | 236 } else { |
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237 emit_int8(op1); |
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238 emit_int8(op2 | encode(dst)); |
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239 emit_int32(imm32); |
0 | 240 } |
241 } | |
242 | |
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243 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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244 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { |
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245 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
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246 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
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247 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); |
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248 emit_int8(op1); |
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249 emit_int8(op2 | encode(dst)); |
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250 emit_int32(imm32); |
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251 } |
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252 |
0 | 253 // immediate-to-memory forms |
304 | 254 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { |
0 | 255 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
256 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
257 if (is8bit(imm32)) { | |
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258 emit_int8(op1 | 0x02); // set sign bit |
304 | 259 emit_operand(rm, adr, 1); |
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260 emit_int8(imm32 & 0xFF); |
0 | 261 } else { |
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262 emit_int8(op1); |
304 | 263 emit_operand(rm, adr, 4); |
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264 emit_int32(imm32); |
0 | 265 } |
266 } | |
267 | |
268 | |
269 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { | |
270 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
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271 emit_int8(op1); |
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272 emit_int8(op2 | encode(dst) << 3 | encode(src)); |
304 | 273 } |
274 | |
275 | |
276 void Assembler::emit_operand(Register reg, Register base, Register index, | |
277 Address::ScaleFactor scale, int disp, | |
278 RelocationHolder const& rspec, | |
279 int rip_relative_correction) { | |
0 | 280 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); |
304 | 281 |
282 // Encode the registers as needed in the fields they are used in | |
283 | |
284 int regenc = encode(reg) << 3; | |
285 int indexenc = index->is_valid() ? encode(index) << 3 : 0; | |
286 int baseenc = base->is_valid() ? encode(base) : 0; | |
287 | |
0 | 288 if (base->is_valid()) { |
289 if (index->is_valid()) { | |
290 assert(scale != Address::no_scale, "inconsistent address"); | |
291 // [base + index*scale + disp] | |
304 | 292 if (disp == 0 && rtype == relocInfo::none && |
293 base != rbp LP64_ONLY(&& base != r13)) { | |
0 | 294 // [base + index*scale] |
295 // [00 reg 100][ss index base] | |
296 assert(index != rsp, "illegal addressing mode"); | |
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297 emit_int8(0x04 | regenc); |
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298 emit_int8(scale << 6 | indexenc | baseenc); |
0 | 299 } else if (is8bit(disp) && rtype == relocInfo::none) { |
300 // [base + index*scale + imm8] | |
301 // [01 reg 100][ss index base] imm8 | |
302 assert(index != rsp, "illegal addressing mode"); | |
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303 emit_int8(0x44 | regenc); |
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304 emit_int8(scale << 6 | indexenc | baseenc); |
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305 emit_int8(disp & 0xFF); |
0 | 306 } else { |
304 | 307 // [base + index*scale + disp32] |
308 // [10 reg 100][ss index base] disp32 | |
0 | 309 assert(index != rsp, "illegal addressing mode"); |
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310 emit_int8(0x84 | regenc); |
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311 emit_int8(scale << 6 | indexenc | baseenc); |
0 | 312 emit_data(disp, rspec, disp32_operand); |
313 } | |
304 | 314 } else if (base == rsp LP64_ONLY(|| base == r12)) { |
315 // [rsp + disp] | |
0 | 316 if (disp == 0 && rtype == relocInfo::none) { |
304 | 317 // [rsp] |
0 | 318 // [00 reg 100][00 100 100] |
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319 emit_int8(0x04 | regenc); |
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320 emit_int8(0x24); |
0 | 321 } else if (is8bit(disp) && rtype == relocInfo::none) { |
304 | 322 // [rsp + imm8] |
323 // [01 reg 100][00 100 100] disp8 | |
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324 emit_int8(0x44 | regenc); |
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325 emit_int8(0x24); |
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326 emit_int8(disp & 0xFF); |
0 | 327 } else { |
304 | 328 // [rsp + imm32] |
329 // [10 reg 100][00 100 100] disp32 | |
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330 emit_int8(0x84 | regenc); |
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331 emit_int8(0x24); |
0 | 332 emit_data(disp, rspec, disp32_operand); |
333 } | |
334 } else { | |
335 // [base + disp] | |
304 | 336 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); |
337 if (disp == 0 && rtype == relocInfo::none && | |
338 base != rbp LP64_ONLY(&& base != r13)) { | |
0 | 339 // [base] |
340 // [00 reg base] | |
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341 emit_int8(0x00 | regenc | baseenc); |
0 | 342 } else if (is8bit(disp) && rtype == relocInfo::none) { |
304 | 343 // [base + disp8] |
344 // [01 reg base] disp8 | |
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345 emit_int8(0x40 | regenc | baseenc); |
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346 emit_int8(disp & 0xFF); |
0 | 347 } else { |
304 | 348 // [base + disp32] |
349 // [10 reg base] disp32 | |
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350 emit_int8(0x80 | regenc | baseenc); |
0 | 351 emit_data(disp, rspec, disp32_operand); |
352 } | |
353 } | |
354 } else { | |
355 if (index->is_valid()) { | |
356 assert(scale != Address::no_scale, "inconsistent address"); | |
357 // [index*scale + disp] | |
304 | 358 // [00 reg 100][ss index 101] disp32 |
0 | 359 assert(index != rsp, "illegal addressing mode"); |
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360 emit_int8(0x04 | regenc); |
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361 emit_int8(scale << 6 | indexenc | 0x05); |
0 | 362 emit_data(disp, rspec, disp32_operand); |
304 | 363 } else if (rtype != relocInfo::none ) { |
364 // [disp] (64bit) RIP-RELATIVE (32bit) abs | |
365 // [00 000 101] disp32 | |
366 | |
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367 emit_int8(0x05 | regenc); |
304 | 368 // Note that the RIP-rel. correction applies to the generated |
369 // disp field, but _not_ to the target address in the rspec. | |
370 | |
371 // disp was created by converting the target address minus the pc | |
372 // at the start of the instruction. That needs more correction here. | |
373 // intptr_t disp = target - next_ip; | |
374 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
375 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; | |
376 int64_t adjusted = disp; | |
377 // Do rip-rel adjustment for 64bit | |
378 LP64_ONLY(adjusted -= (next_ip - inst_mark())); | |
379 assert(is_simm32(adjusted), | |
380 "must be 32bit offset (RIP relative address)"); | |
381 emit_data((int32_t) adjusted, rspec, disp32_operand); | |
382 | |
0 | 383 } else { |
304 | 384 // 32bit never did this, did everything as the rip-rel/disp code above |
385 // [disp] ABSOLUTE | |
386 // [00 reg 100][00 100 101] disp32 | |
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387 emit_int8(0x04 | regenc); |
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388 emit_int8(0x25); |
0 | 389 emit_data(disp, rspec, disp32_operand); |
390 } | |
391 } | |
392 } | |
393 | |
304 | 394 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, |
395 Address::ScaleFactor scale, int disp, | |
396 RelocationHolder const& rspec) { | |
397 emit_operand((Register)reg, base, index, scale, disp, rspec); | |
398 } | |
399 | |
0 | 400 // Secret local extension to Assembler::WhichOperand: |
401 #define end_pc_operand (_WhichOperand_limit) | |
402 | |
403 address Assembler::locate_operand(address inst, WhichOperand which) { | |
404 // Decode the given instruction, and return the address of | |
405 // an embedded 32-bit operand word. | |
406 | |
407 // If "which" is disp32_operand, selects the displacement portion | |
408 // of an effective address specifier. | |
304 | 409 // If "which" is imm64_operand, selects the trailing immediate constant. |
0 | 410 // If "which" is call32_operand, selects the displacement of a call or jump. |
411 // Caller is responsible for ensuring that there is such an operand, | |
304 | 412 // and that it is 32/64 bits wide. |
0 | 413 |
414 // If "which" is end_pc_operand, find the end of the instruction. | |
415 | |
416 address ip = inst; | |
304 | 417 bool is_64bit = false; |
418 | |
419 debug_only(bool has_disp32 = false); | |
420 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn | |
421 | |
422 again_after_prefix: | |
0 | 423 switch (0xFF & *ip++) { |
424 | |
425 // These convenience macros generate groups of "case" labels for the switch. | |
304 | 426 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 |
427 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ | |
0 | 428 case (x)+4: case (x)+5: case (x)+6: case (x)+7 |
304 | 429 #define REP16(x) REP8((x)+0): \ |
0 | 430 case REP8((x)+8) |
431 | |
432 case CS_segment: | |
433 case SS_segment: | |
434 case DS_segment: | |
435 case ES_segment: | |
436 case FS_segment: | |
437 case GS_segment: | |
304 | 438 // Seems dubious |
439 LP64_ONLY(assert(false, "shouldn't have that prefix")); | |
0 | 440 assert(ip == inst+1, "only one prefix allowed"); |
441 goto again_after_prefix; | |
442 | |
304 | 443 case 0x67: |
444 case REX: | |
445 case REX_B: | |
446 case REX_X: | |
447 case REX_XB: | |
448 case REX_R: | |
449 case REX_RB: | |
450 case REX_RX: | |
451 case REX_RXB: | |
452 NOT_LP64(assert(false, "64bit prefixes")); | |
453 goto again_after_prefix; | |
454 | |
455 case REX_W: | |
456 case REX_WB: | |
457 case REX_WX: | |
458 case REX_WXB: | |
459 case REX_WR: | |
460 case REX_WRB: | |
461 case REX_WRX: | |
462 case REX_WRXB: | |
463 NOT_LP64(assert(false, "64bit prefixes")); | |
464 is_64bit = true; | |
465 goto again_after_prefix; | |
466 | |
467 case 0xFF: // pushq a; decl a; incl a; call a; jmp a | |
0 | 468 case 0x88: // movb a, r |
469 case 0x89: // movl a, r | |
470 case 0x8A: // movb r, a | |
471 case 0x8B: // movl r, a | |
472 case 0x8F: // popl a | |
304 | 473 debug_only(has_disp32 = true); |
0 | 474 break; |
475 | |
304 | 476 case 0x68: // pushq #32 |
477 if (which == end_pc_operand) { | |
478 return ip + 4; | |
479 } | |
480 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); | |
0 | 481 return ip; // not produced by emit_operand |
482 | |
483 case 0x66: // movw ... (size prefix) | |
304 | 484 again_after_size_prefix2: |
0 | 485 switch (0xFF & *ip++) { |
304 | 486 case REX: |
487 case REX_B: | |
488 case REX_X: | |
489 case REX_XB: | |
490 case REX_R: | |
491 case REX_RB: | |
492 case REX_RX: | |
493 case REX_RXB: | |
494 case REX_W: | |
495 case REX_WB: | |
496 case REX_WX: | |
497 case REX_WXB: | |
498 case REX_WR: | |
499 case REX_WRB: | |
500 case REX_WRX: | |
501 case REX_WRXB: | |
502 NOT_LP64(assert(false, "64bit prefix found")); | |
503 goto again_after_size_prefix2; | |
0 | 504 case 0x8B: // movw r, a |
505 case 0x89: // movw a, r | |
304 | 506 debug_only(has_disp32 = true); |
0 | 507 break; |
508 case 0xC7: // movw a, #16 | |
304 | 509 debug_only(has_disp32 = true); |
0 | 510 tail_size = 2; // the imm16 |
511 break; | |
512 case 0x0F: // several SSE/SSE2 variants | |
513 ip--; // reparse the 0x0F | |
514 goto again_after_prefix; | |
515 default: | |
516 ShouldNotReachHere(); | |
517 } | |
518 break; | |
519 | |
304 | 520 case REP8(0xB8): // movl/q r, #32/#64(oop?) |
521 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); | |
522 // these asserts are somewhat nonsensical | |
523 #ifndef _LP64 | |
5984 | 524 assert(which == imm_operand || which == disp32_operand, |
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525 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip))); |
304 | 526 #else |
527 assert((which == call32_operand || which == imm_operand) && is_64bit || | |
5984 | 528 which == narrow_oop_operand && !is_64bit, |
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529 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip))); |
304 | 530 #endif // _LP64 |
0 | 531 return ip; |
532 | |
533 case 0x69: // imul r, a, #32 | |
534 case 0xC7: // movl a, #32(oop?) | |
535 tail_size = 4; | |
304 | 536 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 537 break; |
538 | |
539 case 0x0F: // movx..., etc. | |
540 switch (0xFF & *ip++) { | |
4759 | 541 case 0x3A: // pcmpestri |
542 tail_size = 1; | |
543 case 0x38: // ptest, pmovzxbw | |
544 ip++; // skip opcode | |
545 debug_only(has_disp32 = true); // has both kinds of operands! | |
546 break; | |
547 | |
548 case 0x70: // pshufd r, r/a, #8 | |
549 debug_only(has_disp32 = true); // has both kinds of operands! | |
550 case 0x73: // psrldq r, #8 | |
551 tail_size = 1; | |
552 break; | |
553 | |
0 | 554 case 0x12: // movlps |
555 case 0x28: // movaps | |
556 case 0x2E: // ucomiss | |
557 case 0x2F: // comiss | |
558 case 0x54: // andps | |
559 case 0x55: // andnps | |
560 case 0x56: // orps | |
561 case 0x57: // xorps | |
562 case 0x6E: // movd | |
563 case 0x7E: // movd | |
4759 | 564 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush |
304 | 565 debug_only(has_disp32 = true); |
0 | 566 break; |
567 | |
568 case 0xAD: // shrd r, a, %cl | |
569 case 0xAF: // imul r, a | |
304 | 570 case 0xBE: // movsbl r, a (movsxb) |
571 case 0xBF: // movswl r, a (movsxw) | |
572 case 0xB6: // movzbl r, a (movzxb) | |
573 case 0xB7: // movzwl r, a (movzxw) | |
0 | 574 case REP16(0x40): // cmovl cc, r, a |
575 case 0xB0: // cmpxchgb | |
576 case 0xB1: // cmpxchg | |
577 case 0xC1: // xaddl | |
578 case 0xC7: // cmpxchg8 | |
579 case REP16(0x90): // setcc a | |
304 | 580 debug_only(has_disp32 = true); |
0 | 581 // fall out of the switch to decode the address |
582 break; | |
304 | 583 |
4759 | 584 case 0xC4: // pinsrw r, a, #8 |
585 debug_only(has_disp32 = true); | |
586 case 0xC5: // pextrw r, r, #8 | |
587 tail_size = 1; // the imm8 | |
588 break; | |
589 | |
0 | 590 case 0xAC: // shrd r, a, #8 |
304 | 591 debug_only(has_disp32 = true); |
0 | 592 tail_size = 1; // the imm8 |
593 break; | |
304 | 594 |
0 | 595 case REP16(0x80): // jcc rdisp32 |
596 if (which == end_pc_operand) return ip + 4; | |
304 | 597 assert(which == call32_operand, "jcc has no disp32 or imm"); |
0 | 598 return ip; |
599 default: | |
600 ShouldNotReachHere(); | |
601 } | |
602 break; | |
603 | |
604 case 0x81: // addl a, #32; addl r, #32 | |
605 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
304 | 606 // on 32bit in the case of cmpl, the imm might be an oop |
0 | 607 tail_size = 4; |
304 | 608 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 609 break; |
610 | |
611 case 0x83: // addl a, #8; addl r, #8 | |
612 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
304 | 613 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 614 tail_size = 1; |
615 break; | |
616 | |
617 case 0x9B: | |
618 switch (0xFF & *ip++) { | |
619 case 0xD9: // fnstcw a | |
304 | 620 debug_only(has_disp32 = true); |
0 | 621 break; |
622 default: | |
623 ShouldNotReachHere(); | |
624 } | |
625 break; | |
626 | |
627 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a | |
628 case REP4(0x10): // adc... | |
629 case REP4(0x20): // and... | |
630 case REP4(0x30): // xor... | |
631 case REP4(0x08): // or... | |
632 case REP4(0x18): // sbb... | |
633 case REP4(0x28): // sub... | |
304 | 634 case 0xF7: // mull a |
635 case 0x8D: // lea r, a | |
636 case 0x87: // xchg r, a | |
0 | 637 case REP4(0x38): // cmp... |
304 | 638 case 0x85: // test r, a |
639 debug_only(has_disp32 = true); // has both kinds of operands! | |
0 | 640 break; |
641 | |
642 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 | |
643 case 0xC6: // movb a, #8 | |
644 case 0x80: // cmpb a, #8 | |
645 case 0x6B: // imul r, a, #8 | |
304 | 646 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 647 tail_size = 1; // the imm8 |
648 break; | |
649 | |
4759 | 650 case 0xC4: // VEX_3bytes |
651 case 0xC5: // VEX_2bytes | |
652 assert((UseAVX > 0), "shouldn't have VEX prefix"); | |
653 assert(ip == inst+1, "no prefixes allowed"); | |
654 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions | |
655 // but they have prefix 0x0F and processed when 0x0F processed above. | |
656 // | |
657 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES | |
658 // instructions (these instructions are not supported in 64-bit mode). | |
659 // To distinguish them bits [7:6] are set in the VEX second byte since | |
660 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set | |
661 // those VEX bits REX and vvvv bits are inverted. | |
662 // | |
663 // Fortunately C2 doesn't generate these instructions so we don't need | |
664 // to check for them in product version. | |
665 | |
666 // Check second byte | |
667 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); | |
668 | |
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669 int vex_opcode; |
4759 | 670 // First byte |
671 if ((0xFF & *inst) == VEX_3bytes) { | |
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672 vex_opcode = VEX_OPCODE_MASK & *ip; |
4759 | 673 ip++; // third byte |
674 is_64bit = ((VEX_W & *ip) == VEX_W); | |
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675 } else { |
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676 vex_opcode = VEX_OPCODE_0F; |
4759 | 677 } |
678 ip++; // opcode | |
679 // To find the end of instruction (which == end_pc_operand). | |
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680 switch (vex_opcode) { |
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681 case VEX_OPCODE_0F: |
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682 switch (0xFF & *ip) { |
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683 case 0x70: // pshufd r, r/a, #8 |
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684 case 0x71: // ps[rl|ra|ll]w r, #8 |
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685 case 0x72: // ps[rl|ra|ll]d r, #8 |
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686 case 0x73: // ps[rl|ra|ll]q r, #8 |
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687 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8 |
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688 case 0xC4: // pinsrw r, r, r/a, #8 |
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689 case 0xC5: // pextrw r/a, r, #8 |
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690 case 0xC6: // shufp[s|d] r, r, r/a, #8 |
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691 tail_size = 1; // the imm8 |
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692 break; |
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693 } |
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694 break; |
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695 case VEX_OPCODE_0F_3A: |
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696 tail_size = 1; |
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697 break; |
4759 | 698 } |
699 ip++; // skip opcode | |
700 debug_only(has_disp32 = true); // has both kinds of operands! | |
701 break; | |
0 | 702 |
703 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | |
704 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | |
705 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | |
706 case 0xDD: // fld_d a; fst_d a; fstp_d a | |
707 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a | |
708 case 0xDF: // fild_d a; fistp_d a | |
709 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | |
710 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | |
711 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | |
304 | 712 debug_only(has_disp32 = true); |
0 | 713 break; |
714 | |
4759 | 715 case 0xE8: // call rdisp32 |
716 case 0xE9: // jmp rdisp32 | |
717 if (which == end_pc_operand) return ip + 4; | |
718 assert(which == call32_operand, "call has no disp32 or imm"); | |
719 return ip; | |
720 | |
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721 case 0xF0: // Lock |
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722 assert(os::is_MP(), "only on MP"); |
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723 goto again_after_prefix; |
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724 |
0 | 725 case 0xF3: // For SSE |
726 case 0xF2: // For SSE2 | |
304 | 727 switch (0xFF & *ip++) { |
728 case REX: | |
729 case REX_B: | |
730 case REX_X: | |
731 case REX_XB: | |
732 case REX_R: | |
733 case REX_RB: | |
734 case REX_RX: | |
735 case REX_RXB: | |
736 case REX_W: | |
737 case REX_WB: | |
738 case REX_WX: | |
739 case REX_WXB: | |
740 case REX_WR: | |
741 case REX_WRB: | |
742 case REX_WRX: | |
743 case REX_WRXB: | |
744 NOT_LP64(assert(false, "found 64bit prefix")); | |
745 ip++; | |
746 default: | |
747 ip++; | |
748 } | |
749 debug_only(has_disp32 = true); // has both kinds of operands! | |
0 | 750 break; |
751 | |
752 default: | |
753 ShouldNotReachHere(); | |
754 | |
304 | 755 #undef REP8 |
756 #undef REP16 | |
0 | 757 } |
758 | |
759 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); | |
304 | 760 #ifdef _LP64 |
761 assert(which != imm_operand, "instruction is not a movq reg, imm64"); | |
762 #else | |
763 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); | |
764 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); | |
765 #endif // LP64 | |
766 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); | |
0 | 767 |
768 // parse the output of emit_operand | |
769 int op2 = 0xFF & *ip++; | |
770 int base = op2 & 0x07; | |
771 int op3 = -1; | |
772 const int b100 = 4; | |
773 const int b101 = 5; | |
774 if (base == b100 && (op2 >> 6) != 3) { | |
775 op3 = 0xFF & *ip++; | |
776 base = op3 & 0x07; // refetch the base | |
777 } | |
778 // now ip points at the disp (if any) | |
779 | |
780 switch (op2 >> 6) { | |
781 case 0: | |
782 // [00 reg 100][ss index base] | |
304 | 783 // [00 reg 100][00 100 esp] |
0 | 784 // [00 reg base] |
785 // [00 reg 100][ss index 101][disp32] | |
786 // [00 reg 101] [disp32] | |
787 | |
788 if (base == b101) { | |
789 if (which == disp32_operand) | |
790 return ip; // caller wants the disp32 | |
791 ip += 4; // skip the disp32 | |
792 } | |
793 break; | |
794 | |
795 case 1: | |
796 // [01 reg 100][ss index base][disp8] | |
304 | 797 // [01 reg 100][00 100 esp][disp8] |
0 | 798 // [01 reg base] [disp8] |
799 ip += 1; // skip the disp8 | |
800 break; | |
801 | |
802 case 2: | |
803 // [10 reg 100][ss index base][disp32] | |
304 | 804 // [10 reg 100][00 100 esp][disp32] |
0 | 805 // [10 reg base] [disp32] |
806 if (which == disp32_operand) | |
807 return ip; // caller wants the disp32 | |
808 ip += 4; // skip the disp32 | |
809 break; | |
810 | |
811 case 3: | |
812 // [11 reg base] (not a memory addressing mode) | |
813 break; | |
814 } | |
815 | |
816 if (which == end_pc_operand) { | |
817 return ip + tail_size; | |
818 } | |
819 | |
304 | 820 #ifdef _LP64 |
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821 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); |
304 | 822 #else |
823 assert(which == imm_operand, "instruction has only an imm field"); | |
824 #endif // LP64 | |
0 | 825 return ip; |
826 } | |
827 | |
828 address Assembler::locate_next_instruction(address inst) { | |
829 // Secretly share code with locate_operand: | |
830 return locate_operand(inst, end_pc_operand); | |
831 } | |
832 | |
833 | |
834 #ifdef ASSERT | |
835 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { | |
836 address inst = inst_mark(); | |
837 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); | |
838 address opnd; | |
839 | |
840 Relocation* r = rspec.reloc(); | |
841 if (r->type() == relocInfo::none) { | |
842 return; | |
843 } else if (r->is_call() || format == call32_operand) { | |
844 // assert(format == imm32_operand, "cannot specify a nonzero format"); | |
845 opnd = locate_operand(inst, call32_operand); | |
846 } else if (r->is_data()) { | |
304 | 847 assert(format == imm_operand || format == disp32_operand |
848 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); | |
0 | 849 opnd = locate_operand(inst, (WhichOperand)format); |
850 } else { | |
304 | 851 assert(format == imm_operand, "cannot specify a format"); |
0 | 852 return; |
853 } | |
854 assert(opnd == pc(), "must put operand where relocs can find it"); | |
855 } | |
304 | 856 #endif // ASSERT |
857 | |
858 void Assembler::emit_operand32(Register reg, Address adr) { | |
859 assert(reg->encoding() < 8, "no extended registers"); | |
860 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
861 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
862 adr._rspec); | |
863 } | |
864 | |
865 void Assembler::emit_operand(Register reg, Address adr, | |
866 int rip_relative_correction) { | |
867 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
868 adr._rspec, | |
869 rip_relative_correction); | |
870 } | |
871 | |
872 void Assembler::emit_operand(XMMRegister reg, Address adr) { | |
873 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
874 adr._rspec); | |
875 } | |
876 | |
877 // MMX operations | |
878 void Assembler::emit_operand(MMXRegister reg, Address adr) { | |
879 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
880 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
881 } | |
882 | |
883 // work around gcc (3.2.1-7a) bug | |
884 void Assembler::emit_operand(Address adr, MMXRegister reg) { | |
885 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
886 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
0 | 887 } |
888 | |
889 | |
890 void Assembler::emit_farith(int b1, int b2, int i) { | |
891 assert(isByte(b1) && isByte(b2), "wrong opcode"); | |
892 assert(0 <= i && i < 8, "illegal stack offset"); | |
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893 emit_int8(b1); |
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894 emit_int8(b2 + i); |
0 | 895 } |
896 | |
897 | |
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898 // Now the Assembler instructions (identical for 32/64 bits) |
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899 |
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900 void Assembler::adcl(Address dst, int32_t imm32) { |
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901 InstructionMark im(this); |
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902 prefix(dst); |
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903 emit_arith_operand(0x81, rdx, dst, imm32); |
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904 } |
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905 |
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906 void Assembler::adcl(Address dst, Register src) { |
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907 InstructionMark im(this); |
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908 prefix(dst, src); |
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909 emit_int8(0x11); |
2100
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910 emit_operand(src, dst); |
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911 } |
304 | 912 |
913 void Assembler::adcl(Register dst, int32_t imm32) { | |
914 prefix(dst); | |
0 | 915 emit_arith(0x81, 0xD0, dst, imm32); |
916 } | |
917 | |
918 void Assembler::adcl(Register dst, Address src) { | |
919 InstructionMark im(this); | |
304 | 920 prefix(src, dst); |
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921 emit_int8(0x13); |
0 | 922 emit_operand(dst, src); |
923 } | |
924 | |
925 void Assembler::adcl(Register dst, Register src) { | |
304 | 926 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
0 | 927 emit_arith(0x13, 0xC0, dst, src); |
928 } | |
929 | |
304 | 930 void Assembler::addl(Address dst, int32_t imm32) { |
931 InstructionMark im(this); | |
932 prefix(dst); | |
933 emit_arith_operand(0x81, rax, dst, imm32); | |
934 } | |
0 | 935 |
936 void Assembler::addl(Address dst, Register src) { | |
937 InstructionMark im(this); | |
304 | 938 prefix(dst, src); |
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939 emit_int8(0x01); |
0 | 940 emit_operand(src, dst); |
941 } | |
942 | |
304 | 943 void Assembler::addl(Register dst, int32_t imm32) { |
944 prefix(dst); | |
0 | 945 emit_arith(0x81, 0xC0, dst, imm32); |
946 } | |
947 | |
948 void Assembler::addl(Register dst, Address src) { | |
949 InstructionMark im(this); | |
304 | 950 prefix(src, dst); |
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951 emit_int8(0x03); |
0 | 952 emit_operand(dst, src); |
953 } | |
954 | |
955 void Assembler::addl(Register dst, Register src) { | |
304 | 956 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
0 | 957 emit_arith(0x03, 0xC0, dst, src); |
958 } | |
959 | |
960 void Assembler::addr_nop_4() { | |
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961 assert(UseAddressNop, "no CPU support"); |
0 | 962 // 4 bytes: NOP DWORD PTR [EAX+0] |
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963 emit_int8(0x0F); |
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964 emit_int8(0x1F); |
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965 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); |
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966 emit_int8(0); // 8-bits offset (1 byte) |
0 | 967 } |
968 | |
969 void Assembler::addr_nop_5() { | |
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970 assert(UseAddressNop, "no CPU support"); |
0 | 971 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset |
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972 emit_int8(0x0F); |
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973 emit_int8(0x1F); |
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974 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); |
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975 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); |
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976 emit_int8(0); // 8-bits offset (1 byte) |
0 | 977 } |
978 | |
979 void Assembler::addr_nop_7() { | |
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980 assert(UseAddressNop, "no CPU support"); |
0 | 981 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset |
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982 emit_int8(0x0F); |
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983 emit_int8(0x1F); |
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984 emit_int8((unsigned char)0x80); |
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985 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); |
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986 emit_int32(0); // 32-bits offset (4 bytes) |
0 | 987 } |
988 | |
989 void Assembler::addr_nop_8() { | |
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990 assert(UseAddressNop, "no CPU support"); |
0 | 991 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset |
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992 emit_int8(0x0F); |
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993 emit_int8(0x1F); |
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994 emit_int8((unsigned char)0x84); |
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995 // emit_rm(cbuf, 0x2, EAX_enc, 0x4); |
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996 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); |
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997 emit_int32(0); // 32-bits offset (4 bytes) |
0 | 998 } |
999 | |
304 | 1000 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
1001 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1002 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2); |
304 | 1003 } |
1004 | |
1005 void Assembler::addsd(XMMRegister dst, Address src) { | |
1006 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1007 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2); |
304 | 1008 } |
1009 | |
1010 void Assembler::addss(XMMRegister dst, XMMRegister src) { | |
1011 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1012 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3); |
304 | 1013 } |
1014 | |
1015 void Assembler::addss(XMMRegister dst, Address src) { | |
1016 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1017 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3); |
304 | 1018 } |
1019 | |
6894 | 1020 void Assembler::aesdec(XMMRegister dst, Address src) { |
1021 assert(VM_Version::supports_aes(), ""); | |
1022 InstructionMark im(this); | |
1023 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1024 emit_int8((unsigned char)0xDE); |
6894 | 1025 emit_operand(dst, src); |
1026 } | |
1027 | |
1028 void Assembler::aesdec(XMMRegister dst, XMMRegister src) { | |
1029 assert(VM_Version::supports_aes(), ""); | |
1030 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1031 emit_int8((unsigned char)0xDE); |
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1032 emit_int8(0xC0 | encode); |
6894 | 1033 } |
1034 | |
1035 void Assembler::aesdeclast(XMMRegister dst, Address src) { | |
1036 assert(VM_Version::supports_aes(), ""); | |
1037 InstructionMark im(this); | |
1038 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1039 emit_int8((unsigned char)0xDF); |
6894 | 1040 emit_operand(dst, src); |
1041 } | |
1042 | |
1043 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) { | |
1044 assert(VM_Version::supports_aes(), ""); | |
1045 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1046 emit_int8((unsigned char)0xDF); |
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1047 emit_int8((unsigned char)(0xC0 | encode)); |
6894 | 1048 } |
1049 | |
1050 void Assembler::aesenc(XMMRegister dst, Address src) { | |
1051 assert(VM_Version::supports_aes(), ""); | |
1052 InstructionMark im(this); | |
1053 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1054 emit_int8((unsigned char)0xDC); |
6894 | 1055 emit_operand(dst, src); |
1056 } | |
1057 | |
1058 void Assembler::aesenc(XMMRegister dst, XMMRegister src) { | |
1059 assert(VM_Version::supports_aes(), ""); | |
1060 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1061 emit_int8((unsigned char)0xDC); |
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1062 emit_int8(0xC0 | encode); |
6894 | 1063 } |
1064 | |
1065 void Assembler::aesenclast(XMMRegister dst, Address src) { | |
1066 assert(VM_Version::supports_aes(), ""); | |
1067 InstructionMark im(this); | |
1068 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1069 emit_int8((unsigned char)0xDD); |
6894 | 1070 emit_operand(dst, src); |
1071 } | |
1072 | |
1073 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { | |
1074 assert(VM_Version::supports_aes(), ""); | |
1075 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1076 emit_int8((unsigned char)0xDD); |
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1077 emit_int8((unsigned char)(0xC0 | encode)); |
6894 | 1078 } |
1079 | |
1080 | |
4759 | 1081 void Assembler::andl(Address dst, int32_t imm32) { |
1082 InstructionMark im(this); | |
1083 prefix(dst); | |
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1084 emit_int8((unsigned char)0x81); |
4759 | 1085 emit_operand(rsp, dst, 4); |
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1086 emit_int32(imm32); |
4759 | 1087 } |
1088 | |
304 | 1089 void Assembler::andl(Register dst, int32_t imm32) { |
1090 prefix(dst); | |
1091 emit_arith(0x81, 0xE0, dst, imm32); | |
1092 } | |
1093 | |
1094 void Assembler::andl(Register dst, Address src) { | |
1095 InstructionMark im(this); | |
1096 prefix(src, dst); | |
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1097 emit_int8(0x23); |
304 | 1098 emit_operand(dst, src); |
1099 } | |
1100 | |
1101 void Assembler::andl(Register dst, Register src) { | |
1102 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
1103 emit_arith(0x23, 0xC0, dst, src); | |
1104 } | |
1105 | |
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1106 void Assembler::andnl(Register dst, Register src1, Register src2) { |
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1107 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); |
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1108 int encode = vex_prefix_0F38_and_encode(dst, src1, src2); |
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1109 emit_int8((unsigned char)0xF2); |
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1110 emit_int8((unsigned char)(0xC0 | encode)); |
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1111 } |
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1112 |
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1113 void Assembler::andnl(Register dst, Register src1, Address src2) { |
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1114 InstructionMark im(this); |
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1115 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); |
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1116 vex_prefix_0F38(dst, src1, src2); |
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1117 emit_int8((unsigned char)0xF2); |
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1118 emit_operand(dst, src2); |
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1119 } |
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1120 |
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1121 void Assembler::bsfl(Register dst, Register src) { |
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1122 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1123 emit_int8(0x0F); |
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1124 emit_int8((unsigned char)0xBC); |
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1125 emit_int8((unsigned char)(0xC0 | encode)); |
775
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1126 } |
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1127 |
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1128 void Assembler::bsrl(Register dst, Register src) { |
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1129 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1130 emit_int8(0x0F); |
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1131 emit_int8((unsigned char)0xBD); |
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1132 emit_int8((unsigned char)(0xC0 | encode)); |
775
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1133 } |
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1134 |
304 | 1135 void Assembler::bswapl(Register reg) { // bswap |
1136 int encode = prefix_and_encode(reg->encoding()); | |
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1137 emit_int8(0x0F); |
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1138 emit_int8((unsigned char)(0xC8 | encode)); |
304 | 1139 } |
1140 | |
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1141 void Assembler::blsil(Register dst, Register src) { |
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1142 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); |
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1143 int encode = vex_prefix_0F38_and_encode(rbx, dst, src); |
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1144 emit_int8((unsigned char)0xF3); |
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1145 emit_int8((unsigned char)(0xC0 | encode)); |
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1146 } |
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1147 |
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1148 void Assembler::blsil(Register dst, Address src) { |
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1149 InstructionMark im(this); |
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1150 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); |
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1151 vex_prefix_0F38(rbx, dst, src); |
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1152 emit_int8((unsigned char)0xF3); |
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1153 emit_operand(rbx, src); |
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1154 } |
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1155 |
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1156 void Assembler::blsmskl(Register dst, Register src) { |
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1157 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); |
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1158 int encode = vex_prefix_0F38_and_encode(rdx, dst, src); |
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1159 emit_int8((unsigned char)0xF3); |
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1160 emit_int8((unsigned char)(0xC0 | encode)); |
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1161 } |
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1162 |
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1163 void Assembler::blsmskl(Register dst, Address src) { |
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1164 InstructionMark im(this); |
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1165 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); |
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1166 vex_prefix_0F38(rdx, dst, src); |
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1167 emit_int8((unsigned char)0xF3); |
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1168 emit_operand(rdx, src); |
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1169 } |
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1170 |
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1171 void Assembler::blsrl(Register dst, Register src) { |
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1172 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); |
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1173 int encode = vex_prefix_0F38_and_encode(rcx, dst, src); |
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1174 emit_int8((unsigned char)0xF3); |
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1175 emit_int8((unsigned char)(0xC0 | encode)); |
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1176 } |
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1177 |
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1178 void Assembler::blsrl(Register dst, Address src) { |
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1179 InstructionMark im(this); |
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1180 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); |
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1181 vex_prefix_0F38(rcx, dst, src); |
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1182 emit_int8((unsigned char)0xF3); |
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1183 emit_operand(rcx, src); |
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1184 } |
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1185 |
304 | 1186 void Assembler::call(Label& L, relocInfo::relocType rtype) { |
1187 // suspect disp32 is always good | |
1188 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); | |
1189 | |
1190 if (L.is_bound()) { | |
1191 const int long_size = 5; | |
1192 int offs = (int)( target(L) - pc() ); | |
1193 assert(offs <= 0, "assembler error"); | |
1194 InstructionMark im(this); | |
1195 // 1110 1000 #32-bit disp | |
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1196 emit_int8((unsigned char)0xE8); |
304 | 1197 emit_data(offs - long_size, rtype, operand); |
1198 } else { | |
1199 InstructionMark im(this); | |
1200 // 1110 1000 #32-bit disp | |
1201 L.add_patch_at(code(), locator()); | |
1202 | |
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1203 emit_int8((unsigned char)0xE8); |
304 | 1204 emit_data(int(0), rtype, operand); |
1205 } | |
1206 } | |
1207 | |
1208 void Assembler::call(Register dst) { | |
4759 | 1209 int encode = prefix_and_encode(dst->encoding()); |
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1210 emit_int8((unsigned char)0xFF); |
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1211 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 1212 } |
1213 | |
1214 | |
1215 void Assembler::call(Address adr) { | |
1216 InstructionMark im(this); | |
1217 prefix(adr); | |
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1218 emit_int8((unsigned char)0xFF); |
304 | 1219 emit_operand(rdx, adr); |
1220 } | |
1221 | |
1222 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { | |
1223 assert(entry != NULL, "call most probably wrong"); | |
1224 InstructionMark im(this); | |
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1225 emit_int8((unsigned char)0xE8); |
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1226 intptr_t disp = entry - (pc() + sizeof(int32_t)); |
304 | 1227 assert(is_simm32(disp), "must be 32bit offset (call2)"); |
1228 // Technically, should use call32_operand, but this format is | |
1229 // implied by the fact that we're emitting a call instruction. | |
1230 | |
1231 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); | |
1232 emit_data((int) disp, rspec, operand); | |
1233 } | |
1234 | |
1235 void Assembler::cdql() { | |
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1236 emit_int8((unsigned char)0x99); |
304 | 1237 } |
1238 | |
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1239 void Assembler::cld() { |
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1240 emit_int8((unsigned char)0xFC); |
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1241 } |
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1242 |
304 | 1243 void Assembler::cmovl(Condition cc, Register dst, Register src) { |
1244 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
1245 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1246 emit_int8(0x0F); |
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1247 emit_int8(0x40 | cc); |
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1248 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1249 } |
1250 | |
1251 | |
1252 void Assembler::cmovl(Condition cc, Register dst, Address src) { | |
1253 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
1254 prefix(src, dst); | |
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1255 emit_int8(0x0F); |
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1256 emit_int8(0x40 | cc); |
304 | 1257 emit_operand(dst, src); |
1258 } | |
1259 | |
1260 void Assembler::cmpb(Address dst, int imm8) { | |
1261 InstructionMark im(this); | |
1262 prefix(dst); | |
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1263 emit_int8((unsigned char)0x80); |
304 | 1264 emit_operand(rdi, dst, 1); |
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1265 emit_int8(imm8); |
304 | 1266 } |
1267 | |
1268 void Assembler::cmpl(Address dst, int32_t imm32) { | |
1269 InstructionMark im(this); | |
1270 prefix(dst); | |
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1271 emit_int8((unsigned char)0x81); |
304 | 1272 emit_operand(rdi, dst, 4); |
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1273 emit_int32(imm32); |
304 | 1274 } |
1275 | |
1276 void Assembler::cmpl(Register dst, int32_t imm32) { | |
1277 prefix(dst); | |
1278 emit_arith(0x81, 0xF8, dst, imm32); | |
1279 } | |
1280 | |
1281 void Assembler::cmpl(Register dst, Register src) { | |
1282 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
1283 emit_arith(0x3B, 0xC0, dst, src); | |
1284 } | |
1285 | |
1286 | |
1287 void Assembler::cmpl(Register dst, Address src) { | |
1288 InstructionMark im(this); | |
1289 prefix(src, dst); | |
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1290 emit_int8((unsigned char)0x3B); |
304 | 1291 emit_operand(dst, src); |
1292 } | |
1293 | |
1294 void Assembler::cmpw(Address dst, int imm16) { | |
1295 InstructionMark im(this); | |
1296 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); | |
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1297 emit_int8(0x66); |
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1298 emit_int8((unsigned char)0x81); |
304 | 1299 emit_operand(rdi, dst, 2); |
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1300 emit_int16(imm16); |
304 | 1301 } |
1302 | |
1303 // The 32-bit cmpxchg compares the value at adr with the contents of rax, | |
1304 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | |
1305 // The ZF is set if the compared values were equal, and cleared otherwise. | |
1306 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg | |
6834 | 1307 InstructionMark im(this); |
1308 prefix(adr, reg); | |
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1309 emit_int8(0x0F); |
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1310 emit_int8((unsigned char)0xB1); |
6834 | 1311 emit_operand(reg, adr); |
304 | 1312 } |
1313 | |
1314 void Assembler::comisd(XMMRegister dst, Address src) { | |
1315 // NOTE: dbx seems to decode this as comiss even though the | |
1316 // 0x66 is there. Strangly ucomisd comes out correct | |
1317 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1318 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66); |
4759 | 1319 } |
1320 | |
1321 void Assembler::comisd(XMMRegister dst, XMMRegister src) { | |
1322 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1323 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66); |
304 | 1324 } |
1325 | |
1326 void Assembler::comiss(XMMRegister dst, Address src) { | |
1327 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1328 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE); |
304 | 1329 } |
1330 | |
4759 | 1331 void Assembler::comiss(XMMRegister dst, XMMRegister src) { |
1332 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1333 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE); |
4759 | 1334 } |
1335 | |
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1336 void Assembler::cpuid() { |
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1337 emit_int8(0x0F); |
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1338 emit_int8((unsigned char)0xA2); |
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1339 } |
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1340 |
304 | 1341 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { |
1342 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1343 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3); |
304 | 1344 } |
1345 | |
1346 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | |
1347 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1348 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE); |
304 | 1349 } |
1350 | |
1351 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | |
1352 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1353 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2); |
304 | 1354 } |
1355 | |
4759 | 1356 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { |
1357 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1358 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2); |
4759 | 1359 } |
1360 | |
304 | 1361 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { |
1362 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 1363 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
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1364 emit_int8(0x2A); |
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1365 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1366 } |
1367 | |
4759 | 1368 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { |
1369 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1370 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2); |
4759 | 1371 } |
1372 | |
304 | 1373 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { |
1374 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4759 | 1375 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
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1376 emit_int8(0x2A); |
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1377 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1378 } |
1379 | |
4759 | 1380 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { |
1381 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1382 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3); |
4759 | 1383 } |
1384 | |
304 | 1385 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { |
1386 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1387 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3); |
304 | 1388 } |
1389 | |
4759 | 1390 void Assembler::cvtss2sd(XMMRegister dst, Address src) { |
1391 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1392 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3); |
4759 | 1393 } |
1394 | |
1395 | |
304 | 1396 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { |
1397 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 1398 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); |
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1399 emit_int8(0x2C); |
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1400 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1401 } |
1402 | |
1403 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | |
1404 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4759 | 1405 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
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1406 emit_int8(0x2C); |
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1407 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1408 } |
1409 | |
1410 void Assembler::decl(Address dst) { | |
1411 // Don't use it directly. Use MacroAssembler::decrement() instead. | |
1412 InstructionMark im(this); | |
1413 prefix(dst); | |
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1414 emit_int8((unsigned char)0xFF); |
304 | 1415 emit_operand(rcx, dst); |
1416 } | |
1417 | |
1418 void Assembler::divsd(XMMRegister dst, Address src) { | |
1419 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1420 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2); |
304 | 1421 } |
1422 | |
1423 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | |
1424 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1425 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2); |
304 | 1426 } |
1427 | |
1428 void Assembler::divss(XMMRegister dst, Address src) { | |
1429 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1430 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); |
304 | 1431 } |
1432 | |
1433 void Assembler::divss(XMMRegister dst, XMMRegister src) { | |
1434 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1435 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); |
304 | 1436 } |
1437 | |
1438 void Assembler::emms() { | |
1439 NOT_LP64(assert(VM_Version::supports_mmx(), "")); | |
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1440 emit_int8(0x0F); |
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1441 emit_int8(0x77); |
304 | 1442 } |
1443 | |
1444 void Assembler::hlt() { | |
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1445 emit_int8((unsigned char)0xF4); |
304 | 1446 } |
1447 | |
1448 void Assembler::idivl(Register src) { | |
1449 int encode = prefix_and_encode(src->encoding()); | |
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1450 emit_int8((unsigned char)0xF7); |
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1451 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 1452 } |
1453 | |
1920 | 1454 void Assembler::divl(Register src) { // Unsigned |
1455 int encode = prefix_and_encode(src->encoding()); | |
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1456 emit_int8((unsigned char)0xF7); |
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1457 emit_int8((unsigned char)(0xF0 | encode)); |
1920 | 1458 } |
1459 | |
304 | 1460 void Assembler::imull(Register dst, Register src) { |
1461 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1462 emit_int8(0x0F); |
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1463 emit_int8((unsigned char)0xAF); |
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1464 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1465 } |
1466 | |
1467 | |
1468 void Assembler::imull(Register dst, Register src, int value) { | |
1469 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1470 if (is8bit(value)) { | |
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1471 emit_int8(0x6B); |
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1472 emit_int8((unsigned char)(0xC0 | encode)); |
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1473 emit_int8(value & 0xFF); |
304 | 1474 } else { |
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1475 emit_int8(0x69); |
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1476 emit_int8((unsigned char)(0xC0 | encode)); |
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1477 emit_int32(value); |
304 | 1478 } |
1479 } | |
1480 | |
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1481 void Assembler::imull(Register dst, Address src) { |
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1482 InstructionMark im(this); |
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1483 prefix(src, dst); |
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1484 emit_int8(0x0F); |
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1485 emit_int8((unsigned char) 0xAF); |
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1486 emit_operand(dst, src); |
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1487 } |
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1488 |
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1489 |
304 | 1490 void Assembler::incl(Address dst) { |
1491 // Don't use it directly. Use MacroAssembler::increment() instead. | |
1492 InstructionMark im(this); | |
1493 prefix(dst); | |
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1494 emit_int8((unsigned char)0xFF); |
304 | 1495 emit_operand(rax, dst); |
1496 } | |
1497 | |
3851 | 1498 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { |
1499 InstructionMark im(this); | |
304 | 1500 assert((0 <= cc) && (cc < 16), "illegal cc"); |
1501 if (L.is_bound()) { | |
1502 address dst = target(L); | |
1503 assert(dst != NULL, "jcc most probably wrong"); | |
1504 | |
1505 const int short_size = 2; | |
1506 const int long_size = 6; | |
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1507 intptr_t offs = (intptr_t)dst - (intptr_t)pc(); |
3851 | 1508 if (maybe_short && is8bit(offs - short_size)) { |
304 | 1509 // 0111 tttn #8-bit disp |
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1510 emit_int8(0x70 | cc); |
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1511 emit_int8((offs - short_size) & 0xFF); |
304 | 1512 } else { |
1513 // 0000 1111 1000 tttn #32-bit disp | |
1514 assert(is_simm32(offs - long_size), | |
1515 "must be 32bit offset (call4)"); | |
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1516 emit_int8(0x0F); |
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1517 emit_int8((unsigned char)(0x80 | cc)); |
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1518 emit_int32(offs - long_size); |
304 | 1519 } |
1520 } else { | |
1521 // Note: could eliminate cond. jumps to this jump if condition | |
1522 // is the same however, seems to be rather unlikely case. | |
1523 // Note: use jccb() if label to be bound is very close to get | |
1524 // an 8-bit displacement | |
1525 L.add_patch_at(code(), locator()); | |
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1526 emit_int8(0x0F); |
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1527 emit_int8((unsigned char)(0x80 | cc)); |
7476
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1528 emit_int32(0); |
304 | 1529 } |
1530 } | |
1531 | |
1532 void Assembler::jccb(Condition cc, Label& L) { | |
1533 if (L.is_bound()) { | |
1534 const int short_size = 2; | |
1535 address entry = target(L); | |
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1536 #ifdef ASSERT |
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1537 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); |
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1538 intptr_t delta = short_branch_delta(); |
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1539 if (delta != 0) { |
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1540 dist += (dist < 0 ? (-delta) :delta); |
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1541 } |
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1542 assert(is8bit(dist), "Dispacement too large for a short jmp"); |
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1543 #endif |
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1544 intptr_t offs = (intptr_t)entry - (intptr_t)pc(); |
304 | 1545 // 0111 tttn #8-bit disp |
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1546 emit_int8(0x70 | cc); |
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1547 emit_int8((offs - short_size) & 0xFF); |
304 | 1548 } else { |
1549 InstructionMark im(this); | |
1550 L.add_patch_at(code(), locator()); | |
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1551 emit_int8(0x70 | cc); |
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1552 emit_int8(0); |
304 | 1553 } |
1554 } | |
1555 | |
1556 void Assembler::jmp(Address adr) { | |
1557 InstructionMark im(this); | |
1558 prefix(adr); | |
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1559 emit_int8((unsigned char)0xFF); |
304 | 1560 emit_operand(rsp, adr); |
1561 } | |
1562 | |
3851 | 1563 void Assembler::jmp(Label& L, bool maybe_short) { |
304 | 1564 if (L.is_bound()) { |
1565 address entry = target(L); | |
1566 assert(entry != NULL, "jmp most probably wrong"); | |
1567 InstructionMark im(this); | |
1568 const int short_size = 2; | |
1569 const int long_size = 5; | |
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1570 intptr_t offs = entry - pc(); |
3851 | 1571 if (maybe_short && is8bit(offs - short_size)) { |
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1572 emit_int8((unsigned char)0xEB); |
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1573 emit_int8((offs - short_size) & 0xFF); |
304 | 1574 } else { |
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1575 emit_int8((unsigned char)0xE9); |
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1576 emit_int32(offs - long_size); |
304 | 1577 } |
1578 } else { | |
1579 // By default, forward jumps are always 32-bit displacements, since | |
1580 // we can't yet know where the label will be bound. If you're sure that | |
1581 // the forward jump will not run beyond 256 bytes, use jmpb to | |
1582 // force an 8-bit displacement. | |
1583 InstructionMark im(this); | |
1584 L.add_patch_at(code(), locator()); | |
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1585 emit_int8((unsigned char)0xE9); |
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1586 emit_int32(0); |
304 | 1587 } |
1588 } | |
1589 | |
1590 void Assembler::jmp(Register entry) { | |
1591 int encode = prefix_and_encode(entry->encoding()); | |
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1592 emit_int8((unsigned char)0xFF); |
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1593 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 1594 } |
1595 | |
1596 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { | |
1597 InstructionMark im(this); | |
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1598 emit_int8((unsigned char)0xE9); |
304 | 1599 assert(dest != NULL, "must have a target"); |
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1600 intptr_t disp = dest - (pc() + sizeof(int32_t)); |
304 | 1601 assert(is_simm32(disp), "must be 32bit offset (jmp)"); |
1602 emit_data(disp, rspec.reloc(), call32_operand); | |
1603 } | |
1604 | |
1605 void Assembler::jmpb(Label& L) { | |
1606 if (L.is_bound()) { | |
1607 const int short_size = 2; | |
1608 address entry = target(L); | |
1609 assert(entry != NULL, "jmp most probably wrong"); | |
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1610 #ifdef ASSERT |
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1611 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); |
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1612 intptr_t delta = short_branch_delta(); |
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1613 if (delta != 0) { |
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1614 dist += (dist < 0 ? (-delta) :delta); |
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1615 } |
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1616 assert(is8bit(dist), "Dispacement too large for a short jmp"); |
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1617 #endif |
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1618 intptr_t offs = entry - pc(); |
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1619 emit_int8((unsigned char)0xEB); |
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1620 emit_int8((offs - short_size) & 0xFF); |
304 | 1621 } else { |
1622 InstructionMark im(this); | |
1623 L.add_patch_at(code(), locator()); | |
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1624 emit_int8((unsigned char)0xEB); |
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1625 emit_int8(0); |
304 | 1626 } |
1627 } | |
1628 | |
1629 void Assembler::ldmxcsr( Address src) { | |
1630 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1631 InstructionMark im(this); | |
1632 prefix(src); | |
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1633 emit_int8(0x0F); |
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1634 emit_int8((unsigned char)0xAE); |
304 | 1635 emit_operand(as_Register(2), src); |
1636 } | |
1637 | |
1638 void Assembler::leal(Register dst, Address src) { | |
1639 InstructionMark im(this); | |
1640 #ifdef _LP64 | |
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1641 emit_int8(0x67); // addr32 |
304 | 1642 prefix(src, dst); |
1643 #endif // LP64 | |
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1644 emit_int8((unsigned char)0x8D); |
304 | 1645 emit_operand(dst, src); |
1646 } | |
1647 | |
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1648 void Assembler::lfence() { |
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1649 emit_int8(0x0F); |
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1650 emit_int8((unsigned char)0xAE); |
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1651 emit_int8((unsigned char)0xE8); |
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1652 } |
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1653 |
304 | 1654 void Assembler::lock() { |
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1655 emit_int8((unsigned char)0xF0); |
304 | 1656 } |
1657 | |
775
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1658 void Assembler::lzcntl(Register dst, Register src) { |
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1659 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
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1660 emit_int8((unsigned char)0xF3); |
775
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1661 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1662 emit_int8(0x0F); |
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1663 emit_int8((unsigned char)0xBD); |
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1664 emit_int8((unsigned char)(0xC0 | encode)); |
775
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1665 } |
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1666 |
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|
1667 // Emit mfence instruction |
304 | 1668 void Assembler::mfence() { |
671
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1669 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
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1670 emit_int8(0x0F); |
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1671 emit_int8((unsigned char)0xAE); |
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1672 emit_int8((unsigned char)0xF0); |
304 | 1673 } |
1674 | |
1675 void Assembler::mov(Register dst, Register src) { | |
1676 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
1677 } | |
1678 | |
1679 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | |
1680 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1681 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66); |
304 | 1682 } |
1683 | |
1684 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | |
1685 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1686 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE); |
304 | 1687 } |
1688 | |
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1689 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { |
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|
1690 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
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1691 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE); |
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|
1692 emit_int8(0x16); |
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1693 emit_int8((unsigned char)(0xC0 | encode)); |
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1694 } |
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1695 |
304 | 1696 void Assembler::movb(Register dst, Address src) { |
1697 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
1698 InstructionMark im(this); | |
1699 prefix(src, dst, true); | |
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1700 emit_int8((unsigned char)0x8A); |
304 | 1701 emit_operand(dst, src); |
1702 } | |
1703 | |
1704 | |
1705 void Assembler::movb(Address dst, int imm8) { | |
1706 InstructionMark im(this); | |
1707 prefix(dst); | |
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1708 emit_int8((unsigned char)0xC6); |
304 | 1709 emit_operand(rax, dst, 1); |
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1710 emit_int8(imm8); |
304 | 1711 } |
1712 | |
1713 | |
1714 void Assembler::movb(Address dst, Register src) { | |
1715 assert(src->has_byte_register(), "must have byte register"); | |
1716 InstructionMark im(this); | |
1717 prefix(dst, src, true); | |
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1718 emit_int8((unsigned char)0x88); |
304 | 1719 emit_operand(src, dst); |
1720 } | |
1721 | |
1722 void Assembler::movdl(XMMRegister dst, Register src) { | |
1723 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 1724 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
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1725 emit_int8(0x6E); |
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1726 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1727 } |
1728 | |
1729 void Assembler::movdl(Register dst, XMMRegister src) { | |
1730 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1731 // swap src/dst to get correct prefix | |
4759 | 1732 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66); |
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1733 emit_int8(0x7E); |
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1734 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1735 } |
1736 | |
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1737 void Assembler::movdl(XMMRegister dst, Address src) { |
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1738 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
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1739 InstructionMark im(this); |
4759 | 1740 simd_prefix(dst, src, VEX_SIMD_66); |
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1741 emit_int8(0x6E); |
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1742 emit_operand(dst, src); |
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1743 } |
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1744 |
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1745 void Assembler::movdl(Address dst, XMMRegister src) { |
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1746 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
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1747 InstructionMark im(this); |
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1748 simd_prefix(dst, src, VEX_SIMD_66); |
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1749 emit_int8(0x7E); |
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1750 emit_operand(src, dst); |
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1751 } |
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1752 |
304 | 1753 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { |
1754 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1755 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66); |
304 | 1756 } |
1757 | |
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1758 void Assembler::movdqa(XMMRegister dst, Address src) { |
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1759 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
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1760 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66); |
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1761 } |
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1762 |
405 | 1763 void Assembler::movdqu(XMMRegister dst, Address src) { |
1764 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1765 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3); |
405 | 1766 } |
1767 | |
1768 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |
1769 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1770 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3); |
405 | 1771 } |
1772 | |
1773 void Assembler::movdqu(Address dst, XMMRegister src) { | |
1774 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1775 InstructionMark im(this); | |
4759 | 1776 simd_prefix(dst, src, VEX_SIMD_F3); |
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1777 emit_int8(0x7F); |
405 | 1778 emit_operand(src, dst); |
1779 } | |
1780 | |
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1781 // Move Unaligned 256bit Vector |
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1782 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) { |
17913 | 1783 assert(UseAVX > 0, ""); |
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1784 bool vector256 = true; |
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1785 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256); |
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1786 emit_int8(0x6F); |
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1787 emit_int8((unsigned char)(0xC0 | encode)); |
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1788 } |
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1789 |
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1790 void Assembler::vmovdqu(XMMRegister dst, Address src) { |
17913 | 1791 assert(UseAVX > 0, ""); |
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1792 InstructionMark im(this); |
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1793 bool vector256 = true; |
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1794 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256); |
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1795 emit_int8(0x6F); |
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1796 emit_operand(dst, src); |
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1797 } |
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1798 |
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1799 void Assembler::vmovdqu(Address dst, XMMRegister src) { |
17913 | 1800 assert(UseAVX > 0, ""); |
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1801 InstructionMark im(this); |
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1802 bool vector256 = true; |
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1803 // swap src<->dst for encoding |
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1804 assert(src != xnoreg, "sanity"); |
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1805 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256); |
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1806 emit_int8(0x7F); |
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1807 emit_operand(src, dst); |
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1808 } |
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1809 |
304 | 1810 // Uses zero extension on 64bit |
1811 | |
1812 void Assembler::movl(Register dst, int32_t imm32) { | |
1813 int encode = prefix_and_encode(dst->encoding()); | |
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1814 emit_int8((unsigned char)(0xB8 | encode)); |
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1815 emit_int32(imm32); |
304 | 1816 } |
1817 | |
1818 void Assembler::movl(Register dst, Register src) { | |
1819 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1820 emit_int8((unsigned char)0x8B); |
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1821 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1822 } |
1823 | |
1824 void Assembler::movl(Register dst, Address src) { | |
1825 InstructionMark im(this); | |
1826 prefix(src, dst); | |
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1827 emit_int8((unsigned char)0x8B); |
304 | 1828 emit_operand(dst, src); |
1829 } | |
1830 | |
1831 void Assembler::movl(Address dst, int32_t imm32) { | |
1832 InstructionMark im(this); | |
1833 prefix(dst); | |
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1834 emit_int8((unsigned char)0xC7); |
304 | 1835 emit_operand(rax, dst, 4); |
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1836 emit_int32(imm32); |
304 | 1837 } |
1838 | |
1839 void Assembler::movl(Address dst, Register src) { | |
1840 InstructionMark im(this); | |
1841 prefix(dst, src); | |
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1842 emit_int8((unsigned char)0x89); |
304 | 1843 emit_operand(src, dst); |
1844 } | |
1845 | |
1846 // New cpus require to use movsd and movss to avoid partial register stall | |
1847 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
1848 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
1849 void Assembler::movlpd(XMMRegister dst, Address src) { | |
1850 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1851 emit_simd_arith(0x12, dst, src, VEX_SIMD_66); |
304 | 1852 } |
1853 | |
1854 void Assembler::movq( MMXRegister dst, Address src ) { | |
1855 assert( VM_Version::supports_mmx(), "" ); | |
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1856 emit_int8(0x0F); |
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1857 emit_int8(0x6F); |
304 | 1858 emit_operand(dst, src); |
1859 } | |
1860 | |
1861 void Assembler::movq( Address dst, MMXRegister src ) { | |
1862 assert( VM_Version::supports_mmx(), "" ); | |
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1863 emit_int8(0x0F); |
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1864 emit_int8(0x7F); |
304 | 1865 // workaround gcc (3.2.1-7a) bug |
1866 // In that version of gcc with only an emit_operand(MMX, Address) | |
1867 // gcc will tail jump and try and reverse the parameters completely | |
1868 // obliterating dst in the process. By having a version available | |
1869 // that doesn't need to swap the args at the tail jump the bug is | |
1870 // avoided. | |
1871 emit_operand(dst, src); | |
1872 } | |
1873 | |
1874 void Assembler::movq(XMMRegister dst, Address src) { | |
1875 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1876 InstructionMark im(this); | |
4759 | 1877 simd_prefix(dst, src, VEX_SIMD_F3); |
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1878 emit_int8(0x7E); |
304 | 1879 emit_operand(dst, src); |
1880 } | |
1881 | |
1882 void Assembler::movq(Address dst, XMMRegister src) { | |
1883 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1884 InstructionMark im(this); | |
4759 | 1885 simd_prefix(dst, src, VEX_SIMD_66); |
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1886 emit_int8((unsigned char)0xD6); |
304 | 1887 emit_operand(src, dst); |
1888 } | |
1889 | |
1890 void Assembler::movsbl(Register dst, Address src) { // movsxb | |
1891 InstructionMark im(this); | |
1892 prefix(src, dst); | |
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1893 emit_int8(0x0F); |
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1894 emit_int8((unsigned char)0xBE); |
304 | 1895 emit_operand(dst, src); |
1896 } | |
1897 | |
1898 void Assembler::movsbl(Register dst, Register src) { // movsxb | |
1899 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
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1900 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true); |
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1901 emit_int8(0x0F); |
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1902 emit_int8((unsigned char)0xBE); |
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1903 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1904 } |
1905 | |
1906 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | |
1907 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1908 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2); |
304 | 1909 } |
1910 | |
1911 void Assembler::movsd(XMMRegister dst, Address src) { | |
1912 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1913 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2); |
304 | 1914 } |
1915 | |
1916 void Assembler::movsd(Address dst, XMMRegister src) { | |
1917 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1918 InstructionMark im(this); | |
4759 | 1919 simd_prefix(dst, src, VEX_SIMD_F2); |
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1920 emit_int8(0x11); |
304 | 1921 emit_operand(src, dst); |
1922 } | |
1923 | |
1924 void Assembler::movss(XMMRegister dst, XMMRegister src) { | |
1925 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1926 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3); |
304 | 1927 } |
1928 | |
1929 void Assembler::movss(XMMRegister dst, Address src) { | |
1930 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1931 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3); |
304 | 1932 } |
1933 | |
1934 void Assembler::movss(Address dst, XMMRegister src) { | |
1935 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1936 InstructionMark im(this); | |
4759 | 1937 simd_prefix(dst, src, VEX_SIMD_F3); |
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1938 emit_int8(0x11); |
304 | 1939 emit_operand(src, dst); |
1940 } | |
1941 | |
1942 void Assembler::movswl(Register dst, Address src) { // movsxw | |
1943 InstructionMark im(this); | |
1944 prefix(src, dst); | |
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1945 emit_int8(0x0F); |
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1946 emit_int8((unsigned char)0xBF); |
304 | 1947 emit_operand(dst, src); |
1948 } | |
1949 | |
1950 void Assembler::movswl(Register dst, Register src) { // movsxw | |
1951 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1952 emit_int8(0x0F); |
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1953 emit_int8((unsigned char)0xBF); |
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1954 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1955 } |
1956 | |
1957 void Assembler::movw(Address dst, int imm16) { | |
1958 InstructionMark im(this); | |
1959 | |
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1960 emit_int8(0x66); // switch to 16-bit mode |
304 | 1961 prefix(dst); |
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1962 emit_int8((unsigned char)0xC7); |
304 | 1963 emit_operand(rax, dst, 2); |
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1964 emit_int16(imm16); |
304 | 1965 } |
1966 | |
1967 void Assembler::movw(Register dst, Address src) { | |
1968 InstructionMark im(this); | |
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1969 emit_int8(0x66); |
304 | 1970 prefix(src, dst); |
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1971 emit_int8((unsigned char)0x8B); |
304 | 1972 emit_operand(dst, src); |
1973 } | |
1974 | |
1975 void Assembler::movw(Address dst, Register src) { | |
1976 InstructionMark im(this); | |
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1977 emit_int8(0x66); |
304 | 1978 prefix(dst, src); |
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1979 emit_int8((unsigned char)0x89); |
304 | 1980 emit_operand(src, dst); |
1981 } | |
1982 | |
1983 void Assembler::movzbl(Register dst, Address src) { // movzxb | |
1984 InstructionMark im(this); | |
1985 prefix(src, dst); | |
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1986 emit_int8(0x0F); |
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1987 emit_int8((unsigned char)0xB6); |
304 | 1988 emit_operand(dst, src); |
1989 } | |
1990 | |
1991 void Assembler::movzbl(Register dst, Register src) { // movzxb | |
1992 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
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1993 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true); |
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1994 emit_int8(0x0F); |
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1995 emit_int8((unsigned char)0xB6); |
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1996 emit_int8(0xC0 | encode); |
304 | 1997 } |
1998 | |
1999 void Assembler::movzwl(Register dst, Address src) { // movzxw | |
2000 InstructionMark im(this); | |
2001 prefix(src, dst); | |
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2002 emit_int8(0x0F); |
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2003 emit_int8((unsigned char)0xB7); |
304 | 2004 emit_operand(dst, src); |
2005 } | |
2006 | |
2007 void Assembler::movzwl(Register dst, Register src) { // movzxw | |
2008 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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2009 emit_int8(0x0F); |
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2010 emit_int8((unsigned char)0xB7); |
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2011 emit_int8(0xC0 | encode); |
304 | 2012 } |
2013 | |
2014 void Assembler::mull(Address src) { | |
2015 InstructionMark im(this); | |
2016 prefix(src); | |
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2017 emit_int8((unsigned char)0xF7); |
304 | 2018 emit_operand(rsp, src); |
2019 } | |
2020 | |
2021 void Assembler::mull(Register src) { | |
2022 int encode = prefix_and_encode(src->encoding()); | |
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2023 emit_int8((unsigned char)0xF7); |
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2024 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 2025 } |
2026 | |
2027 void Assembler::mulsd(XMMRegister dst, Address src) { | |
2028 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2029 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); |
304 | 2030 } |
2031 | |
2032 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | |
2033 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2034 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); |
304 | 2035 } |
2036 | |
2037 void Assembler::mulss(XMMRegister dst, Address src) { | |
2038 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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2039 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); |
304 | 2040 } |
2041 | |
2042 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | |
2043 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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2044 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); |
304 | 2045 } |
2046 | |
2047 void Assembler::negl(Register dst) { | |
2048 int encode = prefix_and_encode(dst->encoding()); | |
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2049 emit_int8((unsigned char)0xF7); |
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2050 emit_int8((unsigned char)(0xD8 | encode)); |
304 | 2051 } |
2052 | |
0 | 2053 void Assembler::nop(int i) { |
304 | 2054 #ifdef ASSERT |
0 | 2055 assert(i > 0, " "); |
304 | 2056 // The fancy nops aren't currently recognized by debuggers making it a |
2057 // pain to disassemble code while debugging. If asserts are on clearly | |
2058 // speed is not an issue so simply use the single byte traditional nop | |
2059 // to do alignment. | |
2060 | |
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2061 for (; i > 0 ; i--) emit_int8((unsigned char)0x90); |
304 | 2062 return; |
2063 | |
2064 #endif // ASSERT | |
2065 | |
0 | 2066 if (UseAddressNop && VM_Version::is_intel()) { |
2067 // | |
2068 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel | |
2069 // 1: 0x90 | |
2070 // 2: 0x66 0x90 | |
2071 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
2072 // 4: 0x0F 0x1F 0x40 0x00 | |
2073 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
2074 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2075 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2076 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2077 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2078 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2079 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2080 | |
2081 // The rest coding is Intel specific - don't use consecutive address nops | |
2082 | |
2083 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
2084 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
2085 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
2086 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
2087 | |
2088 while(i >= 15) { | |
2089 // For Intel don't generate consecutive addess nops (mix with regular nops) | |
2090 i -= 15; | |
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2091 emit_int8(0x66); // size prefix |
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2092 emit_int8(0x66); // size prefix |
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2093 emit_int8(0x66); // size prefix |
0 | 2094 addr_nop_8(); |
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2095 emit_int8(0x66); // size prefix |
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2096 emit_int8(0x66); // size prefix |
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2097 emit_int8(0x66); // size prefix |
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2098 emit_int8((unsigned char)0x90); |
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2099 // nop |
0 | 2100 } |
2101 switch (i) { | |
2102 case 14: | |
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2103 emit_int8(0x66); // size prefix |
0 | 2104 case 13: |
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2105 emit_int8(0x66); // size prefix |
0 | 2106 case 12: |
2107 addr_nop_8(); | |
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2108 emit_int8(0x66); // size prefix |
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2109 emit_int8(0x66); // size prefix |
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2110 emit_int8(0x66); // size prefix |
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2111 emit_int8((unsigned char)0x90); |
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2112 // nop |
0 | 2113 break; |
2114 case 11: | |
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2115 emit_int8(0x66); // size prefix |
0 | 2116 case 10: |
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2117 emit_int8(0x66); // size prefix |
0 | 2118 case 9: |
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2119 emit_int8(0x66); // size prefix |
0 | 2120 case 8: |
2121 addr_nop_8(); | |
2122 break; | |
2123 case 7: | |
2124 addr_nop_7(); | |
2125 break; | |
2126 case 6: | |
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2127 emit_int8(0x66); // size prefix |
0 | 2128 case 5: |
2129 addr_nop_5(); | |
2130 break; | |
2131 case 4: | |
2132 addr_nop_4(); | |
2133 break; | |
2134 case 3: | |
2135 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
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2136 emit_int8(0x66); // size prefix |
0 | 2137 case 2: |
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2138 emit_int8(0x66); // size prefix |
0 | 2139 case 1: |
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2140 emit_int8((unsigned char)0x90); |
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2141 // nop |
0 | 2142 break; |
2143 default: | |
2144 assert(i == 0, " "); | |
2145 } | |
2146 return; | |
2147 } | |
2148 if (UseAddressNop && VM_Version::is_amd()) { | |
2149 // | |
2150 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. | |
2151 // 1: 0x90 | |
2152 // 2: 0x66 0x90 | |
2153 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
2154 // 4: 0x0F 0x1F 0x40 0x00 | |
2155 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
2156 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2157 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2158 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2159 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2160 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2161 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2162 | |
2163 // The rest coding is AMD specific - use consecutive address nops | |
2164 | |
2165 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2166 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2167 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2168 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2169 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2170 // Size prefixes (0x66) are added for larger sizes | |
2171 | |
2172 while(i >= 22) { | |
2173 i -= 11; | |
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2174 emit_int8(0x66); // size prefix |
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2175 emit_int8(0x66); // size prefix |
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2176 emit_int8(0x66); // size prefix |
0 | 2177 addr_nop_8(); |
2178 } | |
2179 // Generate first nop for size between 21-12 | |
2180 switch (i) { | |
2181 case 21: | |
2182 i -= 1; | |
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2183 emit_int8(0x66); // size prefix |
0 | 2184 case 20: |
2185 case 19: | |
2186 i -= 1; | |
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2187 emit_int8(0x66); // size prefix |
0 | 2188 case 18: |
2189 case 17: | |
2190 i -= 1; | |
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2191 emit_int8(0x66); // size prefix |
0 | 2192 case 16: |
2193 case 15: | |
2194 i -= 8; | |
2195 addr_nop_8(); | |
2196 break; | |
2197 case 14: | |
2198 case 13: | |
2199 i -= 7; | |
2200 addr_nop_7(); | |
2201 break; | |
2202 case 12: | |
2203 i -= 6; | |
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|
2204 emit_int8(0x66); // size prefix |
0 | 2205 addr_nop_5(); |
2206 break; | |
2207 default: | |
2208 assert(i < 12, " "); | |
2209 } | |
2210 | |
2211 // Generate second nop for size between 11-1 | |
2212 switch (i) { | |
2213 case 11: | |
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|
2214 emit_int8(0x66); // size prefix |
0 | 2215 case 10: |
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|
2216 emit_int8(0x66); // size prefix |
0 | 2217 case 9: |
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2218 emit_int8(0x66); // size prefix |
0 | 2219 case 8: |
2220 addr_nop_8(); | |
2221 break; | |
2222 case 7: | |
2223 addr_nop_7(); | |
2224 break; | |
2225 case 6: | |
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2226 emit_int8(0x66); // size prefix |
0 | 2227 case 5: |
2228 addr_nop_5(); | |
2229 break; | |
2230 case 4: | |
2231 addr_nop_4(); | |
2232 break; | |
2233 case 3: | |
2234 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
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2235 emit_int8(0x66); // size prefix |
0 | 2236 case 2: |
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|
2237 emit_int8(0x66); // size prefix |
0 | 2238 case 1: |
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2239 emit_int8((unsigned char)0x90); |
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|
2240 // nop |
0 | 2241 break; |
2242 default: | |
2243 assert(i == 0, " "); | |
2244 } | |
2245 return; | |
2246 } | |
2247 | |
2248 // Using nops with size prefixes "0x66 0x90". | |
2249 // From AMD Optimization Guide: | |
2250 // 1: 0x90 | |
2251 // 2: 0x66 0x90 | |
2252 // 3: 0x66 0x66 0x90 | |
2253 // 4: 0x66 0x66 0x66 0x90 | |
2254 // 5: 0x66 0x66 0x90 0x66 0x90 | |
2255 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 | |
2256 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 | |
2257 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 | |
2258 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
2259 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
2260 // | |
2261 while(i > 12) { | |
2262 i -= 4; | |
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|
2263 emit_int8(0x66); // size prefix |
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|
2264 emit_int8(0x66); |
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|
2265 emit_int8(0x66); |
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changeset
|
2266 emit_int8((unsigned char)0x90); |
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|
2267 // nop |
0 | 2268 } |
2269 // 1 - 12 nops | |
2270 if(i > 8) { | |
2271 if(i > 9) { | |
2272 i -= 1; | |
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|
2273 emit_int8(0x66); |
0 | 2274 } |
2275 i -= 3; | |
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|
2276 emit_int8(0x66); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
2277 emit_int8(0x66); |
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changeset
|
2278 emit_int8((unsigned char)0x90); |
0 | 2279 } |
2280 // 1 - 8 nops | |
2281 if(i > 4) { | |
2282 if(i > 6) { | |
2283 i -= 1; | |
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|
2284 emit_int8(0x66); |
0 | 2285 } |
2286 i -= 3; | |
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changeset
|
2287 emit_int8(0x66); |
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changeset
|
2288 emit_int8(0x66); |
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changeset
|
2289 emit_int8((unsigned char)0x90); |
0 | 2290 } |
2291 switch (i) { | |
2292 case 4: | |
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changeset
|
2293 emit_int8(0x66); |
0 | 2294 case 3: |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
2295 emit_int8(0x66); |
0 | 2296 case 2: |
7430
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changeset
|
2297 emit_int8(0x66); |
0 | 2298 case 1: |
7430
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changeset
|
2299 emit_int8((unsigned char)0x90); |
0 | 2300 break; |
2301 default: | |
2302 assert(i == 0, " "); | |
2303 } | |
2304 } | |
2305 | |
304 | 2306 void Assembler::notl(Register dst) { |
2307 int encode = prefix_and_encode(dst->encoding()); | |
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changeset
|
2308 emit_int8((unsigned char)0xF7); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
2309 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 2310 } |
2311 | |
2312 void Assembler::orl(Address dst, int32_t imm32) { | |
2313 InstructionMark im(this); | |
2314 prefix(dst); | |
2100
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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diff
changeset
|
2315 emit_arith_operand(0x81, rcx, dst, imm32); |
304 | 2316 } |
2317 | |
2318 void Assembler::orl(Register dst, int32_t imm32) { | |
2319 prefix(dst); | |
2320 emit_arith(0x81, 0xC8, dst, imm32); | |
2321 } | |
2322 | |
2323 void Assembler::orl(Register dst, Address src) { | |
2324 InstructionMark im(this); | |
2325 prefix(src, dst); | |
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|
2326 emit_int8(0x0B); |
304 | 2327 emit_operand(dst, src); |
2328 } | |
2329 | |
2330 void Assembler::orl(Register dst, Register src) { | |
2331 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2332 emit_arith(0x0B, 0xC0, dst, src); | |
2333 } | |
2334 | |
4759 | 2335 void Assembler::packuswb(XMMRegister dst, Address src) { |
2336 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2337 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
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|
2338 emit_simd_arith(0x67, dst, src, VEX_SIMD_66); |
4759 | 2339 } |
2340 | |
2341 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { | |
2342 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2343 emit_simd_arith(0x67, dst, src, VEX_SIMD_66); |
4759 | 2344 } |
2345 | |
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|
2346 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
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changeset
|
2347 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
b30b3c2a0cf2
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changeset
|
2348 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector256); |
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|
2349 } |
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2350 |
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changeset
|
2351 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256) { |
8042
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changeset
|
2352 assert(VM_Version::supports_avx2(), ""); |
91a23b11d8dc
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changeset
|
2353 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector256); |
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changeset
|
2354 emit_int8(0x00); |
91a23b11d8dc
8007708: compiler/6855215 assert(VM_Version::supports_sse4_2())
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diff
changeset
|
2355 emit_int8(0xC0 | encode); |
91a23b11d8dc
8007708: compiler/6855215 assert(VM_Version::supports_sse4_2())
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changeset
|
2356 emit_int8(imm8); |
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|
2357 } |
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changeset
|
2358 |
17780 | 2359 void Assembler::pause() { |
2360 emit_int8((unsigned char)0xF3); | |
2361 emit_int8((unsigned char)0x90); | |
2362 } | |
2363 | |
681 | 2364 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
2365 assert(VM_Version::supports_sse4_2(), ""); | |
4759 | 2366 InstructionMark im(this); |
2367 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); | |
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changeset
|
2368 emit_int8(0x61); |
681 | 2369 emit_operand(dst, src); |
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changeset
|
2370 emit_int8(imm8); |
681 | 2371 } |
2372 | |
2373 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | |
2374 assert(VM_Version::supports_sse4_2(), ""); | |
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|
2375 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); |
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|
2376 emit_int8(0x61); |
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changeset
|
2377 emit_int8((unsigned char)(0xC0 | encode)); |
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|
2378 emit_int8(imm8); |
681 | 2379 } |
2380 | |
11080
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2381 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) { |
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2382 assert(VM_Version::supports_sse4_1(), ""); |
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|
2383 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, false); |
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2384 emit_int8(0x16); |
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|
2385 emit_int8((unsigned char)(0xC0 | encode)); |
b800986664f4
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|
2386 emit_int8(imm8); |
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|
2387 } |
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|
2388 |
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2389 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) { |
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changeset
|
2390 assert(VM_Version::supports_sse4_1(), ""); |
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|
2391 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true); |
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|
2392 emit_int8(0x16); |
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changeset
|
2393 emit_int8((unsigned char)(0xC0 | encode)); |
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changeset
|
2394 emit_int8(imm8); |
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2395 } |
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|
2396 |
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2397 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) { |
b800986664f4
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|
2398 assert(VM_Version::supports_sse4_1(), ""); |
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|
2399 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, false); |
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|
2400 emit_int8(0x22); |
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7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
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2401 emit_int8((unsigned char)(0xC0 | encode)); |
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|
2402 emit_int8(imm8); |
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|
2403 } |
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2404 |
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2405 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) { |
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2406 assert(VM_Version::supports_sse4_1(), ""); |
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2407 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, true); |
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|
2408 emit_int8(0x22); |
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|
2409 emit_int8((unsigned char)(0xC0 | encode)); |
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|
2410 emit_int8(imm8); |
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|
2411 } |
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2412 |
4759 | 2413 void Assembler::pmovzxbw(XMMRegister dst, Address src) { |
2414 assert(VM_Version::supports_sse4_1(), ""); | |
2415 InstructionMark im(this); | |
2416 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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2417 emit_int8(0x30); |
4759 | 2418 emit_operand(dst, src); |
2419 } | |
2420 | |
2421 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { | |
2422 assert(VM_Version::supports_sse4_1(), ""); | |
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2423 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
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2424 emit_int8(0x30); |
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2425 emit_int8((unsigned char)(0xC0 | encode)); |
4759 | 2426 } |
2427 | |
304 | 2428 // generic |
2429 void Assembler::pop(Register dst) { | |
2430 int encode = prefix_and_encode(dst->encoding()); | |
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2431 emit_int8(0x58 | encode); |
304 | 2432 } |
2433 | |
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2434 void Assembler::popcntl(Register dst, Address src) { |
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2435 assert(VM_Version::supports_popcnt(), "must support"); |
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|
2436 InstructionMark im(this); |
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|
2437 emit_int8((unsigned char)0xF3); |
643
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|
2438 prefix(src, dst); |
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|
2439 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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|
2440 emit_int8((unsigned char)0xB8); |
643
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|
2441 emit_operand(dst, src); |
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|
2442 } |
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|
2443 |
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2444 void Assembler::popcntl(Register dst, Register src) { |
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|
2445 assert(VM_Version::supports_popcnt(), "must support"); |
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|
2446 emit_int8((unsigned char)0xF3); |
643
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|
2447 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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|
2448 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
2449 emit_int8((unsigned char)0xB8); |
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changeset
|
2450 emit_int8((unsigned char)(0xC0 | encode)); |
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|
2451 } |
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|
2452 |
304 | 2453 void Assembler::popf() { |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
2454 emit_int8((unsigned char)0x9D); |
304 | 2455 } |
2456 | |
1060 | 2457 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 2458 void Assembler::popl(Address dst) { |
2459 // NOTE: this will adjust stack by 8byte on 64bits | |
2460 InstructionMark im(this); | |
2461 prefix(dst); | |
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changeset
|
2462 emit_int8((unsigned char)0x8F); |
304 | 2463 emit_operand(rax, dst); |
2464 } | |
1060 | 2465 #endif |
304 | 2466 |
2467 void Assembler::prefetch_prefix(Address src) { | |
2468 prefix(src); | |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
2469 emit_int8(0x0F); |
304 | 2470 } |
2471 | |
2472 void Assembler::prefetchnta(Address src) { | |
3873
a594deb1d6dc
7081926: assert(VM_Version::supports_sse2()) failed: must support
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3855
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changeset
|
2473 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); |
304 | 2474 InstructionMark im(this); |
2475 prefetch_prefix(src); | |
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diff
changeset
|
2476 emit_int8(0x18); |
304 | 2477 emit_operand(rax, src); // 0, src |
2478 } | |
2479 | |
2480 void Assembler::prefetchr(Address src) { | |
3854 | 2481 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
304 | 2482 InstructionMark im(this); |
2483 prefetch_prefix(src); | |
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changeset
|
2484 emit_int8(0x0D); |
304 | 2485 emit_operand(rax, src); // 0, src |
2486 } | |
2487 | |
2488 void Assembler::prefetcht0(Address src) { | |
2489 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2490 InstructionMark im(this); | |
2491 prefetch_prefix(src); | |
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changeset
|
2492 emit_int8(0x18); |
304 | 2493 emit_operand(rcx, src); // 1, src |
2494 } | |
2495 | |
2496 void Assembler::prefetcht1(Address src) { | |
2497 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2498 InstructionMark im(this); | |
2499 prefetch_prefix(src); | |
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diff
changeset
|
2500 emit_int8(0x18); |
304 | 2501 emit_operand(rdx, src); // 2, src |
2502 } | |
2503 | |
2504 void Assembler::prefetcht2(Address src) { | |
2505 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2506 InstructionMark im(this); | |
2507 prefetch_prefix(src); | |
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diff
changeset
|
2508 emit_int8(0x18); |
304 | 2509 emit_operand(rbx, src); // 3, src |
2510 } | |
2511 | |
2512 void Assembler::prefetchw(Address src) { | |
3854 | 2513 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
304 | 2514 InstructionMark im(this); |
2515 prefetch_prefix(src); | |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
2516 emit_int8(0x0D); |
304 | 2517 emit_operand(rcx, src); // 1, src |
2518 } | |
2519 | |
2520 void Assembler::prefix(Prefix p) { | |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
2521 emit_int8(p); |
304 | 2522 } |
2523 | |
6894 | 2524 void Assembler::pshufb(XMMRegister dst, XMMRegister src) { |
2525 assert(VM_Version::supports_ssse3(), ""); | |
2526 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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|
2527 emit_int8(0x00); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
2528 emit_int8((unsigned char)(0xC0 | encode)); |
6894 | 2529 } |
2530 | |
2531 void Assembler::pshufb(XMMRegister dst, Address src) { | |
2532 assert(VM_Version::supports_ssse3(), ""); | |
2533 InstructionMark im(this); | |
2534 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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changeset
|
2535 emit_int8(0x00); |
6894 | 2536 emit_operand(dst, src); |
2537 } | |
2538 | |
304 | 2539 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { |
2540 assert(isByte(mode), "invalid value"); | |
2541 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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|
2542 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66); |
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diff
changeset
|
2543 emit_int8(mode & 0xFF); |
304 | 2544 |
2545 } | |
2546 | |
2547 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | |
2548 assert(isByte(mode), "invalid value"); | |
2549 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 2550 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2551 InstructionMark im(this); | |
2552 simd_prefix(dst, src, VEX_SIMD_66); | |
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|
2553 emit_int8(0x70); |
304 | 2554 emit_operand(dst, src); |
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changeset
|
2555 emit_int8(mode & 0xFF); |
304 | 2556 } |
2557 | |
2558 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | |
2559 assert(isByte(mode), "invalid value"); | |
2560 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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|
2561 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2); |
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changeset
|
2562 emit_int8(mode & 0xFF); |
304 | 2563 } |
2564 | |
2565 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | |
2566 assert(isByte(mode), "invalid value"); | |
2567 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 2568 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2569 InstructionMark im(this); | |
2570 simd_prefix(dst, src, VEX_SIMD_F2); | |
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|
2571 emit_int8(0x70); |
304 | 2572 emit_operand(dst, src); |
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|
2573 emit_int8(mode & 0xFF); |
304 | 2574 } |
2575 | |
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
2576 void Assembler::psrldq(XMMRegister dst, int shift) { |
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
2577 // Shift 128 bit value in xmm register by number of bytes. |
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
2578 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4759 | 2579 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66); |
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|
2580 emit_int8(0x73); |
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|
2581 emit_int8((unsigned char)(0xC0 | encode)); |
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|
2582 emit_int8(shift); |
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|
2583 } |
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|
2584 |
681 | 2585 void Assembler::ptest(XMMRegister dst, Address src) { |
2586 assert(VM_Version::supports_sse4_1(), ""); | |
4759 | 2587 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2588 InstructionMark im(this); | |
2589 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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|
2590 emit_int8(0x17); |
681 | 2591 emit_operand(dst, src); |
2592 } | |
2593 | |
2594 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | |
2595 assert(VM_Version::supports_sse4_1(), ""); | |
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|
2596 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
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|
2597 emit_int8(0x17); |
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|
2598 emit_int8((unsigned char)(0xC0 | encode)); |
681 | 2599 } |
2600 | |
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|
2601 void Assembler::vptest(XMMRegister dst, Address src) { |
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|
2602 assert(VM_Version::supports_avx(), ""); |
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|
2603 InstructionMark im(this); |
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|
2604 bool vector256 = true; |
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|
2605 assert(dst != xnoreg, "sanity"); |
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|
2606 int dst_enc = dst->encoding(); |
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|
2607 // swap src<->dst for encoding |
7637
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|
2608 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256); |
7477
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|
2609 emit_int8(0x17); |
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changeset
|
2610 emit_operand(dst, src); |
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|
2611 } |
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|
2612 |
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|
2613 void Assembler::vptest(XMMRegister dst, XMMRegister src) { |
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|
2614 assert(VM_Version::supports_avx(), ""); |
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|
2615 bool vector256 = true; |
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2616 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
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2617 emit_int8(0x17); |
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2618 emit_int8((unsigned char)(0xC0 | encode)); |
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2619 } |
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2620 |
4759 | 2621 void Assembler::punpcklbw(XMMRegister dst, Address src) { |
2622 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2623 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
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2624 emit_simd_arith(0x60, dst, src, VEX_SIMD_66); |
4759 | 2625 } |
2626 | |
304 | 2627 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
2628 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2629 emit_simd_arith(0x60, dst, src, VEX_SIMD_66); |
304 | 2630 } |
2631 | |
4759 | 2632 void Assembler::punpckldq(XMMRegister dst, Address src) { |
2633 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2634 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
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2635 emit_simd_arith(0x62, dst, src, VEX_SIMD_66); |
4759 | 2636 } |
2637 | |
2638 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { | |
2639 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2640 emit_simd_arith(0x62, dst, src, VEX_SIMD_66); |
4759 | 2641 } |
2642 | |
6225 | 2643 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) { |
2644 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2645 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66); |
6225 | 2646 } |
2647 | |
304 | 2648 void Assembler::push(int32_t imm32) { |
2649 // in 64bits we push 64bits onto the stack but only | |
2650 // take a 32bit immediate | |
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2651 emit_int8(0x68); |
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2652 emit_int32(imm32); |
304 | 2653 } |
2654 | |
2655 void Assembler::push(Register src) { | |
2656 int encode = prefix_and_encode(src->encoding()); | |
2657 | |
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2658 emit_int8(0x50 | encode); |
304 | 2659 } |
2660 | |
2661 void Assembler::pushf() { | |
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2662 emit_int8((unsigned char)0x9C); |
304 | 2663 } |
2664 | |
1060 | 2665 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 2666 void Assembler::pushl(Address src) { |
2667 // Note this will push 64bit on 64bit | |
2668 InstructionMark im(this); | |
2669 prefix(src); | |
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2670 emit_int8((unsigned char)0xFF); |
304 | 2671 emit_operand(rsi, src); |
2672 } | |
1060 | 2673 #endif |
304 | 2674 |
2675 void Assembler::rcll(Register dst, int imm8) { | |
2676 assert(isShiftCount(imm8), "illegal shift count"); | |
2677 int encode = prefix_and_encode(dst->encoding()); | |
2678 if (imm8 == 1) { | |
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2679 emit_int8((unsigned char)0xD1); |
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2680 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 2681 } else { |
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2682 emit_int8((unsigned char)0xC1); |
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2683 emit_int8((unsigned char)0xD0 | encode); |
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2684 emit_int8(imm8); |
304 | 2685 } |
2686 } | |
2687 | |
17780 | 2688 void Assembler::rdtsc() { |
2689 emit_int8((unsigned char)0x0F); | |
2690 emit_int8((unsigned char)0x31); | |
2691 } | |
2692 | |
304 | 2693 // copies data from [esi] to [edi] using rcx pointer sized words |
2694 // generic | |
2695 void Assembler::rep_mov() { | |
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2696 emit_int8((unsigned char)0xF3); |
304 | 2697 // MOVSQ |
2698 LP64_ONLY(prefix(REX_W)); | |
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2699 emit_int8((unsigned char)0xA5); |
304 | 2700 } |
2701 | |
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2702 // sets rcx bytes with rax, value at [edi] |
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2703 void Assembler::rep_stosb() { |
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2704 emit_int8((unsigned char)0xF3); // REP |
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2705 LP64_ONLY(prefix(REX_W)); |
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2706 emit_int8((unsigned char)0xAA); // STOSB |
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2707 } |
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2708 |
304 | 2709 // sets rcx pointer sized words with rax, value at [edi] |
2710 // generic | |
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2711 void Assembler::rep_stos() { |
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2712 emit_int8((unsigned char)0xF3); // REP |
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2713 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD |
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2714 emit_int8((unsigned char)0xAB); |
304 | 2715 } |
2716 | |
2717 // scans rcx pointer sized words at [edi] for occurance of rax, | |
2718 // generic | |
2719 void Assembler::repne_scan() { // repne_scan | |
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2720 emit_int8((unsigned char)0xF2); |
304 | 2721 // SCASQ |
2722 LP64_ONLY(prefix(REX_W)); | |
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2723 emit_int8((unsigned char)0xAF); |
304 | 2724 } |
2725 | |
2726 #ifdef _LP64 | |
2727 // scans rcx 4 byte words at [edi] for occurance of rax, | |
2728 // generic | |
2729 void Assembler::repne_scanl() { // repne_scan | |
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2730 emit_int8((unsigned char)0xF2); |
304 | 2731 // SCASL |
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2732 emit_int8((unsigned char)0xAF); |
304 | 2733 } |
2734 #endif | |
2735 | |
0 | 2736 void Assembler::ret(int imm16) { |
2737 if (imm16 == 0) { | |
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2738 emit_int8((unsigned char)0xC3); |
0 | 2739 } else { |
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2740 emit_int8((unsigned char)0xC2); |
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2741 emit_int16(imm16); |
0 | 2742 } |
2743 } | |
2744 | |
304 | 2745 void Assembler::sahf() { |
2746 #ifdef _LP64 | |
2747 // Not supported in 64bit mode | |
2748 ShouldNotReachHere(); | |
2749 #endif | |
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2750 emit_int8((unsigned char)0x9E); |
304 | 2751 } |
2752 | |
2753 void Assembler::sarl(Register dst, int imm8) { | |
2754 int encode = prefix_and_encode(dst->encoding()); | |
2755 assert(isShiftCount(imm8), "illegal shift count"); | |
2756 if (imm8 == 1) { | |
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2757 emit_int8((unsigned char)0xD1); |
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2758 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 2759 } else { |
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2760 emit_int8((unsigned char)0xC1); |
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|
2761 emit_int8((unsigned char)(0xF8 | encode)); |
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|
2762 emit_int8(imm8); |
304 | 2763 } |
2764 } | |
2765 | |
2766 void Assembler::sarl(Register dst) { | |
2767 int encode = prefix_and_encode(dst->encoding()); | |
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2768 emit_int8((unsigned char)0xD3); |
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|
2769 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 2770 } |
2771 | |
2772 void Assembler::sbbl(Address dst, int32_t imm32) { | |
2773 InstructionMark im(this); | |
2774 prefix(dst); | |
2775 emit_arith_operand(0x81, rbx, dst, imm32); | |
2776 } | |
2777 | |
2778 void Assembler::sbbl(Register dst, int32_t imm32) { | |
2779 prefix(dst); | |
2780 emit_arith(0x81, 0xD8, dst, imm32); | |
2781 } | |
2782 | |
2783 | |
2784 void Assembler::sbbl(Register dst, Address src) { | |
2785 InstructionMark im(this); | |
2786 prefix(src, dst); | |
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|
2787 emit_int8(0x1B); |
304 | 2788 emit_operand(dst, src); |
2789 } | |
2790 | |
2791 void Assembler::sbbl(Register dst, Register src) { | |
2792 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2793 emit_arith(0x1B, 0xC0, dst, src); | |
2794 } | |
2795 | |
2796 void Assembler::setb(Condition cc, Register dst) { | |
2797 assert(0 <= cc && cc < 16, "illegal cc"); | |
2798 int encode = prefix_and_encode(dst->encoding(), true); | |
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|
2799 emit_int8(0x0F); |
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|
2800 emit_int8((unsigned char)0x90 | cc); |
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|
2801 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 2802 } |
2803 | |
2804 void Assembler::shll(Register dst, int imm8) { | |
2805 assert(isShiftCount(imm8), "illegal shift count"); | |
2806 int encode = prefix_and_encode(dst->encoding()); | |
2807 if (imm8 == 1 ) { | |
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|
2808 emit_int8((unsigned char)0xD1); |
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|
2809 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 2810 } else { |
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|
2811 emit_int8((unsigned char)0xC1); |
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|
2812 emit_int8((unsigned char)(0xE0 | encode)); |
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|
2813 emit_int8(imm8); |
304 | 2814 } |
2815 } | |
2816 | |
2817 void Assembler::shll(Register dst) { | |
2818 int encode = prefix_and_encode(dst->encoding()); | |
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2819 emit_int8((unsigned char)0xD3); |
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|
2820 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 2821 } |
2822 | |
2823 void Assembler::shrl(Register dst, int imm8) { | |
2824 assert(isShiftCount(imm8), "illegal shift count"); | |
2825 int encode = prefix_and_encode(dst->encoding()); | |
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|
2826 emit_int8((unsigned char)0xC1); |
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|
2827 emit_int8((unsigned char)(0xE8 | encode)); |
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|
2828 emit_int8(imm8); |
304 | 2829 } |
2830 | |
2831 void Assembler::shrl(Register dst) { | |
2832 int encode = prefix_and_encode(dst->encoding()); | |
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|
2833 emit_int8((unsigned char)0xD3); |
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|
2834 emit_int8((unsigned char)(0xE8 | encode)); |
304 | 2835 } |
0 | 2836 |
2837 // copies a single word from [esi] to [edi] | |
2838 void Assembler::smovl() { | |
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2839 emit_int8((unsigned char)0xA5); |
0 | 2840 } |
2841 | |
304 | 2842 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
2843 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2844 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); |
304 | 2845 } |
2846 | |
2008 | 2847 void Assembler::sqrtsd(XMMRegister dst, Address src) { |
2848 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2849 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); |
2008 | 2850 } |
2851 | |
2852 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { | |
4759 | 2853 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
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2854 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); |
2008 | 2855 } |
2856 | |
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2857 void Assembler::std() { |
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2858 emit_int8((unsigned char)0xFD); |
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2859 } |
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2860 |
2008 | 2861 void Assembler::sqrtss(XMMRegister dst, Address src) { |
4759 | 2862 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
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2863 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); |
2008 | 2864 } |
2865 | |
304 | 2866 void Assembler::stmxcsr( Address dst) { |
2867 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2868 InstructionMark im(this); | |
2869 prefix(dst); | |
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changeset
|
2870 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
2871 emit_int8((unsigned char)0xAE); |
304 | 2872 emit_operand(as_Register(3), dst); |
2873 } | |
2874 | |
2875 void Assembler::subl(Address dst, int32_t imm32) { | |
2876 InstructionMark im(this); | |
2877 prefix(dst); | |
2100
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
2878 emit_arith_operand(0x81, rbp, dst, imm32); |
304 | 2879 } |
2880 | |
2881 void Assembler::subl(Address dst, Register src) { | |
2882 InstructionMark im(this); | |
2883 prefix(dst, src); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
2884 emit_int8(0x29); |
304 | 2885 emit_operand(src, dst); |
2886 } | |
2887 | |
2100
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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parents:
2014
diff
changeset
|
2888 void Assembler::subl(Register dst, int32_t imm32) { |
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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parents:
2014
diff
changeset
|
2889 prefix(dst); |
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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parents:
2014
diff
changeset
|
2890 emit_arith(0x81, 0xE8, dst, imm32); |
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
2891 } |
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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2014
diff
changeset
|
2892 |
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
2893 // Force generation of a 4 byte immediate value even if it fits into 8bit |
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
2894 void Assembler::subl_imm32(Register dst, int32_t imm32) { |
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
2895 prefix(dst); |
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
2896 emit_arith_imm32(0x81, 0xE8, dst, imm32); |
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
2897 } |
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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parents:
4770
diff
changeset
|
2898 |
304 | 2899 void Assembler::subl(Register dst, Address src) { |
2900 InstructionMark im(this); | |
2901 prefix(src, dst); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
2902 emit_int8(0x2B); |
304 | 2903 emit_operand(dst, src); |
2904 } | |
2905 | |
2906 void Assembler::subl(Register dst, Register src) { | |
2907 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2908 emit_arith(0x2B, 0xC0, dst, src); | |
2909 } | |
2910 | |
2911 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | |
2912 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2913 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2); |
304 | 2914 } |
2915 | |
2916 void Assembler::subsd(XMMRegister dst, Address src) { | |
2917 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2918 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2); |
304 | 2919 } |
2920 | |
2921 void Assembler::subss(XMMRegister dst, XMMRegister src) { | |
2922 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2923 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3); |
304 | 2924 } |
2925 | |
2926 void Assembler::subss(XMMRegister dst, Address src) { | |
2927 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2928 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3); |
304 | 2929 } |
2930 | |
2931 void Assembler::testb(Register dst, int imm8) { | |
2932 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
2933 (void) prefix_and_encode(dst->encoding(), true); | |
2934 emit_arith_b(0xF6, 0xC0, dst, imm8); | |
2935 } | |
2936 | |
2937 void Assembler::testl(Register dst, int32_t imm32) { | |
2938 // not using emit_arith because test | |
2939 // doesn't support sign-extension of | |
2940 // 8bit operands | |
2941 int encode = dst->encoding(); | |
2942 if (encode == 0) { | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
2943 emit_int8((unsigned char)0xA9); |
304 | 2944 } else { |
2945 encode = prefix_and_encode(encode); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
2946 emit_int8((unsigned char)0xF7); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
2947 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 2948 } |
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
twisti
parents:
7475
diff
changeset
|
2949 emit_int32(imm32); |
304 | 2950 } |
2951 | |
2952 void Assembler::testl(Register dst, Register src) { | |
2953 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2954 emit_arith(0x85, 0xC0, dst, src); | |
2955 } | |
2956 | |
2957 void Assembler::testl(Register dst, Address src) { | |
2958 InstructionMark im(this); | |
2959 prefix(src, dst); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
2960 emit_int8((unsigned char)0x85); |
304 | 2961 emit_operand(dst, src); |
2962 } | |
2963 | |
14693
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
2964 void Assembler::tzcntl(Register dst, Register src) { |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
2965 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported"); |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
2966 emit_int8((unsigned char)0xF3); |
9e9af3aa4278
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iveresov
parents:
12972
diff
changeset
|
2967 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
2968 emit_int8(0x0F); |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
2969 emit_int8((unsigned char)0xBC); |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
2970 emit_int8((unsigned char)0xC0 | encode); |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
2971 } |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
2972 |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
2973 void Assembler::tzcntq(Register dst, Register src) { |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
2974 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported"); |
9e9af3aa4278
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iveresov
parents:
12972
diff
changeset
|
2975 emit_int8((unsigned char)0xF3); |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
2976 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
2977 emit_int8(0x0F); |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
2978 emit_int8((unsigned char)0xBC); |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
2979 emit_int8((unsigned char)(0xC0 | encode)); |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
2980 } |
9e9af3aa4278
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iveresov
parents:
12972
diff
changeset
|
2981 |
304 | 2982 void Assembler::ucomisd(XMMRegister dst, Address src) { |
2983 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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parents:
6266
diff
changeset
|
2984 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66); |
304 | 2985 } |
2986 | |
2987 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | |
2988 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2989 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66); |
304 | 2990 } |
2991 | |
2992 void Assembler::ucomiss(XMMRegister dst, Address src) { | |
2993 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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6266
diff
changeset
|
2994 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE); |
304 | 2995 } |
2996 | |
2997 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | |
2998 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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parents:
6266
diff
changeset
|
2999 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE); |
304 | 3000 } |
3001 | |
17780 | 3002 void Assembler::xabort(int8_t imm8) { |
3003 emit_int8((unsigned char)0xC6); | |
3004 emit_int8((unsigned char)0xF8); | |
3005 emit_int8((unsigned char)(imm8 & 0xFF)); | |
3006 } | |
304 | 3007 |
3008 void Assembler::xaddl(Address dst, Register src) { | |
3009 InstructionMark im(this); | |
3010 prefix(dst, src); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
3011 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3012 emit_int8((unsigned char)0xC1); |
304 | 3013 emit_operand(src, dst); |
3014 } | |
3015 | |
17780 | 3016 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) { |
3017 InstructionMark im(this); | |
3018 relocate(rtype); | |
3019 if (abort.is_bound()) { | |
3020 address entry = target(abort); | |
3021 assert(entry != NULL, "abort entry NULL"); | |
3022 intptr_t offset = entry - pc(); | |
3023 emit_int8((unsigned char)0xC7); | |
3024 emit_int8((unsigned char)0xF8); | |
3025 emit_int32(offset - 6); // 2 opcode + 4 address | |
3026 } else { | |
3027 abort.add_patch_at(code(), locator()); | |
3028 emit_int8((unsigned char)0xC7); | |
3029 emit_int8((unsigned char)0xF8); | |
3030 emit_int32(0); | |
3031 } | |
3032 } | |
3033 | |
304 | 3034 void Assembler::xchgl(Register dst, Address src) { // xchg |
3035 InstructionMark im(this); | |
3036 prefix(src, dst); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3037 emit_int8((unsigned char)0x87); |
304 | 3038 emit_operand(dst, src); |
3039 } | |
3040 | |
3041 void Assembler::xchgl(Register dst, Register src) { | |
3042 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
3043 emit_int8((unsigned char)0x87); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3044 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 3045 } |
3046 | |
17780 | 3047 void Assembler::xend() { |
3048 emit_int8((unsigned char)0x0F); | |
3049 emit_int8((unsigned char)0x01); | |
3050 emit_int8((unsigned char)0xD5); | |
3051 } | |
3052 | |
7199
cd3d6a6b95d9
8003240: x86: move MacroAssembler into separate file
twisti
parents:
7198
diff
changeset
|
3053 void Assembler::xgetbv() { |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3054 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3055 emit_int8(0x01); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3056 emit_int8((unsigned char)0xD0); |
7199
cd3d6a6b95d9
8003240: x86: move MacroAssembler into separate file
twisti
parents:
7198
diff
changeset
|
3057 } |
cd3d6a6b95d9
8003240: x86: move MacroAssembler into separate file
twisti
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7198
diff
changeset
|
3058 |
304 | 3059 void Assembler::xorl(Register dst, int32_t imm32) { |
3060 prefix(dst); | |
3061 emit_arith(0x81, 0xF0, dst, imm32); | |
3062 } | |
3063 | |
3064 void Assembler::xorl(Register dst, Address src) { | |
3065 InstructionMark im(this); | |
3066 prefix(src, dst); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
3067 emit_int8(0x33); |
304 | 3068 emit_operand(dst, src); |
3069 } | |
3070 | |
3071 void Assembler::xorl(Register dst, Register src) { | |
3072 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
3073 emit_arith(0x33, 0xC0, dst, src); | |
3074 } | |
3075 | |
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
3076 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
3077 // AVX 3-operands scalar float-point arithmetic instructions |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
3078 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
3079 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
3080 assert(VM_Version::supports_avx(), ""); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
3081 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
3082 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
3083 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
3084 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
3085 assert(VM_Version::supports_avx(), ""); |
6614
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changeset
|
3086 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
3087 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
3088 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
3089 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
3090 assert(VM_Version::supports_avx(), ""); |
6614
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changeset
|
3091 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
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diff
changeset
|
3092 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
3093 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
3094 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
3095 assert(VM_Version::supports_avx(), ""); |
6614
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changeset
|
3096 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
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changeset
|
3097 } |
65149e74c706
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changeset
|
3098 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
3099 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
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changeset
|
3100 assert(VM_Version::supports_avx(), ""); |
6614
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changeset
|
3101 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
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diff
changeset
|
3102 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3103 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3104 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3105 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3106 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3107 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3108 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3109 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3110 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3111 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3112 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3113 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3114 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3115 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3116 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3117 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3118 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3119 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3120 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3121 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3122 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3123 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3124 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3125 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3126 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3127 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3128 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3129 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3130 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3131 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3132 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3133 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3134 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3135 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3136 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3137 } |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3138 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3139 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3140 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3141 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3142 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3143 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3144 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3145 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3146 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3147 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3148 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3149 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3150 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3151 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3152 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3153 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3154 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3155 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3156 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3157 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3158 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3159 //====================VECTOR ARITHMETIC===================================== |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3160 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3161 // Float-point vector arithmetic |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3162 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3163 void Assembler::addpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3164 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3165 emit_simd_arith(0x58, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3166 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3167 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3168 void Assembler::addps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3169 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3170 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3171 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3172 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3173 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3174 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3175 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3176 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3177 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3178 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3179 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3180 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3181 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3182 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3183 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3184 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3185 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3186 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3187 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3188 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3189 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3190 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3191 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3192 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3193 void Assembler::subpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3194 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3195 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3196 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3197 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3198 void Assembler::subps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3199 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3200 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3201 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3202 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3203 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3204 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3205 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3206 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3207 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3208 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3209 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3210 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3211 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3212 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3213 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3214 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3215 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3216 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3217 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3218 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3219 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3220 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3221 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3222 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3223 void Assembler::mulpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3224 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3225 emit_simd_arith(0x59, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3226 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3227 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3228 void Assembler::mulps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3229 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3230 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3231 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3232 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3233 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3234 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3235 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3236 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3237 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3238 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3239 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3240 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3241 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3242 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3243 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3244 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3245 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3246 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3247 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3248 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3249 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3250 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3251 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3252 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3253 void Assembler::divpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3254 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3255 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3256 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3257 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3258 void Assembler::divps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3259 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3260 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3261 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3262 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3263 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3264 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3265 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3266 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3267 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3268 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3269 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3270 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3271 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3272 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3273 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3274 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3275 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3276 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3277 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3278 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3279 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3280 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3281 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3282 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3283 void Assembler::andpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3284 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3285 emit_simd_arith(0x54, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3286 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3287 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3288 void Assembler::andps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3289 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3290 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3291 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3292 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3293 void Assembler::andps(XMMRegister dst, Address src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3294 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3295 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3296 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3297 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3298 void Assembler::andpd(XMMRegister dst, Address src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3299 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3300 emit_simd_arith(0x54, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3301 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3302 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3303 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3304 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3305 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3306 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3307 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3308 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3309 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3310 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3311 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3312 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3313 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3314 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3315 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3316 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3317 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3318 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3319 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3320 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3321 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3322 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3323 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3324 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3325 emit_simd_arith(0x57, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3326 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3327 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3328 void Assembler::xorps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3329 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3330 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3331 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3332 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3333 void Assembler::xorpd(XMMRegister dst, Address src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3334 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3335 emit_simd_arith(0x57, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3336 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3337 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3338 void Assembler::xorps(XMMRegister dst, Address src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3339 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3340 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3341 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3342 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3343 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3344 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3345 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3346 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3347 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3348 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3349 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3350 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3351 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3352 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3353 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3354 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3355 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3356 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3357 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3358 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3359 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3360 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3361 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3362 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3363 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3364 // Integer vector arithmetic |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3365 void Assembler::paddb(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3366 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3367 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3368 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3369 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3370 void Assembler::paddw(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3371 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3372 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3373 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3374 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3375 void Assembler::paddd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3376 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3377 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3378 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3379 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3380 void Assembler::paddq(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3381 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3382 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3383 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3384 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3385 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3386 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3387 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3388 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3389 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3390 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3391 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3392 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3393 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3394 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3395 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3396 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3397 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3398 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3399 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3400 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3401 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3402 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3403 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3404 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3405 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3406 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3407 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3408 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3409 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3410 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3411 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3412 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3413 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3414 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3415 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3416 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3417 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3418 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3419 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3420 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3421 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3422 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3423 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3424 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3425 void Assembler::psubb(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3426 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3427 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3428 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3429 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3430 void Assembler::psubw(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3431 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3432 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3433 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3434 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3435 void Assembler::psubd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3436 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3437 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3438 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3439 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3440 void Assembler::psubq(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3441 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3442 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3443 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3444 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3445 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3446 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3447 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3448 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3449 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3450 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3451 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3452 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3453 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3454 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3455 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3456 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3457 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3458 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3459 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3460 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3461 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3462 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3463 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3464 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3465 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3466 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3467 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3468 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3469 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3470 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3471 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3472 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3473 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3474 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3475 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3476 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3477 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3478 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3479 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3480 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3481 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3482 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3483 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3484 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3485 void Assembler::pmullw(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3486 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3487 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3488 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3489 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3490 void Assembler::pmulld(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3491 assert(VM_Version::supports_sse4_1(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3492 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3493 emit_int8(0x40); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3494 emit_int8((unsigned char)(0xC0 | encode)); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3495 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3496 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3497 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3498 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3499 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3500 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3501 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3502 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3503 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3504 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3505 emit_int8(0x40); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3506 emit_int8((unsigned char)(0xC0 | encode)); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3507 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3508 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3509 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3510 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3511 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3512 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3513 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3514 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3515 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3516 InstructionMark im(this); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3517 int dst_enc = dst->encoding(); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3518 int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3519 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3520 emit_int8(0x40); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3521 emit_operand(dst, src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3522 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3523 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3524 // Shift packed integers left by specified number of bits. |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3525 void Assembler::psllw(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3526 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3527 // XMM6 is for /6 encoding: 66 0F 71 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3528 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3529 emit_int8(0x71); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3530 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3531 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3532 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3533 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3534 void Assembler::pslld(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3535 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3536 // XMM6 is for /6 encoding: 66 0F 72 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3537 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3538 emit_int8(0x72); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3539 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3540 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3541 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3542 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3543 void Assembler::psllq(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3544 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3545 // XMM6 is for /6 encoding: 66 0F 73 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3546 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3547 emit_int8(0x73); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3548 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3549 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3550 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3551 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3552 void Assembler::psllw(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3553 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3554 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3555 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3556 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3557 void Assembler::pslld(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3558 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3559 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3560 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3561 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3562 void Assembler::psllq(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3563 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3564 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3565 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3566 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3567 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3568 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3569 // XMM6 is for /6 encoding: 66 0F 71 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3570 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3571 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3572 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3573 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3574 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3575 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3576 // XMM6 is for /6 encoding: 66 0F 72 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3577 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3578 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3579 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3580 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3581 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3582 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3583 // XMM6 is for /6 encoding: 66 0F 73 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3584 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3585 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3586 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3587 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3588 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3589 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3590 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3591 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3592 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3593 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3594 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3595 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3596 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3597 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3598 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3599 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3600 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3601 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3602 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3603 // Shift packed integers logically right by specified number of bits. |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3604 void Assembler::psrlw(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3605 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3606 // XMM2 is for /2 encoding: 66 0F 71 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3607 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3608 emit_int8(0x71); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3609 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3610 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3611 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3612 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3613 void Assembler::psrld(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3614 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3615 // XMM2 is for /2 encoding: 66 0F 72 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3616 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3617 emit_int8(0x72); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3618 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3619 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3620 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3621 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3622 void Assembler::psrlq(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3623 // Do not confuse it with psrldq SSE2 instruction which |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3624 // shifts 128 bit value in xmm register by number of bytes. |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3625 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3626 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3627 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3628 emit_int8(0x73); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3629 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3630 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3631 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3632 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3633 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3634 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3635 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3636 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3637 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3638 void Assembler::psrld(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3639 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3640 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3641 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3642 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3643 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3644 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3645 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3646 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3647 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3648 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3649 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3650 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3651 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3652 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3653 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3654 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3655 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3656 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3657 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3658 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3659 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3660 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3661 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3662 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3663 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3664 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3665 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3666 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3667 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3668 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3669 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3670 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3671 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3672 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3673 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3674 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3675 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3676 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3677 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3678 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3679 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3680 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3681 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3682 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3683 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3684 // Shift packed integers arithmetically right by specified number of bits. |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3685 void Assembler::psraw(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3686 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3687 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3688 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3689 emit_int8(0x71); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3690 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3691 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3692 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3693 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3694 void Assembler::psrad(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3695 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3696 // XMM4 is for /4 encoding: 66 0F 72 /4 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3697 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3698 emit_int8(0x72); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3699 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3700 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3701 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3702 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3703 void Assembler::psraw(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3704 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3705 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3706 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3707 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3708 void Assembler::psrad(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3709 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3710 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3711 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3712 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3713 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3714 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3715 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3716 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3717 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3718 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3719 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3720 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3721 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3722 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3723 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3724 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3725 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3726 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3727 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3728 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3729 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3730 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3731 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3732 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3733 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3734 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3735 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3736 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3737 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3738 // AND packed integers |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3739 void Assembler::pand(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3740 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3741 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3742 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3743 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3744 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3745 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3746 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3747 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3748 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3749 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3750 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3751 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3752 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3753 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3754 void Assembler::por(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3755 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3756 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3757 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3758 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3759 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3760 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3761 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3762 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3763 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3764 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3765 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3766 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3767 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3768 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3769 void Assembler::pxor(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3770 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3771 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66); |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3772 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3773 |
6225 | 3774 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3775 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3776 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3777 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3778 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3779 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3780 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3781 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3782 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3783 |
6225 | 3784 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3785 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3786 assert(VM_Version::supports_avx(), ""); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3787 bool vector256 = true; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3788 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3789 emit_int8(0x18); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3790 emit_int8((unsigned char)(0xC0 | encode)); |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3791 // 0x00 - insert into lower 128 bits |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3792 // 0x01 - insert into upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3793 emit_int8(0x01); |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3794 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3795 |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3796 void Assembler::vinsertf128h(XMMRegister dst, Address src) { |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3797 assert(VM_Version::supports_avx(), ""); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3798 InstructionMark im(this); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3799 bool vector256 = true; |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3800 assert(dst != xnoreg, "sanity"); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3801 int dst_enc = dst->encoding(); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3802 // swap src<->dst for encoding |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3803 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3804 emit_int8(0x18); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3805 emit_operand(dst, src); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3806 // 0x01 - insert into upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3807 emit_int8(0x01); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3808 } |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3809 |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3810 void Assembler::vextractf128h(Address dst, XMMRegister src) { |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3811 assert(VM_Version::supports_avx(), ""); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3812 InstructionMark im(this); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3813 bool vector256 = true; |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3814 assert(src != xnoreg, "sanity"); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3815 int src_enc = src->encoding(); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3816 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3817 emit_int8(0x19); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3818 emit_operand(src, dst); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3819 // 0x01 - extract from upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3820 emit_int8(0x01); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3821 } |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3822 |
6225 | 3823 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
3824 assert(VM_Version::supports_avx2(), ""); | |
3825 bool vector256 = true; | |
3826 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3827 emit_int8(0x38); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3828 emit_int8((unsigned char)(0xC0 | encode)); |
6225 | 3829 // 0x00 - insert into lower 128 bits |
3830 // 0x01 - insert into upper 128 bits | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3831 emit_int8(0x01); |
6225 | 3832 } |
3833 | |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3834 void Assembler::vinserti128h(XMMRegister dst, Address src) { |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3835 assert(VM_Version::supports_avx2(), ""); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3836 InstructionMark im(this); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3837 bool vector256 = true; |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3838 assert(dst != xnoreg, "sanity"); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3839 int dst_enc = dst->encoding(); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3840 // swap src<->dst for encoding |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3841 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3842 emit_int8(0x38); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3843 emit_operand(dst, src); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3844 // 0x01 - insert into upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3845 emit_int8(0x01); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3846 } |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3847 |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3848 void Assembler::vextracti128h(Address dst, XMMRegister src) { |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3849 assert(VM_Version::supports_avx2(), ""); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3850 InstructionMark im(this); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3851 bool vector256 = true; |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3852 assert(src != xnoreg, "sanity"); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3853 int src_enc = src->encoding(); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3854 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3855 emit_int8(0x39); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3856 emit_operand(src, dst); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3857 // 0x01 - extract from upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3858 emit_int8(0x01); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3859 } |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3860 |
7475
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3861 // duplicate 4-bytes integer data from src into 8 locations in dest |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3862 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) { |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3863 assert(VM_Version::supports_avx2(), ""); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3864 bool vector256 = true; |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3865 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3866 emit_int8(0x58); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3867 emit_int8((unsigned char)(0xC0 | encode)); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3868 } |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3869 |
11080
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3870 // Carry-Less Multiplication Quadword |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3871 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) { |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3872 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), ""); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3873 bool vector256 = false; |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3874 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3875 emit_int8(0x44); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3876 emit_int8((unsigned char)(0xC0 | encode)); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3877 emit_int8((unsigned char)mask); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3878 } |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3879 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3880 void Assembler::vzeroupper() { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3881 assert(VM_Version::supports_avx(), ""); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3882 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3883 emit_int8(0x77); |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3884 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3885 |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3886 |
304 | 3887 #ifndef _LP64 |
3888 // 32bit only pieces of the assembler | |
3889 | |
3890 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | |
3891 // NO PREFIX AS NEVER 64BIT | |
3892 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3893 emit_int8((unsigned char)0x81); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3894 emit_int8((unsigned char)(0xF8 | src1->encoding())); |
304 | 3895 emit_data(imm32, rspec, 0); |
3896 } | |
3897 | |
3898 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { | |
3899 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs | |
3900 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3901 emit_int8((unsigned char)0x81); |
304 | 3902 emit_operand(rdi, src1); |
3903 emit_data(imm32, rspec, 0); | |
3904 } | |
3905 | |
3906 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, | |
3907 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded | |
3908 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. | |
3909 void Assembler::cmpxchg8(Address adr) { | |
3910 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3911 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3912 emit_int8((unsigned char)0xC7); |
304 | 3913 emit_operand(rcx, adr); |
3914 } | |
3915 | |
3916 void Assembler::decl(Register dst) { | |
3917 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3918 emit_int8(0x48 | dst->encoding()); |
304 | 3919 } |
3920 | |
3921 #endif // _LP64 | |
3922 | |
3923 // 64bit typically doesn't use the x87 but needs to for the trig funcs | |
3924 | |
3925 void Assembler::fabs() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3926 emit_int8((unsigned char)0xD9); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3927 emit_int8((unsigned char)0xE1); |
304 | 3928 } |
3929 | |
3930 void Assembler::fadd(int i) { | |
3931 emit_farith(0xD8, 0xC0, i); | |
3932 } | |
3933 | |
3934 void Assembler::fadd_d(Address src) { | |
3935 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3936 emit_int8((unsigned char)0xDC); |
304 | 3937 emit_operand32(rax, src); |
3938 } | |
3939 | |
3940 void Assembler::fadd_s(Address src) { | |
3941 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3942 emit_int8((unsigned char)0xD8); |
304 | 3943 emit_operand32(rax, src); |
3944 } | |
3945 | |
3946 void Assembler::fadda(int i) { | |
3947 emit_farith(0xDC, 0xC0, i); | |
3948 } | |
3949 | |
3950 void Assembler::faddp(int i) { | |
3951 emit_farith(0xDE, 0xC0, i); | |
3952 } | |
3953 | |
3954 void Assembler::fchs() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3955 emit_int8((unsigned char)0xD9); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3956 emit_int8((unsigned char)0xE0); |
304 | 3957 } |
3958 | |
3959 void Assembler::fcom(int i) { | |
3960 emit_farith(0xD8, 0xD0, i); | |
3961 } | |
3962 | |
3963 void Assembler::fcomp(int i) { | |
3964 emit_farith(0xD8, 0xD8, i); | |
3965 } | |
3966 | |
3967 void Assembler::fcomp_d(Address src) { | |
3968 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3969 emit_int8((unsigned char)0xDC); |
304 | 3970 emit_operand32(rbx, src); |
3971 } | |
3972 | |
3973 void Assembler::fcomp_s(Address src) { | |
3974 InstructionMark im(this); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3975 emit_int8((unsigned char)0xD8); |
304 | 3976 emit_operand32(rbx, src); |
3977 } | |
3978 | |
3979 void Assembler::fcompp() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3980 emit_int8((unsigned char)0xDE); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3981 emit_int8((unsigned char)0xD9); |
304 | 3982 } |
3983 | |
3984 void Assembler::fcos() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3985 emit_int8((unsigned char)0xD9); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3986 emit_int8((unsigned char)0xFF); |
304 | 3987 } |
3988 | |
3989 void Assembler::fdecstp() { | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3990 emit_int8((unsigned char)0xD9); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3991 emit_int8((unsigned char)0xF6); |
304 | 3992 } |
3993 | |
3994 void Assembler::fdiv(int i) { | |
3995 emit_farith(0xD8, 0xF0, i); | |
3996 } | |
3997 | |
3998 void Assembler::fdiv_d(Address src) { | |
3999 InstructionMark im(this); | |
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|
4000 emit_int8((unsigned char)0xDC); |
304 | 4001 emit_operand32(rsi, src); |
4002 } | |
4003 | |
4004 void Assembler::fdiv_s(Address src) { | |
4005 InstructionMark im(this); | |
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changeset
|
4006 emit_int8((unsigned char)0xD8); |
304 | 4007 emit_operand32(rsi, src); |
4008 } | |
4009 | |
4010 void Assembler::fdiva(int i) { | |
4011 emit_farith(0xDC, 0xF8, i); | |
4012 } | |
4013 | |
4014 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) | |
4015 // is erroneous for some of the floating-point instructions below. | |
4016 | |
4017 void Assembler::fdivp(int i) { | |
4018 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) | |
4019 } | |
4020 | |
4021 void Assembler::fdivr(int i) { | |
4022 emit_farith(0xD8, 0xF8, i); | |
4023 } | |
4024 | |
4025 void Assembler::fdivr_d(Address src) { | |
4026 InstructionMark im(this); | |
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|
4027 emit_int8((unsigned char)0xDC); |
304 | 4028 emit_operand32(rdi, src); |
4029 } | |
4030 | |
4031 void Assembler::fdivr_s(Address src) { | |
4032 InstructionMark im(this); | |
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|
4033 emit_int8((unsigned char)0xD8); |
304 | 4034 emit_operand32(rdi, src); |
4035 } | |
4036 | |
4037 void Assembler::fdivra(int i) { | |
4038 emit_farith(0xDC, 0xF0, i); | |
4039 } | |
4040 | |
4041 void Assembler::fdivrp(int i) { | |
4042 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) | |
4043 } | |
4044 | |
4045 void Assembler::ffree(int i) { | |
4046 emit_farith(0xDD, 0xC0, i); | |
4047 } | |
4048 | |
4049 void Assembler::fild_d(Address adr) { | |
4050 InstructionMark im(this); | |
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|
4051 emit_int8((unsigned char)0xDF); |
304 | 4052 emit_operand32(rbp, adr); |
4053 } | |
4054 | |
4055 void Assembler::fild_s(Address adr) { | |
4056 InstructionMark im(this); | |
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|
4057 emit_int8((unsigned char)0xDB); |
304 | 4058 emit_operand32(rax, adr); |
4059 } | |
4060 | |
4061 void Assembler::fincstp() { | |
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4062 emit_int8((unsigned char)0xD9); |
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|
4063 emit_int8((unsigned char)0xF7); |
304 | 4064 } |
4065 | |
4066 void Assembler::finit() { | |
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|
4067 emit_int8((unsigned char)0x9B); |
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|
4068 emit_int8((unsigned char)0xDB); |
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|
4069 emit_int8((unsigned char)0xE3); |
304 | 4070 } |
4071 | |
4072 void Assembler::fist_s(Address adr) { | |
4073 InstructionMark im(this); | |
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|
4074 emit_int8((unsigned char)0xDB); |
304 | 4075 emit_operand32(rdx, adr); |
4076 } | |
4077 | |
4078 void Assembler::fistp_d(Address adr) { | |
4079 InstructionMark im(this); | |
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|
4080 emit_int8((unsigned char)0xDF); |
304 | 4081 emit_operand32(rdi, adr); |
4082 } | |
4083 | |
4084 void Assembler::fistp_s(Address adr) { | |
4085 InstructionMark im(this); | |
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|
4086 emit_int8((unsigned char)0xDB); |
304 | 4087 emit_operand32(rbx, adr); |
4088 } | |
0 | 4089 |
4090 void Assembler::fld1() { | |
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|
4091 emit_int8((unsigned char)0xD9); |
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|
4092 emit_int8((unsigned char)0xE8); |
0 | 4093 } |
4094 | |
304 | 4095 void Assembler::fld_d(Address adr) { |
4096 InstructionMark im(this); | |
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|
4097 emit_int8((unsigned char)0xDD); |
304 | 4098 emit_operand32(rax, adr); |
4099 } | |
0 | 4100 |
4101 void Assembler::fld_s(Address adr) { | |
4102 InstructionMark im(this); | |
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|
4103 emit_int8((unsigned char)0xD9); |
304 | 4104 emit_operand32(rax, adr); |
4105 } | |
4106 | |
4107 | |
4108 void Assembler::fld_s(int index) { | |
0 | 4109 emit_farith(0xD9, 0xC0, index); |
4110 } | |
4111 | |
4112 void Assembler::fld_x(Address adr) { | |
4113 InstructionMark im(this); | |
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|
4114 emit_int8((unsigned char)0xDB); |
304 | 4115 emit_operand32(rbp, adr); |
4116 } | |
4117 | |
4118 void Assembler::fldcw(Address src) { | |
4119 InstructionMark im(this); | |
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4120 emit_int8((unsigned char)0xD9); |
304 | 4121 emit_operand32(rbp, src); |
4122 } | |
4123 | |
4124 void Assembler::fldenv(Address src) { | |
0 | 4125 InstructionMark im(this); |
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|
4126 emit_int8((unsigned char)0xD9); |
304 | 4127 emit_operand32(rsp, src); |
4128 } | |
4129 | |
4130 void Assembler::fldlg2() { | |
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4131 emit_int8((unsigned char)0xD9); |
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4132 emit_int8((unsigned char)0xEC); |
304 | 4133 } |
0 | 4134 |
4135 void Assembler::fldln2() { | |
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4136 emit_int8((unsigned char)0xD9); |
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4137 emit_int8((unsigned char)0xED); |
0 | 4138 } |
4139 | |
304 | 4140 void Assembler::fldz() { |
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4141 emit_int8((unsigned char)0xD9); |
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4142 emit_int8((unsigned char)0xEE); |
304 | 4143 } |
0 | 4144 |
4145 void Assembler::flog() { | |
4146 fldln2(); | |
4147 fxch(); | |
4148 fyl2x(); | |
4149 } | |
4150 | |
4151 void Assembler::flog10() { | |
4152 fldlg2(); | |
4153 fxch(); | |
4154 fyl2x(); | |
4155 } | |
4156 | |
304 | 4157 void Assembler::fmul(int i) { |
4158 emit_farith(0xD8, 0xC8, i); | |
4159 } | |
4160 | |
4161 void Assembler::fmul_d(Address src) { | |
4162 InstructionMark im(this); | |
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|
4163 emit_int8((unsigned char)0xDC); |
304 | 4164 emit_operand32(rcx, src); |
4165 } | |
4166 | |
4167 void Assembler::fmul_s(Address src) { | |
4168 InstructionMark im(this); | |
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4169 emit_int8((unsigned char)0xD8); |
304 | 4170 emit_operand32(rcx, src); |
4171 } | |
4172 | |
4173 void Assembler::fmula(int i) { | |
4174 emit_farith(0xDC, 0xC8, i); | |
4175 } | |
4176 | |
4177 void Assembler::fmulp(int i) { | |
4178 emit_farith(0xDE, 0xC8, i); | |
4179 } | |
4180 | |
4181 void Assembler::fnsave(Address dst) { | |
4182 InstructionMark im(this); | |
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4183 emit_int8((unsigned char)0xDD); |
304 | 4184 emit_operand32(rsi, dst); |
4185 } | |
4186 | |
4187 void Assembler::fnstcw(Address src) { | |
4188 InstructionMark im(this); | |
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|
4189 emit_int8((unsigned char)0x9B); |
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|
4190 emit_int8((unsigned char)0xD9); |
304 | 4191 emit_operand32(rdi, src); |
4192 } | |
4193 | |
4194 void Assembler::fnstsw_ax() { | |
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|
4195 emit_int8((unsigned char)0xDF); |
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4196 emit_int8((unsigned char)0xE0); |
304 | 4197 } |
4198 | |
4199 void Assembler::fprem() { | |
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|
4200 emit_int8((unsigned char)0xD9); |
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changeset
|
4201 emit_int8((unsigned char)0xF8); |
304 | 4202 } |
4203 | |
4204 void Assembler::fprem1() { | |
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|
4205 emit_int8((unsigned char)0xD9); |
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changeset
|
4206 emit_int8((unsigned char)0xF5); |
304 | 4207 } |
4208 | |
4209 void Assembler::frstor(Address src) { | |
4210 InstructionMark im(this); | |
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|
4211 emit_int8((unsigned char)0xDD); |
304 | 4212 emit_operand32(rsp, src); |
4213 } | |
0 | 4214 |
4215 void Assembler::fsin() { | |
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changeset
|
4216 emit_int8((unsigned char)0xD9); |
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changeset
|
4217 emit_int8((unsigned char)0xFE); |
0 | 4218 } |
4219 | |
304 | 4220 void Assembler::fsqrt() { |
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changeset
|
4221 emit_int8((unsigned char)0xD9); |
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changeset
|
4222 emit_int8((unsigned char)0xFA); |
304 | 4223 } |
4224 | |
4225 void Assembler::fst_d(Address adr) { | |
4226 InstructionMark im(this); | |
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|
4227 emit_int8((unsigned char)0xDD); |
304 | 4228 emit_operand32(rdx, adr); |
4229 } | |
4230 | |
4231 void Assembler::fst_s(Address adr) { | |
4232 InstructionMark im(this); | |
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changeset
|
4233 emit_int8((unsigned char)0xD9); |
304 | 4234 emit_operand32(rdx, adr); |
4235 } | |
4236 | |
4237 void Assembler::fstp_d(Address adr) { | |
4238 InstructionMark im(this); | |
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changeset
|
4239 emit_int8((unsigned char)0xDD); |
304 | 4240 emit_operand32(rbx, adr); |
4241 } | |
4242 | |
4243 void Assembler::fstp_d(int index) { | |
4244 emit_farith(0xDD, 0xD8, index); | |
4245 } | |
4246 | |
4247 void Assembler::fstp_s(Address adr) { | |
4248 InstructionMark im(this); | |
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changeset
|
4249 emit_int8((unsigned char)0xD9); |
304 | 4250 emit_operand32(rbx, adr); |
4251 } | |
4252 | |
4253 void Assembler::fstp_x(Address adr) { | |
4254 InstructionMark im(this); | |
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|
4255 emit_int8((unsigned char)0xDB); |
304 | 4256 emit_operand32(rdi, adr); |
4257 } | |
4258 | |
4259 void Assembler::fsub(int i) { | |
4260 emit_farith(0xD8, 0xE0, i); | |
4261 } | |
4262 | |
4263 void Assembler::fsub_d(Address src) { | |
4264 InstructionMark im(this); | |
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|
4265 emit_int8((unsigned char)0xDC); |
304 | 4266 emit_operand32(rsp, src); |
4267 } | |
4268 | |
4269 void Assembler::fsub_s(Address src) { | |
4270 InstructionMark im(this); | |
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|
4271 emit_int8((unsigned char)0xD8); |
304 | 4272 emit_operand32(rsp, src); |
4273 } | |
4274 | |
4275 void Assembler::fsuba(int i) { | |
4276 emit_farith(0xDC, 0xE8, i); | |
4277 } | |
4278 | |
4279 void Assembler::fsubp(int i) { | |
4280 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) | |
4281 } | |
4282 | |
4283 void Assembler::fsubr(int i) { | |
4284 emit_farith(0xD8, 0xE8, i); | |
4285 } | |
4286 | |
4287 void Assembler::fsubr_d(Address src) { | |
4288 InstructionMark im(this); | |
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|
4289 emit_int8((unsigned char)0xDC); |
304 | 4290 emit_operand32(rbp, src); |
4291 } | |
4292 | |
4293 void Assembler::fsubr_s(Address src) { | |
4294 InstructionMark im(this); | |
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|
4295 emit_int8((unsigned char)0xD8); |
304 | 4296 emit_operand32(rbp, src); |
4297 } | |
4298 | |
4299 void Assembler::fsubra(int i) { | |
4300 emit_farith(0xDC, 0xE0, i); | |
4301 } | |
4302 | |
4303 void Assembler::fsubrp(int i) { | |
4304 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) | |
0 | 4305 } |
4306 | |
4307 void Assembler::ftan() { | |
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changeset
|
4308 emit_int8((unsigned char)0xD9); |
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changeset
|
4309 emit_int8((unsigned char)0xF2); |
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changeset
|
4310 emit_int8((unsigned char)0xDD); |
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changeset
|
4311 emit_int8((unsigned char)0xD8); |
0 | 4312 } |
4313 | |
304 | 4314 void Assembler::ftst() { |
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changeset
|
4315 emit_int8((unsigned char)0xD9); |
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|
4316 emit_int8((unsigned char)0xE4); |
304 | 4317 } |
0 | 4318 |
4319 void Assembler::fucomi(int i) { | |
4320 // make sure the instruction is supported (introduced for P6, together with cmov) | |
4321 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
4322 emit_farith(0xDB, 0xE8, i); | |
4323 } | |
4324 | |
4325 void Assembler::fucomip(int i) { | |
4326 // make sure the instruction is supported (introduced for P6, together with cmov) | |
4327 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
4328 emit_farith(0xDF, 0xE8, i); | |
4329 } | |
4330 | |
4331 void Assembler::fwait() { | |
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4332 emit_int8((unsigned char)0x9B); |
0 | 4333 } |
4334 | |
304 | 4335 void Assembler::fxch(int i) { |
4336 emit_farith(0xD9, 0xC8, i); | |
4337 } | |
4338 | |
4339 void Assembler::fyl2x() { | |
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4340 emit_int8((unsigned char)0xD9); |
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4341 emit_int8((unsigned char)0xF1); |
304 | 4342 } |
4343 | |
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4344 void Assembler::frndint() { |
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4345 emit_int8((unsigned char)0xD9); |
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4346 emit_int8((unsigned char)0xFC); |
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4347 } |
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4348 |
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4349 void Assembler::f2xm1() { |
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4350 emit_int8((unsigned char)0xD9); |
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4351 emit_int8((unsigned char)0xF0); |
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4352 } |
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4353 |
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4354 void Assembler::fldl2e() { |
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4355 emit_int8((unsigned char)0xD9); |
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4356 emit_int8((unsigned char)0xEA); |
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4357 } |
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4358 |
4759 | 4359 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. |
4360 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; | |
4361 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. | |
4362 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; | |
4363 | |
4364 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. | |
4365 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
4366 if (pre > 0) { | |
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4367 emit_int8(simd_pre[pre]); |
4759 | 4368 } |
4369 if (rex_w) { | |
4370 prefixq(adr, xreg); | |
4371 } else { | |
4372 prefix(adr, xreg); | |
4373 } | |
4374 if (opc > 0) { | |
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4375 emit_int8(0x0F); |
4759 | 4376 int opc2 = simd_opc[opc]; |
4377 if (opc2 > 0) { | |
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4378 emit_int8(opc2); |
4759 | 4379 } |
4380 } | |
4381 } | |
4382 | |
4383 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
4384 if (pre > 0) { | |
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4385 emit_int8(simd_pre[pre]); |
4759 | 4386 } |
4387 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : | |
4388 prefix_and_encode(dst_enc, src_enc); | |
4389 if (opc > 0) { | |
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4390 emit_int8(0x0F); |
4759 | 4391 int opc2 = simd_opc[opc]; |
4392 if (opc2 > 0) { | |
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4393 emit_int8(opc2); |
4759 | 4394 } |
4395 } | |
4396 return encode; | |
4397 } | |
4398 | |
4399 | |
4400 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) { | |
4401 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { | |
4402 prefix(VEX_3bytes); | |
4403 | |
4404 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); | |
4405 byte1 = (~byte1) & 0xE0; | |
4406 byte1 |= opc; | |
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4407 emit_int8(byte1); |
4759 | 4408 |
4409 int byte2 = ((~nds_enc) & 0xf) << 3; | |
4410 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre; | |
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4411 emit_int8(byte2); |
4759 | 4412 } else { |
4413 prefix(VEX_2bytes); | |
4414 | |
4415 int byte1 = vex_r ? VEX_R : 0; | |
4416 byte1 = (~byte1) & 0x80; | |
4417 byte1 |= ((~nds_enc) & 0xf) << 3; | |
4418 byte1 |= (vector256 ? 4 : 0) | pre; | |
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4419 emit_int8(byte1); |
4759 | 4420 } |
4421 } | |
4422 | |
4423 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){ | |
4424 bool vex_r = (xreg_enc >= 8); | |
4425 bool vex_b = adr.base_needs_rex(); | |
4426 bool vex_x = adr.index_needs_rex(); | |
4427 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
4428 } | |
4429 | |
4430 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) { | |
4431 bool vex_r = (dst_enc >= 8); | |
4432 bool vex_b = (src_enc >= 8); | |
4433 bool vex_x = false; | |
4434 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
4435 return (((dst_enc & 7) << 3) | (src_enc & 7)); | |
4436 } | |
4437 | |
4438 | |
4439 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
4440 if (UseAVX > 0) { | |
4441 int xreg_enc = xreg->encoding(); | |
4442 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
4443 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256); | |
4444 } else { | |
4445 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); | |
4446 rex_prefix(adr, xreg, pre, opc, rex_w); | |
4447 } | |
4448 } | |
4449 | |
4450 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
4451 int dst_enc = dst->encoding(); | |
4452 int src_enc = src->encoding(); | |
4453 if (UseAVX > 0) { | |
4454 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
4455 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256); | |
4456 } else { | |
4457 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); | |
4458 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w); | |
4459 } | |
4460 } | |
304 | 4461 |
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4462 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { |
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4463 InstructionMark im(this); |
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4464 simd_prefix(dst, dst, src, pre); |
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4465 emit_int8(opcode); |
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4466 emit_operand(dst, src); |
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|
4467 } |
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|
4468 |
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4469 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { |
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4470 int encode = simd_prefix_and_encode(dst, dst, src, pre); |
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|
4471 emit_int8(opcode); |
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4472 emit_int8((unsigned char)(0xC0 | encode)); |
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|
4473 } |
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|
4474 |
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|
4475 // Versions with no second source register (non-destructive source). |
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4476 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { |
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4477 InstructionMark im(this); |
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4478 simd_prefix(dst, xnoreg, src, pre); |
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|
4479 emit_int8(opcode); |
6614
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|
4480 emit_operand(dst, src); |
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|
4481 } |
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|
4482 |
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4483 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { |
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4484 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre); |
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|
4485 emit_int8(opcode); |
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|
4486 emit_int8((unsigned char)(0xC0 | encode)); |
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|
4487 } |
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|
4488 |
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|
4489 // 3-operands AVX instructions |
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4490 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
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4491 Address src, VexSimdPrefix pre, bool vector256) { |
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4492 InstructionMark im(this); |
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4493 vex_prefix(dst, nds, src, pre, vector256); |
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|
4494 emit_int8(opcode); |
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4495 emit_operand(dst, src); |
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|
4496 } |
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|
4497 |
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4498 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
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4499 XMMRegister src, VexSimdPrefix pre, bool vector256) { |
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4500 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256); |
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4501 emit_int8(opcode); |
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4502 emit_int8((unsigned char)(0xC0 | encode)); |
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4503 } |
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4504 |
304 | 4505 #ifndef _LP64 |
4506 | |
4507 void Assembler::incl(Register dst) { | |
4508 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
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4509 emit_int8(0x40 | dst->encoding()); |
304 | 4510 } |
4511 | |
4512 void Assembler::lea(Register dst, Address src) { | |
4513 leal(dst, src); | |
4514 } | |
4515 | |
4516 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { | |
4517 InstructionMark im(this); | |
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4518 emit_int8((unsigned char)0xC7); |
304 | 4519 emit_operand(rax, dst); |
4520 emit_data((int)imm32, rspec, 0); | |
4521 } | |
4522 | |
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4523 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
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4524 InstructionMark im(this); |
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4525 int encode = prefix_and_encode(dst->encoding()); |
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4526 emit_int8((unsigned char)(0xB8 | encode)); |
642
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4527 emit_data((int)imm32, rspec, 0); |
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4528 } |
304 | 4529 |
4530 void Assembler::popa() { // 32bit | |
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4531 emit_int8(0x61); |
304 | 4532 } |
4533 | |
4534 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { | |
4535 InstructionMark im(this); | |
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4536 emit_int8(0x68); |
304 | 4537 emit_data(imm32, rspec, 0); |
4538 } | |
4539 | |
4540 void Assembler::pusha() { // 32bit | |
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4541 emit_int8(0x60); |
304 | 4542 } |
4543 | |
4544 void Assembler::set_byte_if_not_zero(Register dst) { | |
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changeset
|
4545 emit_int8(0x0F); |
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|
4546 emit_int8((unsigned char)0x95); |
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diff
changeset
|
4547 emit_int8((unsigned char)(0xE0 | dst->encoding())); |
304 | 4548 } |
4549 | |
4550 void Assembler::shldl(Register dst, Register src) { | |
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|
4551 emit_int8(0x0F); |
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|
4552 emit_int8((unsigned char)0xA5); |
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changeset
|
4553 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); |
304 | 4554 } |
4555 | |
4556 void Assembler::shrdl(Register dst, Register src) { | |
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|
4557 emit_int8(0x0F); |
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diff
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|
4558 emit_int8((unsigned char)0xAD); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4559 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); |
304 | 4560 } |
4561 | |
4562 #else // LP64 | |
4563 | |
1369 | 4564 void Assembler::set_byte_if_not_zero(Register dst) { |
4565 int enc = prefix_and_encode(dst->encoding(), true); | |
7430
d02120b7a34f
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diff
changeset
|
4566 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
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|
4567 emit_int8((unsigned char)0x95); |
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changeset
|
4568 emit_int8((unsigned char)(0xE0 | enc)); |
1369 | 4569 } |
4570 | |
304 | 4571 // 64bit only pieces of the assembler |
4572 // This should only be used by 64bit instructions that can use rip-relative | |
4573 // it cannot be used by instructions that want an immediate value. | |
4574 | |
4575 bool Assembler::reachable(AddressLiteral adr) { | |
4576 int64_t disp; | |
4577 // None will force a 64bit literal to the code stream. Likely a placeholder | |
4578 // for something that will be patched later and we need to certain it will | |
4579 // always be reachable. | |
4580 if (adr.reloc() == relocInfo::none) { | |
4581 return false; | |
4582 } | |
4583 if (adr.reloc() == relocInfo::internal_word_type) { | |
4584 // This should be rip relative and easily reachable. | |
4585 return true; | |
4586 } | |
4587 if (adr.reloc() == relocInfo::virtual_call_type || | |
4588 adr.reloc() == relocInfo::opt_virtual_call_type || | |
4589 adr.reloc() == relocInfo::static_call_type || | |
4590 adr.reloc() == relocInfo::static_stub_type ) { | |
4591 // This should be rip relative within the code cache and easily | |
4592 // reachable until we get huge code caches. (At which point | |
4593 // ic code is going to have issues). | |
4594 return true; | |
4595 } | |
4596 if (adr.reloc() != relocInfo::external_word_type && | |
4597 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special | |
4598 adr.reloc() != relocInfo::poll_type && // relocs to identify them | |
4599 adr.reloc() != relocInfo::runtime_call_type ) { | |
4600 return false; | |
4601 } | |
4602 | |
4603 // Stress the correction code | |
4604 if (ForceUnreachable) { | |
4605 // Must be runtimecall reloc, see if it is in the codecache | |
4606 // Flipping stuff in the codecache to be unreachable causes issues | |
4607 // with things like inline caches where the additional instructions | |
4608 // are not handled. | |
4609 if (CodeCache::find_blob(adr._target) == NULL) { | |
4610 return false; | |
4611 } | |
4612 } | |
4613 // For external_word_type/runtime_call_type if it is reachable from where we | |
4614 // are now (possibly a temp buffer) and where we might end up | |
4615 // anywhere in the codeCache then we are always reachable. | |
4616 // This would have to change if we ever save/restore shared code | |
4617 // to be more pessimistic. | |
4618 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); | |
4619 if (!is_simm32(disp)) return false; | |
4620 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); | |
4621 if (!is_simm32(disp)) return false; | |
4622 | |
7198
6ab62ad83507
8003195: AbstractAssembler should not store code pointers but use the CodeSection directly
twisti
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6894
diff
changeset
|
4623 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int)); |
304 | 4624 |
4625 // Because rip relative is a disp + address_of_next_instruction and we | |
4626 // don't know the value of address_of_next_instruction we apply a fudge factor | |
4627 // to make sure we will be ok no matter the size of the instruction we get placed into. | |
4628 // We don't have to fudge the checks above here because they are already worst case. | |
4629 | |
4630 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal | |
4631 // + 4 because better safe than sorry. | |
4632 const int fudge = 12 + 4; | |
4633 if (disp < 0) { | |
4634 disp -= fudge; | |
4635 } else { | |
4636 disp += fudge; | |
4637 } | |
4638 return is_simm32(disp); | |
4639 } | |
4640 | |
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2357
diff
changeset
|
4641 // Check if the polling page is not reachable from the code cache using rip-relative |
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
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2357
diff
changeset
|
4642 // addressing. |
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
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2357
diff
changeset
|
4643 bool Assembler::is_polling_page_far() { |
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2357
diff
changeset
|
4644 intptr_t addr = (intptr_t)os::get_polling_page(); |
4118
59bc0d4d9ea3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
3938
diff
changeset
|
4645 return ForceUnreachable || |
59bc0d4d9ea3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
3938
diff
changeset
|
4646 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) || |
2404
b40d4fa697bf
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iveresov
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2357
diff
changeset
|
4647 !is_simm32(addr - (intptr_t)CodeCache::high_bound()); |
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6964776: c2 should ensure the polling page is reachable on 64 bit
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|
4648 } |
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|
4649 |
304 | 4650 void Assembler::emit_data64(jlong data, |
4651 relocInfo::relocType rtype, | |
4652 int format) { | |
4653 if (rtype == relocInfo::none) { | |
7198
6ab62ad83507
8003195: AbstractAssembler should not store code pointers but use the CodeSection directly
twisti
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6894
diff
changeset
|
4654 emit_int64(data); |
304 | 4655 } else { |
4656 emit_data64(data, Relocation::spec_simple(rtype), format); | |
4657 } | |
4658 } | |
4659 | |
4660 void Assembler::emit_data64(jlong data, | |
4661 RelocationHolder const& rspec, | |
4662 int format) { | |
4663 assert(imm_operand == 0, "default format must be immediate in this file"); | |
4664 assert(imm_operand == format, "must be immediate"); | |
4665 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
4666 // Do not use AbstractAssembler::relocate, which is not intended for | |
4667 // embedded words. Instead, relocate to the enclosing instruction. | |
4668 code_section()->relocate(inst_mark(), rspec, format); | |
4669 #ifdef ASSERT | |
4670 check_relocation(rspec, format); | |
4671 #endif | |
7198
6ab62ad83507
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twisti
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diff
changeset
|
4672 emit_int64(data); |
304 | 4673 } |
4674 | |
4675 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { | |
4676 if (reg_enc >= 8) { | |
4677 prefix(REX_B); | |
4678 reg_enc -= 8; | |
4679 } else if (byteinst && reg_enc >= 4) { | |
4680 prefix(REX); | |
4681 } | |
4682 return reg_enc; | |
4683 } | |
4684 | |
4685 int Assembler::prefixq_and_encode(int reg_enc) { | |
4686 if (reg_enc < 8) { | |
4687 prefix(REX_W); | |
4688 } else { | |
4689 prefix(REX_WB); | |
4690 reg_enc -= 8; | |
4691 } | |
4692 return reg_enc; | |
4693 } | |
4694 | |
16064
03eda0a202e9
Better fix for prefix byte for AMD64 byte instructions
Christian Wimmer <christian.wimmer@oracle.com>
parents:
16047
diff
changeset
|
4695 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) { |
304 | 4696 if (dst_enc < 8) { |
4697 if (src_enc >= 8) { | |
4698 prefix(REX_B); | |
4699 src_enc -= 8; | |
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03eda0a202e9
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Christian Wimmer <christian.wimmer@oracle.com>
parents:
16047
diff
changeset
|
4700 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) { |
304 | 4701 prefix(REX); |
4702 } | |
4703 } else { | |
4704 if (src_enc < 8) { | |
4705 prefix(REX_R); | |
4706 } else { | |
4707 prefix(REX_RB); | |
4708 src_enc -= 8; | |
4709 } | |
4710 dst_enc -= 8; | |
4711 } | |
4712 return dst_enc << 3 | src_enc; | |
4713 } | |
4714 | |
4715 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { | |
4716 if (dst_enc < 8) { | |
4717 if (src_enc < 8) { | |
4718 prefix(REX_W); | |
4719 } else { | |
4720 prefix(REX_WB); | |
4721 src_enc -= 8; | |
4722 } | |
4723 } else { | |
4724 if (src_enc < 8) { | |
4725 prefix(REX_WR); | |
4726 } else { | |
4727 prefix(REX_WRB); | |
4728 src_enc -= 8; | |
4729 } | |
4730 dst_enc -= 8; | |
4731 } | |
4732 return dst_enc << 3 | src_enc; | |
4733 } | |
4734 | |
4735 void Assembler::prefix(Register reg) { | |
4736 if (reg->encoding() >= 8) { | |
4737 prefix(REX_B); | |
4738 } | |
4739 } | |
4740 | |
4741 void Assembler::prefix(Address adr) { | |
4742 if (adr.base_needs_rex()) { | |
4743 if (adr.index_needs_rex()) { | |
4744 prefix(REX_XB); | |
4745 } else { | |
4746 prefix(REX_B); | |
4747 } | |
4748 } else { | |
4749 if (adr.index_needs_rex()) { | |
4750 prefix(REX_X); | |
4751 } | |
4752 } | |
4753 } | |
4754 | |
4755 void Assembler::prefixq(Address adr) { | |
4756 if (adr.base_needs_rex()) { | |
4757 if (adr.index_needs_rex()) { | |
4758 prefix(REX_WXB); | |
4759 } else { | |
4760 prefix(REX_WB); | |
4761 } | |
4762 } else { | |
4763 if (adr.index_needs_rex()) { | |
4764 prefix(REX_WX); | |
4765 } else { | |
4766 prefix(REX_W); | |
4767 } | |
4768 } | |
4769 } | |
4770 | |
4771 | |
4772 void Assembler::prefix(Address adr, Register reg, bool byteinst) { | |
4773 if (reg->encoding() < 8) { | |
4774 if (adr.base_needs_rex()) { | |
4775 if (adr.index_needs_rex()) { | |
4776 prefix(REX_XB); | |
4777 } else { | |
4778 prefix(REX_B); | |
4779 } | |
4780 } else { | |
4781 if (adr.index_needs_rex()) { | |
4782 prefix(REX_X); | |
3855 | 4783 } else if (byteinst && reg->encoding() >= 4 ) { |
304 | 4784 prefix(REX); |
4785 } | |
4786 } | |
4787 } else { | |
4788 if (adr.base_needs_rex()) { | |
4789 if (adr.index_needs_rex()) { | |
4790 prefix(REX_RXB); | |
4791 } else { | |
4792 prefix(REX_RB); | |
4793 } | |
4794 } else { | |
4795 if (adr.index_needs_rex()) { | |
4796 prefix(REX_RX); | |
4797 } else { | |
4798 prefix(REX_R); | |
4799 } | |
4800 } | |
4801 } | |
4802 } | |
4803 | |
4804 void Assembler::prefixq(Address adr, Register src) { | |
4805 if (src->encoding() < 8) { | |
4806 if (adr.base_needs_rex()) { | |
4807 if (adr.index_needs_rex()) { | |
4808 prefix(REX_WXB); | |
4809 } else { | |
4810 prefix(REX_WB); | |
4811 } | |
4812 } else { | |
4813 if (adr.index_needs_rex()) { | |
4814 prefix(REX_WX); | |
4815 } else { | |
4816 prefix(REX_W); | |
4817 } | |
4818 } | |
4819 } else { | |
4820 if (adr.base_needs_rex()) { | |
4821 if (adr.index_needs_rex()) { | |
4822 prefix(REX_WRXB); | |
4823 } else { | |
4824 prefix(REX_WRB); | |
4825 } | |
4826 } else { | |
4827 if (adr.index_needs_rex()) { | |
4828 prefix(REX_WRX); | |
4829 } else { | |
4830 prefix(REX_WR); | |
4831 } | |
4832 } | |
4833 } | |
4834 } | |
4835 | |
4836 void Assembler::prefix(Address adr, XMMRegister reg) { | |
4837 if (reg->encoding() < 8) { | |
4838 if (adr.base_needs_rex()) { | |
4839 if (adr.index_needs_rex()) { | |
4840 prefix(REX_XB); | |
4841 } else { | |
4842 prefix(REX_B); | |
4843 } | |
4844 } else { | |
4845 if (adr.index_needs_rex()) { | |
4846 prefix(REX_X); | |
4847 } | |
4848 } | |
4849 } else { | |
4850 if (adr.base_needs_rex()) { | |
4851 if (adr.index_needs_rex()) { | |
4852 prefix(REX_RXB); | |
4853 } else { | |
4854 prefix(REX_RB); | |
4855 } | |
4856 } else { | |
4857 if (adr.index_needs_rex()) { | |
4858 prefix(REX_RX); | |
4859 } else { | |
4860 prefix(REX_R); | |
4861 } | |
4862 } | |
4863 } | |
4864 } | |
4865 | |
4759 | 4866 void Assembler::prefixq(Address adr, XMMRegister src) { |
4867 if (src->encoding() < 8) { | |
4868 if (adr.base_needs_rex()) { | |
4869 if (adr.index_needs_rex()) { | |
4870 prefix(REX_WXB); | |
4871 } else { | |
4872 prefix(REX_WB); | |
4873 } | |
4874 } else { | |
4875 if (adr.index_needs_rex()) { | |
4876 prefix(REX_WX); | |
4877 } else { | |
4878 prefix(REX_W); | |
4879 } | |
4880 } | |
4881 } else { | |
4882 if (adr.base_needs_rex()) { | |
4883 if (adr.index_needs_rex()) { | |
4884 prefix(REX_WRXB); | |
4885 } else { | |
4886 prefix(REX_WRB); | |
4887 } | |
4888 } else { | |
4889 if (adr.index_needs_rex()) { | |
4890 prefix(REX_WRX); | |
4891 } else { | |
4892 prefix(REX_WR); | |
4893 } | |
4894 } | |
4895 } | |
4896 } | |
4897 | |
304 | 4898 void Assembler::adcq(Register dst, int32_t imm32) { |
4899 (void) prefixq_and_encode(dst->encoding()); | |
4900 emit_arith(0x81, 0xD0, dst, imm32); | |
4901 } | |
4902 | |
4903 void Assembler::adcq(Register dst, Address src) { | |
4904 InstructionMark im(this); | |
4905 prefixq(src, dst); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
4906 emit_int8(0x13); |
304 | 4907 emit_operand(dst, src); |
4908 } | |
4909 | |
4910 void Assembler::adcq(Register dst, Register src) { | |
12329 | 4911 (void) prefixq_and_encode(dst->encoding(), src->encoding()); |
304 | 4912 emit_arith(0x13, 0xC0, dst, src); |
4913 } | |
4914 | |
4915 void Assembler::addq(Address dst, int32_t imm32) { | |
4916 InstructionMark im(this); | |
4917 prefixq(dst); | |
4918 emit_arith_operand(0x81, rax, dst,imm32); | |
4919 } | |
4920 | |
4921 void Assembler::addq(Address dst, Register src) { | |
4922 InstructionMark im(this); | |
4923 prefixq(dst, src); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4924 emit_int8(0x01); |
304 | 4925 emit_operand(src, dst); |
4926 } | |
4927 | |
4928 void Assembler::addq(Register dst, int32_t imm32) { | |
4929 (void) prefixq_and_encode(dst->encoding()); | |
4930 emit_arith(0x81, 0xC0, dst, imm32); | |
4931 } | |
4932 | |
4933 void Assembler::addq(Register dst, Address src) { | |
4934 InstructionMark im(this); | |
4935 prefixq(src, dst); | |
7430
d02120b7a34f
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twisti
parents:
7427
diff
changeset
|
4936 emit_int8(0x03); |
304 | 4937 emit_operand(dst, src); |
4938 } | |
4939 | |
4940 void Assembler::addq(Register dst, Register src) { | |
4941 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4942 emit_arith(0x03, 0xC0, dst, src); | |
4943 } | |
4944 | |
3457 | 4945 void Assembler::andq(Address dst, int32_t imm32) { |
4946 InstructionMark im(this); | |
4947 prefixq(dst); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4948 emit_int8((unsigned char)0x81); |
3457 | 4949 emit_operand(rsp, dst, 4); |
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
twisti
parents:
7475
diff
changeset
|
4950 emit_int32(imm32); |
3457 | 4951 } |
4952 | |
304 | 4953 void Assembler::andq(Register dst, int32_t imm32) { |
4954 (void) prefixq_and_encode(dst->encoding()); | |
4955 emit_arith(0x81, 0xE0, dst, imm32); | |
4956 } | |
4957 | |
4958 void Assembler::andq(Register dst, Address src) { | |
4959 InstructionMark im(this); | |
4960 prefixq(src, dst); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
4961 emit_int8(0x23); |
304 | 4962 emit_operand(dst, src); |
4963 } | |
4964 | |
4965 void Assembler::andq(Register dst, Register src) { | |
12329 | 4966 (void) prefixq_and_encode(dst->encoding(), src->encoding()); |
304 | 4967 emit_arith(0x23, 0xC0, dst, src); |
4968 } | |
4969 | |
14693
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
4970 void Assembler::andnq(Register dst, Register src1, Register src2) { |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
4971 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
4972 int encode = vex_prefix_0F38_and_encode_q(dst, src1, src2); |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
4973 emit_int8((unsigned char)0xF2); |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
4974 emit_int8((unsigned char)(0xC0 | encode)); |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
4975 } |
9e9af3aa4278
8031321: Support Intel bit manipulation instructions
iveresov
parents:
12972
diff
changeset
|
4976 |
9e9af3aa4278
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|
4977 void Assembler::andnq(Register dst, Register src1, Address src2) { |
9e9af3aa4278
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diff
changeset
|
4978 InstructionMark im(this); |
9e9af3aa4278
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diff
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|
4979 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); |
9e9af3aa4278
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diff
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|
4980 vex_prefix_0F38_q(dst, src1, src2); |
9e9af3aa4278
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diff
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|
4981 emit_int8((unsigned char)0xF2); |
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diff
changeset
|
4982 emit_operand(dst, src2); |
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|
4983 } |
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|
4984 |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
|
4985 void Assembler::bsfq(Register dst, Register src) { |
93c14e5562c4
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diff
changeset
|
4986 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
7430
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|
4987 emit_int8(0x0F); |
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|
4988 emit_int8((unsigned char)0xBC); |
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changeset
|
4989 emit_int8((unsigned char)(0xC0 | encode)); |
775
93c14e5562c4
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diff
changeset
|
4990 } |
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diff
changeset
|
4991 |
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diff
changeset
|
4992 void Assembler::bsrq(Register dst, Register src) { |
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|
4993 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
7430
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|
4994 emit_int8(0x0F); |
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|
4995 emit_int8((unsigned char)0xBD); |
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|
4996 emit_int8((unsigned char)(0xC0 | encode)); |
775
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diff
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|
4997 } |
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diff
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|
4998 |
304 | 4999 void Assembler::bswapq(Register reg) { |
5000 int encode = prefixq_and_encode(reg->encoding()); | |
7430
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|
5001 emit_int8(0x0F); |
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|
5002 emit_int8((unsigned char)(0xC8 | encode)); |
304 | 5003 } |
5004 | |
14693
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|
5005 void Assembler::blsiq(Register dst, Register src) { |
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|
5006 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); |
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|
5007 int encode = vex_prefix_0F38_and_encode_q(rbx, dst, src); |
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|
5008 emit_int8((unsigned char)0xF3); |
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changeset
|
5009 emit_int8((unsigned char)(0xC0 | encode)); |
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diff
changeset
|
5010 } |
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changeset
|
5011 |
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diff
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|
5012 void Assembler::blsiq(Register dst, Address src) { |
9e9af3aa4278
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changeset
|
5013 InstructionMark im(this); |
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diff
changeset
|
5014 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); |
9e9af3aa4278
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diff
changeset
|
5015 vex_prefix_0F38_q(rbx, dst, src); |
9e9af3aa4278
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diff
changeset
|
5016 emit_int8((unsigned char)0xF3); |
9e9af3aa4278
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diff
changeset
|
5017 emit_operand(rbx, src); |
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diff
changeset
|
5018 } |
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diff
changeset
|
5019 |
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diff
changeset
|
5020 void Assembler::blsmskq(Register dst, Register src) { |
9e9af3aa4278
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diff
changeset
|
5021 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); |
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|
5022 int encode = vex_prefix_0F38_and_encode_q(rdx, dst, src); |
9e9af3aa4278
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changeset
|
5023 emit_int8((unsigned char)0xF3); |
9e9af3aa4278
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diff
changeset
|
5024 emit_int8((unsigned char)(0xC0 | encode)); |
9e9af3aa4278
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diff
changeset
|
5025 } |
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changeset
|
5026 |
9e9af3aa4278
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diff
changeset
|
5027 void Assembler::blsmskq(Register dst, Address src) { |
9e9af3aa4278
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diff
changeset
|
5028 InstructionMark im(this); |
9e9af3aa4278
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diff
changeset
|
5029 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); |
9e9af3aa4278
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diff
changeset
|
5030 vex_prefix_0F38_q(rdx, dst, src); |
9e9af3aa4278
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diff
changeset
|
5031 emit_int8((unsigned char)0xF3); |
9e9af3aa4278
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diff
changeset
|
5032 emit_operand(rdx, src); |
9e9af3aa4278
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diff
changeset
|
5033 } |
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diff
changeset
|
5034 |
9e9af3aa4278
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diff
changeset
|
5035 void Assembler::blsrq(Register dst, Register src) { |
9e9af3aa4278
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changeset
|
5036 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); |
9e9af3aa4278
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changeset
|
5037 int encode = vex_prefix_0F38_and_encode_q(rcx, dst, src); |
9e9af3aa4278
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diff
changeset
|
5038 emit_int8((unsigned char)0xF3); |
9e9af3aa4278
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diff
changeset
|
5039 emit_int8((unsigned char)(0xC0 | encode)); |
9e9af3aa4278
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diff
changeset
|
5040 } |
9e9af3aa4278
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diff
changeset
|
5041 |
9e9af3aa4278
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diff
changeset
|
5042 void Assembler::blsrq(Register dst, Address src) { |
9e9af3aa4278
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diff
changeset
|
5043 InstructionMark im(this); |
9e9af3aa4278
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diff
changeset
|
5044 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); |
9e9af3aa4278
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diff
changeset
|
5045 vex_prefix_0F38_q(rcx, dst, src); |
9e9af3aa4278
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diff
changeset
|
5046 emit_int8((unsigned char)0xF3); |
9e9af3aa4278
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diff
changeset
|
5047 emit_operand(rcx, src); |
9e9af3aa4278
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diff
changeset
|
5048 } |
9e9af3aa4278
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diff
changeset
|
5049 |
304 | 5050 void Assembler::cdqq() { |
5051 prefix(REX_W); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5052 emit_int8((unsigned char)0x99); |
304 | 5053 } |
5054 | |
5055 void Assembler::clflush(Address adr) { | |
5056 prefix(adr); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
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diff
changeset
|
5057 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
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diff
changeset
|
5058 emit_int8((unsigned char)0xAE); |
304 | 5059 emit_operand(rdi, adr); |
5060 } | |
5061 | |
5062 void Assembler::cmovq(Condition cc, Register dst, Register src) { | |
5063 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5064 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5065 emit_int8(0x40 | cc); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5066 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5067 } |
5068 | |
5069 void Assembler::cmovq(Condition cc, Register dst, Address src) { | |
5070 InstructionMark im(this); | |
5071 prefixq(src, dst); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5072 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
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diff
changeset
|
5073 emit_int8(0x40 | cc); |
304 | 5074 emit_operand(dst, src); |
5075 } | |
5076 | |
5077 void Assembler::cmpq(Address dst, int32_t imm32) { | |
5078 InstructionMark im(this); | |
5079 prefixq(dst); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5080 emit_int8((unsigned char)0x81); |
304 | 5081 emit_operand(rdi, dst, 4); |
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
twisti
parents:
7475
diff
changeset
|
5082 emit_int32(imm32); |
304 | 5083 } |
5084 | |
5085 void Assembler::cmpq(Register dst, int32_t imm32) { | |
5086 (void) prefixq_and_encode(dst->encoding()); | |
5087 emit_arith(0x81, 0xF8, dst, imm32); | |
5088 } | |
5089 | |
5090 void Assembler::cmpq(Address dst, Register src) { | |
5091 InstructionMark im(this); | |
5092 prefixq(dst, src); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5093 emit_int8(0x3B); |
304 | 5094 emit_operand(src, dst); |
5095 } | |
5096 | |
5097 void Assembler::cmpq(Register dst, Register src) { | |
5098 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5099 emit_arith(0x3B, 0xC0, dst, src); | |
5100 } | |
5101 | |
5102 void Assembler::cmpq(Register dst, Address src) { | |
5103 InstructionMark im(this); | |
5104 prefixq(src, dst); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
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diff
changeset
|
5105 emit_int8(0x3B); |
304 | 5106 emit_operand(dst, src); |
5107 } | |
5108 | |
5109 void Assembler::cmpxchgq(Register reg, Address adr) { | |
5110 InstructionMark im(this); | |
5111 prefixq(adr, reg); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
5112 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5113 emit_int8((unsigned char)0xB1); |
304 | 5114 emit_operand(reg, adr); |
5115 } | |
5116 | |
5117 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | |
5118 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 5119 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2); |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
5120 emit_int8(0x2A); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5121 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5122 } |
5123 | |
4759 | 5124 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { |
5125 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
5126 InstructionMark im(this); | |
5127 simd_prefix_q(dst, dst, src, VEX_SIMD_F2); | |
7430
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diff
changeset
|
5128 emit_int8(0x2A); |
4759 | 5129 emit_operand(dst, src); |
5130 } | |
5131 | |
304 | 5132 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { |
5133 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4759 | 5134 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3); |
7430
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diff
changeset
|
5135 emit_int8(0x2A); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5136 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5137 } |
5138 | |
4759 | 5139 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { |
5140 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
5141 InstructionMark im(this); | |
5142 simd_prefix_q(dst, dst, src, VEX_SIMD_F3); | |
7430
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diff
changeset
|
5143 emit_int8(0x2A); |
4759 | 5144 emit_operand(dst, src); |
5145 } | |
5146 | |
304 | 5147 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { |
5148 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 5149 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2); |
7430
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7427
diff
changeset
|
5150 emit_int8(0x2C); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5151 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5152 } |
5153 | |
5154 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | |
5155 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4759 | 5156 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3); |
7430
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diff
changeset
|
5157 emit_int8(0x2C); |
d02120b7a34f
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diff
changeset
|
5158 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5159 } |
5160 | |
5161 void Assembler::decl(Register dst) { | |
5162 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
5163 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) | |
5164 int encode = prefix_and_encode(dst->encoding()); | |
7430
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diff
changeset
|
5165 emit_int8((unsigned char)0xFF); |
d02120b7a34f
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twisti
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diff
changeset
|
5166 emit_int8((unsigned char)(0xC8 | encode)); |
304 | 5167 } |
5168 | |
5169 void Assembler::decq(Register dst) { | |
5170 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
5171 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
5172 int encode = prefixq_and_encode(dst->encoding()); | |
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changeset
|
5173 emit_int8((unsigned char)0xFF); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
5174 emit_int8(0xC8 | encode); |
304 | 5175 } |
5176 | |
5177 void Assembler::decq(Address dst) { | |
5178 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
5179 InstructionMark im(this); | |
5180 prefixq(dst); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5181 emit_int8((unsigned char)0xFF); |
304 | 5182 emit_operand(rcx, dst); |
5183 } | |
5184 | |
5185 void Assembler::fxrstor(Address src) { | |
5186 prefixq(src); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5187 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5188 emit_int8((unsigned char)0xAE); |
304 | 5189 emit_operand(as_Register(1), src); |
5190 } | |
5191 | |
5192 void Assembler::fxsave(Address dst) { | |
5193 prefixq(dst); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5194 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5195 emit_int8((unsigned char)0xAE); |
304 | 5196 emit_operand(as_Register(0), dst); |
5197 } | |
5198 | |
5199 void Assembler::idivq(Register src) { | |
5200 int encode = prefixq_and_encode(src->encoding()); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5201 emit_int8((unsigned char)0xF7); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
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diff
changeset
|
5202 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 5203 } |
5204 | |
5205 void Assembler::imulq(Register dst, Register src) { | |
5206 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5207 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5208 emit_int8((unsigned char)0xAF); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5209 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5210 } |
5211 | |
5212 void Assembler::imulq(Register dst, Register src, int value) { | |
5213 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
5214 if (is8bit(value)) { | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5215 emit_int8(0x6B); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
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diff
changeset
|
5216 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5217 emit_int8(value & 0xFF); |
304 | 5218 } else { |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5219 emit_int8(0x69); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5220 emit_int8((unsigned char)(0xC0 | encode)); |
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
twisti
parents:
7475
diff
changeset
|
5221 emit_int32(value); |
304 | 5222 } |
5223 } | |
5224 | |
12972
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
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12329
diff
changeset
|
5225 void Assembler::imulq(Register dst, Address src) { |
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12329
diff
changeset
|
5226 InstructionMark im(this); |
59e8ad757e19
8026844: Various Math functions needs intrinsification
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12329
diff
changeset
|
5227 prefixq(src, dst); |
59e8ad757e19
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12329
diff
changeset
|
5228 emit_int8(0x0F); |
59e8ad757e19
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parents:
12329
diff
changeset
|
5229 emit_int8((unsigned char) 0xAF); |
59e8ad757e19
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rbackman
parents:
12329
diff
changeset
|
5230 emit_operand(dst, src); |
59e8ad757e19
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12329
diff
changeset
|
5231 } |
59e8ad757e19
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diff
changeset
|
5232 |
304 | 5233 void Assembler::incl(Register dst) { |
5234 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
5235 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
5236 int encode = prefix_and_encode(dst->encoding()); | |
7430
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diff
changeset
|
5237 emit_int8((unsigned char)0xFF); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5238 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5239 } |
5240 | |
5241 void Assembler::incq(Register dst) { | |
5242 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
5243 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
5244 int encode = prefixq_and_encode(dst->encoding()); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5245 emit_int8((unsigned char)0xFF); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5246 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5247 } |
5248 | |
5249 void Assembler::incq(Address dst) { | |
5250 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
5251 InstructionMark im(this); | |
5252 prefixq(dst); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5253 emit_int8((unsigned char)0xFF); |
304 | 5254 emit_operand(rax, dst); |
5255 } | |
5256 | |
5257 void Assembler::lea(Register dst, Address src) { | |
5258 leaq(dst, src); | |
5259 } | |
5260 | |
5261 void Assembler::leaq(Register dst, Address src) { | |
5262 InstructionMark im(this); | |
5263 prefixq(src, dst); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
5264 emit_int8((unsigned char)0x8D); |
304 | 5265 emit_operand(dst, src); |
5266 } | |
5267 | |
5268 void Assembler::mov64(Register dst, int64_t imm64) { | |
5269 InstructionMark im(this); | |
5270 int encode = prefixq_and_encode(dst->encoding()); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
5271 emit_int8((unsigned char)(0xB8 | encode)); |
7198
6ab62ad83507
8003195: AbstractAssembler should not store code pointers but use the CodeSection directly
twisti
parents:
6894
diff
changeset
|
5272 emit_int64(imm64); |
304 | 5273 } |
5274 | |
5275 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { | |
5276 InstructionMark im(this); | |
5277 int encode = prefixq_and_encode(dst->encoding()); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5278 emit_int8(0xB8 | encode); |
304 | 5279 emit_data64(imm64, rspec); |
5280 } | |
5281 | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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diff
changeset
|
5282 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5283 InstructionMark im(this); |
660978a2a31a
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624
diff
changeset
|
5284 int encode = prefix_and_encode(dst->encoding()); |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
5285 emit_int8((unsigned char)(0xB8 | encode)); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5286 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
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parents:
624
diff
changeset
|
5287 } |
660978a2a31a
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624
diff
changeset
|
5288 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5289 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5290 InstructionMark im(this); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5291 prefix(dst); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5292 emit_int8((unsigned char)0xC7); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5293 emit_operand(rax, dst, 4); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5294 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5295 } |
660978a2a31a
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parents:
624
diff
changeset
|
5296 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5297 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5298 InstructionMark im(this); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5299 int encode = prefix_and_encode(src1->encoding()); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5300 emit_int8((unsigned char)0x81); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5301 emit_int8((unsigned char)(0xF8 | encode)); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5302 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5303 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5304 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5305 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5306 InstructionMark im(this); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5307 prefix(src1); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5308 emit_int8((unsigned char)0x81); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5309 emit_operand(rax, src1, 4); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5310 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5311 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5312 |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
5313 void Assembler::lzcntq(Register dst, Register src) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
5314 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5315 emit_int8((unsigned char)0xF3); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
5316 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5317 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5318 emit_int8((unsigned char)0xBD); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5319 emit_int8((unsigned char)(0xC0 | encode)); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
5320 } |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
5321 |
304 | 5322 void Assembler::movdq(XMMRegister dst, Register src) { |
5323 // table D-1 says MMX/SSE2 | |
4759 | 5324 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
5325 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5326 emit_int8(0x6E); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5327 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5328 } |
5329 | |
5330 void Assembler::movdq(Register dst, XMMRegister src) { | |
5331 // table D-1 says MMX/SSE2 | |
4759 | 5332 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
304 | 5333 // swap src/dst to get correct prefix |
4759 | 5334 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5335 emit_int8(0x7E); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5336 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5337 } |
5338 | |
5339 void Assembler::movq(Register dst, Register src) { | |
5340 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
5341 emit_int8((unsigned char)0x8B); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5342 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5343 } |
5344 | |
5345 void Assembler::movq(Register dst, Address src) { | |
5346 InstructionMark im(this); | |
5347 prefixq(src, dst); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5348 emit_int8((unsigned char)0x8B); |
304 | 5349 emit_operand(dst, src); |
5350 } | |
5351 | |
5352 void Assembler::movq(Address dst, Register src) { | |
5353 InstructionMark im(this); | |
5354 prefixq(dst, src); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5355 emit_int8((unsigned char)0x89); |
304 | 5356 emit_operand(src, dst); |
5357 } | |
5358 | |
624 | 5359 void Assembler::movsbq(Register dst, Address src) { |
5360 InstructionMark im(this); | |
5361 prefixq(src, dst); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5362 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5363 emit_int8((unsigned char)0xBE); |
624 | 5364 emit_operand(dst, src); |
5365 } | |
5366 | |
5367 void Assembler::movsbq(Register dst, Register src) { | |
5368 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5369 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5370 emit_int8((unsigned char)0xBE); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
5371 emit_int8((unsigned char)(0xC0 | encode)); |
624 | 5372 } |
5373 | |
304 | 5374 void Assembler::movslq(Register dst, int32_t imm32) { |
5375 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) | |
5376 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) | |
5377 // as a result we shouldn't use until tested at runtime... | |
5378 ShouldNotReachHere(); | |
5379 InstructionMark im(this); | |
5380 int encode = prefixq_and_encode(dst->encoding()); | |
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5381 emit_int8((unsigned char)(0xC7 | encode)); |
7476
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|
5382 emit_int32(imm32); |
304 | 5383 } |
5384 | |
5385 void Assembler::movslq(Address dst, int32_t imm32) { | |
5386 assert(is_simm32(imm32), "lost bits"); | |
5387 InstructionMark im(this); | |
5388 prefixq(dst); | |
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|
5389 emit_int8((unsigned char)0xC7); |
304 | 5390 emit_operand(rax, dst, 4); |
7476
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5391 emit_int32(imm32); |
304 | 5392 } |
5393 | |
5394 void Assembler::movslq(Register dst, Address src) { | |
5395 InstructionMark im(this); | |
5396 prefixq(src, dst); | |
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|
5397 emit_int8(0x63); |
304 | 5398 emit_operand(dst, src); |
5399 } | |
5400 | |
5401 void Assembler::movslq(Register dst, Register src) { | |
5402 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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|
5403 emit_int8(0x63); |
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|
5404 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5405 } |
5406 | |
624 | 5407 void Assembler::movswq(Register dst, Address src) { |
5408 InstructionMark im(this); | |
5409 prefixq(src, dst); | |
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|
5410 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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|
5411 emit_int8((unsigned char)0xBF); |
624 | 5412 emit_operand(dst, src); |
5413 } | |
5414 | |
5415 void Assembler::movswq(Register dst, Register src) { | |
5416 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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|
5417 emit_int8((unsigned char)0x0F); |
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|
5418 emit_int8((unsigned char)0xBF); |
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|
5419 emit_int8((unsigned char)(0xC0 | encode)); |
624 | 5420 } |
5421 | |
5422 void Assembler::movzbq(Register dst, Address src) { | |
5423 InstructionMark im(this); | |
5424 prefixq(src, dst); | |
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|
5425 emit_int8((unsigned char)0x0F); |
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changeset
|
5426 emit_int8((unsigned char)0xB6); |
624 | 5427 emit_operand(dst, src); |
5428 } | |
5429 | |
5430 void Assembler::movzbq(Register dst, Register src) { | |
5431 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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|
5432 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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|
5433 emit_int8((unsigned char)0xB6); |
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changeset
|
5434 emit_int8(0xC0 | encode); |
624 | 5435 } |
5436 | |
5437 void Assembler::movzwq(Register dst, Address src) { | |
5438 InstructionMark im(this); | |
5439 prefixq(src, dst); | |
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|
5440 emit_int8((unsigned char)0x0F); |
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|
5441 emit_int8((unsigned char)0xB7); |
624 | 5442 emit_operand(dst, src); |
5443 } | |
5444 | |
5445 void Assembler::movzwq(Register dst, Register src) { | |
5446 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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|
5447 emit_int8((unsigned char)0x0F); |
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|
5448 emit_int8((unsigned char)0xB7); |
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changeset
|
5449 emit_int8((unsigned char)(0xC0 | encode)); |
624 | 5450 } |
5451 | |
304 | 5452 void Assembler::negq(Register dst) { |
5453 int encode = prefixq_and_encode(dst->encoding()); | |
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changeset
|
5454 emit_int8((unsigned char)0xF7); |
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changeset
|
5455 emit_int8((unsigned char)(0xD8 | encode)); |
304 | 5456 } |
5457 | |
5458 void Assembler::notq(Register dst) { | |
5459 int encode = prefixq_and_encode(dst->encoding()); | |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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|
5460 emit_int8((unsigned char)0xF7); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
5461 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 5462 } |
5463 | |
5464 void Assembler::orq(Address dst, int32_t imm32) { | |
5465 InstructionMark im(this); | |
5466 prefixq(dst); | |
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|
5467 emit_int8((unsigned char)0x81); |
304 | 5468 emit_operand(rcx, dst, 4); |
7476
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changeset
|
5469 emit_int32(imm32); |
304 | 5470 } |
5471 | |
5472 void Assembler::orq(Register dst, int32_t imm32) { | |
5473 (void) prefixq_and_encode(dst->encoding()); | |
5474 emit_arith(0x81, 0xC8, dst, imm32); | |
5475 } | |
5476 | |
5477 void Assembler::orq(Register dst, Address src) { | |
5478 InstructionMark im(this); | |
5479 prefixq(src, dst); | |
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changeset
|
5480 emit_int8(0x0B); |
304 | 5481 emit_operand(dst, src); |
5482 } | |
5483 | |
5484 void Assembler::orq(Register dst, Register src) { | |
5485 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5486 emit_arith(0x0B, 0xC0, dst, src); | |
5487 } | |
5488 | |
5489 void Assembler::popa() { // 64bit | |
5490 movq(r15, Address(rsp, 0)); | |
5491 movq(r14, Address(rsp, wordSize)); | |
5492 movq(r13, Address(rsp, 2 * wordSize)); | |
5493 movq(r12, Address(rsp, 3 * wordSize)); | |
5494 movq(r11, Address(rsp, 4 * wordSize)); | |
5495 movq(r10, Address(rsp, 5 * wordSize)); | |
5496 movq(r9, Address(rsp, 6 * wordSize)); | |
5497 movq(r8, Address(rsp, 7 * wordSize)); | |
5498 movq(rdi, Address(rsp, 8 * wordSize)); | |
5499 movq(rsi, Address(rsp, 9 * wordSize)); | |
5500 movq(rbp, Address(rsp, 10 * wordSize)); | |
5501 // skip rsp | |
5502 movq(rbx, Address(rsp, 12 * wordSize)); | |
5503 movq(rdx, Address(rsp, 13 * wordSize)); | |
5504 movq(rcx, Address(rsp, 14 * wordSize)); | |
5505 movq(rax, Address(rsp, 15 * wordSize)); | |
5506 | |
5507 addq(rsp, 16 * wordSize); | |
5508 } | |
5509 | |
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changeset
|
5510 void Assembler::popcntq(Register dst, Address src) { |
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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changeset
|
5511 assert(VM_Version::supports_popcnt(), "must support"); |
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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changeset
|
5512 InstructionMark im(this); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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|
5513 emit_int8((unsigned char)0xF3); |
643
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changeset
|
5514 prefixq(src, dst); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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|
5515 emit_int8((unsigned char)0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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|
5516 emit_int8((unsigned char)0xB8); |
643
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diff
changeset
|
5517 emit_operand(dst, src); |
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diff
changeset
|
5518 } |
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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diff
changeset
|
5519 |
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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diff
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|
5520 void Assembler::popcntq(Register dst, Register src) { |
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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changeset
|
5521 assert(VM_Version::supports_popcnt(), "must support"); |
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changeset
|
5522 emit_int8((unsigned char)0xF3); |
643
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diff
changeset
|
5523 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
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changeset
|
5524 emit_int8((unsigned char)0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
5525 emit_int8((unsigned char)0xB8); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
5526 emit_int8((unsigned char)(0xC0 | encode)); |
643
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diff
changeset
|
5527 } |
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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diff
changeset
|
5528 |
304 | 5529 void Assembler::popq(Address dst) { |
5530 InstructionMark im(this); | |
5531 prefixq(dst); | |
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diff
changeset
|
5532 emit_int8((unsigned char)0x8F); |
304 | 5533 emit_operand(rax, dst); |
5534 } | |
5535 | |
5536 void Assembler::pusha() { // 64bit | |
5537 // we have to store original rsp. ABI says that 128 bytes | |
5538 // below rsp are local scratch. | |
5539 movq(Address(rsp, -5 * wordSize), rsp); | |
5540 | |
5541 subq(rsp, 16 * wordSize); | |
5542 | |
5543 movq(Address(rsp, 15 * wordSize), rax); | |
5544 movq(Address(rsp, 14 * wordSize), rcx); | |
5545 movq(Address(rsp, 13 * wordSize), rdx); | |
5546 movq(Address(rsp, 12 * wordSize), rbx); | |
5547 // skip rsp | |
5548 movq(Address(rsp, 10 * wordSize), rbp); | |
5549 movq(Address(rsp, 9 * wordSize), rsi); | |
5550 movq(Address(rsp, 8 * wordSize), rdi); | |
5551 movq(Address(rsp, 7 * wordSize), r8); | |
5552 movq(Address(rsp, 6 * wordSize), r9); | |
5553 movq(Address(rsp, 5 * wordSize), r10); | |
5554 movq(Address(rsp, 4 * wordSize), r11); | |
5555 movq(Address(rsp, 3 * wordSize), r12); | |
5556 movq(Address(rsp, 2 * wordSize), r13); | |
5557 movq(Address(rsp, wordSize), r14); | |
5558 movq(Address(rsp, 0), r15); | |
5559 } | |
5560 | |
5561 void Assembler::pushq(Address src) { | |
5562 InstructionMark im(this); | |
5563 prefixq(src); | |
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diff
changeset
|
5564 emit_int8((unsigned char)0xFF); |
304 | 5565 emit_operand(rsi, src); |
5566 } | |
5567 | |
5568 void Assembler::rclq(Register dst, int imm8) { | |
5569 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5570 int encode = prefixq_and_encode(dst->encoding()); | |
5571 if (imm8 == 1) { | |
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|
5572 emit_int8((unsigned char)0xD1); |
d02120b7a34f
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changeset
|
5573 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 5574 } else { |
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changeset
|
5575 emit_int8((unsigned char)0xC1); |
d02120b7a34f
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changeset
|
5576 emit_int8((unsigned char)(0xD0 | encode)); |
d02120b7a34f
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diff
changeset
|
5577 emit_int8(imm8); |
304 | 5578 } |
5579 } | |
5580 void Assembler::sarq(Register dst, int imm8) { | |
5581 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5582 int encode = prefixq_and_encode(dst->encoding()); | |
5583 if (imm8 == 1) { | |
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changeset
|
5584 emit_int8((unsigned char)0xD1); |
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changeset
|
5585 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 5586 } else { |
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changeset
|
5587 emit_int8((unsigned char)0xC1); |
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changeset
|
5588 emit_int8((unsigned char)(0xF8 | encode)); |
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changeset
|
5589 emit_int8(imm8); |
304 | 5590 } |
5591 } | |
5592 | |
5593 void Assembler::sarq(Register dst) { | |
5594 int encode = prefixq_and_encode(dst->encoding()); | |
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changeset
|
5595 emit_int8((unsigned char)0xD3); |
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changeset
|
5596 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 5597 } |
2100
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changeset
|
5598 |
304 | 5599 void Assembler::sbbq(Address dst, int32_t imm32) { |
5600 InstructionMark im(this); | |
5601 prefixq(dst); | |
5602 emit_arith_operand(0x81, rbx, dst, imm32); | |
5603 } | |
5604 | |
5605 void Assembler::sbbq(Register dst, int32_t imm32) { | |
5606 (void) prefixq_and_encode(dst->encoding()); | |
5607 emit_arith(0x81, 0xD8, dst, imm32); | |
5608 } | |
5609 | |
5610 void Assembler::sbbq(Register dst, Address src) { | |
5611 InstructionMark im(this); | |
5612 prefixq(src, dst); | |
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changeset
|
5613 emit_int8(0x1B); |
304 | 5614 emit_operand(dst, src); |
5615 } | |
5616 | |
5617 void Assembler::sbbq(Register dst, Register src) { | |
5618 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5619 emit_arith(0x1B, 0xC0, dst, src); | |
5620 } | |
5621 | |
5622 void Assembler::shlq(Register dst, int imm8) { | |
5623 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5624 int encode = prefixq_and_encode(dst->encoding()); | |
5625 if (imm8 == 1) { | |
7430
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changeset
|
5626 emit_int8((unsigned char)0xD1); |
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changeset
|
5627 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 5628 } else { |
7430
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changeset
|
5629 emit_int8((unsigned char)0xC1); |
d02120b7a34f
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changeset
|
5630 emit_int8((unsigned char)(0xE0 | encode)); |
d02120b7a34f
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diff
changeset
|
5631 emit_int8(imm8); |
304 | 5632 } |
5633 } | |
5634 | |
5635 void Assembler::shlq(Register dst) { | |
5636 int encode = prefixq_and_encode(dst->encoding()); | |
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changeset
|
5637 emit_int8((unsigned char)0xD3); |
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5638 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 5639 } |
5640 | |
5641 void Assembler::shrq(Register dst, int imm8) { | |
5642 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5643 int encode = prefixq_and_encode(dst->encoding()); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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5644 emit_int8((unsigned char)0xC1); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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5645 emit_int8((unsigned char)(0xE8 | encode)); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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5646 emit_int8(imm8); |
304 | 5647 } |
5648 | |
5649 void Assembler::shrq(Register dst) { | |
5650 int encode = prefixq_and_encode(dst->encoding()); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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5651 emit_int8((unsigned char)0xD3); |
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5652 emit_int8(0xE8 | encode); |
304 | 5653 } |
5654 | |
5655 void Assembler::subq(Address dst, int32_t imm32) { | |
5656 InstructionMark im(this); | |
5657 prefixq(dst); | |
2100
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changeset
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5658 emit_arith_operand(0x81, rbp, dst, imm32); |
304 | 5659 } |
5660 | |
5661 void Assembler::subq(Address dst, Register src) { | |
5662 InstructionMark im(this); | |
5663 prefixq(dst, src); | |
7430
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5664 emit_int8(0x29); |
304 | 5665 emit_operand(src, dst); |
5666 } | |
5667 | |
2100
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5668 void Assembler::subq(Register dst, int32_t imm32) { |
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diff
changeset
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5669 (void) prefixq_and_encode(dst->encoding()); |
b1a2afa37ec4
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5670 emit_arith(0x81, 0xE8, dst, imm32); |
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|
5671 } |
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diff
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5672 |
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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diff
changeset
|
5673 // Force generation of a 4 byte immediate value even if it fits into 8bit |
fd8114661503
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5674 void Assembler::subq_imm32(Register dst, int32_t imm32) { |
fd8114661503
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5675 (void) prefixq_and_encode(dst->encoding()); |
fd8114661503
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changeset
|
5676 emit_arith_imm32(0x81, 0xE8, dst, imm32); |
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|
5677 } |
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|
5678 |
304 | 5679 void Assembler::subq(Register dst, Address src) { |
5680 InstructionMark im(this); | |
5681 prefixq(src, dst); | |
7430
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|
5682 emit_int8(0x2B); |
304 | 5683 emit_operand(dst, src); |
5684 } | |
5685 | |
5686 void Assembler::subq(Register dst, Register src) { | |
5687 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5688 emit_arith(0x2B, 0xC0, dst, src); | |
5689 } | |
5690 | |
5691 void Assembler::testq(Register dst, int32_t imm32) { | |
5692 // not using emit_arith because test | |
5693 // doesn't support sign-extension of | |
5694 // 8bit operands | |
5695 int encode = dst->encoding(); | |
5696 if (encode == 0) { | |
5697 prefix(REX_W); | |
7430
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|
5698 emit_int8((unsigned char)0xA9); |
304 | 5699 } else { |
5700 encode = prefixq_and_encode(encode); | |
7430
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|
5701 emit_int8((unsigned char)0xF7); |
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5702 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5703 } |
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
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7475
diff
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|
5704 emit_int32(imm32); |
304 | 5705 } |
5706 | |
5707 void Assembler::testq(Register dst, Register src) { | |
5708 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5709 emit_arith(0x85, 0xC0, dst, src); | |
5710 } | |
5711 | |
5712 void Assembler::xaddq(Address dst, Register src) { | |
5713 InstructionMark im(this); | |
5714 prefixq(dst, src); | |
7430
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|
5715 emit_int8(0x0F); |
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|
5716 emit_int8((unsigned char)0xC1); |
304 | 5717 emit_operand(src, dst); |
5718 } | |
5719 | |
5720 void Assembler::xchgq(Register dst, Address src) { | |
5721 InstructionMark im(this); | |
5722 prefixq(src, dst); | |
7430
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|
5723 emit_int8((unsigned char)0x87); |
304 | 5724 emit_operand(dst, src); |
5725 } | |
5726 | |
5727 void Assembler::xchgq(Register dst, Register src) { | |
5728 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
7430
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|
5729 emit_int8((unsigned char)0x87); |
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|
5730 emit_int8((unsigned char)(0xc0 | encode)); |
304 | 5731 } |
5732 | |
5733 void Assembler::xorq(Register dst, Register src) { | |
5734 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5735 emit_arith(0x33, 0xC0, dst, src); | |
5736 } | |
5737 | |
5738 void Assembler::xorq(Register dst, Address src) { | |
5739 InstructionMark im(this); | |
5740 prefixq(src, dst); | |
7430
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changeset
|
5741 emit_int8(0x33); |
304 | 5742 emit_operand(dst, src); |
5743 } | |
5744 | |
5745 #endif // !LP64 |