Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_64.ad @ 17809:a433eb716ce1
8037821: Account for trampoline stubs when estimating code buffer sizes
Summary: Take into account space needed for "trampoline code" used by calls on PPC64.
Reviewed-by: kvn
Contributed-by: lutz.schmidt@sap.com
| author | goetz |
|---|---|
| date | Tue, 25 Mar 2014 12:54:21 -0700 |
| parents | f040cf9fc9c0 |
| children | 62c54fcc0a35 |
| rev | line source |
|---|---|
| 0 | 1 // |
| 9154 | 2 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // AMD64 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when | |
| 64 // used as byte registers) | |
| 65 | |
| 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code | |
| 67 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 68 // Now that allocator is better, turn on RSI and RDI as SOE registers. | |
| 69 | |
| 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next()); | |
| 72 | |
| 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next()); | |
| 75 | |
| 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next()); | |
| 78 | |
| 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next()); | |
| 81 | |
| 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next()); | |
| 84 | |
| 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code | |
| 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next()); | |
| 88 | |
| 89 #ifdef _WIN64 | |
| 90 | |
| 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 93 | |
| 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 96 | |
| 97 #else | |
| 98 | |
| 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg()); | |
| 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 101 | |
| 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg()); | |
| 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 104 | |
| 105 #endif | |
| 106 | |
| 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg()); | |
| 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next()); | |
| 109 | |
| 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg()); | |
| 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next()); | |
| 112 | |
| 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg()); | |
| 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next()); | |
| 115 | |
| 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg()); | |
| 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next()); | |
| 118 | |
| 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg()); | |
| 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next()); | |
| 121 | |
| 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg()); | |
| 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next()); | |
| 124 | |
| 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg()); | |
| 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next()); | |
| 127 | |
| 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg()); | |
| 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next()); | |
| 130 | |
| 131 | |
| 132 // Floating Point Registers | |
| 133 | |
| 134 // Specify priority of register selection within phases of register | |
| 135 // allocation. Highest priority is first. A useful heuristic is to | |
| 136 // give registers a low priority when they are required by machine | |
| 137 // instructions, like EAX and EDX on I486, and choose no-save registers | |
| 138 // before save-on-call, & save-on-call before save-on-entry. Registers | |
| 139 // which participate in fixed calling sequences should come last. | |
| 140 // Registers which are used as pairs must fall on an even boundary. | |
| 141 | |
| 142 alloc_class chunk0(R10, R10_H, | |
| 143 R11, R11_H, | |
| 144 R8, R8_H, | |
| 145 R9, R9_H, | |
| 146 R12, R12_H, | |
| 147 RCX, RCX_H, | |
| 148 RBX, RBX_H, | |
| 149 RDI, RDI_H, | |
| 150 RDX, RDX_H, | |
| 151 RSI, RSI_H, | |
| 152 RAX, RAX_H, | |
| 153 RBP, RBP_H, | |
| 154 R13, R13_H, | |
| 155 R14, R14_H, | |
| 156 R15, R15_H, | |
| 157 RSP, RSP_H); | |
| 158 | |
| 159 | |
| 160 //----------Architecture Description Register Classes-------------------------- | |
| 161 // Several register classes are automatically defined based upon information in | |
| 162 // this architecture description. | |
| 163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 167 // | |
| 168 | |
| 169 // Class for all pointer registers (including RSP) | |
| 170 reg_class any_reg(RAX, RAX_H, | |
| 171 RDX, RDX_H, | |
| 172 RBP, RBP_H, | |
| 173 RDI, RDI_H, | |
| 174 RSI, RSI_H, | |
| 175 RCX, RCX_H, | |
| 176 RBX, RBX_H, | |
| 177 RSP, RSP_H, | |
| 178 R8, R8_H, | |
| 179 R9, R9_H, | |
| 180 R10, R10_H, | |
| 181 R11, R11_H, | |
| 182 R12, R12_H, | |
| 183 R13, R13_H, | |
| 184 R14, R14_H, | |
| 185 R15, R15_H); | |
| 186 | |
| 187 // Class for all pointer registers except RSP | |
| 188 reg_class ptr_reg(RAX, RAX_H, | |
| 189 RDX, RDX_H, | |
| 190 RBP, RBP_H, | |
| 191 RDI, RDI_H, | |
| 192 RSI, RSI_H, | |
| 193 RCX, RCX_H, | |
| 194 RBX, RBX_H, | |
| 195 R8, R8_H, | |
| 196 R9, R9_H, | |
| 197 R10, R10_H, | |
| 198 R11, R11_H, | |
| 199 R13, R13_H, | |
| 200 R14, R14_H); | |
| 201 | |
| 202 // Class for all pointer registers except RAX and RSP | |
| 203 reg_class ptr_no_rax_reg(RDX, RDX_H, | |
| 204 RBP, RBP_H, | |
| 205 RDI, RDI_H, | |
| 206 RSI, RSI_H, | |
| 207 RCX, RCX_H, | |
| 208 RBX, RBX_H, | |
| 209 R8, R8_H, | |
| 210 R9, R9_H, | |
| 211 R10, R10_H, | |
| 212 R11, R11_H, | |
| 213 R13, R13_H, | |
| 214 R14, R14_H); | |
| 215 | |
| 216 reg_class ptr_no_rbp_reg(RDX, RDX_H, | |
| 217 RAX, RAX_H, | |
| 218 RDI, RDI_H, | |
| 219 RSI, RSI_H, | |
| 220 RCX, RCX_H, | |
| 221 RBX, RBX_H, | |
| 222 R8, R8_H, | |
| 223 R9, R9_H, | |
| 224 R10, R10_H, | |
| 225 R11, R11_H, | |
| 226 R13, R13_H, | |
| 227 R14, R14_H); | |
| 228 | |
| 229 // Class for all pointer registers except RAX, RBX and RSP | |
| 230 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H, | |
| 231 RBP, RBP_H, | |
| 232 RDI, RDI_H, | |
| 233 RSI, RSI_H, | |
| 234 RCX, RCX_H, | |
| 235 R8, R8_H, | |
| 236 R9, R9_H, | |
| 237 R10, R10_H, | |
| 238 R11, R11_H, | |
| 239 R13, R13_H, | |
| 240 R14, R14_H); | |
| 241 | |
| 242 // Singleton class for RAX pointer register | |
| 243 reg_class ptr_rax_reg(RAX, RAX_H); | |
| 244 | |
| 245 // Singleton class for RBX pointer register | |
| 246 reg_class ptr_rbx_reg(RBX, RBX_H); | |
| 247 | |
| 248 // Singleton class for RSI pointer register | |
| 249 reg_class ptr_rsi_reg(RSI, RSI_H); | |
| 250 | |
| 251 // Singleton class for RDI pointer register | |
| 252 reg_class ptr_rdi_reg(RDI, RDI_H); | |
| 253 | |
| 254 // Singleton class for RBP pointer register | |
| 255 reg_class ptr_rbp_reg(RBP, RBP_H); | |
| 256 | |
| 257 // Singleton class for stack pointer | |
| 258 reg_class ptr_rsp_reg(RSP, RSP_H); | |
| 259 | |
| 260 // Singleton class for TLS pointer | |
| 261 reg_class ptr_r15_reg(R15, R15_H); | |
| 262 | |
| 263 // Class for all long registers (except RSP) | |
| 264 reg_class long_reg(RAX, RAX_H, | |
| 265 RDX, RDX_H, | |
| 266 RBP, RBP_H, | |
| 267 RDI, RDI_H, | |
| 268 RSI, RSI_H, | |
| 269 RCX, RCX_H, | |
| 270 RBX, RBX_H, | |
| 271 R8, R8_H, | |
| 272 R9, R9_H, | |
| 273 R10, R10_H, | |
| 274 R11, R11_H, | |
| 275 R13, R13_H, | |
| 276 R14, R14_H); | |
| 277 | |
| 278 // Class for all long registers except RAX, RDX (and RSP) | |
| 279 reg_class long_no_rax_rdx_reg(RBP, RBP_H, | |
| 280 RDI, RDI_H, | |
| 281 RSI, RSI_H, | |
| 282 RCX, RCX_H, | |
| 283 RBX, RBX_H, | |
| 284 R8, R8_H, | |
| 285 R9, R9_H, | |
| 286 R10, R10_H, | |
| 287 R11, R11_H, | |
| 288 R13, R13_H, | |
| 289 R14, R14_H); | |
| 290 | |
| 291 // Class for all long registers except RCX (and RSP) | |
| 292 reg_class long_no_rcx_reg(RBP, RBP_H, | |
| 293 RDI, RDI_H, | |
| 294 RSI, RSI_H, | |
| 295 RAX, RAX_H, | |
| 296 RDX, RDX_H, | |
| 297 RBX, RBX_H, | |
| 298 R8, R8_H, | |
| 299 R9, R9_H, | |
| 300 R10, R10_H, | |
| 301 R11, R11_H, | |
| 302 R13, R13_H, | |
| 303 R14, R14_H); | |
| 304 | |
| 305 // Class for all long registers except RAX (and RSP) | |
| 306 reg_class long_no_rax_reg(RBP, RBP_H, | |
| 307 RDX, RDX_H, | |
| 308 RDI, RDI_H, | |
| 309 RSI, RSI_H, | |
| 310 RCX, RCX_H, | |
| 311 RBX, RBX_H, | |
| 312 R8, R8_H, | |
| 313 R9, R9_H, | |
| 314 R10, R10_H, | |
| 315 R11, R11_H, | |
| 316 R13, R13_H, | |
| 317 R14, R14_H); | |
| 318 | |
| 319 // Singleton class for RAX long register | |
| 320 reg_class long_rax_reg(RAX, RAX_H); | |
| 321 | |
| 322 // Singleton class for RCX long register | |
| 323 reg_class long_rcx_reg(RCX, RCX_H); | |
| 324 | |
| 325 // Singleton class for RDX long register | |
| 326 reg_class long_rdx_reg(RDX, RDX_H); | |
| 327 | |
| 328 // Class for all int registers (except RSP) | |
| 329 reg_class int_reg(RAX, | |
| 330 RDX, | |
| 331 RBP, | |
| 332 RDI, | |
| 333 RSI, | |
| 334 RCX, | |
| 335 RBX, | |
| 336 R8, | |
| 337 R9, | |
| 338 R10, | |
| 339 R11, | |
| 340 R13, | |
| 341 R14); | |
| 342 | |
| 343 // Class for all int registers except RCX (and RSP) | |
| 344 reg_class int_no_rcx_reg(RAX, | |
| 345 RDX, | |
| 346 RBP, | |
| 347 RDI, | |
| 348 RSI, | |
| 349 RBX, | |
| 350 R8, | |
| 351 R9, | |
| 352 R10, | |
| 353 R11, | |
| 354 R13, | |
| 355 R14); | |
| 356 | |
| 357 // Class for all int registers except RAX, RDX (and RSP) | |
| 358 reg_class int_no_rax_rdx_reg(RBP, | |
| 304 | 359 RDI, |
| 0 | 360 RSI, |
| 361 RCX, | |
| 362 RBX, | |
| 363 R8, | |
| 364 R9, | |
| 365 R10, | |
| 366 R11, | |
| 367 R13, | |
| 368 R14); | |
| 369 | |
| 370 // Singleton class for RAX int register | |
| 371 reg_class int_rax_reg(RAX); | |
| 372 | |
| 373 // Singleton class for RBX int register | |
| 374 reg_class int_rbx_reg(RBX); | |
| 375 | |
| 376 // Singleton class for RCX int register | |
| 377 reg_class int_rcx_reg(RCX); | |
| 378 | |
| 379 // Singleton class for RCX int register | |
| 380 reg_class int_rdx_reg(RDX); | |
| 381 | |
| 382 // Singleton class for RCX int register | |
| 383 reg_class int_rdi_reg(RDI); | |
| 384 | |
| 385 // Singleton class for instruction pointer | |
| 386 // reg_class ip_reg(RIP); | |
| 387 | |
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388 %} |
| 0 | 389 |
| 390 //----------SOURCE BLOCK------------------------------------------------------- | |
| 391 // This is a block of C++ code which provides values, functions, and | |
| 392 // definitions necessary in the rest of the architecture description | |
| 393 source %{ | |
| 304 | 394 #define RELOC_IMM64 Assembler::imm_operand |
| 0 | 395 #define RELOC_DISP32 Assembler::disp32_operand |
| 396 | |
| 397 #define __ _masm. | |
| 398 | |
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399 static int preserve_SP_size() { |
| 4759 | 400 return 3; // rex.w, op, rm(reg/reg) |
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401 } |
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402 static int clear_avx_size() { |
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403 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper |
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404 } |
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405 |
| 0 | 406 // !!!!! Special hack to get all types of calls to specify the byte offset |
| 407 // from the start of the call to the point where the return address | |
| 408 // will point. | |
| 409 int MachCallStaticJavaNode::ret_addr_offset() | |
| 410 { | |
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411 int offset = 5; // 5 bytes from start of call to where return address points |
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412 offset += clear_avx_size(); |
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413 if (_method_handle_invoke) |
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414 offset += preserve_SP_size(); |
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415 return offset; |
| 0 | 416 } |
| 417 | |
| 418 int MachCallDynamicJavaNode::ret_addr_offset() | |
| 419 { | |
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420 int offset = 15; // 15 bytes from start of call to where return address points |
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421 offset += clear_avx_size(); |
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422 return offset; |
| 0 | 423 } |
| 424 | |
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425 int MachCallRuntimeNode::ret_addr_offset() { |
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426 int offset = 13; // movq r10,#addr; callq (r10) |
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427 offset += clear_avx_size(); |
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428 return offset; |
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429 } |
| 0 | 430 |
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431 // Indicate if the safepoint node needs the polling page as an input, |
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432 // it does if the polling page is more than disp32 away. |
| 0 | 433 bool SafePointNode::needs_polling_address_input() |
| 434 { | |
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435 return Assembler::is_polling_page_far(); |
| 0 | 436 } |
| 437 | |
| 438 // | |
| 439 // Compute padding required for nodes which need alignment | |
| 440 // | |
| 441 | |
| 442 // The address of the call instruction needs to be 4-byte aligned to | |
| 443 // ensure that it does not span a cache line so that it can be patched. | |
| 444 int CallStaticJavaDirectNode::compute_padding(int current_offset) const | |
| 445 { | |
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446 current_offset += clear_avx_size(); // skip vzeroupper |
| 0 | 447 current_offset += 1; // skip call opcode byte |
| 448 return round_to(current_offset, alignment_required()) - current_offset; | |
| 449 } | |
| 450 | |
| 451 // The address of the call instruction needs to be 4-byte aligned to | |
| 452 // ensure that it does not span a cache line so that it can be patched. | |
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453 int CallStaticJavaHandleNode::compute_padding(int current_offset) const |
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454 { |
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455 current_offset += preserve_SP_size(); // skip mov rbp, rsp |
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456 current_offset += clear_avx_size(); // skip vzeroupper |
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457 current_offset += 1; // skip call opcode byte |
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458 return round_to(current_offset, alignment_required()) - current_offset; |
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459 } |
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460 |
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461 // The address of the call instruction needs to be 4-byte aligned to |
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462 // ensure that it does not span a cache line so that it can be patched. |
| 0 | 463 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const |
| 464 { | |
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465 current_offset += clear_avx_size(); // skip vzeroupper |
| 0 | 466 current_offset += 11; // skip movq instruction + call opcode byte |
| 467 return round_to(current_offset, alignment_required()) - current_offset; | |
| 468 } | |
| 469 | |
| 470 // EMIT_RM() | |
| 1748 | 471 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { |
| 0 | 472 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3); |
| 1748 | 473 cbuf.insts()->emit_int8(c); |
| 0 | 474 } |
| 475 | |
| 476 // EMIT_CC() | |
| 1748 | 477 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { |
| 0 | 478 unsigned char c = (unsigned char) (f1 | f2); |
| 1748 | 479 cbuf.insts()->emit_int8(c); |
| 0 | 480 } |
| 481 | |
| 482 // EMIT_OPCODE() | |
| 1748 | 483 void emit_opcode(CodeBuffer &cbuf, int code) { |
| 484 cbuf.insts()->emit_int8((unsigned char) code); | |
| 0 | 485 } |
| 486 | |
| 487 // EMIT_OPCODE() w/ relocation information | |
| 488 void emit_opcode(CodeBuffer &cbuf, | |
| 489 int code, relocInfo::relocType reloc, int offset, int format) | |
| 490 { | |
| 1748 | 491 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format); |
| 0 | 492 emit_opcode(cbuf, code); |
| 493 } | |
| 494 | |
| 495 // EMIT_D8() | |
| 1748 | 496 void emit_d8(CodeBuffer &cbuf, int d8) { |
| 497 cbuf.insts()->emit_int8((unsigned char) d8); | |
| 0 | 498 } |
| 499 | |
| 500 // EMIT_D16() | |
| 1748 | 501 void emit_d16(CodeBuffer &cbuf, int d16) { |
| 502 cbuf.insts()->emit_int16(d16); | |
| 0 | 503 } |
| 504 | |
| 505 // EMIT_D32() | |
| 1748 | 506 void emit_d32(CodeBuffer &cbuf, int d32) { |
| 507 cbuf.insts()->emit_int32(d32); | |
| 0 | 508 } |
| 509 | |
| 510 // EMIT_D64() | |
| 1748 | 511 void emit_d64(CodeBuffer &cbuf, int64_t d64) { |
| 512 cbuf.insts()->emit_int64(d64); | |
| 0 | 513 } |
| 514 | |
| 515 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 516 void emit_d32_reloc(CodeBuffer& cbuf, | |
| 517 int d32, | |
| 518 relocInfo::relocType reloc, | |
| 519 int format) | |
| 520 { | |
| 521 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc"); | |
| 1748 | 522 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 523 cbuf.insts()->emit_int32(d32); | |
| 0 | 524 } |
| 525 | |
| 526 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 527 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) { |
| 0 | 528 #ifdef ASSERT |
| 529 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 530 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { | |
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531 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop"); |
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532 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 533 } |
| 534 #endif | |
| 1748 | 535 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 536 cbuf.insts()->emit_int32(d32); | |
| 0 | 537 } |
| 538 | |
| 539 void emit_d32_reloc(CodeBuffer& cbuf, address addr) { | |
| 1748 | 540 address next_ip = cbuf.insts_end() + 4; |
| 0 | 541 emit_d32_reloc(cbuf, (int) (addr - next_ip), |
| 542 external_word_Relocation::spec(addr), | |
| 543 RELOC_DISP32); | |
| 544 } | |
| 545 | |
| 546 | |
| 547 // emit 64 bit value and construct relocation entry from relocInfo::relocType | |
| 1748 | 548 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) { |
| 549 cbuf.relocate(cbuf.insts_mark(), reloc, format); | |
| 550 cbuf.insts()->emit_int64(d64); | |
| 0 | 551 } |
| 552 | |
| 553 // emit 64 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 554 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) { |
| 0 | 555 #ifdef ASSERT |
| 556 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 557 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { | |
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558 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop"); |
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559 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()), |
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560 "cannot embed scavengable oops in code"); |
| 0 | 561 } |
| 562 #endif | |
| 1748 | 563 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 564 cbuf.insts()->emit_int64(d64); | |
| 0 | 565 } |
| 566 | |
| 567 // Access stack slot for load or store | |
| 568 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) | |
| 569 { | |
| 570 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src]) | |
| 571 if (-0x80 <= disp && disp < 0x80) { | |
| 572 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte | |
| 573 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 574 emit_d8(cbuf, disp); // Displacement // R/M byte | |
| 575 } else { | |
| 576 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte | |
| 577 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 578 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 579 } | |
| 580 } | |
| 581 | |
| 582 // rRegI ereg, memory mem) %{ // emit_reg_mem | |
| 583 void encode_RegMem(CodeBuffer &cbuf, | |
| 584 int reg, | |
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585 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) |
| 0 | 586 { |
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587 assert(disp_reloc == relocInfo::none, "cannot have disp"); |
| 0 | 588 int regenc = reg & 7; |
| 589 int baseenc = base & 7; | |
| 590 int indexenc = index & 7; | |
| 591 | |
| 592 // There is no index & no scale, use form without SIB byte | |
| 593 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) { | |
| 594 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 595 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 596 emit_rm(cbuf, 0x0, regenc, baseenc); // * | |
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597 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) { |
| 0 | 598 // If 8-bit displacement, mode 0x1 |
| 599 emit_rm(cbuf, 0x1, regenc, baseenc); // * | |
| 600 emit_d8(cbuf, disp); | |
| 601 } else { | |
| 602 // If 32-bit displacement | |
| 603 if (base == -1) { // Special flag for absolute address | |
| 604 emit_rm(cbuf, 0x0, regenc, 0x5); // * | |
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605 if (disp_reloc != relocInfo::none) { |
| 0 | 606 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
| 607 } else { | |
| 608 emit_d32(cbuf, disp); | |
| 609 } | |
| 610 } else { | |
| 611 // Normal base + offset | |
| 612 emit_rm(cbuf, 0x2, regenc, baseenc); // * | |
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613 if (disp_reloc != relocInfo::none) { |
| 0 | 614 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
| 615 } else { | |
| 616 emit_d32(cbuf, disp); | |
| 617 } | |
| 618 } | |
| 619 } | |
| 620 } else { | |
| 621 // Else, encode with the SIB byte | |
| 622 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 623 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 624 // If no displacement | |
| 625 emit_rm(cbuf, 0x0, regenc, 0x4); // * | |
| 626 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 627 } else { | |
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628 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) { |
| 0 | 629 // If 8-bit displacement, mode 0x1 |
| 630 emit_rm(cbuf, 0x1, regenc, 0x4); // * | |
| 631 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 632 emit_d8(cbuf, disp); | |
| 633 } else { | |
| 634 // If 32-bit displacement | |
| 635 if (base == 0x04 ) { | |
| 636 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 637 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid??? | |
| 638 } else { | |
| 639 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 640 emit_rm(cbuf, scale, indexenc, baseenc); // * | |
| 641 } | |
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642 if (disp_reloc != relocInfo::none) { |
| 0 | 643 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
| 644 } else { | |
| 645 emit_d32(cbuf, disp); | |
| 646 } | |
| 647 } | |
| 648 } | |
| 649 } | |
| 650 } | |
| 651 | |
| 3783 | 652 // This could be in MacroAssembler but it's fairly C2 specific |
| 653 void emit_cmpfp_fixup(MacroAssembler& _masm) { | |
| 654 Label exit; | |
| 655 __ jccb(Assembler::noParity, exit); | |
| 656 __ pushf(); | |
| 4759 | 657 // |
| 658 // comiss/ucomiss instructions set ZF,PF,CF flags and | |
| 659 // zero OF,AF,SF for NaN values. | |
| 660 // Fixup flags by zeroing ZF,PF so that compare of NaN | |
| 661 // values returns 'less than' result (CF is set). | |
| 662 // Leave the rest of flags unchanged. | |
| 663 // | |
| 664 // 7 6 5 4 3 2 1 0 | |
| 665 // |S|Z|r|A|r|P|r|C| (r - reserved bit) | |
| 666 // 0 0 1 0 1 0 1 1 (0x2B) | |
| 667 // | |
| 3783 | 668 __ andq(Address(rsp, 0), 0xffffff2b); |
| 669 __ popf(); | |
| 670 __ bind(exit); | |
| 4759 | 671 } |
| 672 | |
| 673 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { | |
| 674 Label done; | |
| 675 __ movl(dst, -1); | |
| 676 __ jcc(Assembler::parity, done); | |
| 677 __ jcc(Assembler::below, done); | |
| 678 __ setb(Assembler::notEqual, dst); | |
| 679 __ movzbl(dst, dst); | |
| 680 __ bind(done); | |
| 3783 | 681 } |
| 682 | |
| 0 | 683 |
| 684 //============================================================================= | |
| 2008 | 685 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
| 686 | |
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687 int Compile::ConstantTable::calculate_table_base_offset() const { |
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688 return 0; // absolute addressing, no offset |
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689 } |
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690 |
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691 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } |
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692 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { |
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693 ShouldNotReachHere(); |
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694 } |
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695 |
| 2008 | 696 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 697 // Empty encoding | |
| 698 } | |
| 699 | |
| 700 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 701 return 0; | |
| 702 } | |
| 703 | |
| 704 #ifndef PRODUCT | |
| 705 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 706 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 707 } | |
| 708 #endif | |
| 709 | |
| 710 | |
| 711 //============================================================================= | |
| 0 | 712 #ifndef PRODUCT |
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713 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
| 0 | 714 Compile* C = ra_->C; |
| 715 | |
| 716 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 717 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
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718 // Remove wordSize for return addr which is already pushed. |
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719 framesize -= wordSize; |
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720 |
| 0 | 721 if (C->need_stack_bang(framesize)) { |
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722 framesize -= wordSize; |
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723 st->print("# stack bang"); |
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724 st->print("\n\t"); |
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725 st->print("pushq rbp\t# Save rbp"); |
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726 if (framesize) { |
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727 st->print("\n\t"); |
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728 st->print("subq rsp, #%d\t# Create frame",framesize); |
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729 } |
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730 } else { |
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731 st->print("subq rsp, #%d\t# Create frame",framesize); |
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732 st->print("\n\t"); |
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733 framesize -= wordSize; |
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734 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize); |
| 0 | 735 } |
| 736 | |
| 737 if (VerifyStackAtCalls) { | |
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738 st->print("\n\t"); |
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739 framesize -= wordSize; |
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740 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize); |
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741 #ifdef ASSERT |
|
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742 st->print("\n\t"); |
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743 st->print("# stack alignment check"); |
|
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744 #endif |
| 0 | 745 } |
|
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746 st->cr(); |
| 0 | 747 } |
| 748 #endif | |
| 749 | |
|
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750 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
| 0 | 751 Compile* C = ra_->C; |
|
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752 MacroAssembler _masm(&cbuf); |
| 0 | 753 |
| 754 int framesize = C->frame_slots() << LogBytesPerInt; | |
|
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755 |
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756 __ verified_entry(framesize, C->need_stack_bang(framesize), false); |
| 0 | 757 |
| 1748 | 758 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 759 |
|
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760 if (C->has_mach_constant_base_node()) { |
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761 // NOTE: We set the table base offset here because users might be |
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762 // emitted before MachConstantBaseNode. |
|
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763 Compile::ConstantTable& constant_table = C->constant_table(); |
|
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764 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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765 } |
| 0 | 766 } |
| 767 | |
| 768 uint MachPrologNode::size(PhaseRegAlloc* ra_) const | |
| 769 { | |
| 770 return MachNode::size(ra_); // too many variables; just compute it | |
| 771 // the hard way | |
| 772 } | |
| 773 | |
| 774 int MachPrologNode::reloc() const | |
| 775 { | |
| 776 return 0; // a large enough number | |
| 777 } | |
| 778 | |
| 779 //============================================================================= | |
| 780 #ifndef PRODUCT | |
| 781 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 782 { | |
| 783 Compile* C = ra_->C; | |
|
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784 if (C->max_vector_size() > 16) { |
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785 st->print("vzeroupper"); |
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786 st->cr(); st->print("\t"); |
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787 } |
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788 |
| 0 | 789 int framesize = C->frame_slots() << LogBytesPerInt; |
| 790 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 791 // Remove word for return adr already pushed | |
| 792 // and RBP | |
| 793 framesize -= 2*wordSize; | |
| 794 | |
| 795 if (framesize) { | |
|
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796 st->print_cr("addq rsp, %d\t# Destroy frame", framesize); |
| 0 | 797 st->print("\t"); |
| 798 } | |
| 799 | |
|
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800 st->print_cr("popq rbp"); |
| 0 | 801 if (do_polling() && C->is_method_compilation()) { |
| 802 st->print("\t"); | |
|
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803 if (Assembler::is_polling_page_far()) { |
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804 st->print_cr("movq rscratch1, #polling_page_address\n\t" |
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805 "testl rax, [rscratch1]\t" |
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806 "# Safepoint: poll for GC"); |
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807 } else { |
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808 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t" |
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809 "# Safepoint: poll for GC"); |
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810 } |
| 0 | 811 } |
| 812 } | |
| 813 #endif | |
| 814 | |
| 815 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 816 { | |
| 817 Compile* C = ra_->C; | |
|
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818 if (C->max_vector_size() > 16) { |
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819 // Clear upper bits of YMM registers when current compiled code uses |
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820 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
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821 MacroAssembler _masm(&cbuf); |
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822 __ vzeroupper(); |
|
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|
823 } |
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824 |
| 0 | 825 int framesize = C->frame_slots() << LogBytesPerInt; |
| 826 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 827 // Remove word for return adr already pushed | |
| 828 // and RBP | |
| 829 framesize -= 2*wordSize; | |
| 830 | |
| 831 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 832 | |
| 833 if (framesize) { | |
| 834 emit_opcode(cbuf, Assembler::REX_W); | |
| 835 if (framesize < 0x80) { | |
| 836 emit_opcode(cbuf, 0x83); // addq rsp, #framesize | |
| 837 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 838 emit_d8(cbuf, framesize); | |
| 839 } else { | |
| 840 emit_opcode(cbuf, 0x81); // addq rsp, #framesize | |
| 841 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 842 emit_d32(cbuf, framesize); | |
| 843 } | |
| 844 } | |
| 845 | |
| 846 // popq rbp | |
| 847 emit_opcode(cbuf, 0x58 | RBP_enc); | |
| 848 | |
| 849 if (do_polling() && C->is_method_compilation()) { | |
|
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850 MacroAssembler _masm(&cbuf); |
|
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851 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); |
|
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852 if (Assembler::is_polling_page_far()) { |
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853 __ lea(rscratch1, polling_page); |
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854 __ relocate(relocInfo::poll_return_type); |
|
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855 __ testl(rax, Address(rscratch1, 0)); |
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856 } else { |
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|
857 __ testl(rax, polling_page); |
|
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|
858 } |
| 0 | 859 } |
| 860 } | |
| 861 | |
| 862 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const | |
| 863 { | |
|
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864 return MachNode::size(ra_); // too many variables; just compute it |
|
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|
865 // the hard way |
| 0 | 866 } |
| 867 | |
| 868 int MachEpilogNode::reloc() const | |
| 869 { | |
| 870 return 2; // a large enough number | |
| 871 } | |
| 872 | |
| 873 const Pipeline* MachEpilogNode::pipeline() const | |
| 874 { | |
| 875 return MachNode::pipeline_class(); | |
| 876 } | |
| 877 | |
| 878 int MachEpilogNode::safepoint_offset() const | |
| 879 { | |
| 880 return 0; | |
| 881 } | |
| 882 | |
| 883 //============================================================================= | |
| 884 | |
| 885 enum RC { | |
| 886 rc_bad, | |
| 887 rc_int, | |
| 888 rc_float, | |
| 889 rc_stack | |
| 890 }; | |
| 891 | |
| 892 static enum RC rc_class(OptoReg::Name reg) | |
| 893 { | |
| 894 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 895 | |
| 896 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 897 | |
| 898 VMReg r = OptoReg::as_VMReg(reg); | |
| 899 | |
| 900 if (r->is_Register()) return rc_int; | |
| 901 | |
| 902 assert(r->is_XMMRegister(), "must be"); | |
| 903 return rc_float; | |
| 904 } | |
| 905 | |
|
6179
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906 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
|
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|
907 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
|
8c92982cbbc4
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|
908 int src_hi, int dst_hi, uint ireg, outputStream* st); |
|
8c92982cbbc4
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|
909 |
|
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|
910 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
|
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|
911 int stack_offset, int reg, uint ireg, outputStream* st); |
|
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|
912 |
|
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|
913 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset, |
|
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|
914 int dst_offset, uint ireg, outputStream* st) { |
|
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|
915 if (cbuf) { |
|
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|
916 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
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|
917 switch (ireg) { |
|
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|
918 case Op_VecS: |
|
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|
919 __ movq(Address(rsp, -8), rax); |
|
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|
920 __ movl(rax, Address(rsp, src_offset)); |
|
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|
921 __ movl(Address(rsp, dst_offset), rax); |
|
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922 __ movq(rax, Address(rsp, -8)); |
|
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|
923 break; |
|
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|
924 case Op_VecD: |
|
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|
925 __ pushq(Address(rsp, src_offset)); |
|
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|
926 __ popq (Address(rsp, dst_offset)); |
|
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|
927 break; |
|
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|
928 case Op_VecX: |
|
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|
929 __ pushq(Address(rsp, src_offset)); |
|
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|
930 __ popq (Address(rsp, dst_offset)); |
|
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|
931 __ pushq(Address(rsp, src_offset+8)); |
|
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|
932 __ popq (Address(rsp, dst_offset+8)); |
|
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|
933 break; |
|
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|
934 case Op_VecY: |
|
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|
935 __ vmovdqu(Address(rsp, -32), xmm0); |
|
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936 __ vmovdqu(xmm0, Address(rsp, src_offset)); |
|
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|
937 __ vmovdqu(Address(rsp, dst_offset), xmm0); |
|
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|
938 __ vmovdqu(xmm0, Address(rsp, -32)); |
|
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|
939 break; |
|
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|
940 default: |
|
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|
941 ShouldNotReachHere(); |
|
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|
942 } |
|
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|
943 #ifndef PRODUCT |
|
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|
944 } else { |
|
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|
945 switch (ireg) { |
|
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|
946 case Op_VecS: |
|
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|
947 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" |
|
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948 "movl rax, [rsp + #%d]\n\t" |
|
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|
949 "movl [rsp + #%d], rax\n\t" |
|
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950 "movq rax, [rsp - #8]", |
|
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|
951 src_offset, dst_offset); |
|
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|
952 break; |
|
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|
953 case Op_VecD: |
|
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954 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
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955 "popq [rsp + #%d]", |
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956 src_offset, dst_offset); |
|
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957 break; |
|
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958 case Op_VecX: |
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959 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t" |
|
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960 "popq [rsp + #%d]\n\t" |
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961 "pushq [rsp + #%d]\n\t" |
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962 "popq [rsp + #%d]", |
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963 src_offset, dst_offset, src_offset+8, dst_offset+8); |
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964 break; |
|
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965 case Op_VecY: |
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966 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t" |
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967 "vmovdqu xmm0, [rsp + #%d]\n\t" |
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968 "vmovdqu [rsp + #%d], xmm0\n\t" |
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969 "vmovdqu xmm0, [rsp - #32]", |
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970 src_offset, dst_offset); |
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971 break; |
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972 default: |
|
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973 ShouldNotReachHere(); |
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974 } |
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975 #endif |
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976 } |
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977 } |
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978 |
| 0 | 979 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf, |
| 980 PhaseRegAlloc* ra_, | |
| 981 bool do_size, | |
|
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982 outputStream* st) const { |
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983 assert(cbuf != NULL || st != NULL, "sanity"); |
| 0 | 984 // Get registers to move |
| 985 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 986 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 987 OptoReg::Name dst_second = ra_->get_reg_second(this); | |
| 988 OptoReg::Name dst_first = ra_->get_reg_first(this); | |
| 989 | |
| 990 enum RC src_second_rc = rc_class(src_second); | |
| 991 enum RC src_first_rc = rc_class(src_first); | |
| 992 enum RC dst_second_rc = rc_class(dst_second); | |
| 993 enum RC dst_first_rc = rc_class(dst_first); | |
| 994 | |
| 995 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), | |
| 996 "must move at least 1 register" ); | |
| 997 | |
| 998 if (src_first == dst_first && src_second == dst_second) { | |
| 999 // Self copy, no move | |
| 1000 return 0; | |
|
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1001 } |
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1002 if (bottom_type()->isa_vect() != NULL) { |
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1003 uint ireg = ideal_reg(); |
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1004 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity"); |
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1005 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity"); |
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1006 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { |
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1007 // mem -> mem |
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1008 int src_offset = ra_->reg2offset(src_first); |
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1009 int dst_offset = ra_->reg2offset(dst_first); |
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1010 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st); |
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1011 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) { |
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1012 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st); |
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1013 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) { |
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1014 int stack_offset = ra_->reg2offset(dst_first); |
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1015 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st); |
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1016 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) { |
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1017 int stack_offset = ra_->reg2offset(src_first); |
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1018 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st); |
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1019 } else { |
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1020 ShouldNotReachHere(); |
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1021 } |
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1022 return 0; |
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1023 } |
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1024 if (src_first_rc == rc_stack) { |
| 0 | 1025 // mem -> |
| 1026 if (dst_first_rc == rc_stack) { | |
| 1027 // mem -> mem | |
| 1028 assert(src_second != dst_first, "overlap"); | |
| 1029 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1030 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1031 // 64-bit | |
| 1032 int src_offset = ra_->reg2offset(src_first); | |
| 1033 int dst_offset = ra_->reg2offset(dst_first); | |
| 1034 if (cbuf) { | |
|
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1035 MacroAssembler _masm(cbuf); |
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1036 __ pushq(Address(rsp, src_offset)); |
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1037 __ popq (Address(rsp, dst_offset)); |
| 0 | 1038 #ifndef PRODUCT |
|
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1039 } else { |
| 0 | 1040 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
|
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1041 "popq [rsp + #%d]", |
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1042 src_offset, dst_offset); |
| 0 | 1043 #endif |
| 1044 } | |
| 1045 } else { | |
| 1046 // 32-bit | |
| 1047 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1048 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1049 // No pushl/popl, so: | |
| 1050 int src_offset = ra_->reg2offset(src_first); | |
| 1051 int dst_offset = ra_->reg2offset(dst_first); | |
| 1052 if (cbuf) { | |
|
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1053 MacroAssembler _masm(cbuf); |
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1054 __ movq(Address(rsp, -8), rax); |
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1055 __ movl(rax, Address(rsp, src_offset)); |
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1056 __ movl(Address(rsp, dst_offset), rax); |
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1057 __ movq(rax, Address(rsp, -8)); |
| 0 | 1058 #ifndef PRODUCT |
|
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1059 } else { |
| 0 | 1060 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" |
|
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1061 "movl rax, [rsp + #%d]\n\t" |
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1062 "movl [rsp + #%d], rax\n\t" |
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1063 "movq rax, [rsp - #8]", |
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1064 src_offset, dst_offset); |
| 0 | 1065 #endif |
| 1066 } | |
| 1067 } | |
|
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1068 return 0; |
| 0 | 1069 } else if (dst_first_rc == rc_int) { |
| 1070 // mem -> gpr | |
| 1071 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1072 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1073 // 64-bit | |
| 1074 int offset = ra_->reg2offset(src_first); | |
| 1075 if (cbuf) { | |
|
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1076 MacroAssembler _masm(cbuf); |
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1077 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset)); |
| 0 | 1078 #ifndef PRODUCT |
|
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1079 } else { |
| 0 | 1080 st->print("movq %s, [rsp + #%d]\t# spill", |
| 1081 Matcher::regName[dst_first], | |
| 1082 offset); | |
| 1083 #endif | |
| 1084 } | |
| 1085 } else { | |
| 1086 // 32-bit | |
| 1087 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1088 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1089 int offset = ra_->reg2offset(src_first); | |
| 1090 if (cbuf) { | |
|
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1091 MacroAssembler _masm(cbuf); |
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1092 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset)); |
| 0 | 1093 #ifndef PRODUCT |
|
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1094 } else { |
| 0 | 1095 st->print("movl %s, [rsp + #%d]\t# spill", |
| 1096 Matcher::regName[dst_first], | |
| 1097 offset); | |
| 1098 #endif | |
| 1099 } | |
| 1100 } | |
|
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1101 return 0; |
| 0 | 1102 } else if (dst_first_rc == rc_float) { |
| 1103 // mem-> xmm | |
| 1104 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1105 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1106 // 64-bit | |
| 1107 int offset = ra_->reg2offset(src_first); | |
| 1108 if (cbuf) { | |
| 4759 | 1109 MacroAssembler _masm(cbuf); |
| 1110 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); | |
| 0 | 1111 #ifndef PRODUCT |
|
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1112 } else { |
| 0 | 1113 st->print("%s %s, [rsp + #%d]\t# spill", |
| 1114 UseXmmLoadAndClearUpper ? "movsd " : "movlpd", | |
| 1115 Matcher::regName[dst_first], | |
| 1116 offset); | |
| 1117 #endif | |
| 1118 } | |
| 1119 } else { | |
| 1120 // 32-bit | |
| 1121 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1122 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1123 int offset = ra_->reg2offset(src_first); | |
| 1124 if (cbuf) { | |
| 4759 | 1125 MacroAssembler _masm(cbuf); |
| 1126 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); | |
| 0 | 1127 #ifndef PRODUCT |
|
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1128 } else { |
| 0 | 1129 st->print("movss %s, [rsp + #%d]\t# spill", |
| 1130 Matcher::regName[dst_first], | |
| 1131 offset); | |
| 1132 #endif | |
| 1133 } | |
| 1134 } | |
|
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1135 return 0; |
| 0 | 1136 } |
| 1137 } else if (src_first_rc == rc_int) { | |
| 1138 // gpr -> | |
| 1139 if (dst_first_rc == rc_stack) { | |
| 1140 // gpr -> mem | |
| 1141 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1142 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1143 // 64-bit | |
| 1144 int offset = ra_->reg2offset(dst_first); | |
| 1145 if (cbuf) { | |
|
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1146 MacroAssembler _masm(cbuf); |
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1147 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1148 #ifndef PRODUCT |
|
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1149 } else { |
| 0 | 1150 st->print("movq [rsp + #%d], %s\t# spill", |
| 1151 offset, | |
| 1152 Matcher::regName[src_first]); | |
| 1153 #endif | |
| 1154 } | |
| 1155 } else { | |
| 1156 // 32-bit | |
| 1157 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1158 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1159 int offset = ra_->reg2offset(dst_first); | |
| 1160 if (cbuf) { | |
|
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1161 MacroAssembler _masm(cbuf); |
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1162 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1163 #ifndef PRODUCT |
|
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1164 } else { |
| 0 | 1165 st->print("movl [rsp + #%d], %s\t# spill", |
| 1166 offset, | |
| 1167 Matcher::regName[src_first]); | |
| 1168 #endif | |
| 1169 } | |
| 1170 } | |
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1171 return 0; |
| 0 | 1172 } else if (dst_first_rc == rc_int) { |
| 1173 // gpr -> gpr | |
| 1174 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1175 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1176 // 64-bit | |
| 1177 if (cbuf) { | |
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1178 MacroAssembler _masm(cbuf); |
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1179 __ movq(as_Register(Matcher::_regEncode[dst_first]), |
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1180 as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1181 #ifndef PRODUCT |
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1182 } else { |
| 0 | 1183 st->print("movq %s, %s\t# spill", |
| 1184 Matcher::regName[dst_first], | |
| 1185 Matcher::regName[src_first]); | |
| 1186 #endif | |
| 1187 } | |
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1188 return 0; |
| 0 | 1189 } else { |
| 1190 // 32-bit | |
| 1191 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1192 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1193 if (cbuf) { | |
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1194 MacroAssembler _masm(cbuf); |
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1195 __ movl(as_Register(Matcher::_regEncode[dst_first]), |
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1196 as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1197 #ifndef PRODUCT |
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1198 } else { |
| 0 | 1199 st->print("movl %s, %s\t# spill", |
| 1200 Matcher::regName[dst_first], | |
| 1201 Matcher::regName[src_first]); | |
| 1202 #endif | |
| 1203 } | |
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1204 return 0; |
| 0 | 1205 } |
| 1206 } else if (dst_first_rc == rc_float) { | |
| 1207 // gpr -> xmm | |
| 1208 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1209 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1210 // 64-bit | |
| 1211 if (cbuf) { | |
| 4759 | 1212 MacroAssembler _masm(cbuf); |
| 1213 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); | |
| 0 | 1214 #ifndef PRODUCT |
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1215 } else { |
| 0 | 1216 st->print("movdq %s, %s\t# spill", |
| 1217 Matcher::regName[dst_first], | |
| 1218 Matcher::regName[src_first]); | |
| 1219 #endif | |
| 1220 } | |
| 1221 } else { | |
| 1222 // 32-bit | |
| 1223 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1224 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1225 if (cbuf) { | |
| 4759 | 1226 MacroAssembler _masm(cbuf); |
| 1227 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); | |
| 0 | 1228 #ifndef PRODUCT |
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1229 } else { |
| 0 | 1230 st->print("movdl %s, %s\t# spill", |
| 1231 Matcher::regName[dst_first], | |
| 1232 Matcher::regName[src_first]); | |
| 1233 #endif | |
| 1234 } | |
| 1235 } | |
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1236 return 0; |
| 0 | 1237 } |
| 1238 } else if (src_first_rc == rc_float) { | |
| 1239 // xmm -> | |
| 1240 if (dst_first_rc == rc_stack) { | |
| 1241 // xmm -> mem | |
| 1242 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1243 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1244 // 64-bit | |
| 1245 int offset = ra_->reg2offset(dst_first); | |
| 1246 if (cbuf) { | |
| 4759 | 1247 MacroAssembler _masm(cbuf); |
| 1248 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1249 #ifndef PRODUCT |
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1250 } else { |
| 0 | 1251 st->print("movsd [rsp + #%d], %s\t# spill", |
| 1252 offset, | |
| 1253 Matcher::regName[src_first]); | |
| 1254 #endif | |
| 1255 } | |
| 1256 } else { | |
| 1257 // 32-bit | |
| 1258 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1259 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1260 int offset = ra_->reg2offset(dst_first); | |
| 1261 if (cbuf) { | |
| 4759 | 1262 MacroAssembler _masm(cbuf); |
| 1263 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1264 #ifndef PRODUCT |
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1265 } else { |
| 0 | 1266 st->print("movss [rsp + #%d], %s\t# spill", |
| 1267 offset, | |
| 1268 Matcher::regName[src_first]); | |
| 1269 #endif | |
| 1270 } | |
| 1271 } | |
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1272 return 0; |
| 0 | 1273 } else if (dst_first_rc == rc_int) { |
| 1274 // xmm -> gpr | |
| 1275 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1276 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1277 // 64-bit | |
| 1278 if (cbuf) { | |
| 4759 | 1279 MacroAssembler _masm(cbuf); |
| 1280 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1281 #ifndef PRODUCT |
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1282 } else { |
| 0 | 1283 st->print("movdq %s, %s\t# spill", |
| 1284 Matcher::regName[dst_first], | |
| 1285 Matcher::regName[src_first]); | |
| 1286 #endif | |
| 1287 } | |
| 1288 } else { | |
| 1289 // 32-bit | |
| 1290 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1291 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1292 if (cbuf) { | |
| 4759 | 1293 MacroAssembler _masm(cbuf); |
| 1294 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1295 #ifndef PRODUCT |
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1296 } else { |
| 0 | 1297 st->print("movdl %s, %s\t# spill", |
| 1298 Matcher::regName[dst_first], | |
| 1299 Matcher::regName[src_first]); | |
| 1300 #endif | |
| 1301 } | |
| 1302 } | |
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1303 return 0; |
| 0 | 1304 } else if (dst_first_rc == rc_float) { |
| 1305 // xmm -> xmm | |
| 1306 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1307 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1308 // 64-bit | |
| 1309 if (cbuf) { | |
| 4759 | 1310 MacroAssembler _masm(cbuf); |
| 1311 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1312 #ifndef PRODUCT |
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1313 } else { |
| 0 | 1314 st->print("%s %s, %s\t# spill", |
| 1315 UseXmmRegToRegMoveAll ? "movapd" : "movsd ", | |
| 1316 Matcher::regName[dst_first], | |
| 1317 Matcher::regName[src_first]); | |
| 1318 #endif | |
| 1319 } | |
| 1320 } else { | |
| 1321 // 32-bit | |
| 1322 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1323 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1324 if (cbuf) { | |
| 4759 | 1325 MacroAssembler _masm(cbuf); |
| 1326 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1327 #ifndef PRODUCT |
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1328 } else { |
| 0 | 1329 st->print("%s %s, %s\t# spill", |
| 1330 UseXmmRegToRegMoveAll ? "movaps" : "movss ", | |
| 1331 Matcher::regName[dst_first], | |
| 1332 Matcher::regName[src_first]); | |
| 1333 #endif | |
| 1334 } | |
| 1335 } | |
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1336 return 0; |
| 0 | 1337 } |
| 1338 } | |
| 1339 | |
| 1340 assert(0," foo "); | |
| 1341 Unimplemented(); | |
| 1342 return 0; | |
| 1343 } | |
| 1344 | |
| 1345 #ifndef PRODUCT | |
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1346 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { |
| 0 | 1347 implementation(NULL, ra_, false, st); |
| 1348 } | |
| 1349 #endif | |
| 1350 | |
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1351 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
| 0 | 1352 implementation(&cbuf, ra_, false, NULL); |
| 1353 } | |
| 1354 | |
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1355 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { |
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1356 return MachNode::size(ra_); |
| 0 | 1357 } |
| 1358 | |
| 1359 //============================================================================= | |
| 1360 #ifndef PRODUCT | |
| 1361 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1362 { | |
| 1363 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1364 int reg = ra_->get_reg_first(this); | |
| 1365 st->print("leaq %s, [rsp + #%d]\t# box lock", | |
| 1366 Matcher::regName[reg], offset); | |
| 1367 } | |
| 1368 #endif | |
| 1369 | |
| 1370 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1371 { | |
| 1372 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1373 int reg = ra_->get_encode(this); | |
| 1374 if (offset >= 0x80) { | |
| 1375 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1376 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1377 emit_rm(cbuf, 0x2, reg & 7, 0x04); | |
| 1378 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1379 emit_d32(cbuf, offset); | |
| 1380 } else { | |
| 1381 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1382 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1383 emit_rm(cbuf, 0x1, reg & 7, 0x04); | |
| 1384 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1385 emit_d8(cbuf, offset); | |
| 1386 } | |
| 1387 } | |
| 1388 | |
| 1389 uint BoxLockNode::size(PhaseRegAlloc *ra_) const | |
| 1390 { | |
| 1391 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1392 return (offset < 0x80) ? 5 : 8; // REX | |
| 1393 } | |
| 1394 | |
| 1395 //============================================================================= | |
| 1396 #ifndef PRODUCT | |
| 1397 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1398 { | |
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1399 if (UseCompressedClassPointers) { |
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1400 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass"); |
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1401 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1"); |
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1402 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check"); |
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1403 } else { |
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1404 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t" |
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1405 "# Inline cache check"); |
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1406 } |
| 0 | 1407 st->print_cr("\tjne SharedRuntime::_ic_miss_stub"); |
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1408 st->print_cr("\tnop\t# nops to align entry point"); |
| 0 | 1409 } |
| 1410 #endif | |
| 1411 | |
| 1412 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1413 { | |
| 1414 MacroAssembler masm(&cbuf); | |
| 1748 | 1415 uint insts_size = cbuf.insts_size(); |
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1416 if (UseCompressedClassPointers) { |
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1417 masm.load_klass(rscratch1, j_rarg0); |
| 304 | 1418 masm.cmpptr(rax, rscratch1); |
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1419 } else { |
| 304 | 1420 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes())); |
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1421 } |
| 0 | 1422 |
| 1423 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1424 | |
| 1425 /* WARNING these NOPs are critical so that verified entry point is properly | |
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1426 4 bytes aligned for patching by NativeJump::patch_verified_entry() */ |
| 1748 | 1427 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3); |
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1428 if (OptoBreakpoint) { |
| 0 | 1429 // Leave space for int3 |
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1430 nops_cnt -= 1; |
| 0 | 1431 } |
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1432 nops_cnt &= 0x3; // Do not add nops if code is aligned. |
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1433 if (nops_cnt > 0) |
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1434 masm.nop(nops_cnt); |
| 0 | 1435 } |
| 1436 | |
| 1437 uint MachUEPNode::size(PhaseRegAlloc* ra_) const | |
| 1438 { | |
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1439 return MachNode::size(ra_); // too many variables; just compute it |
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1440 // the hard way |
| 0 | 1441 } |
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1442 |
| 0 | 1443 |
| 1444 //============================================================================= | |
| 1445 | |
| 1446 int Matcher::regnum_to_fpu_offset(int regnum) | |
| 1447 { | |
| 1448 return regnum - 32; // The FP registers are in the second chunk | |
| 1449 } | |
| 1450 | |
| 1451 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1452 const bool Matcher::convL2FSupported(void) { | |
| 1453 return true; | |
| 1454 } | |
| 1455 | |
| 1456 // Is this branch offset short enough that a short branch can be used? | |
| 1457 // | |
| 1458 // NOTE: If the platform does not provide any short branch variants, then | |
| 1459 // this method should return false for offset 0. | |
| 3851 | 1460 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1461 // The passed offset is relative to address of the branch. | |
| 1462 // On 86 a branch displacement is calculated relative to address | |
| 1463 // of a next instruction. | |
| 1464 offset -= br_size; | |
| 1465 | |
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1466 // the short version of jmpConUCF2 contains multiple branches, |
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1467 // making the reach slightly less |
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1468 if (rule == jmpConUCF2_rule) |
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1469 return (-126 <= offset && offset <= 125); |
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|
1470 return (-128 <= offset && offset <= 127); |
| 0 | 1471 } |
| 1472 | |
| 1473 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1474 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1475 //return value == (int) value; // Cf. storeImmL and immL32. | |
| 1476 | |
| 1477 // Probably always true, even if a temp register is required. | |
| 1478 return true; | |
| 1479 } | |
| 1480 | |
| 1481 // The ecx parameter to rep stosq for the ClearArray node is in words. | |
| 1482 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1483 | |
| 1484 // Threshold size for cleararray. | |
| 1485 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1486 | |
| 4047 | 1487 // No additional cost for CMOVL. |
| 1488 const int Matcher::long_cmove_cost() { return 0; } | |
| 1489 | |
| 1490 // No CMOVF/CMOVD with SSE2 | |
| 1491 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } | |
| 1492 | |
|
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1493 // Does the CPU require late expand (see block.cpp for description of late expand)? |
|
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|
1494 const bool Matcher::require_postalloc_expand = false; |
|
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|
1495 |
| 0 | 1496 // Should the Matcher clone shifts on addressing modes, expecting them |
| 1497 // to be subsumed into complex addressing expressions or compute them | |
| 1498 // into registers? True for Intel but false for most RISCs | |
| 1499 const bool Matcher::clone_shift_expressions = true; | |
| 1500 | |
|
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|
1501 // Do we need to mask the count passed to shift instructions or does |
|
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|
1502 // the cpu only look at the lower 5/6 bits anyway? |
|
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|
1503 const bool Matcher::need_masked_shift_count = false; |
|
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|
1504 |
|
1575
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|
1505 bool Matcher::narrow_oop_use_complex_address() { |
|
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|
1506 assert(UseCompressedOops, "only for compressed oops code"); |
|
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|
1507 return (LogMinObjAlignmentInBytes <= 3); |
|
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|
1508 } |
|
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|
1509 |
|
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|
1510 bool Matcher::narrow_klass_use_complex_address() { |
|
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1511 assert(UseCompressedClassPointers, "only for compressed klass code"); |
|
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|
1512 return (LogKlassAlignmentInBytes <= 3); |
|
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|
1513 } |
|
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|
1514 |
| 0 | 1515 // Is it better to copy float constants, or load them directly from |
| 1516 // memory? Intel can load a float constant from a direct address, | |
| 1517 // requiring no extra registers. Most RISCs will have to materialize | |
| 1518 // an address into a register first, so they would do better to copy | |
| 1519 // the constant from stack. | |
| 1520 const bool Matcher::rematerialize_float_constants = true; // XXX | |
| 1521 | |
| 1522 // If CPU can load and store mis-aligned doubles directly then no | |
| 1523 // fixup is needed. Else we split the double into 2 integer pieces | |
| 1524 // and move it piece-by-piece. Only happens when passing doubles into | |
| 1525 // C code as the Java calling convention forces doubles to be aligned. | |
| 1526 const bool Matcher::misaligned_doubles_ok = true; | |
| 1527 | |
| 1528 // No-op on amd64 | |
| 1529 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {} | |
| 1530 | |
| 1531 // Advertise here if the CPU requires explicit rounding operations to | |
| 1532 // implement the UseStrictFP mode. | |
| 1533 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1534 | |
|
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|
1535 // Are floats conerted to double when stored to stack during deoptimization? |
|
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|
1536 // On x64 it is stored without convertion so we can use normal access. |
|
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|
1537 bool Matcher::float_in_double() { return false; } |
|
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|
1538 |
| 0 | 1539 // Do ints take an entire long register or just half? |
| 1540 const bool Matcher::int_in_long = true; | |
| 1541 | |
| 1542 // Return whether or not this register is ever used as an argument. | |
| 1543 // This function is used on startup to build the trampoline stubs in | |
| 1544 // generateOptoStub. Registers not mentioned will be killed by the VM | |
| 1545 // call in the trampoline, and arguments in those registers not be | |
| 1546 // available to the callee. | |
| 1547 bool Matcher::can_be_java_arg(int reg) | |
| 1548 { | |
| 1549 return | |
|
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1550 reg == RDI_num || reg == RDI_H_num || |
|
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|
1551 reg == RSI_num || reg == RSI_H_num || |
|
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|
1552 reg == RDX_num || reg == RDX_H_num || |
|
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|
1553 reg == RCX_num || reg == RCX_H_num || |
|
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|
1554 reg == R8_num || reg == R8_H_num || |
|
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|
1555 reg == R9_num || reg == R9_H_num || |
|
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|
1556 reg == R12_num || reg == R12_H_num || |
|
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|
1557 reg == XMM0_num || reg == XMM0b_num || |
|
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|
1558 reg == XMM1_num || reg == XMM1b_num || |
|
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|
1559 reg == XMM2_num || reg == XMM2b_num || |
|
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|
1560 reg == XMM3_num || reg == XMM3b_num || |
|
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|
1561 reg == XMM4_num || reg == XMM4b_num || |
|
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|
1562 reg == XMM5_num || reg == XMM5b_num || |
|
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|
1563 reg == XMM6_num || reg == XMM6b_num || |
|
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|
1564 reg == XMM7_num || reg == XMM7b_num; |
| 0 | 1565 } |
| 1566 | |
| 1567 bool Matcher::is_spillable_arg(int reg) | |
| 1568 { | |
| 1569 return can_be_java_arg(reg); | |
| 1570 } | |
| 1571 | |
|
1914
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|
1572 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
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|
1573 // In 64 bit mode a code which use multiply when |
|
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|
1574 // devisor is constant is faster than hardware |
|
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|
1575 // DIV instruction (it uses MulHiL). |
|
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|
1576 return false; |
|
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|
1577 } |
|
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|
1578 |
| 0 | 1579 // Register for DIVI projection of divmodI |
| 1580 RegMask Matcher::divI_proj_mask() { | |
|
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|
1581 return INT_RAX_REG_mask(); |
| 0 | 1582 } |
| 1583 | |
| 1584 // Register for MODI projection of divmodI | |
| 1585 RegMask Matcher::modI_proj_mask() { | |
|
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|
1586 return INT_RDX_REG_mask(); |
| 0 | 1587 } |
| 1588 | |
| 1589 // Register for DIVL projection of divmodL | |
| 1590 RegMask Matcher::divL_proj_mask() { | |
|
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|
1591 return LONG_RAX_REG_mask(); |
| 0 | 1592 } |
| 1593 | |
| 1594 // Register for MODL projection of divmodL | |
| 1595 RegMask Matcher::modL_proj_mask() { | |
|
4121
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|
1596 return LONG_RDX_REG_mask(); |
| 0 | 1597 } |
| 1598 | |
|
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|
1599 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
4121
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|
1600 return PTR_RBP_REG_mask(); |
|
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|
1601 } |
|
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|
1602 |
| 12323 | 1603 const RegMask Matcher::mathExactI_result_proj_mask() { |
| 1604 return INT_RAX_REG_mask(); | |
| 1605 } | |
| 1606 | |
|
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|
1607 const RegMask Matcher::mathExactL_result_proj_mask() { |
|
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|
1608 return LONG_RAX_REG_mask(); |
|
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|
1609 } |
|
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|
1610 |
| 12323 | 1611 const RegMask Matcher::mathExactI_flags_proj_mask() { |
| 1612 return INT_FLAGS_mask(); | |
| 1613 } | |
| 1614 | |
| 0 | 1615 %} |
| 1616 | |
| 1617 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1618 // This block specifies the encoding classes used by the compiler to | |
| 1619 // output byte streams. Encoding classes are parameterized macros | |
| 1620 // used by Machine Instruction Nodes in order to generate the bit | |
| 1621 // encoding of the instruction. Operands specify their base encoding | |
| 1622 // interface with the interface keyword. There are currently | |
| 1623 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, & | |
| 1624 // COND_INTER. REG_INTER causes an operand to generate a function | |
| 1625 // which returns its register number when queried. CONST_INTER causes | |
| 1626 // an operand to generate a function which returns the value of the | |
| 1627 // constant when queried. MEMORY_INTER causes an operand to generate | |
| 1628 // four functions which return the Base Register, the Index Register, | |
| 1629 // the Scale Value, and the Offset Value of the operand when queried. | |
| 1630 // COND_INTER causes an operand to generate six functions which return | |
| 1631 // the encoding code (ie - encoding bits for the instruction) | |
| 1632 // associated with each basic boolean condition for a conditional | |
| 1633 // instruction. | |
| 1634 // | |
| 1635 // Instructions specify two basic values for encoding. Again, a | |
| 1636 // function is available to check if the constant displacement is an | |
| 1637 // oop. They use the ins_encode keyword to specify their encoding | |
| 1638 // classes (which must be a sequence of enc_class names, and their | |
| 1639 // parameters, specified in the encoding block), and they use the | |
| 1640 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1641 // tertiary opcode. Only the opcode sections which a particular | |
| 1642 // instruction needs for encoding need to be specified. | |
| 1643 encode %{ | |
| 1644 // Build emit functions for each basic byte or larger field in the | |
| 1645 // intel encoding scheme (opcode, rm, sib, immediate), and call them | |
| 1646 // from C++ code in the enc_class source block. Emit functions will | |
| 1647 // live in the main source block for now. In future, we can | |
| 1648 // generalize this by adding a syntax that specifies the sizes of | |
| 1649 // fields in an order, so that the adlc can build the emit functions | |
| 1650 // automagically | |
| 1651 | |
| 1652 // Emit primary opcode | |
| 1653 enc_class OpcP | |
| 1654 %{ | |
| 1655 emit_opcode(cbuf, $primary); | |
| 1656 %} | |
| 1657 | |
| 1658 // Emit secondary opcode | |
| 1659 enc_class OpcS | |
| 1660 %{ | |
| 1661 emit_opcode(cbuf, $secondary); | |
| 1662 %} | |
| 1663 | |
| 1664 // Emit tertiary opcode | |
| 1665 enc_class OpcT | |
| 1666 %{ | |
| 1667 emit_opcode(cbuf, $tertiary); | |
| 1668 %} | |
| 1669 | |
| 1670 // Emit opcode directly | |
| 1671 enc_class Opcode(immI d8) | |
| 1672 %{ | |
| 1673 emit_opcode(cbuf, $d8$$constant); | |
| 1674 %} | |
| 1675 | |
| 1676 // Emit size prefix | |
| 1677 enc_class SizePrefix | |
| 1678 %{ | |
| 1679 emit_opcode(cbuf, 0x66); | |
| 1680 %} | |
| 1681 | |
| 1682 enc_class reg(rRegI reg) | |
| 1683 %{ | |
| 1684 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7); | |
| 1685 %} | |
| 1686 | |
| 1687 enc_class reg_reg(rRegI dst, rRegI src) | |
| 1688 %{ | |
| 1689 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 1690 %} | |
| 1691 | |
| 1692 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src) | |
| 1693 %{ | |
| 1694 emit_opcode(cbuf, $opcode$$constant); | |
| 1695 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 1696 %} | |
| 1697 | |
| 1698 enc_class cdql_enc(no_rax_rdx_RegI div) | |
| 1699 %{ | |
| 1700 // Full implementation of Java idiv and irem; checks for | |
| 1701 // special case as described in JVM spec., p.243 & p.271. | |
| 1702 // | |
| 1703 // normal case special case | |
| 1704 // | |
| 1705 // input : rax: dividend min_int | |
| 1706 // reg: divisor -1 | |
| 1707 // | |
| 1708 // output: rax: quotient (= rax idiv reg) min_int | |
| 1709 // rdx: remainder (= rax irem reg) 0 | |
| 1710 // | |
| 1711 // Code sequnce: | |
| 1712 // | |
| 1713 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax | |
| 1714 // 5: 75 07/08 jne e <normal> | |
| 1715 // 7: 33 d2 xor %edx,%edx | |
| 1716 // [div >= 8 -> offset + 1] | |
| 1717 // [REX_B] | |
| 1718 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 1719 // c: 74 03/04 je 11 <done> | |
| 1720 // 000000000000000e <normal>: | |
| 1721 // e: 99 cltd | |
| 1722 // [div >= 8 -> offset + 1] | |
| 1723 // [REX_B] | |
| 1724 // f: f7 f9 idiv $div | |
| 1725 // 0000000000000011 <done>: | |
| 1726 | |
| 1727 // cmp $0x80000000,%eax | |
| 1728 emit_opcode(cbuf, 0x3d); | |
| 1729 emit_d8(cbuf, 0x00); | |
| 1730 emit_d8(cbuf, 0x00); | |
| 1731 emit_d8(cbuf, 0x00); | |
| 1732 emit_d8(cbuf, 0x80); | |
| 1733 | |
| 1734 // jne e <normal> | |
| 1735 emit_opcode(cbuf, 0x75); | |
| 1736 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08); | |
| 1737 | |
| 1738 // xor %edx,%edx | |
| 1739 emit_opcode(cbuf, 0x33); | |
| 1740 emit_d8(cbuf, 0xD2); | |
| 1741 | |
| 1742 // cmp $0xffffffffffffffff,%ecx | |
| 1743 if ($div$$reg >= 8) { | |
| 1744 emit_opcode(cbuf, Assembler::REX_B); | |
| 1745 } | |
| 1746 emit_opcode(cbuf, 0x83); | |
| 1747 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 1748 emit_d8(cbuf, 0xFF); | |
| 1749 | |
| 1750 // je 11 <done> | |
| 1751 emit_opcode(cbuf, 0x74); | |
| 1752 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04); | |
| 1753 | |
| 1754 // <normal> | |
| 1755 // cltd | |
| 1756 emit_opcode(cbuf, 0x99); | |
| 1757 | |
| 1758 // idivl (note: must be emitted by the user of this rule) | |
| 1759 // <done> | |
| 1760 %} | |
| 1761 | |
| 1762 enc_class cdqq_enc(no_rax_rdx_RegL div) | |
| 1763 %{ | |
| 1764 // Full implementation of Java ldiv and lrem; checks for | |
| 1765 // special case as described in JVM spec., p.243 & p.271. | |
| 1766 // | |
| 1767 // normal case special case | |
| 1768 // | |
| 1769 // input : rax: dividend min_long | |
| 1770 // reg: divisor -1 | |
| 1771 // | |
| 1772 // output: rax: quotient (= rax idiv reg) min_long | |
| 1773 // rdx: remainder (= rax irem reg) 0 | |
| 1774 // | |
| 1775 // Code sequnce: | |
| 1776 // | |
| 1777 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx | |
| 1778 // 7: 00 00 80 | |
| 1779 // a: 48 39 d0 cmp %rdx,%rax | |
| 1780 // d: 75 08 jne 17 <normal> | |
| 1781 // f: 33 d2 xor %edx,%edx | |
| 1782 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 1783 // 15: 74 05 je 1c <done> | |
| 1784 // 0000000000000017 <normal>: | |
| 1785 // 17: 48 99 cqto | |
| 1786 // 19: 48 f7 f9 idiv $div | |
| 1787 // 000000000000001c <done>: | |
| 1788 | |
| 1789 // mov $0x8000000000000000,%rdx | |
| 1790 emit_opcode(cbuf, Assembler::REX_W); | |
| 1791 emit_opcode(cbuf, 0xBA); | |
| 1792 emit_d8(cbuf, 0x00); | |
| 1793 emit_d8(cbuf, 0x00); | |
| 1794 emit_d8(cbuf, 0x00); | |
| 1795 emit_d8(cbuf, 0x00); | |
| 1796 emit_d8(cbuf, 0x00); | |
| 1797 emit_d8(cbuf, 0x00); | |
| 1798 emit_d8(cbuf, 0x00); | |
| 1799 emit_d8(cbuf, 0x80); | |
| 1800 | |
| 1801 // cmp %rdx,%rax | |
| 1802 emit_opcode(cbuf, Assembler::REX_W); | |
| 1803 emit_opcode(cbuf, 0x39); | |
| 1804 emit_d8(cbuf, 0xD0); | |
| 1805 | |
| 1806 // jne 17 <normal> | |
| 1807 emit_opcode(cbuf, 0x75); | |
| 1808 emit_d8(cbuf, 0x08); | |
| 1809 | |
| 1810 // xor %edx,%edx | |
| 1811 emit_opcode(cbuf, 0x33); | |
| 1812 emit_d8(cbuf, 0xD2); | |
| 1813 | |
| 1814 // cmp $0xffffffffffffffff,$div | |
| 1815 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB); | |
| 1816 emit_opcode(cbuf, 0x83); | |
| 1817 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 1818 emit_d8(cbuf, 0xFF); | |
| 1819 | |
| 1820 // je 1e <done> | |
| 1821 emit_opcode(cbuf, 0x74); | |
| 1822 emit_d8(cbuf, 0x05); | |
| 1823 | |
| 1824 // <normal> | |
| 1825 // cqto | |
| 1826 emit_opcode(cbuf, Assembler::REX_W); | |
| 1827 emit_opcode(cbuf, 0x99); | |
| 1828 | |
| 1829 // idivq (note: must be emitted by the user of this rule) | |
| 1830 // <done> | |
| 1831 %} | |
| 1832 | |
| 1833 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1834 enc_class OpcSE(immI imm) | |
| 1835 %{ | |
| 1836 // Emit primary opcode and set sign-extend bit | |
| 1837 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1838 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1839 emit_opcode(cbuf, $primary | 0x02); | |
| 1840 } else { | |
| 1841 // 32-bit immediate | |
| 1842 emit_opcode(cbuf, $primary); | |
| 1843 } | |
| 1844 %} | |
| 1845 | |
| 1846 enc_class OpcSErm(rRegI dst, immI imm) | |
| 1847 %{ | |
| 1848 // OpcSEr/m | |
| 1849 int dstenc = $dst$$reg; | |
| 1850 if (dstenc >= 8) { | |
| 1851 emit_opcode(cbuf, Assembler::REX_B); | |
| 1852 dstenc -= 8; | |
| 1853 } | |
| 1854 // Emit primary opcode and set sign-extend bit | |
| 1855 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1856 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1857 emit_opcode(cbuf, $primary | 0x02); | |
| 1858 } else { | |
| 1859 // 32-bit immediate | |
| 1860 emit_opcode(cbuf, $primary); | |
| 1861 } | |
| 1862 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1863 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 1864 %} | |
| 1865 | |
| 1866 enc_class OpcSErm_wide(rRegL dst, immI imm) | |
| 1867 %{ | |
| 1868 // OpcSEr/m | |
| 1869 int dstenc = $dst$$reg; | |
| 1870 if (dstenc < 8) { | |
| 1871 emit_opcode(cbuf, Assembler::REX_W); | |
| 1872 } else { | |
| 1873 emit_opcode(cbuf, Assembler::REX_WB); | |
| 1874 dstenc -= 8; | |
| 1875 } | |
| 1876 // Emit primary opcode and set sign-extend bit | |
| 1877 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1878 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1879 emit_opcode(cbuf, $primary | 0x02); | |
| 1880 } else { | |
| 1881 // 32-bit immediate | |
| 1882 emit_opcode(cbuf, $primary); | |
| 1883 } | |
| 1884 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1885 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 1886 %} | |
| 1887 | |
| 1888 enc_class Con8or32(immI imm) | |
| 1889 %{ | |
| 1890 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1891 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1892 $$$emit8$imm$$constant; | |
| 1893 } else { | |
| 1894 // 32-bit immediate | |
| 1895 $$$emit32$imm$$constant; | |
| 1896 } | |
| 1897 %} | |
| 1898 | |
| 1899 enc_class opc2_reg(rRegI dst) | |
| 1900 %{ | |
| 1901 // BSWAP | |
| 1902 emit_cc(cbuf, $secondary, $dst$$reg); | |
| 1903 %} | |
| 1904 | |
| 1905 enc_class opc3_reg(rRegI dst) | |
| 1906 %{ | |
| 1907 // BSWAP | |
| 1908 emit_cc(cbuf, $tertiary, $dst$$reg); | |
| 1909 %} | |
| 1910 | |
| 1911 enc_class reg_opc(rRegI div) | |
| 1912 %{ | |
| 1913 // INC, DEC, IDIV, IMOD, JMP indirect, ... | |
| 1914 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7); | |
| 1915 %} | |
| 1916 | |
| 1917 enc_class enc_cmov(cmpOp cop) | |
| 1918 %{ | |
| 1919 // CMOV | |
| 1920 $$$emit8$primary; | |
| 1921 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1922 %} | |
| 1923 | |
| 1924 enc_class enc_PartialSubtypeCheck() | |
| 1925 %{ | |
| 1926 Register Rrdi = as_Register(RDI_enc); // result register | |
| 1927 Register Rrax = as_Register(RAX_enc); // super class | |
| 1928 Register Rrcx = as_Register(RCX_enc); // killed | |
| 1929 Register Rrsi = as_Register(RSI_enc); // sub class | |
|
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1930 Label miss; |
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1931 const bool set_cond_codes = true; |
| 0 | 1932 |
| 1933 MacroAssembler _masm(&cbuf); | |
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1934 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi, |
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1935 NULL, &miss, |
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1936 /*set_cond_codes:*/ true); |
| 0 | 1937 if ($primary) { |
| 304 | 1938 __ xorptr(Rrdi, Rrdi); |
| 0 | 1939 } |
| 1940 __ bind(miss); | |
| 1941 %} | |
| 1942 | |
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1943 enc_class clear_avx %{ |
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1944 debug_only(int off0 = cbuf.insts_size()); |
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1945 if (ra_->C->max_vector_size() > 16) { |
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1946 // Clear upper bits of YMM registers when current compiled code uses |
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1947 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
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1948 MacroAssembler _masm(&cbuf); |
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1949 __ vzeroupper(); |
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1950 } |
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1951 debug_only(int off1 = cbuf.insts_size()); |
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1952 assert(off1 - off0 == clear_avx_size(), "correct size prediction"); |
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1953 %} |
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1954 |
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1955 enc_class Java_To_Runtime(method meth) %{ |
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1956 // No relocation needed |
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1957 MacroAssembler _masm(&cbuf); |
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1958 __ mov64(r10, (int64_t) $meth$$method); |
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1959 __ call(r10); |
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1960 %} |
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1961 |
| 0 | 1962 enc_class Java_To_Interpreter(method meth) |
| 1963 %{ | |
| 1964 // CALL Java_To_Interpreter | |
| 1965 // This is the instruction starting address for relocation info. | |
| 1748 | 1966 cbuf.set_insts_mark(); |
| 0 | 1967 $$$emit8$primary; |
| 1968 // CALL directly to the runtime | |
| 1969 emit_d32_reloc(cbuf, | |
| 1748 | 1970 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 1971 runtime_call_Relocation::spec(), |
| 1972 RELOC_DISP32); | |
| 1973 %} | |
| 1974 | |
| 1975 enc_class Java_Static_Call(method meth) | |
| 1976 %{ | |
| 1977 // JAVA STATIC CALL | |
| 1978 // CALL to fixup routine. Fixup routine uses ScopeDesc info to | |
| 1979 // determine who we intended to call. | |
| 1748 | 1980 cbuf.set_insts_mark(); |
| 0 | 1981 $$$emit8$primary; |
| 1982 | |
| 1983 if (!_method) { | |
| 1984 emit_d32_reloc(cbuf, | |
| 1748 | 1985 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 1986 runtime_call_Relocation::spec(), |
| 1987 RELOC_DISP32); | |
| 1988 } else if (_optimized_virtual) { | |
| 1989 emit_d32_reloc(cbuf, | |
| 1748 | 1990 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 1991 opt_virtual_call_Relocation::spec(), |
| 1992 RELOC_DISP32); | |
| 1993 } else { | |
| 1994 emit_d32_reloc(cbuf, | |
| 1748 | 1995 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 1996 static_call_Relocation::spec(), |
| 1997 RELOC_DISP32); | |
| 1998 } | |
| 1999 if (_method) { | |
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2000 // Emit stub for static call. |
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2001 CompiledStaticCall::emit_to_interp_stub(cbuf); |
| 0 | 2002 } |
| 2003 %} | |
| 2004 | |
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2005 enc_class Java_Dynamic_Call(method meth) %{ |
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2006 MacroAssembler _masm(&cbuf); |
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2007 __ ic_call((address)$meth$$method); |
| 0 | 2008 %} |
| 2009 | |
| 2010 enc_class Java_Compiled_Call(method meth) | |
| 2011 %{ | |
| 2012 // JAVA COMPILED CALL | |
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2013 int disp = in_bytes(Method:: from_compiled_offset()); |
| 0 | 2014 |
| 2015 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!! | |
| 2016 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small"); | |
| 2017 | |
| 2018 // callq *disp(%rax) | |
| 1748 | 2019 cbuf.set_insts_mark(); |
| 0 | 2020 $$$emit8$primary; |
| 2021 if (disp < 0x80) { | |
| 2022 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte | |
| 2023 emit_d8(cbuf, disp); // Displacement | |
| 2024 } else { | |
| 2025 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte | |
| 2026 emit_d32(cbuf, disp); // Displacement | |
| 2027 } | |
| 2028 %} | |
| 2029 | |
| 2030 enc_class reg_opc_imm(rRegI dst, immI8 shift) | |
| 2031 %{ | |
| 2032 // SAL, SAR, SHR | |
| 2033 int dstenc = $dst$$reg; | |
| 2034 if (dstenc >= 8) { | |
| 2035 emit_opcode(cbuf, Assembler::REX_B); | |
| 2036 dstenc -= 8; | |
| 2037 } | |
| 2038 $$$emit8$primary; | |
| 2039 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2040 $$$emit8$shift$$constant; | |
| 2041 %} | |
| 2042 | |
| 2043 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift) | |
| 2044 %{ | |
| 2045 // SAL, SAR, SHR | |
| 2046 int dstenc = $dst$$reg; | |
| 2047 if (dstenc < 8) { | |
| 2048 emit_opcode(cbuf, Assembler::REX_W); | |
| 2049 } else { | |
| 2050 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2051 dstenc -= 8; | |
| 2052 } | |
| 2053 $$$emit8$primary; | |
| 2054 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2055 $$$emit8$shift$$constant; | |
| 2056 %} | |
| 2057 | |
| 2058 enc_class load_immI(rRegI dst, immI src) | |
| 2059 %{ | |
| 2060 int dstenc = $dst$$reg; | |
| 2061 if (dstenc >= 8) { | |
| 2062 emit_opcode(cbuf, Assembler::REX_B); | |
| 2063 dstenc -= 8; | |
| 2064 } | |
| 2065 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2066 $$$emit32$src$$constant; | |
| 2067 %} | |
| 2068 | |
| 2069 enc_class load_immL(rRegL dst, immL src) | |
| 2070 %{ | |
| 2071 int dstenc = $dst$$reg; | |
| 2072 if (dstenc < 8) { | |
| 2073 emit_opcode(cbuf, Assembler::REX_W); | |
| 2074 } else { | |
| 2075 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2076 dstenc -= 8; | |
| 2077 } | |
| 2078 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2079 emit_d64(cbuf, $src$$constant); | |
| 2080 %} | |
| 2081 | |
| 2082 enc_class load_immUL32(rRegL dst, immUL32 src) | |
| 2083 %{ | |
| 2084 // same as load_immI, but this time we care about zeroes in the high word | |
| 2085 int dstenc = $dst$$reg; | |
| 2086 if (dstenc >= 8) { | |
| 2087 emit_opcode(cbuf, Assembler::REX_B); | |
| 2088 dstenc -= 8; | |
| 2089 } | |
| 2090 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2091 $$$emit32$src$$constant; | |
| 2092 %} | |
| 2093 | |
| 2094 enc_class load_immL32(rRegL dst, immL32 src) | |
| 2095 %{ | |
| 2096 int dstenc = $dst$$reg; | |
| 2097 if (dstenc < 8) { | |
| 2098 emit_opcode(cbuf, Assembler::REX_W); | |
| 2099 } else { | |
| 2100 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2101 dstenc -= 8; | |
| 2102 } | |
| 2103 emit_opcode(cbuf, 0xC7); | |
| 2104 emit_rm(cbuf, 0x03, 0x00, dstenc); | |
| 2105 $$$emit32$src$$constant; | |
| 2106 %} | |
| 2107 | |
| 2108 enc_class load_immP31(rRegP dst, immP32 src) | |
| 2109 %{ | |
| 2110 // same as load_immI, but this time we care about zeroes in the high word | |
| 2111 int dstenc = $dst$$reg; | |
| 2112 if (dstenc >= 8) { | |
| 2113 emit_opcode(cbuf, Assembler::REX_B); | |
| 2114 dstenc -= 8; | |
| 2115 } | |
| 2116 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2117 $$$emit32$src$$constant; | |
| 2118 %} | |
| 2119 | |
| 2120 enc_class load_immP(rRegP dst, immP src) | |
| 2121 %{ | |
| 2122 int dstenc = $dst$$reg; | |
| 2123 if (dstenc < 8) { | |
| 2124 emit_opcode(cbuf, Assembler::REX_W); | |
| 2125 } else { | |
| 2126 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2127 dstenc -= 8; | |
| 2128 } | |
| 2129 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2130 // This next line should be generated from ADLC | |
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2131 if ($src->constant_reloc() != relocInfo::none) { |
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2132 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64); |
| 0 | 2133 } else { |
| 2134 emit_d64(cbuf, $src$$constant); | |
| 2135 } | |
| 2136 %} | |
| 2137 | |
| 2138 enc_class Con32(immI src) | |
| 2139 %{ | |
| 2140 // Output immediate | |
| 2141 $$$emit32$src$$constant; | |
| 2142 %} | |
| 2143 | |
| 2144 enc_class Con32F_as_bits(immF src) | |
| 2145 %{ | |
| 2146 // Output Float immediate bits | |
| 2147 jfloat jf = $src$$constant; | |
| 2148 jint jf_as_bits = jint_cast(jf); | |
| 2149 emit_d32(cbuf, jf_as_bits); | |
| 2150 %} | |
| 2151 | |
| 2152 enc_class Con16(immI src) | |
| 2153 %{ | |
| 2154 // Output immediate | |
| 2155 $$$emit16$src$$constant; | |
| 2156 %} | |
| 2157 | |
| 2158 // How is this different from Con32??? XXX | |
| 2159 enc_class Con_d32(immI src) | |
| 2160 %{ | |
| 2161 emit_d32(cbuf,$src$$constant); | |
| 2162 %} | |
| 2163 | |
| 2164 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI) | |
| 2165 // Output immediate memory reference | |
| 2166 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2167 emit_d32(cbuf, 0x00); | |
| 2168 %} | |
| 2169 | |
| 2170 enc_class lock_prefix() | |
| 2171 %{ | |
| 2172 if (os::is_MP()) { | |
| 2173 emit_opcode(cbuf, 0xF0); // lock | |
| 2174 } | |
| 2175 %} | |
| 2176 | |
| 2177 enc_class REX_mem(memory mem) | |
| 2178 %{ | |
| 2179 if ($mem$$base >= 8) { | |
| 2180 if ($mem$$index < 8) { | |
| 2181 emit_opcode(cbuf, Assembler::REX_B); | |
| 2182 } else { | |
| 2183 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2184 } | |
| 2185 } else { | |
| 2186 if ($mem$$index >= 8) { | |
| 2187 emit_opcode(cbuf, Assembler::REX_X); | |
| 2188 } | |
| 2189 } | |
| 2190 %} | |
| 2191 | |
| 2192 enc_class REX_mem_wide(memory mem) | |
| 2193 %{ | |
| 2194 if ($mem$$base >= 8) { | |
| 2195 if ($mem$$index < 8) { | |
| 2196 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2197 } else { | |
| 2198 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 2199 } | |
| 2200 } else { | |
| 2201 if ($mem$$index < 8) { | |
| 2202 emit_opcode(cbuf, Assembler::REX_W); | |
| 2203 } else { | |
| 2204 emit_opcode(cbuf, Assembler::REX_WX); | |
| 2205 } | |
| 2206 } | |
| 2207 %} | |
| 2208 | |
| 2209 // for byte regs | |
| 2210 enc_class REX_breg(rRegI reg) | |
| 2211 %{ | |
| 2212 if ($reg$$reg >= 4) { | |
| 2213 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2214 } | |
| 2215 %} | |
| 2216 | |
| 2217 // for byte regs | |
| 2218 enc_class REX_reg_breg(rRegI dst, rRegI src) | |
| 2219 %{ | |
| 2220 if ($dst$$reg < 8) { | |
| 2221 if ($src$$reg >= 4) { | |
| 2222 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2223 } | |
| 2224 } else { | |
| 2225 if ($src$$reg < 8) { | |
| 2226 emit_opcode(cbuf, Assembler::REX_R); | |
| 2227 } else { | |
| 2228 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2229 } | |
| 2230 } | |
| 2231 %} | |
| 2232 | |
| 2233 // for byte regs | |
| 2234 enc_class REX_breg_mem(rRegI reg, memory mem) | |
| 2235 %{ | |
| 2236 if ($reg$$reg < 8) { | |
| 2237 if ($mem$$base < 8) { | |
| 2238 if ($mem$$index >= 8) { | |
| 2239 emit_opcode(cbuf, Assembler::REX_X); | |
| 2240 } else if ($reg$$reg >= 4) { | |
| 2241 emit_opcode(cbuf, Assembler::REX); | |
| 2242 } | |
| 2243 } else { | |
| 2244 if ($mem$$index < 8) { | |
| 2245 emit_opcode(cbuf, Assembler::REX_B); | |
| 2246 } else { | |
| 2247 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2248 } | |
| 2249 } | |
| 2250 } else { | |
| 2251 if ($mem$$base < 8) { | |
| 2252 if ($mem$$index < 8) { | |
| 2253 emit_opcode(cbuf, Assembler::REX_R); | |
| 2254 } else { | |
| 2255 emit_opcode(cbuf, Assembler::REX_RX); | |
| 2256 } | |
| 2257 } else { | |
| 2258 if ($mem$$index < 8) { | |
| 2259 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2260 } else { | |
| 2261 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 2262 } | |
| 2263 } | |
| 2264 } | |
| 2265 %} | |
| 2266 | |
| 2267 enc_class REX_reg(rRegI reg) | |
| 2268 %{ | |
| 2269 if ($reg$$reg >= 8) { | |
| 2270 emit_opcode(cbuf, Assembler::REX_B); | |
| 2271 } | |
| 2272 %} | |
| 2273 | |
| 2274 enc_class REX_reg_wide(rRegI reg) | |
| 2275 %{ | |
| 2276 if ($reg$$reg < 8) { | |
| 2277 emit_opcode(cbuf, Assembler::REX_W); | |
| 2278 } else { | |
| 2279 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2280 } | |
| 2281 %} | |
| 2282 | |
| 2283 enc_class REX_reg_reg(rRegI dst, rRegI src) | |
| 2284 %{ | |
| 2285 if ($dst$$reg < 8) { | |
| 2286 if ($src$$reg >= 8) { | |
| 2287 emit_opcode(cbuf, Assembler::REX_B); | |
| 2288 } | |
| 2289 } else { | |
| 2290 if ($src$$reg < 8) { | |
| 2291 emit_opcode(cbuf, Assembler::REX_R); | |
| 2292 } else { | |
| 2293 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2294 } | |
| 2295 } | |
| 2296 %} | |
| 2297 | |
| 2298 enc_class REX_reg_reg_wide(rRegI dst, rRegI src) | |
| 2299 %{ | |
| 2300 if ($dst$$reg < 8) { | |
| 2301 if ($src$$reg < 8) { | |
| 2302 emit_opcode(cbuf, Assembler::REX_W); | |
| 2303 } else { | |
| 2304 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2305 } | |
| 2306 } else { | |
| 2307 if ($src$$reg < 8) { | |
| 2308 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2309 } else { | |
| 2310 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2311 } | |
| 2312 } | |
| 2313 %} | |
| 2314 | |
| 2315 enc_class REX_reg_mem(rRegI reg, memory mem) | |
| 2316 %{ | |
| 2317 if ($reg$$reg < 8) { | |
| 2318 if ($mem$$base < 8) { | |
| 2319 if ($mem$$index >= 8) { | |
| 2320 emit_opcode(cbuf, Assembler::REX_X); | |
| 2321 } | |
| 2322 } else { | |
| 2323 if ($mem$$index < 8) { | |
| 2324 emit_opcode(cbuf, Assembler::REX_B); | |
| 2325 } else { | |
| 2326 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2327 } | |
| 2328 } | |
| 2329 } else { | |
| 2330 if ($mem$$base < 8) { | |
| 2331 if ($mem$$index < 8) { | |
| 2332 emit_opcode(cbuf, Assembler::REX_R); | |
| 2333 } else { | |
| 2334 emit_opcode(cbuf, Assembler::REX_RX); | |
| 2335 } | |
| 2336 } else { | |
| 2337 if ($mem$$index < 8) { | |
| 2338 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2339 } else { | |
| 2340 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 2341 } | |
| 2342 } | |
| 2343 } | |
| 2344 %} | |
| 2345 | |
| 2346 enc_class REX_reg_mem_wide(rRegL reg, memory mem) | |
| 2347 %{ | |
| 2348 if ($reg$$reg < 8) { | |
| 2349 if ($mem$$base < 8) { | |
| 2350 if ($mem$$index < 8) { | |
| 2351 emit_opcode(cbuf, Assembler::REX_W); | |
| 2352 } else { | |
| 2353 emit_opcode(cbuf, Assembler::REX_WX); | |
| 2354 } | |
| 2355 } else { | |
| 2356 if ($mem$$index < 8) { | |
| 2357 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2358 } else { | |
| 2359 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 2360 } | |
| 2361 } | |
| 2362 } else { | |
| 2363 if ($mem$$base < 8) { | |
| 2364 if ($mem$$index < 8) { | |
| 2365 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2366 } else { | |
| 2367 emit_opcode(cbuf, Assembler::REX_WRX); | |
| 2368 } | |
| 2369 } else { | |
| 2370 if ($mem$$index < 8) { | |
| 2371 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2372 } else { | |
| 2373 emit_opcode(cbuf, Assembler::REX_WRXB); | |
| 2374 } | |
| 2375 } | |
| 2376 } | |
| 2377 %} | |
| 2378 | |
| 2379 enc_class reg_mem(rRegI ereg, memory mem) | |
| 2380 %{ | |
| 2381 // High registers handle in encode_RegMem | |
| 2382 int reg = $ereg$$reg; | |
| 2383 int base = $mem$$base; | |
| 2384 int index = $mem$$index; | |
| 2385 int scale = $mem$$scale; | |
| 2386 int disp = $mem$$disp; | |
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2387 relocInfo::relocType disp_reloc = $mem->disp_reloc(); |
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2388 |
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2389 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc); |
| 0 | 2390 %} |
| 2391 | |
| 2392 enc_class RM_opc_mem(immI rm_opcode, memory mem) | |
| 2393 %{ | |
| 2394 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2395 | |
| 2396 // High registers handle in encode_RegMem | |
| 2397 int base = $mem$$base; | |
| 2398 int index = $mem$$index; | |
| 2399 int scale = $mem$$scale; | |
| 2400 int displace = $mem$$disp; | |
| 2401 | |
|
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2402 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when |
| 0 | 2403 // working with static |
| 2404 // globals | |
| 2405 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, | |
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2406 disp_reloc); |
| 0 | 2407 %} |
| 2408 | |
| 2409 enc_class reg_lea(rRegI dst, rRegI src0, immI src1) | |
| 2410 %{ | |
| 2411 int reg_encoding = $dst$$reg; | |
| 2412 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2413 int index = 0x04; // 0x04 indicates no index | |
| 2414 int scale = 0x00; // 0x00 indicates no scale | |
| 2415 int displace = $src1$$constant; // 0x00 indicates no displacement | |
|
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2416 relocInfo::relocType disp_reloc = relocInfo::none; |
| 0 | 2417 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, |
|
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2418 disp_reloc); |
| 0 | 2419 %} |
| 2420 | |
| 2421 enc_class neg_reg(rRegI dst) | |
| 2422 %{ | |
| 2423 int dstenc = $dst$$reg; | |
| 2424 if (dstenc >= 8) { | |
| 2425 emit_opcode(cbuf, Assembler::REX_B); | |
| 2426 dstenc -= 8; | |
| 2427 } | |
| 2428 // NEG $dst | |
| 2429 emit_opcode(cbuf, 0xF7); | |
| 2430 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 2431 %} | |
| 2432 | |
| 2433 enc_class neg_reg_wide(rRegI dst) | |
| 2434 %{ | |
| 2435 int dstenc = $dst$$reg; | |
| 2436 if (dstenc < 8) { | |
| 2437 emit_opcode(cbuf, Assembler::REX_W); | |
| 2438 } else { | |
| 2439 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2440 dstenc -= 8; | |
| 2441 } | |
| 2442 // NEG $dst | |
| 2443 emit_opcode(cbuf, 0xF7); | |
| 2444 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 2445 %} | |
| 2446 | |
| 2447 enc_class setLT_reg(rRegI dst) | |
| 2448 %{ | |
| 2449 int dstenc = $dst$$reg; | |
| 2450 if (dstenc >= 8) { | |
| 2451 emit_opcode(cbuf, Assembler::REX_B); | |
| 2452 dstenc -= 8; | |
| 2453 } else if (dstenc >= 4) { | |
| 2454 emit_opcode(cbuf, Assembler::REX); | |
| 2455 } | |
| 2456 // SETLT $dst | |
| 2457 emit_opcode(cbuf, 0x0F); | |
| 2458 emit_opcode(cbuf, 0x9C); | |
| 2459 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 2460 %} | |
| 2461 | |
| 2462 enc_class setNZ_reg(rRegI dst) | |
| 2463 %{ | |
| 2464 int dstenc = $dst$$reg; | |
| 2465 if (dstenc >= 8) { | |
| 2466 emit_opcode(cbuf, Assembler::REX_B); | |
| 2467 dstenc -= 8; | |
| 2468 } else if (dstenc >= 4) { | |
| 2469 emit_opcode(cbuf, Assembler::REX); | |
| 2470 } | |
| 2471 // SETNZ $dst | |
| 2472 emit_opcode(cbuf, 0x0F); | |
| 2473 emit_opcode(cbuf, 0x95); | |
| 2474 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 2475 %} | |
| 2476 | |
| 2477 | |
| 2478 // Compare the lonogs and set -1, 0, or 1 into dst | |
| 2479 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst) | |
| 2480 %{ | |
| 2481 int src1enc = $src1$$reg; | |
| 2482 int src2enc = $src2$$reg; | |
| 2483 int dstenc = $dst$$reg; | |
| 2484 | |
| 2485 // cmpq $src1, $src2 | |
| 2486 if (src1enc < 8) { | |
| 2487 if (src2enc < 8) { | |
| 2488 emit_opcode(cbuf, Assembler::REX_W); | |
| 2489 } else { | |
| 2490 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2491 } | |
| 2492 } else { | |
| 2493 if (src2enc < 8) { | |
| 2494 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2495 } else { | |
| 2496 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2497 } | |
| 2498 } | |
| 2499 emit_opcode(cbuf, 0x3B); | |
| 2500 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7); | |
| 2501 | |
| 2502 // movl $dst, -1 | |
| 2503 if (dstenc >= 8) { | |
| 2504 emit_opcode(cbuf, Assembler::REX_B); | |
| 2505 } | |
| 2506 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
| 2507 emit_d32(cbuf, -1); | |
| 2508 | |
| 2509 // jl,s done | |
| 2510 emit_opcode(cbuf, 0x7C); | |
| 2511 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
| 2512 | |
| 2513 // setne $dst | |
| 2514 if (dstenc >= 4) { | |
| 2515 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2516 } | |
| 2517 emit_opcode(cbuf, 0x0F); | |
| 2518 emit_opcode(cbuf, 0x95); | |
| 2519 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
| 2520 | |
| 2521 // movzbl $dst, $dst | |
| 2522 if (dstenc >= 4) { | |
| 2523 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
| 2524 } | |
| 2525 emit_opcode(cbuf, 0x0F); | |
| 2526 emit_opcode(cbuf, 0xB6); | |
| 2527 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
| 2528 %} | |
| 2529 | |
| 2530 enc_class Push_ResultXD(regD dst) %{ | |
| 4759 | 2531 MacroAssembler _masm(&cbuf); |
| 2532 __ fstp_d(Address(rsp, 0)); | |
| 2533 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); | |
| 2534 __ addptr(rsp, 8); | |
| 0 | 2535 %} |
| 2536 | |
| 2537 enc_class Push_SrcXD(regD src) %{ | |
| 2538 MacroAssembler _masm(&cbuf); | |
| 4759 | 2539 __ subptr(rsp, 8); |
| 2540 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2541 __ fld_d(Address(rsp, 0)); | |
| 2542 %} | |
| 2543 | |
| 0 | 2544 |
| 2545 // obj: object to lock | |
| 2546 // box: box address (header location) -- killed | |
| 2547 // tmp: rax -- killed | |
| 2548 // scr: rbx -- killed | |
| 2549 // | |
| 2550 // What follows is a direct transliteration of fast_lock() and fast_unlock() | |
| 2551 // from i486.ad. See that file for comments. | |
| 2552 // TODO: where possible switch from movq (r, 0) to movl(r,0) and | |
| 2553 // use the shorter encoding. (Movl clears the high-order 32-bits). | |
| 2554 | |
| 2555 | |
| 2556 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr) | |
| 2557 %{ | |
| 2558 Register objReg = as_Register((int)$obj$$reg); | |
| 2559 Register boxReg = as_Register((int)$box$$reg); | |
| 2560 Register tmpReg = as_Register($tmp$$reg); | |
| 2561 Register scrReg = as_Register($scr$$reg); | |
| 2562 MacroAssembler masm(&cbuf); | |
| 2563 | |
| 2564 // Verify uniqueness of register assignments -- necessary but not sufficient | |
| 2565 assert (objReg != boxReg && objReg != tmpReg && | |
| 2566 objReg != scrReg && tmpReg != scrReg, "invariant") ; | |
| 2567 | |
| 2568 if (_counters != NULL) { | |
| 2569 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); | |
| 2570 } | |
| 2571 if (EmitSync & 1) { | |
| 304 | 2572 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
|
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2573 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; |
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2574 masm.cmpptr(rsp, (int32_t)NULL_WORD) ; |
| 0 | 2575 } else |
| 2576 if (EmitSync & 2) { | |
| 2577 Label DONE_LABEL; | |
| 2578 if (UseBiasedLocking) { | |
| 2579 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. | |
| 2580 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); | |
| 2581 } | |
| 304 | 2582 // QQQ was movl... |
| 2583 masm.movptr(tmpReg, 0x1); | |
| 2584 masm.orptr(tmpReg, Address(objReg, 0)); | |
| 2585 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 2586 if (os::is_MP()) { |
| 2587 masm.lock(); | |
| 2588 } | |
| 304 | 2589 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 2590 masm.jcc(Assembler::equal, DONE_LABEL); |
| 2591 | |
| 2592 // Recursive locking | |
| 304 | 2593 masm.subptr(tmpReg, rsp); |
| 2594 masm.andptr(tmpReg, 7 - os::vm_page_size()); | |
| 2595 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 2596 |
| 2597 masm.bind(DONE_LABEL); | |
| 2598 masm.nop(); // avoid branch to branch | |
| 2599 } else { | |
| 2600 Label DONE_LABEL, IsInflated, Egress; | |
| 2601 | |
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2602 masm.movptr(tmpReg, Address(objReg, 0)) ; |
| 304 | 2603 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased |
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2604 masm.jcc (Assembler::notZero, IsInflated) ; |
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2605 |
| 0 | 2606 // it's stack-locked, biased or neutral |
| 2607 // TODO: optimize markword triage order to reduce the number of | |
| 2608 // conditional branches in the most common cases. | |
| 2609 // Beware -- there's a subtle invariant that fetch of the markword | |
| 2610 // at [FETCH], below, will never observe a biased encoding (*101b). | |
| 2611 // If this invariant is not held we'll suffer exclusion (safety) failure. | |
| 2612 | |
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2613 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 2614 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters); |
| 304 | 2615 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
| 0 | 2616 } |
| 2617 | |
| 304 | 2618 // was q will it destroy high? |
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2619 masm.orl (tmpReg, 1) ; |
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2620 masm.movptr(Address(boxReg, 0), tmpReg) ; |
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2621 if (os::is_MP()) { masm.lock(); } |
| 304 | 2622 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 2623 if (_counters != NULL) { |
| 2624 masm.cond_inc32(Assembler::equal, | |
| 2625 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
| 2626 } | |
| 2627 masm.jcc (Assembler::equal, DONE_LABEL); | |
| 2628 | |
| 2629 // Recursive locking | |
| 304 | 2630 masm.subptr(tmpReg, rsp); |
| 2631 masm.andptr(tmpReg, 7 - os::vm_page_size()); | |
| 2632 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 2633 if (_counters != NULL) { |
| 2634 masm.cond_inc32(Assembler::equal, | |
| 2635 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
| 2636 } | |
| 2637 masm.jmp (DONE_LABEL) ; | |
| 2638 | |
| 2639 masm.bind (IsInflated) ; | |
| 2640 // It's inflated | |
| 2641 | |
| 2642 // TODO: someday avoid the ST-before-CAS penalty by | |
| 2643 // relocating (deferring) the following ST. | |
| 2644 // We should also think about trying a CAS without having | |
| 2645 // fetched _owner. If the CAS is successful we may | |
| 2646 // avoid an RTO->RTS upgrade on the $line. | |
| 304 | 2647 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
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2648 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; |
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2649 |
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2650 masm.mov (boxReg, tmpReg) ; |
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2651 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
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2652 masm.testptr(tmpReg, tmpReg) ; |
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2653 masm.jcc (Assembler::notZero, DONE_LABEL) ; |
| 0 | 2654 |
| 2655 // It's inflated and appears unlocked | |
|
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2656 if (os::is_MP()) { masm.lock(); } |
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2657 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 0 | 2658 // Intentional fall-through into DONE_LABEL ... |
| 2659 | |
| 2660 masm.bind (DONE_LABEL) ; | |
| 2661 masm.nop () ; // avoid jmp to jmp | |
| 2662 } | |
| 2663 %} | |
| 2664 | |
| 2665 // obj: object to unlock | |
| 2666 // box: box address (displaced header location), killed | |
| 2667 // RBX: killed tmp; cannot be obj nor box | |
| 2668 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp) | |
| 2669 %{ | |
| 2670 | |
| 2671 Register objReg = as_Register($obj$$reg); | |
| 2672 Register boxReg = as_Register($box$$reg); | |
| 2673 Register tmpReg = as_Register($tmp$$reg); | |
| 2674 MacroAssembler masm(&cbuf); | |
| 2675 | |
|
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2676 if (EmitSync & 4) { |
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2677 masm.cmpptr(rsp, 0) ; |
| 0 | 2678 } else |
| 2679 if (EmitSync & 8) { | |
| 2680 Label DONE_LABEL; | |
| 2681 if (UseBiasedLocking) { | |
| 2682 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
| 2683 } | |
| 2684 | |
| 2685 // Check whether the displaced header is 0 | |
| 2686 //(=> recursive unlock) | |
| 304 | 2687 masm.movptr(tmpReg, Address(boxReg, 0)); |
| 2688 masm.testptr(tmpReg, tmpReg); | |
| 0 | 2689 masm.jcc(Assembler::zero, DONE_LABEL); |
| 2690 | |
| 2691 // If not recursive lock, reset the header to displaced header | |
| 2692 if (os::is_MP()) { | |
| 2693 masm.lock(); | |
| 2694 } | |
| 304 | 2695 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
| 0 | 2696 masm.bind(DONE_LABEL); |
| 2697 masm.nop(); // avoid branch to branch | |
| 2698 } else { | |
| 2699 Label DONE_LABEL, Stacked, CheckSucc ; | |
| 2700 | |
|
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2701 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 2702 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
| 2703 } | |
|
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2704 |
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2705 masm.movptr(tmpReg, Address(objReg, 0)) ; |
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2706 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ; |
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2707 masm.jcc (Assembler::zero, DONE_LABEL) ; |
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2708 masm.testl (tmpReg, 0x02) ; |
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2709 masm.jcc (Assembler::zero, Stacked) ; |
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2710 |
| 0 | 2711 // It's inflated |
|
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2712 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
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2713 masm.xorptr(boxReg, r15_thread) ; |
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2714 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; |
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2715 masm.jcc (Assembler::notZero, DONE_LABEL) ; |
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2716 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; |
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2717 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; |
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2718 masm.jcc (Assembler::notZero, CheckSucc) ; |
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2719 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
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2720 masm.jmp (DONE_LABEL) ; |
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2721 |
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2722 if ((EmitSync & 65536) == 0) { |
| 0 | 2723 Label LSuccess, LGoSlowPath ; |
| 2724 masm.bind (CheckSucc) ; | |
| 304 | 2725 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 2726 masm.jcc (Assembler::zero, LGoSlowPath) ; |
| 2727 | |
| 2728 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the | |
| 2729 // the explicit ST;MEMBAR combination, but masm doesn't currently support | |
| 2730 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc | |
| 2731 // are all faster when the write buffer is populated. | |
| 304 | 2732 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 2733 if (os::is_MP()) { |
| 304 | 2734 masm.lock () ; masm.addl (Address(rsp, 0), 0) ; |
| 0 | 2735 } |
| 304 | 2736 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 2737 masm.jcc (Assembler::notZero, LSuccess) ; |
| 2738 | |
| 304 | 2739 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX |
| 0 | 2740 if (os::is_MP()) { masm.lock(); } |
| 304 | 2741 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 2742 masm.jcc (Assembler::notEqual, LSuccess) ; |
| 2743 // Intentional fall-through into slow-path | |
| 2744 | |
| 2745 masm.bind (LGoSlowPath) ; | |
| 2746 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure | |
| 2747 masm.jmp (DONE_LABEL) ; | |
| 2748 | |
| 2749 masm.bind (LSuccess) ; | |
| 2750 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success | |
| 2751 masm.jmp (DONE_LABEL) ; | |
| 2752 } | |
| 2753 | |
|
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2754 masm.bind (Stacked) ; |
| 304 | 2755 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch |
|
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2756 if (os::is_MP()) { masm.lock(); } |
| 304 | 2757 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
| 0 | 2758 |
| 2759 if (EmitSync & 65536) { | |
| 2760 masm.bind (CheckSucc) ; | |
| 2761 } | |
| 2762 masm.bind(DONE_LABEL); | |
| 2763 if (EmitSync & 32768) { | |
| 2764 masm.nop(); // avoid branch to branch | |
| 2765 } | |
| 2766 } | |
| 2767 %} | |
| 2768 | |
|
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2769 |
| 0 | 2770 enc_class enc_rethrow() |
| 2771 %{ | |
| 1748 | 2772 cbuf.set_insts_mark(); |
| 0 | 2773 emit_opcode(cbuf, 0xE9); // jmp entry |
| 2774 emit_d32_reloc(cbuf, | |
| 1748 | 2775 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4), |
| 0 | 2776 runtime_call_Relocation::spec(), |
| 2777 RELOC_DISP32); | |
| 2778 %} | |
| 2779 | |
| 2780 %} | |
| 2781 | |
| 2782 | |
|
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2783 |
| 0 | 2784 //----------FRAME-------------------------------------------------------------- |
| 2785 // Definition of frame structure and management information. | |
| 2786 // | |
| 2787 // S T A C K L A Y O U T Allocators stack-slot number | |
| 2788 // | (to get allocators register number | |
| 2789 // G Owned by | | v add OptoReg::stack0()) | |
| 2790 // r CALLER | | | |
| 2791 // o | +--------+ pad to even-align allocators stack-slot | |
| 2792 // w V | pad0 | numbers; owned by CALLER | |
| 2793 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 2794 // h ^ | in | 5 | |
| 2795 // | | args | 4 Holes in incoming args owned by SELF | |
| 2796 // | | | | 3 | |
| 2797 // | | +--------+ | |
| 2798 // V | | old out| Empty on Intel, window on Sparc | |
| 2799 // | old |preserve| Must be even aligned. | |
| 2800 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 2801 // | | in | 3 area for Intel ret address | |
| 2802 // Owned by |preserve| Empty on Sparc. | |
| 2803 // SELF +--------+ | |
| 2804 // | | pad2 | 2 pad to align old SP | |
| 2805 // | +--------+ 1 | |
| 2806 // | | locks | 0 | |
| 2807 // | +--------+----> OptoReg::stack0(), even aligned | |
| 2808 // | | pad1 | 11 pad to align new SP | |
| 2809 // | +--------+ | |
| 2810 // | | | 10 | |
| 2811 // | | spills | 9 spills | |
| 2812 // V | | 8 (pad0 slot for callee) | |
| 2813 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 2814 // ^ | out | 7 | |
| 2815 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 2816 // Owned by +--------+ | |
| 2817 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 2818 // | new |preserve| Must be even-aligned. | |
| 2819 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 2820 // | | | | |
| 2821 // | |
| 2822 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 2823 // known from SELF's arguments and the Java calling convention. | |
| 2824 // Region 6-7 is determined per call site. | |
| 2825 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 2826 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 2827 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 2828 // incoming area, as the Java calling convention is completely under | |
| 2829 // the control of the AD file. Doubles can be sorted and packed to | |
| 2830 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 2831 // varargs C calling conventions. | |
| 2832 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 2833 // even aligned with pad0 as needed. | |
| 2834 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 2835 // region 6-11 is even aligned; it may be padded out more so that | |
| 2836 // the region from SP to FP meets the minimum stack alignment. | |
| 2837 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack | |
| 2838 // alignment. Region 11, pad1, may be dynamically extended so that | |
| 2839 // SP meets the minimum alignment. | |
| 2840 | |
| 2841 frame | |
| 2842 %{ | |
| 2843 // What direction does stack grow in (assumed to be same for C & Java) | |
| 2844 stack_direction(TOWARDS_LOW); | |
| 2845 | |
| 2846 // These three registers define part of the calling convention | |
| 2847 // between compiled code and the interpreter. | |
| 2848 inline_cache_reg(RAX); // Inline Cache Register | |
| 2849 interpreter_method_oop_reg(RBX); // Method Oop Register when | |
| 2850 // calling interpreter | |
| 2851 | |
| 2852 // Optional: name the operand used by cisc-spilling to access | |
| 2853 // [stack_pointer + offset] | |
| 2854 cisc_spilling_operand_name(indOffset32); | |
| 2855 | |
| 2856 // Number of stack slots consumed by locking an object | |
| 2857 sync_stack_slots(2); | |
| 2858 | |
| 2859 // Compiled code's Frame Pointer | |
| 2860 frame_pointer(RSP); | |
| 2861 | |
| 2862 // Interpreter stores its frame pointer in a register which is | |
| 2863 // stored to the stack by I2CAdaptors. | |
| 2864 // I2CAdaptors convert from interpreted java to compiled java. | |
| 2865 interpreter_frame_pointer(RBP); | |
| 2866 | |
| 2867 // Stack alignment requirement | |
| 2868 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes) | |
| 2869 | |
| 2870 // Number of stack slots between incoming argument block and the start of | |
| 2871 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 2872 // EPILOG must remove this many slots. amd64 needs two slots for | |
| 2873 // return address. | |
| 2874 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls); | |
| 2875 | |
| 2876 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 2877 // for calls to C. Supports the var-args backing area for register parms. | |
| 2878 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt); | |
| 2879 | |
| 2880 // The after-PROLOG location of the return address. Location of | |
| 2881 // return address specifies a type (REG or STACK) and a number | |
| 2882 // representing the register number (i.e. - use a register name) or | |
| 2883 // stack slot. | |
| 2884 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 2885 // Otherwise, it is above the locks and verification slot and alignment word | |
| 2886 return_addr(STACK - 2 + | |
| 4950 | 2887 round_to((Compile::current()->in_preserve_stack_slots() + |
| 2888 Compile::current()->fixed_slots()), | |
| 2889 stack_alignment_in_slots())); | |
| 0 | 2890 |
| 2891 // Body of function which returns an integer array locating | |
| 2892 // arguments either in registers or in stack slots. Passed an array | |
| 2893 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 2894 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 2895 // arguments for a CALLEE. Incoming stack arguments are | |
| 2896 // automatically biased by the preserve_stack_slots field above. | |
| 2897 | |
| 2898 calling_convention | |
| 2899 %{ | |
| 2900 // No difference between ingoing/outgoing just pass false | |
| 2901 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 2902 %} | |
| 2903 | |
| 2904 c_calling_convention | |
| 2905 %{ | |
| 2906 // This is obviously always outgoing | |
|
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2907 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); |
| 0 | 2908 %} |
| 2909 | |
| 2910 // Location of compiled Java return values. Same as C for now. | |
| 2911 return_value | |
| 2912 %{ | |
| 2913 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, | |
| 2914 "only return normal values"); | |
| 2915 | |
| 2916 static const int lo[Op_RegL + 1] = { | |
| 2917 0, | |
| 2918 0, | |
|
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2919 RAX_num, // Op_RegN |
| 0 | 2920 RAX_num, // Op_RegI |
| 2921 RAX_num, // Op_RegP | |
| 2922 XMM0_num, // Op_RegF | |
| 2923 XMM0_num, // Op_RegD | |
| 2924 RAX_num // Op_RegL | |
| 2925 }; | |
| 2926 static const int hi[Op_RegL + 1] = { | |
| 2927 0, | |
| 2928 0, | |
|
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2929 OptoReg::Bad, // Op_RegN |
| 0 | 2930 OptoReg::Bad, // Op_RegI |
| 2931 RAX_H_num, // Op_RegP | |
| 2932 OptoReg::Bad, // Op_RegF | |
|
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2933 XMM0b_num, // Op_RegD |
| 0 | 2934 RAX_H_num // Op_RegL |
| 2935 }; | |
|
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2936 // Excluded flags and vector registers. |
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2937 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type"); |
| 0 | 2938 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]); |
| 2939 %} | |
| 2940 %} | |
| 2941 | |
| 2942 //----------ATTRIBUTES--------------------------------------------------------- | |
| 2943 //----------Operand Attributes------------------------------------------------- | |
| 2944 op_attrib op_cost(0); // Required cost attribute | |
| 2945 | |
| 2946 //----------Instruction Attributes--------------------------------------------- | |
| 2947 ins_attrib ins_cost(100); // Required cost attribute | |
| 2948 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 2949 ins_attrib ins_short_branch(0); // Required flag: is this instruction | |
| 2950 // a non-matching short branch variant | |
| 2951 // of some long branch? | |
| 2952 ins_attrib ins_alignment(1); // Required alignment attribute (must | |
| 2953 // be a power of 2) specifies the | |
| 2954 // alignment that some part of the | |
| 2955 // instruction (not necessarily the | |
| 2956 // start) requires. If > 1, a | |
| 2957 // compute_padding() function must be | |
| 2958 // provided for the instruction | |
| 2959 | |
| 2960 //----------OPERANDS----------------------------------------------------------- | |
| 2961 // Operand definitions must precede instruction definitions for correct parsing | |
| 2962 // in the ADLC because operands constitute user defined types which are used in | |
| 2963 // instruction definitions. | |
| 2964 | |
| 2965 //----------Simple Operands---------------------------------------------------- | |
| 2966 // Immediate Operands | |
| 2967 // Integer Immediate | |
| 2968 operand immI() | |
| 2969 %{ | |
| 2970 match(ConI); | |
| 2971 | |
| 2972 op_cost(10); | |
| 2973 format %{ %} | |
| 2974 interface(CONST_INTER); | |
| 2975 %} | |
| 2976 | |
| 2977 // Constant for test vs zero | |
| 2978 operand immI0() | |
| 2979 %{ | |
| 2980 predicate(n->get_int() == 0); | |
| 2981 match(ConI); | |
| 2982 | |
| 2983 op_cost(0); | |
| 2984 format %{ %} | |
| 2985 interface(CONST_INTER); | |
| 2986 %} | |
| 2987 | |
| 2988 // Constant for increment | |
| 2989 operand immI1() | |
| 2990 %{ | |
| 2991 predicate(n->get_int() == 1); | |
| 2992 match(ConI); | |
| 2993 | |
| 2994 op_cost(0); | |
| 2995 format %{ %} | |
| 2996 interface(CONST_INTER); | |
| 2997 %} | |
| 2998 | |
| 2999 // Constant for decrement | |
| 3000 operand immI_M1() | |
| 3001 %{ | |
| 3002 predicate(n->get_int() == -1); | |
| 3003 match(ConI); | |
| 3004 | |
| 3005 op_cost(0); | |
| 3006 format %{ %} | |
| 3007 interface(CONST_INTER); | |
| 3008 %} | |
| 3009 | |
| 3010 // Valid scale values for addressing modes | |
| 3011 operand immI2() | |
| 3012 %{ | |
| 3013 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 3014 match(ConI); | |
| 3015 | |
| 3016 format %{ %} | |
| 3017 interface(CONST_INTER); | |
| 3018 %} | |
| 3019 | |
| 3020 operand immI8() | |
| 3021 %{ | |
| 3022 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80)); | |
| 3023 match(ConI); | |
| 3024 | |
| 3025 op_cost(5); | |
| 3026 format %{ %} | |
| 3027 interface(CONST_INTER); | |
| 3028 %} | |
| 3029 | |
| 3030 operand immI16() | |
| 3031 %{ | |
| 3032 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 3033 match(ConI); | |
| 3034 | |
| 3035 op_cost(10); | |
| 3036 format %{ %} | |
| 3037 interface(CONST_INTER); | |
| 3038 %} | |
| 3039 | |
|
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3040 // Int Immediate non-negative |
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3041 operand immU31() |
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3042 %{ |
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3043 predicate(n->get_int() >= 0); |
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3044 match(ConI); |
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|
3045 |
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|
3046 op_cost(0); |
|
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3047 format %{ %} |
|
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3048 interface(CONST_INTER); |
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3049 %} |
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3050 |
| 0 | 3051 // Constant for long shifts |
| 3052 operand immI_32() | |
| 3053 %{ | |
| 3054 predicate( n->get_int() == 32 ); | |
| 3055 match(ConI); | |
| 3056 | |
| 3057 op_cost(0); | |
| 3058 format %{ %} | |
| 3059 interface(CONST_INTER); | |
| 3060 %} | |
| 3061 | |
| 3062 // Constant for long shifts | |
| 3063 operand immI_64() | |
| 3064 %{ | |
| 3065 predicate( n->get_int() == 64 ); | |
| 3066 match(ConI); | |
| 3067 | |
| 3068 op_cost(0); | |
| 3069 format %{ %} | |
| 3070 interface(CONST_INTER); | |
| 3071 %} | |
| 3072 | |
| 3073 // Pointer Immediate | |
| 3074 operand immP() | |
| 3075 %{ | |
| 3076 match(ConP); | |
| 3077 | |
| 3078 op_cost(10); | |
| 3079 format %{ %} | |
| 3080 interface(CONST_INTER); | |
| 3081 %} | |
| 3082 | |
| 3083 // NULL Pointer Immediate | |
| 3084 operand immP0() | |
| 3085 %{ | |
| 3086 predicate(n->get_ptr() == 0); | |
| 3087 match(ConP); | |
| 3088 | |
| 3089 op_cost(5); | |
| 3090 format %{ %} | |
| 3091 interface(CONST_INTER); | |
| 3092 %} | |
| 3093 | |
|
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3094 // Pointer Immediate |
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3095 operand immN() %{ |
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3096 match(ConN); |
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3097 |
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3098 op_cost(10); |
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3099 format %{ %} |
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3100 interface(CONST_INTER); |
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3101 %} |
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3102 |
|
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3103 operand immNKlass() %{ |
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3104 match(ConNKlass); |
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|
3105 |
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|
3106 op_cost(10); |
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3107 format %{ %} |
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3108 interface(CONST_INTER); |
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3109 %} |
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3110 |
|
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3111 // NULL Pointer Immediate |
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3112 operand immN0() %{ |
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3113 predicate(n->get_narrowcon() == 0); |
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3114 match(ConN); |
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3115 |
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3116 op_cost(5); |
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3117 format %{ %} |
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3118 interface(CONST_INTER); |
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3119 %} |
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3120 |
| 0 | 3121 operand immP31() |
| 3122 %{ | |
|
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3123 predicate(n->as_Type()->type()->reloc() == relocInfo::none |
| 0 | 3124 && (n->get_ptr() >> 31) == 0); |
| 3125 match(ConP); | |
| 3126 | |
| 3127 op_cost(5); | |
| 3128 format %{ %} | |
| 3129 interface(CONST_INTER); | |
| 3130 %} | |
| 3131 | |
|
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3132 |
| 0 | 3133 // Long Immediate |
| 3134 operand immL() | |
| 3135 %{ | |
| 3136 match(ConL); | |
| 3137 | |
| 3138 op_cost(20); | |
| 3139 format %{ %} | |
| 3140 interface(CONST_INTER); | |
| 3141 %} | |
| 3142 | |
| 3143 // Long Immediate 8-bit | |
| 3144 operand immL8() | |
| 3145 %{ | |
| 3146 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L); | |
| 3147 match(ConL); | |
| 3148 | |
| 3149 op_cost(5); | |
| 3150 format %{ %} | |
| 3151 interface(CONST_INTER); | |
| 3152 %} | |
| 3153 | |
| 3154 // Long Immediate 32-bit unsigned | |
| 3155 operand immUL32() | |
| 3156 %{ | |
| 3157 predicate(n->get_long() == (unsigned int) (n->get_long())); | |
| 3158 match(ConL); | |
| 3159 | |
| 3160 op_cost(10); | |
| 3161 format %{ %} | |
| 3162 interface(CONST_INTER); | |
| 3163 %} | |
| 3164 | |
| 3165 // Long Immediate 32-bit signed | |
| 3166 operand immL32() | |
| 3167 %{ | |
| 3168 predicate(n->get_long() == (int) (n->get_long())); | |
| 3169 match(ConL); | |
| 3170 | |
| 3171 op_cost(15); | |
| 3172 format %{ %} | |
| 3173 interface(CONST_INTER); | |
| 3174 %} | |
| 3175 | |
| 3176 // Long Immediate zero | |
| 3177 operand immL0() | |
| 3178 %{ | |
| 3179 predicate(n->get_long() == 0L); | |
| 3180 match(ConL); | |
| 3181 | |
| 3182 op_cost(10); | |
| 3183 format %{ %} | |
| 3184 interface(CONST_INTER); | |
| 3185 %} | |
| 3186 | |
| 3187 // Constant for increment | |
| 3188 operand immL1() | |
| 3189 %{ | |
| 3190 predicate(n->get_long() == 1); | |
| 3191 match(ConL); | |
| 3192 | |
| 3193 format %{ %} | |
| 3194 interface(CONST_INTER); | |
| 3195 %} | |
| 3196 | |
| 3197 // Constant for decrement | |
| 3198 operand immL_M1() | |
| 3199 %{ | |
| 3200 predicate(n->get_long() == -1); | |
| 3201 match(ConL); | |
| 3202 | |
| 3203 format %{ %} | |
| 3204 interface(CONST_INTER); | |
| 3205 %} | |
| 3206 | |
| 3207 // Long Immediate: the value 10 | |
| 3208 operand immL10() | |
| 3209 %{ | |
| 3210 predicate(n->get_long() == 10); | |
| 3211 match(ConL); | |
| 3212 | |
| 3213 format %{ %} | |
| 3214 interface(CONST_INTER); | |
| 3215 %} | |
| 3216 | |
| 3217 // Long immediate from 0 to 127. | |
| 3218 // Used for a shorter form of long mul by 10. | |
| 3219 operand immL_127() | |
| 3220 %{ | |
| 3221 predicate(0 <= n->get_long() && n->get_long() < 0x80); | |
| 3222 match(ConL); | |
| 3223 | |
| 3224 op_cost(10); | |
| 3225 format %{ %} | |
| 3226 interface(CONST_INTER); | |
| 3227 %} | |
| 3228 | |
| 3229 // Long Immediate: low 32-bit mask | |
| 3230 operand immL_32bits() | |
| 3231 %{ | |
| 3232 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3233 match(ConL); | |
| 3234 op_cost(20); | |
| 3235 | |
| 3236 format %{ %} | |
| 3237 interface(CONST_INTER); | |
| 3238 %} | |
| 3239 | |
| 3240 // Float Immediate zero | |
| 3241 operand immF0() | |
| 3242 %{ | |
| 3243 predicate(jint_cast(n->getf()) == 0); | |
| 3244 match(ConF); | |
| 3245 | |
| 3246 op_cost(5); | |
| 3247 format %{ %} | |
| 3248 interface(CONST_INTER); | |
| 3249 %} | |
| 3250 | |
| 3251 // Float Immediate | |
| 3252 operand immF() | |
| 3253 %{ | |
| 3254 match(ConF); | |
| 3255 | |
| 3256 op_cost(15); | |
| 3257 format %{ %} | |
| 3258 interface(CONST_INTER); | |
| 3259 %} | |
| 3260 | |
| 3261 // Double Immediate zero | |
| 3262 operand immD0() | |
| 3263 %{ | |
| 3264 predicate(jlong_cast(n->getd()) == 0); | |
| 3265 match(ConD); | |
| 3266 | |
| 3267 op_cost(5); | |
| 3268 format %{ %} | |
| 3269 interface(CONST_INTER); | |
| 3270 %} | |
| 3271 | |
| 3272 // Double Immediate | |
| 3273 operand immD() | |
| 3274 %{ | |
| 3275 match(ConD); | |
| 3276 | |
| 3277 op_cost(15); | |
| 3278 format %{ %} | |
| 3279 interface(CONST_INTER); | |
| 3280 %} | |
| 3281 | |
| 3282 // Immediates for special shifts (sign extend) | |
| 3283 | |
| 3284 // Constants for increment | |
| 3285 operand immI_16() | |
| 3286 %{ | |
| 3287 predicate(n->get_int() == 16); | |
| 3288 match(ConI); | |
| 3289 | |
| 3290 format %{ %} | |
| 3291 interface(CONST_INTER); | |
| 3292 %} | |
| 3293 | |
| 3294 operand immI_24() | |
| 3295 %{ | |
| 3296 predicate(n->get_int() == 24); | |
| 3297 match(ConI); | |
| 3298 | |
| 3299 format %{ %} | |
| 3300 interface(CONST_INTER); | |
| 3301 %} | |
| 3302 | |
| 3303 // Constant for byte-wide masking | |
| 3304 operand immI_255() | |
| 3305 %{ | |
| 3306 predicate(n->get_int() == 255); | |
| 3307 match(ConI); | |
| 3308 | |
| 3309 format %{ %} | |
| 3310 interface(CONST_INTER); | |
| 3311 %} | |
| 3312 | |
| 3313 // Constant for short-wide masking | |
| 3314 operand immI_65535() | |
| 3315 %{ | |
| 3316 predicate(n->get_int() == 65535); | |
| 3317 match(ConI); | |
| 3318 | |
| 3319 format %{ %} | |
| 3320 interface(CONST_INTER); | |
| 3321 %} | |
| 3322 | |
| 3323 // Constant for byte-wide masking | |
| 3324 operand immL_255() | |
| 3325 %{ | |
| 3326 predicate(n->get_long() == 255); | |
| 3327 match(ConL); | |
| 3328 | |
| 3329 format %{ %} | |
| 3330 interface(CONST_INTER); | |
| 3331 %} | |
| 3332 | |
| 3333 // Constant for short-wide masking | |
| 3334 operand immL_65535() | |
| 3335 %{ | |
| 3336 predicate(n->get_long() == 65535); | |
| 3337 match(ConL); | |
| 3338 | |
| 3339 format %{ %} | |
| 3340 interface(CONST_INTER); | |
| 3341 %} | |
| 3342 | |
| 3343 // Register Operands | |
| 3344 // Integer Register | |
| 3345 operand rRegI() | |
| 3346 %{ | |
| 3347 constraint(ALLOC_IN_RC(int_reg)); | |
| 3348 match(RegI); | |
| 3349 | |
| 3350 match(rax_RegI); | |
| 3351 match(rbx_RegI); | |
| 3352 match(rcx_RegI); | |
| 3353 match(rdx_RegI); | |
| 3354 match(rdi_RegI); | |
| 3355 | |
| 3356 format %{ %} | |
| 3357 interface(REG_INTER); | |
| 3358 %} | |
| 3359 | |
| 3360 // Special Registers | |
| 3361 operand rax_RegI() | |
| 3362 %{ | |
| 3363 constraint(ALLOC_IN_RC(int_rax_reg)); | |
| 3364 match(RegI); | |
| 3365 match(rRegI); | |
| 3366 | |
| 3367 format %{ "RAX" %} | |
| 3368 interface(REG_INTER); | |
| 3369 %} | |
| 3370 | |
| 3371 // Special Registers | |
| 3372 operand rbx_RegI() | |
| 3373 %{ | |
| 3374 constraint(ALLOC_IN_RC(int_rbx_reg)); | |
| 3375 match(RegI); | |
| 3376 match(rRegI); | |
| 3377 | |
| 3378 format %{ "RBX" %} | |
| 3379 interface(REG_INTER); | |
| 3380 %} | |
| 3381 | |
| 3382 operand rcx_RegI() | |
| 3383 %{ | |
| 3384 constraint(ALLOC_IN_RC(int_rcx_reg)); | |
| 3385 match(RegI); | |
| 3386 match(rRegI); | |
| 3387 | |
| 3388 format %{ "RCX" %} | |
| 3389 interface(REG_INTER); | |
| 3390 %} | |
| 3391 | |
| 3392 operand rdx_RegI() | |
| 3393 %{ | |
| 3394 constraint(ALLOC_IN_RC(int_rdx_reg)); | |
| 3395 match(RegI); | |
| 3396 match(rRegI); | |
| 3397 | |
| 3398 format %{ "RDX" %} | |
| 3399 interface(REG_INTER); | |
| 3400 %} | |
| 3401 | |
| 3402 operand rdi_RegI() | |
| 3403 %{ | |
| 3404 constraint(ALLOC_IN_RC(int_rdi_reg)); | |
| 3405 match(RegI); | |
| 3406 match(rRegI); | |
| 3407 | |
| 3408 format %{ "RDI" %} | |
| 3409 interface(REG_INTER); | |
| 3410 %} | |
| 3411 | |
| 3412 operand no_rcx_RegI() | |
| 3413 %{ | |
| 3414 constraint(ALLOC_IN_RC(int_no_rcx_reg)); | |
| 3415 match(RegI); | |
| 3416 match(rax_RegI); | |
| 3417 match(rbx_RegI); | |
| 3418 match(rdx_RegI); | |
| 3419 match(rdi_RegI); | |
| 3420 | |
| 3421 format %{ %} | |
| 3422 interface(REG_INTER); | |
| 3423 %} | |
| 3424 | |
| 3425 operand no_rax_rdx_RegI() | |
| 3426 %{ | |
| 3427 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg)); | |
| 3428 match(RegI); | |
| 3429 match(rbx_RegI); | |
| 3430 match(rcx_RegI); | |
| 3431 match(rdi_RegI); | |
| 3432 | |
| 3433 format %{ %} | |
| 3434 interface(REG_INTER); | |
| 3435 %} | |
| 3436 | |
| 3437 // Pointer Register | |
| 3438 operand any_RegP() | |
| 3439 %{ | |
| 3440 constraint(ALLOC_IN_RC(any_reg)); | |
| 3441 match(RegP); | |
| 3442 match(rax_RegP); | |
| 3443 match(rbx_RegP); | |
| 3444 match(rdi_RegP); | |
| 3445 match(rsi_RegP); | |
| 3446 match(rbp_RegP); | |
| 3447 match(r15_RegP); | |
| 3448 match(rRegP); | |
| 3449 | |
| 3450 format %{ %} | |
| 3451 interface(REG_INTER); | |
| 3452 %} | |
| 3453 | |
| 3454 operand rRegP() | |
| 3455 %{ | |
| 3456 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3457 match(RegP); | |
| 3458 match(rax_RegP); | |
| 3459 match(rbx_RegP); | |
| 3460 match(rdi_RegP); | |
| 3461 match(rsi_RegP); | |
| 3462 match(rbp_RegP); | |
| 3463 match(r15_RegP); // See Q&A below about r15_RegP. | |
| 3464 | |
| 3465 format %{ %} | |
| 3466 interface(REG_INTER); | |
| 3467 %} | |
| 3468 | |
|
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3469 operand rRegN() %{ |
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3470 constraint(ALLOC_IN_RC(int_reg)); |
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3471 match(RegN); |
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3472 |
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3473 format %{ %} |
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3474 interface(REG_INTER); |
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3475 %} |
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3476 |
| 0 | 3477 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP? |
| 3478 // Answer: Operand match rules govern the DFA as it processes instruction inputs. | |
| 3479 // It's fine for an instruction input which expects rRegP to match a r15_RegP. | |
| 3480 // The output of an instruction is controlled by the allocator, which respects | |
| 3481 // register class masks, not match rules. Unless an instruction mentions | |
| 3482 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered | |
| 3483 // by the allocator as an input. | |
| 3484 | |
| 3485 operand no_rax_RegP() | |
| 3486 %{ | |
| 3487 constraint(ALLOC_IN_RC(ptr_no_rax_reg)); | |
| 3488 match(RegP); | |
| 3489 match(rbx_RegP); | |
| 3490 match(rsi_RegP); | |
| 3491 match(rdi_RegP); | |
| 3492 | |
| 3493 format %{ %} | |
| 3494 interface(REG_INTER); | |
| 3495 %} | |
| 3496 | |
| 3497 operand no_rbp_RegP() | |
| 3498 %{ | |
| 3499 constraint(ALLOC_IN_RC(ptr_no_rbp_reg)); | |
| 3500 match(RegP); | |
| 3501 match(rbx_RegP); | |
| 3502 match(rsi_RegP); | |
| 3503 match(rdi_RegP); | |
| 3504 | |
| 3505 format %{ %} | |
| 3506 interface(REG_INTER); | |
| 3507 %} | |
| 3508 | |
| 3509 operand no_rax_rbx_RegP() | |
| 3510 %{ | |
| 3511 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg)); | |
| 3512 match(RegP); | |
| 3513 match(rsi_RegP); | |
| 3514 match(rdi_RegP); | |
| 3515 | |
| 3516 format %{ %} | |
| 3517 interface(REG_INTER); | |
| 3518 %} | |
| 3519 | |
| 3520 // Special Registers | |
| 3521 // Return a pointer value | |
| 3522 operand rax_RegP() | |
| 3523 %{ | |
| 3524 constraint(ALLOC_IN_RC(ptr_rax_reg)); | |
| 3525 match(RegP); | |
| 3526 match(rRegP); | |
| 3527 | |
| 3528 format %{ %} | |
| 3529 interface(REG_INTER); | |
| 3530 %} | |
| 3531 | |
|
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3532 // Special Registers |
|
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3533 // Return a compressed pointer value |
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3534 operand rax_RegN() |
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3535 %{ |
|
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3536 constraint(ALLOC_IN_RC(int_rax_reg)); |
|
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|
3537 match(RegN); |
|
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|
3538 match(rRegN); |
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|
3539 |
|
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|
3540 format %{ %} |
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3541 interface(REG_INTER); |
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3542 %} |
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|
3543 |
| 0 | 3544 // Used in AtomicAdd |
| 3545 operand rbx_RegP() | |
| 3546 %{ | |
| 3547 constraint(ALLOC_IN_RC(ptr_rbx_reg)); | |
| 3548 match(RegP); | |
| 3549 match(rRegP); | |
| 3550 | |
| 3551 format %{ %} | |
| 3552 interface(REG_INTER); | |
| 3553 %} | |
| 3554 | |
| 3555 operand rsi_RegP() | |
| 3556 %{ | |
| 3557 constraint(ALLOC_IN_RC(ptr_rsi_reg)); | |
| 3558 match(RegP); | |
| 3559 match(rRegP); | |
| 3560 | |
| 3561 format %{ %} | |
| 3562 interface(REG_INTER); | |
| 3563 %} | |
| 3564 | |
| 3565 // Used in rep stosq | |
| 3566 operand rdi_RegP() | |
| 3567 %{ | |
| 3568 constraint(ALLOC_IN_RC(ptr_rdi_reg)); | |
| 3569 match(RegP); | |
| 3570 match(rRegP); | |
| 3571 | |
| 3572 format %{ %} | |
| 3573 interface(REG_INTER); | |
| 3574 %} | |
| 3575 | |
| 3576 operand rbp_RegP() | |
| 3577 %{ | |
| 3578 constraint(ALLOC_IN_RC(ptr_rbp_reg)); | |
| 3579 match(RegP); | |
| 3580 match(rRegP); | |
| 3581 | |
| 3582 format %{ %} | |
| 3583 interface(REG_INTER); | |
| 3584 %} | |
| 3585 | |
| 3586 operand r15_RegP() | |
| 3587 %{ | |
| 3588 constraint(ALLOC_IN_RC(ptr_r15_reg)); | |
| 3589 match(RegP); | |
| 3590 match(rRegP); | |
| 3591 | |
| 3592 format %{ %} | |
| 3593 interface(REG_INTER); | |
| 3594 %} | |
| 3595 | |
| 3596 operand rRegL() | |
| 3597 %{ | |
| 3598 constraint(ALLOC_IN_RC(long_reg)); | |
| 3599 match(RegL); | |
| 3600 match(rax_RegL); | |
| 3601 match(rdx_RegL); | |
| 3602 | |
| 3603 format %{ %} | |
| 3604 interface(REG_INTER); | |
| 3605 %} | |
| 3606 | |
| 3607 // Special Registers | |
| 3608 operand no_rax_rdx_RegL() | |
| 3609 %{ | |
| 3610 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 3611 match(RegL); | |
| 3612 match(rRegL); | |
| 3613 | |
| 3614 format %{ %} | |
| 3615 interface(REG_INTER); | |
| 3616 %} | |
| 3617 | |
| 3618 operand no_rax_RegL() | |
| 3619 %{ | |
| 3620 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 3621 match(RegL); | |
| 3622 match(rRegL); | |
| 3623 match(rdx_RegL); | |
| 3624 | |
| 3625 format %{ %} | |
| 3626 interface(REG_INTER); | |
| 3627 %} | |
| 3628 | |
| 3629 operand no_rcx_RegL() | |
| 3630 %{ | |
| 3631 constraint(ALLOC_IN_RC(long_no_rcx_reg)); | |
| 3632 match(RegL); | |
| 3633 match(rRegL); | |
| 3634 | |
| 3635 format %{ %} | |
| 3636 interface(REG_INTER); | |
| 3637 %} | |
| 3638 | |
| 3639 operand rax_RegL() | |
| 3640 %{ | |
| 3641 constraint(ALLOC_IN_RC(long_rax_reg)); | |
| 3642 match(RegL); | |
| 3643 match(rRegL); | |
| 3644 | |
| 3645 format %{ "RAX" %} | |
| 3646 interface(REG_INTER); | |
| 3647 %} | |
| 3648 | |
| 3649 operand rcx_RegL() | |
| 3650 %{ | |
| 3651 constraint(ALLOC_IN_RC(long_rcx_reg)); | |
| 3652 match(RegL); | |
| 3653 match(rRegL); | |
| 3654 | |
| 3655 format %{ %} | |
| 3656 interface(REG_INTER); | |
| 3657 %} | |
| 3658 | |
| 3659 operand rdx_RegL() | |
| 3660 %{ | |
| 3661 constraint(ALLOC_IN_RC(long_rdx_reg)); | |
| 3662 match(RegL); | |
| 3663 match(rRegL); | |
| 3664 | |
| 3665 format %{ %} | |
| 3666 interface(REG_INTER); | |
| 3667 %} | |
| 3668 | |
| 3669 // Flags register, used as output of compare instructions | |
| 3670 operand rFlagsReg() | |
| 3671 %{ | |
| 3672 constraint(ALLOC_IN_RC(int_flags)); | |
| 3673 match(RegFlags); | |
| 3674 | |
| 3675 format %{ "RFLAGS" %} | |
| 3676 interface(REG_INTER); | |
| 3677 %} | |
| 3678 | |
| 3679 // Flags register, used as output of FLOATING POINT compare instructions | |
| 3680 operand rFlagsRegU() | |
| 3681 %{ | |
| 3682 constraint(ALLOC_IN_RC(int_flags)); | |
| 3683 match(RegFlags); | |
| 3684 | |
| 3685 format %{ "RFLAGS_U" %} | |
| 3686 interface(REG_INTER); | |
| 3687 %} | |
| 3688 | |
|
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|
3689 operand rFlagsRegUCF() %{ |
|
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|
3690 constraint(ALLOC_IN_RC(int_flags)); |
|
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|
3691 match(RegFlags); |
|
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|
3692 predicate(false); |
|
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|
3693 |
|
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|
3694 format %{ "RFLAGS_U_CF" %} |
|
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|
3695 interface(REG_INTER); |
|
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|
3696 %} |
|
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|
3697 |
| 0 | 3698 // Float register operands |
| 3699 operand regF() | |
| 3700 %{ | |
| 3701 constraint(ALLOC_IN_RC(float_reg)); | |
| 3702 match(RegF); | |
| 3703 | |
| 3704 format %{ %} | |
| 3705 interface(REG_INTER); | |
| 3706 %} | |
| 3707 | |
| 3708 // Double register operands | |
|
2404
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|
3709 operand regD() |
| 0 | 3710 %{ |
| 3711 constraint(ALLOC_IN_RC(double_reg)); | |
| 3712 match(RegD); | |
| 3713 | |
| 3714 format %{ %} | |
| 3715 interface(REG_INTER); | |
| 3716 %} | |
| 3717 | |
| 3718 //----------Memory Operands---------------------------------------------------- | |
| 3719 // Direct Memory Operand | |
| 3720 // operand direct(immP addr) | |
| 3721 // %{ | |
| 3722 // match(addr); | |
| 3723 | |
| 3724 // format %{ "[$addr]" %} | |
| 3725 // interface(MEMORY_INTER) %{ | |
| 3726 // base(0xFFFFFFFF); | |
| 3727 // index(0x4); | |
| 3728 // scale(0x0); | |
| 3729 // disp($addr); | |
| 3730 // %} | |
| 3731 // %} | |
| 3732 | |
| 3733 // Indirect Memory Operand | |
| 3734 operand indirect(any_RegP reg) | |
| 3735 %{ | |
| 3736 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3737 match(reg); | |
| 3738 | |
| 3739 format %{ "[$reg]" %} | |
| 3740 interface(MEMORY_INTER) %{ | |
| 3741 base($reg); | |
| 3742 index(0x4); | |
| 3743 scale(0x0); | |
| 3744 disp(0x0); | |
| 3745 %} | |
| 3746 %} | |
| 3747 | |
| 3748 // Indirect Memory Plus Short Offset Operand | |
| 3749 operand indOffset8(any_RegP reg, immL8 off) | |
| 3750 %{ | |
| 3751 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3752 match(AddP reg off); | |
| 3753 | |
| 3754 format %{ "[$reg + $off (8-bit)]" %} | |
| 3755 interface(MEMORY_INTER) %{ | |
| 3756 base($reg); | |
| 3757 index(0x4); | |
| 3758 scale(0x0); | |
| 3759 disp($off); | |
| 3760 %} | |
| 3761 %} | |
| 3762 | |
| 3763 // Indirect Memory Plus Long Offset Operand | |
| 3764 operand indOffset32(any_RegP reg, immL32 off) | |
| 3765 %{ | |
| 3766 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3767 match(AddP reg off); | |
| 3768 | |
| 3769 format %{ "[$reg + $off (32-bit)]" %} | |
| 3770 interface(MEMORY_INTER) %{ | |
| 3771 base($reg); | |
| 3772 index(0x4); | |
| 3773 scale(0x0); | |
| 3774 disp($off); | |
| 3775 %} | |
| 3776 %} | |
| 3777 | |
| 3778 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 3779 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off) | |
| 3780 %{ | |
| 3781 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3782 match(AddP (AddP reg lreg) off); | |
| 3783 | |
| 3784 op_cost(10); | |
| 3785 format %{"[$reg + $off + $lreg]" %} | |
| 3786 interface(MEMORY_INTER) %{ | |
| 3787 base($reg); | |
| 3788 index($lreg); | |
| 3789 scale(0x0); | |
| 3790 disp($off); | |
| 3791 %} | |
| 3792 %} | |
| 3793 | |
| 3794 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 3795 operand indIndex(any_RegP reg, rRegL lreg) | |
| 3796 %{ | |
| 3797 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3798 match(AddP reg lreg); | |
| 3799 | |
| 3800 op_cost(10); | |
| 3801 format %{"[$reg + $lreg]" %} | |
| 3802 interface(MEMORY_INTER) %{ | |
| 3803 base($reg); | |
| 3804 index($lreg); | |
| 3805 scale(0x0); | |
| 3806 disp(0x0); | |
| 3807 %} | |
| 3808 %} | |
| 3809 | |
| 3810 // Indirect Memory Times Scale Plus Index Register | |
| 3811 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale) | |
| 3812 %{ | |
| 3813 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3814 match(AddP reg (LShiftL lreg scale)); | |
| 3815 | |
| 3816 op_cost(10); | |
| 3817 format %{"[$reg + $lreg << $scale]" %} | |
| 3818 interface(MEMORY_INTER) %{ | |
| 3819 base($reg); | |
| 3820 index($lreg); | |
| 3821 scale($scale); | |
| 3822 disp(0x0); | |
| 3823 %} | |
| 3824 %} | |
| 3825 | |
| 3826 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 3827 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale) | |
| 3828 %{ | |
| 3829 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3830 match(AddP (AddP reg (LShiftL lreg scale)) off); | |
| 3831 | |
| 3832 op_cost(10); | |
| 3833 format %{"[$reg + $off + $lreg << $scale]" %} | |
| 3834 interface(MEMORY_INTER) %{ | |
| 3835 base($reg); | |
| 3836 index($lreg); | |
| 3837 scale($scale); | |
| 3838 disp($off); | |
| 3839 %} | |
| 3840 %} | |
| 3841 | |
| 3842 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand | |
| 3843 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) | |
| 3844 %{ | |
| 3845 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3846 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); | |
| 3847 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off); | |
| 3848 | |
| 3849 op_cost(10); | |
| 3850 format %{"[$reg + $off + $idx << $scale]" %} | |
| 3851 interface(MEMORY_INTER) %{ | |
| 3852 base($reg); | |
| 3853 index($idx); | |
| 3854 scale($scale); | |
| 3855 disp($off); | |
| 3856 %} | |
| 3857 %} | |
| 3858 | |
|
642
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3859 // Indirect Narrow Oop Plus Offset Operand |
|
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|
3860 // Note: x86 architecture doesn't support "scale * index + offset" without a base |
|
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|
3861 // we can't free r12 even with Universe::narrow_oop_base() == NULL. |
|
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|
3862 operand indCompressedOopOffset(rRegN reg, immL32 off) %{ |
|
1571
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|
3863 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8)); |
|
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|
3864 constraint(ALLOC_IN_RC(ptr_reg)); |
|
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|
3865 match(AddP (DecodeN reg) off); |
|
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|
3866 |
|
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|
3867 op_cost(10); |
|
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|
3868 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %} |
|
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|
3869 interface(MEMORY_INTER) %{ |
|
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|
3870 base(0xc); // R12 |
|
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|
3871 index($reg); |
|
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|
3872 scale(0x3); |
|
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|
3873 disp($off); |
|
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|
3874 %} |
|
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|
3875 %} |
|
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|
3876 |
|
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|
3877 // Indirect Memory Operand |
|
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|
3878 operand indirectNarrow(rRegN reg) |
|
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|
3879 %{ |
|
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|
3880 predicate(Universe::narrow_oop_shift() == 0); |
|
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|
3881 constraint(ALLOC_IN_RC(ptr_reg)); |
|
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|
3882 match(DecodeN reg); |
|
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|
3883 |
|
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|
3884 format %{ "[$reg]" %} |
|
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|
3885 interface(MEMORY_INTER) %{ |
|
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|
3886 base($reg); |
|
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|
3887 index(0x4); |
|
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|
3888 scale(0x0); |
|
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|
3889 disp(0x0); |
|
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|
3890 %} |
|
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|
3891 %} |
|
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|
3892 |
|
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|
3893 // Indirect Memory Plus Short Offset Operand |
|
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|
3894 operand indOffset8Narrow(rRegN reg, immL8 off) |
|
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|
3895 %{ |
|
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|
3896 predicate(Universe::narrow_oop_shift() == 0); |
|
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|
3897 constraint(ALLOC_IN_RC(ptr_reg)); |
|
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|
3898 match(AddP (DecodeN reg) off); |
|
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|
3899 |
|
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changeset
|
3900 format %{ "[$reg + $off (8-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3901 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3902 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3903 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3904 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3905 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3906 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3907 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3908 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3909 // Indirect Memory Plus Long Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3910 operand indOffset32Narrow(rRegN reg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3911 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3912 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3913 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3914 match(AddP (DecodeN reg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3915 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3916 format %{ "[$reg + $off (32-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3917 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3918 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3919 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3920 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3921 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3922 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3923 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3924 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3925 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3926 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3927 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3928 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3929 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3930 match(AddP (AddP (DecodeN reg) lreg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3931 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3932 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3933 format %{"[$reg + $off + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3934 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3935 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3936 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3937 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3938 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3939 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3940 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3941 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3942 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3943 operand indIndexNarrow(rRegN reg, rRegL lreg) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3944 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3945 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3946 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3947 match(AddP (DecodeN reg) lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3948 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3949 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3950 format %{"[$reg + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3951 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3952 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3953 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3954 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3955 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3956 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3957 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3958 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3959 // Indirect Memory Times Scale Plus Index Register |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3960 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3961 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3962 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3963 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3964 match(AddP (DecodeN reg) (LShiftL lreg scale)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3965 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3966 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3967 format %{"[$reg + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3968 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3969 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3970 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3971 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3972 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3973 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3974 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3975 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3976 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3977 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3978 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3979 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3980 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3981 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3982 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3983 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3984 format %{"[$reg + $off + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3985 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3986 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3987 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3988 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3989 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3990 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3991 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3992 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3993 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3994 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3995 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3996 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3997 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3998 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3999 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4000 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4001 format %{"[$reg + $off + $idx << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4002 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4003 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4004 index($idx); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4005 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4006 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4007 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4008 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4009 |
| 0 | 4010 //----------Special Memory Operands-------------------------------------------- |
| 4011 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4012 // values on the stack where a match requires a value to | |
| 4013 // flow through memory. | |
| 4014 operand stackSlotP(sRegP reg) | |
| 4015 %{ | |
| 4016 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4017 // No match rule because this operand is only generated in matching | |
| 4018 | |
| 4019 format %{ "[$reg]" %} | |
| 4020 interface(MEMORY_INTER) %{ | |
| 4021 base(0x4); // RSP | |
| 4022 index(0x4); // No Index | |
| 4023 scale(0x0); // No Scale | |
| 4024 disp($reg); // Stack Offset | |
| 4025 %} | |
| 4026 %} | |
| 4027 | |
| 4028 operand stackSlotI(sRegI reg) | |
| 4029 %{ | |
| 4030 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4031 // No match rule because this operand is only generated in matching | |
| 4032 | |
| 4033 format %{ "[$reg]" %} | |
| 4034 interface(MEMORY_INTER) %{ | |
| 4035 base(0x4); // RSP | |
| 4036 index(0x4); // No Index | |
| 4037 scale(0x0); // No Scale | |
| 4038 disp($reg); // Stack Offset | |
| 4039 %} | |
| 4040 %} | |
| 4041 | |
| 4042 operand stackSlotF(sRegF reg) | |
| 4043 %{ | |
| 4044 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4045 // No match rule because this operand is only generated in matching | |
| 4046 | |
| 4047 format %{ "[$reg]" %} | |
| 4048 interface(MEMORY_INTER) %{ | |
| 4049 base(0x4); // RSP | |
| 4050 index(0x4); // No Index | |
| 4051 scale(0x0); // No Scale | |
| 4052 disp($reg); // Stack Offset | |
| 4053 %} | |
| 4054 %} | |
| 4055 | |
| 4056 operand stackSlotD(sRegD reg) | |
| 4057 %{ | |
| 4058 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4059 // No match rule because this operand is only generated in matching | |
| 4060 | |
| 4061 format %{ "[$reg]" %} | |
| 4062 interface(MEMORY_INTER) %{ | |
| 4063 base(0x4); // RSP | |
| 4064 index(0x4); // No Index | |
| 4065 scale(0x0); // No Scale | |
| 4066 disp($reg); // Stack Offset | |
| 4067 %} | |
| 4068 %} | |
| 4069 operand stackSlotL(sRegL reg) | |
| 4070 %{ | |
| 4071 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4072 // No match rule because this operand is only generated in matching | |
| 4073 | |
| 4074 format %{ "[$reg]" %} | |
| 4075 interface(MEMORY_INTER) %{ | |
| 4076 base(0x4); // RSP | |
| 4077 index(0x4); // No Index | |
| 4078 scale(0x0); // No Scale | |
| 4079 disp($reg); // Stack Offset | |
| 4080 %} | |
| 4081 %} | |
| 4082 | |
| 4083 //----------Conditional Branch Operands---------------------------------------- | |
| 4084 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4085 // the following set of codes: | |
| 4086 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4087 // | |
| 4088 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4089 // by the comparison instruction that sets a condition code flags register. | |
| 4090 // That result is represented by a flags operand whose subtype is appropriate | |
| 4091 // to the unsignedness (etc.) of the comparison. | |
| 4092 // | |
| 4093 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4094 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4095 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4096 | |
| 4097 // Comparision Code | |
| 4098 operand cmpOp() | |
| 4099 %{ | |
| 4100 match(Bool); | |
| 4101 | |
| 4102 format %{ "" %} | |
| 4103 interface(COND_INTER) %{ | |
|
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|
4104 equal(0x4, "e"); |
|
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|
4105 not_equal(0x5, "ne"); |
|
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|
4106 less(0xC, "l"); |
|
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|
4107 greater_equal(0xD, "ge"); |
|
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|
4108 less_equal(0xE, "le"); |
|
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|
4109 greater(0xF, "g"); |
| 12323 | 4110 overflow(0x0, "o"); |
| 4111 no_overflow(0x1, "no"); | |
| 0 | 4112 %} |
| 4113 %} | |
| 4114 | |
| 4115 // Comparison Code, unsigned compare. Used by FP also, with | |
| 4116 // C2 (unordered) turned into GT or LT already. The other bits | |
| 4117 // C0 and C3 are turned into Carry & Zero flags. | |
| 4118 operand cmpOpU() | |
| 4119 %{ | |
| 4120 match(Bool); | |
| 4121 | |
| 4122 format %{ "" %} | |
| 4123 interface(COND_INTER) %{ | |
|
415
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|
4124 equal(0x4, "e"); |
|
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|
4125 not_equal(0x5, "ne"); |
|
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|
4126 less(0x2, "b"); |
|
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|
4127 greater_equal(0x3, "nb"); |
|
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|
4128 less_equal(0x6, "be"); |
|
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|
4129 greater(0x7, "nbe"); |
| 12323 | 4130 overflow(0x0, "o"); |
| 4131 no_overflow(0x1, "no"); | |
|
415
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|
4132 %} |
|
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|
4133 %} |
|
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|
4134 |
|
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|
4135 |
|
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|
4136 // Floating comparisons that don't require any fixup for the unordered case |
|
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|
4137 operand cmpOpUCF() %{ |
|
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|
4138 match(Bool); |
|
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|
4139 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
|
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|
4140 n->as_Bool()->_test._test == BoolTest::ge || |
|
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|
4141 n->as_Bool()->_test._test == BoolTest::le || |
|
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|
4142 n->as_Bool()->_test._test == BoolTest::gt); |
|
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|
4143 format %{ "" %} |
|
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|
4144 interface(COND_INTER) %{ |
|
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|
4145 equal(0x4, "e"); |
|
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|
4146 not_equal(0x5, "ne"); |
|
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|
4147 less(0x2, "b"); |
|
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|
4148 greater_equal(0x3, "nb"); |
|
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|
4149 less_equal(0x6, "be"); |
|
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|
4150 greater(0x7, "nbe"); |
| 12323 | 4151 overflow(0x0, "o"); |
| 4152 no_overflow(0x1, "no"); | |
|
415
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|
4153 %} |
|
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|
4154 %} |
|
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|
4155 |
|
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|
4156 |
|
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|
4157 // Floating comparisons that can be fixed up with extra conditional jumps |
|
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|
4158 operand cmpOpUCF2() %{ |
|
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|
4159 match(Bool); |
|
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|
4160 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
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|
4161 n->as_Bool()->_test._test == BoolTest::eq); |
|
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|
4162 format %{ "" %} |
|
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|
4163 interface(COND_INTER) %{ |
|
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|
4164 equal(0x4, "e"); |
|
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|
4165 not_equal(0x5, "ne"); |
|
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|
4166 less(0x2, "b"); |
|
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|
4167 greater_equal(0x3, "nb"); |
|
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|
4168 less_equal(0x6, "be"); |
|
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|
4169 greater(0x7, "nbe"); |
| 12323 | 4170 overflow(0x0, "o"); |
| 4171 no_overflow(0x1, "no"); | |
| 0 | 4172 %} |
| 4173 %} | |
| 4174 | |
| 4175 | |
| 4176 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4177 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 4178 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4179 // instructions for every form of operand when the instruction accepts |
| 4180 // multiple operand types with the same basic encoding and format. The classic | |
| 4181 // case of this is memory operands. | |
| 4182 | |
| 4183 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, | |
|
113
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|
4184 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, |
|
642
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|
4185 indCompressedOopOffset, |
|
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|
4186 indirectNarrow, indOffset8Narrow, indOffset32Narrow, |
|
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|
4187 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, |
|
12056
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|
4188 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow); |
| 0 | 4189 |
| 4190 //----------PIPELINE----------------------------------------------------------- | |
| 4191 // Rules which define the behavior of the target architectures pipeline. | |
| 4192 pipeline %{ | |
| 4193 | |
| 4194 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4195 attributes %{ | |
| 4196 variable_size_instructions; // Fixed size instructions | |
| 4197 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 4198 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 4199 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4200 instruction_fetch_units = 1; // of 16 bytes | |
| 4201 | |
| 4202 // List of nop instructions | |
| 4203 nops( MachNop ); | |
| 4204 %} | |
| 4205 | |
| 4206 //----------RESOURCES---------------------------------------------------------- | |
| 4207 // Resources are the functional units available to the machine | |
| 4208 | |
| 4209 // Generic P2/P3 pipeline | |
| 4210 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 4211 // 3 instructions decoded per cycle. | |
| 4212 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 4213 // 3 ALU op, only ALU0 handles mul instructions. | |
| 4214 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 4215 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2, | |
| 4216 BR, FPU, | |
| 4217 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2); | |
| 4218 | |
| 4219 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4220 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4221 | |
| 4222 // Generic P2/P3 pipeline | |
| 4223 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 4224 | |
| 4225 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4226 // Pipeline Classes describe the stages in which input and output are | |
| 4227 // referenced by the hardware pipeline. | |
| 4228 | |
| 4229 // Naming convention: ialu or fpu | |
| 4230 // Then: _reg | |
| 4231 // Then: _reg if there is a 2nd register | |
| 4232 // Then: _long if it's a pair of instructions implementing a long | |
| 4233 // Then: _fat if it requires the big decoder | |
| 4234 // Or: _mem if it requires the big decoder and a memory unit. | |
| 4235 | |
| 4236 // Integer ALU reg operation | |
| 4237 pipe_class ialu_reg(rRegI dst) | |
| 4238 %{ | |
| 4239 single_instruction; | |
| 4240 dst : S4(write); | |
| 4241 dst : S3(read); | |
| 4242 DECODE : S0; // any decoder | |
| 4243 ALU : S3; // any alu | |
| 4244 %} | |
| 4245 | |
| 4246 // Long ALU reg operation | |
| 4247 pipe_class ialu_reg_long(rRegL dst) | |
| 4248 %{ | |
| 4249 instruction_count(2); | |
| 4250 dst : S4(write); | |
| 4251 dst : S3(read); | |
| 4252 DECODE : S0(2); // any 2 decoders | |
| 4253 ALU : S3(2); // both alus | |
| 4254 %} | |
| 4255 | |
| 4256 // Integer ALU reg operation using big decoder | |
| 4257 pipe_class ialu_reg_fat(rRegI dst) | |
| 4258 %{ | |
| 4259 single_instruction; | |
| 4260 dst : S4(write); | |
| 4261 dst : S3(read); | |
| 4262 D0 : S0; // big decoder only | |
| 4263 ALU : S3; // any alu | |
| 4264 %} | |
| 4265 | |
| 4266 // Long ALU reg operation using big decoder | |
| 4267 pipe_class ialu_reg_long_fat(rRegL dst) | |
| 4268 %{ | |
| 4269 instruction_count(2); | |
| 4270 dst : S4(write); | |
| 4271 dst : S3(read); | |
| 4272 D0 : S0(2); // big decoder only; twice | |
| 4273 ALU : S3(2); // any 2 alus | |
| 4274 %} | |
| 4275 | |
| 4276 // Integer ALU reg-reg operation | |
| 4277 pipe_class ialu_reg_reg(rRegI dst, rRegI src) | |
| 4278 %{ | |
| 4279 single_instruction; | |
| 4280 dst : S4(write); | |
| 4281 src : S3(read); | |
| 4282 DECODE : S0; // any decoder | |
| 4283 ALU : S3; // any alu | |
| 4284 %} | |
| 4285 | |
| 4286 // Long ALU reg-reg operation | |
| 4287 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src) | |
| 4288 %{ | |
| 4289 instruction_count(2); | |
| 4290 dst : S4(write); | |
| 4291 src : S3(read); | |
| 4292 DECODE : S0(2); // any 2 decoders | |
| 4293 ALU : S3(2); // both alus | |
| 4294 %} | |
| 4295 | |
| 4296 // Integer ALU reg-reg operation | |
| 4297 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) | |
| 4298 %{ | |
| 4299 single_instruction; | |
| 4300 dst : S4(write); | |
| 4301 src : S3(read); | |
| 4302 D0 : S0; // big decoder only | |
| 4303 ALU : S3; // any alu | |
| 4304 %} | |
| 4305 | |
| 4306 // Long ALU reg-reg operation | |
| 4307 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src) | |
| 4308 %{ | |
| 4309 instruction_count(2); | |
| 4310 dst : S4(write); | |
| 4311 src : S3(read); | |
| 4312 D0 : S0(2); // big decoder only; twice | |
| 4313 ALU : S3(2); // both alus | |
| 4314 %} | |
| 4315 | |
| 4316 // Integer ALU reg-mem operation | |
| 4317 pipe_class ialu_reg_mem(rRegI dst, memory mem) | |
| 4318 %{ | |
| 4319 single_instruction; | |
| 4320 dst : S5(write); | |
| 4321 mem : S3(read); | |
| 4322 D0 : S0; // big decoder only | |
| 4323 ALU : S4; // any alu | |
| 4324 MEM : S3; // any mem | |
| 4325 %} | |
| 4326 | |
| 4327 // Integer mem operation (prefetch) | |
| 4328 pipe_class ialu_mem(memory mem) | |
| 4329 %{ | |
| 4330 single_instruction; | |
| 4331 mem : S3(read); | |
| 4332 D0 : S0; // big decoder only | |
| 4333 MEM : S3; // any mem | |
| 4334 %} | |
| 4335 | |
| 4336 // Integer Store to Memory | |
| 4337 pipe_class ialu_mem_reg(memory mem, rRegI src) | |
| 4338 %{ | |
| 4339 single_instruction; | |
| 4340 mem : S3(read); | |
| 4341 src : S5(read); | |
| 4342 D0 : S0; // big decoder only | |
| 4343 ALU : S4; // any alu | |
| 4344 MEM : S3; | |
| 4345 %} | |
| 4346 | |
| 4347 // // Long Store to Memory | |
| 4348 // pipe_class ialu_mem_long_reg(memory mem, rRegL src) | |
| 4349 // %{ | |
| 4350 // instruction_count(2); | |
| 4351 // mem : S3(read); | |
| 4352 // src : S5(read); | |
| 4353 // D0 : S0(2); // big decoder only; twice | |
| 4354 // ALU : S4(2); // any 2 alus | |
| 4355 // MEM : S3(2); // Both mems | |
| 4356 // %} | |
| 4357 | |
| 4358 // Integer Store to Memory | |
| 4359 pipe_class ialu_mem_imm(memory mem) | |
| 4360 %{ | |
| 4361 single_instruction; | |
| 4362 mem : S3(read); | |
| 4363 D0 : S0; // big decoder only | |
| 4364 ALU : S4; // any alu | |
| 4365 MEM : S3; | |
| 4366 %} | |
| 4367 | |
| 4368 // Integer ALU0 reg-reg operation | |
| 4369 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) | |
| 4370 %{ | |
| 4371 single_instruction; | |
| 4372 dst : S4(write); | |
| 4373 src : S3(read); | |
| 4374 D0 : S0; // Big decoder only | |
| 4375 ALU0 : S3; // only alu0 | |
| 4376 %} | |
| 4377 | |
| 4378 // Integer ALU0 reg-mem operation | |
| 4379 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) | |
| 4380 %{ | |
| 4381 single_instruction; | |
| 4382 dst : S5(write); | |
| 4383 mem : S3(read); | |
| 4384 D0 : S0; // big decoder only | |
| 4385 ALU0 : S4; // ALU0 only | |
| 4386 MEM : S3; // any mem | |
| 4387 %} | |
| 4388 | |
| 4389 // Integer ALU reg-reg operation | |
| 4390 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2) | |
| 4391 %{ | |
| 4392 single_instruction; | |
| 4393 cr : S4(write); | |
| 4394 src1 : S3(read); | |
| 4395 src2 : S3(read); | |
| 4396 DECODE : S0; // any decoder | |
| 4397 ALU : S3; // any alu | |
| 4398 %} | |
| 4399 | |
| 4400 // Integer ALU reg-imm operation | |
| 4401 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1) | |
| 4402 %{ | |
| 4403 single_instruction; | |
| 4404 cr : S4(write); | |
| 4405 src1 : S3(read); | |
| 4406 DECODE : S0; // any decoder | |
| 4407 ALU : S3; // any alu | |
| 4408 %} | |
| 4409 | |
| 4410 // Integer ALU reg-mem operation | |
| 4411 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2) | |
| 4412 %{ | |
| 4413 single_instruction; | |
| 4414 cr : S4(write); | |
| 4415 src1 : S3(read); | |
| 4416 src2 : S3(read); | |
| 4417 D0 : S0; // big decoder only | |
| 4418 ALU : S4; // any alu | |
| 4419 MEM : S3; | |
| 4420 %} | |
| 4421 | |
| 4422 // Conditional move reg-reg | |
| 4423 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y) | |
| 4424 %{ | |
| 4425 instruction_count(4); | |
| 4426 y : S4(read); | |
| 4427 q : S3(read); | |
| 4428 p : S3(read); | |
| 4429 DECODE : S0(4); // any decoder | |
| 4430 %} | |
| 4431 | |
| 4432 // Conditional move reg-reg | |
| 4433 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr) | |
| 4434 %{ | |
| 4435 single_instruction; | |
| 4436 dst : S4(write); | |
| 4437 src : S3(read); | |
| 4438 cr : S3(read); | |
| 4439 DECODE : S0; // any decoder | |
| 4440 %} | |
| 4441 | |
| 4442 // Conditional move reg-mem | |
| 4443 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src) | |
| 4444 %{ | |
| 4445 single_instruction; | |
| 4446 dst : S4(write); | |
| 4447 src : S3(read); | |
| 4448 cr : S3(read); | |
| 4449 DECODE : S0; // any decoder | |
| 4450 MEM : S3; | |
| 4451 %} | |
| 4452 | |
| 4453 // Conditional move reg-reg long | |
| 4454 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src) | |
| 4455 %{ | |
| 4456 single_instruction; | |
| 4457 dst : S4(write); | |
| 4458 src : S3(read); | |
| 4459 cr : S3(read); | |
| 4460 DECODE : S0(2); // any 2 decoders | |
| 4461 %} | |
| 4462 | |
| 4463 // XXX | |
| 4464 // // Conditional move double reg-reg | |
| 4465 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src) | |
| 4466 // %{ | |
| 4467 // single_instruction; | |
| 4468 // dst : S4(write); | |
| 4469 // src : S3(read); | |
| 4470 // cr : S3(read); | |
| 4471 // DECODE : S0; // any decoder | |
| 4472 // %} | |
| 4473 | |
| 4474 // Float reg-reg operation | |
| 4475 pipe_class fpu_reg(regD dst) | |
| 4476 %{ | |
| 4477 instruction_count(2); | |
| 4478 dst : S3(read); | |
| 4479 DECODE : S0(2); // any 2 decoders | |
| 4480 FPU : S3; | |
| 4481 %} | |
| 4482 | |
| 4483 // Float reg-reg operation | |
| 4484 pipe_class fpu_reg_reg(regD dst, regD src) | |
| 4485 %{ | |
| 4486 instruction_count(2); | |
| 4487 dst : S4(write); | |
| 4488 src : S3(read); | |
| 4489 DECODE : S0(2); // any 2 decoders | |
| 4490 FPU : S3; | |
| 4491 %} | |
| 4492 | |
| 4493 // Float reg-reg operation | |
| 4494 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) | |
| 4495 %{ | |
| 4496 instruction_count(3); | |
| 4497 dst : S4(write); | |
| 4498 src1 : S3(read); | |
| 4499 src2 : S3(read); | |
| 4500 DECODE : S0(3); // any 3 decoders | |
| 4501 FPU : S3(2); | |
| 4502 %} | |
| 4503 | |
| 4504 // Float reg-reg operation | |
| 4505 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) | |
| 4506 %{ | |
| 4507 instruction_count(4); | |
| 4508 dst : S4(write); | |
| 4509 src1 : S3(read); | |
| 4510 src2 : S3(read); | |
| 4511 src3 : S3(read); | |
| 4512 DECODE : S0(4); // any 3 decoders | |
| 4513 FPU : S3(2); | |
| 4514 %} | |
| 4515 | |
| 4516 // Float reg-reg operation | |
| 4517 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) | |
| 4518 %{ | |
| 4519 instruction_count(4); | |
| 4520 dst : S4(write); | |
| 4521 src1 : S3(read); | |
| 4522 src2 : S3(read); | |
| 4523 src3 : S3(read); | |
| 4524 DECODE : S1(3); // any 3 decoders | |
| 4525 D0 : S0; // Big decoder only | |
| 4526 FPU : S3(2); | |
| 4527 MEM : S3; | |
| 4528 %} | |
| 4529 | |
| 4530 // Float reg-mem operation | |
| 4531 pipe_class fpu_reg_mem(regD dst, memory mem) | |
| 4532 %{ | |
| 4533 instruction_count(2); | |
| 4534 dst : S5(write); | |
| 4535 mem : S3(read); | |
| 4536 D0 : S0; // big decoder only | |
| 4537 DECODE : S1; // any decoder for FPU POP | |
| 4538 FPU : S4; | |
| 4539 MEM : S3; // any mem | |
| 4540 %} | |
| 4541 | |
| 4542 // Float reg-mem operation | |
| 4543 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) | |
| 4544 %{ | |
| 4545 instruction_count(3); | |
| 4546 dst : S5(write); | |
| 4547 src1 : S3(read); | |
| 4548 mem : S3(read); | |
| 4549 D0 : S0; // big decoder only | |
| 4550 DECODE : S1(2); // any decoder for FPU POP | |
| 4551 FPU : S4; | |
| 4552 MEM : S3; // any mem | |
| 4553 %} | |
| 4554 | |
| 4555 // Float mem-reg operation | |
| 4556 pipe_class fpu_mem_reg(memory mem, regD src) | |
| 4557 %{ | |
| 4558 instruction_count(2); | |
| 4559 src : S5(read); | |
| 4560 mem : S3(read); | |
| 4561 DECODE : S0; // any decoder for FPU PUSH | |
| 4562 D0 : S1; // big decoder only | |
| 4563 FPU : S4; | |
| 4564 MEM : S3; // any mem | |
| 4565 %} | |
| 4566 | |
| 4567 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) | |
| 4568 %{ | |
| 4569 instruction_count(3); | |
| 4570 src1 : S3(read); | |
| 4571 src2 : S3(read); | |
| 4572 mem : S3(read); | |
| 4573 DECODE : S0(2); // any decoder for FPU PUSH | |
| 4574 D0 : S1; // big decoder only | |
| 4575 FPU : S4; | |
| 4576 MEM : S3; // any mem | |
| 4577 %} | |
| 4578 | |
| 4579 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) | |
| 4580 %{ | |
| 4581 instruction_count(3); | |
| 4582 src1 : S3(read); | |
| 4583 src2 : S3(read); | |
| 4584 mem : S4(read); | |
| 4585 DECODE : S0; // any decoder for FPU PUSH | |
| 4586 D0 : S0(2); // big decoder only | |
| 4587 FPU : S4; | |
| 4588 MEM : S3(2); // any mem | |
| 4589 %} | |
| 4590 | |
| 4591 pipe_class fpu_mem_mem(memory dst, memory src1) | |
| 4592 %{ | |
| 4593 instruction_count(2); | |
| 4594 src1 : S3(read); | |
| 4595 dst : S4(read); | |
| 4596 D0 : S0(2); // big decoder only | |
| 4597 MEM : S3(2); // any mem | |
| 4598 %} | |
| 4599 | |
| 4600 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) | |
| 4601 %{ | |
| 4602 instruction_count(3); | |
| 4603 src1 : S3(read); | |
| 4604 src2 : S3(read); | |
| 4605 dst : S4(read); | |
| 4606 D0 : S0(3); // big decoder only | |
| 4607 FPU : S4; | |
| 4608 MEM : S3(3); // any mem | |
| 4609 %} | |
| 4610 | |
| 4611 pipe_class fpu_mem_reg_con(memory mem, regD src1) | |
| 4612 %{ | |
| 4613 instruction_count(3); | |
| 4614 src1 : S4(read); | |
| 4615 mem : S4(read); | |
| 4616 DECODE : S0; // any decoder for FPU PUSH | |
| 4617 D0 : S0(2); // big decoder only | |
| 4618 FPU : S4; | |
| 4619 MEM : S3(2); // any mem | |
| 4620 %} | |
| 4621 | |
| 4622 // Float load constant | |
| 4623 pipe_class fpu_reg_con(regD dst) | |
| 4624 %{ | |
| 4625 instruction_count(2); | |
| 4626 dst : S5(write); | |
| 4627 D0 : S0; // big decoder only for the load | |
| 4628 DECODE : S1; // any decoder for FPU POP | |
| 4629 FPU : S4; | |
| 4630 MEM : S3; // any mem | |
| 4631 %} | |
| 4632 | |
| 4633 // Float load constant | |
| 4634 pipe_class fpu_reg_reg_con(regD dst, regD src) | |
| 4635 %{ | |
| 4636 instruction_count(3); | |
| 4637 dst : S5(write); | |
| 4638 src : S3(read); | |
| 4639 D0 : S0; // big decoder only for the load | |
| 4640 DECODE : S1(2); // any decoder for FPU POP | |
| 4641 FPU : S4; | |
| 4642 MEM : S3; // any mem | |
| 4643 %} | |
| 4644 | |
| 4645 // UnConditional branch | |
| 4646 pipe_class pipe_jmp(label labl) | |
| 4647 %{ | |
| 4648 single_instruction; | |
| 4649 BR : S3; | |
| 4650 %} | |
| 4651 | |
| 4652 // Conditional branch | |
| 4653 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl) | |
| 4654 %{ | |
| 4655 single_instruction; | |
| 4656 cr : S1(read); | |
| 4657 BR : S3; | |
| 4658 %} | |
| 4659 | |
| 4660 // Allocation idiom | |
| 4661 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr) | |
| 4662 %{ | |
| 4663 instruction_count(1); force_serialization; | |
| 4664 fixed_latency(6); | |
| 4665 heap_ptr : S3(read); | |
| 4666 DECODE : S0(3); | |
| 4667 D0 : S2; | |
| 4668 MEM : S3; | |
| 4669 ALU : S3(2); | |
| 4670 dst : S5(write); | |
| 4671 BR : S5; | |
| 4672 %} | |
| 4673 | |
| 4674 // Generic big/slow expanded idiom | |
| 4675 pipe_class pipe_slow() | |
| 4676 %{ | |
| 4677 instruction_count(10); multiple_bundles; force_serialization; | |
| 4678 fixed_latency(100); | |
| 4679 D0 : S0(2); | |
| 4680 MEM : S3(2); | |
| 4681 %} | |
| 4682 | |
| 4683 // The real do-nothing guy | |
| 4684 pipe_class empty() | |
| 4685 %{ | |
| 4686 instruction_count(0); | |
| 4687 %} | |
| 4688 | |
| 4689 // Define the class for the Nop node | |
| 4690 define | |
| 4691 %{ | |
| 4692 MachNop = empty; | |
| 4693 %} | |
| 4694 | |
| 4695 %} | |
| 4696 | |
| 4697 //----------INSTRUCTIONS------------------------------------------------------- | |
| 4698 // | |
| 4699 // match -- States which machine-independent subtree may be replaced | |
| 4700 // by this instruction. | |
| 4701 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 4702 // selection to identify a minimum cost tree of machine | |
| 4703 // instructions that matches a tree of machine-independent | |
| 4704 // instructions. | |
| 4705 // format -- A string providing the disassembly for this instruction. | |
| 4706 // The value of an instruction's operand may be inserted | |
| 4707 // by referring to it with a '$' prefix. | |
| 4708 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 4709 // to within an encode class as $primary, $secondary, and $tertiary | |
| 4710 // rrspectively. The primary opcode is commonly used to | |
| 4711 // indicate the type of machine instruction, while secondary | |
| 4712 // and tertiary are often used for prefix options or addressing | |
| 4713 // modes. | |
| 4714 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 4715 // name must have been defined in an 'enc_class' specification | |
| 4716 // in the encode section of the architecture description. | |
| 4717 | |
| 4718 | |
| 4719 //----------Load/Store/Move Instructions--------------------------------------- | |
| 4720 //----------Load Instructions-------------------------------------------------- | |
| 4721 | |
| 4722 // Load Byte (8 bit signed) | |
| 4723 instruct loadB(rRegI dst, memory mem) | |
| 4724 %{ | |
| 4725 match(Set dst (LoadB mem)); | |
| 4726 | |
| 4727 ins_cost(125); | |
| 4728 format %{ "movsbl $dst, $mem\t# byte" %} | |
| 624 | 4729 |
| 4730 ins_encode %{ | |
| 4731 __ movsbl($dst$$Register, $mem$$Address); | |
| 4732 %} | |
| 4733 | |
| 0 | 4734 ins_pipe(ialu_reg_mem); |
| 4735 %} | |
| 4736 | |
| 624 | 4737 // Load Byte (8 bit signed) into Long Register |
| 4738 instruct loadB2L(rRegL dst, memory mem) | |
| 4739 %{ | |
| 4740 match(Set dst (ConvI2L (LoadB mem))); | |
| 4741 | |
| 4742 ins_cost(125); | |
| 4743 format %{ "movsbq $dst, $mem\t# byte -> long" %} | |
| 4744 | |
| 4745 ins_encode %{ | |
| 4746 __ movsbq($dst$$Register, $mem$$Address); | |
| 4747 %} | |
| 4748 | |
| 4749 ins_pipe(ialu_reg_mem); | |
| 4750 %} | |
| 4751 | |
| 4752 // Load Unsigned Byte (8 bit UNsigned) | |
| 4753 instruct loadUB(rRegI dst, memory mem) | |
| 4754 %{ | |
| 4755 match(Set dst (LoadUB mem)); | |
| 0 | 4756 |
| 4757 ins_cost(125); | |
| 4758 format %{ "movzbl $dst, $mem\t# ubyte" %} | |
| 624 | 4759 |
| 4760 ins_encode %{ | |
| 4761 __ movzbl($dst$$Register, $mem$$Address); | |
| 4762 %} | |
| 4763 | |
| 0 | 4764 ins_pipe(ialu_reg_mem); |
| 4765 %} | |
| 4766 | |
| 624 | 4767 // Load Unsigned Byte (8 bit UNsigned) into Long Register |
| 4768 instruct loadUB2L(rRegL dst, memory mem) | |
| 4769 %{ | |
| 4770 match(Set dst (ConvI2L (LoadUB mem))); | |
| 4771 | |
| 4772 ins_cost(125); | |
| 4773 format %{ "movzbq $dst, $mem\t# ubyte -> long" %} | |
| 4774 | |
| 4775 ins_encode %{ | |
| 4776 __ movzbq($dst$$Register, $mem$$Address); | |
| 4777 %} | |
| 4778 | |
| 4779 ins_pipe(ialu_reg_mem); | |
| 4780 %} | |
| 0 | 4781 |
| 824 | 4782 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register |
| 4783 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{ | |
| 4784 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 4785 effect(KILL cr); | |
| 4786 | |
| 4787 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 4788 "andl $dst, $mask" %} | |
| 4789 ins_encode %{ | |
| 4790 Register Rdst = $dst$$Register; | |
| 4791 __ movzbq(Rdst, $mem$$Address); | |
| 4792 __ andl(Rdst, $mask$$constant); | |
| 4793 %} | |
| 4794 ins_pipe(ialu_reg_mem); | |
| 4795 %} | |
| 4796 | |
| 0 | 4797 // Load Short (16 bit signed) |
| 4798 instruct loadS(rRegI dst, memory mem) | |
| 4799 %{ | |
| 4800 match(Set dst (LoadS mem)); | |
| 4801 | |
| 624 | 4802 ins_cost(125); |
| 0 | 4803 format %{ "movswl $dst, $mem\t# short" %} |
| 624 | 4804 |
| 4805 ins_encode %{ | |
| 4806 __ movswl($dst$$Register, $mem$$Address); | |
| 4807 %} | |
| 4808 | |
| 0 | 4809 ins_pipe(ialu_reg_mem); |
| 4810 %} | |
| 4811 | |
| 785 | 4812 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 4813 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 4814 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 4815 | |
| 4816 ins_cost(125); | |
| 4817 format %{ "movsbl $dst, $mem\t# short -> byte" %} | |
| 4818 ins_encode %{ | |
| 4819 __ movsbl($dst$$Register, $mem$$Address); | |
| 4820 %} | |
| 4821 ins_pipe(ialu_reg_mem); | |
| 4822 %} | |
| 4823 | |
| 624 | 4824 // Load Short (16 bit signed) into Long Register |
| 4825 instruct loadS2L(rRegL dst, memory mem) | |
| 4826 %{ | |
| 4827 match(Set dst (ConvI2L (LoadS mem))); | |
| 4828 | |
| 4829 ins_cost(125); | |
| 4830 format %{ "movswq $dst, $mem\t# short -> long" %} | |
| 4831 | |
| 4832 ins_encode %{ | |
| 4833 __ movswq($dst$$Register, $mem$$Address); | |
| 4834 %} | |
| 4835 | |
| 4836 ins_pipe(ialu_reg_mem); | |
| 4837 %} | |
| 0 | 4838 |
|
558
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6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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parents:
420
diff
changeset
|
4839 // Load Unsigned Short/Char (16 bit UNsigned) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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parents:
420
diff
changeset
|
4840 instruct loadUS(rRegI dst, memory mem) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
4841 %{ |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
4842 match(Set dst (LoadUS mem)); |
| 0 | 4843 |
| 4844 ins_cost(125); | |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
4845 format %{ "movzwl $dst, $mem\t# ushort/char" %} |
| 624 | 4846 |
| 4847 ins_encode %{ | |
| 4848 __ movzwl($dst$$Register, $mem$$Address); | |
| 4849 %} | |
| 4850 | |
| 0 | 4851 ins_pipe(ialu_reg_mem); |
| 4852 %} | |
| 4853 | |
| 785 | 4854 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 4855 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 4856 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 4857 | |
| 4858 ins_cost(125); | |
| 4859 format %{ "movsbl $dst, $mem\t# ushort -> byte" %} | |
| 4860 ins_encode %{ | |
| 4861 __ movsbl($dst$$Register, $mem$$Address); | |
| 4862 %} | |
| 4863 ins_pipe(ialu_reg_mem); | |
| 4864 %} | |
| 4865 | |
| 624 | 4866 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 4867 instruct loadUS2L(rRegL dst, memory mem) | |
| 4868 %{ | |
| 4869 match(Set dst (ConvI2L (LoadUS mem))); | |
| 4870 | |
| 4871 ins_cost(125); | |
| 4872 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %} | |
| 4873 | |
| 4874 ins_encode %{ | |
| 4875 __ movzwq($dst$$Register, $mem$$Address); | |
| 4876 %} | |
| 4877 | |
| 4878 ins_pipe(ialu_reg_mem); | |
| 4879 %} | |
| 0 | 4880 |
| 824 | 4881 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 4882 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 4883 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 4884 | |
| 4885 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %} | |
| 4886 ins_encode %{ | |
| 4887 __ movzbq($dst$$Register, $mem$$Address); | |
| 4888 %} | |
| 4889 ins_pipe(ialu_reg_mem); | |
| 4890 %} | |
| 4891 | |
| 4892 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register | |
| 4893 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{ | |
| 4894 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 4895 effect(KILL cr); | |
| 4896 | |
| 4897 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 4898 "andl $dst, $mask" %} | |
| 4899 ins_encode %{ | |
| 4900 Register Rdst = $dst$$Register; | |
| 4901 __ movzwq(Rdst, $mem$$Address); | |
| 4902 __ andl(Rdst, $mask$$constant); | |
| 4903 %} | |
| 4904 ins_pipe(ialu_reg_mem); | |
| 4905 %} | |
| 4906 | |
| 0 | 4907 // Load Integer |
| 4908 instruct loadI(rRegI dst, memory mem) | |
| 4909 %{ | |
| 4910 match(Set dst (LoadI mem)); | |
| 4911 | |
| 624 | 4912 ins_cost(125); |
| 0 | 4913 format %{ "movl $dst, $mem\t# int" %} |
| 624 | 4914 |
| 4915 ins_encode %{ | |
| 4916 __ movl($dst$$Register, $mem$$Address); | |
| 4917 %} | |
| 4918 | |
| 4919 ins_pipe(ialu_reg_mem); | |
| 4920 %} | |
| 4921 | |
| 785 | 4922 // Load Integer (32 bit signed) to Byte (8 bit signed) |
| 4923 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 4924 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 4925 | |
| 4926 ins_cost(125); | |
| 4927 format %{ "movsbl $dst, $mem\t# int -> byte" %} | |
| 4928 ins_encode %{ | |
| 4929 __ movsbl($dst$$Register, $mem$$Address); | |
| 4930 %} | |
| 4931 ins_pipe(ialu_reg_mem); | |
| 4932 %} | |
| 4933 | |
| 4934 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
| 4935 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ | |
| 4936 match(Set dst (AndI (LoadI mem) mask)); | |
| 4937 | |
| 4938 ins_cost(125); | |
| 4939 format %{ "movzbl $dst, $mem\t# int -> ubyte" %} | |
| 4940 ins_encode %{ | |
| 4941 __ movzbl($dst$$Register, $mem$$Address); | |
| 4942 %} | |
| 4943 ins_pipe(ialu_reg_mem); | |
| 4944 %} | |
| 4945 | |
| 4946 // Load Integer (32 bit signed) to Short (16 bit signed) | |
| 4947 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ | |
| 4948 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 4949 | |
| 4950 ins_cost(125); | |
| 4951 format %{ "movswl $dst, $mem\t# int -> short" %} | |
| 4952 ins_encode %{ | |
| 4953 __ movswl($dst$$Register, $mem$$Address); | |
| 4954 %} | |
| 4955 ins_pipe(ialu_reg_mem); | |
| 4956 %} | |
| 4957 | |
| 4958 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
| 4959 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ | |
| 4960 match(Set dst (AndI (LoadI mem) mask)); | |
| 4961 | |
| 4962 ins_cost(125); | |
| 4963 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %} | |
| 4964 ins_encode %{ | |
| 4965 __ movzwl($dst$$Register, $mem$$Address); | |
| 4966 %} | |
| 4967 ins_pipe(ialu_reg_mem); | |
| 4968 %} | |
| 4969 | |
| 624 | 4970 // Load Integer into Long Register |
| 4971 instruct loadI2L(rRegL dst, memory mem) | |
| 4972 %{ | |
| 4973 match(Set dst (ConvI2L (LoadI mem))); | |
| 4974 | |
| 4975 ins_cost(125); | |
| 4976 format %{ "movslq $dst, $mem\t# int -> long" %} | |
| 4977 | |
| 4978 ins_encode %{ | |
| 4979 __ movslq($dst$$Register, $mem$$Address); | |
| 4980 %} | |
| 4981 | |
| 4982 ins_pipe(ialu_reg_mem); | |
| 4983 %} | |
| 4984 | |
| 824 | 4985 // Load Integer with mask 0xFF into Long Register |
| 4986 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 4987 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 4988 | |
| 4989 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %} | |
| 4990 ins_encode %{ | |
| 4991 __ movzbq($dst$$Register, $mem$$Address); | |
| 4992 %} | |
| 4993 ins_pipe(ialu_reg_mem); | |
| 4994 %} | |
| 4995 | |
| 4996 // Load Integer with mask 0xFFFF into Long Register | |
| 4997 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{ | |
| 4998 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 4999 | |
| 5000 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %} | |
| 5001 ins_encode %{ | |
| 5002 __ movzwq($dst$$Register, $mem$$Address); | |
| 5003 %} | |
| 5004 ins_pipe(ialu_reg_mem); | |
| 5005 %} | |
| 5006 | |
|
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|
5007 // Load Integer with a 31-bit mask into Long Register |
|
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5008 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{ |
| 824 | 5009 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
| 5010 effect(KILL cr); | |
| 5011 | |
|
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|
5012 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t" |
| 824 | 5013 "andl $dst, $mask" %} |
| 5014 ins_encode %{ | |
| 5015 Register Rdst = $dst$$Register; | |
| 5016 __ movl(Rdst, $mem$$Address); | |
| 5017 __ andl(Rdst, $mask$$constant); | |
| 5018 %} | |
| 5019 ins_pipe(ialu_reg_mem); | |
| 5020 %} | |
| 5021 | |
| 624 | 5022 // Load Unsigned Integer into Long Register |
| 6849 | 5023 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask) |
| 5024 %{ | |
| 5025 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
| 624 | 5026 |
| 5027 ins_cost(125); | |
| 5028 format %{ "movl $dst, $mem\t# uint -> long" %} | |
| 5029 | |
| 5030 ins_encode %{ | |
| 5031 __ movl($dst$$Register, $mem$$Address); | |
| 5032 %} | |
| 5033 | |
| 0 | 5034 ins_pipe(ialu_reg_mem); |
| 5035 %} | |
| 5036 | |
| 5037 // Load Long | |
| 5038 instruct loadL(rRegL dst, memory mem) | |
| 5039 %{ | |
| 5040 match(Set dst (LoadL mem)); | |
| 5041 | |
| 624 | 5042 ins_cost(125); |
| 0 | 5043 format %{ "movq $dst, $mem\t# long" %} |
| 624 | 5044 |
| 5045 ins_encode %{ | |
| 5046 __ movq($dst$$Register, $mem$$Address); | |
| 5047 %} | |
| 5048 | |
| 0 | 5049 ins_pipe(ialu_reg_mem); // XXX |
| 5050 %} | |
| 5051 | |
| 5052 // Load Range | |
| 5053 instruct loadRange(rRegI dst, memory mem) | |
| 5054 %{ | |
| 5055 match(Set dst (LoadRange mem)); | |
| 5056 | |
| 5057 ins_cost(125); // XXX | |
| 5058 format %{ "movl $dst, $mem\t# range" %} | |
| 5059 opcode(0x8B); | |
| 5060 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5061 ins_pipe(ialu_reg_mem); | |
| 5062 %} | |
| 5063 | |
| 5064 // Load Pointer | |
| 5065 instruct loadP(rRegP dst, memory mem) | |
| 5066 %{ | |
| 5067 match(Set dst (LoadP mem)); | |
| 5068 | |
| 5069 ins_cost(125); // XXX | |
| 5070 format %{ "movq $dst, $mem\t# ptr" %} | |
| 5071 opcode(0x8B); | |
| 5072 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5073 ins_pipe(ialu_reg_mem); // XXX | |
| 5074 %} | |
| 5075 | |
|
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5076 // Load Compressed Pointer |
| 163 | 5077 instruct loadN(rRegN dst, memory mem) |
|
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5078 %{ |
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|
5079 match(Set dst (LoadN mem)); |
|
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|
5080 |
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|
5081 ins_cost(125); // XXX |
|
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5082 format %{ "movl $dst, $mem\t# compressed ptr" %} |
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5083 ins_encode %{ |
|
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5084 __ movl($dst$$Register, $mem$$Address); |
|
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5085 %} |
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|
5086 ins_pipe(ialu_reg_mem); // XXX |
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|
5087 %} |
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|
5088 |
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|
5089 |
| 0 | 5090 // Load Klass Pointer |
| 5091 instruct loadKlass(rRegP dst, memory mem) | |
| 5092 %{ | |
| 5093 match(Set dst (LoadKlass mem)); | |
| 5094 | |
| 5095 ins_cost(125); // XXX | |
| 5096 format %{ "movq $dst, $mem\t# class" %} | |
| 5097 opcode(0x8B); | |
| 5098 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5099 ins_pipe(ialu_reg_mem); // XXX | |
| 5100 %} | |
| 5101 | |
|
164
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|
5102 // Load narrow Klass Pointer |
|
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|
5103 instruct loadNKlass(rRegN dst, memory mem) |
|
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|
5104 %{ |
|
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|
5105 match(Set dst (LoadNKlass mem)); |
|
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|
5106 |
|
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|
5107 ins_cost(125); // XXX |
|
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|
5108 format %{ "movl $dst, $mem\t# compressed klass ptr" %} |
|
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|
5109 ins_encode %{ |
|
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|
5110 __ movl($dst$$Register, $mem$$Address); |
|
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|
5111 %} |
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|
5112 ins_pipe(ialu_reg_mem); // XXX |
|
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|
5113 %} |
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|
5114 |
| 0 | 5115 // Load Float |
| 5116 instruct loadF(regF dst, memory mem) | |
| 5117 %{ | |
| 5118 match(Set dst (LoadF mem)); | |
| 5119 | |
| 5120 ins_cost(145); // XXX | |
| 5121 format %{ "movss $dst, $mem\t# float" %} | |
| 4759 | 5122 ins_encode %{ |
| 5123 __ movflt($dst$$XMMRegister, $mem$$Address); | |
| 5124 %} | |
| 0 | 5125 ins_pipe(pipe_slow); // XXX |
| 5126 %} | |
| 5127 | |
| 5128 // Load Double | |
| 5129 instruct loadD_partial(regD dst, memory mem) | |
| 5130 %{ | |
| 5131 predicate(!UseXmmLoadAndClearUpper); | |
| 5132 match(Set dst (LoadD mem)); | |
| 5133 | |
| 5134 ins_cost(145); // XXX | |
| 5135 format %{ "movlpd $dst, $mem\t# double" %} | |
| 4759 | 5136 ins_encode %{ |
| 5137 __ movdbl($dst$$XMMRegister, $mem$$Address); | |
| 5138 %} | |
| 0 | 5139 ins_pipe(pipe_slow); // XXX |
| 5140 %} | |
| 5141 | |
| 5142 instruct loadD(regD dst, memory mem) | |
| 5143 %{ | |
| 5144 predicate(UseXmmLoadAndClearUpper); | |
| 5145 match(Set dst (LoadD mem)); | |
| 5146 | |
| 5147 ins_cost(145); // XXX | |
| 5148 format %{ "movsd $dst, $mem\t# double" %} | |
| 4759 | 5149 ins_encode %{ |
| 5150 __ movdbl($dst$$XMMRegister, $mem$$Address); | |
| 5151 %} | |
| 0 | 5152 ins_pipe(pipe_slow); // XXX |
| 5153 %} | |
| 5154 | |
| 5155 // Load Effective Address | |
| 5156 instruct leaP8(rRegP dst, indOffset8 mem) | |
| 5157 %{ | |
| 5158 match(Set dst mem); | |
| 5159 | |
| 5160 ins_cost(110); // XXX | |
| 5161 format %{ "leaq $dst, $mem\t# ptr 8" %} | |
| 5162 opcode(0x8D); | |
| 5163 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5164 ins_pipe(ialu_reg_reg_fat); | |
| 5165 %} | |
| 5166 | |
| 5167 instruct leaP32(rRegP dst, indOffset32 mem) | |
| 5168 %{ | |
| 5169 match(Set dst mem); | |
| 5170 | |
| 5171 ins_cost(110); | |
| 5172 format %{ "leaq $dst, $mem\t# ptr 32" %} | |
| 5173 opcode(0x8D); | |
| 5174 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5175 ins_pipe(ialu_reg_reg_fat); | |
| 5176 %} | |
| 5177 | |
| 5178 // instruct leaPIdx(rRegP dst, indIndex mem) | |
| 5179 // %{ | |
| 5180 // match(Set dst mem); | |
| 5181 | |
| 5182 // ins_cost(110); | |
| 5183 // format %{ "leaq $dst, $mem\t# ptr idx" %} | |
| 5184 // opcode(0x8D); | |
| 5185 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5186 // ins_pipe(ialu_reg_reg_fat); | |
| 5187 // %} | |
| 5188 | |
| 5189 instruct leaPIdxOff(rRegP dst, indIndexOffset mem) | |
| 5190 %{ | |
| 5191 match(Set dst mem); | |
| 5192 | |
| 5193 ins_cost(110); | |
| 5194 format %{ "leaq $dst, $mem\t# ptr idxoff" %} | |
| 5195 opcode(0x8D); | |
| 5196 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5197 ins_pipe(ialu_reg_reg_fat); | |
| 5198 %} | |
| 5199 | |
| 5200 instruct leaPIdxScale(rRegP dst, indIndexScale mem) | |
| 5201 %{ | |
| 5202 match(Set dst mem); | |
| 5203 | |
| 5204 ins_cost(110); | |
| 5205 format %{ "leaq $dst, $mem\t# ptr idxscale" %} | |
| 5206 opcode(0x8D); | |
| 5207 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5208 ins_pipe(ialu_reg_reg_fat); | |
| 5209 %} | |
| 5210 | |
| 5211 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem) | |
| 5212 %{ | |
| 5213 match(Set dst mem); | |
| 5214 | |
| 5215 ins_cost(110); | |
| 5216 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %} | |
| 5217 opcode(0x8D); | |
| 5218 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5219 ins_pipe(ialu_reg_reg_fat); | |
| 5220 %} | |
| 5221 | |
|
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|
5222 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem) |
|
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|
5223 %{ |
|
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|
5224 match(Set dst mem); |
|
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|
5225 |
|
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|
5226 ins_cost(110); |
|
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|
5227 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %} |
|
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|
5228 opcode(0x8D); |
|
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|
5229 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
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|
5230 ins_pipe(ialu_reg_reg_fat); |
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|
5231 %} |
|
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|
5232 |
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|
5233 // Load Effective Address which uses Narrow (32-bits) oop |
|
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|
5234 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem) |
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5235 %{ |
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5236 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0)); |
|
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5237 match(Set dst mem); |
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|
5238 |
|
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|
5239 ins_cost(110); |
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|
5240 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %} |
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|
5241 opcode(0x8D); |
|
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5242 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
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5243 ins_pipe(ialu_reg_reg_fat); |
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|
5244 %} |
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|
5245 |
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|
5246 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem) |
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|
5247 %{ |
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5248 predicate(Universe::narrow_oop_shift() == 0); |
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5249 match(Set dst mem); |
|
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|
5250 |
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|
5251 ins_cost(110); // XXX |
|
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5252 format %{ "leaq $dst, $mem\t# ptr off8narrow" %} |
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|
5253 opcode(0x8D); |
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5254 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
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5255 ins_pipe(ialu_reg_reg_fat); |
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|
5256 %} |
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5257 |
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5258 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem) |
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5259 %{ |
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5260 predicate(Universe::narrow_oop_shift() == 0); |
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5261 match(Set dst mem); |
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|
5262 |
|
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|
5263 ins_cost(110); |
|
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|
5264 format %{ "leaq $dst, $mem\t# ptr off32narrow" %} |
|
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diff
changeset
|
5265 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5266 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5267 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5268 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5269 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5270 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5271 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5272 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5273 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5274 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5275 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5276 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5277 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5278 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5279 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5280 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5281 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5282 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5283 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5284 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5285 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5286 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5287 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5288 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5289 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5290 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5291 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5292 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5293 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5294 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5295 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5296 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5297 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5298 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5299 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5300 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5301 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5302 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5303 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5304 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5305 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5306 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5307 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5308 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5309 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5310 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5311 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5312 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5313 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5314 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5315 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5316 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
5317 |
| 0 | 5318 instruct loadConI(rRegI dst, immI src) |
| 5319 %{ | |
| 5320 match(Set dst src); | |
| 5321 | |
| 5322 format %{ "movl $dst, $src\t# int" %} | |
| 5323 ins_encode(load_immI(dst, src)); | |
| 5324 ins_pipe(ialu_reg_fat); // XXX | |
| 5325 %} | |
| 5326 | |
| 5327 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr) | |
| 5328 %{ | |
| 5329 match(Set dst src); | |
| 5330 effect(KILL cr); | |
| 5331 | |
| 5332 ins_cost(50); | |
| 5333 format %{ "xorl $dst, $dst\t# int" %} | |
| 5334 opcode(0x33); /* + rd */ | |
| 5335 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5336 ins_pipe(ialu_reg); | |
| 5337 %} | |
| 5338 | |
| 5339 instruct loadConL(rRegL dst, immL src) | |
| 5340 %{ | |
| 5341 match(Set dst src); | |
| 5342 | |
| 5343 ins_cost(150); | |
| 5344 format %{ "movq $dst, $src\t# long" %} | |
| 5345 ins_encode(load_immL(dst, src)); | |
| 5346 ins_pipe(ialu_reg); | |
| 5347 %} | |
| 5348 | |
| 5349 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr) | |
| 5350 %{ | |
| 5351 match(Set dst src); | |
| 5352 effect(KILL cr); | |
| 5353 | |
| 5354 ins_cost(50); | |
| 5355 format %{ "xorl $dst, $dst\t# long" %} | |
| 5356 opcode(0x33); /* + rd */ | |
| 5357 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5358 ins_pipe(ialu_reg); // XXX | |
| 5359 %} | |
| 5360 | |
| 5361 instruct loadConUL32(rRegL dst, immUL32 src) | |
| 5362 %{ | |
| 5363 match(Set dst src); | |
| 5364 | |
| 5365 ins_cost(60); | |
| 5366 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %} | |
| 5367 ins_encode(load_immUL32(dst, src)); | |
| 5368 ins_pipe(ialu_reg); | |
| 5369 %} | |
| 5370 | |
| 5371 instruct loadConL32(rRegL dst, immL32 src) | |
| 5372 %{ | |
| 5373 match(Set dst src); | |
| 5374 | |
| 5375 ins_cost(70); | |
| 5376 format %{ "movq $dst, $src\t# long (32-bit)" %} | |
| 5377 ins_encode(load_immL32(dst, src)); | |
| 5378 ins_pipe(ialu_reg); | |
| 5379 %} | |
| 5380 | |
| 2008 | 5381 instruct loadConP(rRegP dst, immP con) %{ |
| 5382 match(Set dst con); | |
| 5383 | |
| 5384 format %{ "movq $dst, $con\t# ptr" %} | |
| 5385 ins_encode(load_immP(dst, con)); | |
| 0 | 5386 ins_pipe(ialu_reg_fat); // XXX |
| 5387 %} | |
| 5388 | |
| 5389 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr) | |
| 5390 %{ | |
| 5391 match(Set dst src); | |
| 5392 effect(KILL cr); | |
| 5393 | |
| 5394 ins_cost(50); | |
| 5395 format %{ "xorl $dst, $dst\t# ptr" %} | |
| 5396 opcode(0x33); /* + rd */ | |
| 5397 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5398 ins_pipe(ialu_reg); | |
| 5399 %} | |
| 5400 | |
| 5401 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr) | |
| 5402 %{ | |
| 5403 match(Set dst src); | |
| 5404 effect(KILL cr); | |
| 5405 | |
| 5406 ins_cost(60); | |
| 5407 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %} | |
| 5408 ins_encode(load_immP31(dst, src)); | |
| 5409 ins_pipe(ialu_reg); | |
| 5410 %} | |
| 5411 | |
| 2008 | 5412 instruct loadConF(regF dst, immF con) %{ |
| 5413 match(Set dst con); | |
| 0 | 5414 ins_cost(125); |
| 2008 | 5415 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
| 5416 ins_encode %{ | |
| 5417 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 5418 %} | |
| 0 | 5419 ins_pipe(pipe_slow); |
| 5420 %} | |
| 5421 | |
|
113
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6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
71
diff
changeset
|
5422 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
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|
5423 match(Set dst src); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5424 effect(KILL cr); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
5425 format %{ "xorq $dst, $src\t# compressed NULL ptr" %} |
|
113
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
5426 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5427 __ xorq($dst$$Register, $dst$$Register); |
|
113
ba764ed4b6f2
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coleenp
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71
diff
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|
5428 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5429 ins_pipe(ialu_reg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5430 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5431 |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5432 instruct loadConN(rRegN dst, immN src) %{ |
|
113
ba764ed4b6f2
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diff
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|
5433 match(Set dst src); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5434 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5435 ins_cost(125); |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5436 format %{ "movl $dst, $src\t# compressed ptr" %} |
|
113
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diff
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|
5437 ins_encode %{ |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
5438 address con = (address)$src$$constant; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5439 if (con == NULL) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
5440 ShouldNotReachHere(); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5441 } else { |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5442 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant); |
|
113
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71
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|
5443 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5444 %} |
|
ba764ed4b6f2
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coleenp
parents:
71
diff
changeset
|
5445 ins_pipe(ialu_reg_fat); // XXX |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
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|
5446 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
5447 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5448 instruct loadConNKlass(rRegN dst, immNKlass src) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5449 match(Set dst src); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5450 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5451 ins_cost(125); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5452 format %{ "movl $dst, $src\t# compressed klass ptr" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5453 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5454 address con = (address)$src$$constant; |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5455 if (con == NULL) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5456 ShouldNotReachHere(); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5457 } else { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5458 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5459 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5460 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5461 ins_pipe(ialu_reg_fat); // XXX |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5462 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5463 |
| 0 | 5464 instruct loadConF0(regF dst, immF0 src) |
| 5465 %{ | |
| 5466 match(Set dst src); | |
| 5467 ins_cost(100); | |
| 5468 | |
| 5469 format %{ "xorps $dst, $dst\t# float 0.0" %} | |
| 4759 | 5470 ins_encode %{ |
| 5471 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5472 %} | |
| 0 | 5473 ins_pipe(pipe_slow); |
| 5474 %} | |
| 5475 | |
| 5476 // Use the same format since predicate() can not be used here. | |
| 2008 | 5477 instruct loadConD(regD dst, immD con) %{ |
| 5478 match(Set dst con); | |
| 0 | 5479 ins_cost(125); |
| 2008 | 5480 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
| 5481 ins_encode %{ | |
| 5482 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 5483 %} | |
| 0 | 5484 ins_pipe(pipe_slow); |
| 5485 %} | |
| 5486 | |
| 5487 instruct loadConD0(regD dst, immD0 src) | |
| 5488 %{ | |
| 5489 match(Set dst src); | |
| 5490 ins_cost(100); | |
| 5491 | |
| 5492 format %{ "xorpd $dst, $dst\t# double 0.0" %} | |
| 4759 | 5493 ins_encode %{ |
| 5494 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5495 %} | |
| 0 | 5496 ins_pipe(pipe_slow); |
| 5497 %} | |
| 5498 | |
| 5499 instruct loadSSI(rRegI dst, stackSlotI src) | |
| 5500 %{ | |
| 5501 match(Set dst src); | |
| 5502 | |
| 5503 ins_cost(125); | |
| 5504 format %{ "movl $dst, $src\t# int stk" %} | |
| 5505 opcode(0x8B); | |
| 5506 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 5507 ins_pipe(ialu_reg_mem); | |
| 5508 %} | |
| 5509 | |
| 5510 instruct loadSSL(rRegL dst, stackSlotL src) | |
| 5511 %{ | |
| 5512 match(Set dst src); | |
| 5513 | |
| 5514 ins_cost(125); | |
| 5515 format %{ "movq $dst, $src\t# long stk" %} | |
| 5516 opcode(0x8B); | |
| 5517 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 5518 ins_pipe(ialu_reg_mem); | |
| 5519 %} | |
| 5520 | |
| 5521 instruct loadSSP(rRegP dst, stackSlotP src) | |
| 5522 %{ | |
| 5523 match(Set dst src); | |
| 5524 | |
| 5525 ins_cost(125); | |
| 5526 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 5527 opcode(0x8B); | |
| 5528 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 5529 ins_pipe(ialu_reg_mem); | |
| 5530 %} | |
| 5531 | |
| 5532 instruct loadSSF(regF dst, stackSlotF src) | |
| 5533 %{ | |
| 5534 match(Set dst src); | |
| 5535 | |
| 5536 ins_cost(125); | |
| 5537 format %{ "movss $dst, $src\t# float stk" %} | |
| 4759 | 5538 ins_encode %{ |
| 5539 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 5540 %} | |
| 0 | 5541 ins_pipe(pipe_slow); // XXX |
| 5542 %} | |
| 5543 | |
| 5544 // Use the same format since predicate() can not be used here. | |
| 5545 instruct loadSSD(regD dst, stackSlotD src) | |
| 5546 %{ | |
| 5547 match(Set dst src); | |
| 5548 | |
| 5549 ins_cost(125); | |
| 5550 format %{ "movsd $dst, $src\t# double stk" %} | |
| 5551 ins_encode %{ | |
| 5552 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 5553 %} | |
| 5554 ins_pipe(pipe_slow); // XXX | |
| 5555 %} | |
| 5556 | |
| 5557 // Prefetch instructions. | |
| 5558 // Must be safe to execute with invalid address (cannot fault). | |
| 5559 | |
| 5560 instruct prefetchr( memory mem ) %{ | |
| 5561 predicate(ReadPrefetchInstr==3); | |
| 5562 match(PrefetchRead mem); | |
| 5563 ins_cost(125); | |
| 5564 | |
| 5565 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %} | |
| 3854 | 5566 ins_encode %{ |
| 5567 __ prefetchr($mem$$Address); | |
| 5568 %} | |
| 0 | 5569 ins_pipe(ialu_mem); |
| 5570 %} | |
| 5571 | |
| 5572 instruct prefetchrNTA( memory mem ) %{ | |
| 5573 predicate(ReadPrefetchInstr==0); | |
| 5574 match(PrefetchRead mem); | |
| 5575 ins_cost(125); | |
| 5576 | |
| 5577 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %} | |
| 3854 | 5578 ins_encode %{ |
| 5579 __ prefetchnta($mem$$Address); | |
| 5580 %} | |
| 0 | 5581 ins_pipe(ialu_mem); |
| 5582 %} | |
| 5583 | |
| 5584 instruct prefetchrT0( memory mem ) %{ | |
| 5585 predicate(ReadPrefetchInstr==1); | |
| 5586 match(PrefetchRead mem); | |
| 5587 ins_cost(125); | |
| 5588 | |
| 5589 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %} | |
| 3854 | 5590 ins_encode %{ |
| 5591 __ prefetcht0($mem$$Address); | |
| 5592 %} | |
| 0 | 5593 ins_pipe(ialu_mem); |
| 5594 %} | |
| 5595 | |
| 5596 instruct prefetchrT2( memory mem ) %{ | |
| 5597 predicate(ReadPrefetchInstr==2); | |
| 5598 match(PrefetchRead mem); | |
| 5599 ins_cost(125); | |
| 5600 | |
| 5601 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %} | |
| 3854 | 5602 ins_encode %{ |
| 5603 __ prefetcht2($mem$$Address); | |
| 5604 %} | |
| 0 | 5605 ins_pipe(ialu_mem); |
| 5606 %} | |
| 5607 | |
| 5608 instruct prefetchwNTA( memory mem ) %{ | |
| 5609 match(PrefetchWrite mem); | |
| 5610 ins_cost(125); | |
| 5611 | |
| 5612 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %} | |
| 3854 | 5613 ins_encode %{ |
| 5614 __ prefetchnta($mem$$Address); | |
| 5615 %} | |
| 0 | 5616 ins_pipe(ialu_mem); |
| 5617 %} | |
| 5618 | |
| 3854 | 5619 // Prefetch instructions for allocation. |
| 5620 | |
| 5621 instruct prefetchAlloc( memory mem ) %{ | |
| 5622 predicate(AllocatePrefetchInstr==3); | |
| 5623 match(PrefetchAllocation mem); | |
| 5624 ins_cost(125); | |
| 5625 | |
| 5626 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %} | |
| 5627 ins_encode %{ | |
| 5628 __ prefetchw($mem$$Address); | |
| 5629 %} | |
| 5630 ins_pipe(ialu_mem); | |
| 5631 %} | |
| 5632 | |
| 5633 instruct prefetchAllocNTA( memory mem ) %{ | |
| 5634 predicate(AllocatePrefetchInstr==0); | |
| 5635 match(PrefetchAllocation mem); | |
| 0 | 5636 ins_cost(125); |
| 5637 | |
| 3854 | 5638 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %} |
| 5639 ins_encode %{ | |
| 5640 __ prefetchnta($mem$$Address); | |
| 5641 %} | |
| 0 | 5642 ins_pipe(ialu_mem); |
| 5643 %} | |
| 5644 | |
| 3854 | 5645 instruct prefetchAllocT0( memory mem ) %{ |
| 5646 predicate(AllocatePrefetchInstr==1); | |
| 5647 match(PrefetchAllocation mem); | |
| 0 | 5648 ins_cost(125); |
| 5649 | |
| 3854 | 5650 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %} |
| 5651 ins_encode %{ | |
| 5652 __ prefetcht0($mem$$Address); | |
| 5653 %} | |
| 5654 ins_pipe(ialu_mem); | |
| 5655 %} | |
| 5656 | |
| 5657 instruct prefetchAllocT2( memory mem ) %{ | |
| 5658 predicate(AllocatePrefetchInstr==2); | |
| 5659 match(PrefetchAllocation mem); | |
| 5660 ins_cost(125); | |
| 5661 | |
| 5662 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %} | |
| 5663 ins_encode %{ | |
| 5664 __ prefetcht2($mem$$Address); | |
| 5665 %} | |
| 0 | 5666 ins_pipe(ialu_mem); |
| 5667 %} | |
| 5668 | |
| 5669 //----------Store Instructions------------------------------------------------- | |
| 5670 | |
| 5671 // Store Byte | |
| 5672 instruct storeB(memory mem, rRegI src) | |
| 5673 %{ | |
| 5674 match(Set mem (StoreB mem src)); | |
| 5675 | |
| 5676 ins_cost(125); // XXX | |
| 5677 format %{ "movb $mem, $src\t# byte" %} | |
| 5678 opcode(0x88); | |
| 5679 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 5680 ins_pipe(ialu_mem_reg); | |
| 5681 %} | |
| 5682 | |
| 5683 // Store Char/Short | |
| 5684 instruct storeC(memory mem, rRegI src) | |
| 5685 %{ | |
| 5686 match(Set mem (StoreC mem src)); | |
| 5687 | |
| 5688 ins_cost(125); // XXX | |
| 5689 format %{ "movw $mem, $src\t# char/short" %} | |
| 5690 opcode(0x89); | |
| 5691 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 5692 ins_pipe(ialu_mem_reg); | |
| 5693 %} | |
| 5694 | |
| 5695 // Store Integer | |
| 5696 instruct storeI(memory mem, rRegI src) | |
| 5697 %{ | |
| 5698 match(Set mem (StoreI mem src)); | |
| 5699 | |
| 5700 ins_cost(125); // XXX | |
| 5701 format %{ "movl $mem, $src\t# int" %} | |
| 5702 opcode(0x89); | |
| 5703 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 5704 ins_pipe(ialu_mem_reg); | |
| 5705 %} | |
| 5706 | |
| 5707 // Store Long | |
| 5708 instruct storeL(memory mem, rRegL src) | |
| 5709 %{ | |
| 5710 match(Set mem (StoreL mem src)); | |
| 5711 | |
| 5712 ins_cost(125); // XXX | |
| 5713 format %{ "movq $mem, $src\t# long" %} | |
| 5714 opcode(0x89); | |
| 5715 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 5716 ins_pipe(ialu_mem_reg); // XXX | |
| 5717 %} | |
| 5718 | |
| 5719 // Store Pointer | |
| 5720 instruct storeP(memory mem, any_RegP src) | |
| 5721 %{ | |
| 5722 match(Set mem (StoreP mem src)); | |
| 5723 | |
| 5724 ins_cost(125); // XXX | |
| 5725 format %{ "movq $mem, $src\t# ptr" %} | |
| 5726 opcode(0x89); | |
| 5727 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 5728 ins_pipe(ialu_mem_reg); | |
| 5729 %} | |
| 5730 | |
|
642
660978a2a31a
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diff
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|
5731 instruct storeImmP0(memory mem, immP0 zero) |
|
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|
5732 %{ |
|
6848
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diff
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|
5733 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
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|
5734 match(Set mem (StoreP mem zero)); |
|
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diff
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|
5735 |
|
660978a2a31a
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|
5736 ins_cost(125); // XXX |
|
660978a2a31a
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diff
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|
5737 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %} |
|
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|
5738 ins_encode %{ |
|
660978a2a31a
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624
diff
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|
5739 __ movq($mem$$Address, r12); |
|
660978a2a31a
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diff
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|
5740 %} |
|
660978a2a31a
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624
diff
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|
5741 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
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diff
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|
5742 %} |
|
660978a2a31a
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|
5743 |
| 0 | 5744 // Store NULL Pointer, mark word, or other simple pointer constant. |
| 5745 instruct storeImmP(memory mem, immP31 src) | |
| 5746 %{ | |
| 5747 match(Set mem (StoreP mem src)); | |
| 5748 | |
|
642
660978a2a31a
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|
5749 ins_cost(150); // XXX |
| 0 | 5750 format %{ "movq $mem, $src\t# ptr" %} |
| 5751 opcode(0xC7); /* C7 /0 */ | |
| 5752 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 5753 ins_pipe(ialu_mem_imm); | |
| 5754 %} | |
| 5755 | |
|
113
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|
5756 // Store Compressed Pointer |
| 163 | 5757 instruct storeN(memory mem, rRegN src) |
|
113
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|
5758 %{ |
|
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|
5759 match(Set mem (StoreN mem src)); |
|
ba764ed4b6f2
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|
5760 |
|
ba764ed4b6f2
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|
5761 ins_cost(125); // XXX |
|
164
c436414a719e
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diff
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|
5762 format %{ "movl $mem, $src\t# compressed ptr" %} |
|
113
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|
5763 ins_encode %{ |
|
642
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|
5764 __ movl($mem$$Address, $src$$Register); |
|
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|
5765 %} |
|
660978a2a31a
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|
5766 ins_pipe(ialu_mem_reg); |
|
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|
5767 %} |
|
660978a2a31a
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|
5768 |
|
6848
8e47bac5643a
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diff
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|
5769 instruct storeNKlass(memory mem, rRegN src) |
|
8e47bac5643a
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diff
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|
5770 %{ |
|
8e47bac5643a
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6795
diff
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|
5771 match(Set mem (StoreNKlass mem src)); |
|
8e47bac5643a
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diff
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|
5772 |
|
8e47bac5643a
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6795
diff
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|
5773 ins_cost(125); // XXX |
|
8e47bac5643a
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diff
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|
5774 format %{ "movl $mem, $src\t# compressed klass ptr" %} |
|
8e47bac5643a
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diff
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|
5775 ins_encode %{ |
|
8e47bac5643a
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diff
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|
5776 __ movl($mem$$Address, $src$$Register); |
|
8e47bac5643a
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diff
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|
5777 %} |
|
8e47bac5643a
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diff
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|
5778 ins_pipe(ialu_mem_reg); |
|
8e47bac5643a
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diff
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|
5779 %} |
|
8e47bac5643a
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diff
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|
5780 |
|
642
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624
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|
5781 instruct storeImmN0(memory mem, immN0 zero) |
|
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|
5782 %{ |
|
6848
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|
5783 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL); |
|
642
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|
5784 match(Set mem (StoreN mem zero)); |
|
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|
5785 |
|
660978a2a31a
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|
5786 ins_cost(125); // XXX |
|
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|
5787 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %} |
|
660978a2a31a
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|
5788 ins_encode %{ |
|
660978a2a31a
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|
5789 __ movl($mem$$Address, r12); |
|
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|
5790 %} |
|
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|
5791 ins_pipe(ialu_mem_reg); |
|
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|
5792 %} |
|
ba764ed4b6f2
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|
5793 |
|
642
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624
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|
5794 instruct storeImmN(memory mem, immN src) |
|
660978a2a31a
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624
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|
5795 %{ |
|
660978a2a31a
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624
diff
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|
5796 match(Set mem (StoreN mem src)); |
|
660978a2a31a
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624
diff
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|
5797 |
|
660978a2a31a
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624
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|
5798 ins_cost(150); // XXX |
|
660978a2a31a
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changeset
|
5799 format %{ "movl $mem, $src\t# compressed ptr" %} |
|
660978a2a31a
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|
5800 ins_encode %{ |
|
660978a2a31a
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parents:
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|
5801 address con = (address)$src$$constant; |
|
660978a2a31a
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diff
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|
5802 if (con == NULL) { |
|
660978a2a31a
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|
5803 __ movl($mem$$Address, (int32_t)0); |
|
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|
5804 } else { |
|
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diff
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|
5805 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
660978a2a31a
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|
5806 } |
|
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|
5807 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5808 ins_pipe(ialu_mem_imm); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5809 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5810 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5811 instruct storeImmNKlass(memory mem, immNKlass src) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5812 %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5813 match(Set mem (StoreNKlass mem src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5814 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5815 ins_cost(150); // XXX |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5816 format %{ "movl $mem, $src\t# compressed klass ptr" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5817 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5818 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5819 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5820 ins_pipe(ialu_mem_imm); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5821 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5822 |
| 0 | 5823 // Store Integer Immediate |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5824 instruct storeImmI0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5825 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5826 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5827 match(Set mem (StoreI mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5828 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5829 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5830 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5831 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5832 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5833 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5834 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5835 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5836 |
| 0 | 5837 instruct storeImmI(memory mem, immI src) |
| 5838 %{ | |
| 5839 match(Set mem (StoreI mem src)); | |
| 5840 | |
| 5841 ins_cost(150); | |
| 5842 format %{ "movl $mem, $src\t# int" %} | |
| 5843 opcode(0xC7); /* C7 /0 */ | |
| 5844 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 5845 ins_pipe(ialu_mem_imm); | |
| 5846 %} | |
| 5847 | |
| 5848 // Store Long Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5849 instruct storeImmL0(memory mem, immL0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5850 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5851 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5852 match(Set mem (StoreL mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5853 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5854 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5855 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5856 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5857 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5858 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5859 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5860 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5861 |
| 0 | 5862 instruct storeImmL(memory mem, immL32 src) |
| 5863 %{ | |
| 5864 match(Set mem (StoreL mem src)); | |
| 5865 | |
| 5866 ins_cost(150); | |
| 5867 format %{ "movq $mem, $src\t# long" %} | |
| 5868 opcode(0xC7); /* C7 /0 */ | |
| 5869 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 5870 ins_pipe(ialu_mem_imm); | |
| 5871 %} | |
| 5872 | |
| 5873 // Store Short/Char Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5874 instruct storeImmC0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5875 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5876 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5877 match(Set mem (StoreC mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5878 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5879 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5880 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5881 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5882 __ movw($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5883 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5884 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5885 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5886 |
| 0 | 5887 instruct storeImmI16(memory mem, immI16 src) |
| 5888 %{ | |
| 5889 predicate(UseStoreImmI16); | |
| 5890 match(Set mem (StoreC mem src)); | |
| 5891 | |
| 5892 ins_cost(150); | |
| 5893 format %{ "movw $mem, $src\t# short/char" %} | |
| 5894 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 5895 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src)); | |
| 5896 ins_pipe(ialu_mem_imm); | |
| 5897 %} | |
| 5898 | |
| 5899 // Store Byte Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5900 instruct storeImmB0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5901 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5902 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5903 match(Set mem (StoreB mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5904 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5905 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5906 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5907 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5908 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5909 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5910 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5911 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5912 |
| 0 | 5913 instruct storeImmB(memory mem, immI8 src) |
| 5914 %{ | |
| 5915 match(Set mem (StoreB mem src)); | |
| 5916 | |
| 5917 ins_cost(150); // XXX | |
| 5918 format %{ "movb $mem, $src\t# byte" %} | |
| 5919 opcode(0xC6); /* C6 /0 */ | |
| 5920 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 5921 ins_pipe(ialu_mem_imm); | |
| 5922 %} | |
| 5923 | |
| 5924 // Store CMS card-mark Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5925 instruct storeImmCM0_reg(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5926 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5927 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5928 match(Set mem (StoreCM mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5929 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5930 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5931 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5932 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5933 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5934 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5935 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5936 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5937 |
| 0 | 5938 instruct storeImmCM0(memory mem, immI0 src) |
| 5939 %{ | |
| 5940 match(Set mem (StoreCM mem src)); | |
| 5941 | |
| 5942 ins_cost(150); // XXX | |
| 5943 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %} | |
| 5944 opcode(0xC6); /* C6 /0 */ | |
| 5945 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 5946 ins_pipe(ialu_mem_imm); | |
| 5947 %} | |
| 5948 | |
| 5949 // Store Float | |
| 5950 instruct storeF(memory mem, regF src) | |
| 5951 %{ | |
| 5952 match(Set mem (StoreF mem src)); | |
| 5953 | |
| 5954 ins_cost(95); // XXX | |
| 5955 format %{ "movss $mem, $src\t# float" %} | |
| 4759 | 5956 ins_encode %{ |
| 5957 __ movflt($mem$$Address, $src$$XMMRegister); | |
| 5958 %} | |
| 0 | 5959 ins_pipe(pipe_slow); // XXX |
| 5960 %} | |
| 5961 | |
| 5962 // Store immediate Float value (it is faster than store from XMM register) | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5963 instruct storeF0(memory mem, immF0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5964 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5965 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5966 match(Set mem (StoreF mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5967 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5968 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5969 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5970 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5971 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5972 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5973 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5974 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5975 |
| 0 | 5976 instruct storeF_imm(memory mem, immF src) |
| 5977 %{ | |
| 5978 match(Set mem (StoreF mem src)); | |
| 5979 | |
| 5980 ins_cost(50); | |
| 5981 format %{ "movl $mem, $src\t# float" %} | |
| 5982 opcode(0xC7); /* C7 /0 */ | |
| 5983 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 5984 ins_pipe(ialu_mem_imm); | |
| 5985 %} | |
| 5986 | |
| 5987 // Store Double | |
| 5988 instruct storeD(memory mem, regD src) | |
| 5989 %{ | |
| 5990 match(Set mem (StoreD mem src)); | |
| 5991 | |
| 5992 ins_cost(95); // XXX | |
| 5993 format %{ "movsd $mem, $src\t# double" %} | |
| 4759 | 5994 ins_encode %{ |
| 5995 __ movdbl($mem$$Address, $src$$XMMRegister); | |
| 5996 %} | |
| 0 | 5997 ins_pipe(pipe_slow); // XXX |
| 5998 %} | |
| 5999 | |
| 6000 // Store immediate double 0.0 (it is faster than store from XMM register) | |
| 6001 instruct storeD0_imm(memory mem, immD0 src) | |
| 6002 %{ | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6003 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 6004 match(Set mem (StoreD mem src)); |
| 6005 | |
| 6006 ins_cost(50); | |
| 6007 format %{ "movq $mem, $src\t# double 0." %} | |
| 6008 opcode(0xC7); /* C7 /0 */ | |
| 6009 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 6010 ins_pipe(ialu_mem_imm); | |
| 6011 %} | |
| 6012 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6013 instruct storeD0(memory mem, immD0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6014 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6015 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6016 match(Set mem (StoreD mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6017 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6018 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6019 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6020 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6021 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6022 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6023 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6024 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6025 |
| 0 | 6026 instruct storeSSI(stackSlotI dst, rRegI src) |
| 6027 %{ | |
| 6028 match(Set dst src); | |
| 6029 | |
| 6030 ins_cost(100); | |
| 6031 format %{ "movl $dst, $src\t# int stk" %} | |
| 6032 opcode(0x89); | |
| 6033 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 6034 ins_pipe( ialu_mem_reg ); | |
| 6035 %} | |
| 6036 | |
| 6037 instruct storeSSL(stackSlotL dst, rRegL src) | |
| 6038 %{ | |
| 6039 match(Set dst src); | |
| 6040 | |
| 6041 ins_cost(100); | |
| 6042 format %{ "movq $dst, $src\t# long stk" %} | |
| 6043 opcode(0x89); | |
| 6044 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 6045 ins_pipe(ialu_mem_reg); | |
| 6046 %} | |
| 6047 | |
| 6048 instruct storeSSP(stackSlotP dst, rRegP src) | |
| 6049 %{ | |
| 6050 match(Set dst src); | |
| 6051 | |
| 6052 ins_cost(100); | |
| 6053 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 6054 opcode(0x89); | |
| 6055 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 6056 ins_pipe(ialu_mem_reg); | |
| 6057 %} | |
| 6058 | |
| 6059 instruct storeSSF(stackSlotF dst, regF src) | |
| 6060 %{ | |
| 6061 match(Set dst src); | |
| 6062 | |
| 6063 ins_cost(95); // XXX | |
| 6064 format %{ "movss $dst, $src\t# float stk" %} | |
| 4759 | 6065 ins_encode %{ |
| 6066 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 6067 %} | |
| 0 | 6068 ins_pipe(pipe_slow); // XXX |
| 6069 %} | |
| 6070 | |
| 6071 instruct storeSSD(stackSlotD dst, regD src) | |
| 6072 %{ | |
| 6073 match(Set dst src); | |
| 6074 | |
| 6075 ins_cost(95); // XXX | |
| 6076 format %{ "movsd $dst, $src\t# double stk" %} | |
| 4759 | 6077 ins_encode %{ |
| 6078 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 6079 %} | |
| 0 | 6080 ins_pipe(pipe_slow); // XXX |
| 6081 %} | |
| 6082 | |
| 6083 //----------BSWAP Instructions------------------------------------------------- | |
| 6084 instruct bytes_reverse_int(rRegI dst) %{ | |
| 6085 match(Set dst (ReverseBytesI dst)); | |
| 6086 | |
| 6087 format %{ "bswapl $dst" %} | |
| 6088 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */ | |
| 6089 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) ); | |
| 6090 ins_pipe( ialu_reg ); | |
| 6091 %} | |
| 6092 | |
| 6093 instruct bytes_reverse_long(rRegL dst) %{ | |
| 6094 match(Set dst (ReverseBytesL dst)); | |
| 6095 | |
| 6096 format %{ "bswapq $dst" %} | |
| 6097 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */ | |
| 6098 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) ); | |
| 6099 ins_pipe( ialu_reg); | |
| 6100 %} | |
| 6101 | |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6102 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6103 match(Set dst (ReverseBytesUS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6104 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6105 |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6106 format %{ "bswapl $dst\n\t" |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6107 "shrl $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6108 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6109 __ bswapl($dst$$Register); |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6110 __ shrl($dst$$Register, 16); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6111 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6112 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6113 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6114 |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6115 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6116 match(Set dst (ReverseBytesS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6117 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6118 |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6119 format %{ "bswapl $dst\n\t" |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6120 "sar $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6121 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6122 __ bswapl($dst$$Register); |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6123 __ sarl($dst$$Register, 16); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6124 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6125 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6126 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6127 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6128 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6129 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6130 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6131 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6132 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6133 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6134 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6135 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6136 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6137 __ lzcntl($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6138 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6139 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6140 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6141 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6142 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6143 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6144 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6145 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6146 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6147 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6148 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6149 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6150 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6151 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6152 "addl $dst, 31" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6153 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6154 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6155 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6156 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6157 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6158 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6159 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6160 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6161 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6162 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6163 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6164 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6165 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6166 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6167 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6168 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6169 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6170 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6171 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6172 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6173 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6174 __ lzcntq($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6175 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6176 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6177 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6178 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6179 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6180 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6181 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6182 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6183 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6184 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6185 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6186 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6187 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6188 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6189 "addl $dst, 63" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6190 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6191 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6192 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6193 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6194 __ bsrq(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6195 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6196 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6197 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6198 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6199 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6200 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6201 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6202 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6203 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6204 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6205 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6206 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6207 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6208 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6209 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6210 "movl $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6211 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6212 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6213 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6214 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6215 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6216 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6217 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6218 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6219 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6220 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6221 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6222 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6223 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6224 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6225 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6226 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6227 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6228 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6229 "movl $dst, 64\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6230 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6231 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6232 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6233 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6234 __ bsfq(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6235 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6236 __ movl(Rdst, BitsPerLong); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6237 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6238 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6239 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6240 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6241 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6242 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6243 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6244 |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6245 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6246 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6247 match(Set dst (PopCountI src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6248 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6249 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6250 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6251 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6252 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6253 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6254 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6255 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6256 |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6257 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6258 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6259 match(Set dst (PopCountI (LoadI mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6260 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6261 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6262 format %{ "popcnt $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6263 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6264 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6265 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6266 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6267 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6268 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6269 // Note: Long.bitCount(long) returns an int. |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6270 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6271 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6272 match(Set dst (PopCountL src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6273 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6274 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6275 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6276 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6277 __ popcntq($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6278 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6279 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6280 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6281 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6282 // Note: Long.bitCount(long) returns an int. |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6283 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6284 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6285 match(Set dst (PopCountL (LoadL mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6286 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6287 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6288 format %{ "popcnt $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6289 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6290 __ popcntq($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6291 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6292 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6293 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6294 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6295 |
| 0 | 6296 //----------MemBar Instructions----------------------------------------------- |
| 6297 // Memory barrier flavors | |
| 6298 | |
| 6299 instruct membar_acquire() | |
| 6300 %{ | |
| 6301 match(MemBarAcquire); | |
|
14439
50fdb38839eb
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
14428
diff
changeset
|
6302 match(LoadFence); |
| 0 | 6303 ins_cost(0); |
| 6304 | |
| 6305 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6306 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
| 0 | 6307 ins_encode(); |
| 6308 ins_pipe(empty); | |
| 6309 %} | |
| 6310 | |
| 6311 instruct membar_acquire_lock() | |
| 6312 %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6313 match(MemBarAcquireLock); |
| 0 | 6314 ins_cost(0); |
| 6315 | |
| 6316 size(0); | |
| 6317 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 6318 ins_encode(); | |
| 6319 ins_pipe(empty); | |
| 6320 %} | |
| 6321 | |
| 6322 instruct membar_release() | |
| 6323 %{ | |
| 6324 match(MemBarRelease); | |
|
14439
50fdb38839eb
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
14428
diff
changeset
|
6325 match(StoreFence); |
| 0 | 6326 ins_cost(0); |
| 6327 | |
| 6328 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6329 format %{ "MEMBAR-release ! (empty encoding)" %} |
| 0 | 6330 ins_encode(); |
| 6331 ins_pipe(empty); | |
| 6332 %} | |
| 6333 | |
| 6334 instruct membar_release_lock() | |
| 6335 %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6336 match(MemBarReleaseLock); |
| 0 | 6337 ins_cost(0); |
| 6338 | |
| 6339 size(0); | |
| 6340 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 6341 ins_encode(); | |
| 6342 ins_pipe(empty); | |
| 6343 %} | |
| 6344 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6345 instruct membar_volatile(rFlagsReg cr) %{ |
| 0 | 6346 match(MemBarVolatile); |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6347 effect(KILL cr); |
| 0 | 6348 ins_cost(400); |
| 6349 | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6350 format %{ |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6351 $$template |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6352 if (os::is_MP()) { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6353 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6354 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6355 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6356 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6357 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6358 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6359 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6360 %} |
| 0 | 6361 ins_pipe(pipe_slow); |
| 6362 %} | |
| 6363 | |
| 6364 instruct unnecessary_membar_volatile() | |
| 6365 %{ | |
| 6366 match(MemBarVolatile); | |
| 6367 predicate(Matcher::post_store_load_barrier(n)); | |
| 6368 ins_cost(0); | |
| 6369 | |
| 6370 size(0); | |
| 6371 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6372 ins_encode(); | |
| 6373 ins_pipe(empty); | |
| 6374 %} | |
| 6375 | |
|
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6376 instruct membar_storestore() %{ |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6377 match(MemBarStoreStore); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6378 ins_cost(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6379 |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6380 size(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6381 format %{ "MEMBAR-storestore (empty encoding)" %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6382 ins_encode( ); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6383 ins_pipe(empty); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6384 %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6385 |
| 0 | 6386 //----------Move Instructions-------------------------------------------------- |
| 6387 | |
| 6388 instruct castX2P(rRegP dst, rRegL src) | |
| 6389 %{ | |
| 6390 match(Set dst (CastX2P src)); | |
| 6391 | |
| 6392 format %{ "movq $dst, $src\t# long->ptr" %} | |
| 4759 | 6393 ins_encode %{ |
| 6394 if ($dst$$reg != $src$$reg) { | |
| 6395 __ movptr($dst$$Register, $src$$Register); | |
| 6396 } | |
| 6397 %} | |
| 0 | 6398 ins_pipe(ialu_reg_reg); // XXX |
| 6399 %} | |
| 6400 | |
| 6401 instruct castP2X(rRegL dst, rRegP src) | |
| 6402 %{ | |
| 6403 match(Set dst (CastP2X src)); | |
| 6404 | |
| 6405 format %{ "movq $dst, $src\t# ptr -> long" %} | |
| 4759 | 6406 ins_encode %{ |
| 6407 if ($dst$$reg != $src$$reg) { | |
| 6408 __ movptr($dst$$Register, $src$$Register); | |
| 6409 } | |
| 6410 %} | |
| 0 | 6411 ins_pipe(ialu_reg_reg); // XXX |
| 6412 %} | |
| 6413 | |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6414 // Convert oop into int for vectors alignment masking |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6415 instruct convP2I(rRegI dst, rRegP src) |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6416 %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6417 match(Set dst (ConvL2I (CastP2X src))); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6418 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6419 format %{ "movl $dst, $src\t# ptr -> int" %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6420 ins_encode %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6421 __ movl($dst$$Register, $src$$Register); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6422 %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6423 ins_pipe(ialu_reg_reg); // XXX |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6424 %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6425 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6426 // Convert compressed oop into int for vectors alignment masking |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6427 // in case of 32bit oops (heap < 4Gb). |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6428 instruct convN2I(rRegI dst, rRegN src) |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6429 %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6430 predicate(Universe::narrow_oop_shift() == 0); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6431 match(Set dst (ConvL2I (CastP2X (DecodeN src)))); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6432 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6433 format %{ "movl $dst, $src\t# compressed ptr -> int" %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6434 ins_encode %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6435 __ movl($dst$$Register, $src$$Register); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6436 %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6437 ins_pipe(ialu_reg_reg); // XXX |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6438 %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6439 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6440 // Convert oop pointer into compressed form |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6441 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6442 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6443 match(Set dst (EncodeP src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6444 effect(KILL cr); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6445 format %{ "encode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6446 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6447 Register s = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6448 Register d = $dst$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6449 if (s != d) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6450 __ movq(d, s); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6451 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6452 __ encode_heap_oop(d); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6453 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6454 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6455 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6456 |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6457 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6458 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6459 match(Set dst (EncodeP src)); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6460 effect(KILL cr); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6461 format %{ "encode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6462 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6463 __ encode_heap_oop_not_null($dst$$Register, $src$$Register); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6464 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6465 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6466 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6467 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6468 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6469 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull && |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6470 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6471 match(Set dst (DecodeN src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6472 effect(KILL cr); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6473 format %{ "decode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6474 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6475 Register s = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6476 Register d = $dst$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6477 if (s != d) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6478 __ movq(d, s); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6479 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6480 __ decode_heap_oop(d); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6481 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6482 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6483 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6484 |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
6485 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6486 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull || |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6487 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
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parents:
113
diff
changeset
|
6488 match(Set dst (DecodeN src)); |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
6489 effect(KILL cr); |
|
124
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
6490 format %{ "decode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
6491 ins_encode %{ |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6492 Register s = $src$$Register; |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6493 Register d = $dst$$Register; |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6494 if (s != d) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6495 __ decode_heap_oop_not_null(d, s); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6496 } else { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6497 __ decode_heap_oop_not_null(d); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6498 } |
|
124
b130b98db9cf
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113
diff
changeset
|
6499 %} |
|
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
6500 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6501 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6502 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6503 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6504 match(Set dst (EncodePKlass src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6505 effect(KILL cr); |
|
12056
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
10171
diff
changeset
|
6506 format %{ "encode_klass_not_null $dst,$src" %} |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6507 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6508 __ encode_klass_not_null($dst$$Register, $src$$Register); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6509 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6510 ins_pipe(ialu_reg_long); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6511 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6512 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6513 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
8e47bac5643a
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roland
parents:
6795
diff
changeset
|
6514 match(Set dst (DecodeNKlass src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6515 effect(KILL cr); |
|
12056
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
10171
diff
changeset
|
6516 format %{ "decode_klass_not_null $dst,$src" %} |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6517 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6518 Register s = $src$$Register; |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6519 Register d = $dst$$Register; |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6520 if (s != d) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6521 __ decode_klass_not_null(d, s); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6522 } else { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6523 __ decode_klass_not_null(d); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6524 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6525 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6526 ins_pipe(ialu_reg_long); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6527 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6528 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6529 |
| 0 | 6530 //----------Conditional Move--------------------------------------------------- |
| 6531 // Jump | |
| 6532 // dummy instruction for generating temp registers | |
| 6533 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ | |
| 6534 match(Jump (LShiftL switch_val shift)); | |
| 6535 ins_cost(350); | |
| 6536 predicate(false); | |
| 6537 effect(TEMP dest); | |
| 6538 | |
| 2008 | 6539 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6540 "jmp [$dest + $switch_val << $shift]\n\t" %} |
| 2008 | 6541 ins_encode %{ |
| 6542 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6543 // to do that and the compiler is using that register as one it can allocate. | |
| 6544 // So we build it all by hand. | |
| 6545 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant); | |
| 6546 // ArrayAddress dispatch(table, index); | |
| 6547 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant); | |
| 6548 __ lea($dest$$Register, $constantaddress); | |
| 6549 __ jmp(dispatch); | |
| 6550 %} | |
| 0 | 6551 ins_pipe(pipe_jmp); |
| 6552 %} | |
| 6553 | |
| 6554 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ | |
| 6555 match(Jump (AddL (LShiftL switch_val shift) offset)); | |
| 6556 ins_cost(350); | |
| 6557 effect(TEMP dest); | |
| 6558 | |
| 2008 | 6559 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6560 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %} |
| 2008 | 6561 ins_encode %{ |
| 6562 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6563 // to do that and the compiler is using that register as one it can allocate. | |
| 6564 // So we build it all by hand. | |
| 6565 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); | |
| 6566 // ArrayAddress dispatch(table, index); | |
| 6567 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); | |
| 6568 __ lea($dest$$Register, $constantaddress); | |
| 6569 __ jmp(dispatch); | |
| 6570 %} | |
| 0 | 6571 ins_pipe(pipe_jmp); |
| 6572 %} | |
| 6573 | |
| 6574 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{ | |
| 6575 match(Jump switch_val); | |
| 6576 ins_cost(350); | |
| 6577 effect(TEMP dest); | |
| 6578 | |
| 2008 | 6579 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6580 "jmp [$dest + $switch_val]\n\t" %} |
| 2008 | 6581 ins_encode %{ |
| 6582 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6583 // to do that and the compiler is using that register as one it can allocate. | |
| 6584 // So we build it all by hand. | |
| 6585 // Address index(noreg, switch_reg, Address::times_1); | |
| 6586 // ArrayAddress dispatch(table, index); | |
| 6587 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1); | |
| 6588 __ lea($dest$$Register, $constantaddress); | |
| 6589 __ jmp(dispatch); | |
| 6590 %} | |
| 0 | 6591 ins_pipe(pipe_jmp); |
| 6592 %} | |
| 6593 | |
| 6594 // Conditional move | |
| 6595 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop) | |
| 6596 %{ | |
| 6597 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6598 | |
| 6599 ins_cost(200); // XXX | |
| 6600 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 6601 opcode(0x0F, 0x40); | |
| 6602 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6603 ins_pipe(pipe_cmov_reg); | |
| 6604 %} | |
| 6605 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6606 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 0 | 6607 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
| 6608 | |
| 6609 ins_cost(200); // XXX | |
| 6610 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 6611 opcode(0x0F, 0x40); | |
| 6612 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6613 ins_pipe(pipe_cmov_reg); | |
| 6614 %} | |
| 6615 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6616 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6617 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6618 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6619 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6620 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6621 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6622 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6623 |
| 0 | 6624 // Conditional move |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6625 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 6626 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
| 6627 | |
| 6628 ins_cost(250); // XXX | |
| 6629 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 6630 opcode(0x0F, 0x40); | |
| 6631 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6632 ins_pipe(pipe_cmov_mem); | |
| 6633 %} | |
| 6634 | |
| 6635 // Conditional move | |
| 6636 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src) | |
| 6637 %{ | |
| 6638 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 6639 | |
| 6640 ins_cost(250); // XXX | |
| 6641 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 6642 opcode(0x0F, 0x40); | |
| 6643 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6644 ins_pipe(pipe_cmov_mem); | |
| 6645 %} | |
| 6646 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6647 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6648 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6649 ins_cost(250); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6650 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6651 cmovI_memU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6652 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6653 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6654 |
| 0 | 6655 // Conditional move |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6656 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop) |
|
c436414a719e
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163
diff
changeset
|
6657 %{ |
|
c436414a719e
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163
diff
changeset
|
6658 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
c436414a719e
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kvn
parents:
163
diff
changeset
|
6659 |
|
c436414a719e
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kvn
parents:
163
diff
changeset
|
6660 ins_cost(200); // XXX |
|
c436414a719e
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163
diff
changeset
|
6661 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %} |
|
c436414a719e
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163
diff
changeset
|
6662 opcode(0x0F, 0x40); |
|
c436414a719e
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kvn
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163
diff
changeset
|
6663 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
c436414a719e
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kvn
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163
diff
changeset
|
6664 ins_pipe(pipe_cmov_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6665 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6666 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
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163
diff
changeset
|
6667 // Conditional move |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6668 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src) |
|
164
c436414a719e
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kvn
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163
diff
changeset
|
6669 %{ |
|
c436414a719e
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kvn
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163
diff
changeset
|
6670 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6671 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6672 ins_cost(200); // XXX |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6673 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6674 opcode(0x0F, 0x40); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6675 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
c436414a719e
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kvn
parents:
163
diff
changeset
|
6676 ins_pipe(pipe_cmov_reg); |
|
c436414a719e
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kvn
parents:
163
diff
changeset
|
6677 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6678 |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6679 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6680 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6681 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6682 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6683 cmovN_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
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|
6684 %} |
|
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|
6685 %} |
|
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|
6686 |
|
164
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|
6687 // Conditional move |
| 0 | 6688 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop) |
| 6689 %{ | |
| 6690 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6691 | |
| 6692 ins_cost(200); // XXX | |
| 6693 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %} | |
| 6694 opcode(0x0F, 0x40); | |
| 6695 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6696 ins_pipe(pipe_cmov_reg); // XXX | |
| 6697 %} | |
| 6698 | |
| 6699 // Conditional move | |
|
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|
6700 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src) |
| 0 | 6701 %{ |
| 6702 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6703 | |
| 6704 ins_cost(200); // XXX | |
| 6705 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %} | |
| 6706 opcode(0x0F, 0x40); | |
| 6707 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6708 ins_pipe(pipe_cmov_reg); // XXX | |
| 6709 %} | |
| 6710 | |
|
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|
6711 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{ |
|
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|
6712 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
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|
6713 ins_cost(200); |
|
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|
6714 expand %{ |
|
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|
6715 cmovP_regU(cop, cr, dst, src); |
|
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|
6716 %} |
|
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|
6717 %} |
|
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|
6718 |
| 0 | 6719 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 6720 // correctly meets the two pointer arguments; one is an incoming | |
| 6721 // register but the other is a memory operand. ALSO appears to | |
| 6722 // be buggy with implicit null checks. | |
| 6723 // | |
| 6724 //// Conditional move | |
| 6725 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src) | |
| 6726 //%{ | |
| 6727 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6728 // ins_cost(250); | |
| 6729 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6730 // opcode(0x0F,0x40); | |
| 6731 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 6732 // ins_pipe( pipe_cmov_mem ); | |
| 6733 //%} | |
| 6734 // | |
| 6735 //// Conditional move | |
| 6736 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src) | |
| 6737 //%{ | |
| 6738 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6739 // ins_cost(250); | |
| 6740 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6741 // opcode(0x0F,0x40); | |
| 6742 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 6743 // ins_pipe( pipe_cmov_mem ); | |
| 6744 //%} | |
| 6745 | |
| 6746 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src) | |
| 6747 %{ | |
| 6748 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6749 | |
| 6750 ins_cost(200); // XXX | |
| 6751 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 6752 opcode(0x0F, 0x40); | |
| 6753 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6754 ins_pipe(pipe_cmov_reg); // XXX | |
| 6755 %} | |
| 6756 | |
| 6757 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src) | |
| 6758 %{ | |
| 6759 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 6760 | |
| 6761 ins_cost(200); // XXX | |
| 6762 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 6763 opcode(0x0F, 0x40); | |
| 6764 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6765 ins_pipe(pipe_cmov_mem); // XXX | |
| 6766 %} | |
| 6767 | |
| 6768 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src) | |
| 6769 %{ | |
| 6770 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6771 | |
| 6772 ins_cost(200); // XXX | |
| 6773 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 6774 opcode(0x0F, 0x40); | |
| 6775 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6776 ins_pipe(pipe_cmov_reg); // XXX | |
| 6777 %} | |
| 6778 | |
|
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|
6779 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{ |
|
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|
6780 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
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|
6781 ins_cost(200); |
|
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|
6782 expand %{ |
|
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|
6783 cmovL_regU(cop, cr, dst, src); |
|
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|
6784 %} |
|
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|
6785 %} |
|
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|
6786 |
| 0 | 6787 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src) |
| 6788 %{ | |
| 6789 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 6790 | |
| 6791 ins_cost(200); // XXX | |
| 6792 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 6793 opcode(0x0F, 0x40); | |
| 6794 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6795 ins_pipe(pipe_cmov_mem); // XXX | |
| 6796 %} | |
| 6797 | |
|
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|
6798 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{ |
|
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|
6799 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); |
|
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|
6800 ins_cost(200); |
|
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changeset
|
6801 expand %{ |
|
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|
6802 cmovL_memU(cop, cr, dst, src); |
|
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|
6803 %} |
|
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|
6804 %} |
|
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|
6805 |
| 0 | 6806 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src) |
| 6807 %{ | |
| 6808 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6809 | |
| 6810 ins_cost(200); // XXX | |
| 6811 format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 6812 "movss $dst, $src\n" | |
| 6813 "skip:" %} | |
| 4759 | 6814 ins_encode %{ |
| 6815 Label Lskip; | |
| 6816 // Invert sense of branch from sense of CMOV | |
| 6817 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6818 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6819 __ bind(Lskip); | |
| 6820 %} | |
| 0 | 6821 ins_pipe(pipe_slow); |
| 6822 %} | |
| 6823 | |
| 6824 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src) | |
| 6825 // %{ | |
| 6826 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src)))); | |
| 6827 | |
| 6828 // ins_cost(200); // XXX | |
| 6829 // format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 6830 // "movss $dst, $src\n" | |
| 6831 // "skip:" %} | |
| 6832 // ins_encode(enc_cmovf_mem_branch(cop, dst, src)); | |
| 6833 // ins_pipe(pipe_slow); | |
| 6834 // %} | |
| 6835 | |
| 6836 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src) | |
| 6837 %{ | |
| 6838 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6839 | |
| 6840 ins_cost(200); // XXX | |
| 6841 format %{ "jn$cop skip\t# unsigned cmove float\n\t" | |
| 6842 "movss $dst, $src\n" | |
| 6843 "skip:" %} | |
| 4759 | 6844 ins_encode %{ |
| 6845 Label Lskip; | |
| 6846 // Invert sense of branch from sense of CMOV | |
| 6847 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6848 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6849 __ bind(Lskip); | |
| 6850 %} | |
| 0 | 6851 ins_pipe(pipe_slow); |
| 6852 %} | |
| 6853 | |
|
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|
6854 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{ |
|
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|
6855 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
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changeset
|
6856 ins_cost(200); |
|
4d9884b01ba6
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diff
changeset
|
6857 expand %{ |
|
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diff
changeset
|
6858 cmovF_regU(cop, cr, dst, src); |
|
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parents:
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changeset
|
6859 %} |
|
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parents:
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changeset
|
6860 %} |
|
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diff
changeset
|
6861 |
| 0 | 6862 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src) |
| 6863 %{ | |
| 6864 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6865 | |
| 6866 ins_cost(200); // XXX | |
| 6867 format %{ "jn$cop skip\t# signed cmove double\n\t" | |
| 6868 "movsd $dst, $src\n" | |
| 6869 "skip:" %} | |
| 4759 | 6870 ins_encode %{ |
| 6871 Label Lskip; | |
| 6872 // Invert sense of branch from sense of CMOV | |
| 6873 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6874 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 6875 __ bind(Lskip); | |
| 6876 %} | |
| 0 | 6877 ins_pipe(pipe_slow); |
| 6878 %} | |
| 6879 | |
| 6880 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src) | |
| 6881 %{ | |
| 6882 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6883 | |
| 6884 ins_cost(200); // XXX | |
| 6885 format %{ "jn$cop skip\t# unsigned cmove double\n\t" | |
| 6886 "movsd $dst, $src\n" | |
| 6887 "skip:" %} | |
| 4759 | 6888 ins_encode %{ |
| 6889 Label Lskip; | |
| 6890 // Invert sense of branch from sense of CMOV | |
| 6891 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6892 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 6893 __ bind(Lskip); | |
| 6894 %} | |
| 0 | 6895 ins_pipe(pipe_slow); |
| 6896 %} | |
| 6897 | |
|
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changeset
|
6898 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{ |
|
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diff
changeset
|
6899 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
parents:
403
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changeset
|
6900 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
6901 expand %{ |
|
4d9884b01ba6
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parents:
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diff
changeset
|
6902 cmovD_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
6903 %} |
|
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parents:
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changeset
|
6904 %} |
|
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|
6905 |
| 0 | 6906 //----------Arithmetic Instructions-------------------------------------------- |
| 6907 //----------Addition Instructions---------------------------------------------- | |
| 6908 | |
| 12323 | 6909 instruct addExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr) |
| 6910 %{ | |
| 6911 match(AddExactI dst src); | |
| 6912 effect(DEF cr); | |
| 6913 | |
| 6914 format %{ "addl $dst, $src\t# addExact int" %} | |
| 6915 ins_encode %{ | |
| 6916 __ addl($dst$$Register, $src$$Register); | |
| 6917 %} | |
| 6918 ins_pipe(ialu_reg_reg); | |
| 6919 %} | |
| 6920 | |
| 6921 instruct addExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr) | |
| 6922 %{ | |
| 6923 match(AddExactI dst src); | |
| 6924 effect(DEF cr); | |
| 6925 | |
| 6926 format %{ "addl $dst, $src\t# addExact int" %} | |
| 6927 ins_encode %{ | |
| 6928 __ addl($dst$$Register, $src$$constant); | |
| 6929 %} | |
| 6930 ins_pipe(ialu_reg_reg); | |
| 6931 %} | |
| 6932 | |
|
12972
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|
6933 instruct addExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) |
|
59e8ad757e19
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diff
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|
6934 %{ |
|
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diff
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|
6935 match(AddExactI dst (LoadI src)); |
|
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diff
changeset
|
6936 effect(DEF cr); |
|
59e8ad757e19
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diff
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|
6937 |
|
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changeset
|
6938 ins_cost(125); // XXX |
|
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diff
changeset
|
6939 format %{ "addl $dst, $src\t# addExact int" %} |
|
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rbackman
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diff
changeset
|
6940 ins_encode %{ |
|
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|
6941 __ addl($dst$$Register, $src$$Address); |
|
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changeset
|
6942 %} |
|
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|
6943 |
|
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changeset
|
6944 ins_pipe(ialu_reg_mem); |
|
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changeset
|
6945 %} |
|
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|
6946 |
|
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changeset
|
6947 instruct addExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) |
|
59e8ad757e19
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|
6948 %{ |
|
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diff
changeset
|
6949 match(AddExactL dst src); |
|
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diff
changeset
|
6950 effect(DEF cr); |
|
59e8ad757e19
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diff
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|
6951 |
|
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diff
changeset
|
6952 format %{ "addq $dst, $src\t# addExact long" %} |
|
59e8ad757e19
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diff
changeset
|
6953 ins_encode %{ |
|
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|
6954 __ addq($dst$$Register, $src$$Register); |
|
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diff
changeset
|
6955 %} |
|
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diff
changeset
|
6956 ins_pipe(ialu_reg_reg); |
|
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diff
changeset
|
6957 %} |
|
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diff
changeset
|
6958 |
|
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6959 instruct addExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr) |
|
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|
6960 %{ |
|
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|
6961 match(AddExactL dst src); |
|
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|
6962 effect(DEF cr); |
|
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|
6963 |
|
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|
6964 format %{ "addq $dst, $src\t# addExact long" %} |
|
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|
6965 ins_encode %{ |
|
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|
6966 __ addq($dst$$Register, $src$$constant); |
|
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|
6967 %} |
|
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|
6968 ins_pipe(ialu_reg_reg); |
|
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|
6969 %} |
|
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|
6970 |
|
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|
6971 instruct addExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr) |
|
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|
6972 %{ |
|
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|
6973 match(AddExactL dst (LoadL src)); |
|
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|
6974 effect(DEF cr); |
|
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|
6975 |
|
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|
6976 ins_cost(125); // XXX |
|
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|
6977 format %{ "addq $dst, $src\t# addExact long" %} |
|
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|
6978 ins_encode %{ |
|
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|
6979 __ addq($dst$$Register, $src$$Address); |
|
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|
6980 %} |
|
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|
6981 |
|
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|
6982 ins_pipe(ialu_reg_mem); |
|
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|
6983 %} |
|
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|
6984 |
| 0 | 6985 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) |
| 6986 %{ | |
| 6987 match(Set dst (AddI dst src)); | |
| 6988 effect(KILL cr); | |
| 6989 | |
| 6990 format %{ "addl $dst, $src\t# int" %} | |
| 6991 opcode(0x03); | |
| 6992 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 6993 ins_pipe(ialu_reg_reg); | |
| 6994 %} | |
| 6995 | |
| 6996 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 6997 %{ | |
| 6998 match(Set dst (AddI dst src)); | |
| 6999 effect(KILL cr); | |
| 7000 | |
| 7001 format %{ "addl $dst, $src\t# int" %} | |
| 7002 opcode(0x81, 0x00); /* /0 id */ | |
| 7003 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 7004 ins_pipe( ialu_reg ); | |
| 7005 %} | |
| 7006 | |
| 7007 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7008 %{ | |
| 7009 match(Set dst (AddI dst (LoadI src))); | |
| 7010 effect(KILL cr); | |
| 7011 | |
| 7012 ins_cost(125); // XXX | |
| 7013 format %{ "addl $dst, $src\t# int" %} | |
| 7014 opcode(0x03); | |
| 7015 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 7016 ins_pipe(ialu_reg_mem); | |
| 7017 %} | |
| 7018 | |
| 7019 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 7020 %{ | |
| 7021 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7022 effect(KILL cr); | |
| 7023 | |
| 7024 ins_cost(150); // XXX | |
| 7025 format %{ "addl $dst, $src\t# int" %} | |
| 7026 opcode(0x01); /* Opcode 01 /r */ | |
| 7027 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 7028 ins_pipe(ialu_mem_reg); | |
| 7029 %} | |
| 7030 | |
| 7031 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 7032 %{ | |
| 7033 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7034 effect(KILL cr); | |
| 7035 | |
| 7036 ins_cost(125); // XXX | |
| 7037 format %{ "addl $dst, $src\t# int" %} | |
| 7038 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7039 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 7040 ins_pipe(ialu_mem_imm); | |
| 7041 %} | |
| 7042 | |
| 7043 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 7044 %{ | |
| 7045 predicate(UseIncDec); | |
| 7046 match(Set dst (AddI dst src)); | |
| 7047 effect(KILL cr); | |
| 7048 | |
| 7049 format %{ "incl $dst\t# int" %} | |
| 7050 opcode(0xFF, 0x00); // FF /0 | |
| 7051 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7052 ins_pipe(ialu_reg); | |
| 7053 %} | |
| 7054 | |
| 7055 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr) | |
| 7056 %{ | |
| 7057 predicate(UseIncDec); | |
| 7058 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7059 effect(KILL cr); | |
| 7060 | |
| 7061 ins_cost(125); // XXX | |
| 7062 format %{ "incl $dst\t# int" %} | |
| 7063 opcode(0xFF); /* Opcode FF /0 */ | |
| 7064 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 7065 ins_pipe(ialu_mem_imm); | |
| 7066 %} | |
| 7067 | |
| 7068 // XXX why does that use AddI | |
| 7069 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr) | |
| 7070 %{ | |
| 7071 predicate(UseIncDec); | |
| 7072 match(Set dst (AddI dst src)); | |
| 7073 effect(KILL cr); | |
| 7074 | |
| 7075 format %{ "decl $dst\t# int" %} | |
| 7076 opcode(0xFF, 0x01); // FF /1 | |
| 7077 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7078 ins_pipe(ialu_reg); | |
| 7079 %} | |
| 7080 | |
| 7081 // XXX why does that use AddI | |
| 7082 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr) | |
| 7083 %{ | |
| 7084 predicate(UseIncDec); | |
| 7085 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7086 effect(KILL cr); | |
| 7087 | |
| 7088 ins_cost(125); // XXX | |
| 7089 format %{ "decl $dst\t# int" %} | |
| 7090 opcode(0xFF); /* Opcode FF /1 */ | |
| 7091 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 7092 ins_pipe(ialu_mem_imm); | |
| 7093 %} | |
| 7094 | |
| 7095 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1) | |
| 7096 %{ | |
| 7097 match(Set dst (AddI src0 src1)); | |
| 7098 | |
| 7099 ins_cost(110); | |
| 7100 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %} | |
| 7101 opcode(0x8D); /* 0x8D /r */ | |
| 7102 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 7103 ins_pipe(ialu_reg_reg); | |
| 7104 %} | |
| 7105 | |
| 7106 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 7107 %{ | |
| 7108 match(Set dst (AddL dst src)); | |
| 7109 effect(KILL cr); | |
| 7110 | |
| 7111 format %{ "addq $dst, $src\t# long" %} | |
| 7112 opcode(0x03); | |
| 7113 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7114 ins_pipe(ialu_reg_reg); | |
| 7115 %} | |
| 7116 | |
| 7117 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 7118 %{ | |
| 7119 match(Set dst (AddL dst src)); | |
| 7120 effect(KILL cr); | |
| 7121 | |
| 7122 format %{ "addq $dst, $src\t# long" %} | |
| 7123 opcode(0x81, 0x00); /* /0 id */ | |
| 7124 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7125 ins_pipe( ialu_reg ); | |
| 7126 %} | |
| 7127 | |
| 7128 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7129 %{ | |
| 7130 match(Set dst (AddL dst (LoadL src))); | |
| 7131 effect(KILL cr); | |
| 7132 | |
| 7133 ins_cost(125); // XXX | |
| 7134 format %{ "addq $dst, $src\t# long" %} | |
| 7135 opcode(0x03); | |
| 7136 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 7137 ins_pipe(ialu_reg_mem); | |
| 7138 %} | |
| 7139 | |
| 7140 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 7141 %{ | |
| 7142 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7143 effect(KILL cr); | |
| 7144 | |
| 7145 ins_cost(150); // XXX | |
| 7146 format %{ "addq $dst, $src\t# long" %} | |
| 7147 opcode(0x01); /* Opcode 01 /r */ | |
| 7148 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7149 ins_pipe(ialu_mem_reg); | |
| 7150 %} | |
| 7151 | |
| 7152 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 7153 %{ | |
| 7154 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7155 effect(KILL cr); | |
| 7156 | |
| 7157 ins_cost(125); // XXX | |
| 7158 format %{ "addq $dst, $src\t# long" %} | |
| 7159 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7160 ins_encode(REX_mem_wide(dst), | |
| 7161 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 7162 ins_pipe(ialu_mem_imm); | |
| 7163 %} | |
| 7164 | |
| 7165 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr) | |
| 7166 %{ | |
| 7167 predicate(UseIncDec); | |
| 7168 match(Set dst (AddL dst src)); | |
| 7169 effect(KILL cr); | |
| 7170 | |
| 7171 format %{ "incq $dst\t# long" %} | |
| 7172 opcode(0xFF, 0x00); // FF /0 | |
| 7173 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7174 ins_pipe(ialu_reg); | |
| 7175 %} | |
| 7176 | |
| 7177 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr) | |
| 7178 %{ | |
| 7179 predicate(UseIncDec); | |
| 7180 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7181 effect(KILL cr); | |
| 7182 | |
| 7183 ins_cost(125); // XXX | |
| 7184 format %{ "incq $dst\t# long" %} | |
| 7185 opcode(0xFF); /* Opcode FF /0 */ | |
| 7186 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 7187 ins_pipe(ialu_mem_imm); | |
| 7188 %} | |
| 7189 | |
| 7190 // XXX why does that use AddL | |
| 7191 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr) | |
| 7192 %{ | |
| 7193 predicate(UseIncDec); | |
| 7194 match(Set dst (AddL dst src)); | |
| 7195 effect(KILL cr); | |
| 7196 | |
| 7197 format %{ "decq $dst\t# long" %} | |
| 7198 opcode(0xFF, 0x01); // FF /1 | |
| 7199 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7200 ins_pipe(ialu_reg); | |
| 7201 %} | |
| 7202 | |
| 7203 // XXX why does that use AddL | |
| 7204 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr) | |
| 7205 %{ | |
| 7206 predicate(UseIncDec); | |
| 7207 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7208 effect(KILL cr); | |
| 7209 | |
| 7210 ins_cost(125); // XXX | |
| 7211 format %{ "decq $dst\t# long" %} | |
| 7212 opcode(0xFF); /* Opcode FF /1 */ | |
| 7213 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 7214 ins_pipe(ialu_mem_imm); | |
| 7215 %} | |
| 7216 | |
| 7217 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1) | |
| 7218 %{ | |
| 7219 match(Set dst (AddL src0 src1)); | |
| 7220 | |
| 7221 ins_cost(110); | |
| 7222 format %{ "leaq $dst, [$src0 + $src1]\t# long" %} | |
| 7223 opcode(0x8D); /* 0x8D /r */ | |
| 7224 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 7225 ins_pipe(ialu_reg_reg); | |
| 7226 %} | |
| 7227 | |
| 7228 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr) | |
| 7229 %{ | |
| 7230 match(Set dst (AddP dst src)); | |
| 7231 effect(KILL cr); | |
| 7232 | |
| 7233 format %{ "addq $dst, $src\t# ptr" %} | |
| 7234 opcode(0x03); | |
| 7235 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7236 ins_pipe(ialu_reg_reg); | |
| 7237 %} | |
| 7238 | |
| 7239 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr) | |
| 7240 %{ | |
| 7241 match(Set dst (AddP dst src)); | |
| 7242 effect(KILL cr); | |
| 7243 | |
| 7244 format %{ "addq $dst, $src\t# ptr" %} | |
| 7245 opcode(0x81, 0x00); /* /0 id */ | |
| 7246 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7247 ins_pipe( ialu_reg ); | |
| 7248 %} | |
| 7249 | |
| 7250 // XXX addP mem ops ???? | |
| 7251 | |
| 7252 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1) | |
| 7253 %{ | |
| 7254 match(Set dst (AddP src0 src1)); | |
| 7255 | |
| 7256 ins_cost(110); | |
| 7257 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %} | |
| 7258 opcode(0x8D); /* 0x8D /r */ | |
| 7259 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX | |
| 7260 ins_pipe(ialu_reg_reg); | |
| 7261 %} | |
| 7262 | |
| 7263 instruct checkCastPP(rRegP dst) | |
| 7264 %{ | |
| 7265 match(Set dst (CheckCastPP dst)); | |
| 7266 | |
| 7267 size(0); | |
| 7268 format %{ "# checkcastPP of $dst" %} | |
| 7269 ins_encode(/* empty encoding */); | |
| 7270 ins_pipe(empty); | |
| 7271 %} | |
| 7272 | |
| 7273 instruct castPP(rRegP dst) | |
| 7274 %{ | |
| 7275 match(Set dst (CastPP dst)); | |
| 7276 | |
| 7277 size(0); | |
| 7278 format %{ "# castPP of $dst" %} | |
| 7279 ins_encode(/* empty encoding */); | |
| 7280 ins_pipe(empty); | |
| 7281 %} | |
| 7282 | |
| 7283 instruct castII(rRegI dst) | |
| 7284 %{ | |
| 7285 match(Set dst (CastII dst)); | |
| 7286 | |
| 7287 size(0); | |
| 7288 format %{ "# castII of $dst" %} | |
| 7289 ins_encode(/* empty encoding */); | |
| 7290 ins_cost(0); | |
| 7291 ins_pipe(empty); | |
| 7292 %} | |
| 7293 | |
| 7294 // LoadP-locked same as a regular LoadP when used with compare-swap | |
| 7295 instruct loadPLocked(rRegP dst, memory mem) | |
| 7296 %{ | |
| 7297 match(Set dst (LoadPLocked mem)); | |
| 7298 | |
| 7299 ins_cost(125); // XXX | |
| 7300 format %{ "movq $dst, $mem\t# ptr locked" %} | |
| 7301 opcode(0x8B); | |
| 7302 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 7303 ins_pipe(ialu_reg_mem); // XXX | |
| 7304 %} | |
| 7305 | |
| 7306 // Conditional-store of the updated heap-top. | |
| 7307 // Used during allocation of the shared heap. | |
| 7308 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 7309 | |
| 7310 instruct storePConditional(memory heap_top_ptr, | |
| 7311 rax_RegP oldval, rRegP newval, | |
| 7312 rFlagsReg cr) | |
| 7313 %{ | |
| 7314 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
|
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7315 |
| 0 | 7316 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " |
| 7317 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} | |
| 7318 opcode(0x0F, 0xB1); | |
| 7319 ins_encode(lock_prefix, | |
| 7320 REX_reg_mem_wide(newval, heap_top_ptr), | |
| 7321 OpcP, OpcS, | |
| 7322 reg_mem(newval, heap_top_ptr)); | |
| 7323 ins_pipe(pipe_cmpxchg); | |
| 7324 %} | |
| 7325 | |
|
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7326 // Conditional-store of an int value. |
|
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7327 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
|
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7328 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr) |
|
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7329 %{ |
|
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7330 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
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|
7331 effect(KILL oldval); |
|
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7332 |
|
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|
7333 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 7334 opcode(0x0F, 0xB1); |
| 7335 ins_encode(lock_prefix, | |
|
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7336 REX_reg_mem(newval, mem), |
| 0 | 7337 OpcP, OpcS, |
|
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7338 reg_mem(newval, mem)); |
| 0 | 7339 ins_pipe(pipe_cmpxchg); |
| 7340 %} | |
| 7341 | |
|
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7342 // Conditional-store of a long value. |
|
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7343 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
|
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7344 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr) |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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415
diff
changeset
|
7345 %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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415
diff
changeset
|
7346 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
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415
diff
changeset
|
7347 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7348 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
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415
diff
changeset
|
7349 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 7350 opcode(0x0F, 0xB1); |
| 7351 ins_encode(lock_prefix, | |
|
420
a1980da045cc
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415
diff
changeset
|
7352 REX_reg_mem_wide(newval, mem), |
| 0 | 7353 OpcP, OpcS, |
|
420
a1980da045cc
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415
diff
changeset
|
7354 reg_mem(newval, mem)); |
| 0 | 7355 ins_pipe(pipe_cmpxchg); |
| 7356 %} | |
| 7357 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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415
diff
changeset
|
7358 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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415
diff
changeset
|
7359 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them |
| 0 | 7360 instruct compareAndSwapP(rRegI res, |
| 7361 memory mem_ptr, | |
| 7362 rax_RegP oldval, rRegP newval, | |
| 7363 rFlagsReg cr) | |
| 7364 %{ | |
|
6795
7eca5de9e0b6
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6725
diff
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|
7365 predicate(VM_Version::supports_cx8()); |
| 0 | 7366 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
| 7367 effect(KILL cr, KILL oldval); | |
| 7368 | |
| 7369 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 7370 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7371 "sete $res\n\t" | |
| 7372 "movzbl $res, $res" %} | |
| 7373 opcode(0x0F, 0xB1); | |
| 7374 ins_encode(lock_prefix, | |
| 7375 REX_reg_mem_wide(newval, mem_ptr), | |
| 7376 OpcP, OpcS, | |
| 7377 reg_mem(newval, mem_ptr), | |
| 7378 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7379 REX_reg_breg(res, res), // movzbl | |
| 7380 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7381 ins_pipe( pipe_cmpxchg ); | |
| 7382 %} | |
| 7383 | |
| 7384 instruct compareAndSwapL(rRegI res, | |
| 7385 memory mem_ptr, | |
| 7386 rax_RegL oldval, rRegL newval, | |
| 7387 rFlagsReg cr) | |
| 7388 %{ | |
|
6795
7eca5de9e0b6
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6725
diff
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|
7389 predicate(VM_Version::supports_cx8()); |
| 0 | 7390 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
| 7391 effect(KILL cr, KILL oldval); | |
| 7392 | |
| 7393 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 7394 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7395 "sete $res\n\t" | |
| 7396 "movzbl $res, $res" %} | |
| 7397 opcode(0x0F, 0xB1); | |
| 7398 ins_encode(lock_prefix, | |
| 7399 REX_reg_mem_wide(newval, mem_ptr), | |
| 7400 OpcP, OpcS, | |
| 7401 reg_mem(newval, mem_ptr), | |
| 7402 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7403 REX_reg_breg(res, res), // movzbl | |
| 7404 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7405 ins_pipe( pipe_cmpxchg ); | |
| 7406 %} | |
| 7407 | |
| 7408 instruct compareAndSwapI(rRegI res, | |
| 7409 memory mem_ptr, | |
| 7410 rax_RegI oldval, rRegI newval, | |
| 7411 rFlagsReg cr) | |
| 7412 %{ | |
| 7413 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 7414 effect(KILL cr, KILL oldval); | |
| 7415 | |
| 7416 format %{ "cmpxchgl $mem_ptr,$newval\t# " | |
| 7417 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7418 "sete $res\n\t" | |
| 7419 "movzbl $res, $res" %} | |
| 7420 opcode(0x0F, 0xB1); | |
| 7421 ins_encode(lock_prefix, | |
| 7422 REX_reg_mem(newval, mem_ptr), | |
| 7423 OpcP, OpcS, | |
| 7424 reg_mem(newval, mem_ptr), | |
| 7425 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7426 REX_reg_breg(res, res), // movzbl | |
| 7427 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7428 ins_pipe( pipe_cmpxchg ); | |
| 7429 %} | |
| 7430 | |
| 7431 | |
|
113
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|
7432 instruct compareAndSwapN(rRegI res, |
|
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changeset
|
7433 memory mem_ptr, |
|
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diff
changeset
|
7434 rax_RegN oldval, rRegN newval, |
|
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|
7435 rFlagsReg cr) %{ |
|
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diff
changeset
|
7436 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
|
ba764ed4b6f2
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diff
changeset
|
7437 effect(KILL cr, KILL oldval); |
|
ba764ed4b6f2
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71
diff
changeset
|
7438 |
|
ba764ed4b6f2
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diff
changeset
|
7439 format %{ "cmpxchgl $mem_ptr,$newval\t# " |
|
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changeset
|
7440 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" |
|
ba764ed4b6f2
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diff
changeset
|
7441 "sete $res\n\t" |
|
ba764ed4b6f2
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diff
changeset
|
7442 "movzbl $res, $res" %} |
|
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71
diff
changeset
|
7443 opcode(0x0F, 0xB1); |
|
ba764ed4b6f2
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changeset
|
7444 ins_encode(lock_prefix, |
|
ba764ed4b6f2
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changeset
|
7445 REX_reg_mem(newval, mem_ptr), |
|
ba764ed4b6f2
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diff
changeset
|
7446 OpcP, OpcS, |
|
ba764ed4b6f2
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coleenp
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diff
changeset
|
7447 reg_mem(newval, mem_ptr), |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
7448 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete |
|
ba764ed4b6f2
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diff
changeset
|
7449 REX_reg_breg(res, res), // movzbl |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
7450 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
7451 ins_pipe( pipe_cmpxchg ); |
|
ba764ed4b6f2
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71
diff
changeset
|
7452 %} |
|
ba764ed4b6f2
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71
diff
changeset
|
7453 |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7454 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7455 predicate(n->as_LoadStore()->result_not_used()); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7456 match(Set dummy (GetAndAddI mem add)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7457 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7458 format %{ "ADDL [$mem],$add" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7459 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7460 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
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roland
parents:
6725
diff
changeset
|
7461 __ addl($mem$$Address, $add$$constant); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7462 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7463 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7464 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7465 |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7466 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7467 match(Set newval (GetAndAddI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7468 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7469 format %{ "XADDL [$mem],$newval" %} |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7470 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7471 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
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6725
diff
changeset
|
7472 __ xaddl($mem$$Address, $newval$$Register); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7473 %} |
|
7eca5de9e0b6
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6725
diff
changeset
|
7474 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7475 %} |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7476 |
|
10139
35c15dad89ea
8011901: Unsafe.getAndAddLong(obj, off, delta) does not work properly with long deltas
roland
parents:
9154
diff
changeset
|
7477 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{ |
|
6795
7eca5de9e0b6
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6725
diff
changeset
|
7478 predicate(n->as_LoadStore()->result_not_used()); |
|
7eca5de9e0b6
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6725
diff
changeset
|
7479 match(Set dummy (GetAndAddL mem add)); |
|
7eca5de9e0b6
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6725
diff
changeset
|
7480 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7481 format %{ "ADDQ [$mem],$add" %} |
|
7eca5de9e0b6
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6725
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changeset
|
7482 ins_encode %{ |
|
7eca5de9e0b6
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diff
changeset
|
7483 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
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6725
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changeset
|
7484 __ addq($mem$$Address, $add$$constant); |
|
7eca5de9e0b6
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changeset
|
7485 %} |
|
7eca5de9e0b6
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changeset
|
7486 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
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6725
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changeset
|
7487 %} |
|
7eca5de9e0b6
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changeset
|
7488 |
|
7eca5de9e0b6
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changeset
|
7489 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{ |
|
7eca5de9e0b6
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6725
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changeset
|
7490 match(Set newval (GetAndAddL mem newval)); |
|
7eca5de9e0b6
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6725
diff
changeset
|
7491 effect(KILL cr); |
|
7eca5de9e0b6
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changeset
|
7492 format %{ "XADDQ [$mem],$newval" %} |
|
7eca5de9e0b6
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|
7493 ins_encode %{ |
|
7eca5de9e0b6
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diff
changeset
|
7494 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
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changeset
|
7495 __ xaddq($mem$$Address, $newval$$Register); |
|
7eca5de9e0b6
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changeset
|
7496 %} |
|
7eca5de9e0b6
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changeset
|
7497 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
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changeset
|
7498 %} |
|
7eca5de9e0b6
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changeset
|
7499 |
|
7eca5de9e0b6
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changeset
|
7500 instruct xchgI( memory mem, rRegI newval) %{ |
|
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|
7501 match(Set newval (GetAndSetI mem newval)); |
|
7eca5de9e0b6
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changeset
|
7502 format %{ "XCHGL $newval,[$mem]" %} |
|
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|
7503 ins_encode %{ |
|
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changeset
|
7504 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
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|
7505 %} |
|
7eca5de9e0b6
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changeset
|
7506 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
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changeset
|
7507 %} |
|
7eca5de9e0b6
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changeset
|
7508 |
|
7eca5de9e0b6
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changeset
|
7509 instruct xchgL( memory mem, rRegL newval) %{ |
|
7eca5de9e0b6
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changeset
|
7510 match(Set newval (GetAndSetL mem newval)); |
|
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changeset
|
7511 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
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changeset
|
7512 ins_encode %{ |
|
7eca5de9e0b6
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changeset
|
7513 __ xchgq($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
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|
7514 %} |
|
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parents:
6725
diff
changeset
|
7515 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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diff
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|
7516 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7517 |
|
7eca5de9e0b6
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6725
diff
changeset
|
7518 instruct xchgP( memory mem, rRegP newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7519 match(Set newval (GetAndSetP mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7520 format %{ "XCHGQ $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
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|
7521 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7522 __ xchgq($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7523 %} |
|
7eca5de9e0b6
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parents:
6725
diff
changeset
|
7524 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7525 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7526 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7527 instruct xchgN( memory mem, rRegN newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7528 match(Set newval (GetAndSetN mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7529 format %{ "XCHGL $newval,$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7530 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7531 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7532 %} |
|
7eca5de9e0b6
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6725
diff
changeset
|
7533 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
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roland
parents:
6725
diff
changeset
|
7534 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7535 |
| 0 | 7536 //----------Subtraction Instructions------------------------------------------- |
| 7537 | |
| 7538 // Integer Subtraction Instructions | |
| 7539 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7540 %{ | |
| 7541 match(Set dst (SubI dst src)); | |
| 7542 effect(KILL cr); | |
| 7543 | |
| 7544 format %{ "subl $dst, $src\t# int" %} | |
| 7545 opcode(0x2B); | |
| 7546 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 7547 ins_pipe(ialu_reg_reg); | |
| 7548 %} | |
| 7549 | |
| 7550 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 7551 %{ | |
| 7552 match(Set dst (SubI dst src)); | |
| 7553 effect(KILL cr); | |
| 7554 | |
| 7555 format %{ "subl $dst, $src\t# int" %} | |
| 7556 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 7557 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 7558 ins_pipe(ialu_reg); | |
| 7559 %} | |
| 7560 | |
| 7561 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7562 %{ | |
| 7563 match(Set dst (SubI dst (LoadI src))); | |
| 7564 effect(KILL cr); | |
| 7565 | |
| 7566 ins_cost(125); | |
| 7567 format %{ "subl $dst, $src\t# int" %} | |
| 7568 opcode(0x2B); | |
| 7569 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 7570 ins_pipe(ialu_reg_mem); | |
| 7571 %} | |
| 7572 | |
| 7573 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 7574 %{ | |
| 7575 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 7576 effect(KILL cr); | |
| 7577 | |
| 7578 ins_cost(150); | |
| 7579 format %{ "subl $dst, $src\t# int" %} | |
| 7580 opcode(0x29); /* Opcode 29 /r */ | |
| 7581 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 7582 ins_pipe(ialu_mem_reg); | |
| 7583 %} | |
| 7584 | |
| 7585 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 7586 %{ | |
| 7587 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 7588 effect(KILL cr); | |
| 7589 | |
| 7590 ins_cost(125); // XXX | |
| 7591 format %{ "subl $dst, $src\t# int" %} | |
| 7592 opcode(0x81); /* Opcode 81 /5 id */ | |
| 7593 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 7594 ins_pipe(ialu_mem_imm); | |
| 7595 %} | |
| 7596 | |
|
12972
59e8ad757e19
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diff
changeset
|
7597 instruct subExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
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diff
changeset
|
7598 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
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parents:
12334
diff
changeset
|
7599 match(SubExactI dst src); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7600 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7601 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
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diff
changeset
|
7602 format %{ "subl $dst, $src\t# subExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7603 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7604 __ subl($dst$$Register, $src$$Register); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7605 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7606 ins_pipe(ialu_reg_reg); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7607 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7608 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7609 instruct subExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7610 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7611 match(SubExactI dst src); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7612 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7613 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7614 format %{ "subl $dst, $src\t# subExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7615 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7616 __ subl($dst$$Register, $src$$constant); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7617 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7618 ins_pipe(ialu_reg_reg); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7619 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7620 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7621 instruct subExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7622 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7623 match(SubExactI dst (LoadI src)); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7624 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7625 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7626 ins_cost(125); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7627 format %{ "subl $dst, $src\t# subExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7628 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7629 __ subl($dst$$Register, $src$$Address); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7630 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7631 ins_pipe(ialu_reg_mem); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7632 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7633 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7634 instruct subExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7635 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7636 match(SubExactL dst src); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7637 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7638 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7639 format %{ "subq $dst, $src\t# subExact long" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7640 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7641 __ subq($dst$$Register, $src$$Register); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7642 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7643 ins_pipe(ialu_reg_reg); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7644 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7645 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7646 instruct subExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7647 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7648 match(SubExactL dst (LoadL src)); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7649 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7650 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7651 format %{ "subq $dst, $src\t# subExact long" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7652 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7653 __ subq($dst$$Register, $src$$constant); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7654 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7655 ins_pipe(ialu_reg_reg); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7656 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7657 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7658 instruct subExactL_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7659 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7660 match(SubExactI dst src); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7661 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7662 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7663 ins_cost(125); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7664 format %{ "subq $dst, $src\t# subExact long" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7665 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7666 __ subq($dst$$Register, $src$$Address); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7667 %} |
|
59e8ad757e19
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rbackman
parents:
12334
diff
changeset
|
7668 ins_pipe(ialu_reg_mem); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7669 %} |
|
59e8ad757e19
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rbackman
parents:
12334
diff
changeset
|
7670 |
| 0 | 7671 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) |
| 7672 %{ | |
| 7673 match(Set dst (SubL dst src)); | |
| 7674 effect(KILL cr); | |
| 7675 | |
| 7676 format %{ "subq $dst, $src\t# long" %} | |
| 7677 opcode(0x2B); | |
| 7678 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7679 ins_pipe(ialu_reg_reg); | |
| 7680 %} | |
| 7681 | |
| 7682 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr) | |
| 7683 %{ | |
| 7684 match(Set dst (SubL dst src)); | |
| 7685 effect(KILL cr); | |
| 7686 | |
| 7687 format %{ "subq $dst, $src\t# long" %} | |
| 7688 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 7689 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7690 ins_pipe(ialu_reg); | |
| 7691 %} | |
| 7692 | |
| 7693 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7694 %{ | |
| 7695 match(Set dst (SubL dst (LoadL src))); | |
| 7696 effect(KILL cr); | |
| 7697 | |
| 7698 ins_cost(125); | |
| 7699 format %{ "subq $dst, $src\t# long" %} | |
| 7700 opcode(0x2B); | |
| 7701 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 7702 ins_pipe(ialu_reg_mem); | |
| 7703 %} | |
| 7704 | |
| 7705 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 7706 %{ | |
| 7707 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 7708 effect(KILL cr); | |
| 7709 | |
| 7710 ins_cost(150); | |
| 7711 format %{ "subq $dst, $src\t# long" %} | |
| 7712 opcode(0x29); /* Opcode 29 /r */ | |
| 7713 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7714 ins_pipe(ialu_mem_reg); | |
| 7715 %} | |
| 7716 | |
| 7717 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 7718 %{ | |
| 7719 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 7720 effect(KILL cr); | |
| 7721 | |
| 7722 ins_cost(125); // XXX | |
| 7723 format %{ "subq $dst, $src\t# long" %} | |
| 7724 opcode(0x81); /* Opcode 81 /5 id */ | |
| 7725 ins_encode(REX_mem_wide(dst), | |
| 7726 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 7727 ins_pipe(ialu_mem_imm); | |
| 7728 %} | |
| 7729 | |
| 7730 // Subtract from a pointer | |
| 7731 // XXX hmpf??? | |
| 7732 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr) | |
| 7733 %{ | |
| 7734 match(Set dst (AddP dst (SubI zero src))); | |
| 7735 effect(KILL cr); | |
| 7736 | |
| 7737 format %{ "subq $dst, $src\t# ptr - int" %} | |
| 7738 opcode(0x2B); | |
| 7739 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7740 ins_pipe(ialu_reg_reg); | |
| 7741 %} | |
| 7742 | |
| 7743 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 7744 %{ | |
| 7745 match(Set dst (SubI zero dst)); | |
| 7746 effect(KILL cr); | |
| 7747 | |
| 7748 format %{ "negl $dst\t# int" %} | |
| 7749 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7750 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7751 ins_pipe(ialu_reg); | |
| 7752 %} | |
| 7753 | |
| 7754 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr) | |
| 7755 %{ | |
| 7756 match(Set dst (StoreI dst (SubI zero (LoadI dst)))); | |
| 7757 effect(KILL cr); | |
| 7758 | |
| 7759 format %{ "negl $dst\t# int" %} | |
| 7760 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7761 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7762 ins_pipe(ialu_reg); | |
| 7763 %} | |
| 7764 | |
| 7765 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr) | |
| 7766 %{ | |
| 7767 match(Set dst (SubL zero dst)); | |
| 7768 effect(KILL cr); | |
| 7769 | |
| 7770 format %{ "negq $dst\t# long" %} | |
| 7771 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7772 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7773 ins_pipe(ialu_reg); | |
| 7774 %} | |
| 7775 | |
| 7776 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr) | |
| 7777 %{ | |
| 7778 match(Set dst (StoreL dst (SubL zero (LoadL dst)))); | |
| 7779 effect(KILL cr); | |
| 7780 | |
| 7781 format %{ "negq $dst\t# long" %} | |
| 7782 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7783 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7784 ins_pipe(ialu_reg); | |
| 7785 %} | |
| 7786 | |
|
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|
7787 instruct negExactI_rReg(rax_RegI dst, rFlagsReg cr) |
|
59e8ad757e19
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|
7788 %{ |
|
59e8ad757e19
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|
7789 match(NegExactI dst); |
|
59e8ad757e19
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|
7790 effect(KILL cr); |
|
59e8ad757e19
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|
7791 |
|
59e8ad757e19
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|
7792 format %{ "negl $dst\t# negExact int" %} |
|
59e8ad757e19
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|
7793 ins_encode %{ |
|
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|
7794 __ negl($dst$$Register); |
|
59e8ad757e19
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|
7795 %} |
|
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|
7796 ins_pipe(ialu_reg); |
|
59e8ad757e19
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|
7797 %} |
|
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|
7798 |
|
59e8ad757e19
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|
7799 instruct negExactL_rReg(rax_RegL dst, rFlagsReg cr) |
|
59e8ad757e19
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|
7800 %{ |
|
59e8ad757e19
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|
7801 match(NegExactL dst); |
|
59e8ad757e19
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parents:
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changeset
|
7802 effect(KILL cr); |
|
59e8ad757e19
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|
7803 |
|
59e8ad757e19
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|
7804 format %{ "negq $dst\t# negExact long" %} |
|
59e8ad757e19
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|
7805 ins_encode %{ |
|
59e8ad757e19
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|
7806 __ negq($dst$$Register); |
|
59e8ad757e19
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|
7807 %} |
|
59e8ad757e19
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|
7808 ins_pipe(ialu_reg); |
|
59e8ad757e19
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|
7809 %} |
|
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|
7810 |
| 0 | 7811 |
| 7812 //----------Multiplication/Division Instructions------------------------------- | |
| 7813 // Integer Multiplication Instructions | |
| 7814 // Multiply Register | |
| 7815 | |
| 7816 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7817 %{ | |
| 7818 match(Set dst (MulI dst src)); | |
| 7819 effect(KILL cr); | |
| 7820 | |
| 7821 ins_cost(300); | |
| 7822 format %{ "imull $dst, $src\t# int" %} | |
| 7823 opcode(0x0F, 0xAF); | |
| 7824 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 7825 ins_pipe(ialu_reg_reg_alu0); | |
| 7826 %} | |
| 7827 | |
| 7828 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) | |
| 7829 %{ | |
| 7830 match(Set dst (MulI src imm)); | |
| 7831 effect(KILL cr); | |
| 7832 | |
| 7833 ins_cost(300); | |
| 7834 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 7835 opcode(0x69); /* 69 /r id */ | |
| 7836 ins_encode(REX_reg_reg(dst, src), | |
| 7837 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 7838 ins_pipe(ialu_reg_reg_alu0); | |
| 7839 %} | |
| 7840 | |
| 7841 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7842 %{ | |
| 7843 match(Set dst (MulI dst (LoadI src))); | |
| 7844 effect(KILL cr); | |
| 7845 | |
| 7846 ins_cost(350); | |
| 7847 format %{ "imull $dst, $src\t# int" %} | |
| 7848 opcode(0x0F, 0xAF); | |
| 7849 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 7850 ins_pipe(ialu_reg_mem_alu0); | |
| 7851 %} | |
| 7852 | |
| 7853 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) | |
| 7854 %{ | |
| 7855 match(Set dst (MulI (LoadI src) imm)); | |
| 7856 effect(KILL cr); | |
| 7857 | |
| 7858 ins_cost(300); | |
| 7859 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 7860 opcode(0x69); /* 69 /r id */ | |
| 7861 ins_encode(REX_reg_mem(dst, src), | |
| 7862 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 7863 ins_pipe(ialu_reg_mem_alu0); | |
| 7864 %} | |
| 7865 | |
| 7866 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 7867 %{ | |
| 7868 match(Set dst (MulL dst src)); | |
| 7869 effect(KILL cr); | |
| 7870 | |
| 7871 ins_cost(300); | |
| 7872 format %{ "imulq $dst, $src\t# long" %} | |
| 7873 opcode(0x0F, 0xAF); | |
| 7874 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 7875 ins_pipe(ialu_reg_reg_alu0); | |
| 7876 %} | |
| 7877 | |
| 7878 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) | |
| 7879 %{ | |
| 7880 match(Set dst (MulL src imm)); | |
| 7881 effect(KILL cr); | |
| 7882 | |
| 7883 ins_cost(300); | |
| 7884 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 7885 opcode(0x69); /* 69 /r id */ | |
| 7886 ins_encode(REX_reg_reg_wide(dst, src), | |
| 7887 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 7888 ins_pipe(ialu_reg_reg_alu0); | |
| 7889 %} | |
| 7890 | |
| 7891 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7892 %{ | |
| 7893 match(Set dst (MulL dst (LoadL src))); | |
| 7894 effect(KILL cr); | |
| 7895 | |
| 7896 ins_cost(350); | |
| 7897 format %{ "imulq $dst, $src\t# long" %} | |
| 7898 opcode(0x0F, 0xAF); | |
| 7899 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 7900 ins_pipe(ialu_reg_mem_alu0); | |
| 7901 %} | |
| 7902 | |
| 7903 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) | |
| 7904 %{ | |
| 7905 match(Set dst (MulL (LoadL src) imm)); | |
| 7906 effect(KILL cr); | |
| 7907 | |
| 7908 ins_cost(300); | |
| 7909 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 7910 opcode(0x69); /* 69 /r id */ | |
| 7911 ins_encode(REX_reg_mem_wide(dst, src), | |
| 7912 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 7913 ins_pipe(ialu_reg_mem_alu0); | |
| 7914 %} | |
| 7915 | |
| 145 | 7916 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) |
| 7917 %{ | |
| 7918 match(Set dst (MulHiL src rax)); | |
| 7919 effect(USE_KILL rax, KILL cr); | |
| 7920 | |
| 7921 ins_cost(300); | |
| 7922 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} | |
| 7923 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 7924 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 7925 ins_pipe(ialu_reg_reg_alu0); | |
| 7926 %} | |
| 7927 | |
|
12972
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|
7928 |
|
59e8ad757e19
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|
7929 instruct mulExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr) |
|
59e8ad757e19
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|
7930 %{ |
|
59e8ad757e19
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changeset
|
7931 match(MulExactI dst src); |
|
59e8ad757e19
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parents:
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diff
changeset
|
7932 effect(DEF cr); |
|
59e8ad757e19
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parents:
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diff
changeset
|
7933 |
|
59e8ad757e19
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diff
changeset
|
7934 ins_cost(300); |
|
59e8ad757e19
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changeset
|
7935 format %{ "imull $dst, $src\t# mulExact int" %} |
|
59e8ad757e19
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diff
changeset
|
7936 ins_encode %{ |
|
59e8ad757e19
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diff
changeset
|
7937 __ imull($dst$$Register, $src$$Register); |
|
59e8ad757e19
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|
7938 %} |
|
59e8ad757e19
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|
7939 ins_pipe(ialu_reg_reg_alu0); |
|
59e8ad757e19
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diff
changeset
|
7940 %} |
|
59e8ad757e19
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rbackman
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diff
changeset
|
7941 |
|
59e8ad757e19
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rbackman
parents:
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diff
changeset
|
7942 |
|
59e8ad757e19
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diff
changeset
|
7943 instruct mulExactI_rReg_imm(rax_RegI dst, rRegI src, immI imm, rFlagsReg cr) |
|
59e8ad757e19
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|
7944 %{ |
|
59e8ad757e19
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parents:
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diff
changeset
|
7945 match(MulExactI src imm); |
|
59e8ad757e19
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parents:
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diff
changeset
|
7946 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
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diff
changeset
|
7947 |
|
59e8ad757e19
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rbackman
parents:
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diff
changeset
|
7948 ins_cost(300); |
|
59e8ad757e19
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diff
changeset
|
7949 format %{ "imull $dst, $src, $imm\t# mulExact int" %} |
|
59e8ad757e19
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parents:
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diff
changeset
|
7950 ins_encode %{ |
|
59e8ad757e19
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diff
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|
7951 __ imull($dst$$Register, $src$$Register, $imm$$constant); |
|
59e8ad757e19
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diff
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|
7952 %} |
|
59e8ad757e19
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diff
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|
7953 ins_pipe(ialu_reg_reg_alu0); |
|
59e8ad757e19
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diff
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|
7954 %} |
|
59e8ad757e19
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diff
changeset
|
7955 |
|
59e8ad757e19
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|
7956 instruct mulExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) |
|
59e8ad757e19
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|
7957 %{ |
|
59e8ad757e19
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|
7958 match(MulExactI dst (LoadI src)); |
|
59e8ad757e19
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|
7959 effect(DEF cr); |
|
59e8ad757e19
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diff
changeset
|
7960 |
|
59e8ad757e19
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diff
changeset
|
7961 ins_cost(350); |
|
59e8ad757e19
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|
7962 format %{ "imull $dst, $src\t# mulExact int" %} |
|
59e8ad757e19
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diff
changeset
|
7963 ins_encode %{ |
|
59e8ad757e19
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diff
changeset
|
7964 __ imull($dst$$Register, $src$$Address); |
|
59e8ad757e19
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diff
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|
7965 %} |
|
59e8ad757e19
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diff
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|
7966 ins_pipe(ialu_reg_mem_alu0); |
|
59e8ad757e19
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diff
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|
7967 %} |
|
59e8ad757e19
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diff
changeset
|
7968 |
|
59e8ad757e19
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changeset
|
7969 instruct mulExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) |
|
59e8ad757e19
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diff
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|
7970 %{ |
|
59e8ad757e19
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diff
changeset
|
7971 match(MulExactL dst src); |
|
59e8ad757e19
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parents:
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diff
changeset
|
7972 effect(DEF cr); |
|
59e8ad757e19
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diff
changeset
|
7973 |
|
59e8ad757e19
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diff
changeset
|
7974 ins_cost(300); |
|
59e8ad757e19
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diff
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|
7975 format %{ "imulq $dst, $src\t# mulExact long" %} |
|
59e8ad757e19
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parents:
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diff
changeset
|
7976 ins_encode %{ |
|
59e8ad757e19
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diff
changeset
|
7977 __ imulq($dst$$Register, $src$$Register); |
|
59e8ad757e19
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diff
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|
7978 %} |
|
59e8ad757e19
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|
7979 ins_pipe(ialu_reg_reg_alu0); |
|
59e8ad757e19
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diff
changeset
|
7980 %} |
|
59e8ad757e19
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diff
changeset
|
7981 |
|
59e8ad757e19
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diff
changeset
|
7982 instruct mulExactL_rReg_imm(rax_RegL dst, rRegL src, immL32 imm, rFlagsReg cr) |
|
59e8ad757e19
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diff
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|
7983 %{ |
|
59e8ad757e19
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diff
changeset
|
7984 match(MulExactL src imm); |
|
59e8ad757e19
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parents:
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diff
changeset
|
7985 effect(DEF cr); |
|
59e8ad757e19
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diff
changeset
|
7986 |
|
59e8ad757e19
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diff
changeset
|
7987 ins_cost(300); |
|
59e8ad757e19
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diff
changeset
|
7988 format %{ "imulq $dst, $src, $imm\t# mulExact long" %} |
|
59e8ad757e19
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parents:
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diff
changeset
|
7989 ins_encode %{ |
|
59e8ad757e19
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diff
changeset
|
7990 __ imulq($dst$$Register, $src$$Register, $imm$$constant); |
|
59e8ad757e19
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diff
changeset
|
7991 %} |
|
59e8ad757e19
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diff
changeset
|
7992 ins_pipe(ialu_reg_reg_alu0); |
|
59e8ad757e19
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diff
changeset
|
7993 %} |
|
59e8ad757e19
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diff
changeset
|
7994 |
|
59e8ad757e19
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diff
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|
7995 instruct mulExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr) |
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7996 %{ |
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7997 match(MulExactL dst (LoadL src)); |
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7998 effect(DEF cr); |
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7999 |
|
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8000 ins_cost(350); |
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8001 format %{ "imulq $dst, $src\t# mulExact long" %} |
|
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8002 ins_encode %{ |
|
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8003 __ imulq($dst$$Register, $src$$Address); |
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8004 %} |
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8005 ins_pipe(ialu_reg_mem_alu0); |
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8006 %} |
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8007 |
| 0 | 8008 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
| 8009 rFlagsReg cr) | |
| 8010 %{ | |
| 8011 match(Set rax (DivI rax div)); | |
| 8012 effect(KILL rdx, KILL cr); | |
| 8013 | |
| 8014 ins_cost(30*100+10*100); // XXX | |
| 8015 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 8016 "jne,s normal\n\t" | |
| 8017 "xorl rdx, rdx\n\t" | |
| 8018 "cmpl $div, -1\n\t" | |
| 8019 "je,s done\n" | |
| 8020 "normal: cdql\n\t" | |
| 8021 "idivl $div\n" | |
| 8022 "done:" %} | |
| 8023 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8024 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8025 ins_pipe(ialu_reg_reg_alu0); | |
| 8026 %} | |
| 8027 | |
| 8028 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 8029 rFlagsReg cr) | |
| 8030 %{ | |
| 8031 match(Set rax (DivL rax div)); | |
| 8032 effect(KILL rdx, KILL cr); | |
| 8033 | |
| 8034 ins_cost(30*100+10*100); // XXX | |
| 8035 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 8036 "cmpq rax, rdx\n\t" | |
| 8037 "jne,s normal\n\t" | |
| 8038 "xorl rdx, rdx\n\t" | |
| 8039 "cmpq $div, -1\n\t" | |
| 8040 "je,s done\n" | |
| 8041 "normal: cdqq\n\t" | |
| 8042 "idivq $div\n" | |
| 8043 "done:" %} | |
| 8044 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8045 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8046 ins_pipe(ialu_reg_reg_alu0); | |
| 8047 %} | |
| 8048 | |
| 8049 // Integer DIVMOD with Register, both quotient and mod results | |
| 8050 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, | |
| 8051 rFlagsReg cr) | |
| 8052 %{ | |
| 8053 match(DivModI rax div); | |
| 8054 effect(KILL cr); | |
| 8055 | |
| 8056 ins_cost(30*100+10*100); // XXX | |
| 8057 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 8058 "jne,s normal\n\t" | |
| 8059 "xorl rdx, rdx\n\t" | |
| 8060 "cmpl $div, -1\n\t" | |
| 8061 "je,s done\n" | |
| 8062 "normal: cdql\n\t" | |
| 8063 "idivl $div\n" | |
| 8064 "done:" %} | |
| 8065 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8066 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8067 ins_pipe(pipe_slow); | |
| 8068 %} | |
| 8069 | |
| 8070 // Long DIVMOD with Register, both quotient and mod results | |
| 8071 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 8072 rFlagsReg cr) | |
| 8073 %{ | |
| 8074 match(DivModL rax div); | |
| 8075 effect(KILL cr); | |
| 8076 | |
| 8077 ins_cost(30*100+10*100); // XXX | |
| 8078 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 8079 "cmpq rax, rdx\n\t" | |
| 8080 "jne,s normal\n\t" | |
| 8081 "xorl rdx, rdx\n\t" | |
| 8082 "cmpq $div, -1\n\t" | |
| 8083 "je,s done\n" | |
| 8084 "normal: cdqq\n\t" | |
| 8085 "idivq $div\n" | |
| 8086 "done:" %} | |
| 8087 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8088 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8089 ins_pipe(pipe_slow); | |
| 8090 %} | |
| 8091 | |
| 8092 //----------- DivL-By-Constant-Expansions-------------------------------------- | |
| 8093 // DivI cases are handled by the compiler | |
| 8094 | |
| 605 | 8095 // Magic constant, reciprocal of 10 |
| 0 | 8096 instruct loadConL_0x6666666666666667(rRegL dst) |
| 8097 %{ | |
| 8098 effect(DEF dst); | |
| 8099 | |
| 8100 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %} | |
| 8101 ins_encode(load_immL(dst, 0x6666666666666667)); | |
| 8102 ins_pipe(ialu_reg); | |
| 8103 %} | |
| 8104 | |
| 8105 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) | |
| 8106 %{ | |
| 8107 effect(DEF dst, USE src, USE_KILL rax, KILL cr); | |
| 8108 | |
| 8109 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %} | |
| 8110 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 8111 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 8112 ins_pipe(ialu_reg_reg_alu0); | |
| 8113 %} | |
| 8114 | |
| 8115 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr) | |
| 8116 %{ | |
| 8117 effect(USE_DEF dst, KILL cr); | |
| 8118 | |
| 8119 format %{ "sarq $dst, #63\t# Used in div-by-10" %} | |
| 8120 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8121 ins_encode(reg_opc_imm_wide(dst, 0x3F)); | |
| 8122 ins_pipe(ialu_reg); | |
| 8123 %} | |
| 8124 | |
| 8125 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr) | |
| 8126 %{ | |
| 8127 effect(USE_DEF dst, KILL cr); | |
| 8128 | |
| 8129 format %{ "sarq $dst, #2\t# Used in div-by-10" %} | |
| 8130 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8131 ins_encode(reg_opc_imm_wide(dst, 0x2)); | |
| 8132 ins_pipe(ialu_reg); | |
| 8133 %} | |
| 8134 | |
| 8135 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div) | |
| 8136 %{ | |
| 8137 match(Set dst (DivL src div)); | |
| 8138 | |
| 8139 ins_cost((5+8)*100); | |
| 8140 expand %{ | |
| 8141 rax_RegL rax; // Killed temp | |
| 8142 rFlagsReg cr; // Killed | |
| 8143 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667 | |
| 8144 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src | |
| 8145 sarL_rReg_63(src, cr); // sarq src, 63 | |
| 8146 sarL_rReg_2(dst, cr); // sarq rdx, 2 | |
| 8147 subL_rReg(dst, src, cr); // subl rdx, src | |
| 8148 %} | |
| 8149 %} | |
| 8150 | |
| 8151 //----------------------------------------------------------------------------- | |
| 8152 | |
| 8153 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, | |
| 8154 rFlagsReg cr) | |
| 8155 %{ | |
| 8156 match(Set rdx (ModI rax div)); | |
| 8157 effect(KILL rax, KILL cr); | |
| 8158 | |
| 8159 ins_cost(300); // XXX | |
| 8160 format %{ "cmpl rax, 0x80000000\t# irem\n\t" | |
| 8161 "jne,s normal\n\t" | |
| 8162 "xorl rdx, rdx\n\t" | |
| 8163 "cmpl $div, -1\n\t" | |
| 8164 "je,s done\n" | |
| 8165 "normal: cdql\n\t" | |
| 8166 "idivl $div\n" | |
| 8167 "done:" %} | |
| 8168 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8169 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8170 ins_pipe(ialu_reg_reg_alu0); | |
| 8171 %} | |
| 8172 | |
| 8173 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, | |
| 8174 rFlagsReg cr) | |
| 8175 %{ | |
| 8176 match(Set rdx (ModL rax div)); | |
| 8177 effect(KILL rax, KILL cr); | |
| 8178 | |
| 8179 ins_cost(300); // XXX | |
| 8180 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t" | |
| 8181 "cmpq rax, rdx\n\t" | |
| 8182 "jne,s normal\n\t" | |
| 8183 "xorl rdx, rdx\n\t" | |
| 8184 "cmpq $div, -1\n\t" | |
| 8185 "je,s done\n" | |
| 8186 "normal: cdqq\n\t" | |
| 8187 "idivq $div\n" | |
| 8188 "done:" %} | |
| 8189 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8190 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8191 ins_pipe(ialu_reg_reg_alu0); | |
| 8192 %} | |
| 8193 | |
| 8194 // Integer Shift Instructions | |
| 8195 // Shift Left by one | |
| 8196 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8197 %{ | |
| 8198 match(Set dst (LShiftI dst shift)); | |
| 8199 effect(KILL cr); | |
| 8200 | |
| 8201 format %{ "sall $dst, $shift" %} | |
| 8202 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8203 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8204 ins_pipe(ialu_reg); | |
| 8205 %} | |
| 8206 | |
| 8207 // Shift Left by one | |
| 8208 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8209 %{ | |
| 8210 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8211 effect(KILL cr); | |
| 8212 | |
| 8213 format %{ "sall $dst, $shift\t" %} | |
| 8214 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8215 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8216 ins_pipe(ialu_mem_imm); | |
| 8217 %} | |
| 8218 | |
| 8219 // Shift Left by 8-bit immediate | |
| 8220 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8221 %{ | |
| 8222 match(Set dst (LShiftI dst shift)); | |
| 8223 effect(KILL cr); | |
| 8224 | |
| 8225 format %{ "sall $dst, $shift" %} | |
| 8226 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8227 ins_encode(reg_opc_imm(dst, shift)); | |
| 8228 ins_pipe(ialu_reg); | |
| 8229 %} | |
| 8230 | |
| 8231 // Shift Left by 8-bit immediate | |
| 8232 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8233 %{ | |
| 8234 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8235 effect(KILL cr); | |
| 8236 | |
| 8237 format %{ "sall $dst, $shift" %} | |
| 8238 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8239 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8240 ins_pipe(ialu_mem_imm); | |
| 8241 %} | |
| 8242 | |
| 8243 // Shift Left by variable | |
| 8244 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8245 %{ | |
| 8246 match(Set dst (LShiftI dst shift)); | |
| 8247 effect(KILL cr); | |
| 8248 | |
| 8249 format %{ "sall $dst, $shift" %} | |
| 8250 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8251 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8252 ins_pipe(ialu_reg_reg); | |
| 8253 %} | |
| 8254 | |
| 8255 // Shift Left by variable | |
| 8256 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8257 %{ | |
| 8258 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8259 effect(KILL cr); | |
| 8260 | |
| 8261 format %{ "sall $dst, $shift" %} | |
| 8262 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8263 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8264 ins_pipe(ialu_mem_reg); | |
| 8265 %} | |
| 8266 | |
| 8267 // Arithmetic shift right by one | |
| 8268 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8269 %{ | |
| 8270 match(Set dst (RShiftI dst shift)); | |
| 8271 effect(KILL cr); | |
| 8272 | |
| 8273 format %{ "sarl $dst, $shift" %} | |
| 8274 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8275 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8276 ins_pipe(ialu_reg); | |
| 8277 %} | |
| 8278 | |
| 8279 // Arithmetic shift right by one | |
| 8280 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8281 %{ | |
| 8282 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8283 effect(KILL cr); | |
| 8284 | |
| 8285 format %{ "sarl $dst, $shift" %} | |
| 8286 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8287 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8288 ins_pipe(ialu_mem_imm); | |
| 8289 %} | |
| 8290 | |
| 8291 // Arithmetic Shift Right by 8-bit immediate | |
| 8292 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8293 %{ | |
| 8294 match(Set dst (RShiftI dst shift)); | |
| 8295 effect(KILL cr); | |
| 8296 | |
| 8297 format %{ "sarl $dst, $shift" %} | |
| 8298 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8299 ins_encode(reg_opc_imm(dst, shift)); | |
| 8300 ins_pipe(ialu_mem_imm); | |
| 8301 %} | |
| 8302 | |
| 8303 // Arithmetic Shift Right by 8-bit immediate | |
| 8304 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8305 %{ | |
| 8306 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8307 effect(KILL cr); | |
| 8308 | |
| 8309 format %{ "sarl $dst, $shift" %} | |
| 8310 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8311 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8312 ins_pipe(ialu_mem_imm); | |
| 8313 %} | |
| 8314 | |
| 8315 // Arithmetic Shift Right by variable | |
| 8316 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8317 %{ | |
| 8318 match(Set dst (RShiftI dst shift)); | |
| 8319 effect(KILL cr); | |
| 8320 | |
| 8321 format %{ "sarl $dst, $shift" %} | |
| 8322 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8323 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8324 ins_pipe(ialu_reg_reg); | |
| 8325 %} | |
| 8326 | |
| 8327 // Arithmetic Shift Right by variable | |
| 8328 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8329 %{ | |
| 8330 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8331 effect(KILL cr); | |
| 8332 | |
| 8333 format %{ "sarl $dst, $shift" %} | |
| 8334 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8335 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8336 ins_pipe(ialu_mem_reg); | |
| 8337 %} | |
| 8338 | |
| 8339 // Logical shift right by one | |
| 8340 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8341 %{ | |
| 8342 match(Set dst (URShiftI dst shift)); | |
| 8343 effect(KILL cr); | |
| 8344 | |
| 8345 format %{ "shrl $dst, $shift" %} | |
| 8346 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8347 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8348 ins_pipe(ialu_reg); | |
| 8349 %} | |
| 8350 | |
| 8351 // Logical shift right by one | |
| 8352 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8353 %{ | |
| 8354 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8355 effect(KILL cr); | |
| 8356 | |
| 8357 format %{ "shrl $dst, $shift" %} | |
| 8358 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8359 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8360 ins_pipe(ialu_mem_imm); | |
| 8361 %} | |
| 8362 | |
| 8363 // Logical Shift Right by 8-bit immediate | |
| 8364 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8365 %{ | |
| 8366 match(Set dst (URShiftI dst shift)); | |
| 8367 effect(KILL cr); | |
| 8368 | |
| 8369 format %{ "shrl $dst, $shift" %} | |
| 8370 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8371 ins_encode(reg_opc_imm(dst, shift)); | |
| 8372 ins_pipe(ialu_reg); | |
| 8373 %} | |
| 8374 | |
| 8375 // Logical Shift Right by 8-bit immediate | |
| 8376 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8377 %{ | |
| 8378 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8379 effect(KILL cr); | |
| 8380 | |
| 8381 format %{ "shrl $dst, $shift" %} | |
| 8382 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8383 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8384 ins_pipe(ialu_mem_imm); | |
| 8385 %} | |
| 8386 | |
| 8387 // Logical Shift Right by variable | |
| 8388 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8389 %{ | |
| 8390 match(Set dst (URShiftI dst shift)); | |
| 8391 effect(KILL cr); | |
| 8392 | |
| 8393 format %{ "shrl $dst, $shift" %} | |
| 8394 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8395 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8396 ins_pipe(ialu_reg_reg); | |
| 8397 %} | |
| 8398 | |
| 8399 // Logical Shift Right by variable | |
| 8400 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8401 %{ | |
| 8402 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8403 effect(KILL cr); | |
| 8404 | |
| 8405 format %{ "shrl $dst, $shift" %} | |
| 8406 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8407 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8408 ins_pipe(ialu_mem_reg); | |
| 8409 %} | |
| 8410 | |
| 8411 // Long Shift Instructions | |
| 8412 // Shift Left by one | |
| 8413 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8414 %{ | |
| 8415 match(Set dst (LShiftL dst shift)); | |
| 8416 effect(KILL cr); | |
| 8417 | |
| 8418 format %{ "salq $dst, $shift" %} | |
| 8419 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8420 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8421 ins_pipe(ialu_reg); | |
| 8422 %} | |
| 8423 | |
| 8424 // Shift Left by one | |
| 8425 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8426 %{ | |
| 8427 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8428 effect(KILL cr); | |
| 8429 | |
| 8430 format %{ "salq $dst, $shift" %} | |
| 8431 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8432 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8433 ins_pipe(ialu_mem_imm); | |
| 8434 %} | |
| 8435 | |
| 8436 // Shift Left by 8-bit immediate | |
| 8437 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8438 %{ | |
| 8439 match(Set dst (LShiftL dst shift)); | |
| 8440 effect(KILL cr); | |
| 8441 | |
| 8442 format %{ "salq $dst, $shift" %} | |
| 8443 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8444 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8445 ins_pipe(ialu_reg); | |
| 8446 %} | |
| 8447 | |
| 8448 // Shift Left by 8-bit immediate | |
| 8449 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8450 %{ | |
| 8451 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8452 effect(KILL cr); | |
| 8453 | |
| 8454 format %{ "salq $dst, $shift" %} | |
| 8455 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8456 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8457 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8458 ins_pipe(ialu_mem_imm); | |
| 8459 %} | |
| 8460 | |
| 8461 // Shift Left by variable | |
| 8462 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8463 %{ | |
| 8464 match(Set dst (LShiftL dst shift)); | |
| 8465 effect(KILL cr); | |
| 8466 | |
| 8467 format %{ "salq $dst, $shift" %} | |
| 8468 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8469 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8470 ins_pipe(ialu_reg_reg); | |
| 8471 %} | |
| 8472 | |
| 8473 // Shift Left by variable | |
| 8474 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8475 %{ | |
| 8476 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8477 effect(KILL cr); | |
| 8478 | |
| 8479 format %{ "salq $dst, $shift" %} | |
| 8480 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8481 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8482 ins_pipe(ialu_mem_reg); | |
| 8483 %} | |
| 8484 | |
| 8485 // Arithmetic shift right by one | |
| 8486 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8487 %{ | |
| 8488 match(Set dst (RShiftL dst shift)); | |
| 8489 effect(KILL cr); | |
| 8490 | |
| 8491 format %{ "sarq $dst, $shift" %} | |
| 8492 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8493 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8494 ins_pipe(ialu_reg); | |
| 8495 %} | |
| 8496 | |
| 8497 // Arithmetic shift right by one | |
| 8498 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8499 %{ | |
| 8500 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8501 effect(KILL cr); | |
| 8502 | |
| 8503 format %{ "sarq $dst, $shift" %} | |
| 8504 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8505 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8506 ins_pipe(ialu_mem_imm); | |
| 8507 %} | |
| 8508 | |
| 8509 // Arithmetic Shift Right by 8-bit immediate | |
| 8510 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8511 %{ | |
| 8512 match(Set dst (RShiftL dst shift)); | |
| 8513 effect(KILL cr); | |
| 8514 | |
| 8515 format %{ "sarq $dst, $shift" %} | |
| 8516 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8517 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8518 ins_pipe(ialu_mem_imm); | |
| 8519 %} | |
| 8520 | |
| 8521 // Arithmetic Shift Right by 8-bit immediate | |
| 8522 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8523 %{ | |
| 8524 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8525 effect(KILL cr); | |
| 8526 | |
| 8527 format %{ "sarq $dst, $shift" %} | |
| 8528 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8529 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8530 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8531 ins_pipe(ialu_mem_imm); | |
| 8532 %} | |
| 8533 | |
| 8534 // Arithmetic Shift Right by variable | |
| 8535 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8536 %{ | |
| 8537 match(Set dst (RShiftL dst shift)); | |
| 8538 effect(KILL cr); | |
| 8539 | |
| 8540 format %{ "sarq $dst, $shift" %} | |
| 8541 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8542 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8543 ins_pipe(ialu_reg_reg); | |
| 8544 %} | |
| 8545 | |
| 8546 // Arithmetic Shift Right by variable | |
| 8547 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8548 %{ | |
| 8549 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8550 effect(KILL cr); | |
| 8551 | |
| 8552 format %{ "sarq $dst, $shift" %} | |
| 8553 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8554 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8555 ins_pipe(ialu_mem_reg); | |
| 8556 %} | |
| 8557 | |
| 8558 // Logical shift right by one | |
| 8559 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8560 %{ | |
| 8561 match(Set dst (URShiftL dst shift)); | |
| 8562 effect(KILL cr); | |
| 8563 | |
| 8564 format %{ "shrq $dst, $shift" %} | |
| 8565 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8566 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst )); | |
| 8567 ins_pipe(ialu_reg); | |
| 8568 %} | |
| 8569 | |
| 8570 // Logical shift right by one | |
| 8571 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8572 %{ | |
| 8573 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8574 effect(KILL cr); | |
| 8575 | |
| 8576 format %{ "shrq $dst, $shift" %} | |
| 8577 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8578 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8579 ins_pipe(ialu_mem_imm); | |
| 8580 %} | |
| 8581 | |
| 8582 // Logical Shift Right by 8-bit immediate | |
| 8583 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8584 %{ | |
| 8585 match(Set dst (URShiftL dst shift)); | |
| 8586 effect(KILL cr); | |
| 8587 | |
| 8588 format %{ "shrq $dst, $shift" %} | |
| 8589 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8590 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8591 ins_pipe(ialu_reg); | |
| 8592 %} | |
| 8593 | |
|
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|
8594 |
| 0 | 8595 // Logical Shift Right by 8-bit immediate |
| 8596 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8597 %{ | |
| 8598 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8599 effect(KILL cr); | |
| 8600 | |
| 8601 format %{ "shrq $dst, $shift" %} | |
| 8602 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8603 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8604 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8605 ins_pipe(ialu_mem_imm); | |
| 8606 %} | |
| 8607 | |
| 8608 // Logical Shift Right by variable | |
| 8609 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8610 %{ | |
| 8611 match(Set dst (URShiftL dst shift)); | |
| 8612 effect(KILL cr); | |
| 8613 | |
| 8614 format %{ "shrq $dst, $shift" %} | |
| 8615 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8616 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8617 ins_pipe(ialu_reg_reg); | |
| 8618 %} | |
| 8619 | |
| 8620 // Logical Shift Right by variable | |
| 8621 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8622 %{ | |
| 8623 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8624 effect(KILL cr); | |
| 8625 | |
| 8626 format %{ "shrq $dst, $shift" %} | |
| 8627 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8628 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8629 ins_pipe(ialu_mem_reg); | |
| 8630 %} | |
| 8631 | |
| 8632 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. | |
| 8633 // This idiom is used by the compiler for the i2b bytecode. | |
| 8634 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour) | |
| 8635 %{ | |
| 8636 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); | |
| 8637 | |
| 8638 format %{ "movsbl $dst, $src\t# i2b" %} | |
| 8639 opcode(0x0F, 0xBE); | |
| 8640 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8641 ins_pipe(ialu_reg_reg); | |
| 8642 %} | |
| 8643 | |
| 8644 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 8645 // This idiom is used by the compiler the i2s bytecode. | |
| 8646 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen) | |
| 8647 %{ | |
| 8648 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); | |
| 8649 | |
| 8650 format %{ "movswl $dst, $src\t# i2s" %} | |
| 8651 opcode(0x0F, 0xBF); | |
| 8652 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8653 ins_pipe(ialu_reg_reg); | |
| 8654 %} | |
| 8655 | |
| 8656 // ROL/ROR instructions | |
| 8657 | |
| 8658 // ROL expand | |
| 8659 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{ | |
| 8660 effect(KILL cr, USE_DEF dst); | |
| 8661 | |
| 8662 format %{ "roll $dst" %} | |
| 8663 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8664 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8665 ins_pipe(ialu_reg); | |
| 8666 %} | |
| 8667 | |
| 8668 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{ | |
| 8669 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8670 | |
| 8671 format %{ "roll $dst, $shift" %} | |
| 8672 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 8673 ins_encode( reg_opc_imm(dst, shift) ); | |
| 8674 ins_pipe(ialu_reg); | |
| 8675 %} | |
| 8676 | |
| 8677 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8678 %{ | |
| 8679 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8680 | |
| 8681 format %{ "roll $dst, $shift" %} | |
| 8682 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8683 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8684 ins_pipe(ialu_reg_reg); | |
| 8685 %} | |
| 8686 // end of ROL expand | |
| 8687 | |
| 8688 // Rotate Left by one | |
| 8689 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 8690 %{ | |
| 8691 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8692 | |
| 8693 expand %{ | |
| 8694 rolI_rReg_imm1(dst, cr); | |
| 8695 %} | |
| 8696 %} | |
| 8697 | |
| 8698 // Rotate Left by 8-bit immediate | |
| 8699 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 8700 %{ | |
| 8701 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8702 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8703 | |
| 8704 expand %{ | |
| 8705 rolI_rReg_imm8(dst, lshift, cr); | |
| 8706 %} | |
| 8707 %} | |
| 8708 | |
| 8709 // Rotate Left by variable | |
| 8710 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8711 %{ | |
| 8712 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 8713 | |
| 8714 expand %{ | |
| 8715 rolI_rReg_CL(dst, shift, cr); | |
| 8716 %} | |
| 8717 %} | |
| 8718 | |
| 8719 // Rotate Left by variable | |
| 8720 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 8721 %{ | |
| 8722 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 8723 | |
| 8724 expand %{ | |
| 8725 rolI_rReg_CL(dst, shift, cr); | |
| 8726 %} | |
| 8727 %} | |
| 8728 | |
| 8729 // ROR expand | |
| 8730 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr) | |
| 8731 %{ | |
| 8732 effect(USE_DEF dst, KILL cr); | |
| 8733 | |
| 8734 format %{ "rorl $dst" %} | |
| 8735 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 8736 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8737 ins_pipe(ialu_reg); | |
| 8738 %} | |
| 8739 | |
| 8740 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8741 %{ | |
| 8742 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8743 | |
| 8744 format %{ "rorl $dst, $shift" %} | |
| 8745 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 8746 ins_encode(reg_opc_imm(dst, shift)); | |
| 8747 ins_pipe(ialu_reg); | |
| 8748 %} | |
| 8749 | |
| 8750 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8751 %{ | |
| 8752 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8753 | |
| 8754 format %{ "rorl $dst, $shift" %} | |
| 8755 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 8756 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8757 ins_pipe(ialu_reg_reg); | |
| 8758 %} | |
| 8759 // end of ROR expand | |
| 8760 | |
| 8761 // Rotate Right by one | |
| 8762 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 8763 %{ | |
| 8764 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8765 | |
| 8766 expand %{ | |
| 8767 rorI_rReg_imm1(dst, cr); | |
| 8768 %} | |
| 8769 %} | |
| 8770 | |
| 8771 // Rotate Right by 8-bit immediate | |
| 8772 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 8773 %{ | |
| 8774 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8775 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8776 | |
| 8777 expand %{ | |
| 8778 rorI_rReg_imm8(dst, rshift, cr); | |
| 8779 %} | |
| 8780 %} | |
| 8781 | |
| 8782 // Rotate Right by variable | |
| 8783 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8784 %{ | |
| 8785 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 8786 | |
| 8787 expand %{ | |
| 8788 rorI_rReg_CL(dst, shift, cr); | |
| 8789 %} | |
| 8790 %} | |
| 8791 | |
| 8792 // Rotate Right by variable | |
| 8793 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 8794 %{ | |
| 8795 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 8796 | |
| 8797 expand %{ | |
| 8798 rorI_rReg_CL(dst, shift, cr); | |
| 8799 %} | |
| 8800 %} | |
| 8801 | |
| 8802 // for long rotate | |
| 8803 // ROL expand | |
| 8804 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{ | |
| 8805 effect(USE_DEF dst, KILL cr); | |
| 8806 | |
| 8807 format %{ "rolq $dst" %} | |
| 8808 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8809 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8810 ins_pipe(ialu_reg); | |
| 8811 %} | |
| 8812 | |
| 8813 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{ | |
| 8814 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8815 | |
| 8816 format %{ "rolq $dst, $shift" %} | |
| 8817 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 8818 ins_encode( reg_opc_imm_wide(dst, shift) ); | |
| 8819 ins_pipe(ialu_reg); | |
| 8820 %} | |
| 8821 | |
| 8822 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8823 %{ | |
| 8824 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8825 | |
| 8826 format %{ "rolq $dst, $shift" %} | |
| 8827 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8828 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8829 ins_pipe(ialu_reg_reg); | |
| 8830 %} | |
| 8831 // end of ROL expand | |
| 8832 | |
| 8833 // Rotate Left by one | |
| 8834 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 8835 %{ | |
| 8836 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 8837 | |
| 8838 expand %{ | |
| 8839 rolL_rReg_imm1(dst, cr); | |
| 8840 %} | |
| 8841 %} | |
| 8842 | |
| 8843 // Rotate Left by 8-bit immediate | |
| 8844 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 8845 %{ | |
| 8846 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 8847 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 8848 | |
| 8849 expand %{ | |
| 8850 rolL_rReg_imm8(dst, lshift, cr); | |
| 8851 %} | |
| 8852 %} | |
| 8853 | |
| 8854 // Rotate Left by variable | |
| 8855 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8856 %{ | |
| 8857 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift)))); | |
| 8858 | |
| 8859 expand %{ | |
| 8860 rolL_rReg_CL(dst, shift, cr); | |
| 8861 %} | |
| 8862 %} | |
| 8863 | |
| 8864 // Rotate Left by variable | |
| 8865 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 8866 %{ | |
| 8867 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift)))); | |
| 8868 | |
| 8869 expand %{ | |
| 8870 rolL_rReg_CL(dst, shift, cr); | |
| 8871 %} | |
| 8872 %} | |
| 8873 | |
| 8874 // ROR expand | |
| 8875 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr) | |
| 8876 %{ | |
| 8877 effect(USE_DEF dst, KILL cr); | |
| 8878 | |
| 8879 format %{ "rorq $dst" %} | |
| 8880 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 8881 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8882 ins_pipe(ialu_reg); | |
| 8883 %} | |
| 8884 | |
| 8885 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8886 %{ | |
| 8887 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8888 | |
| 8889 format %{ "rorq $dst, $shift" %} | |
| 8890 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 8891 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8892 ins_pipe(ialu_reg); | |
| 8893 %} | |
| 8894 | |
| 8895 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8896 %{ | |
| 8897 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8898 | |
| 8899 format %{ "rorq $dst, $shift" %} | |
| 8900 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 8901 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8902 ins_pipe(ialu_reg_reg); | |
| 8903 %} | |
| 8904 // end of ROR expand | |
| 8905 | |
| 8906 // Rotate Right by one | |
| 8907 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 8908 %{ | |
| 8909 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 8910 | |
| 8911 expand %{ | |
| 8912 rorL_rReg_imm1(dst, cr); | |
| 8913 %} | |
| 8914 %} | |
| 8915 | |
| 8916 // Rotate Right by 8-bit immediate | |
| 8917 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 8918 %{ | |
| 8919 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 8920 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 8921 | |
| 8922 expand %{ | |
| 8923 rorL_rReg_imm8(dst, rshift, cr); | |
| 8924 %} | |
| 8925 %} | |
| 8926 | |
| 8927 // Rotate Right by variable | |
| 8928 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8929 %{ | |
| 8930 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift)))); | |
| 8931 | |
| 8932 expand %{ | |
| 8933 rorL_rReg_CL(dst, shift, cr); | |
| 8934 %} | |
| 8935 %} | |
| 8936 | |
| 8937 // Rotate Right by variable | |
| 8938 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 8939 %{ | |
| 8940 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift)))); | |
| 8941 | |
| 8942 expand %{ | |
| 8943 rorL_rReg_CL(dst, shift, cr); | |
| 8944 %} | |
| 8945 %} | |
| 8946 | |
| 8947 // Logical Instructions | |
| 8948 | |
| 8949 // Integer Logical Instructions | |
| 8950 | |
| 8951 // And Instructions | |
| 8952 // And Register with Register | |
| 8953 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8954 %{ | |
| 8955 match(Set dst (AndI dst src)); | |
| 8956 effect(KILL cr); | |
| 8957 | |
| 8958 format %{ "andl $dst, $src\t# int" %} | |
| 8959 opcode(0x23); | |
| 8960 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 8961 ins_pipe(ialu_reg_reg); | |
| 8962 %} | |
| 8963 | |
| 8964 // And Register with Immediate 255 | |
| 8965 instruct andI_rReg_imm255(rRegI dst, immI_255 src) | |
| 8966 %{ | |
| 8967 match(Set dst (AndI dst src)); | |
| 8968 | |
| 8969 format %{ "movzbl $dst, $dst\t# int & 0xFF" %} | |
| 8970 opcode(0x0F, 0xB6); | |
| 8971 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 8972 ins_pipe(ialu_reg); | |
| 8973 %} | |
| 8974 | |
| 8975 // And Register with Immediate 255 and promote to long | |
| 8976 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask) | |
| 8977 %{ | |
| 8978 match(Set dst (ConvI2L (AndI src mask))); | |
| 8979 | |
| 8980 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %} | |
| 8981 opcode(0x0F, 0xB6); | |
| 8982 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8983 ins_pipe(ialu_reg); | |
| 8984 %} | |
| 8985 | |
| 8986 // And Register with Immediate 65535 | |
| 8987 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src) | |
| 8988 %{ | |
| 8989 match(Set dst (AndI dst src)); | |
| 8990 | |
| 8991 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %} | |
| 8992 opcode(0x0F, 0xB7); | |
| 8993 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 8994 ins_pipe(ialu_reg); | |
| 8995 %} | |
| 8996 | |
| 8997 // And Register with Immediate 65535 and promote to long | |
| 8998 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask) | |
| 8999 %{ | |
| 9000 match(Set dst (ConvI2L (AndI src mask))); | |
| 9001 | |
| 9002 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %} | |
| 9003 opcode(0x0F, 0xB7); | |
| 9004 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 9005 ins_pipe(ialu_reg); | |
| 9006 %} | |
| 9007 | |
| 9008 // And Register with Immediate | |
| 9009 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9010 %{ | |
| 9011 match(Set dst (AndI dst src)); | |
| 9012 effect(KILL cr); | |
| 9013 | |
| 9014 format %{ "andl $dst, $src\t# int" %} | |
| 9015 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 9016 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9017 ins_pipe(ialu_reg); | |
| 9018 %} | |
| 9019 | |
| 9020 // And Register with Memory | |
| 9021 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9022 %{ | |
| 9023 match(Set dst (AndI dst (LoadI src))); | |
| 9024 effect(KILL cr); | |
| 9025 | |
| 9026 ins_cost(125); | |
| 9027 format %{ "andl $dst, $src\t# int" %} | |
| 9028 opcode(0x23); | |
| 9029 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9030 ins_pipe(ialu_reg_mem); | |
| 9031 %} | |
| 9032 | |
| 9033 // And Memory with Register | |
| 9034 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9035 %{ | |
| 9036 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9037 effect(KILL cr); | |
| 9038 | |
| 9039 ins_cost(150); | |
| 9040 format %{ "andl $dst, $src\t# int" %} | |
| 9041 opcode(0x21); /* Opcode 21 /r */ | |
| 9042 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9043 ins_pipe(ialu_mem_reg); | |
| 9044 %} | |
| 9045 | |
| 9046 // And Memory with Immediate | |
| 9047 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9048 %{ | |
| 9049 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9050 effect(KILL cr); | |
| 9051 | |
| 9052 ins_cost(125); | |
| 9053 format %{ "andl $dst, $src\t# int" %} | |
| 9054 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9055 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9056 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9057 ins_pipe(ialu_mem_imm); | |
| 9058 %} | |
| 9059 | |
| 9060 // Or Instructions | |
| 9061 // Or Register with Register | |
| 9062 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9063 %{ | |
| 9064 match(Set dst (OrI dst src)); | |
| 9065 effect(KILL cr); | |
| 9066 | |
| 9067 format %{ "orl $dst, $src\t# int" %} | |
| 9068 opcode(0x0B); | |
| 9069 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9070 ins_pipe(ialu_reg_reg); | |
| 9071 %} | |
| 9072 | |
| 9073 // Or Register with Immediate | |
| 9074 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9075 %{ | |
| 9076 match(Set dst (OrI dst src)); | |
| 9077 effect(KILL cr); | |
| 9078 | |
| 9079 format %{ "orl $dst, $src\t# int" %} | |
| 9080 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 9081 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9082 ins_pipe(ialu_reg); | |
| 9083 %} | |
| 9084 | |
| 9085 // Or Register with Memory | |
| 9086 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9087 %{ | |
| 9088 match(Set dst (OrI dst (LoadI src))); | |
| 9089 effect(KILL cr); | |
| 9090 | |
| 9091 ins_cost(125); | |
| 9092 format %{ "orl $dst, $src\t# int" %} | |
| 9093 opcode(0x0B); | |
| 9094 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9095 ins_pipe(ialu_reg_mem); | |
| 9096 %} | |
| 9097 | |
| 9098 // Or Memory with Register | |
| 9099 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9100 %{ | |
| 9101 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9102 effect(KILL cr); | |
| 9103 | |
| 9104 ins_cost(150); | |
| 9105 format %{ "orl $dst, $src\t# int" %} | |
| 9106 opcode(0x09); /* Opcode 09 /r */ | |
| 9107 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9108 ins_pipe(ialu_mem_reg); | |
| 9109 %} | |
| 9110 | |
| 9111 // Or Memory with Immediate | |
| 9112 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9113 %{ | |
| 9114 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9115 effect(KILL cr); | |
| 9116 | |
| 9117 ins_cost(125); | |
| 9118 format %{ "orl $dst, $src\t# int" %} | |
| 9119 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 9120 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9121 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9122 ins_pipe(ialu_mem_imm); | |
| 9123 %} | |
| 9124 | |
| 9125 // Xor Instructions | |
| 9126 // Xor Register with Register | |
| 9127 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9128 %{ | |
| 9129 match(Set dst (XorI dst src)); | |
| 9130 effect(KILL cr); | |
| 9131 | |
| 9132 format %{ "xorl $dst, $src\t# int" %} | |
| 9133 opcode(0x33); | |
| 9134 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9135 ins_pipe(ialu_reg_reg); | |
| 9136 %} | |
| 9137 | |
| 403 | 9138 // Xor Register with Immediate -1 |
| 9139 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{ | |
|
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9140 match(Set dst (XorI dst imm)); |
|
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9141 |
|
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9142 format %{ "not $dst" %} |
| 403 | 9143 ins_encode %{ |
| 9144 __ notl($dst$$Register); | |
| 9145 %} | |
| 9146 ins_pipe(ialu_reg); | |
| 9147 %} | |
| 9148 | |
| 0 | 9149 // Xor Register with Immediate |
| 9150 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9151 %{ | |
| 9152 match(Set dst (XorI dst src)); | |
| 9153 effect(KILL cr); | |
| 9154 | |
| 9155 format %{ "xorl $dst, $src\t# int" %} | |
| 9156 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 9157 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9158 ins_pipe(ialu_reg); | |
| 9159 %} | |
| 9160 | |
| 9161 // Xor Register with Memory | |
| 9162 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9163 %{ | |
| 9164 match(Set dst (XorI dst (LoadI src))); | |
| 9165 effect(KILL cr); | |
| 9166 | |
| 9167 ins_cost(125); | |
| 9168 format %{ "xorl $dst, $src\t# int" %} | |
| 9169 opcode(0x33); | |
| 9170 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9171 ins_pipe(ialu_reg_mem); | |
| 9172 %} | |
| 9173 | |
| 9174 // Xor Memory with Register | |
| 9175 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9176 %{ | |
| 9177 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9178 effect(KILL cr); | |
| 9179 | |
| 9180 ins_cost(150); | |
| 9181 format %{ "xorl $dst, $src\t# int" %} | |
| 9182 opcode(0x31); /* Opcode 31 /r */ | |
| 9183 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9184 ins_pipe(ialu_mem_reg); | |
| 9185 %} | |
| 9186 | |
| 9187 // Xor Memory with Immediate | |
| 9188 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9189 %{ | |
| 9190 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9191 effect(KILL cr); | |
| 9192 | |
| 9193 ins_cost(125); | |
| 9194 format %{ "xorl $dst, $src\t# int" %} | |
| 9195 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 9196 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9197 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9198 ins_pipe(ialu_mem_imm); | |
| 9199 %} | |
| 9200 | |
| 9201 | |
| 9202 // Long Logical Instructions | |
| 9203 | |
| 9204 // And Instructions | |
| 9205 // And Register with Register | |
| 9206 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9207 %{ | |
| 9208 match(Set dst (AndL dst src)); | |
| 9209 effect(KILL cr); | |
| 9210 | |
| 9211 format %{ "andq $dst, $src\t# long" %} | |
| 9212 opcode(0x23); | |
| 9213 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9214 ins_pipe(ialu_reg_reg); | |
| 9215 %} | |
| 9216 | |
| 9217 // And Register with Immediate 255 | |
| 9218 instruct andL_rReg_imm255(rRegL dst, immL_255 src) | |
| 9219 %{ | |
| 9220 match(Set dst (AndL dst src)); | |
| 9221 | |
|
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9222 format %{ "movzbq $dst, $dst\t# long & 0xFF" %} |
| 0 | 9223 opcode(0x0F, 0xB6); |
| 9224 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9225 ins_pipe(ialu_reg); | |
| 9226 %} | |
| 9227 | |
| 9228 // And Register with Immediate 65535 | |
|
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9229 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src) |
| 0 | 9230 %{ |
| 9231 match(Set dst (AndL dst src)); | |
| 9232 | |
| 9233 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %} | |
| 9234 opcode(0x0F, 0xB7); | |
| 9235 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9236 ins_pipe(ialu_reg); | |
| 9237 %} | |
| 9238 | |
| 9239 // And Register with Immediate | |
| 9240 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9241 %{ | |
| 9242 match(Set dst (AndL dst src)); | |
| 9243 effect(KILL cr); | |
| 9244 | |
| 9245 format %{ "andq $dst, $src\t# long" %} | |
| 9246 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 9247 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9248 ins_pipe(ialu_reg); | |
| 9249 %} | |
| 9250 | |
| 9251 // And Register with Memory | |
| 9252 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9253 %{ | |
| 9254 match(Set dst (AndL dst (LoadL src))); | |
| 9255 effect(KILL cr); | |
| 9256 | |
| 9257 ins_cost(125); | |
| 9258 format %{ "andq $dst, $src\t# long" %} | |
| 9259 opcode(0x23); | |
| 9260 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9261 ins_pipe(ialu_reg_mem); | |
| 9262 %} | |
| 9263 | |
| 9264 // And Memory with Register | |
| 9265 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9266 %{ | |
| 9267 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9268 effect(KILL cr); | |
| 9269 | |
| 9270 ins_cost(150); | |
| 9271 format %{ "andq $dst, $src\t# long" %} | |
| 9272 opcode(0x21); /* Opcode 21 /r */ | |
| 9273 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9274 ins_pipe(ialu_mem_reg); | |
| 9275 %} | |
| 9276 | |
| 9277 // And Memory with Immediate | |
| 9278 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9279 %{ | |
| 9280 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9281 effect(KILL cr); | |
| 9282 | |
| 9283 ins_cost(125); | |
| 9284 format %{ "andq $dst, $src\t# long" %} | |
| 9285 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9286 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9287 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9288 ins_pipe(ialu_mem_imm); | |
| 9289 %} | |
| 9290 | |
| 9291 // Or Instructions | |
| 9292 // Or Register with Register | |
| 9293 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9294 %{ | |
| 9295 match(Set dst (OrL dst src)); | |
| 9296 effect(KILL cr); | |
| 9297 | |
| 9298 format %{ "orq $dst, $src\t# long" %} | |
| 9299 opcode(0x0B); | |
| 9300 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9301 ins_pipe(ialu_reg_reg); | |
| 9302 %} | |
| 9303 | |
|
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9304 // Use any_RegP to match R15 (TLS register) without spilling. |
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9305 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{ |
|
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9306 match(Set dst (OrL dst (CastP2X src))); |
|
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9307 effect(KILL cr); |
|
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|
9308 |
|
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|
9309 format %{ "orq $dst, $src\t# long" %} |
|
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9310 opcode(0x0B); |
|
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9311 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
|
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9312 ins_pipe(ialu_reg_reg); |
|
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9313 %} |
|
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9314 |
|
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9315 |
| 0 | 9316 // Or Register with Immediate |
| 9317 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9318 %{ | |
| 9319 match(Set dst (OrL dst src)); | |
| 9320 effect(KILL cr); | |
| 9321 | |
| 9322 format %{ "orq $dst, $src\t# long" %} | |
| 9323 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 9324 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9325 ins_pipe(ialu_reg); | |
| 9326 %} | |
| 9327 | |
| 9328 // Or Register with Memory | |
| 9329 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9330 %{ | |
| 9331 match(Set dst (OrL dst (LoadL src))); | |
| 9332 effect(KILL cr); | |
| 9333 | |
| 9334 ins_cost(125); | |
| 9335 format %{ "orq $dst, $src\t# long" %} | |
| 9336 opcode(0x0B); | |
| 9337 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9338 ins_pipe(ialu_reg_mem); | |
| 9339 %} | |
| 9340 | |
| 9341 // Or Memory with Register | |
| 9342 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9343 %{ | |
| 9344 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 9345 effect(KILL cr); | |
| 9346 | |
| 9347 ins_cost(150); | |
| 9348 format %{ "orq $dst, $src\t# long" %} | |
| 9349 opcode(0x09); /* Opcode 09 /r */ | |
| 9350 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9351 ins_pipe(ialu_mem_reg); | |
| 9352 %} | |
| 9353 | |
| 9354 // Or Memory with Immediate | |
| 9355 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9356 %{ | |
| 9357 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 9358 effect(KILL cr); | |
| 9359 | |
| 9360 ins_cost(125); | |
| 9361 format %{ "orq $dst, $src\t# long" %} | |
| 9362 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 9363 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9364 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9365 ins_pipe(ialu_mem_imm); | |
| 9366 %} | |
| 9367 | |
| 9368 // Xor Instructions | |
| 9369 // Xor Register with Register | |
| 9370 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9371 %{ | |
| 9372 match(Set dst (XorL dst src)); | |
| 9373 effect(KILL cr); | |
| 9374 | |
| 9375 format %{ "xorq $dst, $src\t# long" %} | |
| 9376 opcode(0x33); | |
| 9377 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9378 ins_pipe(ialu_reg_reg); | |
| 9379 %} | |
| 9380 | |
| 403 | 9381 // Xor Register with Immediate -1 |
| 9382 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{ | |
|
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|
9383 match(Set dst (XorL dst imm)); |
|
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|
9384 |
|
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|
9385 format %{ "notq $dst" %} |
| 403 | 9386 ins_encode %{ |
| 9387 __ notq($dst$$Register); | |
| 9388 %} | |
| 9389 ins_pipe(ialu_reg); | |
| 9390 %} | |
| 9391 | |
| 0 | 9392 // Xor Register with Immediate |
| 9393 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9394 %{ | |
| 9395 match(Set dst (XorL dst src)); | |
| 9396 effect(KILL cr); | |
| 9397 | |
| 9398 format %{ "xorq $dst, $src\t# long" %} | |
| 9399 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 9400 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9401 ins_pipe(ialu_reg); | |
| 9402 %} | |
| 9403 | |
| 9404 // Xor Register with Memory | |
| 9405 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9406 %{ | |
| 9407 match(Set dst (XorL dst (LoadL src))); | |
| 9408 effect(KILL cr); | |
| 9409 | |
| 9410 ins_cost(125); | |
| 9411 format %{ "xorq $dst, $src\t# long" %} | |
| 9412 opcode(0x33); | |
| 9413 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9414 ins_pipe(ialu_reg_mem); | |
| 9415 %} | |
| 9416 | |
| 9417 // Xor Memory with Register | |
| 9418 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9419 %{ | |
| 9420 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 9421 effect(KILL cr); | |
| 9422 | |
| 9423 ins_cost(150); | |
| 9424 format %{ "xorq $dst, $src\t# long" %} | |
| 9425 opcode(0x31); /* Opcode 31 /r */ | |
| 9426 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9427 ins_pipe(ialu_mem_reg); | |
| 9428 %} | |
| 9429 | |
| 9430 // Xor Memory with Immediate | |
| 9431 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9432 %{ | |
| 9433 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 9434 effect(KILL cr); | |
| 9435 | |
| 9436 ins_cost(125); | |
| 9437 format %{ "xorq $dst, $src\t# long" %} | |
| 9438 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 9439 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9440 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9441 ins_pipe(ialu_mem_imm); | |
| 9442 %} | |
| 9443 | |
| 9444 // Convert Int to Boolean | |
| 9445 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9446 %{ | |
| 9447 match(Set dst (Conv2B src)); | |
| 9448 effect(KILL cr); | |
| 9449 | |
| 9450 format %{ "testl $src, $src\t# ci2b\n\t" | |
| 9451 "setnz $dst\n\t" | |
| 9452 "movzbl $dst, $dst" %} | |
| 9453 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl | |
| 9454 setNZ_reg(dst), | |
| 9455 REX_reg_breg(dst, dst), // movzbl | |
| 9456 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 9457 ins_pipe(pipe_slow); // XXX | |
| 9458 %} | |
| 9459 | |
| 9460 // Convert Pointer to Boolean | |
| 9461 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr) | |
| 9462 %{ | |
| 9463 match(Set dst (Conv2B src)); | |
| 9464 effect(KILL cr); | |
| 9465 | |
| 9466 format %{ "testq $src, $src\t# cp2b\n\t" | |
| 9467 "setnz $dst\n\t" | |
| 9468 "movzbl $dst, $dst" %} | |
| 9469 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq | |
| 9470 setNZ_reg(dst), | |
| 9471 REX_reg_breg(dst, dst), // movzbl | |
| 9472 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 9473 ins_pipe(pipe_slow); // XXX | |
| 9474 %} | |
| 9475 | |
| 9476 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr) | |
| 9477 %{ | |
| 9478 match(Set dst (CmpLTMask p q)); | |
| 9479 effect(KILL cr); | |
| 9480 | |
| 9154 | 9481 ins_cost(400); |
| 0 | 9482 format %{ "cmpl $p, $q\t# cmpLTMask\n\t" |
| 9483 "setlt $dst\n\t" | |
| 9484 "movzbl $dst, $dst\n\t" | |
| 9485 "negl $dst" %} | |
| 9486 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl | |
| 9487 setLT_reg(dst), | |
| 9488 REX_reg_breg(dst, dst), // movzbl | |
| 9489 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst), | |
| 9490 neg_reg(dst)); | |
| 9491 ins_pipe(pipe_slow); | |
| 9492 %} | |
| 9493 | |
| 9494 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 9495 %{ | |
| 9496 match(Set dst (CmpLTMask dst zero)); | |
| 9497 effect(KILL cr); | |
| 9498 | |
| 9154 | 9499 ins_cost(100); |
| 0 | 9500 format %{ "sarl $dst, #31\t# cmpLTMask0" %} |
| 9154 | 9501 ins_encode %{ |
| 9502 __ sarl($dst$$Register, 31); | |
| 9503 %} | |
| 0 | 9504 ins_pipe(ialu_reg); |
| 9505 %} | |
| 9506 | |
| 9154 | 9507 /* Better to save a register than avoid a branch */ |
| 9508 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr) | |
| 0 | 9509 %{ |
| 9510 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 9154 | 9511 effect(KILL cr); |
| 9512 ins_cost(300); | |
| 9513 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t" | |
| 9514 "jge done\n\t" | |
| 9515 "addl $p,$y\n" | |
| 9516 "done: " %} | |
|
3738
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|
9517 ins_encode %{ |
|
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|
9518 Register Rp = $p$$Register; |
|
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|
9519 Register Rq = $q$$Register; |
|
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|
9520 Register Ry = $y$$Register; |
| 9154 | 9521 Label done; |
|
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|
9522 __ subl(Rp, Rq); |
| 9154 | 9523 __ jccb(Assembler::greaterEqual, done); |
| 9524 __ addl(Rp, Ry); | |
| 9525 __ bind(done); | |
|
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|
9526 %} |
| 0 | 9527 ins_pipe(pipe_cmplt); |
| 9528 %} | |
| 9529 | |
| 9154 | 9530 /* Better to save a register than avoid a branch */ |
| 9531 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr) | |
| 9532 %{ | |
| 9533 match(Set y (AndI (CmpLTMask p q) y)); | |
| 9534 effect(KILL cr); | |
| 9535 | |
| 9536 ins_cost(300); | |
| 9537 | |
| 9538 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t" | |
| 9539 "jlt done\n\t" | |
| 9540 "xorl $y, $y\n" | |
| 9541 "done: " %} | |
| 9542 ins_encode %{ | |
| 9543 Register Rp = $p$$Register; | |
| 9544 Register Rq = $q$$Register; | |
| 9545 Register Ry = $y$$Register; | |
| 9546 Label done; | |
| 9547 __ cmpl(Rp, Rq); | |
| 9548 __ jccb(Assembler::less, done); | |
| 9549 __ xorl(Ry, Ry); | |
| 9550 __ bind(done); | |
| 9551 %} | |
| 9552 ins_pipe(pipe_cmplt); | |
| 9553 %} | |
| 9554 | |
| 9555 | |
| 0 | 9556 //---------- FP Instructions------------------------------------------------ |
| 9557 | |
| 9558 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2) | |
| 9559 %{ | |
| 9560 match(Set cr (CmpF src1 src2)); | |
| 9561 | |
| 9562 ins_cost(145); | |
| 9563 format %{ "ucomiss $src1, $src2\n\t" | |
| 9564 "jnp,s exit\n\t" | |
| 9565 "pushfq\t# saw NaN, set CF\n\t" | |
| 9566 "andq [rsp], #0xffffff2b\n\t" | |
| 9567 "popfq\n" | |
| 4759 | 9568 "exit:" %} |
| 9569 ins_encode %{ | |
| 9570 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9571 emit_cmpfp_fixup(_masm); | |
| 9572 %} | |
| 0 | 9573 ins_pipe(pipe_slow); |
| 9574 %} | |
| 9575 | |
|
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|
9576 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{ |
|
4d9884b01ba6
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403
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|
9577 match(Set cr (CmpF src1 src2)); |
|
4d9884b01ba6
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403
diff
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|
9578 |
| 4759 | 9579 ins_cost(100); |
|
415
4d9884b01ba6
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diff
changeset
|
9580 format %{ "ucomiss $src1, $src2" %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9581 ins_encode %{ |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9582 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9583 %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9584 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
9585 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9586 |
| 0 | 9587 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2) |
| 9588 %{ | |
| 9589 match(Set cr (CmpF src1 (LoadF src2))); | |
| 9590 | |
| 9591 ins_cost(145); | |
| 9592 format %{ "ucomiss $src1, $src2\n\t" | |
| 9593 "jnp,s exit\n\t" | |
| 9594 "pushfq\t# saw NaN, set CF\n\t" | |
| 9595 "andq [rsp], #0xffffff2b\n\t" | |
| 9596 "popfq\n" | |
| 4759 | 9597 "exit:" %} |
| 9598 ins_encode %{ | |
| 9599 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9600 emit_cmpfp_fixup(_masm); | |
| 9601 %} | |
| 0 | 9602 ins_pipe(pipe_slow); |
| 9603 %} | |
| 9604 | |
|
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
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403
diff
changeset
|
9605 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
9606 match(Set cr (CmpF src1 (LoadF src2))); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9607 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
9608 ins_cost(100); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9609 format %{ "ucomiss $src1, $src2" %} |
| 4759 | 9610 ins_encode %{ |
| 9611 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9612 %} | |
|
415
4d9884b01ba6
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diff
changeset
|
9613 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
9614 %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9615 |
| 2008 | 9616 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{ |
| 9617 match(Set cr (CmpF src con)); | |
| 0 | 9618 |
| 9619 ins_cost(145); | |
| 2008 | 9620 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
| 0 | 9621 "jnp,s exit\n\t" |
| 9622 "pushfq\t# saw NaN, set CF\n\t" | |
| 9623 "andq [rsp], #0xffffff2b\n\t" | |
| 9624 "popfq\n" | |
| 4759 | 9625 "exit:" %} |
| 2008 | 9626 ins_encode %{ |
| 9627 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 3783 | 9628 emit_cmpfp_fixup(_masm); |
| 2008 | 9629 %} |
| 9630 ins_pipe(pipe_slow); | |
| 9631 %} | |
| 9632 | |
| 9633 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{ | |
| 9634 match(Set cr (CmpF src con)); | |
|
415
4d9884b01ba6
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403
diff
changeset
|
9635 ins_cost(100); |
| 2008 | 9636 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %} |
| 9637 ins_encode %{ | |
| 9638 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 9639 %} | |
|
415
4d9884b01ba6
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diff
changeset
|
9640 ins_pipe(pipe_slow); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9641 %} |
|
4d9884b01ba6
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403
diff
changeset
|
9642 |
| 0 | 9643 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2) |
| 9644 %{ | |
| 9645 match(Set cr (CmpD src1 src2)); | |
| 9646 | |
| 9647 ins_cost(145); | |
| 9648 format %{ "ucomisd $src1, $src2\n\t" | |
| 9649 "jnp,s exit\n\t" | |
| 9650 "pushfq\t# saw NaN, set CF\n\t" | |
| 9651 "andq [rsp], #0xffffff2b\n\t" | |
| 9652 "popfq\n" | |
| 4759 | 9653 "exit:" %} |
| 9654 ins_encode %{ | |
| 9655 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9656 emit_cmpfp_fixup(_masm); | |
| 9657 %} | |
| 0 | 9658 ins_pipe(pipe_slow); |
| 9659 %} | |
| 9660 | |
|
415
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changeset
|
9661 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{ |
|
4d9884b01ba6
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403
diff
changeset
|
9662 match(Set cr (CmpD src1 src2)); |
|
4d9884b01ba6
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diff
changeset
|
9663 |
|
4d9884b01ba6
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403
diff
changeset
|
9664 ins_cost(100); |
|
4d9884b01ba6
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diff
changeset
|
9665 format %{ "ucomisd $src1, $src2 test" %} |
|
4d9884b01ba6
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403
diff
changeset
|
9666 ins_encode %{ |
|
4d9884b01ba6
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diff
changeset
|
9667 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); |
|
4d9884b01ba6
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diff
changeset
|
9668 %} |
|
4d9884b01ba6
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403
diff
changeset
|
9669 ins_pipe(pipe_slow); |
|
4d9884b01ba6
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403
diff
changeset
|
9670 %} |
|
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diff
changeset
|
9671 |
| 0 | 9672 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2) |
| 9673 %{ | |
| 9674 match(Set cr (CmpD src1 (LoadD src2))); | |
| 9675 | |
| 9676 ins_cost(145); | |
| 9677 format %{ "ucomisd $src1, $src2\n\t" | |
| 9678 "jnp,s exit\n\t" | |
| 9679 "pushfq\t# saw NaN, set CF\n\t" | |
| 9680 "andq [rsp], #0xffffff2b\n\t" | |
| 9681 "popfq\n" | |
| 4759 | 9682 "exit:" %} |
| 9683 ins_encode %{ | |
| 9684 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9685 emit_cmpfp_fixup(_masm); | |
| 9686 %} | |
| 0 | 9687 ins_pipe(pipe_slow); |
| 9688 %} | |
| 9689 | |
|
415
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diff
changeset
|
9690 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{ |
|
4d9884b01ba6
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diff
changeset
|
9691 match(Set cr (CmpD src1 (LoadD src2))); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9692 |
|
4d9884b01ba6
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403
diff
changeset
|
9693 ins_cost(100); |
|
4d9884b01ba6
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diff
changeset
|
9694 format %{ "ucomisd $src1, $src2" %} |
| 4759 | 9695 ins_encode %{ |
| 9696 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9697 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
9698 ins_pipe(pipe_slow); |
|
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diff
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|
9699 %} |
|
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diff
changeset
|
9700 |
| 2008 | 9701 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{ |
| 9702 match(Set cr (CmpD src con)); | |
| 0 | 9703 |
| 9704 ins_cost(145); | |
| 2008 | 9705 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9706 "jnp,s exit\n\t" |
| 9707 "pushfq\t# saw NaN, set CF\n\t" | |
| 9708 "andq [rsp], #0xffffff2b\n\t" | |
| 9709 "popfq\n" | |
| 4759 | 9710 "exit:" %} |
| 2008 | 9711 ins_encode %{ |
| 9712 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 3783 | 9713 emit_cmpfp_fixup(_masm); |
| 2008 | 9714 %} |
| 9715 ins_pipe(pipe_slow); | |
| 9716 %} | |
| 9717 | |
| 9718 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{ | |
| 9719 match(Set cr (CmpD src con)); | |
|
415
4d9884b01ba6
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parents:
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diff
changeset
|
9720 ins_cost(100); |
| 2008 | 9721 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %} |
| 9722 ins_encode %{ | |
| 9723 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 9724 %} | |
|
415
4d9884b01ba6
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diff
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|
9725 ins_pipe(pipe_slow); |
|
4d9884b01ba6
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parents:
403
diff
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|
9726 %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9727 |
| 0 | 9728 // Compare into -1,0,1 |
| 9729 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr) | |
| 9730 %{ | |
| 9731 match(Set dst (CmpF3 src1 src2)); | |
| 9732 effect(KILL cr); | |
| 9733 | |
| 9734 ins_cost(275); | |
| 9735 format %{ "ucomiss $src1, $src2\n\t" | |
| 9736 "movl $dst, #-1\n\t" | |
| 9737 "jp,s done\n\t" | |
| 9738 "jb,s done\n\t" | |
| 9739 "setne $dst\n\t" | |
| 9740 "movzbl $dst, $dst\n" | |
| 9741 "done:" %} | |
| 4759 | 9742 ins_encode %{ |
| 9743 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9744 emit_cmpfp3(_masm, $dst$$Register); | |
| 9745 %} | |
| 0 | 9746 ins_pipe(pipe_slow); |
| 9747 %} | |
| 9748 | |
| 9749 // Compare into -1,0,1 | |
| 9750 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr) | |
| 9751 %{ | |
| 9752 match(Set dst (CmpF3 src1 (LoadF src2))); | |
| 9753 effect(KILL cr); | |
| 9754 | |
| 9755 ins_cost(275); | |
| 9756 format %{ "ucomiss $src1, $src2\n\t" | |
| 9757 "movl $dst, #-1\n\t" | |
| 9758 "jp,s done\n\t" | |
| 9759 "jb,s done\n\t" | |
| 9760 "setne $dst\n\t" | |
| 9761 "movzbl $dst, $dst\n" | |
| 9762 "done:" %} | |
| 4759 | 9763 ins_encode %{ |
| 9764 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9765 emit_cmpfp3(_masm, $dst$$Register); | |
| 9766 %} | |
| 0 | 9767 ins_pipe(pipe_slow); |
| 9768 %} | |
| 9769 | |
| 9770 // Compare into -1,0,1 | |
| 2008 | 9771 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{ |
| 9772 match(Set dst (CmpF3 src con)); | |
| 0 | 9773 effect(KILL cr); |
| 9774 | |
| 9775 ins_cost(275); | |
| 2008 | 9776 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
| 0 | 9777 "movl $dst, #-1\n\t" |
| 9778 "jp,s done\n\t" | |
| 9779 "jb,s done\n\t" | |
| 9780 "setne $dst\n\t" | |
| 9781 "movzbl $dst, $dst\n" | |
| 9782 "done:" %} | |
| 2008 | 9783 ins_encode %{ |
| 9784 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 4759 | 9785 emit_cmpfp3(_masm, $dst$$Register); |
| 2008 | 9786 %} |
| 0 | 9787 ins_pipe(pipe_slow); |
| 9788 %} | |
| 9789 | |
| 9790 // Compare into -1,0,1 | |
| 9791 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr) | |
| 9792 %{ | |
| 9793 match(Set dst (CmpD3 src1 src2)); | |
| 9794 effect(KILL cr); | |
| 9795 | |
| 9796 ins_cost(275); | |
| 9797 format %{ "ucomisd $src1, $src2\n\t" | |
| 9798 "movl $dst, #-1\n\t" | |
| 9799 "jp,s done\n\t" | |
| 9800 "jb,s done\n\t" | |
| 9801 "setne $dst\n\t" | |
| 9802 "movzbl $dst, $dst\n" | |
| 9803 "done:" %} | |
| 4759 | 9804 ins_encode %{ |
| 9805 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9806 emit_cmpfp3(_masm, $dst$$Register); | |
| 9807 %} | |
| 0 | 9808 ins_pipe(pipe_slow); |
| 9809 %} | |
| 9810 | |
| 9811 // Compare into -1,0,1 | |
| 9812 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr) | |
| 9813 %{ | |
| 9814 match(Set dst (CmpD3 src1 (LoadD src2))); | |
| 9815 effect(KILL cr); | |
| 9816 | |
| 9817 ins_cost(275); | |
| 9818 format %{ "ucomisd $src1, $src2\n\t" | |
| 9819 "movl $dst, #-1\n\t" | |
| 9820 "jp,s done\n\t" | |
| 9821 "jb,s done\n\t" | |
| 9822 "setne $dst\n\t" | |
| 9823 "movzbl $dst, $dst\n" | |
| 9824 "done:" %} | |
| 4759 | 9825 ins_encode %{ |
| 9826 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9827 emit_cmpfp3(_masm, $dst$$Register); | |
| 9828 %} | |
| 0 | 9829 ins_pipe(pipe_slow); |
| 9830 %} | |
| 9831 | |
| 9832 // Compare into -1,0,1 | |
| 2008 | 9833 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{ |
| 9834 match(Set dst (CmpD3 src con)); | |
| 0 | 9835 effect(KILL cr); |
| 9836 | |
| 9837 ins_cost(275); | |
| 2008 | 9838 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9839 "movl $dst, #-1\n\t" |
| 9840 "jp,s done\n\t" | |
| 9841 "jb,s done\n\t" | |
| 9842 "setne $dst\n\t" | |
| 9843 "movzbl $dst, $dst\n" | |
| 9844 "done:" %} | |
| 2008 | 9845 ins_encode %{ |
| 9846 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 4759 | 9847 emit_cmpfp3(_masm, $dst$$Register); |
| 2008 | 9848 %} |
| 0 | 9849 ins_pipe(pipe_slow); |
| 9850 %} | |
| 9851 | |
| 9852 // -----------Trig and Trancendental Instructions------------------------------ | |
| 9853 instruct cosD_reg(regD dst) %{ | |
| 9854 match(Set dst (CosD dst)); | |
| 9855 | |
| 9856 format %{ "dcos $dst\n\t" %} | |
| 9857 opcode(0xD9, 0xFF); | |
| 9858 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 9859 ins_pipe( pipe_slow ); | |
| 9860 %} | |
| 9861 | |
| 9862 instruct sinD_reg(regD dst) %{ | |
| 9863 match(Set dst (SinD dst)); | |
| 9864 | |
| 9865 format %{ "dsin $dst\n\t" %} | |
| 9866 opcode(0xD9, 0xFE); | |
| 9867 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 9868 ins_pipe( pipe_slow ); | |
| 9869 %} | |
| 9870 | |
| 9871 instruct tanD_reg(regD dst) %{ | |
| 9872 match(Set dst (TanD dst)); | |
| 9873 | |
| 9874 format %{ "dtan $dst\n\t" %} | |
| 9875 ins_encode( Push_SrcXD(dst), | |
| 9876 Opcode(0xD9), Opcode(0xF2), //fptan | |
| 9877 Opcode(0xDD), Opcode(0xD8), //fstp st | |
| 9878 Push_ResultXD(dst) ); | |
| 9879 ins_pipe( pipe_slow ); | |
| 9880 %} | |
| 9881 | |
| 9882 instruct log10D_reg(regD dst) %{ | |
| 9883 // The source and result Double operands in XMM registers | |
| 9884 match(Set dst (Log10D dst)); | |
| 9885 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 9886 // fyl2x ; compute log_10(2) * log_2(x) | |
| 9887 format %{ "fldlg2\t\t\t#Log10\n\t" | |
| 9888 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t" | |
| 9889 %} | |
| 9890 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 9891 Push_SrcXD(dst), | |
| 9892 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 9893 Push_ResultXD(dst)); | |
| 9894 | |
| 9895 ins_pipe( pipe_slow ); | |
| 9896 %} | |
| 9897 | |
| 9898 instruct logD_reg(regD dst) %{ | |
| 9899 // The source and result Double operands in XMM registers | |
| 9900 match(Set dst (LogD dst)); | |
| 9901 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 9902 // fyl2x ; compute log_e(2) * log_2(x) | |
| 9903 format %{ "fldln2\t\t\t#Log_e\n\t" | |
| 9904 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t" | |
| 9905 %} | |
| 9906 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 9907 Push_SrcXD(dst), | |
| 9908 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 9909 Push_ResultXD(dst)); | |
| 9910 ins_pipe( pipe_slow ); | |
| 9911 %} | |
| 9912 | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
9913 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9914 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9915 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9916 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
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|
9917 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
9918 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
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diff
changeset
|
9919 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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diff
changeset
|
9920 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9921 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9922 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
9923 __ fast_pow(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
9924 __ fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
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|
9925 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
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|
9926 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
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|
9927 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
9928 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
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|
9929 %} |
|
6759698e3140
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roland
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5984
diff
changeset
|
9930 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
9931 instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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diff
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|
9932 match(Set dst (ExpD src)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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diff
changeset
|
9933 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
6759698e3140
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roland
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5984
diff
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|
9934 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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diff
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|
9935 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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5984
diff
changeset
|
9936 __ subptr(rsp, 8); |
|
6759698e3140
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roland
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diff
changeset
|
9937 __ movdbl(Address(rsp, 0), $src$$XMMRegister); |
|
6759698e3140
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diff
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|
9938 __ fld_d(Address(rsp, 0)); |
|
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7133857: exp() and pow() should use the x87 ISA on x86
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diff
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|
9939 __ fast_exp(); |
|
6759698e3140
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roland
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diff
changeset
|
9940 __ fstp_d(Address(rsp, 0)); |
|
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7133857: exp() and pow() should use the x87 ISA on x86
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|
9941 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
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|
9942 __ addptr(rsp, 8); |
|
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|
9943 %} |
|
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|
9944 ins_pipe( pipe_slow ); |
|
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roland
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|
9945 %} |
| 0 | 9946 |
| 9947 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 9948 | |
| 9949 instruct roundFloat_nop(regF dst) | |
| 9950 %{ | |
| 9951 match(Set dst (RoundFloat dst)); | |
| 9952 | |
| 9953 ins_cost(0); | |
| 9954 ins_encode(); | |
| 9955 ins_pipe(empty); | |
| 9956 %} | |
| 9957 | |
| 9958 instruct roundDouble_nop(regD dst) | |
| 9959 %{ | |
| 9960 match(Set dst (RoundDouble dst)); | |
| 9961 | |
| 9962 ins_cost(0); | |
| 9963 ins_encode(); | |
| 9964 ins_pipe(empty); | |
| 9965 %} | |
| 9966 | |
| 9967 instruct convF2D_reg_reg(regD dst, regF src) | |
| 9968 %{ | |
| 9969 match(Set dst (ConvF2D src)); | |
| 9970 | |
| 9971 format %{ "cvtss2sd $dst, $src" %} | |
| 4759 | 9972 ins_encode %{ |
| 9973 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); | |
| 9974 %} | |
| 0 | 9975 ins_pipe(pipe_slow); // XXX |
| 9976 %} | |
| 9977 | |
| 9978 instruct convF2D_reg_mem(regD dst, memory src) | |
| 9979 %{ | |
| 9980 match(Set dst (ConvF2D (LoadF src))); | |
| 9981 | |
| 9982 format %{ "cvtss2sd $dst, $src" %} | |
| 4759 | 9983 ins_encode %{ |
| 9984 __ cvtss2sd ($dst$$XMMRegister, $src$$Address); | |
| 9985 %} | |
| 0 | 9986 ins_pipe(pipe_slow); // XXX |
| 9987 %} | |
| 9988 | |
| 9989 instruct convD2F_reg_reg(regF dst, regD src) | |
| 9990 %{ | |
| 9991 match(Set dst (ConvD2F src)); | |
| 9992 | |
| 9993 format %{ "cvtsd2ss $dst, $src" %} | |
| 4759 | 9994 ins_encode %{ |
| 9995 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); | |
| 9996 %} | |
| 0 | 9997 ins_pipe(pipe_slow); // XXX |
| 9998 %} | |
| 9999 | |
| 10000 instruct convD2F_reg_mem(regF dst, memory src) | |
| 10001 %{ | |
| 10002 match(Set dst (ConvD2F (LoadD src))); | |
| 10003 | |
| 10004 format %{ "cvtsd2ss $dst, $src" %} | |
| 4759 | 10005 ins_encode %{ |
| 10006 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address); | |
| 10007 %} | |
| 0 | 10008 ins_pipe(pipe_slow); // XXX |
| 10009 %} | |
| 10010 | |
| 10011 // XXX do mem variants | |
| 10012 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr) | |
| 10013 %{ | |
| 10014 match(Set dst (ConvF2I src)); | |
| 10015 effect(KILL cr); | |
| 10016 | |
| 10017 format %{ "cvttss2sil $dst, $src\t# f2i\n\t" | |
| 10018 "cmpl $dst, #0x80000000\n\t" | |
| 10019 "jne,s done\n\t" | |
| 10020 "subq rsp, #8\n\t" | |
| 10021 "movss [rsp], $src\n\t" | |
| 10022 "call f2i_fixup\n\t" | |
| 10023 "popq $dst\n" | |
| 10024 "done: "%} | |
| 4759 | 10025 ins_encode %{ |
| 10026 Label done; | |
| 10027 __ cvttss2sil($dst$$Register, $src$$XMMRegister); | |
| 10028 __ cmpl($dst$$Register, 0x80000000); | |
| 10029 __ jccb(Assembler::notEqual, done); | |
| 10030 __ subptr(rsp, 8); | |
| 10031 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10032 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup()))); | |
| 10033 __ pop($dst$$Register); | |
| 10034 __ bind(done); | |
| 10035 %} | |
| 0 | 10036 ins_pipe(pipe_slow); |
| 10037 %} | |
| 10038 | |
| 10039 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr) | |
| 10040 %{ | |
| 10041 match(Set dst (ConvF2L src)); | |
| 10042 effect(KILL cr); | |
| 10043 | |
| 10044 format %{ "cvttss2siq $dst, $src\t# f2l\n\t" | |
| 10045 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 10046 "jne,s done\n\t" | |
| 10047 "subq rsp, #8\n\t" | |
| 10048 "movss [rsp], $src\n\t" | |
| 10049 "call f2l_fixup\n\t" | |
| 10050 "popq $dst\n" | |
| 10051 "done: "%} | |
| 4759 | 10052 ins_encode %{ |
| 10053 Label done; | |
| 10054 __ cvttss2siq($dst$$Register, $src$$XMMRegister); | |
| 10055 __ cmp64($dst$$Register, | |
| 10056 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); | |
| 10057 __ jccb(Assembler::notEqual, done); | |
| 10058 __ subptr(rsp, 8); | |
| 10059 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10060 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup()))); | |
| 10061 __ pop($dst$$Register); | |
| 10062 __ bind(done); | |
| 10063 %} | |
| 0 | 10064 ins_pipe(pipe_slow); |
| 10065 %} | |
| 10066 | |
| 10067 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr) | |
| 10068 %{ | |
| 10069 match(Set dst (ConvD2I src)); | |
| 10070 effect(KILL cr); | |
| 10071 | |
| 10072 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t" | |
| 10073 "cmpl $dst, #0x80000000\n\t" | |
| 10074 "jne,s done\n\t" | |
| 10075 "subq rsp, #8\n\t" | |
| 10076 "movsd [rsp], $src\n\t" | |
| 10077 "call d2i_fixup\n\t" | |
| 10078 "popq $dst\n" | |
| 10079 "done: "%} | |
| 4759 | 10080 ins_encode %{ |
| 10081 Label done; | |
| 10082 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); | |
| 10083 __ cmpl($dst$$Register, 0x80000000); | |
| 10084 __ jccb(Assembler::notEqual, done); | |
| 10085 __ subptr(rsp, 8); | |
| 10086 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10087 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup()))); | |
| 10088 __ pop($dst$$Register); | |
| 10089 __ bind(done); | |
| 10090 %} | |
| 0 | 10091 ins_pipe(pipe_slow); |
| 10092 %} | |
| 10093 | |
| 10094 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr) | |
| 10095 %{ | |
| 10096 match(Set dst (ConvD2L src)); | |
| 10097 effect(KILL cr); | |
| 10098 | |
| 10099 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t" | |
| 10100 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 10101 "jne,s done\n\t" | |
| 10102 "subq rsp, #8\n\t" | |
| 10103 "movsd [rsp], $src\n\t" | |
| 10104 "call d2l_fixup\n\t" | |
| 10105 "popq $dst\n" | |
| 10106 "done: "%} | |
| 4759 | 10107 ins_encode %{ |
| 10108 Label done; | |
| 10109 __ cvttsd2siq($dst$$Register, $src$$XMMRegister); | |
| 10110 __ cmp64($dst$$Register, | |
| 10111 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); | |
| 10112 __ jccb(Assembler::notEqual, done); | |
| 10113 __ subptr(rsp, 8); | |
| 10114 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10115 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup()))); | |
| 10116 __ pop($dst$$Register); | |
| 10117 __ bind(done); | |
| 10118 %} | |
| 0 | 10119 ins_pipe(pipe_slow); |
| 10120 %} | |
| 10121 | |
| 10122 instruct convI2F_reg_reg(regF dst, rRegI src) | |
| 10123 %{ | |
| 71 | 10124 predicate(!UseXmmI2F); |
| 0 | 10125 match(Set dst (ConvI2F src)); |
| 10126 | |
| 10127 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 4759 | 10128 ins_encode %{ |
| 10129 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); | |
| 10130 %} | |
| 0 | 10131 ins_pipe(pipe_slow); // XXX |
| 10132 %} | |
| 10133 | |
| 10134 instruct convI2F_reg_mem(regF dst, memory src) | |
| 10135 %{ | |
| 10136 match(Set dst (ConvI2F (LoadI src))); | |
| 10137 | |
| 10138 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 4759 | 10139 ins_encode %{ |
| 10140 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address); | |
| 10141 %} | |
| 0 | 10142 ins_pipe(pipe_slow); // XXX |
| 10143 %} | |
| 10144 | |
| 10145 instruct convI2D_reg_reg(regD dst, rRegI src) | |
| 10146 %{ | |
| 71 | 10147 predicate(!UseXmmI2D); |
| 0 | 10148 match(Set dst (ConvI2D src)); |
| 10149 | |
| 10150 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 4759 | 10151 ins_encode %{ |
| 10152 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); | |
| 10153 %} | |
| 0 | 10154 ins_pipe(pipe_slow); // XXX |
| 10155 %} | |
| 10156 | |
| 10157 instruct convI2D_reg_mem(regD dst, memory src) | |
| 10158 %{ | |
| 10159 match(Set dst (ConvI2D (LoadI src))); | |
| 10160 | |
| 10161 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 4759 | 10162 ins_encode %{ |
| 10163 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address); | |
| 10164 %} | |
| 0 | 10165 ins_pipe(pipe_slow); // XXX |
| 10166 %} | |
| 10167 | |
| 71 | 10168 instruct convXI2F_reg(regF dst, rRegI src) |
| 10169 %{ | |
| 10170 predicate(UseXmmI2F); | |
| 10171 match(Set dst (ConvI2F src)); | |
| 10172 | |
| 10173 format %{ "movdl $dst, $src\n\t" | |
| 10174 "cvtdq2psl $dst, $dst\t# i2f" %} | |
| 10175 ins_encode %{ | |
| 10176 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10177 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10178 %} | |
| 10179 ins_pipe(pipe_slow); // XXX | |
| 10180 %} | |
| 10181 | |
| 10182 instruct convXI2D_reg(regD dst, rRegI src) | |
| 10183 %{ | |
| 10184 predicate(UseXmmI2D); | |
| 10185 match(Set dst (ConvI2D src)); | |
| 10186 | |
| 10187 format %{ "movdl $dst, $src\n\t" | |
| 10188 "cvtdq2pdl $dst, $dst\t# i2d" %} | |
| 10189 ins_encode %{ | |
| 10190 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10191 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10192 %} | |
| 10193 ins_pipe(pipe_slow); // XXX | |
| 10194 %} | |
| 10195 | |
| 0 | 10196 instruct convL2F_reg_reg(regF dst, rRegL src) |
| 10197 %{ | |
| 10198 match(Set dst (ConvL2F src)); | |
| 10199 | |
| 10200 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 4759 | 10201 ins_encode %{ |
| 10202 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register); | |
| 10203 %} | |
| 0 | 10204 ins_pipe(pipe_slow); // XXX |
| 10205 %} | |
| 10206 | |
| 10207 instruct convL2F_reg_mem(regF dst, memory src) | |
| 10208 %{ | |
| 10209 match(Set dst (ConvL2F (LoadL src))); | |
| 10210 | |
| 10211 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 4759 | 10212 ins_encode %{ |
| 10213 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address); | |
| 10214 %} | |
| 0 | 10215 ins_pipe(pipe_slow); // XXX |
| 10216 %} | |
| 10217 | |
| 10218 instruct convL2D_reg_reg(regD dst, rRegL src) | |
| 10219 %{ | |
| 10220 match(Set dst (ConvL2D src)); | |
| 10221 | |
| 10222 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 4759 | 10223 ins_encode %{ |
| 10224 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register); | |
| 10225 %} | |
| 0 | 10226 ins_pipe(pipe_slow); // XXX |
| 10227 %} | |
| 10228 | |
| 10229 instruct convL2D_reg_mem(regD dst, memory src) | |
| 10230 %{ | |
| 10231 match(Set dst (ConvL2D (LoadL src))); | |
| 10232 | |
| 10233 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 4759 | 10234 ins_encode %{ |
| 10235 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address); | |
| 10236 %} | |
| 0 | 10237 ins_pipe(pipe_slow); // XXX |
| 10238 %} | |
| 10239 | |
| 10240 instruct convI2L_reg_reg(rRegL dst, rRegI src) | |
| 10241 %{ | |
| 10242 match(Set dst (ConvI2L src)); | |
| 10243 | |
| 10244 ins_cost(125); | |
| 10245 format %{ "movslq $dst, $src\t# i2l" %} | |
| 824 | 10246 ins_encode %{ |
| 10247 __ movslq($dst$$Register, $src$$Register); | |
| 10248 %} | |
| 0 | 10249 ins_pipe(ialu_reg_reg); |
| 10250 %} | |
| 10251 | |
| 10252 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src) | |
| 10253 // %{ | |
| 10254 // match(Set dst (ConvI2L src)); | |
| 10255 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 && | |
| 10256 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0); | |
| 10257 // predicate(((const TypeNode*) n)->type()->is_long()->_hi == | |
| 10258 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi && | |
| 10259 // ((const TypeNode*) n)->type()->is_long()->_lo == | |
| 10260 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo); | |
| 10261 | |
| 10262 // format %{ "movl $dst, $src\t# unsigned i2l" %} | |
| 10263 // ins_encode(enc_copy(dst, src)); | |
| 10264 // // opcode(0x63); // needs REX.W | |
| 10265 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); | |
| 10266 // ins_pipe(ialu_reg_reg); | |
| 10267 // %} | |
| 10268 | |
| 10269 // Zero-extend convert int to long | |
| 10270 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask) | |
| 10271 %{ | |
| 10272 match(Set dst (AndL (ConvI2L src) mask)); | |
| 10273 | |
| 10274 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 4759 | 10275 ins_encode %{ |
| 10276 if ($dst$$reg != $src$$reg) { | |
| 10277 __ movl($dst$$Register, $src$$Register); | |
| 10278 } | |
| 10279 %} | |
| 0 | 10280 ins_pipe(ialu_reg_reg); |
| 10281 %} | |
| 10282 | |
| 10283 // Zero-extend convert int to long | |
| 10284 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask) | |
| 10285 %{ | |
| 10286 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); | |
| 10287 | |
| 10288 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 4759 | 10289 ins_encode %{ |
| 10290 __ movl($dst$$Register, $src$$Address); | |
| 10291 %} | |
| 0 | 10292 ins_pipe(ialu_reg_mem); |
| 10293 %} | |
| 10294 | |
| 10295 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask) | |
| 10296 %{ | |
| 10297 match(Set dst (AndL src mask)); | |
| 10298 | |
| 10299 format %{ "movl $dst, $src\t# zero-extend long" %} | |
| 4759 | 10300 ins_encode %{ |
| 10301 __ movl($dst$$Register, $src$$Register); | |
| 10302 %} | |
| 0 | 10303 ins_pipe(ialu_reg_reg); |
| 10304 %} | |
| 10305 | |
| 10306 instruct convL2I_reg_reg(rRegI dst, rRegL src) | |
| 10307 %{ | |
| 10308 match(Set dst (ConvL2I src)); | |
| 10309 | |
| 10310 format %{ "movl $dst, $src\t# l2i" %} | |
| 4759 | 10311 ins_encode %{ |
| 10312 __ movl($dst$$Register, $src$$Register); | |
| 10313 %} | |
| 0 | 10314 ins_pipe(ialu_reg_reg); |
| 10315 %} | |
| 10316 | |
| 10317 | |
| 10318 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ | |
| 10319 match(Set dst (MoveF2I src)); | |
| 10320 effect(DEF dst, USE src); | |
| 10321 | |
| 10322 ins_cost(125); | |
| 10323 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %} | |
| 4759 | 10324 ins_encode %{ |
| 10325 __ movl($dst$$Register, Address(rsp, $src$$disp)); | |
| 10326 %} | |
| 0 | 10327 ins_pipe(ialu_reg_mem); |
| 10328 %} | |
| 10329 | |
| 10330 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 10331 match(Set dst (MoveI2F src)); | |
| 10332 effect(DEF dst, USE src); | |
| 10333 | |
| 10334 ins_cost(125); | |
| 10335 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %} | |
| 4759 | 10336 ins_encode %{ |
| 10337 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10338 %} | |
| 0 | 10339 ins_pipe(pipe_slow); |
| 10340 %} | |
| 10341 | |
| 10342 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{ | |
| 10343 match(Set dst (MoveD2L src)); | |
| 10344 effect(DEF dst, USE src); | |
| 10345 | |
| 10346 ins_cost(125); | |
| 10347 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %} | |
| 4759 | 10348 ins_encode %{ |
| 10349 __ movq($dst$$Register, Address(rsp, $src$$disp)); | |
| 10350 %} | |
| 0 | 10351 ins_pipe(ialu_reg_mem); |
| 10352 %} | |
| 10353 | |
| 10354 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{ | |
| 10355 predicate(!UseXmmLoadAndClearUpper); | |
| 10356 match(Set dst (MoveL2D src)); | |
| 10357 effect(DEF dst, USE src); | |
| 10358 | |
| 10359 ins_cost(125); | |
| 10360 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 4759 | 10361 ins_encode %{ |
| 10362 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10363 %} | |
| 0 | 10364 ins_pipe(pipe_slow); |
| 10365 %} | |
| 10366 | |
| 10367 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 10368 predicate(UseXmmLoadAndClearUpper); | |
| 10369 match(Set dst (MoveL2D src)); | |
| 10370 effect(DEF dst, USE src); | |
| 10371 | |
| 10372 ins_cost(125); | |
| 10373 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 4759 | 10374 ins_encode %{ |
| 10375 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10376 %} | |
| 0 | 10377 ins_pipe(pipe_slow); |
| 10378 %} | |
| 10379 | |
| 10380 | |
| 10381 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 10382 match(Set dst (MoveF2I src)); | |
| 10383 effect(DEF dst, USE src); | |
| 10384 | |
| 10385 ins_cost(95); // XXX | |
| 10386 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %} | |
| 4759 | 10387 ins_encode %{ |
| 10388 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 10389 %} | |
| 0 | 10390 ins_pipe(pipe_slow); |
| 10391 %} | |
| 10392 | |
| 10393 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ | |
| 10394 match(Set dst (MoveI2F src)); | |
| 10395 effect(DEF dst, USE src); | |
| 10396 | |
| 10397 ins_cost(100); | |
| 10398 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %} | |
| 4759 | 10399 ins_encode %{ |
| 10400 __ movl(Address(rsp, $dst$$disp), $src$$Register); | |
| 10401 %} | |
| 0 | 10402 ins_pipe( ialu_mem_reg ); |
| 10403 %} | |
| 10404 | |
| 10405 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 10406 match(Set dst (MoveD2L src)); | |
| 10407 effect(DEF dst, USE src); | |
| 10408 | |
| 10409 ins_cost(95); // XXX | |
| 10410 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %} | |
| 4759 | 10411 ins_encode %{ |
| 10412 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 10413 %} | |
| 0 | 10414 ins_pipe(pipe_slow); |
| 10415 %} | |
| 10416 | |
| 10417 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{ | |
| 10418 match(Set dst (MoveL2D src)); | |
| 10419 effect(DEF dst, USE src); | |
| 10420 | |
| 10421 ins_cost(100); | |
| 10422 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %} | |
| 4759 | 10423 ins_encode %{ |
| 10424 __ movq(Address(rsp, $dst$$disp), $src$$Register); | |
| 10425 %} | |
| 0 | 10426 ins_pipe(ialu_mem_reg); |
| 10427 %} | |
| 10428 | |
| 10429 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{ | |
| 10430 match(Set dst (MoveF2I src)); | |
| 10431 effect(DEF dst, USE src); | |
| 10432 ins_cost(85); | |
| 10433 format %{ "movd $dst,$src\t# MoveF2I" %} | |
| 4759 | 10434 ins_encode %{ |
| 10435 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 10436 %} | |
| 0 | 10437 ins_pipe( pipe_slow ); |
| 10438 %} | |
| 10439 | |
| 10440 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{ | |
| 10441 match(Set dst (MoveD2L src)); | |
| 10442 effect(DEF dst, USE src); | |
| 10443 ins_cost(85); | |
| 10444 format %{ "movd $dst,$src\t# MoveD2L" %} | |
| 4759 | 10445 ins_encode %{ |
| 10446 __ movdq($dst$$Register, $src$$XMMRegister); | |
| 10447 %} | |
| 0 | 10448 ins_pipe( pipe_slow ); |
| 10449 %} | |
| 10450 | |
| 10451 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{ | |
| 10452 match(Set dst (MoveI2F src)); | |
| 10453 effect(DEF dst, USE src); | |
|
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10454 ins_cost(100); |
| 0 | 10455 format %{ "movd $dst,$src\t# MoveI2F" %} |
| 4759 | 10456 ins_encode %{ |
| 10457 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10458 %} | |
| 0 | 10459 ins_pipe( pipe_slow ); |
| 10460 %} | |
| 10461 | |
| 10462 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{ | |
| 10463 match(Set dst (MoveL2D src)); | |
| 10464 effect(DEF dst, USE src); | |
|
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10465 ins_cost(100); |
| 0 | 10466 format %{ "movd $dst,$src\t# MoveL2D" %} |
| 4759 | 10467 ins_encode %{ |
| 10468 __ movdq($dst$$XMMRegister, $src$$Register); | |
| 10469 %} | |
| 0 | 10470 ins_pipe( pipe_slow ); |
| 10471 %} | |
| 10472 | |
| 10473 | |
| 10474 // ======================================================================= | |
| 10475 // fast clearing of an array | |
| 10476 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, | |
| 10477 rFlagsReg cr) | |
| 10478 %{ | |
|
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10479 predicate(!UseFastStosb); |
| 0 | 10480 match(Set dummy (ClearArray cnt base)); |
| 10481 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 10482 | |
|
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10483 format %{ "xorq rax, rax\t# ClearArray:\n\t" |
|
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10484 "rep stosq\t# Store rax to *rdi++ while rcx--" %} |
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10485 ins_encode %{ |
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10486 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
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10487 %} |
| 0 | 10488 ins_pipe(pipe_slow); |
| 10489 %} | |
| 10490 | |
|
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10491 instruct rep_fast_stosb(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, |
|
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10492 rFlagsReg cr) |
|
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10493 %{ |
|
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10494 predicate(UseFastStosb); |
|
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10495 match(Set dummy (ClearArray cnt base)); |
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10496 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); |
|
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10497 format %{ "xorq rax, rax\t# ClearArray:\n\t" |
|
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10498 "shlq rcx,3\t# Convert doublewords to bytes\n\t" |
|
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10499 "rep stosb\t# Store rax to *rdi++ while rcx--" %} |
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10500 ins_encode %{ |
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10501 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10502 %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10503 ins_pipe( pipe_slow ); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10504 %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10505 |
| 2262 | 10506 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2, |
| 10507 rax_RegI result, regD tmp1, rFlagsReg cr) | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10508 %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10509 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 10510 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 10511 | |
| 10512 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10513 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10514 __ string_compare($str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10515 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 10516 $tmp1$$XMMRegister); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10517 %} |
| 681 | 10518 ins_pipe( pipe_slow ); |
| 10519 %} | |
| 10520 | |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10521 // fast search of substring with known size. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10522 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10523 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10524 %{ |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10525 predicate(UseSSE42Intrinsics); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10526 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10527 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10528 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10529 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10530 ins_encode %{ |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10531 int icnt2 = (int)$int_cnt2$$constant; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10532 if (icnt2 >= 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10533 // IndexOf for constant substrings with size >= 8 elements |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10534 // which don't need to be loaded through stack. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10535 __ string_indexofC8($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10536 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10537 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10538 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10539 } else { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10540 // Small strings are loaded through stack if they cross page boundary. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10541 __ string_indexof($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10542 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10543 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10544 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10545 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10546 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10547 ins_pipe( pipe_slow ); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10548 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10549 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10550 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2, |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10551 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr) |
| 681 | 10552 %{ |
| 10553 predicate(UseSSE42Intrinsics); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10554 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10555 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10556 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10557 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10558 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10559 __ string_indexof($str1$$Register, $str2$$Register, |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10560 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10561 (-1), $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10562 $vec$$XMMRegister, $tmp$$Register); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10563 %} |
| 681 | 10564 ins_pipe( pipe_slow ); |
| 10565 %} | |
| 10566 | |
| 10567 // fast string equals | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10568 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10569 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10570 %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10571 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10572 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10573 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10574 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10575 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10576 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10577 $cnt$$Register, $result$$Register, $tmp3$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10578 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10579 %} |
| 0 | 10580 ins_pipe( pipe_slow ); |
| 10581 %} | |
| 10582 | |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10583 // fast array equals |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10584 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10585 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr) |
| 681 | 10586 %{ |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10587 match(Set result (AryEq ary1 ary2)); |
| 681 | 10588 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10589 //ins_cost(300); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10590 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10591 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10592 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10593 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10594 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10595 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10596 %} |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10597 ins_pipe( pipe_slow ); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10598 %} |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10599 |
|
7637
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10600 // encode char[] to byte[] in ISO_8859_1 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10601 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10602 regD tmp1, regD tmp2, regD tmp3, regD tmp4, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10603 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10604 match(Set result (EncodeISOArray src (Binary dst len))); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10605 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10606 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10607 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10608 ins_encode %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10609 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10610 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10611 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10612 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10613 ins_pipe( pipe_slow ); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10614 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10615 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10616 |
| 0 | 10617 //----------Control Flow Instructions------------------------------------------ |
| 10618 // Signed compare Instructions | |
| 10619 | |
| 10620 // XXX more variants!! | |
| 10621 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) | |
| 10622 %{ | |
| 10623 match(Set cr (CmpI op1 op2)); | |
| 10624 effect(DEF cr, USE op1, USE op2); | |
| 10625 | |
| 10626 format %{ "cmpl $op1, $op2" %} | |
| 10627 opcode(0x3B); /* Opcode 3B /r */ | |
| 10628 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10629 ins_pipe(ialu_cr_reg_reg); | |
| 10630 %} | |
| 10631 | |
| 10632 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) | |
| 10633 %{ | |
| 10634 match(Set cr (CmpI op1 op2)); | |
| 10635 | |
| 10636 format %{ "cmpl $op1, $op2" %} | |
| 10637 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 10638 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 10639 ins_pipe(ialu_cr_reg_imm); | |
| 10640 %} | |
| 10641 | |
| 10642 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2) | |
| 10643 %{ | |
| 10644 match(Set cr (CmpI op1 (LoadI op2))); | |
| 10645 | |
| 10646 ins_cost(500); // XXX | |
| 10647 format %{ "cmpl $op1, $op2" %} | |
| 10648 opcode(0x3B); /* Opcode 3B /r */ | |
| 10649 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10650 ins_pipe(ialu_cr_reg_mem); | |
| 10651 %} | |
| 10652 | |
| 10653 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero) | |
| 10654 %{ | |
| 10655 match(Set cr (CmpI src zero)); | |
| 10656 | |
| 10657 format %{ "testl $src, $src" %} | |
| 10658 opcode(0x85); | |
| 10659 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 10660 ins_pipe(ialu_cr_reg_imm); | |
| 10661 %} | |
| 10662 | |
| 10663 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero) | |
| 10664 %{ | |
| 10665 match(Set cr (CmpI (AndI src con) zero)); | |
| 10666 | |
| 10667 format %{ "testl $src, $con" %} | |
| 10668 opcode(0xF7, 0x00); | |
| 10669 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con)); | |
| 10670 ins_pipe(ialu_cr_reg_imm); | |
| 10671 %} | |
| 10672 | |
| 10673 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero) | |
| 10674 %{ | |
| 10675 match(Set cr (CmpI (AndI src (LoadI mem)) zero)); | |
| 10676 | |
| 10677 format %{ "testl $src, $mem" %} | |
| 10678 opcode(0x85); | |
| 10679 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 10680 ins_pipe(ialu_cr_reg_mem); | |
| 10681 %} | |
| 10682 | |
| 10683 // Unsigned compare Instructions; really, same as signed except they | |
| 10684 // produce an rFlagsRegU instead of rFlagsReg. | |
| 10685 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2) | |
| 10686 %{ | |
| 10687 match(Set cr (CmpU op1 op2)); | |
| 10688 | |
| 10689 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10690 opcode(0x3B); /* Opcode 3B /r */ | |
| 10691 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10692 ins_pipe(ialu_cr_reg_reg); | |
| 10693 %} | |
| 10694 | |
| 10695 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2) | |
| 10696 %{ | |
| 10697 match(Set cr (CmpU op1 op2)); | |
| 10698 | |
| 10699 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10700 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 10701 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 10702 ins_pipe(ialu_cr_reg_imm); | |
| 10703 %} | |
| 10704 | |
| 10705 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2) | |
| 10706 %{ | |
| 10707 match(Set cr (CmpU op1 (LoadI op2))); | |
| 10708 | |
| 10709 ins_cost(500); // XXX | |
| 10710 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10711 opcode(0x3B); /* Opcode 3B /r */ | |
| 10712 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10713 ins_pipe(ialu_cr_reg_mem); | |
| 10714 %} | |
| 10715 | |
| 10716 // // // Cisc-spilled version of cmpU_rReg | |
| 10717 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2) | |
| 10718 // //%{ | |
| 10719 // // match(Set cr (CmpU (LoadI op1) op2)); | |
| 10720 // // | |
| 10721 // // format %{ "CMPu $op1,$op2" %} | |
| 10722 // // ins_cost(500); | |
| 10723 // // opcode(0x39); /* Opcode 39 /r */ | |
| 10724 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 10725 // //%} | |
| 10726 | |
| 10727 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero) | |
| 10728 %{ | |
| 10729 match(Set cr (CmpU src zero)); | |
| 10730 | |
| 10731 format %{ "testl $src, $src\t# unsigned" %} | |
| 10732 opcode(0x85); | |
| 10733 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 10734 ins_pipe(ialu_cr_reg_imm); | |
| 10735 %} | |
| 10736 | |
| 10737 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2) | |
| 10738 %{ | |
| 10739 match(Set cr (CmpP op1 op2)); | |
| 10740 | |
| 10741 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 10742 opcode(0x3B); /* Opcode 3B /r */ | |
| 10743 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10744 ins_pipe(ialu_cr_reg_reg); | |
| 10745 %} | |
| 10746 | |
| 10747 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) | |
| 10748 %{ | |
| 10749 match(Set cr (CmpP op1 (LoadP op2))); | |
| 10750 | |
| 10751 ins_cost(500); // XXX | |
| 10752 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 10753 opcode(0x3B); /* Opcode 3B /r */ | |
| 10754 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10755 ins_pipe(ialu_cr_reg_mem); | |
| 10756 %} | |
| 10757 | |
| 10758 // // // Cisc-spilled version of cmpP_rReg | |
| 10759 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2) | |
| 10760 // //%{ | |
| 10761 // // match(Set cr (CmpP (LoadP op1) op2)); | |
| 10762 // // | |
| 10763 // // format %{ "CMPu $op1,$op2" %} | |
| 10764 // // ins_cost(500); | |
| 10765 // // opcode(0x39); /* Opcode 39 /r */ | |
| 10766 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 10767 // //%} | |
| 10768 | |
| 10769 // XXX this is generalized by compP_rReg_mem??? | |
| 10770 // Compare raw pointer (used in out-of-heap check). | |
| 10771 // Only works because non-oop pointers must be raw pointers | |
| 10772 // and raw pointers have no anti-dependencies. | |
| 10773 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) | |
| 10774 %{ | |
|
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10775 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none); |
| 0 | 10776 match(Set cr (CmpP op1 (LoadP op2))); |
| 10777 | |
| 10778 format %{ "cmpq $op1, $op2\t# raw ptr" %} | |
| 10779 opcode(0x3B); /* Opcode 3B /r */ | |
| 10780 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10781 ins_pipe(ialu_cr_reg_mem); | |
| 10782 %} | |
| 10783 | |
| 10784 // This will generate a signed flags result. This should be OK since | |
| 10785 // any compare to a zero should be eq/neq. | |
| 10786 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero) | |
| 10787 %{ | |
| 10788 match(Set cr (CmpP src zero)); | |
| 10789 | |
| 10790 format %{ "testq $src, $src\t# ptr" %} | |
| 10791 opcode(0x85); | |
| 10792 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 10793 ins_pipe(ialu_cr_reg_imm); | |
| 10794 %} | |
| 10795 | |
| 10796 // This will generate a signed flags result. This should be OK since | |
| 10797 // any compare to a zero should be eq/neq. | |
|
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10798 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) |
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10799 %{ |
|
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10800 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 10801 match(Set cr (CmpP (LoadP op) zero)); |
| 10802 | |
| 10803 ins_cost(500); // XXX | |
| 10804 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} | |
| 10805 opcode(0xF7); /* Opcode F7 /0 */ | |
| 10806 ins_encode(REX_mem_wide(op), | |
| 10807 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF)); | |
| 10808 ins_pipe(ialu_cr_reg_imm); | |
| 10809 %} | |
| 10810 | |
|
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10811 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) |
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10812 %{ |
|
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10813 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
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10814 match(Set cr (CmpP (LoadP mem) zero)); |
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10815 |
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10816 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} |
|
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10817 ins_encode %{ |
|
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10818 __ cmpq(r12, $mem$$Address); |
|
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10819 %} |
|
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10820 ins_pipe(ialu_cr_reg_mem); |
|
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10821 %} |
|
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|
10822 |
|
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|
10823 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2) |
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10824 %{ |
|
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10825 match(Set cr (CmpN op1 op2)); |
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|
10826 |
|
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|
10827 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
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10828 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %} |
|
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10829 ins_pipe(ialu_cr_reg_reg); |
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|
10830 %} |
|
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|
10831 |
|
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|
10832 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem) |
|
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10833 %{ |
|
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10834 match(Set cr (CmpN src (LoadN mem))); |
|
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10835 |
|
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10836 format %{ "cmpl $src, $mem\t# compressed ptr" %} |
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10837 ins_encode %{ |
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|
10838 __ cmpl($src$$Register, $mem$$Address); |
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10839 %} |
|
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|
10840 ins_pipe(ialu_cr_reg_mem); |
|
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|
10841 %} |
|
660978a2a31a
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|
10842 |
|
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|
10843 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{ |
|
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10844 match(Set cr (CmpN op1 op2)); |
|
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|
10845 |
|
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|
10846 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
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10847 ins_encode %{ |
|
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10848 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant); |
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10849 %} |
|
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10850 ins_pipe(ialu_cr_reg_imm); |
|
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|
10851 %} |
|
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|
10852 |
|
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|
10853 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src) |
|
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10854 %{ |
|
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10855 match(Set cr (CmpN src (LoadN mem))); |
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10856 |
|
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10857 format %{ "cmpl $mem, $src\t# compressed ptr" %} |
|
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10858 ins_encode %{ |
|
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|
10859 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
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10860 %} |
|
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|
10861 ins_pipe(ialu_cr_reg_mem); |
|
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10862 %} |
|
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|
10863 |
|
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10864 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{ |
|
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10865 match(Set cr (CmpN op1 op2)); |
|
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|
10866 |
|
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|
10867 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %} |
|
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|
10868 ins_encode %{ |
|
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|
10869 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant); |
|
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|
10870 %} |
|
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|
10871 ins_pipe(ialu_cr_reg_imm); |
|
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|
10872 %} |
|
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|
10873 |
|
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|
10874 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src) |
|
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|
10875 %{ |
|
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|
10876 match(Set cr (CmpN src (LoadNKlass mem))); |
|
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|
10877 |
|
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|
10878 format %{ "cmpl $mem, $src\t# compressed klass ptr" %} |
|
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|
10879 ins_encode %{ |
|
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|
10880 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant); |
|
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|
10881 %} |
|
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|
10882 ins_pipe(ialu_cr_reg_mem); |
|
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|
10883 %} |
|
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|
10884 |
|
113
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|
10885 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{ |
|
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10886 match(Set cr (CmpN src zero)); |
|
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|
10887 |
|
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|
10888 format %{ "testl $src, $src\t# compressed ptr" %} |
|
113
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10889 ins_encode %{ __ testl($src$$Register, $src$$Register); %} |
|
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|
10890 ins_pipe(ialu_cr_reg_imm); |
|
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|
10891 %} |
|
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|
10892 |
|
642
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|
10893 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero) |
|
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|
10894 %{ |
|
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|
10895 predicate(Universe::narrow_oop_base() != NULL); |
|
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10896 match(Set cr (CmpN (LoadN mem) zero)); |
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|
10897 |
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|
10898 ins_cost(500); // XXX |
|
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10899 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %} |
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10900 ins_encode %{ |
|
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|
10901 __ cmpl($mem$$Address, (int)0xFFFFFFFF); |
|
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|
10902 %} |
|
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|
10903 ins_pipe(ialu_cr_reg_mem); |
|
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|
10904 %} |
|
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|
10905 |
|
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|
10906 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero) |
|
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|
10907 %{ |
|
6848
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|
10908 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL)); |
|
642
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|
10909 match(Set cr (CmpN (LoadN mem) zero)); |
|
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|
10910 |
|
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|
10911 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %} |
|
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|
10912 ins_encode %{ |
|
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|
10913 __ cmpl(r12, $mem$$Address); |
|
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|
10914 %} |
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|
10915 ins_pipe(ialu_cr_reg_mem); |
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|
10916 %} |
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|
10917 |
| 0 | 10918 // Yanked all unsigned pointer compare operations. |
| 10919 // Pointer compares are done with CmpP which is already unsigned. | |
| 10920 | |
| 10921 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) | |
| 10922 %{ | |
| 10923 match(Set cr (CmpL op1 op2)); | |
| 10924 | |
| 10925 format %{ "cmpq $op1, $op2" %} | |
| 10926 opcode(0x3B); /* Opcode 3B /r */ | |
| 10927 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10928 ins_pipe(ialu_cr_reg_reg); | |
| 10929 %} | |
| 10930 | |
| 10931 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) | |
| 10932 %{ | |
| 10933 match(Set cr (CmpL op1 op2)); | |
| 10934 | |
| 10935 format %{ "cmpq $op1, $op2" %} | |
| 10936 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 10937 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2)); | |
| 10938 ins_pipe(ialu_cr_reg_imm); | |
| 10939 %} | |
| 10940 | |
| 10941 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2) | |
| 10942 %{ | |
| 10943 match(Set cr (CmpL op1 (LoadL op2))); | |
| 10944 | |
| 10945 format %{ "cmpq $op1, $op2" %} | |
| 10946 opcode(0x3B); /* Opcode 3B /r */ | |
| 10947 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10948 ins_pipe(ialu_cr_reg_mem); | |
| 10949 %} | |
| 10950 | |
| 10951 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero) | |
| 10952 %{ | |
| 10953 match(Set cr (CmpL src zero)); | |
| 10954 | |
| 10955 format %{ "testq $src, $src" %} | |
| 10956 opcode(0x85); | |
| 10957 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 10958 ins_pipe(ialu_cr_reg_imm); | |
| 10959 %} | |
| 10960 | |
| 10961 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero) | |
| 10962 %{ | |
| 10963 match(Set cr (CmpL (AndL src con) zero)); | |
| 10964 | |
| 10965 format %{ "testq $src, $con\t# long" %} | |
| 10966 opcode(0xF7, 0x00); | |
| 10967 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con)); | |
| 10968 ins_pipe(ialu_cr_reg_imm); | |
| 10969 %} | |
| 10970 | |
| 10971 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero) | |
| 10972 %{ | |
| 10973 match(Set cr (CmpL (AndL src (LoadL mem)) zero)); | |
| 10974 | |
| 10975 format %{ "testq $src, $mem" %} | |
| 10976 opcode(0x85); | |
| 10977 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 10978 ins_pipe(ialu_cr_reg_mem); | |
| 10979 %} | |
| 10980 | |
| 10981 // Manifest a CmpL result in an integer register. Very painful. | |
| 10982 // This is the test to avoid. | |
| 10983 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags) | |
| 10984 %{ | |
| 10985 match(Set dst (CmpL3 src1 src2)); | |
| 10986 effect(KILL flags); | |
| 10987 | |
| 10988 ins_cost(275); // XXX | |
| 10989 format %{ "cmpq $src1, $src2\t# CmpL3\n\t" | |
| 10990 "movl $dst, -1\n\t" | |
| 10991 "jl,s done\n\t" | |
| 10992 "setne $dst\n\t" | |
| 10993 "movzbl $dst, $dst\n\t" | |
| 10994 "done:" %} | |
| 10995 ins_encode(cmpl3_flag(src1, src2, dst)); | |
| 10996 ins_pipe(pipe_slow); | |
| 10997 %} | |
| 10998 | |
| 10999 //----------Max and Min-------------------------------------------------------- | |
| 11000 // Min Instructions | |
| 11001 | |
| 11002 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) | |
| 11003 %{ | |
| 11004 effect(USE_DEF dst, USE src, USE cr); | |
| 11005 | |
| 11006 format %{ "cmovlgt $dst, $src\t# min" %} | |
| 11007 opcode(0x0F, 0x4F); | |
| 11008 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 11009 ins_pipe(pipe_cmov_reg); | |
| 11010 %} | |
| 11011 | |
| 11012 | |
| 11013 instruct minI_rReg(rRegI dst, rRegI src) | |
| 11014 %{ | |
| 11015 match(Set dst (MinI dst src)); | |
| 11016 | |
| 11017 ins_cost(200); | |
| 11018 expand %{ | |
| 11019 rFlagsReg cr; | |
| 11020 compI_rReg(cr, dst, src); | |
| 11021 cmovI_reg_g(dst, src, cr); | |
| 11022 %} | |
| 11023 %} | |
| 11024 | |
| 11025 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr) | |
| 11026 %{ | |
| 11027 effect(USE_DEF dst, USE src, USE cr); | |
| 11028 | |
| 11029 format %{ "cmovllt $dst, $src\t# max" %} | |
| 11030 opcode(0x0F, 0x4C); | |
| 11031 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 11032 ins_pipe(pipe_cmov_reg); | |
| 11033 %} | |
| 11034 | |
| 11035 | |
| 11036 instruct maxI_rReg(rRegI dst, rRegI src) | |
| 11037 %{ | |
| 11038 match(Set dst (MaxI dst src)); | |
| 11039 | |
| 11040 ins_cost(200); | |
| 11041 expand %{ | |
| 11042 rFlagsReg cr; | |
| 11043 compI_rReg(cr, dst, src); | |
| 11044 cmovI_reg_l(dst, src, cr); | |
| 11045 %} | |
| 11046 %} | |
| 11047 | |
| 11048 // ============================================================================ | |
| 11049 // Branch Instructions | |
| 11050 | |
| 11051 // Jump Direct - Label defines a relative address from JMP+1 | |
| 11052 instruct jmpDir(label labl) | |
| 11053 %{ | |
| 11054 match(Goto); | |
| 11055 effect(USE labl); | |
| 11056 | |
| 11057 ins_cost(300); | |
| 11058 format %{ "jmp $labl" %} | |
| 11059 size(5); | |
| 3851 | 11060 ins_encode %{ |
| 11061 Label* L = $labl$$label; | |
| 11062 __ jmp(*L, false); // Always long jump | |
| 11063 %} | |
| 0 | 11064 ins_pipe(pipe_jmp); |
| 11065 %} | |
| 11066 | |
| 11067 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11068 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl) | |
| 11069 %{ | |
| 11070 match(If cop cr); | |
| 11071 effect(USE labl); | |
| 11072 | |
| 11073 ins_cost(300); | |
| 11074 format %{ "j$cop $labl" %} | |
| 11075 size(6); | |
| 3851 | 11076 ins_encode %{ |
| 11077 Label* L = $labl$$label; | |
| 11078 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11079 %} | |
| 0 | 11080 ins_pipe(pipe_jcc); |
| 11081 %} | |
| 11082 | |
| 11083 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11084 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl) | |
| 11085 %{ | |
| 11086 match(CountedLoopEnd cop cr); | |
| 11087 effect(USE labl); | |
| 11088 | |
| 11089 ins_cost(300); | |
| 11090 format %{ "j$cop $labl\t# loop end" %} | |
| 11091 size(6); | |
| 3851 | 11092 ins_encode %{ |
| 11093 Label* L = $labl$$label; | |
| 11094 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11095 %} | |
| 0 | 11096 ins_pipe(pipe_jcc); |
| 11097 %} | |
| 11098 | |
| 11099 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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11100 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 11101 match(CountedLoopEnd cop cmp); |
| 11102 effect(USE labl); | |
| 11103 | |
| 11104 ins_cost(300); | |
| 11105 format %{ "j$cop,u $labl\t# loop end" %} | |
| 11106 size(6); | |
| 3851 | 11107 ins_encode %{ |
| 11108 Label* L = $labl$$label; | |
| 11109 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11110 %} | |
| 0 | 11111 ins_pipe(pipe_jcc); |
| 11112 %} | |
| 11113 | |
|
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11114 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
11115 match(CountedLoopEnd cop cmp); |
|
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|
11116 effect(USE labl); |
|
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|
11117 |
|
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|
11118 ins_cost(200); |
|
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|
11119 format %{ "j$cop,u $labl\t# loop end" %} |
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|
11120 size(6); |
| 3851 | 11121 ins_encode %{ |
| 11122 Label* L = $labl$$label; | |
| 11123 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11124 %} | |
|
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|
11125 ins_pipe(pipe_jcc); |
|
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|
11126 %} |
|
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|
11127 |
| 0 | 11128 // Jump Direct Conditional - using unsigned comparison |
|
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|
11129 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 11130 match(If cop cmp); |
| 11131 effect(USE labl); | |
| 11132 | |
| 11133 ins_cost(300); | |
|
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|
11134 format %{ "j$cop,u $labl" %} |
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|
11135 size(6); |
| 3851 | 11136 ins_encode %{ |
| 11137 Label* L = $labl$$label; | |
| 11138 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11139 %} | |
|
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|
11140 ins_pipe(pipe_jcc); |
|
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|
11141 %} |
|
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|
11142 |
|
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|
11143 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
11144 match(If cop cmp); |
|
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|
11145 effect(USE labl); |
|
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|
11146 |
|
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|
11147 ins_cost(200); |
|
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|
11148 format %{ "j$cop,u $labl" %} |
| 0 | 11149 size(6); |
| 3851 | 11150 ins_encode %{ |
| 11151 Label* L = $labl$$label; | |
| 11152 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11153 %} | |
| 0 | 11154 ins_pipe(pipe_jcc); |
| 11155 %} | |
| 11156 | |
|
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11157 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
11158 match(If cop cmp); |
|
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|
11159 effect(USE labl); |
|
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diff
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|
11160 |
|
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|
11161 ins_cost(200); |
|
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|
11162 format %{ $$template |
|
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|
11163 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
11164 $$emit$$"jp,u $labl\n\t" |
|
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|
11165 $$emit$$"j$cop,u $labl" |
|
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|
11166 } else { |
|
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|
11167 $$emit$$"jp,u done\n\t" |
|
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11168 $$emit$$"j$cop,u $labl\n\t" |
|
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11169 $$emit$$"done:" |
|
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|
11170 } |
|
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|
11171 %} |
|
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|
11172 ins_encode %{ |
|
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|
11173 Label* l = $labl$$label; |
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11174 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 11175 __ jcc(Assembler::parity, *l, false); |
| 11176 __ jcc(Assembler::notEqual, *l, false); | |
|
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11177 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 11178 Label done; |
| 11179 __ jccb(Assembler::parity, done); | |
| 11180 __ jcc(Assembler::equal, *l, false); | |
| 11181 __ bind(done); | |
|
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11182 } else { |
|
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|
11183 ShouldNotReachHere(); |
|
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11184 } |
|
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|
11185 %} |
|
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|
11186 ins_pipe(pipe_jcc); |
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11187 %} |
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11188 |
| 0 | 11189 // ============================================================================ |
| 11190 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary | |
| 11191 // superklass array for an instance of the superklass. Set a hidden | |
| 11192 // internal cache on a hit (cache is checked with exposed code in | |
| 11193 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The | |
| 11194 // encoding ALSO sets flags. | |
| 11195 | |
| 11196 instruct partialSubtypeCheck(rdi_RegP result, | |
| 11197 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 11198 rFlagsReg cr) | |
| 11199 %{ | |
| 11200 match(Set result (PartialSubtypeCheck sub super)); | |
| 11201 effect(KILL rcx, KILL cr); | |
| 11202 | |
| 11203 ins_cost(1100); // slightly larger than the next version | |
|
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|
11204 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t" |
|
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|
11205 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t" |
|
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11206 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 11207 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t" |
| 11208 "jne,s miss\t\t# Missed: rdi not-zero\n\t" | |
|
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|
11209 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t" |
| 0 | 11210 "xorq $result, $result\t\t Hit: rdi zero\n\t" |
| 11211 "miss:\t" %} | |
| 11212 | |
| 11213 opcode(0x1); // Force a XOR of RDI | |
| 11214 ins_encode(enc_PartialSubtypeCheck()); | |
| 11215 ins_pipe(pipe_slow); | |
| 11216 %} | |
| 11217 | |
| 11218 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr, | |
| 11219 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 11220 immP0 zero, | |
| 11221 rdi_RegP result) | |
| 11222 %{ | |
| 11223 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 11224 effect(KILL rcx, KILL result); | |
| 11225 | |
| 11226 ins_cost(1000); | |
|
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|
11227 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t" |
|
6725
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11228 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t" |
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11229 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 11230 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t" |
| 11231 "jne,s miss\t\t# Missed: flags nz\n\t" | |
|
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|
11232 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t" |
| 0 | 11233 "miss:\t" %} |
| 11234 | |
| 11235 opcode(0x0); // No need to XOR RDI | |
| 11236 ins_encode(enc_PartialSubtypeCheck()); | |
| 11237 ins_pipe(pipe_slow); | |
| 11238 %} | |
| 11239 | |
| 11240 // ============================================================================ | |
| 11241 // Branch Instructions -- short offset versions | |
| 11242 // | |
| 11243 // These instructions are used to replace jumps of a long offset (the default | |
| 11244 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 11245 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 11246 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 11247 // method in the MachNode which can be used to do in-place replacement of the | |
| 11248 // long variant with the shorter variant. The compiler will determine if a | |
| 11249 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 11250 // specific code section of the file. | |
| 11251 | |
| 11252 // Jump Direct - Label defines a relative address from JMP+1 | |
|
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|
11253 instruct jmpDir_short(label labl) %{ |
| 0 | 11254 match(Goto); |
| 11255 effect(USE labl); | |
| 11256 | |
| 11257 ins_cost(300); | |
| 11258 format %{ "jmp,s $labl" %} | |
| 11259 size(2); | |
| 3851 | 11260 ins_encode %{ |
| 11261 Label* L = $labl$$label; | |
| 11262 __ jmpb(*L); | |
| 11263 %} | |
| 0 | 11264 ins_pipe(pipe_jmp); |
| 11265 ins_short_branch(1); | |
| 11266 %} | |
| 11267 | |
| 11268 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
11269 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 11270 match(If cop cr); |
| 11271 effect(USE labl); | |
| 11272 | |
| 11273 ins_cost(300); | |
| 11274 format %{ "j$cop,s $labl" %} | |
| 11275 size(2); | |
| 3851 | 11276 ins_encode %{ |
| 11277 Label* L = $labl$$label; | |
| 11278 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11279 %} | |
| 0 | 11280 ins_pipe(pipe_jcc); |
| 11281 ins_short_branch(1); | |
| 11282 %} | |
| 11283 | |
| 11284 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
11285 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 11286 match(CountedLoopEnd cop cr); |
| 11287 effect(USE labl); | |
| 11288 | |
| 11289 ins_cost(300); | |
|
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|
11290 format %{ "j$cop,s $labl\t# loop end" %} |
| 0 | 11291 size(2); |
| 3851 | 11292 ins_encode %{ |
| 11293 Label* L = $labl$$label; | |
| 11294 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11295 %} | |
| 0 | 11296 ins_pipe(pipe_jcc); |
| 11297 ins_short_branch(1); | |
| 11298 %} | |
| 11299 | |
| 11300 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
11301 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
11302 match(CountedLoopEnd cop cmp); |
|
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|
11303 effect(USE labl); |
|
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|
11304 |
|
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|
11305 ins_cost(300); |
|
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|
11306 format %{ "j$cop,us $labl\t# loop end" %} |
|
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|
11307 size(2); |
| 3851 | 11308 ins_encode %{ |
| 11309 Label* L = $labl$$label; | |
| 11310 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11311 %} | |
|
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|
11312 ins_pipe(pipe_jcc); |
|
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|
11313 ins_short_branch(1); |
|
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|
11314 %} |
|
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|
11315 |
|
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|
11316 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 11317 match(CountedLoopEnd cop cmp); |
| 11318 effect(USE labl); | |
| 11319 | |
| 11320 ins_cost(300); | |
|
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|
11321 format %{ "j$cop,us $labl\t# loop end" %} |
|
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|
11322 size(2); |
| 3851 | 11323 ins_encode %{ |
| 11324 Label* L = $labl$$label; | |
| 11325 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11326 %} | |
|
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|
11327 ins_pipe(pipe_jcc); |
|
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|
11328 ins_short_branch(1); |
|
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|
11329 %} |
|
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|
11330 |
|
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|
11331 // Jump Direct Conditional - using unsigned comparison |
|
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|
11332 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
11333 match(If cop cmp); |
|
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|
11334 effect(USE labl); |
|
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|
11335 |
|
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|
11336 ins_cost(300); |
| 0 | 11337 format %{ "j$cop,us $labl" %} |
| 11338 size(2); | |
| 3851 | 11339 ins_encode %{ |
| 11340 Label* L = $labl$$label; | |
| 11341 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11342 %} | |
| 0 | 11343 ins_pipe(pipe_jcc); |
| 11344 ins_short_branch(1); | |
| 11345 %} | |
| 11346 | |
|
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|
11347 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 11348 match(If cop cmp); |
| 11349 effect(USE labl); | |
| 11350 | |
| 11351 ins_cost(300); | |
| 11352 format %{ "j$cop,us $labl" %} | |
| 11353 size(2); | |
| 3851 | 11354 ins_encode %{ |
| 11355 Label* L = $labl$$label; | |
| 11356 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11357 %} | |
| 0 | 11358 ins_pipe(pipe_jcc); |
| 11359 ins_short_branch(1); | |
| 11360 %} | |
| 11361 | |
|
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|
11362 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
11363 match(If cop cmp); |
|
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|
11364 effect(USE labl); |
|
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|
11365 |
|
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|
11366 ins_cost(300); |
|
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|
11367 format %{ $$template |
|
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|
11368 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
11369 $$emit$$"jp,u,s $labl\n\t" |
|
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|
11370 $$emit$$"j$cop,u,s $labl" |
|
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|
11371 } else { |
|
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|
11372 $$emit$$"jp,u,s done\n\t" |
|
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|
11373 $$emit$$"j$cop,u,s $labl\n\t" |
|
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|
11374 $$emit$$"done:" |
|
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|
11375 } |
|
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|
11376 %} |
|
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|
11377 size(4); |
|
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|
11378 ins_encode %{ |
|
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|
11379 Label* l = $labl$$label; |
|
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|
11380 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 11381 __ jccb(Assembler::parity, *l); |
| 11382 __ jccb(Assembler::notEqual, *l); | |
|
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|
11383 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 11384 Label done; |
| 11385 __ jccb(Assembler::parity, done); | |
| 11386 __ jccb(Assembler::equal, *l); | |
| 11387 __ bind(done); | |
|
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|
11388 } else { |
| 3851 | 11389 ShouldNotReachHere(); |
| 11390 } | |
|
415
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|
11391 %} |
|
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changeset
|
11392 ins_pipe(pipe_jcc); |
|
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|
11393 ins_short_branch(1); |
|
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|
11394 %} |
|
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|
11395 |
| 0 | 11396 // ============================================================================ |
| 11397 // inlined locking and unlocking | |
| 11398 | |
| 11399 instruct cmpFastLock(rFlagsReg cr, | |
| 4777 | 11400 rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) |
| 0 | 11401 %{ |
| 11402 match(Set cr (FastLock object box)); | |
| 4777 | 11403 effect(TEMP tmp, TEMP scr, USE_KILL box); |
| 0 | 11404 |
| 11405 ins_cost(300); | |
| 4777 | 11406 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %} |
| 0 | 11407 ins_encode(Fast_Lock(object, box, tmp, scr)); |
| 11408 ins_pipe(pipe_slow); | |
| 11409 %} | |
| 11410 | |
| 11411 instruct cmpFastUnlock(rFlagsReg cr, | |
| 11412 rRegP object, rax_RegP box, rRegP tmp) | |
| 11413 %{ | |
| 11414 match(Set cr (FastUnlock object box)); | |
| 4777 | 11415 effect(TEMP tmp, USE_KILL box); |
| 0 | 11416 |
| 11417 ins_cost(300); | |
| 4777 | 11418 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %} |
| 0 | 11419 ins_encode(Fast_Unlock(object, box, tmp)); |
| 11420 ins_pipe(pipe_slow); | |
| 11421 %} | |
| 11422 | |
| 11423 | |
| 11424 // ============================================================================ | |
| 11425 // Safepoint Instructions | |
| 11426 instruct safePoint_poll(rFlagsReg cr) | |
| 11427 %{ | |
|
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11428 predicate(!Assembler::is_polling_page_far()); |
| 0 | 11429 match(SafePoint); |
| 11430 effect(KILL cr); | |
| 11431 | |
|
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11432 format %{ "testl rax, [rip + #offset_to_poll_page]\t" |
| 0 | 11433 "# Safepoint: poll for GC" %} |
| 11434 ins_cost(125); | |
|
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11435 ins_encode %{ |
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11436 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type); |
|
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11437 __ testl(rax, addr); |
|
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11438 %} |
|
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11439 ins_pipe(ialu_reg_mem); |
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11440 %} |
|
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11441 |
|
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11442 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll) |
|
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11443 %{ |
|
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11444 predicate(Assembler::is_polling_page_far()); |
|
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11445 match(SafePoint poll); |
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11446 effect(KILL cr, USE poll); |
|
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11447 |
|
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11448 format %{ "testl rax, [$poll]\t" |
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11449 "# Safepoint: poll for GC" %} |
|
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11450 ins_cost(125); |
|
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11451 ins_encode %{ |
|
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11452 __ relocate(relocInfo::poll_type); |
|
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11453 __ testl(rax, Address($poll$$Register, 0)); |
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11454 %} |
| 0 | 11455 ins_pipe(ialu_reg_mem); |
| 11456 %} | |
| 11457 | |
| 11458 // ============================================================================ | |
| 11459 // Procedure Call/Return Instructions | |
| 11460 // Call Java Static Instruction | |
| 11461 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 11462 // compute_padding() functions will have to be adjusted. | |
|
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11463 instruct CallStaticJavaDirect(method meth) %{ |
| 0 | 11464 match(CallStaticJava); |
|
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11465 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
| 0 | 11466 effect(USE meth); |
| 11467 | |
| 11468 ins_cost(300); | |
| 11469 format %{ "call,static " %} | |
| 11470 opcode(0xE8); /* E8 cd */ | |
|
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11471 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog); |
| 0 | 11472 ins_pipe(pipe_slow); |
| 11473 ins_alignment(4); | |
| 11474 %} | |
| 11475 | |
|
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11476 // Call Java Static Instruction (method handle version) |
|
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11477 // Note: If this code changes, the corresponding ret_addr_offset() and |
|
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11478 // compute_padding() functions will have to be adjusted. |
| 1567 | 11479 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{ |
|
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11480 match(CallStaticJava); |
|
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11481 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
|
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11482 effect(USE meth); |
|
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11483 // RBP is saved by all callees (for interpreter stack correction). |
|
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11484 // We use it here for a similar purpose, in {preserve,restore}_SP. |
|
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|
11485 |
|
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11486 ins_cost(300); |
|
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11487 format %{ "call,static/MethodHandle " %} |
|
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|
11488 opcode(0xE8); /* E8 cd */ |
|
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11489 ins_encode(clear_avx, preserve_SP, |
|
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11490 Java_Static_Call(meth), |
|
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11491 restore_SP, |
|
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11492 call_epilog); |
|
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11493 ins_pipe(pipe_slow); |
|
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11494 ins_alignment(4); |
|
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11495 %} |
|
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11496 |
| 0 | 11497 // Call Java Dynamic Instruction |
| 11498 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 11499 // compute_padding() functions will have to be adjusted. | |
| 11500 instruct CallDynamicJavaDirect(method meth) | |
| 11501 %{ | |
| 11502 match(CallDynamicJava); | |
| 11503 effect(USE meth); | |
| 11504 | |
| 11505 ins_cost(300); | |
| 11506 format %{ "movq rax, #Universe::non_oop_word()\n\t" | |
| 11507 "call,dynamic " %} | |
|
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11508 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog); |
| 0 | 11509 ins_pipe(pipe_slow); |
| 11510 ins_alignment(4); | |
| 11511 %} | |
| 11512 | |
| 11513 // Call Runtime Instruction | |
| 11514 instruct CallRuntimeDirect(method meth) | |
| 11515 %{ | |
| 11516 match(CallRuntime); | |
| 11517 effect(USE meth); | |
| 11518 | |
| 11519 ins_cost(300); | |
| 11520 format %{ "call,runtime " %} | |
|
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11521 ins_encode(clear_avx, Java_To_Runtime(meth)); |
| 0 | 11522 ins_pipe(pipe_slow); |
| 11523 %} | |
| 11524 | |
| 11525 // Call runtime without safepoint | |
| 11526 instruct CallLeafDirect(method meth) | |
| 11527 %{ | |
| 11528 match(CallLeaf); | |
| 11529 effect(USE meth); | |
| 11530 | |
| 11531 ins_cost(300); | |
| 11532 format %{ "call_leaf,runtime " %} | |
|
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11533 ins_encode(clear_avx, Java_To_Runtime(meth)); |
| 0 | 11534 ins_pipe(pipe_slow); |
| 11535 %} | |
| 11536 | |
| 11537 // Call runtime without safepoint | |
| 11538 instruct CallLeafNoFPDirect(method meth) | |
| 11539 %{ | |
| 11540 match(CallLeafNoFP); | |
| 11541 effect(USE meth); | |
| 11542 | |
| 11543 ins_cost(300); | |
| 11544 format %{ "call_leaf_nofp,runtime " %} | |
| 11545 ins_encode(Java_To_Runtime(meth)); | |
| 11546 ins_pipe(pipe_slow); | |
| 11547 %} | |
| 11548 | |
| 11549 // Return Instruction | |
| 11550 // Remove the return address & jump to it. | |
| 11551 // Notice: We always emit a nop after a ret to make sure there is room | |
| 11552 // for safepoint patching | |
| 11553 instruct Ret() | |
| 11554 %{ | |
| 11555 match(Return); | |
| 11556 | |
| 11557 format %{ "ret" %} | |
| 11558 opcode(0xC3); | |
| 11559 ins_encode(OpcP); | |
| 11560 ins_pipe(pipe_jmp); | |
| 11561 %} | |
| 11562 | |
| 11563 // Tail Call; Jump from runtime stub to Java code. | |
| 11564 // Also known as an 'interprocedural jump'. | |
| 11565 // Target of jump will eventually return to caller. | |
| 11566 // TailJump below removes the return address. | |
| 11567 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop) | |
| 11568 %{ | |
| 11569 match(TailCall jump_target method_oop); | |
| 11570 | |
| 11571 ins_cost(300); | |
| 11572 format %{ "jmp $jump_target\t# rbx holds method oop" %} | |
| 11573 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 11574 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 11575 ins_pipe(pipe_jmp); | |
| 11576 %} | |
| 11577 | |
| 11578 // Tail Jump; remove the return address; jump to target. | |
| 11579 // TailCall above leaves the return address around. | |
| 11580 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop) | |
| 11581 %{ | |
| 11582 match(TailJump jump_target ex_oop); | |
| 11583 | |
| 11584 ins_cost(300); | |
| 11585 format %{ "popq rdx\t# pop return address\n\t" | |
| 11586 "jmp $jump_target" %} | |
| 11587 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 11588 ins_encode(Opcode(0x5a), // popq rdx | |
| 11589 REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 11590 ins_pipe(pipe_jmp); | |
| 11591 %} | |
| 11592 | |
| 11593 // Create exception oop: created by stack-crawling runtime code. | |
| 11594 // Created exception is now available to this handler, and is setup | |
| 11595 // just prior to jumping to this handler. No code emitted. | |
| 11596 instruct CreateException(rax_RegP ex_oop) | |
| 11597 %{ | |
| 11598 match(Set ex_oop (CreateEx)); | |
| 11599 | |
| 11600 size(0); | |
| 11601 // use the following format syntax | |
| 11602 format %{ "# exception oop is in rax; no code emitted" %} | |
| 11603 ins_encode(); | |
| 11604 ins_pipe(empty); | |
| 11605 %} | |
| 11606 | |
| 11607 // Rethrow exception: | |
| 11608 // The exception oop will come in the first argument position. | |
| 11609 // Then JUMP (not call) to the rethrow stub code. | |
| 11610 instruct RethrowException() | |
| 11611 %{ | |
| 11612 match(Rethrow); | |
| 11613 | |
| 11614 // use the following format syntax | |
| 11615 format %{ "jmp rethrow_stub" %} | |
| 11616 ins_encode(enc_rethrow); | |
| 11617 ins_pipe(pipe_jmp); | |
| 11618 %} | |
| 11619 | |
| 11620 | |
| 4950 | 11621 // ============================================================================ |
| 11622 // This name is KNOWN by the ADLC and cannot be changed. | |
| 11623 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 11624 // for this guy. | |
| 11625 instruct tlsLoadP(r15_RegP dst) %{ | |
| 11626 match(Set dst (ThreadLocal)); | |
| 11627 effect(DEF dst); | |
| 11628 | |
| 11629 size(0); | |
| 11630 format %{ "# TLS is in R15" %} | |
| 11631 ins_encode( /*empty encoding*/ ); | |
| 11632 ins_pipe(ialu_reg_reg); | |
| 11633 %} | |
| 11634 | |
| 11635 | |
| 0 | 11636 //----------PEEPHOLE RULES----------------------------------------------------- |
| 11637 // These must follow all instruction definitions as they use the names | |
| 11638 // defined in the instructions definitions. | |
| 11639 // | |
| 605 | 11640 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 11641 // |
| 11642 // peepconstraint %{ | |
| 11643 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 11644 // [, ...] ); | |
| 11645 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 11646 // | |
| 11647 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 11648 // // provide an instruction_number.operand_name for each operand that appears | |
| 11649 // // in the replacement instruction's match rule | |
| 11650 // | |
| 11651 // ---------VM FLAGS--------------------------------------------------------- | |
| 11652 // | |
| 11653 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 11654 // | |
| 11655 // Each peephole rule is given an identifying number starting with zero and | |
| 11656 // increasing by one in the order seen by the parser. An individual peephole | |
| 11657 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 11658 // on the command-line. | |
| 11659 // | |
| 11660 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 11661 // | |
| 11662 // Only match adjacent instructions in same basic block | |
| 11663 // Only equality constraints | |
| 11664 // Only constraints between operands, not (0.dest_reg == RAX_enc) | |
| 11665 // Only one replacement instruction | |
| 11666 // | |
| 11667 // ---------EXAMPLE---------------------------------------------------------- | |
| 11668 // | |
| 11669 // // pertinent parts of existing instructions in architecture description | |
| 11670 // instruct movI(rRegI dst, rRegI src) | |
| 11671 // %{ | |
| 11672 // match(Set dst (CopyI src)); | |
| 11673 // %} | |
| 11674 // | |
| 11675 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 11676 // %{ | |
| 11677 // match(Set dst (AddI dst src)); | |
| 11678 // effect(KILL cr); | |
| 11679 // %} | |
| 11680 // | |
| 11681 // // Change (inc mov) to lea | |
| 11682 // peephole %{ | |
| 11683 // // increment preceeded by register-register move | |
| 11684 // peepmatch ( incI_rReg movI ); | |
| 11685 // // require that the destination register of the increment | |
| 11686 // // match the destination register of the move | |
| 11687 // peepconstraint ( 0.dst == 1.dst ); | |
| 11688 // // construct a replacement instruction that sets | |
| 11689 // // the destination to ( move's source register + one ) | |
| 11690 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) ); | |
| 11691 // %} | |
| 11692 // | |
| 11693 | |
| 11694 // Implementation no longer uses movX instructions since | |
| 11695 // machine-independent system no longer uses CopyX nodes. | |
| 11696 // | |
| 11697 // peephole | |
| 11698 // %{ | |
| 11699 // peepmatch (incI_rReg movI); | |
| 11700 // peepconstraint (0.dst == 1.dst); | |
| 11701 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11702 // %} | |
| 11703 | |
| 11704 // peephole | |
| 11705 // %{ | |
| 11706 // peepmatch (decI_rReg movI); | |
| 11707 // peepconstraint (0.dst == 1.dst); | |
| 11708 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11709 // %} | |
| 11710 | |
| 11711 // peephole | |
| 11712 // %{ | |
| 11713 // peepmatch (addI_rReg_imm movI); | |
| 11714 // peepconstraint (0.dst == 1.dst); | |
| 11715 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11716 // %} | |
| 11717 | |
| 11718 // peephole | |
| 11719 // %{ | |
| 11720 // peepmatch (incL_rReg movL); | |
| 11721 // peepconstraint (0.dst == 1.dst); | |
| 11722 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11723 // %} | |
| 11724 | |
| 11725 // peephole | |
| 11726 // %{ | |
| 11727 // peepmatch (decL_rReg movL); | |
| 11728 // peepconstraint (0.dst == 1.dst); | |
| 11729 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11730 // %} | |
| 11731 | |
| 11732 // peephole | |
| 11733 // %{ | |
| 11734 // peepmatch (addL_rReg_imm movL); | |
| 11735 // peepconstraint (0.dst == 1.dst); | |
| 11736 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11737 // %} | |
| 11738 | |
| 11739 // peephole | |
| 11740 // %{ | |
| 11741 // peepmatch (addP_rReg_imm movP); | |
| 11742 // peepconstraint (0.dst == 1.dst); | |
| 11743 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src)); | |
| 11744 // %} | |
| 11745 | |
| 11746 // // Change load of spilled value to only a spill | |
| 11747 // instruct storeI(memory mem, rRegI src) | |
| 11748 // %{ | |
| 11749 // match(Set mem (StoreI mem src)); | |
| 11750 // %} | |
| 11751 // | |
| 11752 // instruct loadI(rRegI dst, memory mem) | |
| 11753 // %{ | |
| 11754 // match(Set dst (LoadI mem)); | |
| 11755 // %} | |
| 11756 // | |
| 11757 | |
| 11758 peephole | |
| 11759 %{ | |
| 11760 peepmatch (loadI storeI); | |
| 11761 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 11762 peepreplace (storeI(1.mem 1.mem 1.src)); | |
| 11763 %} | |
| 11764 | |
| 11765 peephole | |
| 11766 %{ | |
| 11767 peepmatch (loadL storeL); | |
| 11768 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 11769 peepreplace (storeL(1.mem 1.mem 1.src)); | |
| 11770 %} | |
| 11771 | |
| 11772 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 11773 // These must follow all instruction definitions as they use the names | |
| 11774 // defined in the instructions definitions. |